VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 36627

Last change on this file since 36627 was 36627, checked in by vboxsync, 14 years ago

Fix regression introduced with r70774. Change the RC structure of the mapping cache instead of the R0 one
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File size: 174.9 KB
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1/* $Id: PGMInternal.h 36627 2011-04-08 15:38:47Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef struct PGMPAGE
692{
693 /** The physical address and the Page ID. */
694 RTHCPHYS HCPhysAndPageID;
695 /** Combination of:
696 * - [0-7]: u2HandlerPhysStateY - the physical handler state
697 * (PGM_PAGE_HNDL_PHYS_STATE_*).
698 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
699 * (PGM_PAGE_HNDL_VIRT_STATE_*).
700 * - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
701 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
702 * - [15]: fWrittenToY - flag indicating that a write monitored page was
703 * written to when set.
704 * - [11-13]: 3 unused bits.
705 * @remarks Warning! All accesses to the bits are hardcoded.
706 *
707 * @todo Change this to a union with both bitfields, u8 and u accessors.
708 * That'll help deal with some of the hardcoded accesses.
709 *
710 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
711 * will make it possible to turn some of the 16-bit accesses into
712 * 32-bit ones, which may be efficient (stalls).
713 */
714 RTUINT16U u16MiscY;
715 /** The page state.
716 * Only 3 bits are really needed for this. */
717 uint16_t uStateY : 3;
718 /** The page type (PGMPAGETYPE).
719 * Only 3 bits are really needed for this. */
720 uint16_t uTypeY : 3;
721 /** PTE index for usage tracking (page pool). */
722 uint16_t uPteIdx : 10;
723 /** Usage tracking (page pool). */
724 uint16_t u16TrackingY;
725 /** The number of read locks on this page. */
726 uint8_t cReadLocksY;
727 /** The number of write locks on this page. */
728 uint8_t cWriteLocksY;
729} PGMPAGE;
730AssertCompileSize(PGMPAGE, 16);
731/** Pointer to a physical guest page. */
732typedef PGMPAGE *PPGMPAGE;
733/** Pointer to a const physical guest page. */
734typedef const PGMPAGE *PCPGMPAGE;
735/** Pointer to a physical guest page pointer. */
736typedef PPGMPAGE *PPPGMPAGE;
737
738
739/**
740 * Clears the page structure.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_CLEAR(pPage) \
744 do { \
745 (pPage)->HCPhysAndPageID = 0; \
746 (pPage)->uStateY = 0; \
747 (pPage)->uTypeY = 0; \
748 (pPage)->uPteIdx = 0; \
749 (pPage)->u16MiscY.u = 0; \
750 (pPage)->u16TrackingY = 0; \
751 (pPage)->cReadLocksY = 0; \
752 (pPage)->cWriteLocksY = 0; \
753 } while (0)
754
755/**
756 * Initializes the page structure.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760 do { \
761 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
764 (pPage)->uStateY = (_uState); \
765 (pPage)->uTypeY = (_uType); \
766 (pPage)->uPteIdx = 0; \
767 (pPage)->u16MiscY.u = 0; \
768 (pPage)->u16TrackingY = 0; \
769 (pPage)->cReadLocksY = 0; \
770 (pPage)->cWriteLocksY = 0; \
771 } while (0)
772
773/**
774 * Initializes the page structure of a ZERO page.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 * @param pVM The VM handle (for getting the zero page address).
777 * @param uType The page type (PGMPAGETYPE).
778 */
779#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
780 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
781
782
783/** @name The Page state, PGMPAGE::uStateY.
784 * @{ */
785/** The zero page.
786 * This is a per-VM page that's never ever mapped writable. */
787#define PGM_PAGE_STATE_ZERO 0
788/** A allocated page.
789 * This is a per-VM page allocated from the page pool (or wherever
790 * we get MMIO2 pages from if the type is MMIO2).
791 */
792#define PGM_PAGE_STATE_ALLOCATED 1
793/** A allocated page that's being monitored for writes.
794 * The shadow page table mappings are read-only. When a write occurs, the
795 * fWrittenTo member is set, the page remapped as read-write and the state
796 * moved back to allocated. */
797#define PGM_PAGE_STATE_WRITE_MONITORED 2
798/** The page is shared, aka. copy-on-write.
799 * This is a page that's shared with other VMs. */
800#define PGM_PAGE_STATE_SHARED 3
801/** The page is ballooned, so no longer available for this VM. */
802#define PGM_PAGE_STATE_BALLOONED 4
803/** @} */
804
805
806/**
807 * Gets the page state.
808 * @returns page state (PGM_PAGE_STATE_*).
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
812
813/**
814 * Sets the page state.
815 * @param pPage Pointer to the physical guest page tracking structure.
816 * @param _uState The new page state.
817 */
818#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
819
820
821/**
822 * Gets the host physical address of the guest page.
823 * @returns host physical address (RTHCPHYS).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
827
828/**
829 * Sets the host physical address of the guest page.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 * @param _HCPhys The new host physical address.
832 */
833#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
834 do { \
835 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
836 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
837 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
838 | (SetHCPhysTmp << (28-12)); \
839 } while (0)
840
841/**
842 * Get the Page ID.
843 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
847
848/**
849 * Sets the Page ID.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
853 do { \
854 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
855 | ((_idPage) & UINT32_C(0x0fffffff)); \
856 } while (0)
857
858/**
859 * Get the Chunk ID.
860 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
864
865/**
866 * Get the index of the page within the allocation chunk.
867 * @returns The page index.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
871
872/**
873 * Gets the page type.
874 * @returns The page type.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
878
879/**
880 * Sets the page type.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param _enmType The new page type (PGMPAGETYPE).
883 */
884#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
885
886/**
887 * Gets the page table index
888 * @returns The page table index.
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
892
893/**
894 * Sets the page table index
895 * @param pPage Pointer to the physical guest page tracking structure.
896 * @param iPte New page table index.
897 */
898#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
899
900/**
901 * Checks if the page is marked for MMIO.
902 * @returns true/false.
903 * @param pPage Pointer to the physical guest page tracking structure.
904 */
905#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
906
907/**
908 * Checks if the page is backed by the ZERO page.
909 * @returns true/false.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
913
914/**
915 * Checks if the page is backed by a SHARED page.
916 * @returns true/false.
917 * @param pPage Pointer to the physical guest page tracking structure.
918 */
919#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
920
921/**
922 * Checks if the page is ballooned.
923 * @returns true/false.
924 * @param pPage Pointer to the physical guest page tracking structure.
925 */
926#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
927
928/**
929 * Checks if the page is allocated.
930 * @returns true/false.
931 * @param pPage Pointer to the physical guest page tracking structure.
932 */
933#define PGM_PAGE_IS_ALLOCATED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ALLOCATED )
934
935/**
936 * Marks the page as written to (for GMM change monitoring).
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
940
941/**
942 * Clears the written-to indicator.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
946
947/**
948 * Checks if the page was marked as written-to.
949 * @returns true/false.
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
953
954/**
955 * Marks the page as dirty for FTM
956 * @param pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x04); } while (0)
959
960/**
961 * Clears the FTM dirty indicator
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
965
966/**
967 * Checks if the page was marked as dirty for FTM
968 * @returns true/false.
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
972
973
974/** @name PT usage values (PGMPAGE::u2PDEType).
975 *
976 * @{ */
977/** Either as a PT or PDE. */
978#define PGM_PAGE_PDE_TYPE_DONTCARE 0
979/** Must use a page table to map the range. */
980#define PGM_PAGE_PDE_TYPE_PT 1
981/** Can use a page directory entry to map the continuous range. */
982#define PGM_PAGE_PDE_TYPE_PDE 2
983/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
984#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
985/** @} */
986
987/**
988 * Set the PDE type of the page
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param uType PGM_PAGE_PDE_TYPE_*
991 */
992#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
993 do { \
994 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
995 | (((uType) & UINT8_C(0x03)) << 5); \
996 } while (0)
997
998/**
999 * Checks if the page was marked being part of a large page
1000 * @returns true/false.
1001 * @param pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1004
1005/** Enabled optimized access handler tests.
1006 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1007 * layout. When enabled, the compiler should normally generate more compact
1008 * code.
1009 */
1010#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1011
1012/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1013 *
1014 * @remarks The values are assigned in order of priority, so we can calculate
1015 * the correct state for a page with different handlers installed.
1016 * @{ */
1017/** No handler installed. */
1018#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1019/** Monitoring is temporarily disabled. */
1020#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1021/** Write access is monitored. */
1022#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1023/** All access is monitored. */
1024#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1025/** @} */
1026
1027/**
1028 * Gets the physical access handler state of a page.
1029 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1033 ( (pPage)->u16MiscY.au8[0] )
1034
1035/**
1036 * Sets the physical access handler state of a page.
1037 * @param pPage Pointer to the physical guest page tracking structure.
1038 * @param _uState The new state value.
1039 */
1040#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1041 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1042
1043/**
1044 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1045 * @returns true/false
1046 * @param pPage Pointer to the physical guest page tracking structure.
1047 */
1048#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1049 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1050
1051/**
1052 * Checks if the page has any active physical access handlers.
1053 * @returns true/false
1054 * @param pPage Pointer to the physical guest page tracking structure.
1055 */
1056#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1057 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1058
1059
1060/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1061 *
1062 * @remarks The values are assigned in order of priority, so we can calculate
1063 * the correct state for a page with different handlers installed.
1064 * @{ */
1065/** No handler installed. */
1066#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1067/* 1 is reserved so the lineup is identical with the physical ones. */
1068/** Write access is monitored. */
1069#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1070/** All access is monitored. */
1071#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1072/** @} */
1073
1074/**
1075 * Gets the virtual access handler state of a page.
1076 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1080
1081/**
1082 * Sets the virtual access handler state of a page.
1083 * @param pPage Pointer to the physical guest page tracking structure.
1084 * @param _uState The new state value.
1085 */
1086#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1087 do { \
1088 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1089 | ((_uState) & UINT8_C(0x03)); \
1090 } while (0)
1091
1092/**
1093 * Checks if the page has any virtual access handlers.
1094 * @returns true/false
1095 * @param pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1098 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1099
1100/**
1101 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1102 * virtual handlers.
1103 * @returns true/false
1104 * @param pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1107 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1108
1109
1110/**
1111 * Checks if the page has any access handlers, including temporarily disabled ones.
1112 * @returns true/false
1113 * @param pPage Pointer to the physical guest page tracking structure.
1114 */
1115#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1116# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1117 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1118#else
1119# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1120 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1121 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1122#endif
1123
1124/**
1125 * Checks if the page has any active access handlers.
1126 * @returns true/false
1127 * @param pPage Pointer to the physical guest page tracking structure.
1128 */
1129#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1130# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1131 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1132#else
1133# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1134 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1135 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1136#endif
1137
1138/**
1139 * Checks if the page has any active access handlers catching all accesses.
1140 * @returns true/false
1141 * @param pPage Pointer to the physical guest page tracking structure.
1142 */
1143#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1144# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1145 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1146 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1147#else
1148# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1149 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1150 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1151#endif
1152
1153
1154/** @def PGM_PAGE_GET_TRACKING
1155 * Gets the packed shadow page pool tracking data associated with a guest page.
1156 * @returns uint16_t containing the data.
1157 * @param pPage Pointer to the physical guest page tracking structure.
1158 */
1159#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1160
1161/** @def PGM_PAGE_SET_TRACKING
1162 * Sets the packed shadow page pool tracking data associated with a guest page.
1163 * @param pPage Pointer to the physical guest page tracking structure.
1164 * @param u16TrackingData The tracking data to store.
1165 */
1166#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1167 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1168
1169/** @def PGM_PAGE_GET_TD_CREFS
1170 * Gets the @a cRefs tracking data member.
1171 * @returns cRefs.
1172 * @param pPage Pointer to the physical guest page tracking structure.
1173 */
1174#define PGM_PAGE_GET_TD_CREFS(pPage) \
1175 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1176
1177/** @def PGM_PAGE_GET_TD_IDX
1178 * Gets the @a idx tracking data member.
1179 * @returns idx.
1180 * @param pPage Pointer to the physical guest page tracking structure.
1181 */
1182#define PGM_PAGE_GET_TD_IDX(pPage) \
1183 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1184
1185
1186/** Max number of locks on a page. */
1187#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1188
1189/** Get the read lock count.
1190 * @returns count.
1191 * @param pPage Pointer to the physical guest page tracking structure.
1192 */
1193#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1194
1195/** Get the write lock count.
1196 * @returns count.
1197 * @param pPage Pointer to the physical guest page tracking structure.
1198 */
1199#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1200
1201/** Decrement the read lock counter.
1202 * @param pPage Pointer to the physical guest page tracking structure.
1203 */
1204#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1205
1206/** Decrement the write lock counter.
1207 * @param pPage Pointer to the physical guest page tracking structure.
1208 */
1209#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1210
1211/** Increment the read lock counter.
1212 * @param pPage Pointer to the physical guest page tracking structure.
1213 */
1214#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1215
1216/** Increment the write lock counter.
1217 * @param pPage Pointer to the physical guest page tracking structure.
1218 */
1219#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1220
1221
1222#if 0
1223/** Enables sanity checking of write monitoring using CRC-32. */
1224# define PGMLIVESAVERAMPAGE_WITH_CRC32
1225#endif
1226
1227/**
1228 * Per page live save tracking data.
1229 */
1230typedef struct PGMLIVESAVERAMPAGE
1231{
1232 /** Number of times it has been dirtied. */
1233 uint32_t cDirtied : 24;
1234 /** Whether it is currently dirty. */
1235 uint32_t fDirty : 1;
1236 /** Ignore the page.
1237 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1238 * deal with these after pausing the VM and DevPCI have said it bit about
1239 * remappings. */
1240 uint32_t fIgnore : 1;
1241 /** Was a ZERO page last time around. */
1242 uint32_t fZero : 1;
1243 /** Was a SHARED page last time around. */
1244 uint32_t fShared : 1;
1245 /** Whether the page is/was write monitored in a previous pass. */
1246 uint32_t fWriteMonitored : 1;
1247 /** Whether the page is/was write monitored earlier in this pass. */
1248 uint32_t fWriteMonitoredJustNow : 1;
1249 /** Bits reserved for future use. */
1250 uint32_t u2Reserved : 2;
1251#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1252 /** CRC-32 for the page. This is for internal consistency checks. */
1253 uint32_t u32Crc;
1254#endif
1255} PGMLIVESAVERAMPAGE;
1256#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1258#else
1259AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1260#endif
1261/** Pointer to the per page live save tracking data. */
1262typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1263
1264/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1265#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1266
1267
1268/**
1269 * Ram range for GC Phys to HC Phys conversion.
1270 *
1271 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1272 * conversions too, but we'll let MM handle that for now.
1273 *
1274 * This structure is used by linked lists in both GC and HC.
1275 */
1276typedef struct PGMRAMRANGE
1277{
1278 /** Start of the range. Page aligned. */
1279 RTGCPHYS GCPhys;
1280 /** Size of the range. (Page aligned of course). */
1281 RTGCPHYS cb;
1282 /** Pointer to the next RAM range - for R3. */
1283 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1284 /** Pointer to the next RAM range - for R0. */
1285 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1286 /** Pointer to the next RAM range - for RC. */
1287 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1288 /** PGM_RAM_RANGE_FLAGS_* flags. */
1289 uint32_t fFlags;
1290 /** Last address in the range (inclusive). Page aligned (-1). */
1291 RTGCPHYS GCPhysLast;
1292 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1293 R3PTRTYPE(void *) pvR3;
1294 /** Live save per page tracking data. */
1295 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1296 /** The range description. */
1297 R3PTRTYPE(const char *) pszDesc;
1298 /** Pointer to self - R0 pointer. */
1299 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1300 /** Pointer to self - RC pointer. */
1301 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1302 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1303 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1304 /** Array of physical guest page tracking structures. */
1305 PGMPAGE aPages[1];
1306} PGMRAMRANGE;
1307/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1308typedef PGMRAMRANGE *PPGMRAMRANGE;
1309
1310/** @name PGMRAMRANGE::fFlags
1311 * @{ */
1312/** The RAM range is floating around as an independent guest mapping. */
1313#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1314/** Ad hoc RAM range for an ROM mapping. */
1315#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1316/** Ad hoc RAM range for an MMIO mapping. */
1317#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1318/** Ad hoc RAM range for an MMIO2 mapping. */
1319#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1320/** @} */
1321
1322/** Tests if a RAM range is an ad hoc one or not.
1323 * @returns true/false.
1324 * @param pRam The RAM range.
1325 */
1326#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1327 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1328
1329
1330/**
1331 * Per page tracking structure for ROM image.
1332 *
1333 * A ROM image may have a shadow page, in which case we may have two pages
1334 * backing it. This structure contains the PGMPAGE for both while
1335 * PGMRAMRANGE have a copy of the active one. It is important that these
1336 * aren't out of sync in any regard other than page pool tracking data.
1337 */
1338typedef struct PGMROMPAGE
1339{
1340 /** The page structure for the virgin ROM page. */
1341 PGMPAGE Virgin;
1342 /** The page structure for the shadow RAM page. */
1343 PGMPAGE Shadow;
1344 /** The current protection setting. */
1345 PGMROMPROT enmProt;
1346 /** Live save status information. Makes use of unused alignment space. */
1347 struct
1348 {
1349 /** The previous protection value. */
1350 uint8_t u8Prot;
1351 /** Written to flag set by the handler. */
1352 bool fWrittenTo;
1353 /** Whether the shadow page is dirty or not. */
1354 bool fDirty;
1355 /** Whether it was dirtied in the recently. */
1356 bool fDirtiedRecently;
1357 } LiveSave;
1358} PGMROMPAGE;
1359AssertCompileSizeAlignment(PGMROMPAGE, 8);
1360/** Pointer to a ROM page tracking structure. */
1361typedef PGMROMPAGE *PPGMROMPAGE;
1362
1363
1364/**
1365 * A registered ROM image.
1366 *
1367 * This is needed to keep track of ROM image since they generally intrude
1368 * into a PGMRAMRANGE. It also keeps track of additional info like the
1369 * two page sets (read-only virgin and read-write shadow), the current
1370 * state of each page.
1371 *
1372 * Because access handlers cannot easily be executed in a different
1373 * context, the ROM ranges needs to be accessible and in all contexts.
1374 */
1375typedef struct PGMROMRANGE
1376{
1377 /** Pointer to the next range - R3. */
1378 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1379 /** Pointer to the next range - R0. */
1380 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1381 /** Pointer to the next range - RC. */
1382 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1383 /** Pointer alignment */
1384 RTRCPTR RCPtrAlignment;
1385 /** Address of the range. */
1386 RTGCPHYS GCPhys;
1387 /** Address of the last byte in the range. */
1388 RTGCPHYS GCPhysLast;
1389 /** Size of the range. */
1390 RTGCPHYS cb;
1391 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1392 uint32_t fFlags;
1393 /** The saved state range ID. */
1394 uint8_t idSavedState;
1395 /** Alignment padding. */
1396 uint8_t au8Alignment[3];
1397 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1398 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1399 /** The size bits pvOriginal points to. */
1400 uint32_t cbOriginal;
1401 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1402 * This is used for strictness checks. */
1403 R3PTRTYPE(const void *) pvOriginal;
1404 /** The ROM description. */
1405 R3PTRTYPE(const char *) pszDesc;
1406 /** The per page tracking structures. */
1407 PGMROMPAGE aPages[1];
1408} PGMROMRANGE;
1409/** Pointer to a ROM range. */
1410typedef PGMROMRANGE *PPGMROMRANGE;
1411
1412
1413/**
1414 * Live save per page data for an MMIO2 page.
1415 *
1416 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1417 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1418 * CRC-32 for detecting changes as well as special handling of zero pages. This
1419 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1420 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1421 * because of speed (2.5x and 6x slower).)
1422 *
1423 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1424 * save but normally is disabled. Since we can write monitor guest
1425 * accesses on our own, we only need this for host accesses. Shouldn't be
1426 * too difficult for DevVGA, VMMDev might be doable, the planned
1427 * networking fun will be fun since it involves ring-0.
1428 */
1429typedef struct PGMLIVESAVEMMIO2PAGE
1430{
1431 /** Set if the page is considered dirty. */
1432 bool fDirty;
1433 /** The number of scans this page has remained unchanged for.
1434 * Only updated for dirty pages. */
1435 uint8_t cUnchangedScans;
1436 /** Whether this page was zero at the last scan. */
1437 bool fZero;
1438 /** Alignment padding. */
1439 bool fReserved;
1440 /** CRC-32 for the first half of the page.
1441 * This is used together with u32CrcH2 to quickly detect changes in the page
1442 * during the non-final passes. */
1443 uint32_t u32CrcH1;
1444 /** CRC-32 for the second half of the page. */
1445 uint32_t u32CrcH2;
1446 /** SHA-1 for the saved page.
1447 * This is used in the final pass to skip pages without changes. */
1448 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1449} PGMLIVESAVEMMIO2PAGE;
1450/** Pointer to a live save status data for an MMIO2 page. */
1451typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1452
1453/**
1454 * A registered MMIO2 (= Device RAM) range.
1455 *
1456 * There are a few reason why we need to keep track of these
1457 * registrations. One of them is the deregistration & cleanup stuff,
1458 * while another is that the PGMRAMRANGE associated with such a region may
1459 * have to be removed from the ram range list.
1460 *
1461 * Overlapping with a RAM range has to be 100% or none at all. The pages
1462 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1463 * will be raised if a partial overlap or an overlap of ROM pages is
1464 * encountered. On an overlap we will free all the existing RAM pages and
1465 * put in the ram range pages instead.
1466 */
1467typedef struct PGMMMIO2RANGE
1468{
1469 /** The owner of the range. (a device) */
1470 PPDMDEVINSR3 pDevInsR3;
1471 /** Pointer to the ring-3 mapping of the allocation. */
1472 RTR3PTR pvR3;
1473 /** Pointer to the next range - R3. */
1474 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1475 /** Whether it's mapped or not. */
1476 bool fMapped;
1477 /** Whether it's overlapping or not. */
1478 bool fOverlapping;
1479 /** The PCI region number.
1480 * @remarks This ASSUMES that nobody will ever really need to have multiple
1481 * PCI devices with matching MMIO region numbers on a single device. */
1482 uint8_t iRegion;
1483 /** The saved state range ID. */
1484 uint8_t idSavedState;
1485 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1486 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1487 /** Live save per page tracking data. */
1488 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1489 /** The associated RAM range. */
1490 PGMRAMRANGE RamRange;
1491} PGMMMIO2RANGE;
1492/** Pointer to a MMIO2 range. */
1493typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1494
1495
1496
1497
1498/**
1499 * PGMPhysRead/Write cache entry
1500 */
1501typedef struct PGMPHYSCACHEENTRY
1502{
1503 /** R3 pointer to physical page. */
1504 R3PTRTYPE(uint8_t *) pbR3;
1505 /** GC Physical address for cache entry */
1506 RTGCPHYS GCPhys;
1507#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1508 RTGCPHYS u32Padding0; /**< alignment padding. */
1509#endif
1510} PGMPHYSCACHEENTRY;
1511
1512/**
1513 * PGMPhysRead/Write cache to reduce REM memory access overhead
1514 */
1515typedef struct PGMPHYSCACHE
1516{
1517 /** Bitmap of valid cache entries */
1518 uint64_t aEntries;
1519 /** Cache entries */
1520 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1521} PGMPHYSCACHE;
1522
1523
1524/** Pointer to an allocation chunk ring-3 mapping. */
1525typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1526/** Pointer to an allocation chunk ring-3 mapping pointer. */
1527typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1528
1529/**
1530 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1531 *
1532 * The primary tree (Core) uses the chunk id as key.
1533 */
1534typedef struct PGMCHUNKR3MAP
1535{
1536 /** The key is the chunk id. */
1537 AVLU32NODECORE Core;
1538 /** The current age thingy. */
1539 uint32_t iAge;
1540 /** The current reference count. */
1541 uint32_t volatile cRefs;
1542 /** The current permanent reference count. */
1543 uint32_t volatile cPermRefs;
1544 /** The mapping address. */
1545 void *pv;
1546} PGMCHUNKR3MAP;
1547
1548/**
1549 * Allocation chunk ring-3 mapping TLB entry.
1550 */
1551typedef struct PGMCHUNKR3MAPTLBE
1552{
1553 /** The chunk id. */
1554 uint32_t volatile idChunk;
1555#if HC_ARCH_BITS == 64
1556 uint32_t u32Padding; /**< alignment padding. */
1557#endif
1558 /** The chunk map. */
1559#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1560 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1561#else
1562 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1563#endif
1564} PGMCHUNKR3MAPTLBE;
1565/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1566typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1567
1568/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1569 * @remark Must be a power of two value. */
1570#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1571
1572/**
1573 * Allocation chunk ring-3 mapping TLB.
1574 *
1575 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1576 * At first glance this might look kinda odd since AVL trees are
1577 * supposed to give the most optimal lookup times of all trees
1578 * due to their balancing. However, take a tree with 1023 nodes
1579 * in it, that's 10 levels, meaning that most searches has to go
1580 * down 9 levels before they find what they want. This isn't fast
1581 * compared to a TLB hit. There is the factor of cache misses,
1582 * and of course the problem with trees and branch prediction.
1583 * This is why we use TLBs in front of most of the trees.
1584 *
1585 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1586 * difficult when we switch to the new inlined AVL trees (from kStuff).
1587 */
1588typedef struct PGMCHUNKR3MAPTLB
1589{
1590 /** The TLB entries. */
1591 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1592} PGMCHUNKR3MAPTLB;
1593
1594/**
1595 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1596 * @returns Chunk TLB index.
1597 * @param idChunk The Chunk ID.
1598 */
1599#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1600
1601
1602/**
1603 * Ring-3 guest page mapping TLB entry.
1604 * @remarks used in ring-0 as well at the moment.
1605 */
1606typedef struct PGMPAGER3MAPTLBE
1607{
1608 /** Address of the page. */
1609 RTGCPHYS volatile GCPhys;
1610 /** The guest page. */
1611#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1612 R3PTRTYPE(PPGMPAGE) volatile pPage;
1613#else
1614 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1615#endif
1616 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1617#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1618 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1619#else
1620 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1621#endif
1622 /** The address */
1623#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1624 R3PTRTYPE(void *) volatile pv;
1625#else
1626 R3R0PTRTYPE(void *) volatile pv;
1627#endif
1628#if HC_ARCH_BITS == 32
1629 uint32_t u32Padding; /**< alignment padding. */
1630#endif
1631} PGMPAGER3MAPTLBE;
1632/** Pointer to an entry in the HC physical TLB. */
1633typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1634
1635
1636/** The number of entries in the ring-3 guest page mapping TLB.
1637 * @remarks The value must be a power of two. */
1638#define PGM_PAGER3MAPTLB_ENTRIES 256
1639
1640/**
1641 * Ring-3 guest page mapping TLB.
1642 * @remarks used in ring-0 as well at the moment.
1643 */
1644typedef struct PGMPAGER3MAPTLB
1645{
1646 /** The TLB entries. */
1647 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1648} PGMPAGER3MAPTLB;
1649/** Pointer to the ring-3 guest page mapping TLB. */
1650typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1651
1652/**
1653 * Calculates the index of the TLB entry for the specified guest page.
1654 * @returns Physical TLB index.
1655 * @param GCPhys The guest physical address.
1656 */
1657#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1658
1659
1660/**
1661 * Raw-mode context dynamic mapping cache entry.
1662 *
1663 * Because of raw-mode context being reloctable and all relocations are applied
1664 * in ring-3, this has to be defined here and be RC specific.
1665 *
1666 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1667 */
1668typedef struct PGMRCDYNMAPENTRY
1669{
1670 /** The physical address of the currently mapped page.
1671 * This is duplicate for three reasons: cache locality, cache policy of the PT
1672 * mappings and sanity checks. */
1673 RTHCPHYS HCPhys;
1674 /** Pointer to the page. */
1675 RTRCPTR pvPage;
1676 /** The number of references. */
1677 int32_t volatile cRefs;
1678 /** PTE pointer union. */
1679 struct PGMRCDYNMAPENTRY_PPTE
1680 {
1681 /** PTE pointer, 32-bit legacy version. */
1682 RCPTRTYPE(PX86PTE) pLegacy;
1683 /** PTE pointer, PAE version. */
1684 RCPTRTYPE(PX86PTEPAE) pPae;
1685 } uPte;
1686 /** Alignment padding. */
1687 RTRCPTR RCPtrAlignment;
1688} PGMRCDYNMAPENTRY;
1689/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1690typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1691
1692
1693/**
1694 * Dynamic mapping cache for the raw-mode context.
1695 *
1696 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1697 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1698 * so that we can perform relocations from PGMR3Relocate. This has the
1699 * consequence that we must have separate ring-0 and raw-mode context versions
1700 * of this struct even if they share the basic elements.
1701 *
1702 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1703 */
1704typedef struct PGMRCDYNMAP
1705{
1706 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1707 uint32_t u32Magic;
1708 /** Array for tracking and managing the pages. */
1709 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1710 /** The cache size given as a number of pages. */
1711 uint32_t cPages;
1712 /** The current load.
1713 * This does not include guard pages. */
1714 uint32_t cLoad;
1715 /** The max load ever.
1716 * This is maintained to get trigger adding of more mapping space. */
1717 uint32_t cMaxLoad;
1718 /** The number of guard pages. */
1719 uint32_t cGuardPages;
1720 /** The number of users (protected by hInitLock). */
1721 uint32_t cUsers;
1722} PGMRCDYNMAP;
1723/** Pointer to the dynamic cache for the raw-mode context. */
1724typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1725
1726
1727/**
1728 * Mapping cache usage set entry.
1729 *
1730 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1731 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1732 * cache. If it's extended to include ring-3, well, then something
1733 * will have be changed here...
1734 */
1735typedef struct PGMMAPSETENTRY
1736{
1737 /** Pointer to the page. */
1738#ifndef IN_RC
1739 RTR0PTR pvPage;
1740#else
1741 RTRCPTR pvPage;
1742# if HC_ARCH_BITS == 64
1743 uint32_t u32Alignment2;
1744# endif
1745#endif
1746 /** The mapping cache index. */
1747 uint16_t iPage;
1748 /** The number of references.
1749 * The max is UINT16_MAX - 1. */
1750 uint16_t cRefs;
1751 /** The number inlined references.
1752 * The max is UINT16_MAX - 1. */
1753 uint16_t cInlinedRefs;
1754 /** Unreferences. */
1755 uint16_t cUnrefs;
1756
1757#if HC_ARCH_BITS == 32
1758 uint32_t u32Alignment1;
1759#endif
1760 /** The physical address for this entry. */
1761 RTHCPHYS HCPhys;
1762} PGMMAPSETENTRY;
1763AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1764AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1765/** Pointer to a mapping cache usage set entry. */
1766typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1767
1768/**
1769 * Mapping cache usage set.
1770 *
1771 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1772 * done during exits / traps. The set is
1773 */
1774typedef struct PGMMAPSET
1775{
1776 /** The number of occupied entries.
1777 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1778 * dynamic mappings. */
1779 uint32_t cEntries;
1780 /** The start of the current subset.
1781 * This is UINT32_MAX if no subset is currently open. */
1782 uint32_t iSubset;
1783 /** The index of the current CPU, only valid if the set is open. */
1784 int32_t iCpu;
1785 uint32_t alignment;
1786 /** The entries. */
1787 PGMMAPSETENTRY aEntries[64];
1788 /** HCPhys -> iEntry fast lookup table.
1789 * Use PGMMAPSET_HASH for hashing.
1790 * The entries may or may not be valid, check against cEntries. */
1791 uint8_t aiHashTable[128];
1792} PGMMAPSET;
1793AssertCompileSizeAlignment(PGMMAPSET, 8);
1794/** Pointer to the mapping cache set. */
1795typedef PGMMAPSET *PPGMMAPSET;
1796
1797/** PGMMAPSET::cEntries value for a closed set. */
1798#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1799
1800/** Hash function for aiHashTable. */
1801#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1802
1803
1804/** @name Context neutral page mapper TLB.
1805 *
1806 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1807 * code is writting in a kind of context neutral way. Time will show whether
1808 * this actually makes sense or not...
1809 *
1810 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1811 * context ends up using a global mapping cache on some platforms
1812 * (darwin).
1813 *
1814 * @{ */
1815/** @typedef PPGMPAGEMAPTLB
1816 * The page mapper TLB pointer type for the current context. */
1817/** @typedef PPGMPAGEMAPTLB
1818 * The page mapper TLB entry pointer type for the current context. */
1819/** @typedef PPGMPAGEMAPTLB
1820 * The page mapper TLB entry pointer pointer type for the current context. */
1821/** @def PGM_PAGEMAPTLB_ENTRIES
1822 * The number of TLB entries in the page mapper TLB for the current context. */
1823/** @def PGM_PAGEMAPTLB_IDX
1824 * Calculate the TLB index for a guest physical address.
1825 * @returns The TLB index.
1826 * @param GCPhys The guest physical address. */
1827/** @typedef PPGMPAGEMAP
1828 * Pointer to a page mapper unit for current context. */
1829/** @typedef PPPGMPAGEMAP
1830 * Pointer to a page mapper unit pointer for current context. */
1831#ifdef IN_RC
1832// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1833// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1834// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1835# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1836# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1837 typedef void * PPGMPAGEMAP;
1838 typedef void ** PPPGMPAGEMAP;
1839//#elif IN_RING0
1840// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1841// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1842// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1843//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1844//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1845// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1846// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1847#else
1848 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1849 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1850 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1851# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1852# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1853 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1854 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1855#endif
1856/** @} */
1857
1858
1859/** @name PGM Pool Indexes.
1860 * Aka. the unique shadow page identifier.
1861 * @{ */
1862/** NIL page pool IDX. */
1863#define NIL_PGMPOOL_IDX 0
1864/** The first normal index. */
1865#define PGMPOOL_IDX_FIRST_SPECIAL 1
1866/** Page directory (32-bit root). */
1867#define PGMPOOL_IDX_PD 1
1868/** Page Directory Pointer Table (PAE root). */
1869#define PGMPOOL_IDX_PDPT 2
1870/** AMD64 CR3 level index.*/
1871#define PGMPOOL_IDX_AMD64_CR3 3
1872/** Nested paging root.*/
1873#define PGMPOOL_IDX_NESTED_ROOT 4
1874/** The first normal index. */
1875#define PGMPOOL_IDX_FIRST 5
1876/** The last valid index. (inclusive, 14 bits) */
1877#define PGMPOOL_IDX_LAST 0x3fff
1878/** @} */
1879
1880/** The NIL index for the parent chain. */
1881#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1882#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1883
1884/**
1885 * Node in the chain linking a shadowed page to it's parent (user).
1886 */
1887#pragma pack(1)
1888typedef struct PGMPOOLUSER
1889{
1890 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1891 uint16_t iNext;
1892 /** The user page index. */
1893 uint16_t iUser;
1894 /** Index into the user table. */
1895 uint32_t iUserTable;
1896} PGMPOOLUSER, *PPGMPOOLUSER;
1897typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1898#pragma pack()
1899
1900
1901/** The NIL index for the phys ext chain. */
1902#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1903/** The NIL pte index for a phys ext chain slot. */
1904#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1905
1906/**
1907 * Node in the chain of physical cross reference extents.
1908 * @todo Calling this an 'extent' is not quite right, find a better name.
1909 * @todo find out the optimal size of the aidx array
1910 */
1911#pragma pack(1)
1912typedef struct PGMPOOLPHYSEXT
1913{
1914 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1915 uint16_t iNext;
1916 /** Alignment. */
1917 uint16_t u16Align;
1918 /** The user page index. */
1919 uint16_t aidx[3];
1920 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1921 uint16_t apte[3];
1922} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1923typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1924#pragma pack()
1925
1926
1927/**
1928 * The kind of page that's being shadowed.
1929 */
1930typedef enum PGMPOOLKIND
1931{
1932 /** The virtual invalid 0 entry. */
1933 PGMPOOLKIND_INVALID = 0,
1934 /** The entry is free (=unused). */
1935 PGMPOOLKIND_FREE,
1936
1937 /** Shw: 32-bit page table; Gst: no paging */
1938 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1939 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1940 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1941 /** Shw: 32-bit page table; Gst: 4MB page. */
1942 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1943 /** Shw: PAE page table; Gst: no paging */
1944 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1945 /** Shw: PAE page table; Gst: 32-bit page table. */
1946 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1947 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1948 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1949 /** Shw: PAE page table; Gst: PAE page table. */
1950 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1951 /** Shw: PAE page table; Gst: 2MB page. */
1952 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1953
1954 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1955 PGMPOOLKIND_32BIT_PD,
1956 /** Shw: 32-bit page directory. Gst: no paging. */
1957 PGMPOOLKIND_32BIT_PD_PHYS,
1958 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1959 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1960 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1961 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1962 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1963 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1964 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1965 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1966 /** Shw: PAE page directory; Gst: PAE page directory. */
1967 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1968 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1969 PGMPOOLKIND_PAE_PD_PHYS,
1970
1971 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1972 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1973 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1974 PGMPOOLKIND_PAE_PDPT,
1975 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1976 PGMPOOLKIND_PAE_PDPT_PHYS,
1977
1978 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1979 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1980 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1981 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1982 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1983 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1984 /** Shw: 64-bit page directory table; Gst: no paging */
1985 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1986
1987 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1988 PGMPOOLKIND_64BIT_PML4,
1989
1990 /** Shw: EPT page directory pointer table; Gst: no paging */
1991 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1992 /** Shw: EPT page directory table; Gst: no paging */
1993 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1994 /** Shw: EPT page table; Gst: no paging */
1995 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1996
1997 /** Shw: Root Nested paging table. */
1998 PGMPOOLKIND_ROOT_NESTED,
1999
2000 /** The last valid entry. */
2001 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2002} PGMPOOLKIND;
2003
2004/**
2005 * The access attributes of the page; only applies to big pages.
2006 */
2007typedef enum
2008{
2009 PGMPOOLACCESS_DONTCARE = 0,
2010 PGMPOOLACCESS_USER_RW,
2011 PGMPOOLACCESS_USER_R,
2012 PGMPOOLACCESS_USER_RW_NX,
2013 PGMPOOLACCESS_USER_R_NX,
2014 PGMPOOLACCESS_SUPERVISOR_RW,
2015 PGMPOOLACCESS_SUPERVISOR_R,
2016 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2017 PGMPOOLACCESS_SUPERVISOR_R_NX
2018} PGMPOOLACCESS;
2019
2020/**
2021 * The tracking data for a page in the pool.
2022 */
2023typedef struct PGMPOOLPAGE
2024{
2025 /** AVL node code with the (R3) physical address of this page. */
2026 AVLOHCPHYSNODECORE Core;
2027 /** Pointer to the R3 mapping of the page. */
2028#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2029 R3PTRTYPE(void *) pvPageR3;
2030#else
2031 R3R0PTRTYPE(void *) pvPageR3;
2032#endif
2033 /** The guest physical address. */
2034#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2035 uint32_t Alignment0;
2036#endif
2037 RTGCPHYS GCPhys;
2038
2039 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2040 RTGCPTR pvLastAccessHandlerRip;
2041 RTGCPTR pvLastAccessHandlerFault;
2042 uint64_t cLastAccessHandlerCount;
2043
2044 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2045 uint8_t enmKind;
2046 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2047 uint8_t enmAccess;
2048 /** The index of this page. */
2049 uint16_t idx;
2050 /** The next entry in the list this page currently resides in.
2051 * It's either in the free list or in the GCPhys hash. */
2052 uint16_t iNext;
2053 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2054 uint16_t iUserHead;
2055 /** The number of present entries. */
2056 uint16_t cPresent;
2057 /** The first entry in the table which is present. */
2058 uint16_t iFirstPresent;
2059 /** The number of modifications to the monitored page. */
2060 uint16_t cModifications;
2061 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2062 uint16_t iModifiedNext;
2063 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2064 uint16_t iModifiedPrev;
2065 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2066 uint16_t iMonitoredNext;
2067 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2068 uint16_t iMonitoredPrev;
2069 /** The next page in the age list. */
2070 uint16_t iAgeNext;
2071 /** The previous page in the age list. */
2072 uint16_t iAgePrev;
2073 /** Used to indicate that the page is zeroed. */
2074 bool fZeroed;
2075 /** Used to indicate that a PT has non-global entries. */
2076 bool fSeenNonGlobal;
2077 /** Used to indicate that we're monitoring writes to the guest page. */
2078 bool fMonitored;
2079 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2080 * (All pages are in the age list.) */
2081 bool fCached;
2082 /** This is used by the R3 access handlers when invoked by an async thread.
2083 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2084 bool volatile fReusedFlushPending;
2085 /** Used to mark the page as dirty (write monitoring is temporarily
2086 * off). */
2087 bool fDirty;
2088
2089 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2090 uint32_t cLocked;
2091 uint32_t idxDirty;
2092 RTGCPTR pvDirtyFault;
2093} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2094/** Pointer to a const pool page. */
2095typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2096
2097
2098/** The hash table size. */
2099# define PGMPOOL_HASH_SIZE 0x40
2100/** The hash function. */
2101# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2102
2103
2104/**
2105 * The shadow page pool instance data.
2106 *
2107 * It's all one big allocation made at init time, except for the
2108 * pages that is. The user nodes follows immediately after the
2109 * page structures.
2110 */
2111typedef struct PGMPOOL
2112{
2113 /** The VM handle - R3 Ptr. */
2114 PVMR3 pVMR3;
2115 /** The VM handle - R0 Ptr. */
2116 PVMR0 pVMR0;
2117 /** The VM handle - RC Ptr. */
2118 PVMRC pVMRC;
2119 /** The max pool size. This includes the special IDs. */
2120 uint16_t cMaxPages;
2121 /** The current pool size. */
2122 uint16_t cCurPages;
2123 /** The head of the free page list. */
2124 uint16_t iFreeHead;
2125 /* Padding. */
2126 uint16_t u16Padding;
2127 /** Head of the chain of free user nodes. */
2128 uint16_t iUserFreeHead;
2129 /** The number of user nodes we've allocated. */
2130 uint16_t cMaxUsers;
2131 /** The number of present page table entries in the entire pool. */
2132 uint32_t cPresent;
2133 /** Pointer to the array of user nodes - RC pointer. */
2134 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2135 /** Pointer to the array of user nodes - R3 pointer. */
2136 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2137 /** Pointer to the array of user nodes - R0 pointer. */
2138 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2139 /** Head of the chain of free phys ext nodes. */
2140 uint16_t iPhysExtFreeHead;
2141 /** The number of user nodes we've allocated. */
2142 uint16_t cMaxPhysExts;
2143 /** Pointer to the array of physical xref extent - RC pointer. */
2144 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2145 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2146 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2147 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2148 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2149 /** Hash table for GCPhys addresses. */
2150 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2151 /** The head of the age list. */
2152 uint16_t iAgeHead;
2153 /** The tail of the age list. */
2154 uint16_t iAgeTail;
2155 /** Set if the cache is enabled. */
2156 bool fCacheEnabled;
2157 /** Alignment padding. */
2158 bool afPadding1[3];
2159 /** Head of the list of modified pages. */
2160 uint16_t iModifiedHead;
2161 /** The current number of modified pages. */
2162 uint16_t cModifiedPages;
2163 /** Access handler, RC. */
2164 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2165 /** Access handler, R0. */
2166 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2167 /** Access handler, R3. */
2168 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2169 /** The access handler description (R3 ptr). */
2170 R3PTRTYPE(const char *) pszAccessHandler;
2171# if HC_ARCH_BITS == 32
2172 /** Alignment padding. */
2173 uint32_t u32Padding2;
2174# endif
2175 /* Next available slot. */
2176 uint32_t idxFreeDirtyPage;
2177 /* Number of active dirty pages. */
2178 uint32_t cDirtyPages;
2179 /* Array of current dirty pgm pool page indices. */
2180 struct
2181 {
2182 uint16_t uIdx;
2183 uint16_t Alignment[3];
2184 uint64_t aPage[512];
2185 } aDirtyPages[16];
2186 /** The number of pages currently in use. */
2187 uint16_t cUsedPages;
2188#ifdef VBOX_WITH_STATISTICS
2189 /** The high water mark for cUsedPages. */
2190 uint16_t cUsedPagesHigh;
2191 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2192 /** Profiling pgmPoolAlloc(). */
2193 STAMPROFILEADV StatAlloc;
2194 /** Profiling pgmR3PoolClearDoIt(). */
2195 STAMPROFILE StatClearAll;
2196 /** Profiling pgmR3PoolReset(). */
2197 STAMPROFILE StatR3Reset;
2198 /** Profiling pgmPoolFlushPage(). */
2199 STAMPROFILE StatFlushPage;
2200 /** Profiling pgmPoolFree(). */
2201 STAMPROFILE StatFree;
2202 /** Counting explicit flushes by PGMPoolFlushPage(). */
2203 STAMCOUNTER StatForceFlushPage;
2204 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2205 STAMCOUNTER StatForceFlushDirtyPage;
2206 /** Counting flushes for reused pages. */
2207 STAMCOUNTER StatForceFlushReused;
2208 /** Profiling time spent zeroing pages. */
2209 STAMPROFILE StatZeroPage;
2210 /** Profiling of pgmPoolTrackDeref. */
2211 STAMPROFILE StatTrackDeref;
2212 /** Profiling pgmTrackFlushGCPhysPT. */
2213 STAMPROFILE StatTrackFlushGCPhysPT;
2214 /** Profiling pgmTrackFlushGCPhysPTs. */
2215 STAMPROFILE StatTrackFlushGCPhysPTs;
2216 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2217 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2218 /** Number of times we've been out of user records. */
2219 STAMCOUNTER StatTrackFreeUpOneUser;
2220 /** Nr of flushed entries. */
2221 STAMCOUNTER StatTrackFlushEntry;
2222 /** Nr of updated entries. */
2223 STAMCOUNTER StatTrackFlushEntryKeep;
2224 /** Profiling deref activity related tracking GC physical pages. */
2225 STAMPROFILE StatTrackDerefGCPhys;
2226 /** Number of linear searches for a HCPhys in the ram ranges. */
2227 STAMCOUNTER StatTrackLinearRamSearches;
2228 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2229 STAMCOUNTER StamTrackPhysExtAllocFailures;
2230 /** Profiling the RC/R0 access handler. */
2231 STAMPROFILE StatMonitorRZ;
2232 /** Times we've failed interpreting the instruction. */
2233 STAMCOUNTER StatMonitorRZEmulateInstr;
2234 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2235 STAMPROFILE StatMonitorRZFlushPage;
2236 /* Times we've detected a page table reinit. */
2237 STAMCOUNTER StatMonitorRZFlushReinit;
2238 /** Counting flushes for pages that are modified too often. */
2239 STAMCOUNTER StatMonitorRZFlushModOverflow;
2240 /** Times we've detected fork(). */
2241 STAMCOUNTER StatMonitorRZFork;
2242 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2243 STAMPROFILE StatMonitorRZHandled;
2244 /** Times we've failed interpreting a patch code instruction. */
2245 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2246 /** Times we've failed interpreting a patch code instruction during flushing. */
2247 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2248 /** The number of times we've seen rep prefixes we can't handle. */
2249 STAMCOUNTER StatMonitorRZRepPrefix;
2250 /** Profiling the REP STOSD cases we've handled. */
2251 STAMPROFILE StatMonitorRZRepStosd;
2252 /** Nr of handled PT faults. */
2253 STAMCOUNTER StatMonitorRZFaultPT;
2254 /** Nr of handled PD faults. */
2255 STAMCOUNTER StatMonitorRZFaultPD;
2256 /** Nr of handled PDPT faults. */
2257 STAMCOUNTER StatMonitorRZFaultPDPT;
2258 /** Nr of handled PML4 faults. */
2259 STAMCOUNTER StatMonitorRZFaultPML4;
2260
2261 /** Profiling the R3 access handler. */
2262 STAMPROFILE StatMonitorR3;
2263 /** Times we've failed interpreting the instruction. */
2264 STAMCOUNTER StatMonitorR3EmulateInstr;
2265 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2266 STAMPROFILE StatMonitorR3FlushPage;
2267 /* Times we've detected a page table reinit. */
2268 STAMCOUNTER StatMonitorR3FlushReinit;
2269 /** Counting flushes for pages that are modified too often. */
2270 STAMCOUNTER StatMonitorR3FlushModOverflow;
2271 /** Times we've detected fork(). */
2272 STAMCOUNTER StatMonitorR3Fork;
2273 /** Profiling the R3 access we've handled (except REP STOSD). */
2274 STAMPROFILE StatMonitorR3Handled;
2275 /** The number of times we've seen rep prefixes we can't handle. */
2276 STAMCOUNTER StatMonitorR3RepPrefix;
2277 /** Profiling the REP STOSD cases we've handled. */
2278 STAMPROFILE StatMonitorR3RepStosd;
2279 /** Nr of handled PT faults. */
2280 STAMCOUNTER StatMonitorR3FaultPT;
2281 /** Nr of handled PD faults. */
2282 STAMCOUNTER StatMonitorR3FaultPD;
2283 /** Nr of handled PDPT faults. */
2284 STAMCOUNTER StatMonitorR3FaultPDPT;
2285 /** Nr of handled PML4 faults. */
2286 STAMCOUNTER StatMonitorR3FaultPML4;
2287 /** The number of times we're called in an async thread an need to flush. */
2288 STAMCOUNTER StatMonitorR3Async;
2289 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2290 STAMCOUNTER StatResetDirtyPages;
2291 /** Times we've called pgmPoolAddDirtyPage. */
2292 STAMCOUNTER StatDirtyPage;
2293 /** Times we've had to flush duplicates for dirty page management. */
2294 STAMCOUNTER StatDirtyPageDupFlush;
2295 /** Times we've had to flush because of overflow. */
2296 STAMCOUNTER StatDirtyPageOverFlowFlush;
2297
2298 /** The high water mark for cModifiedPages. */
2299 uint16_t cModifiedPagesHigh;
2300 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2301
2302 /** The number of cache hits. */
2303 STAMCOUNTER StatCacheHits;
2304 /** The number of cache misses. */
2305 STAMCOUNTER StatCacheMisses;
2306 /** The number of times we've got a conflict of 'kind' in the cache. */
2307 STAMCOUNTER StatCacheKindMismatches;
2308 /** Number of times we've been out of pages. */
2309 STAMCOUNTER StatCacheFreeUpOne;
2310 /** The number of cacheable allocations. */
2311 STAMCOUNTER StatCacheCacheable;
2312 /** The number of uncacheable allocations. */
2313 STAMCOUNTER StatCacheUncacheable;
2314#else
2315 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2316#endif
2317 /** The AVL tree for looking up a page by its HC physical address. */
2318 AVLOHCPHYSTREE HCPhysTree;
2319 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2320 /** Array of pages. (cMaxPages in length)
2321 * The Id is the index into thist array.
2322 */
2323 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2324} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2325AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2326AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2327AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2328#ifdef VBOX_WITH_STATISTICS
2329AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2330#endif
2331AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2332
2333
2334/** @def PGMPOOL_PAGE_2_PTR
2335 * Maps a pool page pool into the current context.
2336 *
2337 * @returns VBox status code.
2338 * @param pVM The VM handle.
2339 * @param pPage The pool page.
2340 *
2341 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2342 * small page window employeed by that function. Be careful.
2343 * @remark There is no need to assert on the result.
2344 */
2345#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2346# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2347#elif defined(VBOX_STRICT)
2348# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2349DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2350{
2351 Assert(pPage && pPage->pvPageR3);
2352 return pPage->pvPageR3;
2353}
2354#else
2355# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2356#endif
2357
2358
2359/** @def PGMPOOL_PAGE_2_PTR_V2
2360 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2361 *
2362 * @returns VBox status code.
2363 * @param pVM The VM handle.
2364 * @param pVCpu The current CPU.
2365 * @param pPage The pool page.
2366 *
2367 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2368 * small page window employeed by that function. Be careful.
2369 * @remark There is no need to assert on the result.
2370 */
2371#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2372# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2373#else
2374# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2375#endif
2376
2377
2378/** @name Per guest page tracking data.
2379 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2380 * is to use more bits for it and split it up later on. But for now we'll play
2381 * safe and change as little as possible.
2382 *
2383 * The 16-bit word has two parts:
2384 *
2385 * The first 14-bit forms the @a idx field. It is either the index of a page in
2386 * the shadow page pool, or and index into the extent list.
2387 *
2388 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2389 * shadow page pool references to the page. If cRefs equals
2390 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2391 * (misnomer) table and not the shadow page pool.
2392 *
2393 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2394 * the 16-bit word.
2395 *
2396 * @{ */
2397/** The shift count for getting to the cRefs part. */
2398#define PGMPOOL_TD_CREFS_SHIFT 14
2399/** The mask applied after shifting the tracking data down by
2400 * PGMPOOL_TD_CREFS_SHIFT. */
2401#define PGMPOOL_TD_CREFS_MASK 0x3
2402/** The cRefs value used to indicate that the idx is the head of a
2403 * physical cross reference list. */
2404#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2405/** The shift used to get idx. */
2406#define PGMPOOL_TD_IDX_SHIFT 0
2407/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2408#define PGMPOOL_TD_IDX_MASK 0x3fff
2409/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2410 * simply too many mappings of this page. */
2411#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2412
2413/** @def PGMPOOL_TD_MAKE
2414 * Makes a 16-bit tracking data word.
2415 *
2416 * @returns tracking data.
2417 * @param cRefs The @a cRefs field. Must be within bounds!
2418 * @param idx The @a idx field. Must also be within bounds! */
2419#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2420
2421/** @def PGMPOOL_TD_GET_CREFS
2422 * Get the @a cRefs field from a tracking data word.
2423 *
2424 * @returns The @a cRefs field
2425 * @param u16 The tracking data word.
2426 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2427 * non-zero @a u16. */
2428#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2429
2430/** @def PGMPOOL_TD_GET_IDX
2431 * Get the @a idx field from a tracking data word.
2432 *
2433 * @returns The @a idx field
2434 * @param u16 The tracking data word. */
2435#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2436/** @} */
2437
2438
2439/**
2440 * Trees are using self relative offsets as pointers.
2441 * So, all its data, including the root pointer, must be in the heap for HC and GC
2442 * to have the same layout.
2443 */
2444typedef struct PGMTREES
2445{
2446 /** Physical access handlers (AVL range+offsetptr tree). */
2447 AVLROGCPHYSTREE PhysHandlers;
2448 /** Virtual access handlers (AVL range + GC ptr tree). */
2449 AVLROGCPTRTREE VirtHandlers;
2450 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2451 AVLROGCPHYSTREE PhysToVirtHandlers;
2452 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2453 AVLROGCPTRTREE HyperVirtHandlers;
2454} PGMTREES;
2455/** Pointer to PGM trees. */
2456typedef PGMTREES *PPGMTREES;
2457
2458
2459/**
2460 * Page fault guest state for the AMD64 paging mode.
2461 */
2462typedef struct PGMPTWALKCORE
2463{
2464 /** The guest virtual address that is being resolved by the walk
2465 * (input). */
2466 RTGCPTR GCPtr;
2467
2468 /** The guest physical address that is the result of the walk.
2469 * @remarks only valid if fSucceeded is set. */
2470 RTGCPHYS GCPhys;
2471
2472 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2473 bool fSucceeded;
2474 /** The level problem arrised at.
2475 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2476 * level 8. This is 0 on success. */
2477 uint8_t uLevel;
2478 /** Set if the page isn't present. */
2479 bool fNotPresent;
2480 /** Encountered a bad physical address. */
2481 bool fBadPhysAddr;
2482 /** Set if there was reserved bit violations. */
2483 bool fRsvdError;
2484 /** Set if it involves a big page (2/4 MB). */
2485 bool fBigPage;
2486 /** Set if it involves a gigantic page (1 GB). */
2487 bool fGigantPage;
2488 /** The effect X86_PTE_US flag for the address. */
2489 bool fEffectiveUS;
2490 /** The effect X86_PTE_RW flag for the address. */
2491 bool fEffectiveRW;
2492 /** The effect X86_PTE_NX flag for the address. */
2493 bool fEffectiveNX;
2494} PGMPTWALKCORE;
2495
2496
2497/**
2498 * Guest page table walk for the AMD64 mode.
2499 */
2500typedef struct PGMPTWALKGSTAMD64
2501{
2502 /** The common core. */
2503 PGMPTWALKCORE Core;
2504
2505 PX86PML4 pPml4;
2506 PX86PML4E pPml4e;
2507 X86PML4E Pml4e;
2508
2509 PX86PDPT pPdpt;
2510 PX86PDPE pPdpe;
2511 X86PDPE Pdpe;
2512
2513 PX86PDPAE pPd;
2514 PX86PDEPAE pPde;
2515 X86PDEPAE Pde;
2516
2517 PX86PTPAE pPt;
2518 PX86PTEPAE pPte;
2519 X86PTEPAE Pte;
2520} PGMPTWALKGSTAMD64;
2521/** Pointer to a AMD64 guest page table walk. */
2522typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2523/** Pointer to a const AMD64 guest page table walk. */
2524typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2525
2526/**
2527 * Guest page table walk for the PAE mode.
2528 */
2529typedef struct PGMPTWALKGSTPAE
2530{
2531 /** The common core. */
2532 PGMPTWALKCORE Core;
2533
2534 PX86PDPT pPdpt;
2535 PX86PDPE pPdpe;
2536 X86PDPE Pdpe;
2537
2538 PX86PDPAE pPd;
2539 PX86PDEPAE pPde;
2540 X86PDEPAE Pde;
2541
2542 PX86PTPAE pPt;
2543 PX86PTEPAE pPte;
2544 X86PTEPAE Pte;
2545} PGMPTWALKGSTPAE;
2546/** Pointer to a PAE guest page table walk. */
2547typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2548/** Pointer to a const AMD64 guest page table walk. */
2549typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2550
2551/**
2552 * Guest page table walk for the 32-bit mode.
2553 */
2554typedef struct PGMPTWALKGST32BIT
2555{
2556 /** The common core. */
2557 PGMPTWALKCORE Core;
2558
2559 PX86PD pPd;
2560 PX86PDE pPde;
2561 X86PDE Pde;
2562
2563 PX86PT pPt;
2564 PX86PTE pPte;
2565 X86PTE Pte;
2566} PGMPTWALKGST32BIT;
2567/** Pointer to a 32-bit guest page table walk. */
2568typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2569/** Pointer to a const 32-bit guest page table walk. */
2570typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2571
2572
2573/** @name Paging mode macros
2574 * @{
2575 */
2576#ifdef IN_RC
2577# define PGM_CTX(a,b) a##RC##b
2578# define PGM_CTX_STR(a,b) a "GC" b
2579# define PGM_CTX_DECL(type) VMMRCDECL(type)
2580#else
2581# ifdef IN_RING3
2582# define PGM_CTX(a,b) a##R3##b
2583# define PGM_CTX_STR(a,b) a "R3" b
2584# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2585# else
2586# define PGM_CTX(a,b) a##R0##b
2587# define PGM_CTX_STR(a,b) a "R0" b
2588# define PGM_CTX_DECL(type) VMMDECL(type)
2589# endif
2590#endif
2591
2592#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2593#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2594#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2595#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2596#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2597#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2598#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2599#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2600#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2601#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2602#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2603#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2604#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2605#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2606#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2607#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2608#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2609
2610#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2611#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2612#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2613#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2614#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2615#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2616#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2617#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2618#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2619#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2620#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2621#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2622#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2623#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2624#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2625#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2626#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2627
2628/* Shw_Gst */
2629#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2630#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2631#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2632#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2633#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2634#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2635#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2636#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2637#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2638#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2639#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2640#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2641#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2642#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2643#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2644#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2645#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2646#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2647#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2648
2649#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2650#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2651#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2652#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2653#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2654#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2655#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2656#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2657#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2658#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2659#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2660#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2661#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2662#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2663#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2664#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2665#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2666#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2667#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2668#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2669#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2670#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2671#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2672#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2673#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2674#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2675#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2676#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2677#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2678#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2679#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2680#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2681#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2682#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2683#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2684#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2685#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2686
2687#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2688#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2689/** @} */
2690
2691/**
2692 * Data for each paging mode.
2693 */
2694typedef struct PGMMODEDATA
2695{
2696 /** The guest mode type. */
2697 uint32_t uGstType;
2698 /** The shadow mode type. */
2699 uint32_t uShwType;
2700
2701 /** @name Function pointers for Shadow paging.
2702 * @{
2703 */
2704 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2705 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2706 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2707 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2708
2709 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2710 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2711
2712 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2713 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2714 /** @} */
2715
2716 /** @name Function pointers for Guest paging.
2717 * @{
2718 */
2719 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2720 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2721 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2722 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2723 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2724 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2725 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2726 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2727 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2728 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2729 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2730 /** @} */
2731
2732 /** @name Function pointers for Both Shadow and Guest paging.
2733 * @{
2734 */
2735 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2736 /* no pfnR3BthTrap0eHandler */
2737 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2738 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2739 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2740 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2741#ifdef VBOX_STRICT
2742 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2743#endif
2744 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2745 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2746
2747 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2748 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2749 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2750 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2751 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2752#ifdef VBOX_STRICT
2753 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2754#endif
2755 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2756 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2757
2758 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2759 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2760 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2761 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2762 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2763#ifdef VBOX_STRICT
2764 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2765#endif
2766 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2767 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2768 /** @} */
2769} PGMMODEDATA, *PPGMMODEDATA;
2770
2771
2772#ifdef VBOX_WITH_STATISTICS
2773/**
2774 * PGM statistics.
2775 *
2776 * These lives on the heap when compiled in as they would otherwise waste
2777 * unnecessary space in release builds.
2778 */
2779typedef struct PGMSTATS
2780{
2781 /* R3 only: */
2782 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2783 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2784
2785 /* R3+RZ */
2786 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2787 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2788 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2789 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2790 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2791 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2792 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2793 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2794 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2795 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2796 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2797 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2798 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2799 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2800 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2801 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2802 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2803 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2804 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2805 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2806 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2807 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2808 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2809 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2810/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2811 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2812 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2813/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2814
2815 /* RC only: */
2816 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2817 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2818
2819 STAMCOUNTER StatRZPhysRead;
2820 STAMCOUNTER StatRZPhysReadBytes;
2821 STAMCOUNTER StatRZPhysWrite;
2822 STAMCOUNTER StatRZPhysWriteBytes;
2823 STAMCOUNTER StatR3PhysRead;
2824 STAMCOUNTER StatR3PhysReadBytes;
2825 STAMCOUNTER StatR3PhysWrite;
2826 STAMCOUNTER StatR3PhysWriteBytes;
2827 STAMCOUNTER StatRCPhysRead;
2828 STAMCOUNTER StatRCPhysReadBytes;
2829 STAMCOUNTER StatRCPhysWrite;
2830 STAMCOUNTER StatRCPhysWriteBytes;
2831
2832 STAMCOUNTER StatRZPhysSimpleRead;
2833 STAMCOUNTER StatRZPhysSimpleReadBytes;
2834 STAMCOUNTER StatRZPhysSimpleWrite;
2835 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2836 STAMCOUNTER StatR3PhysSimpleRead;
2837 STAMCOUNTER StatR3PhysSimpleReadBytes;
2838 STAMCOUNTER StatR3PhysSimpleWrite;
2839 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2840 STAMCOUNTER StatRCPhysSimpleRead;
2841 STAMCOUNTER StatRCPhysSimpleReadBytes;
2842 STAMCOUNTER StatRCPhysSimpleWrite;
2843 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2844
2845 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2846 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2847 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2848 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2849 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2850 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2851 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2852
2853 /** Time spent by the host OS for large page allocation. */
2854 STAMPROFILE StatAllocLargePage;
2855 /** Time spent clearing the newly allocated large pages. */
2856 STAMPROFILE StatClearLargePage;
2857 /** The number of times allocating a large pages takes more than the allowed period. */
2858 STAMCOUNTER StatLargePageOverflow;
2859 /** pgmPhysIsValidLargePage profiling - R3 */
2860 STAMPROFILE StatR3IsValidLargePage;
2861 /** pgmPhysIsValidLargePage profiling - RZ*/
2862 STAMPROFILE StatRZIsValidLargePage;
2863
2864 STAMPROFILE StatChunkAging;
2865 STAMPROFILE StatChunkFindCandidate;
2866 STAMPROFILE StatChunkUnmap;
2867 STAMPROFILE StatChunkMap;
2868} PGMSTATS;
2869#endif /* VBOX_WITH_STATISTICS */
2870
2871
2872/**
2873 * Converts a PGM pointer into a VM pointer.
2874 * @returns Pointer to the VM structure the PGM is part of.
2875 * @param pPGM Pointer to PGM instance data.
2876 */
2877#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2878
2879/**
2880 * PGM Data (part of VM)
2881 */
2882typedef struct PGM
2883{
2884 /** Offset to the VM structure. */
2885 int32_t offVM;
2886 /** Offset of the PGMCPU structure relative to VMCPU. */
2887 int32_t offVCpuPGM;
2888
2889 /** @cfgm{RamPreAlloc, boolean, false}
2890 * Indicates whether the base RAM should all be allocated before starting
2891 * the VM (default), or if it should be allocated when first written to.
2892 */
2893 bool fRamPreAlloc;
2894 /** Indicates whether write monitoring is currently in use.
2895 * This is used to prevent conflicts between live saving and page sharing
2896 * detection. */
2897 bool fPhysWriteMonitoringEngaged;
2898 /** Set if the CPU has less than 52-bit physical address width.
2899 * This is used */
2900 bool fLessThan52PhysicalAddressBits;
2901 /** Set when nested paging is active.
2902 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2903 * compilers optimize the code better. Whether we use nested paging or
2904 * not is something we find out during VMM initialization and we won't
2905 * change this later on. */
2906 bool fNestedPaging;
2907 /** The host paging mode. (This is what SUPLib reports.) */
2908 SUPPAGINGMODE enmHostMode;
2909 /** We're not in a state which permits writes to guest memory.
2910 * (Only used in strict builds.) */
2911 bool fNoMorePhysWrites;
2912 /** Set if PCI passthrough is enabled. */
2913 bool fPciPassthrough;
2914 /** Alignment padding that makes the next member start on a 8 byte boundary. */
2915 bool afAlignment1[2];
2916
2917 /** Indicates that PGMR3FinalizeMappings has been called and that further
2918 * PGMR3MapIntermediate calls will be rejected. */
2919 bool fFinalizedMappings;
2920 /** If set no conflict checks are required. */
2921 bool fMappingsFixed;
2922 /** If set if restored as fixed but we were unable to re-fixate at the old
2923 * location because of room or address incompatibilities. */
2924 bool fMappingsFixedRestored;
2925 /** If set, then no mappings are put into the shadow page table.
2926 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2927 bool fMappingsDisabled;
2928 /** Size of fixed mapping.
2929 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2930 uint32_t cbMappingFixed;
2931 /** Generation ID for the RAM ranges. This member is incremented everytime
2932 * a RAM range is linked or unlinked. */
2933 uint32_t volatile idRamRangesGen;
2934
2935 /** Base address (GC) of fixed mapping.
2936 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2937 RTGCPTR GCPtrMappingFixed;
2938 /** The address of the previous RAM range mapping. */
2939 RTGCPTR GCPtrPrevRamRangeMapping;
2940
2941 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2942 RTGCPHYS GCPhys4MBPSEMask;
2943 /** Mask containing the invalid bits of a guest physical address.
2944 * @remarks this does not stop at bit 52. */
2945 RTGCPHYS GCPhysInvAddrMask;
2946
2947
2948 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2949 * This is sorted by physical address and contains no overlapping ranges. */
2950 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2951 /** PGM offset based trees - R3 Ptr. */
2952 R3PTRTYPE(PPGMTREES) pTreesR3;
2953 /** Caching the last physical handler we looked up in R3. */
2954 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2955 /** Shadow Page Pool - R3 Ptr. */
2956 R3PTRTYPE(PPGMPOOL) pPoolR3;
2957 /** Linked list of GC mappings - for HC.
2958 * The list is sorted ascending on address. */
2959 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2960 /** Pointer to the list of ROM ranges - for R3.
2961 * This is sorted by physical address and contains no overlapping ranges. */
2962 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2963 /** Pointer to the list of MMIO2 ranges - for R3.
2964 * Registration order. */
2965 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2966 /** Pointer to SHW+GST mode data (function pointers).
2967 * The index into this table is made up from */
2968 R3PTRTYPE(PPGMMODEDATA) paModeData;
2969 /*RTR3PTR R3PtrAlignment0;*/
2970
2971
2972 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2973 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2974 /** PGM offset based trees - R0 Ptr. */
2975 R0PTRTYPE(PPGMTREES) pTreesR0;
2976 /** Caching the last physical handler we looked up in R0. */
2977 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2978 /** Shadow Page Pool - R0 Ptr. */
2979 R0PTRTYPE(PPGMPOOL) pPoolR0;
2980 /** Linked list of GC mappings - for R0.
2981 * The list is sorted ascending on address. */
2982 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2983 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2984 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2985 /*RTR0PTR R0PtrAlignment0;*/
2986
2987
2988 /** RC pointer corresponding to PGM::pRamRangesR3. */
2989 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2990 /** PGM offset based trees - RC Ptr. */
2991 RCPTRTYPE(PPGMTREES) pTreesRC;
2992 /** Caching the last physical handler we looked up in RC. */
2993 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2994 /** Shadow Page Pool - RC Ptr. */
2995 RCPTRTYPE(PPGMPOOL) pPoolRC;
2996 /** Linked list of GC mappings - for RC.
2997 * The list is sorted ascending on address. */
2998 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2999 /** RC pointer corresponding to PGM::pRomRangesR3. */
3000 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3001 /*RTRCPTR RCPtrAlignment0;*/
3002 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3003 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3004 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3005 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3006
3007
3008 /** Pointer to the 5 page CR3 content mapping.
3009 * The first page is always the CR3 (in some form) while the 4 other pages
3010 * are used of the PDs in PAE mode. */
3011 RTGCPTR GCPtrCR3Mapping;
3012
3013 /** @name Intermediate Context
3014 * @{ */
3015 /** Pointer to the intermediate page directory - Normal. */
3016 R3PTRTYPE(PX86PD) pInterPD;
3017 /** Pointer to the intermediate page tables - Normal.
3018 * There are two page tables, one for the identity mapping and one for
3019 * the host context mapping (of the core code). */
3020 R3PTRTYPE(PX86PT) apInterPTs[2];
3021 /** Pointer to the intermediate page tables - PAE. */
3022 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3023 /** Pointer to the intermediate page directory - PAE. */
3024 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3025 /** Pointer to the intermediate page directory - PAE. */
3026 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3027 /** Pointer to the intermediate page-map level 4 - AMD64. */
3028 R3PTRTYPE(PX86PML4) pInterPaePML4;
3029 /** Pointer to the intermediate page directory - AMD64. */
3030 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3031 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3032 RTHCPHYS HCPhysInterPD;
3033 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3034 RTHCPHYS HCPhysInterPaePDPT;
3035 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3036 RTHCPHYS HCPhysInterPaePML4;
3037 /** @} */
3038
3039 /** Base address of the dynamic page mapping area.
3040 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3041 *
3042 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3043 * work out. Some cleaning up of the initialization that would
3044 * remove this memory is yet to be done...
3045 */
3046 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3047 /** The address of the raw-mode context mapping cache. */
3048 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3049 /** The address of the ring-0 mapping cache if we're making use of it. */
3050 RTR0PTR pvR0DynMapUsed;
3051#if HC_ARCH_BITS == 32
3052 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3053 uint32_t u32Alignment2;
3054#endif
3055
3056 /** PGM critical section.
3057 * This protects the physical & virtual access handlers, ram ranges,
3058 * and the page flag updating (some of it anyway).
3059 */
3060 PDMCRITSECT CritSect;
3061
3062 /**
3063 * Data associated with managing the ring-3 mappings of the allocation chunks.
3064 */
3065 struct
3066 {
3067 /** The chunk tree, ordered by chunk id. */
3068#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3069 R3PTRTYPE(PAVLU32NODECORE) pTree;
3070#else
3071 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3072#endif
3073#if HC_ARCH_BITS == 32
3074 uint32_t u32Alignment;
3075#endif
3076 /** The chunk mapping TLB. */
3077 PGMCHUNKR3MAPTLB Tlb;
3078 /** The number of mapped chunks. */
3079 uint32_t c;
3080 /** The maximum number of mapped chunks.
3081 * @cfgm PGM/MaxRing3Chunks */
3082 uint32_t cMax;
3083 /** The current time. */
3084 uint32_t iNow;
3085 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3086 uint32_t AgeingCountdown;
3087 } ChunkR3Map;
3088
3089 /**
3090 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3091 */
3092 PGMPAGER3MAPTLB PhysTlbHC;
3093
3094 /** @name The zero page.
3095 * @{ */
3096 /** The host physical address of the zero page. */
3097 RTHCPHYS HCPhysZeroPg;
3098 /** The ring-3 mapping of the zero page. */
3099 RTR3PTR pvZeroPgR3;
3100 /** The ring-0 mapping of the zero page. */
3101 RTR0PTR pvZeroPgR0;
3102 /** The GC mapping of the zero page. */
3103 RTRCPTR pvZeroPgRC;
3104 RTRCPTR RCPtrAlignment3;
3105 /** @}*/
3106
3107 /** @name The Invalid MMIO page.
3108 * This page is filled with 0xfeedface.
3109 * @{ */
3110 /** The host physical address of the invalid MMIO page. */
3111 RTHCPHYS HCPhysMmioPg;
3112 /** The host pysical address of the invalid MMIO page plus all invalid
3113 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3114 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3115 RTHCPHYS HCPhysInvMmioPg;
3116 /** The ring-3 mapping of the invalid MMIO page. */
3117 RTR3PTR pvMmioPgR3;
3118#if HC_ARCH_BITS == 32
3119 RTR3PTR R3PtrAlignment4;
3120#endif
3121 /** @} */
3122
3123
3124 /** The number of handy pages. */
3125 uint32_t cHandyPages;
3126
3127 /** The number of large handy pages. */
3128 uint32_t cLargeHandyPages;
3129
3130 /**
3131 * Array of handy pages.
3132 *
3133 * This array is used in a two way communication between pgmPhysAllocPage
3134 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3135 * an intermediary.
3136 *
3137 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3138 * (The current size of 32 pages, means 128 KB of handy memory.)
3139 */
3140 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3141
3142 /**
3143 * Array of large handy pages. (currently size 1)
3144 *
3145 * This array is used in a two way communication between pgmPhysAllocLargePage
3146 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3147 * an intermediary.
3148 */
3149 GMMPAGEDESC aLargeHandyPage[1];
3150
3151 /**
3152 * Live save data.
3153 */
3154 struct
3155 {
3156 /** Per type statistics. */
3157 struct
3158 {
3159 /** The number of ready pages. */
3160 uint32_t cReadyPages;
3161 /** The number of dirty pages. */
3162 uint32_t cDirtyPages;
3163 /** The number of ready zero pages. */
3164 uint32_t cZeroPages;
3165 /** The number of write monitored pages. */
3166 uint32_t cMonitoredPages;
3167 } Rom,
3168 Mmio2,
3169 Ram;
3170 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3171 uint32_t cIgnoredPages;
3172 /** Indicates that a live save operation is active. */
3173 bool fActive;
3174 /** Padding. */
3175 bool afReserved[2];
3176 /** The next history index. */
3177 uint8_t iDirtyPagesHistory;
3178 /** History of the total amount of dirty pages. */
3179 uint32_t acDirtyPagesHistory[64];
3180 /** Short term dirty page average. */
3181 uint32_t cDirtyPagesShort;
3182 /** Long term dirty page average. */
3183 uint32_t cDirtyPagesLong;
3184 /** The number of saved pages. This is used to get some kind of estimate of the
3185 * link speed so we can decide when we're done. It is reset after the first
3186 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3187 * zero pages. */
3188 uint64_t cSavedPages;
3189 /** The nanosecond timestamp when cSavedPages was 0. */
3190 uint64_t uSaveStartNS;
3191 /** Pages per second (for statistics). */
3192 uint32_t cPagesPerSecond;
3193 uint32_t cAlignment;
3194 } LiveSave;
3195
3196 /** @name Error injection.
3197 * @{ */
3198 /** Inject handy page allocation errors pretending we're completely out of
3199 * memory. */
3200 bool volatile fErrInjHandyPages;
3201 /** Padding. */
3202 bool afReserved[3];
3203 /** @} */
3204
3205 /** @name Release Statistics
3206 * @{ */
3207 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3208 uint32_t cPrivatePages; /**< The number of private pages. */
3209 uint32_t cSharedPages; /**< The number of shared pages. */
3210 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3211 uint32_t cZeroPages; /**< The number of zero backed pages. */
3212 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3213 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3214 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3215 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3216 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3217 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3218 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3219 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3220 uint32_t cLargePages; /**< The number of large pages. */
3221 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3222/* uint32_t aAlignment4[1]; */
3223
3224 /** The number of times we were forced to change the hypervisor region location. */
3225 STAMCOUNTER cRelocations;
3226
3227 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3228 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3229 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3230 /** @} */
3231
3232#ifdef VBOX_WITH_STATISTICS
3233 /** @name Statistics on the heap.
3234 * @{ */
3235 R3PTRTYPE(PGMSTATS *) pStatsR3;
3236 R0PTRTYPE(PGMSTATS *) pStatsR0;
3237 RCPTRTYPE(PGMSTATS *) pStatsRC;
3238 RTRCPTR RCPtrAlignment;
3239 /** @} */
3240#endif
3241} PGM;
3242#ifndef IN_TSTVMSTRUCTGC /* HACK */
3243AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3244AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3245AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3246AssertCompileMemberAlignment(PGM, CritSect, 8);
3247AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3248AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3249AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3250AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3251AssertCompileMemberAlignment(PGM, cRelocations, 8);
3252#endif /* !IN_TSTVMSTRUCTGC */
3253/** Pointer to the PGM instance data. */
3254typedef PGM *PPGM;
3255
3256
3257
3258typedef struct PGMCPUSTATS
3259{
3260 /* Common */
3261 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3262 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3263
3264 /* R0 only: */
3265 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3266 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3267
3268 /* RZ only: */
3269 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3270 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3271 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3272 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3273 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3274 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3275 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3276 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3277 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3278 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3279 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3280 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3281 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3282 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3283 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3284 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3285 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3286 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3287 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3288 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3289 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3290 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3291 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3292 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3293 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3294 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3295 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3296 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3297 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3298 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3299 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3300 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3301 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3302 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3303 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3304 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3305 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3306 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3307 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3308 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3309 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3310 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3311 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3312 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3313 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3314 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3315 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3316 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3317 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3318 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3319 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3320 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3321 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3322 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3323 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3324 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3325 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3326 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3327 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3328 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3329 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3330 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3331 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3332 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3333 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3334 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3335 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3336 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3337 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3338 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3339 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3340 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3341 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3342 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3343 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3344 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3345
3346 /* HC - R3 and (maybe) R0: */
3347
3348 /* RZ & R3: */
3349 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3350 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3351 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3352 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3353 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3354 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3355 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3356 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3357 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3358 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3359 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3360 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3361 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3362 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3363 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3364 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3365 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3366 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3367 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3368 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3369 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3370 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3371 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3372 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3373 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3374 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3375 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3376 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3377 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3378 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3379 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3380 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3381 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3382 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3383 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3384 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3385 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3386 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3387 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3388 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3389 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3390 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3391 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3392 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3393 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3394 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3395 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3396
3397 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3398 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3399 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3400 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3401 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3402 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3403 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3404 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3405 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3406 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3407 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3408 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3409 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3410 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3411 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3412 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3413 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3414 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3415 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3416 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3417 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3418 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3419 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3420 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3421 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3422 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3423 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3424 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3425 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3426 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3427 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3428 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3429 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3430 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3431 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3432 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3433 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3434 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3435 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3436 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3437 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3438 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3439 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3440 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3441 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3442 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3443 /** @} */
3444} PGMCPUSTATS;
3445
3446
3447/**
3448 * Converts a PGMCPU pointer into a VM pointer.
3449 * @returns Pointer to the VM structure the PGM is part of.
3450 * @param pPGM Pointer to PGMCPU instance data.
3451 */
3452#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3453
3454/**
3455 * Converts a PGMCPU pointer into a PGM pointer.
3456 * @returns Pointer to the VM structure the PGM is part of.
3457 * @param pPGM Pointer to PGMCPU instance data.
3458 */
3459#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3460
3461/**
3462 * PGMCPU Data (part of VMCPU).
3463 */
3464typedef struct PGMCPU
3465{
3466 /** Offset to the VM structure. */
3467 int32_t offVM;
3468 /** Offset to the VMCPU structure. */
3469 int32_t offVCpu;
3470 /** Offset of the PGM structure relative to VMCPU. */
3471 int32_t offPGM;
3472 uint32_t uPadding0; /**< structure size alignment. */
3473
3474#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3475 /** Automatically tracked physical memory mapping set.
3476 * Ring-0 and strict raw-mode builds. */
3477 PGMMAPSET AutoSet;
3478#endif
3479
3480 /** A20 gate mask.
3481 * Our current approach to A20 emulation is to let REM do it and don't bother
3482 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3483 * But whould need arrise, we'll subject physical addresses to this mask. */
3484 RTGCPHYS GCPhysA20Mask;
3485 /** A20 gate state - boolean! */
3486 bool fA20Enabled;
3487 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3488 bool fNoExecuteEnabled;
3489 /** Unused bits. */
3490 bool afUnused[2];
3491
3492 /** What needs syncing (PGM_SYNC_*).
3493 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3494 * PGMFlushTLB, and PGMR3Load. */
3495 RTUINT fSyncFlags;
3496
3497 /** The shadow paging mode. */
3498 PGMMODE enmShadowMode;
3499 /** The guest paging mode. */
3500 PGMMODE enmGuestMode;
3501
3502 /** The current physical address representing in the guest CR3 register. */
3503 RTGCPHYS GCPhysCR3;
3504
3505 /** @name 32-bit Guest Paging.
3506 * @{ */
3507 /** The guest's page directory, R3 pointer. */
3508 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3509#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3510 /** The guest's page directory, R0 pointer. */
3511 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3512#endif
3513 /** The guest's page directory, static RC mapping. */
3514 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3515 /** Mask containing the MBZ bits of a big page PDE. */
3516 uint32_t fGst32BitMbzBigPdeMask;
3517 /** Set if the page size extension (PSE) is enabled. */
3518 bool fGst32BitPageSizeExtension;
3519 /** Alignment padding. */
3520 bool afAlignment2[3];
3521 /** @} */
3522
3523 /** @name PAE Guest Paging.
3524 * @{ */
3525 /** The guest's page directory pointer table, static RC mapping. */
3526 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3527 /** The guest's page directory pointer table, R3 pointer. */
3528 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3529#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3530 /** The guest's page directory pointer table, R0 pointer. */
3531 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3532#endif
3533
3534 /** The guest's page directories, R3 pointers.
3535 * These are individual pointers and don't have to be adjacent.
3536 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3537 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3538 /** The guest's page directories, R0 pointers.
3539 * Same restrictions as apGstPaePDsR3. */
3540#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3541 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3542#endif
3543 /** The guest's page directories, static GC mapping.
3544 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3545 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3546 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3547 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3548 RTGCPHYS aGCPhysGstPaePDs[4];
3549 /** The physical addresses of the monitored guest page directories (PAE). */
3550 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3551 /** Mask containing the MBZ PTE bits. */
3552 uint64_t fGstPaeMbzPteMask;
3553 /** Mask containing the MBZ PDE bits. */
3554 uint64_t fGstPaeMbzPdeMask;
3555 /** Mask containing the MBZ big page PDE bits. */
3556 uint64_t fGstPaeMbzBigPdeMask;
3557 /** Mask containing the MBZ PDPE bits. */
3558 uint64_t fGstPaeMbzPdpeMask;
3559 /** @} */
3560
3561 /** @name AMD64 Guest Paging.
3562 * @{ */
3563 /** The guest's page directory pointer table, R3 pointer. */
3564 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3565#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3566 /** The guest's page directory pointer table, R0 pointer. */
3567 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3568#else
3569 RTR0PTR alignment6b; /**< alignment equalizer. */
3570#endif
3571 /** Mask containing the MBZ PTE bits. */
3572 uint64_t fGstAmd64MbzPteMask;
3573 /** Mask containing the MBZ PDE bits. */
3574 uint64_t fGstAmd64MbzPdeMask;
3575 /** Mask containing the MBZ big page PDE bits. */
3576 uint64_t fGstAmd64MbzBigPdeMask;
3577 /** Mask containing the MBZ PDPE bits. */
3578 uint64_t fGstAmd64MbzPdpeMask;
3579 /** Mask containing the MBZ big page PDPE bits. */
3580 uint64_t fGstAmd64MbzBigPdpeMask;
3581 /** Mask containing the MBZ PML4E bits. */
3582 uint64_t fGstAmd64MbzPml4eMask;
3583 /** Mask containing the PDPE bits that we shadow. */
3584 uint64_t fGstAmd64ShadowedPdpeMask;
3585 /** Mask containing the PML4E bits that we shadow. */
3586 uint64_t fGstAmd64ShadowedPml4eMask;
3587 /** @} */
3588
3589 /** @name PAE and AMD64 Guest Paging.
3590 * @{ */
3591 /** Mask containing the PTE bits that we shadow. */
3592 uint64_t fGst64ShadowedPteMask;
3593 /** Mask containing the PDE bits that we shadow. */
3594 uint64_t fGst64ShadowedPdeMask;
3595 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3596 uint64_t fGst64ShadowedBigPdeMask;
3597 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3598 uint64_t fGst64ShadowedBigPde4PteMask;
3599 /** @} */
3600
3601 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3602 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3603 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3604 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3605 /** Pointer to the page of the current active CR3 - RC Ptr. */
3606 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3607 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3608 uint32_t iShwUser;
3609 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3610 uint32_t iShwUserTable;
3611# if HC_ARCH_BITS == 64
3612 RTRCPTR alignment6; /**< structure size alignment. */
3613# endif
3614 /** @} */
3615
3616 /** @name Function pointers for Shadow paging.
3617 * @{
3618 */
3619 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3620 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3621 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3622 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3623
3624 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3625 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3626
3627 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3628 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3629
3630 /** @} */
3631
3632 /** @name Function pointers for Guest paging.
3633 * @{
3634 */
3635 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3636 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3637 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3638 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3639 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3640 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3641 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3642 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3643#if HC_ARCH_BITS == 64
3644 RTRCPTR alignment3; /**< structure size alignment. */
3645#endif
3646
3647 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3648 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3649 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3650 /** @} */
3651
3652 /** @name Function pointers for Both Shadow and Guest paging.
3653 * @{
3654 */
3655 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3656 /* no pfnR3BthTrap0eHandler */
3657 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3658 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3659 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3660 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3661 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3662 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3663 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3664
3665 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3666 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3667 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3668 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3669 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3670 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3671 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3672 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3673
3674 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3675 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3676 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3677 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3678 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3679 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3680 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3681 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3682#if 0
3683 RTRCPTR alignment2; /**< structure size alignment. */
3684#endif
3685 /** @} */
3686
3687 /** For saving stack space, the disassembler state is allocated here instead of
3688 * on the stack.
3689 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3690 union
3691 {
3692 /** The disassembler scratch space. */
3693 DISCPUSTATE DisState;
3694 /** Padding. */
3695 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3696 };
3697
3698 /** Count the number of pgm pool access handler calls. */
3699 uint64_t cPoolAccessHandler;
3700
3701 /** @name Release Statistics
3702 * @{ */
3703 /** The number of times the guest has switched mode since last reset or statistics reset. */
3704 STAMCOUNTER cGuestModeChanges;
3705 /** @} */
3706
3707#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3708 /** @name Statistics
3709 * @{ */
3710 /** RC: Pointer to the statistics. */
3711 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3712 /** RC: Which statistic this \#PF should be attributed to. */
3713 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3714 /** R0: Pointer to the statistics. */
3715 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3716 /** R0: Which statistic this \#PF should be attributed to. */
3717 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3718 /** R3: Pointer to the statistics. */
3719 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3720 /** Alignment padding. */
3721 RTR3PTR pPaddingR3;
3722 /** @} */
3723#endif /* VBOX_WITH_STATISTICS */
3724} PGMCPU;
3725/** Pointer to the per-cpu PGM data. */
3726typedef PGMCPU *PPGMCPU;
3727
3728
3729/** @name PGM::fSyncFlags Flags
3730 * @{
3731 */
3732/** Updates the virtual access handler state bit in PGMPAGE. */
3733#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3734/** Always sync CR3. */
3735#define PGM_SYNC_ALWAYS RT_BIT(1)
3736/** Check monitoring on next CR3 (re)load and invalidate page.
3737 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3738#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3739/** Check guest mapping in SyncCR3. */
3740#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3741/** Clear the page pool (a light weight flush). */
3742#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3743#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3744/** @} */
3745
3746
3747RT_C_DECLS_BEGIN
3748
3749int pgmLock(PVM pVM);
3750void pgmUnlock(PVM pVM);
3751
3752int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3753int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3754int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3755PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3756int pgmMapResolveConflicts(PVM pVM);
3757DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3758
3759void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3760bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3761void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3762int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3763DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3764#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3765void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3766#else
3767# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3768#endif
3769DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3770int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3771
3772int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3773int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3774int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3775int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3776int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3777void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3778int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3779int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3780int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3781int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3782int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3783int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3784int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3785VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3786VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3787int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3788
3789#ifdef IN_RING3
3790void pgmR3PhysRelinkRamRanges(PVM pVM);
3791int pgmR3PhysRamPreAllocate(PVM pVM);
3792int pgmR3PhysRamReset(PVM pVM);
3793int pgmR3PhysRomReset(PVM pVM);
3794int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3795int pgmR3PhysRamTerm(PVM pVM);
3796void pgmR3PhysRomTerm(PVM pVM);
3797
3798int pgmR3PoolInit(PVM pVM);
3799void pgmR3PoolRelocate(PVM pVM);
3800void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3801void pgmR3PoolReset(PVM pVM);
3802void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3803DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3804void pgmR3PoolWriteProtectPages(PVM pVM);
3805
3806#endif /* IN_RING3 */
3807#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3808int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3809int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3810# ifdef LOG_ENABLED
3811void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3812# else
3813void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3814# endif
3815#endif
3816int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3817 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3818
3819DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3820 PPPGMPOOLPAGE ppPage)
3821{
3822 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3823}
3824
3825void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3826void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3827int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3828void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3829PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3830PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3831int pgmPoolSyncCR3(PVMCPU pVCpu);
3832bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3833void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3834int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3835void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3836uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3837void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3838void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3839int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3840void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3841
3842void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3843void pgmPoolResetDirtyPages(PVM pVM);
3844void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3845
3846int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3847int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3848
3849void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3850void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3851int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3852int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3853
3854int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3855int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3856
3857int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3858int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3859int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3860int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3861
3862# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3863DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3864DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3865# endif
3866
3867RT_C_DECLS_END
3868
3869/** @} */
3870
3871#endif
3872
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