VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 36904

Last change on this file since 36904 was 36904, checked in by vboxsync, 14 years ago

Alignment fix.
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File size: 177.6 KB
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1/* $Id: PGMInternal.h 36904 2011-04-30 12:04:21Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef struct PGMPAGE
692{
693 /** The physical address and the Page ID. */
694 RTHCPHYS HCPhysAndPageID;
695 /** Combination of:
696 * - [0-7]: u2HandlerPhysStateY - the physical handler state
697 * (PGM_PAGE_HNDL_PHYS_STATE_*).
698 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
699 * (PGM_PAGE_HNDL_VIRT_STATE_*).
700 * - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
701 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
702 * - [15]: fWrittenToY - flag indicating that a write monitored page was
703 * written to when set.
704 * - [11-13]: 3 unused bits.
705 * @remarks Warning! All accesses to the bits are hardcoded.
706 *
707 * @todo Change this to a union with both bitfields, u8 and u accessors.
708 * That'll help deal with some of the hardcoded accesses.
709 *
710 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
711 * will make it possible to turn some of the 16-bit accesses into
712 * 32-bit ones, which may be efficient (stalls).
713 */
714 RTUINT16U u16MiscY;
715 /** The page state.
716 * Only 3 bits are really needed for this. */
717 uint16_t uStateY : 3;
718 /** The page type (PGMPAGETYPE).
719 * Only 3 bits are really needed for this. */
720 uint16_t uTypeY : 3;
721 /** PTE index for usage tracking (page pool). */
722 uint16_t uPteIdx : 10;
723 /** Usage tracking (page pool). */
724 uint16_t u16TrackingY;
725 /** The number of read locks on this page. */
726 uint8_t cReadLocksY;
727 /** The number of write locks on this page. */
728 uint8_t cWriteLocksY;
729} PGMPAGE;
730AssertCompileSize(PGMPAGE, 16);
731/** Pointer to a physical guest page. */
732typedef PGMPAGE *PPGMPAGE;
733/** Pointer to a const physical guest page. */
734typedef const PGMPAGE *PCPGMPAGE;
735/** Pointer to a physical guest page pointer. */
736typedef PPGMPAGE *PPPGMPAGE;
737
738
739/**
740 * Clears the page structure.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_CLEAR(pPage) \
744 do { \
745 (pPage)->HCPhysAndPageID = 0; \
746 (pPage)->uStateY = 0; \
747 (pPage)->uTypeY = 0; \
748 (pPage)->uPteIdx = 0; \
749 (pPage)->u16MiscY.u = 0; \
750 (pPage)->u16TrackingY = 0; \
751 (pPage)->cReadLocksY = 0; \
752 (pPage)->cWriteLocksY = 0; \
753 } while (0)
754
755/**
756 * Initializes the page structure.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760 do { \
761 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
764 (pPage)->uStateY = (_uState); \
765 (pPage)->uTypeY = (_uType); \
766 (pPage)->uPteIdx = 0; \
767 (pPage)->u16MiscY.u = 0; \
768 (pPage)->u16TrackingY = 0; \
769 (pPage)->cReadLocksY = 0; \
770 (pPage)->cWriteLocksY = 0; \
771 } while (0)
772
773/**
774 * Initializes the page structure of a ZERO page.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 * @param pVM The VM handle (for getting the zero page address).
777 * @param uType The page type (PGMPAGETYPE).
778 */
779#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
780 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
781
782
783/** @name The Page state, PGMPAGE::uStateY.
784 * @{ */
785/** The zero page.
786 * This is a per-VM page that's never ever mapped writable. */
787#define PGM_PAGE_STATE_ZERO 0
788/** A allocated page.
789 * This is a per-VM page allocated from the page pool (or wherever
790 * we get MMIO2 pages from if the type is MMIO2).
791 */
792#define PGM_PAGE_STATE_ALLOCATED 1
793/** A allocated page that's being monitored for writes.
794 * The shadow page table mappings are read-only. When a write occurs, the
795 * fWrittenTo member is set, the page remapped as read-write and the state
796 * moved back to allocated. */
797#define PGM_PAGE_STATE_WRITE_MONITORED 2
798/** The page is shared, aka. copy-on-write.
799 * This is a page that's shared with other VMs. */
800#define PGM_PAGE_STATE_SHARED 3
801/** The page is ballooned, so no longer available for this VM. */
802#define PGM_PAGE_STATE_BALLOONED 4
803/** @} */
804
805
806/**
807 * Gets the page state.
808 * @returns page state (PGM_PAGE_STATE_*).
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
812
813/**
814 * Sets the page state.
815 * @param pPage Pointer to the physical guest page tracking structure.
816 * @param _uState The new page state.
817 */
818#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
819
820
821/**
822 * Gets the host physical address of the guest page.
823 * @returns host physical address (RTHCPHYS).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
827
828/**
829 * Sets the host physical address of the guest page.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 * @param _HCPhys The new host physical address.
832 */
833#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
834 do { \
835 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
836 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
837 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
838 | (SetHCPhysTmp << (28-12)); \
839 } while (0)
840
841/**
842 * Get the Page ID.
843 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
847
848/**
849 * Sets the Page ID.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
853 do { \
854 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
855 | ((_idPage) & UINT32_C(0x0fffffff)); \
856 } while (0)
857
858/**
859 * Get the Chunk ID.
860 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
864
865/**
866 * Get the index of the page within the allocation chunk.
867 * @returns The page index.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
871
872/**
873 * Gets the page type.
874 * @returns The page type.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
878
879/**
880 * Sets the page type.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param _enmType The new page type (PGMPAGETYPE).
883 */
884#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
885
886/**
887 * Gets the page table index
888 * @returns The page table index.
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
892
893/**
894 * Sets the page table index
895 * @param pPage Pointer to the physical guest page tracking structure.
896 * @param iPte New page table index.
897 */
898#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
899
900/**
901 * Checks if the page is marked for MMIO.
902 * @returns true/false.
903 * @param pPage Pointer to the physical guest page tracking structure.
904 */
905#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
906
907/**
908 * Checks if the page is backed by the ZERO page.
909 * @returns true/false.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
913
914/**
915 * Checks if the page is backed by a SHARED page.
916 * @returns true/false.
917 * @param pPage Pointer to the physical guest page tracking structure.
918 */
919#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
920
921/**
922 * Checks if the page is ballooned.
923 * @returns true/false.
924 * @param pPage Pointer to the physical guest page tracking structure.
925 */
926#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
927
928/**
929 * Checks if the page is allocated.
930 * @returns true/false.
931 * @param pPage Pointer to the physical guest page tracking structure.
932 */
933#define PGM_PAGE_IS_ALLOCATED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ALLOCATED )
934
935/**
936 * Marks the page as written to (for GMM change monitoring).
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
940
941/**
942 * Clears the written-to indicator.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
946
947/**
948 * Checks if the page was marked as written-to.
949 * @returns true/false.
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
953
954/**
955 * Marks the page as dirty for FTM
956 * @param pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x04); } while (0)
959
960/**
961 * Clears the FTM dirty indicator
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
965
966/**
967 * Checks if the page was marked as dirty for FTM
968 * @returns true/false.
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
972
973
974/** @name PT usage values (PGMPAGE::u2PDEType).
975 *
976 * @{ */
977/** Either as a PT or PDE. */
978#define PGM_PAGE_PDE_TYPE_DONTCARE 0
979/** Must use a page table to map the range. */
980#define PGM_PAGE_PDE_TYPE_PT 1
981/** Can use a page directory entry to map the continuous range. */
982#define PGM_PAGE_PDE_TYPE_PDE 2
983/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
984#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
985/** @} */
986
987/**
988 * Set the PDE type of the page
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param uType PGM_PAGE_PDE_TYPE_*
991 */
992#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
993 do { \
994 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
995 | (((uType) & UINT8_C(0x03)) << 5); \
996 } while (0)
997
998/**
999 * Checks if the page was marked being part of a large page
1000 * @returns true/false.
1001 * @param pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1004
1005/** Enabled optimized access handler tests.
1006 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1007 * layout. When enabled, the compiler should normally generate more compact
1008 * code.
1009 */
1010#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1011
1012/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1013 *
1014 * @remarks The values are assigned in order of priority, so we can calculate
1015 * the correct state for a page with different handlers installed.
1016 * @{ */
1017/** No handler installed. */
1018#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1019/** Monitoring is temporarily disabled. */
1020#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1021/** Write access is monitored. */
1022#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1023/** All access is monitored. */
1024#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1025/** @} */
1026
1027/**
1028 * Gets the physical access handler state of a page.
1029 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1033 ( (pPage)->u16MiscY.au8[0] )
1034
1035/**
1036 * Sets the physical access handler state of a page.
1037 * @param pPage Pointer to the physical guest page tracking structure.
1038 * @param _uState The new state value.
1039 */
1040#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1041 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1042
1043/**
1044 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1045 * @returns true/false
1046 * @param pPage Pointer to the physical guest page tracking structure.
1047 */
1048#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1049 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1050
1051/**
1052 * Checks if the page has any active physical access handlers.
1053 * @returns true/false
1054 * @param pPage Pointer to the physical guest page tracking structure.
1055 */
1056#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1057 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1058
1059
1060/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1061 *
1062 * @remarks The values are assigned in order of priority, so we can calculate
1063 * the correct state for a page with different handlers installed.
1064 * @{ */
1065/** No handler installed. */
1066#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1067/* 1 is reserved so the lineup is identical with the physical ones. */
1068/** Write access is monitored. */
1069#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1070/** All access is monitored. */
1071#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1072/** @} */
1073
1074/**
1075 * Gets the virtual access handler state of a page.
1076 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1080
1081/**
1082 * Sets the virtual access handler state of a page.
1083 * @param pPage Pointer to the physical guest page tracking structure.
1084 * @param _uState The new state value.
1085 */
1086#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1087 do { \
1088 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1089 | ((_uState) & UINT8_C(0x03)); \
1090 } while (0)
1091
1092/**
1093 * Checks if the page has any virtual access handlers.
1094 * @returns true/false
1095 * @param pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1098 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1099
1100/**
1101 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1102 * virtual handlers.
1103 * @returns true/false
1104 * @param pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1107 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1108
1109
1110/**
1111 * Checks if the page has any access handlers, including temporarily disabled ones.
1112 * @returns true/false
1113 * @param pPage Pointer to the physical guest page tracking structure.
1114 */
1115#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1116# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1117 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1118#else
1119# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1120 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1121 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1122#endif
1123
1124/**
1125 * Checks if the page has any active access handlers.
1126 * @returns true/false
1127 * @param pPage Pointer to the physical guest page tracking structure.
1128 */
1129#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1130# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1131 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1132#else
1133# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1134 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1135 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1136#endif
1137
1138/**
1139 * Checks if the page has any active access handlers catching all accesses.
1140 * @returns true/false
1141 * @param pPage Pointer to the physical guest page tracking structure.
1142 */
1143#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1144# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1145 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1146 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1147#else
1148# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1149 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1150 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1151#endif
1152
1153
1154/** @def PGM_PAGE_GET_TRACKING
1155 * Gets the packed shadow page pool tracking data associated with a guest page.
1156 * @returns uint16_t containing the data.
1157 * @param pPage Pointer to the physical guest page tracking structure.
1158 */
1159#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1160
1161/** @def PGM_PAGE_SET_TRACKING
1162 * Sets the packed shadow page pool tracking data associated with a guest page.
1163 * @param pPage Pointer to the physical guest page tracking structure.
1164 * @param u16TrackingData The tracking data to store.
1165 */
1166#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1167 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1168
1169/** @def PGM_PAGE_GET_TD_CREFS
1170 * Gets the @a cRefs tracking data member.
1171 * @returns cRefs.
1172 * @param pPage Pointer to the physical guest page tracking structure.
1173 */
1174#define PGM_PAGE_GET_TD_CREFS(pPage) \
1175 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1176
1177/** @def PGM_PAGE_GET_TD_IDX
1178 * Gets the @a idx tracking data member.
1179 * @returns idx.
1180 * @param pPage Pointer to the physical guest page tracking structure.
1181 */
1182#define PGM_PAGE_GET_TD_IDX(pPage) \
1183 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1184
1185
1186/** Max number of locks on a page. */
1187#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1188
1189/** Get the read lock count.
1190 * @returns count.
1191 * @param pPage Pointer to the physical guest page tracking structure.
1192 */
1193#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1194
1195/** Get the write lock count.
1196 * @returns count.
1197 * @param pPage Pointer to the physical guest page tracking structure.
1198 */
1199#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1200
1201/** Decrement the read lock counter.
1202 * @param pPage Pointer to the physical guest page tracking structure.
1203 */
1204#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1205
1206/** Decrement the write lock counter.
1207 * @param pPage Pointer to the physical guest page tracking structure.
1208 */
1209#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1210
1211/** Increment the read lock counter.
1212 * @param pPage Pointer to the physical guest page tracking structure.
1213 */
1214#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1215
1216/** Increment the write lock counter.
1217 * @param pPage Pointer to the physical guest page tracking structure.
1218 */
1219#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1220
1221
1222#if 0
1223/** Enables sanity checking of write monitoring using CRC-32. */
1224# define PGMLIVESAVERAMPAGE_WITH_CRC32
1225#endif
1226
1227/**
1228 * Per page live save tracking data.
1229 */
1230typedef struct PGMLIVESAVERAMPAGE
1231{
1232 /** Number of times it has been dirtied. */
1233 uint32_t cDirtied : 24;
1234 /** Whether it is currently dirty. */
1235 uint32_t fDirty : 1;
1236 /** Ignore the page.
1237 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1238 * deal with these after pausing the VM and DevPCI have said it bit about
1239 * remappings. */
1240 uint32_t fIgnore : 1;
1241 /** Was a ZERO page last time around. */
1242 uint32_t fZero : 1;
1243 /** Was a SHARED page last time around. */
1244 uint32_t fShared : 1;
1245 /** Whether the page is/was write monitored in a previous pass. */
1246 uint32_t fWriteMonitored : 1;
1247 /** Whether the page is/was write monitored earlier in this pass. */
1248 uint32_t fWriteMonitoredJustNow : 1;
1249 /** Bits reserved for future use. */
1250 uint32_t u2Reserved : 2;
1251#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1252 /** CRC-32 for the page. This is for internal consistency checks. */
1253 uint32_t u32Crc;
1254#endif
1255} PGMLIVESAVERAMPAGE;
1256#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1258#else
1259AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1260#endif
1261/** Pointer to the per page live save tracking data. */
1262typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1263
1264/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1265#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1266
1267
1268/** Enables the RAM range search trees. */
1269#define PGM_USE_RAMRANGE_SEARCH_TREES
1270
1271/**
1272 * RAM range for GC Phys to HC Phys conversion.
1273 *
1274 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1275 * conversions too, but we'll let MM handle that for now.
1276 *
1277 * This structure is used by linked lists in both GC and HC.
1278 */
1279typedef struct PGMRAMRANGE
1280{
1281 /** Start of the range. Page aligned. */
1282 RTGCPHYS GCPhys;
1283 /** Size of the range. (Page aligned of course). */
1284 RTGCPHYS cb;
1285 /** Pointer to the next RAM range - for R3. */
1286 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1287 /** Pointer to the next RAM range - for R0. */
1288 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1289 /** Pointer to the next RAM range - for RC. */
1290 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1291 /** PGM_RAM_RANGE_FLAGS_* flags. */
1292 uint32_t fFlags;
1293 /** Last address in the range (inclusive). Page aligned (-1). */
1294 RTGCPHYS GCPhysLast;
1295 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1296 R3PTRTYPE(void *) pvR3;
1297 /** Live save per page tracking data. */
1298 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1299 /** The range description. */
1300 R3PTRTYPE(const char *) pszDesc;
1301 /** Pointer to self - R0 pointer. */
1302 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1303 /** Pointer to self - RC pointer. */
1304 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1305
1306#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1307 /** Pointer to the left search three node - ring-3 context. */
1308 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1309 /** Pointer to the right search three node - ring-3 context. */
1310 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1311 /** Pointer to the left search three node - ring-0 context. */
1312 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1313 /** Pointer to the right search three node - ring-0 context. */
1314 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1315 /** Pointer to the left search three node - raw-mode context. */
1316 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1317 /** Pointer to the right search three node - raw-mode context. */
1318 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1319#endif
1320
1321 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1322#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1323 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 3 : 3];
1324#else
1325 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1326#endif
1327 /** Array of physical guest page tracking structures. */
1328 PGMPAGE aPages[1];
1329} PGMRAMRANGE;
1330/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1331typedef PGMRAMRANGE *PPGMRAMRANGE;
1332
1333/** @name PGMRAMRANGE::fFlags
1334 * @{ */
1335/** The RAM range is floating around as an independent guest mapping. */
1336#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1337/** Ad hoc RAM range for an ROM mapping. */
1338#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1339/** Ad hoc RAM range for an MMIO mapping. */
1340#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1341/** Ad hoc RAM range for an MMIO2 mapping. */
1342#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1343/** @} */
1344
1345/** Tests if a RAM range is an ad hoc one or not.
1346 * @returns true/false.
1347 * @param pRam The RAM range.
1348 */
1349#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1350 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1351
1352/** The number of entries in the RAM range TLBs (there is one for each
1353 * context). Must be a power of two. */
1354#define PGM_RAMRANGE_TLB_ENTRIES 8
1355
1356/**
1357 * Calculates the RAM range TLB index for the physical address.
1358 *
1359 * @returns RAM range TLB index.
1360 * @param GCPhys The guest physical address.
1361 */
1362#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1363
1364
1365
1366/**
1367 * Per page tracking structure for ROM image.
1368 *
1369 * A ROM image may have a shadow page, in which case we may have two pages
1370 * backing it. This structure contains the PGMPAGE for both while
1371 * PGMRAMRANGE have a copy of the active one. It is important that these
1372 * aren't out of sync in any regard other than page pool tracking data.
1373 */
1374typedef struct PGMROMPAGE
1375{
1376 /** The page structure for the virgin ROM page. */
1377 PGMPAGE Virgin;
1378 /** The page structure for the shadow RAM page. */
1379 PGMPAGE Shadow;
1380 /** The current protection setting. */
1381 PGMROMPROT enmProt;
1382 /** Live save status information. Makes use of unused alignment space. */
1383 struct
1384 {
1385 /** The previous protection value. */
1386 uint8_t u8Prot;
1387 /** Written to flag set by the handler. */
1388 bool fWrittenTo;
1389 /** Whether the shadow page is dirty or not. */
1390 bool fDirty;
1391 /** Whether it was dirtied in the recently. */
1392 bool fDirtiedRecently;
1393 } LiveSave;
1394} PGMROMPAGE;
1395AssertCompileSizeAlignment(PGMROMPAGE, 8);
1396/** Pointer to a ROM page tracking structure. */
1397typedef PGMROMPAGE *PPGMROMPAGE;
1398
1399
1400/**
1401 * A registered ROM image.
1402 *
1403 * This is needed to keep track of ROM image since they generally intrude
1404 * into a PGMRAMRANGE. It also keeps track of additional info like the
1405 * two page sets (read-only virgin and read-write shadow), the current
1406 * state of each page.
1407 *
1408 * Because access handlers cannot easily be executed in a different
1409 * context, the ROM ranges needs to be accessible and in all contexts.
1410 */
1411typedef struct PGMROMRANGE
1412{
1413 /** Pointer to the next range - R3. */
1414 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1415 /** Pointer to the next range - R0. */
1416 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1417 /** Pointer to the next range - RC. */
1418 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1419 /** Pointer alignment */
1420 RTRCPTR RCPtrAlignment;
1421 /** Address of the range. */
1422 RTGCPHYS GCPhys;
1423 /** Address of the last byte in the range. */
1424 RTGCPHYS GCPhysLast;
1425 /** Size of the range. */
1426 RTGCPHYS cb;
1427 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1428 uint32_t fFlags;
1429 /** The saved state range ID. */
1430 uint8_t idSavedState;
1431 /** Alignment padding. */
1432 uint8_t au8Alignment[3];
1433 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1434 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1435 /** The size bits pvOriginal points to. */
1436 uint32_t cbOriginal;
1437 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1438 * This is used for strictness checks. */
1439 R3PTRTYPE(const void *) pvOriginal;
1440 /** The ROM description. */
1441 R3PTRTYPE(const char *) pszDesc;
1442 /** The per page tracking structures. */
1443 PGMROMPAGE aPages[1];
1444} PGMROMRANGE;
1445/** Pointer to a ROM range. */
1446typedef PGMROMRANGE *PPGMROMRANGE;
1447
1448
1449/**
1450 * Live save per page data for an MMIO2 page.
1451 *
1452 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1453 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1454 * CRC-32 for detecting changes as well as special handling of zero pages. This
1455 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1456 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1457 * because of speed (2.5x and 6x slower).)
1458 *
1459 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1460 * save but normally is disabled. Since we can write monitor guest
1461 * accesses on our own, we only need this for host accesses. Shouldn't be
1462 * too difficult for DevVGA, VMMDev might be doable, the planned
1463 * networking fun will be fun since it involves ring-0.
1464 */
1465typedef struct PGMLIVESAVEMMIO2PAGE
1466{
1467 /** Set if the page is considered dirty. */
1468 bool fDirty;
1469 /** The number of scans this page has remained unchanged for.
1470 * Only updated for dirty pages. */
1471 uint8_t cUnchangedScans;
1472 /** Whether this page was zero at the last scan. */
1473 bool fZero;
1474 /** Alignment padding. */
1475 bool fReserved;
1476 /** CRC-32 for the first half of the page.
1477 * This is used together with u32CrcH2 to quickly detect changes in the page
1478 * during the non-final passes. */
1479 uint32_t u32CrcH1;
1480 /** CRC-32 for the second half of the page. */
1481 uint32_t u32CrcH2;
1482 /** SHA-1 for the saved page.
1483 * This is used in the final pass to skip pages without changes. */
1484 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1485} PGMLIVESAVEMMIO2PAGE;
1486/** Pointer to a live save status data for an MMIO2 page. */
1487typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1488
1489/**
1490 * A registered MMIO2 (= Device RAM) range.
1491 *
1492 * There are a few reason why we need to keep track of these
1493 * registrations. One of them is the deregistration & cleanup stuff,
1494 * while another is that the PGMRAMRANGE associated with such a region may
1495 * have to be removed from the ram range list.
1496 *
1497 * Overlapping with a RAM range has to be 100% or none at all. The pages
1498 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1499 * will be raised if a partial overlap or an overlap of ROM pages is
1500 * encountered. On an overlap we will free all the existing RAM pages and
1501 * put in the ram range pages instead.
1502 */
1503typedef struct PGMMMIO2RANGE
1504{
1505 /** The owner of the range. (a device) */
1506 PPDMDEVINSR3 pDevInsR3;
1507 /** Pointer to the ring-3 mapping of the allocation. */
1508 RTR3PTR pvR3;
1509 /** Pointer to the next range - R3. */
1510 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1511 /** Whether it's mapped or not. */
1512 bool fMapped;
1513 /** Whether it's overlapping or not. */
1514 bool fOverlapping;
1515 /** The PCI region number.
1516 * @remarks This ASSUMES that nobody will ever really need to have multiple
1517 * PCI devices with matching MMIO region numbers on a single device. */
1518 uint8_t iRegion;
1519 /** The saved state range ID. */
1520 uint8_t idSavedState;
1521 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1522 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1523 /** Live save per page tracking data. */
1524 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1525 /** The associated RAM range. */
1526 PGMRAMRANGE RamRange;
1527} PGMMMIO2RANGE;
1528/** Pointer to a MMIO2 range. */
1529typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1530
1531
1532
1533
1534/**
1535 * PGMPhysRead/Write cache entry
1536 */
1537typedef struct PGMPHYSCACHEENTRY
1538{
1539 /** R3 pointer to physical page. */
1540 R3PTRTYPE(uint8_t *) pbR3;
1541 /** GC Physical address for cache entry */
1542 RTGCPHYS GCPhys;
1543#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1544 RTGCPHYS u32Padding0; /**< alignment padding. */
1545#endif
1546} PGMPHYSCACHEENTRY;
1547
1548/**
1549 * PGMPhysRead/Write cache to reduce REM memory access overhead
1550 */
1551typedef struct PGMPHYSCACHE
1552{
1553 /** Bitmap of valid cache entries */
1554 uint64_t aEntries;
1555 /** Cache entries */
1556 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1557} PGMPHYSCACHE;
1558
1559
1560/** Pointer to an allocation chunk ring-3 mapping. */
1561typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1562/** Pointer to an allocation chunk ring-3 mapping pointer. */
1563typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1564
1565/**
1566 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1567 *
1568 * The primary tree (Core) uses the chunk id as key.
1569 */
1570typedef struct PGMCHUNKR3MAP
1571{
1572 /** The key is the chunk id. */
1573 AVLU32NODECORE Core;
1574 /** The current age thingy. */
1575 uint32_t iAge;
1576 /** The current reference count. */
1577 uint32_t volatile cRefs;
1578 /** The current permanent reference count. */
1579 uint32_t volatile cPermRefs;
1580 /** The mapping address. */
1581 void *pv;
1582} PGMCHUNKR3MAP;
1583
1584/**
1585 * Allocation chunk ring-3 mapping TLB entry.
1586 */
1587typedef struct PGMCHUNKR3MAPTLBE
1588{
1589 /** The chunk id. */
1590 uint32_t volatile idChunk;
1591#if HC_ARCH_BITS == 64
1592 uint32_t u32Padding; /**< alignment padding. */
1593#endif
1594 /** The chunk map. */
1595#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1596 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1597#else
1598 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1599#endif
1600} PGMCHUNKR3MAPTLBE;
1601/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1602typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1603
1604/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1605 * @remark Must be a power of two value. */
1606#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1607
1608/**
1609 * Allocation chunk ring-3 mapping TLB.
1610 *
1611 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1612 * At first glance this might look kinda odd since AVL trees are
1613 * supposed to give the most optimal lookup times of all trees
1614 * due to their balancing. However, take a tree with 1023 nodes
1615 * in it, that's 10 levels, meaning that most searches has to go
1616 * down 9 levels before they find what they want. This isn't fast
1617 * compared to a TLB hit. There is the factor of cache misses,
1618 * and of course the problem with trees and branch prediction.
1619 * This is why we use TLBs in front of most of the trees.
1620 *
1621 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1622 * difficult when we switch to the new inlined AVL trees (from kStuff).
1623 */
1624typedef struct PGMCHUNKR3MAPTLB
1625{
1626 /** The TLB entries. */
1627 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1628} PGMCHUNKR3MAPTLB;
1629
1630/**
1631 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1632 * @returns Chunk TLB index.
1633 * @param idChunk The Chunk ID.
1634 */
1635#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1636
1637
1638/**
1639 * Ring-3 guest page mapping TLB entry.
1640 * @remarks used in ring-0 as well at the moment.
1641 */
1642typedef struct PGMPAGER3MAPTLBE
1643{
1644 /** Address of the page. */
1645 RTGCPHYS volatile GCPhys;
1646 /** The guest page. */
1647#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1648 R3PTRTYPE(PPGMPAGE) volatile pPage;
1649#else
1650 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1651#endif
1652 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1653#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1654 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1655#else
1656 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1657#endif
1658 /** The address */
1659#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1660 R3PTRTYPE(void *) volatile pv;
1661#else
1662 R3R0PTRTYPE(void *) volatile pv;
1663#endif
1664#if HC_ARCH_BITS == 32
1665 uint32_t u32Padding; /**< alignment padding. */
1666#endif
1667} PGMPAGER3MAPTLBE;
1668/** Pointer to an entry in the HC physical TLB. */
1669typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1670
1671
1672/** The number of entries in the ring-3 guest page mapping TLB.
1673 * @remarks The value must be a power of two. */
1674#define PGM_PAGER3MAPTLB_ENTRIES 256
1675
1676/**
1677 * Ring-3 guest page mapping TLB.
1678 * @remarks used in ring-0 as well at the moment.
1679 */
1680typedef struct PGMPAGER3MAPTLB
1681{
1682 /** The TLB entries. */
1683 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1684} PGMPAGER3MAPTLB;
1685/** Pointer to the ring-3 guest page mapping TLB. */
1686typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1687
1688/**
1689 * Calculates the index of the TLB entry for the specified guest page.
1690 * @returns Physical TLB index.
1691 * @param GCPhys The guest physical address.
1692 */
1693#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1694
1695
1696/**
1697 * Raw-mode context dynamic mapping cache entry.
1698 *
1699 * Because of raw-mode context being reloctable and all relocations are applied
1700 * in ring-3, this has to be defined here and be RC specific.
1701 *
1702 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1703 */
1704typedef struct PGMRCDYNMAPENTRY
1705{
1706 /** The physical address of the currently mapped page.
1707 * This is duplicate for three reasons: cache locality, cache policy of the PT
1708 * mappings and sanity checks. */
1709 RTHCPHYS HCPhys;
1710 /** Pointer to the page. */
1711 RTRCPTR pvPage;
1712 /** The number of references. */
1713 int32_t volatile cRefs;
1714 /** PTE pointer union. */
1715 struct PGMRCDYNMAPENTRY_PPTE
1716 {
1717 /** PTE pointer, 32-bit legacy version. */
1718 RCPTRTYPE(PX86PTE) pLegacy;
1719 /** PTE pointer, PAE version. */
1720 RCPTRTYPE(PX86PTEPAE) pPae;
1721 } uPte;
1722} PGMRCDYNMAPENTRY;
1723/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1724typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1725
1726
1727/**
1728 * Dynamic mapping cache for the raw-mode context.
1729 *
1730 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1731 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1732 * so that we can perform relocations from PGMR3Relocate. This has the
1733 * consequence that we must have separate ring-0 and raw-mode context versions
1734 * of this struct even if they share the basic elements.
1735 *
1736 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1737 */
1738typedef struct PGMRCDYNMAP
1739{
1740 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1741 uint32_t u32Magic;
1742 /** Array for tracking and managing the pages. */
1743 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1744 /** The cache size given as a number of pages. */
1745 uint32_t cPages;
1746 /** The current load.
1747 * This does not include guard pages. */
1748 uint32_t cLoad;
1749 /** The max load ever.
1750 * This is maintained to get trigger adding of more mapping space. */
1751 uint32_t cMaxLoad;
1752 /** The number of guard pages. */
1753 uint32_t cGuardPages;
1754 /** The number of users (protected by hInitLock). */
1755 uint32_t cUsers;
1756} PGMRCDYNMAP;
1757/** Pointer to the dynamic cache for the raw-mode context. */
1758typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1759
1760
1761/**
1762 * Mapping cache usage set entry.
1763 *
1764 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1765 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1766 * cache. If it's extended to include ring-3, well, then something
1767 * will have be changed here...
1768 */
1769typedef struct PGMMAPSETENTRY
1770{
1771 /** Pointer to the page. */
1772#ifndef IN_RC
1773 RTR0PTR pvPage;
1774#else
1775 RTRCPTR pvPage;
1776# if HC_ARCH_BITS == 64
1777 uint32_t u32Alignment2;
1778# endif
1779#endif
1780 /** The mapping cache index. */
1781 uint16_t iPage;
1782 /** The number of references.
1783 * The max is UINT16_MAX - 1. */
1784 uint16_t cRefs;
1785 /** The number inlined references.
1786 * The max is UINT16_MAX - 1. */
1787 uint16_t cInlinedRefs;
1788 /** Unreferences. */
1789 uint16_t cUnrefs;
1790
1791#if HC_ARCH_BITS == 32
1792 uint32_t u32Alignment1;
1793#endif
1794 /** The physical address for this entry. */
1795 RTHCPHYS HCPhys;
1796} PGMMAPSETENTRY;
1797AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1798AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1799/** Pointer to a mapping cache usage set entry. */
1800typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1801
1802/**
1803 * Mapping cache usage set.
1804 *
1805 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1806 * done during exits / traps. The set is
1807 */
1808typedef struct PGMMAPSET
1809{
1810 /** The number of occupied entries.
1811 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1812 * dynamic mappings. */
1813 uint32_t cEntries;
1814 /** The start of the current subset.
1815 * This is UINT32_MAX if no subset is currently open. */
1816 uint32_t iSubset;
1817 /** The index of the current CPU, only valid if the set is open. */
1818 int32_t iCpu;
1819 uint32_t alignment;
1820 /** The entries. */
1821 PGMMAPSETENTRY aEntries[64];
1822 /** HCPhys -> iEntry fast lookup table.
1823 * Use PGMMAPSET_HASH for hashing.
1824 * The entries may or may not be valid, check against cEntries. */
1825 uint8_t aiHashTable[128];
1826} PGMMAPSET;
1827AssertCompileSizeAlignment(PGMMAPSET, 8);
1828/** Pointer to the mapping cache set. */
1829typedef PGMMAPSET *PPGMMAPSET;
1830
1831/** PGMMAPSET::cEntries value for a closed set. */
1832#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1833
1834/** Hash function for aiHashTable. */
1835#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1836
1837
1838/** @name Context neutral page mapper TLB.
1839 *
1840 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1841 * code is writting in a kind of context neutral way. Time will show whether
1842 * this actually makes sense or not...
1843 *
1844 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1845 * context ends up using a global mapping cache on some platforms
1846 * (darwin).
1847 *
1848 * @{ */
1849/** @typedef PPGMPAGEMAPTLB
1850 * The page mapper TLB pointer type for the current context. */
1851/** @typedef PPGMPAGEMAPTLB
1852 * The page mapper TLB entry pointer type for the current context. */
1853/** @typedef PPGMPAGEMAPTLB
1854 * The page mapper TLB entry pointer pointer type for the current context. */
1855/** @def PGM_PAGEMAPTLB_ENTRIES
1856 * The number of TLB entries in the page mapper TLB for the current context. */
1857/** @def PGM_PAGEMAPTLB_IDX
1858 * Calculate the TLB index for a guest physical address.
1859 * @returns The TLB index.
1860 * @param GCPhys The guest physical address. */
1861/** @typedef PPGMPAGEMAP
1862 * Pointer to a page mapper unit for current context. */
1863/** @typedef PPPGMPAGEMAP
1864 * Pointer to a page mapper unit pointer for current context. */
1865#ifdef IN_RC
1866// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1867// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1868// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1869# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1870# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1871 typedef void * PPGMPAGEMAP;
1872 typedef void ** PPPGMPAGEMAP;
1873//#elif IN_RING0
1874// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1875// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1876// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1877//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1878//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1879// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1880// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1881#else
1882 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1883 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1884 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1885# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1886# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1887 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1888 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1889#endif
1890/** @} */
1891
1892
1893/** @name PGM Pool Indexes.
1894 * Aka. the unique shadow page identifier.
1895 * @{ */
1896/** NIL page pool IDX. */
1897#define NIL_PGMPOOL_IDX 0
1898/** The first normal index. */
1899#define PGMPOOL_IDX_FIRST_SPECIAL 1
1900/** Page directory (32-bit root). */
1901#define PGMPOOL_IDX_PD 1
1902/** Page Directory Pointer Table (PAE root). */
1903#define PGMPOOL_IDX_PDPT 2
1904/** AMD64 CR3 level index.*/
1905#define PGMPOOL_IDX_AMD64_CR3 3
1906/** Nested paging root.*/
1907#define PGMPOOL_IDX_NESTED_ROOT 4
1908/** The first normal index. */
1909#define PGMPOOL_IDX_FIRST 5
1910/** The last valid index. (inclusive, 14 bits) */
1911#define PGMPOOL_IDX_LAST 0x3fff
1912/** @} */
1913
1914/** The NIL index for the parent chain. */
1915#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1916#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1917
1918/**
1919 * Node in the chain linking a shadowed page to it's parent (user).
1920 */
1921#pragma pack(1)
1922typedef struct PGMPOOLUSER
1923{
1924 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1925 uint16_t iNext;
1926 /** The user page index. */
1927 uint16_t iUser;
1928 /** Index into the user table. */
1929 uint32_t iUserTable;
1930} PGMPOOLUSER, *PPGMPOOLUSER;
1931typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1932#pragma pack()
1933
1934
1935/** The NIL index for the phys ext chain. */
1936#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1937/** The NIL pte index for a phys ext chain slot. */
1938#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1939
1940/**
1941 * Node in the chain of physical cross reference extents.
1942 * @todo Calling this an 'extent' is not quite right, find a better name.
1943 * @todo find out the optimal size of the aidx array
1944 */
1945#pragma pack(1)
1946typedef struct PGMPOOLPHYSEXT
1947{
1948 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1949 uint16_t iNext;
1950 /** Alignment. */
1951 uint16_t u16Align;
1952 /** The user page index. */
1953 uint16_t aidx[3];
1954 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1955 uint16_t apte[3];
1956} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1957typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1958#pragma pack()
1959
1960
1961/**
1962 * The kind of page that's being shadowed.
1963 */
1964typedef enum PGMPOOLKIND
1965{
1966 /** The virtual invalid 0 entry. */
1967 PGMPOOLKIND_INVALID = 0,
1968 /** The entry is free (=unused). */
1969 PGMPOOLKIND_FREE,
1970
1971 /** Shw: 32-bit page table; Gst: no paging */
1972 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1973 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1974 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1975 /** Shw: 32-bit page table; Gst: 4MB page. */
1976 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1977 /** Shw: PAE page table; Gst: no paging */
1978 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1979 /** Shw: PAE page table; Gst: 32-bit page table. */
1980 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1981 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1982 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1983 /** Shw: PAE page table; Gst: PAE page table. */
1984 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1985 /** Shw: PAE page table; Gst: 2MB page. */
1986 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1987
1988 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1989 PGMPOOLKIND_32BIT_PD,
1990 /** Shw: 32-bit page directory. Gst: no paging. */
1991 PGMPOOLKIND_32BIT_PD_PHYS,
1992 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1993 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1994 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1995 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1996 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1997 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1998 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1999 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2000 /** Shw: PAE page directory; Gst: PAE page directory. */
2001 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2002 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2003 PGMPOOLKIND_PAE_PD_PHYS,
2004
2005 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2006 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2007 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2008 PGMPOOLKIND_PAE_PDPT,
2009 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2010 PGMPOOLKIND_PAE_PDPT_PHYS,
2011
2012 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2013 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2014 /** Shw: 64-bit page directory pointer table; Gst: no paging */
2015 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2016 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2017 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2018 /** Shw: 64-bit page directory table; Gst: no paging */
2019 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2020
2021 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2022 PGMPOOLKIND_64BIT_PML4,
2023
2024 /** Shw: EPT page directory pointer table; Gst: no paging */
2025 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2026 /** Shw: EPT page directory table; Gst: no paging */
2027 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2028 /** Shw: EPT page table; Gst: no paging */
2029 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2030
2031 /** Shw: Root Nested paging table. */
2032 PGMPOOLKIND_ROOT_NESTED,
2033
2034 /** The last valid entry. */
2035 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2036} PGMPOOLKIND;
2037
2038/**
2039 * The access attributes of the page; only applies to big pages.
2040 */
2041typedef enum
2042{
2043 PGMPOOLACCESS_DONTCARE = 0,
2044 PGMPOOLACCESS_USER_RW,
2045 PGMPOOLACCESS_USER_R,
2046 PGMPOOLACCESS_USER_RW_NX,
2047 PGMPOOLACCESS_USER_R_NX,
2048 PGMPOOLACCESS_SUPERVISOR_RW,
2049 PGMPOOLACCESS_SUPERVISOR_R,
2050 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2051 PGMPOOLACCESS_SUPERVISOR_R_NX
2052} PGMPOOLACCESS;
2053
2054/**
2055 * The tracking data for a page in the pool.
2056 */
2057typedef struct PGMPOOLPAGE
2058{
2059 /** AVL node code with the (R3) physical address of this page. */
2060 AVLOHCPHYSNODECORE Core;
2061 /** Pointer to the R3 mapping of the page. */
2062#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2063 R3PTRTYPE(void *) pvPageR3;
2064#else
2065 R3R0PTRTYPE(void *) pvPageR3;
2066#endif
2067 /** The guest physical address. */
2068#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2069 uint32_t Alignment0;
2070#endif
2071 RTGCPHYS GCPhys;
2072
2073 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2074 RTGCPTR pvLastAccessHandlerRip;
2075 RTGCPTR pvLastAccessHandlerFault;
2076 uint64_t cLastAccessHandlerCount;
2077
2078 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2079 uint8_t enmKind;
2080 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2081 uint8_t enmAccess;
2082 /** The index of this page. */
2083 uint16_t idx;
2084 /** The next entry in the list this page currently resides in.
2085 * It's either in the free list or in the GCPhys hash. */
2086 uint16_t iNext;
2087 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2088 uint16_t iUserHead;
2089 /** The number of present entries. */
2090 uint16_t cPresent;
2091 /** The first entry in the table which is present. */
2092 uint16_t iFirstPresent;
2093 /** The number of modifications to the monitored page. */
2094 uint16_t cModifications;
2095 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2096 uint16_t iModifiedNext;
2097 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2098 uint16_t iModifiedPrev;
2099 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2100 uint16_t iMonitoredNext;
2101 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2102 uint16_t iMonitoredPrev;
2103 /** The next page in the age list. */
2104 uint16_t iAgeNext;
2105 /** The previous page in the age list. */
2106 uint16_t iAgePrev;
2107 /** Used to indicate that the page is zeroed. */
2108 bool fZeroed;
2109 /** Used to indicate that a PT has non-global entries. */
2110 bool fSeenNonGlobal;
2111 /** Used to indicate that we're monitoring writes to the guest page. */
2112 bool fMonitored;
2113 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2114 * (All pages are in the age list.) */
2115 bool fCached;
2116 /** This is used by the R3 access handlers when invoked by an async thread.
2117 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2118 bool volatile fReusedFlushPending;
2119 /** Used to mark the page as dirty (write monitoring is temporarily
2120 * off). */
2121 bool fDirty;
2122
2123 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2124 uint32_t cLocked;
2125 uint32_t idxDirty;
2126 RTGCPTR pvDirtyFault;
2127} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2128/** Pointer to a const pool page. */
2129typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2130
2131
2132/** The hash table size. */
2133# define PGMPOOL_HASH_SIZE 0x40
2134/** The hash function. */
2135# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2136
2137
2138/**
2139 * The shadow page pool instance data.
2140 *
2141 * It's all one big allocation made at init time, except for the
2142 * pages that is. The user nodes follows immediately after the
2143 * page structures.
2144 */
2145typedef struct PGMPOOL
2146{
2147 /** The VM handle - R3 Ptr. */
2148 PVMR3 pVMR3;
2149 /** The VM handle - R0 Ptr. */
2150 PVMR0 pVMR0;
2151 /** The VM handle - RC Ptr. */
2152 PVMRC pVMRC;
2153 /** The max pool size. This includes the special IDs. */
2154 uint16_t cMaxPages;
2155 /** The current pool size. */
2156 uint16_t cCurPages;
2157 /** The head of the free page list. */
2158 uint16_t iFreeHead;
2159 /* Padding. */
2160 uint16_t u16Padding;
2161 /** Head of the chain of free user nodes. */
2162 uint16_t iUserFreeHead;
2163 /** The number of user nodes we've allocated. */
2164 uint16_t cMaxUsers;
2165 /** The number of present page table entries in the entire pool. */
2166 uint32_t cPresent;
2167 /** Pointer to the array of user nodes - RC pointer. */
2168 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2169 /** Pointer to the array of user nodes - R3 pointer. */
2170 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2171 /** Pointer to the array of user nodes - R0 pointer. */
2172 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2173 /** Head of the chain of free phys ext nodes. */
2174 uint16_t iPhysExtFreeHead;
2175 /** The number of user nodes we've allocated. */
2176 uint16_t cMaxPhysExts;
2177 /** Pointer to the array of physical xref extent - RC pointer. */
2178 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2179 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2180 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2181 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2182 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2183 /** Hash table for GCPhys addresses. */
2184 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2185 /** The head of the age list. */
2186 uint16_t iAgeHead;
2187 /** The tail of the age list. */
2188 uint16_t iAgeTail;
2189 /** Set if the cache is enabled. */
2190 bool fCacheEnabled;
2191 /** Alignment padding. */
2192 bool afPadding1[3];
2193 /** Head of the list of modified pages. */
2194 uint16_t iModifiedHead;
2195 /** The current number of modified pages. */
2196 uint16_t cModifiedPages;
2197 /** Access handler, RC. */
2198 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2199 /** Access handler, R0. */
2200 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2201 /** Access handler, R3. */
2202 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2203 /** The access handler description (R3 ptr). */
2204 R3PTRTYPE(const char *) pszAccessHandler;
2205# if HC_ARCH_BITS == 32
2206 /** Alignment padding. */
2207 uint32_t u32Padding2;
2208# endif
2209 /* Next available slot. */
2210 uint32_t idxFreeDirtyPage;
2211 /* Number of active dirty pages. */
2212 uint32_t cDirtyPages;
2213 /* Array of current dirty pgm pool page indices. */
2214 struct
2215 {
2216 uint16_t uIdx;
2217 uint16_t Alignment[3];
2218 uint64_t aPage[512];
2219 } aDirtyPages[16];
2220 /** The number of pages currently in use. */
2221 uint16_t cUsedPages;
2222#ifdef VBOX_WITH_STATISTICS
2223 /** The high water mark for cUsedPages. */
2224 uint16_t cUsedPagesHigh;
2225 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2226 /** Profiling pgmPoolAlloc(). */
2227 STAMPROFILEADV StatAlloc;
2228 /** Profiling pgmR3PoolClearDoIt(). */
2229 STAMPROFILE StatClearAll;
2230 /** Profiling pgmR3PoolReset(). */
2231 STAMPROFILE StatR3Reset;
2232 /** Profiling pgmPoolFlushPage(). */
2233 STAMPROFILE StatFlushPage;
2234 /** Profiling pgmPoolFree(). */
2235 STAMPROFILE StatFree;
2236 /** Counting explicit flushes by PGMPoolFlushPage(). */
2237 STAMCOUNTER StatForceFlushPage;
2238 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2239 STAMCOUNTER StatForceFlushDirtyPage;
2240 /** Counting flushes for reused pages. */
2241 STAMCOUNTER StatForceFlushReused;
2242 /** Profiling time spent zeroing pages. */
2243 STAMPROFILE StatZeroPage;
2244 /** Profiling of pgmPoolTrackDeref. */
2245 STAMPROFILE StatTrackDeref;
2246 /** Profiling pgmTrackFlushGCPhysPT. */
2247 STAMPROFILE StatTrackFlushGCPhysPT;
2248 /** Profiling pgmTrackFlushGCPhysPTs. */
2249 STAMPROFILE StatTrackFlushGCPhysPTs;
2250 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2251 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2252 /** Number of times we've been out of user records. */
2253 STAMCOUNTER StatTrackFreeUpOneUser;
2254 /** Nr of flushed entries. */
2255 STAMCOUNTER StatTrackFlushEntry;
2256 /** Nr of updated entries. */
2257 STAMCOUNTER StatTrackFlushEntryKeep;
2258 /** Profiling deref activity related tracking GC physical pages. */
2259 STAMPROFILE StatTrackDerefGCPhys;
2260 /** Number of linear searches for a HCPhys in the ram ranges. */
2261 STAMCOUNTER StatTrackLinearRamSearches;
2262 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2263 STAMCOUNTER StamTrackPhysExtAllocFailures;
2264 /** Profiling the RC/R0 access handler. */
2265 STAMPROFILE StatMonitorRZ;
2266 /** Times we've failed interpreting the instruction. */
2267 STAMCOUNTER StatMonitorRZEmulateInstr;
2268 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2269 STAMPROFILE StatMonitorRZFlushPage;
2270 /* Times we've detected a page table reinit. */
2271 STAMCOUNTER StatMonitorRZFlushReinit;
2272 /** Counting flushes for pages that are modified too often. */
2273 STAMCOUNTER StatMonitorRZFlushModOverflow;
2274 /** Times we've detected fork(). */
2275 STAMCOUNTER StatMonitorRZFork;
2276 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2277 STAMPROFILE StatMonitorRZHandled;
2278 /** Times we've failed interpreting a patch code instruction. */
2279 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2280 /** Times we've failed interpreting a patch code instruction during flushing. */
2281 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2282 /** The number of times we've seen rep prefixes we can't handle. */
2283 STAMCOUNTER StatMonitorRZRepPrefix;
2284 /** Profiling the REP STOSD cases we've handled. */
2285 STAMPROFILE StatMonitorRZRepStosd;
2286 /** Nr of handled PT faults. */
2287 STAMCOUNTER StatMonitorRZFaultPT;
2288 /** Nr of handled PD faults. */
2289 STAMCOUNTER StatMonitorRZFaultPD;
2290 /** Nr of handled PDPT faults. */
2291 STAMCOUNTER StatMonitorRZFaultPDPT;
2292 /** Nr of handled PML4 faults. */
2293 STAMCOUNTER StatMonitorRZFaultPML4;
2294
2295 /** Profiling the R3 access handler. */
2296 STAMPROFILE StatMonitorR3;
2297 /** Times we've failed interpreting the instruction. */
2298 STAMCOUNTER StatMonitorR3EmulateInstr;
2299 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2300 STAMPROFILE StatMonitorR3FlushPage;
2301 /* Times we've detected a page table reinit. */
2302 STAMCOUNTER StatMonitorR3FlushReinit;
2303 /** Counting flushes for pages that are modified too often. */
2304 STAMCOUNTER StatMonitorR3FlushModOverflow;
2305 /** Times we've detected fork(). */
2306 STAMCOUNTER StatMonitorR3Fork;
2307 /** Profiling the R3 access we've handled (except REP STOSD). */
2308 STAMPROFILE StatMonitorR3Handled;
2309 /** The number of times we've seen rep prefixes we can't handle. */
2310 STAMCOUNTER StatMonitorR3RepPrefix;
2311 /** Profiling the REP STOSD cases we've handled. */
2312 STAMPROFILE StatMonitorR3RepStosd;
2313 /** Nr of handled PT faults. */
2314 STAMCOUNTER StatMonitorR3FaultPT;
2315 /** Nr of handled PD faults. */
2316 STAMCOUNTER StatMonitorR3FaultPD;
2317 /** Nr of handled PDPT faults. */
2318 STAMCOUNTER StatMonitorR3FaultPDPT;
2319 /** Nr of handled PML4 faults. */
2320 STAMCOUNTER StatMonitorR3FaultPML4;
2321 /** The number of times we're called in an async thread an need to flush. */
2322 STAMCOUNTER StatMonitorR3Async;
2323 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2324 STAMCOUNTER StatResetDirtyPages;
2325 /** Times we've called pgmPoolAddDirtyPage. */
2326 STAMCOUNTER StatDirtyPage;
2327 /** Times we've had to flush duplicates for dirty page management. */
2328 STAMCOUNTER StatDirtyPageDupFlush;
2329 /** Times we've had to flush because of overflow. */
2330 STAMCOUNTER StatDirtyPageOverFlowFlush;
2331
2332 /** The high water mark for cModifiedPages. */
2333 uint16_t cModifiedPagesHigh;
2334 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2335
2336 /** The number of cache hits. */
2337 STAMCOUNTER StatCacheHits;
2338 /** The number of cache misses. */
2339 STAMCOUNTER StatCacheMisses;
2340 /** The number of times we've got a conflict of 'kind' in the cache. */
2341 STAMCOUNTER StatCacheKindMismatches;
2342 /** Number of times we've been out of pages. */
2343 STAMCOUNTER StatCacheFreeUpOne;
2344 /** The number of cacheable allocations. */
2345 STAMCOUNTER StatCacheCacheable;
2346 /** The number of uncacheable allocations. */
2347 STAMCOUNTER StatCacheUncacheable;
2348#else
2349 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2350#endif
2351 /** The AVL tree for looking up a page by its HC physical address. */
2352 AVLOHCPHYSTREE HCPhysTree;
2353 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2354 /** Array of pages. (cMaxPages in length)
2355 * The Id is the index into thist array.
2356 */
2357 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2358} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2359AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2360AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2361AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2362#ifdef VBOX_WITH_STATISTICS
2363AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2364#endif
2365AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2366
2367
2368/** @def PGMPOOL_PAGE_2_PTR
2369 * Maps a pool page pool into the current context.
2370 *
2371 * @returns VBox status code.
2372 * @param pVM The VM handle.
2373 * @param pPage The pool page.
2374 *
2375 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2376 * small page window employeed by that function. Be careful.
2377 * @remark There is no need to assert on the result.
2378 */
2379#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2380# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2381#elif defined(VBOX_STRICT)
2382# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2383DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2384{
2385 Assert(pPage && pPage->pvPageR3);
2386 return pPage->pvPageR3;
2387}
2388#else
2389# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2390#endif
2391
2392
2393/** @def PGMPOOL_PAGE_2_PTR_V2
2394 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2395 *
2396 * @returns VBox status code.
2397 * @param pVM The VM handle.
2398 * @param pVCpu The current CPU.
2399 * @param pPage The pool page.
2400 *
2401 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2402 * small page window employeed by that function. Be careful.
2403 * @remark There is no need to assert on the result.
2404 */
2405#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2406# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2407#else
2408# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2409#endif
2410
2411
2412/** @name Per guest page tracking data.
2413 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2414 * is to use more bits for it and split it up later on. But for now we'll play
2415 * safe and change as little as possible.
2416 *
2417 * The 16-bit word has two parts:
2418 *
2419 * The first 14-bit forms the @a idx field. It is either the index of a page in
2420 * the shadow page pool, or and index into the extent list.
2421 *
2422 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2423 * shadow page pool references to the page. If cRefs equals
2424 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2425 * (misnomer) table and not the shadow page pool.
2426 *
2427 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2428 * the 16-bit word.
2429 *
2430 * @{ */
2431/** The shift count for getting to the cRefs part. */
2432#define PGMPOOL_TD_CREFS_SHIFT 14
2433/** The mask applied after shifting the tracking data down by
2434 * PGMPOOL_TD_CREFS_SHIFT. */
2435#define PGMPOOL_TD_CREFS_MASK 0x3
2436/** The cRefs value used to indicate that the idx is the head of a
2437 * physical cross reference list. */
2438#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2439/** The shift used to get idx. */
2440#define PGMPOOL_TD_IDX_SHIFT 0
2441/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2442#define PGMPOOL_TD_IDX_MASK 0x3fff
2443/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2444 * simply too many mappings of this page. */
2445#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2446
2447/** @def PGMPOOL_TD_MAKE
2448 * Makes a 16-bit tracking data word.
2449 *
2450 * @returns tracking data.
2451 * @param cRefs The @a cRefs field. Must be within bounds!
2452 * @param idx The @a idx field. Must also be within bounds! */
2453#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2454
2455/** @def PGMPOOL_TD_GET_CREFS
2456 * Get the @a cRefs field from a tracking data word.
2457 *
2458 * @returns The @a cRefs field
2459 * @param u16 The tracking data word.
2460 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2461 * non-zero @a u16. */
2462#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2463
2464/** @def PGMPOOL_TD_GET_IDX
2465 * Get the @a idx field from a tracking data word.
2466 *
2467 * @returns The @a idx field
2468 * @param u16 The tracking data word. */
2469#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2470/** @} */
2471
2472
2473/**
2474 * Trees are using self relative offsets as pointers.
2475 * So, all its data, including the root pointer, must be in the heap for HC and GC
2476 * to have the same layout.
2477 */
2478typedef struct PGMTREES
2479{
2480 /** Physical access handlers (AVL range+offsetptr tree). */
2481 AVLROGCPHYSTREE PhysHandlers;
2482 /** Virtual access handlers (AVL range + GC ptr tree). */
2483 AVLROGCPTRTREE VirtHandlers;
2484 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2485 AVLROGCPHYSTREE PhysToVirtHandlers;
2486 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2487 AVLROGCPTRTREE HyperVirtHandlers;
2488} PGMTREES;
2489/** Pointer to PGM trees. */
2490typedef PGMTREES *PPGMTREES;
2491
2492
2493/**
2494 * Page fault guest state for the AMD64 paging mode.
2495 */
2496typedef struct PGMPTWALKCORE
2497{
2498 /** The guest virtual address that is being resolved by the walk
2499 * (input). */
2500 RTGCPTR GCPtr;
2501
2502 /** The guest physical address that is the result of the walk.
2503 * @remarks only valid if fSucceeded is set. */
2504 RTGCPHYS GCPhys;
2505
2506 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2507 bool fSucceeded;
2508 /** The level problem arrised at.
2509 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2510 * level 8. This is 0 on success. */
2511 uint8_t uLevel;
2512 /** Set if the page isn't present. */
2513 bool fNotPresent;
2514 /** Encountered a bad physical address. */
2515 bool fBadPhysAddr;
2516 /** Set if there was reserved bit violations. */
2517 bool fRsvdError;
2518 /** Set if it involves a big page (2/4 MB). */
2519 bool fBigPage;
2520 /** Set if it involves a gigantic page (1 GB). */
2521 bool fGigantPage;
2522 /** The effect X86_PTE_US flag for the address. */
2523 bool fEffectiveUS;
2524 /** The effect X86_PTE_RW flag for the address. */
2525 bool fEffectiveRW;
2526 /** The effect X86_PTE_NX flag for the address. */
2527 bool fEffectiveNX;
2528} PGMPTWALKCORE;
2529
2530
2531/**
2532 * Guest page table walk for the AMD64 mode.
2533 */
2534typedef struct PGMPTWALKGSTAMD64
2535{
2536 /** The common core. */
2537 PGMPTWALKCORE Core;
2538
2539 PX86PML4 pPml4;
2540 PX86PML4E pPml4e;
2541 X86PML4E Pml4e;
2542
2543 PX86PDPT pPdpt;
2544 PX86PDPE pPdpe;
2545 X86PDPE Pdpe;
2546
2547 PX86PDPAE pPd;
2548 PX86PDEPAE pPde;
2549 X86PDEPAE Pde;
2550
2551 PX86PTPAE pPt;
2552 PX86PTEPAE pPte;
2553 X86PTEPAE Pte;
2554} PGMPTWALKGSTAMD64;
2555/** Pointer to a AMD64 guest page table walk. */
2556typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2557/** Pointer to a const AMD64 guest page table walk. */
2558typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2559
2560/**
2561 * Guest page table walk for the PAE mode.
2562 */
2563typedef struct PGMPTWALKGSTPAE
2564{
2565 /** The common core. */
2566 PGMPTWALKCORE Core;
2567
2568 PX86PDPT pPdpt;
2569 PX86PDPE pPdpe;
2570 X86PDPE Pdpe;
2571
2572 PX86PDPAE pPd;
2573 PX86PDEPAE pPde;
2574 X86PDEPAE Pde;
2575
2576 PX86PTPAE pPt;
2577 PX86PTEPAE pPte;
2578 X86PTEPAE Pte;
2579} PGMPTWALKGSTPAE;
2580/** Pointer to a PAE guest page table walk. */
2581typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2582/** Pointer to a const AMD64 guest page table walk. */
2583typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2584
2585/**
2586 * Guest page table walk for the 32-bit mode.
2587 */
2588typedef struct PGMPTWALKGST32BIT
2589{
2590 /** The common core. */
2591 PGMPTWALKCORE Core;
2592
2593 PX86PD pPd;
2594 PX86PDE pPde;
2595 X86PDE Pde;
2596
2597 PX86PT pPt;
2598 PX86PTE pPte;
2599 X86PTE Pte;
2600} PGMPTWALKGST32BIT;
2601/** Pointer to a 32-bit guest page table walk. */
2602typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2603/** Pointer to a const 32-bit guest page table walk. */
2604typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2605
2606
2607/** @name Paging mode macros
2608 * @{
2609 */
2610#ifdef IN_RC
2611# define PGM_CTX(a,b) a##RC##b
2612# define PGM_CTX_STR(a,b) a "GC" b
2613# define PGM_CTX_DECL(type) VMMRCDECL(type)
2614#else
2615# ifdef IN_RING3
2616# define PGM_CTX(a,b) a##R3##b
2617# define PGM_CTX_STR(a,b) a "R3" b
2618# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2619# else
2620# define PGM_CTX(a,b) a##R0##b
2621# define PGM_CTX_STR(a,b) a "R0" b
2622# define PGM_CTX_DECL(type) VMMDECL(type)
2623# endif
2624#endif
2625
2626#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2627#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2628#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2629#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2630#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2631#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2632#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2633#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2634#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2635#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2636#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2637#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2638#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2639#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2640#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2641#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2642#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2643
2644#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2645#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2646#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2647#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2648#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2649#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2650#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2651#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2652#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2653#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2654#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2655#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2656#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2657#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2658#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2659#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2660#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2661
2662/* Shw_Gst */
2663#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2664#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2665#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2666#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2667#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2668#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2669#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2670#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2671#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2672#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2673#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2674#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2675#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2676#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2677#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2678#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2679#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2680#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2681#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2682
2683#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2684#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2685#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2686#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2687#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2688#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2689#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2690#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2691#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2692#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2693#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2694#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2695#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2696#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2697#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2698#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2699#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2700#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2701#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2702#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2703#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2704#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2705#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2706#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2707#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2708#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2709#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2710#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2711#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2712#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2713#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2714#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2715#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2716#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2717#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2718#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2719#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2720
2721#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2722#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2723/** @} */
2724
2725/**
2726 * Data for each paging mode.
2727 */
2728typedef struct PGMMODEDATA
2729{
2730 /** The guest mode type. */
2731 uint32_t uGstType;
2732 /** The shadow mode type. */
2733 uint32_t uShwType;
2734
2735 /** @name Function pointers for Shadow paging.
2736 * @{
2737 */
2738 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2739 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2740 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2741 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2742
2743 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2744 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2745
2746 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2747 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2748 /** @} */
2749
2750 /** @name Function pointers for Guest paging.
2751 * @{
2752 */
2753 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2754 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2755 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2756 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2757 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2758 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2759 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2760 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2761 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2762 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2763 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2764 /** @} */
2765
2766 /** @name Function pointers for Both Shadow and Guest paging.
2767 * @{
2768 */
2769 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2770 /* no pfnR3BthTrap0eHandler */
2771 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2772 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2773 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2774 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2775#ifdef VBOX_STRICT
2776 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2777#endif
2778 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2779 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2780
2781 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2782 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2783 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2784 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2785 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2786#ifdef VBOX_STRICT
2787 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2788#endif
2789 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2790 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2791
2792 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2793 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2794 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2795 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2796 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2797#ifdef VBOX_STRICT
2798 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2799#endif
2800 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2801 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2802 /** @} */
2803} PGMMODEDATA, *PPGMMODEDATA;
2804
2805
2806#ifdef VBOX_WITH_STATISTICS
2807/**
2808 * PGM statistics.
2809 *
2810 * These lives on the heap when compiled in as they would otherwise waste
2811 * unnecessary space in release builds.
2812 */
2813typedef struct PGMSTATS
2814{
2815 /* R3 only: */
2816 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2817 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2818
2819 /* R3+RZ */
2820 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2821 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2822 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2823 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2824 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2825 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2826 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2827 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2828 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2829 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2830 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2831 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2832 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2833 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2834 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2835 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2836 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2837 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2838 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2839 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2840 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2841 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2842 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2843 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2844 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2845 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2846 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2847 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2848/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2849 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2850 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2851/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2852
2853 /* RC only: */
2854 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2855 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2856
2857 STAMCOUNTER StatRZPhysRead;
2858 STAMCOUNTER StatRZPhysReadBytes;
2859 STAMCOUNTER StatRZPhysWrite;
2860 STAMCOUNTER StatRZPhysWriteBytes;
2861 STAMCOUNTER StatR3PhysRead;
2862 STAMCOUNTER StatR3PhysReadBytes;
2863 STAMCOUNTER StatR3PhysWrite;
2864 STAMCOUNTER StatR3PhysWriteBytes;
2865 STAMCOUNTER StatRCPhysRead;
2866 STAMCOUNTER StatRCPhysReadBytes;
2867 STAMCOUNTER StatRCPhysWrite;
2868 STAMCOUNTER StatRCPhysWriteBytes;
2869
2870 STAMCOUNTER StatRZPhysSimpleRead;
2871 STAMCOUNTER StatRZPhysSimpleReadBytes;
2872 STAMCOUNTER StatRZPhysSimpleWrite;
2873 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2874 STAMCOUNTER StatR3PhysSimpleRead;
2875 STAMCOUNTER StatR3PhysSimpleReadBytes;
2876 STAMCOUNTER StatR3PhysSimpleWrite;
2877 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2878 STAMCOUNTER StatRCPhysSimpleRead;
2879 STAMCOUNTER StatRCPhysSimpleReadBytes;
2880 STAMCOUNTER StatRCPhysSimpleWrite;
2881 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2882
2883 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2884 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2885 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2886 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2887 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2888 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2889 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2890
2891 /** Time spent by the host OS for large page allocation. */
2892 STAMPROFILE StatAllocLargePage;
2893 /** Time spent clearing the newly allocated large pages. */
2894 STAMPROFILE StatClearLargePage;
2895 /** The number of times allocating a large pages takes more than the allowed period. */
2896 STAMCOUNTER StatLargePageOverflow;
2897 /** pgmPhysIsValidLargePage profiling - R3 */
2898 STAMPROFILE StatR3IsValidLargePage;
2899 /** pgmPhysIsValidLargePage profiling - RZ*/
2900 STAMPROFILE StatRZIsValidLargePage;
2901
2902 STAMPROFILE StatChunkAging;
2903 STAMPROFILE StatChunkFindCandidate;
2904 STAMPROFILE StatChunkUnmap;
2905 STAMPROFILE StatChunkMap;
2906} PGMSTATS;
2907#endif /* VBOX_WITH_STATISTICS */
2908
2909
2910/**
2911 * Converts a PGM pointer into a VM pointer.
2912 * @returns Pointer to the VM structure the PGM is part of.
2913 * @param pPGM Pointer to PGM instance data.
2914 */
2915#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2916
2917/**
2918 * PGM Data (part of VM)
2919 */
2920typedef struct PGM
2921{
2922 /** Offset to the VM structure. */
2923 int32_t offVM;
2924 /** Offset of the PGMCPU structure relative to VMCPU. */
2925 int32_t offVCpuPGM;
2926
2927 /** @cfgm{RamPreAlloc, boolean, false}
2928 * Indicates whether the base RAM should all be allocated before starting
2929 * the VM (default), or if it should be allocated when first written to.
2930 */
2931 bool fRamPreAlloc;
2932 /** Indicates whether write monitoring is currently in use.
2933 * This is used to prevent conflicts between live saving and page sharing
2934 * detection. */
2935 bool fPhysWriteMonitoringEngaged;
2936 /** Set if the CPU has less than 52-bit physical address width.
2937 * This is used */
2938 bool fLessThan52PhysicalAddressBits;
2939 /** Set when nested paging is active.
2940 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2941 * compilers optimize the code better. Whether we use nested paging or
2942 * not is something we find out during VMM initialization and we won't
2943 * change this later on. */
2944 bool fNestedPaging;
2945 /** The host paging mode. (This is what SUPLib reports.) */
2946 SUPPAGINGMODE enmHostMode;
2947 /** We're not in a state which permits writes to guest memory.
2948 * (Only used in strict builds.) */
2949 bool fNoMorePhysWrites;
2950 /** Set if PCI passthrough is enabled. */
2951 bool fPciPassthrough;
2952 /** Alignment padding that makes the next member start on a 8 byte boundary. */
2953 bool afAlignment1[2];
2954
2955 /** Indicates that PGMR3FinalizeMappings has been called and that further
2956 * PGMR3MapIntermediate calls will be rejected. */
2957 bool fFinalizedMappings;
2958 /** If set no conflict checks are required. */
2959 bool fMappingsFixed;
2960 /** If set if restored as fixed but we were unable to re-fixate at the old
2961 * location because of room or address incompatibilities. */
2962 bool fMappingsFixedRestored;
2963 /** If set, then no mappings are put into the shadow page table.
2964 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2965 bool fMappingsDisabled;
2966 /** Size of fixed mapping.
2967 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2968 uint32_t cbMappingFixed;
2969 /** Generation ID for the RAM ranges. This member is incremented everytime
2970 * a RAM range is linked or unlinked. */
2971 uint32_t volatile idRamRangesGen;
2972
2973 /** Base address (GC) of fixed mapping.
2974 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2975 RTGCPTR GCPtrMappingFixed;
2976 /** The address of the previous RAM range mapping. */
2977 RTGCPTR GCPtrPrevRamRangeMapping;
2978
2979 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2980 RTGCPHYS GCPhys4MBPSEMask;
2981 /** Mask containing the invalid bits of a guest physical address.
2982 * @remarks this does not stop at bit 52. */
2983 RTGCPHYS GCPhysInvAddrMask;
2984
2985
2986 /** RAM range TLB for R3. */
2987 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2988 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2989 * This is sorted by physical address and contains no overlapping ranges. */
2990 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2991 /** Root of the RAM range search tree for ring-3. */
2992 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2993 /** PGM offset based trees - R3 Ptr. */
2994 R3PTRTYPE(PPGMTREES) pTreesR3;
2995 /** Caching the last physical handler we looked up in R3. */
2996 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2997 /** Shadow Page Pool - R3 Ptr. */
2998 R3PTRTYPE(PPGMPOOL) pPoolR3;
2999 /** Linked list of GC mappings - for HC.
3000 * The list is sorted ascending on address. */
3001 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3002 /** Pointer to the list of ROM ranges - for R3.
3003 * This is sorted by physical address and contains no overlapping ranges. */
3004 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3005 /** Pointer to the list of MMIO2 ranges - for R3.
3006 * Registration order. */
3007 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3008 /** Pointer to SHW+GST mode data (function pointers).
3009 * The index into this table is made up from */
3010 R3PTRTYPE(PPGMMODEDATA) paModeData;
3011 RTR3PTR R3PtrAlignment0;
3012
3013 /** RAM range TLB for R0. */
3014 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3015 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3016 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3017 /** Root of the RAM range search tree for ring-0. */
3018 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3019 /** PGM offset based trees - R0 Ptr. */
3020 R0PTRTYPE(PPGMTREES) pTreesR0;
3021 /** Caching the last physical handler we looked up in R0. */
3022 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3023 /** Shadow Page Pool - R0 Ptr. */
3024 R0PTRTYPE(PPGMPOOL) pPoolR0;
3025 /** Linked list of GC mappings - for R0.
3026 * The list is sorted ascending on address. */
3027 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3028 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3029 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3030 RTR0PTR R0PtrAlignment0;
3031
3032
3033 /** RAM range TLB for RC. */
3034 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3035 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3036 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3037 /** Root of the RAM range search tree for raw-mode context. */
3038 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3039 /** PGM offset based trees - RC Ptr. */
3040 RCPTRTYPE(PPGMTREES) pTreesRC;
3041 /** Caching the last physical handler we looked up in RC. */
3042 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3043 /** Shadow Page Pool - RC Ptr. */
3044 RCPTRTYPE(PPGMPOOL) pPoolRC;
3045 /** Linked list of GC mappings - for RC.
3046 * The list is sorted ascending on address. */
3047 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3048 /** RC pointer corresponding to PGM::pRomRangesR3. */
3049 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3050 RTRCPTR RCPtrAlignment0;
3051 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3052 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3053 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3054 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3055
3056
3057 /** Pointer to the 5 page CR3 content mapping.
3058 * The first page is always the CR3 (in some form) while the 4 other pages
3059 * are used of the PDs in PAE mode. */
3060 RTGCPTR GCPtrCR3Mapping;
3061
3062 /** @name Intermediate Context
3063 * @{ */
3064 /** Pointer to the intermediate page directory - Normal. */
3065 R3PTRTYPE(PX86PD) pInterPD;
3066 /** Pointer to the intermediate page tables - Normal.
3067 * There are two page tables, one for the identity mapping and one for
3068 * the host context mapping (of the core code). */
3069 R3PTRTYPE(PX86PT) apInterPTs[2];
3070 /** Pointer to the intermediate page tables - PAE. */
3071 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3072 /** Pointer to the intermediate page directory - PAE. */
3073 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3074 /** Pointer to the intermediate page directory - PAE. */
3075 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3076 /** Pointer to the intermediate page-map level 4 - AMD64. */
3077 R3PTRTYPE(PX86PML4) pInterPaePML4;
3078 /** Pointer to the intermediate page directory - AMD64. */
3079 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3080 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3081 RTHCPHYS HCPhysInterPD;
3082 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3083 RTHCPHYS HCPhysInterPaePDPT;
3084 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3085 RTHCPHYS HCPhysInterPaePML4;
3086 /** @} */
3087
3088 /** Base address of the dynamic page mapping area.
3089 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3090 *
3091 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3092 * work out. Some cleaning up of the initialization that would
3093 * remove this memory is yet to be done...
3094 */
3095 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3096 /** The address of the raw-mode context mapping cache. */
3097 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3098 /** The address of the ring-0 mapping cache if we're making use of it. */
3099 RTR0PTR pvR0DynMapUsed;
3100#if HC_ARCH_BITS == 32
3101 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3102 uint32_t u32Alignment2;
3103#endif
3104
3105 /** PGM critical section.
3106 * This protects the physical & virtual access handlers, ram ranges,
3107 * and the page flag updating (some of it anyway).
3108 */
3109 PDMCRITSECT CritSect;
3110
3111 /**
3112 * Data associated with managing the ring-3 mappings of the allocation chunks.
3113 */
3114 struct
3115 {
3116 /** The chunk tree, ordered by chunk id. */
3117#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3118 R3PTRTYPE(PAVLU32NODECORE) pTree;
3119#else
3120 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3121#endif
3122#if HC_ARCH_BITS == 32
3123 uint32_t u32Alignment;
3124#endif
3125 /** The chunk mapping TLB. */
3126 PGMCHUNKR3MAPTLB Tlb;
3127 /** The number of mapped chunks. */
3128 uint32_t c;
3129 /** The maximum number of mapped chunks.
3130 * @cfgm PGM/MaxRing3Chunks */
3131 uint32_t cMax;
3132 /** The current time. */
3133 uint32_t iNow;
3134 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3135 uint32_t AgeingCountdown;
3136 } ChunkR3Map;
3137
3138 /**
3139 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3140 */
3141 PGMPAGER3MAPTLB PhysTlbHC;
3142
3143 /** @name The zero page.
3144 * @{ */
3145 /** The host physical address of the zero page. */
3146 RTHCPHYS HCPhysZeroPg;
3147 /** The ring-3 mapping of the zero page. */
3148 RTR3PTR pvZeroPgR3;
3149 /** The ring-0 mapping of the zero page. */
3150 RTR0PTR pvZeroPgR0;
3151 /** The GC mapping of the zero page. */
3152 RTRCPTR pvZeroPgRC;
3153 RTRCPTR RCPtrAlignment3;
3154 /** @}*/
3155
3156 /** @name The Invalid MMIO page.
3157 * This page is filled with 0xfeedface.
3158 * @{ */
3159 /** The host physical address of the invalid MMIO page. */
3160 RTHCPHYS HCPhysMmioPg;
3161 /** The host pysical address of the invalid MMIO page plus all invalid
3162 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3163 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3164 RTHCPHYS HCPhysInvMmioPg;
3165 /** The ring-3 mapping of the invalid MMIO page. */
3166 RTR3PTR pvMmioPgR3;
3167#if HC_ARCH_BITS == 32
3168 RTR3PTR R3PtrAlignment4;
3169#endif
3170 /** @} */
3171
3172
3173 /** The number of handy pages. */
3174 uint32_t cHandyPages;
3175
3176 /** The number of large handy pages. */
3177 uint32_t cLargeHandyPages;
3178
3179 /**
3180 * Array of handy pages.
3181 *
3182 * This array is used in a two way communication between pgmPhysAllocPage
3183 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3184 * an intermediary.
3185 *
3186 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3187 * (The current size of 32 pages, means 128 KB of handy memory.)
3188 */
3189 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3190
3191 /**
3192 * Array of large handy pages. (currently size 1)
3193 *
3194 * This array is used in a two way communication between pgmPhysAllocLargePage
3195 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3196 * an intermediary.
3197 */
3198 GMMPAGEDESC aLargeHandyPage[1];
3199
3200 /**
3201 * Live save data.
3202 */
3203 struct
3204 {
3205 /** Per type statistics. */
3206 struct
3207 {
3208 /** The number of ready pages. */
3209 uint32_t cReadyPages;
3210 /** The number of dirty pages. */
3211 uint32_t cDirtyPages;
3212 /** The number of ready zero pages. */
3213 uint32_t cZeroPages;
3214 /** The number of write monitored pages. */
3215 uint32_t cMonitoredPages;
3216 } Rom,
3217 Mmio2,
3218 Ram;
3219 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3220 uint32_t cIgnoredPages;
3221 /** Indicates that a live save operation is active. */
3222 bool fActive;
3223 /** Padding. */
3224 bool afReserved[2];
3225 /** The next history index. */
3226 uint8_t iDirtyPagesHistory;
3227 /** History of the total amount of dirty pages. */
3228 uint32_t acDirtyPagesHistory[64];
3229 /** Short term dirty page average. */
3230 uint32_t cDirtyPagesShort;
3231 /** Long term dirty page average. */
3232 uint32_t cDirtyPagesLong;
3233 /** The number of saved pages. This is used to get some kind of estimate of the
3234 * link speed so we can decide when we're done. It is reset after the first
3235 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3236 * zero pages. */
3237 uint64_t cSavedPages;
3238 /** The nanosecond timestamp when cSavedPages was 0. */
3239 uint64_t uSaveStartNS;
3240 /** Pages per second (for statistics). */
3241 uint32_t cPagesPerSecond;
3242 uint32_t cAlignment;
3243 } LiveSave;
3244
3245 /** @name Error injection.
3246 * @{ */
3247 /** Inject handy page allocation errors pretending we're completely out of
3248 * memory. */
3249 bool volatile fErrInjHandyPages;
3250 /** Padding. */
3251 bool afReserved[3];
3252 /** @} */
3253
3254 /** @name Release Statistics
3255 * @{ */
3256 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3257 uint32_t cPrivatePages; /**< The number of private pages. */
3258 uint32_t cSharedPages; /**< The number of shared pages. */
3259 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3260 uint32_t cZeroPages; /**< The number of zero backed pages. */
3261 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3262 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3263 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3264 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3265 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3266 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3267 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3268 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3269 uint32_t cLargePages; /**< The number of large pages. */
3270 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3271/* uint32_t aAlignment4[1]; */
3272
3273 /** The number of times we were forced to change the hypervisor region location. */
3274 STAMCOUNTER cRelocations;
3275
3276 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3277 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3278 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3279 /** @} */
3280
3281#ifdef VBOX_WITH_STATISTICS
3282 /** @name Statistics on the heap.
3283 * @{ */
3284 R3PTRTYPE(PGMSTATS *) pStatsR3;
3285 R0PTRTYPE(PGMSTATS *) pStatsR0;
3286 RCPTRTYPE(PGMSTATS *) pStatsRC;
3287 RTRCPTR RCPtrAlignment;
3288 /** @} */
3289#endif
3290} PGM;
3291#ifndef IN_TSTVMSTRUCTGC /* HACK */
3292AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3293AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3294AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3295AssertCompileMemberAlignment(PGM, CritSect, 8);
3296AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3297AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3298AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3299AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3300AssertCompileMemberAlignment(PGM, cRelocations, 8);
3301#endif /* !IN_TSTVMSTRUCTGC */
3302/** Pointer to the PGM instance data. */
3303typedef PGM *PPGM;
3304
3305
3306
3307typedef struct PGMCPUSTATS
3308{
3309 /* Common */
3310 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3311 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3312
3313 /* R0 only: */
3314 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3315 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3316
3317 /* RZ only: */
3318 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3319 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3320 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3321 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3322 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3323 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3324 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3325 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3326 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3327 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3328 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3329 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3330 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3331 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3332 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3333 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3334 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3335 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3336 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3337 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3338 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3339 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3340 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3341 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3342 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3343 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3344 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3345 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3346 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3347 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3348 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3349 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3350 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3351 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3352 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3353 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3354 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3355 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3356 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3357 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3358 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3359 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3360 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3361 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3362 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3363 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3364 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3365 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3366 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3367 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3368 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3369 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3370 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3371 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3372 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3373 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3374 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3375 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3376 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3377 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3378 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3379 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3380 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3381 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3382 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3383 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3384 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3385 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3386 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3387 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3388 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3389 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3390 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3391 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3392 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3393 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3394
3395 /* HC - R3 and (maybe) R0: */
3396
3397 /* RZ & R3: */
3398 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3399 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3400 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3401 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3402 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3403 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3404 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3405 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3406 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3407 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3408 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3409 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3410 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3411 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3412 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3413 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3414 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3415 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3416 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3417 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3418 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3419 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3420 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3421 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3422 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3423 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3424 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3425 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3426 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3427 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3428 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3429 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3430 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3431 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3432 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3433 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3434 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3435 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3436 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3437 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3438 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3439 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3440 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3441 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3442 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3443 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3444 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3445
3446 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3447 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3448 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3449 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3450 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3451 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3452 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3453 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3454 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3455 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3456 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3457 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3458 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3459 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3460 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3461 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3462 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3463 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3464 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3465 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3466 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3467 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3468 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3469 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3470 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3471 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3472 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3473 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3474 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3475 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3476 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3477 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3478 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3479 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3480 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3481 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3482 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3483 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3484 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3485 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3486 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3487 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3488 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3489 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3490 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3491 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3492 /** @} */
3493} PGMCPUSTATS;
3494
3495
3496/**
3497 * Converts a PGMCPU pointer into a VM pointer.
3498 * @returns Pointer to the VM structure the PGM is part of.
3499 * @param pPGM Pointer to PGMCPU instance data.
3500 */
3501#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3502
3503/**
3504 * Converts a PGMCPU pointer into a PGM pointer.
3505 * @returns Pointer to the VM structure the PGM is part of.
3506 * @param pPGM Pointer to PGMCPU instance data.
3507 */
3508#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3509
3510/**
3511 * PGMCPU Data (part of VMCPU).
3512 */
3513typedef struct PGMCPU
3514{
3515 /** Offset to the VM structure. */
3516 int32_t offVM;
3517 /** Offset to the VMCPU structure. */
3518 int32_t offVCpu;
3519 /** Offset of the PGM structure relative to VMCPU. */
3520 int32_t offPGM;
3521 uint32_t uPadding0; /**< structure size alignment. */
3522
3523#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3524 /** Automatically tracked physical memory mapping set.
3525 * Ring-0 and strict raw-mode builds. */
3526 PGMMAPSET AutoSet;
3527#endif
3528
3529 /** A20 gate mask.
3530 * Our current approach to A20 emulation is to let REM do it and don't bother
3531 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3532 * But whould need arrise, we'll subject physical addresses to this mask. */
3533 RTGCPHYS GCPhysA20Mask;
3534 /** A20 gate state - boolean! */
3535 bool fA20Enabled;
3536 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3537 bool fNoExecuteEnabled;
3538 /** Unused bits. */
3539 bool afUnused[2];
3540
3541 /** What needs syncing (PGM_SYNC_*).
3542 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3543 * PGMFlushTLB, and PGMR3Load. */
3544 RTUINT fSyncFlags;
3545
3546 /** The shadow paging mode. */
3547 PGMMODE enmShadowMode;
3548 /** The guest paging mode. */
3549 PGMMODE enmGuestMode;
3550
3551 /** The current physical address representing in the guest CR3 register. */
3552 RTGCPHYS GCPhysCR3;
3553
3554 /** @name 32-bit Guest Paging.
3555 * @{ */
3556 /** The guest's page directory, R3 pointer. */
3557 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3558#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3559 /** The guest's page directory, R0 pointer. */
3560 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3561#endif
3562 /** The guest's page directory, static RC mapping. */
3563 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3564 /** Mask containing the MBZ bits of a big page PDE. */
3565 uint32_t fGst32BitMbzBigPdeMask;
3566 /** Set if the page size extension (PSE) is enabled. */
3567 bool fGst32BitPageSizeExtension;
3568 /** Alignment padding. */
3569 bool afAlignment2[3];
3570 /** @} */
3571
3572 /** @name PAE Guest Paging.
3573 * @{ */
3574 /** The guest's page directory pointer table, static RC mapping. */
3575 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3576 /** The guest's page directory pointer table, R3 pointer. */
3577 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3578#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3579 /** The guest's page directory pointer table, R0 pointer. */
3580 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3581#endif
3582
3583 /** The guest's page directories, R3 pointers.
3584 * These are individual pointers and don't have to be adjacent.
3585 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3586 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3587 /** The guest's page directories, R0 pointers.
3588 * Same restrictions as apGstPaePDsR3. */
3589#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3590 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3591#endif
3592 /** The guest's page directories, static GC mapping.
3593 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3594 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3595 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3596 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3597 RTGCPHYS aGCPhysGstPaePDs[4];
3598 /** The physical addresses of the monitored guest page directories (PAE). */
3599 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3600 /** Mask containing the MBZ PTE bits. */
3601 uint64_t fGstPaeMbzPteMask;
3602 /** Mask containing the MBZ PDE bits. */
3603 uint64_t fGstPaeMbzPdeMask;
3604 /** Mask containing the MBZ big page PDE bits. */
3605 uint64_t fGstPaeMbzBigPdeMask;
3606 /** Mask containing the MBZ PDPE bits. */
3607 uint64_t fGstPaeMbzPdpeMask;
3608 /** @} */
3609
3610 /** @name AMD64 Guest Paging.
3611 * @{ */
3612 /** The guest's page directory pointer table, R3 pointer. */
3613 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3614#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3615 /** The guest's page directory pointer table, R0 pointer. */
3616 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3617#else
3618 RTR0PTR alignment6b; /**< alignment equalizer. */
3619#endif
3620 /** Mask containing the MBZ PTE bits. */
3621 uint64_t fGstAmd64MbzPteMask;
3622 /** Mask containing the MBZ PDE bits. */
3623 uint64_t fGstAmd64MbzPdeMask;
3624 /** Mask containing the MBZ big page PDE bits. */
3625 uint64_t fGstAmd64MbzBigPdeMask;
3626 /** Mask containing the MBZ PDPE bits. */
3627 uint64_t fGstAmd64MbzPdpeMask;
3628 /** Mask containing the MBZ big page PDPE bits. */
3629 uint64_t fGstAmd64MbzBigPdpeMask;
3630 /** Mask containing the MBZ PML4E bits. */
3631 uint64_t fGstAmd64MbzPml4eMask;
3632 /** Mask containing the PDPE bits that we shadow. */
3633 uint64_t fGstAmd64ShadowedPdpeMask;
3634 /** Mask containing the PML4E bits that we shadow. */
3635 uint64_t fGstAmd64ShadowedPml4eMask;
3636 /** @} */
3637
3638 /** @name PAE and AMD64 Guest Paging.
3639 * @{ */
3640 /** Mask containing the PTE bits that we shadow. */
3641 uint64_t fGst64ShadowedPteMask;
3642 /** Mask containing the PDE bits that we shadow. */
3643 uint64_t fGst64ShadowedPdeMask;
3644 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3645 uint64_t fGst64ShadowedBigPdeMask;
3646 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3647 uint64_t fGst64ShadowedBigPde4PteMask;
3648 /** @} */
3649
3650 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3651 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3652 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3653 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3654 /** Pointer to the page of the current active CR3 - RC Ptr. */
3655 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3656 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3657 uint32_t iShwUser;
3658 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3659 uint32_t iShwUserTable;
3660# if HC_ARCH_BITS == 64
3661 RTRCPTR alignment6; /**< structure size alignment. */
3662# endif
3663 /** @} */
3664
3665 /** @name Function pointers for Shadow paging.
3666 * @{
3667 */
3668 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3669 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3670 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3671 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3672
3673 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3674 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3675
3676 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3677 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3678
3679 /** @} */
3680
3681 /** @name Function pointers for Guest paging.
3682 * @{
3683 */
3684 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3685 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3686 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3687 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3688 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3689 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3690 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3691 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3692#if HC_ARCH_BITS == 64
3693 RTRCPTR alignment3; /**< structure size alignment. */
3694#endif
3695
3696 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3697 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3698 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3699 /** @} */
3700
3701 /** @name Function pointers for Both Shadow and Guest paging.
3702 * @{
3703 */
3704 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3705 /* no pfnR3BthTrap0eHandler */
3706 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3707 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3708 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3709 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3710 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3711 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3712 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3713
3714 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3715 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3716 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3717 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3718 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3719 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3720 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3721 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3722
3723 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3724 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3725 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3726 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3727 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3728 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3729 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3730 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3731#if 0
3732 RTRCPTR alignment2; /**< structure size alignment. */
3733#endif
3734 /** @} */
3735
3736 /** For saving stack space, the disassembler state is allocated here instead of
3737 * on the stack.
3738 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3739 union
3740 {
3741 /** The disassembler scratch space. */
3742 DISCPUSTATE DisState;
3743 /** Padding. */
3744 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3745 };
3746
3747 /** Count the number of pgm pool access handler calls. */
3748 uint64_t cPoolAccessHandler;
3749
3750 /** @name Release Statistics
3751 * @{ */
3752 /** The number of times the guest has switched mode since last reset or statistics reset. */
3753 STAMCOUNTER cGuestModeChanges;
3754 /** @} */
3755
3756#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3757 /** @name Statistics
3758 * @{ */
3759 /** RC: Pointer to the statistics. */
3760 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3761 /** RC: Which statistic this \#PF should be attributed to. */
3762 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3763 /** R0: Pointer to the statistics. */
3764 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3765 /** R0: Which statistic this \#PF should be attributed to. */
3766 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3767 /** R3: Pointer to the statistics. */
3768 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3769 /** Alignment padding. */
3770 RTR3PTR pPaddingR3;
3771 /** @} */
3772#endif /* VBOX_WITH_STATISTICS */
3773} PGMCPU;
3774/** Pointer to the per-cpu PGM data. */
3775typedef PGMCPU *PPGMCPU;
3776
3777
3778/** @name PGM::fSyncFlags Flags
3779 * @{
3780 */
3781/** Updates the virtual access handler state bit in PGMPAGE. */
3782#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3783/** Always sync CR3. */
3784#define PGM_SYNC_ALWAYS RT_BIT(1)
3785/** Check monitoring on next CR3 (re)load and invalidate page.
3786 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3787#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3788/** Check guest mapping in SyncCR3. */
3789#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3790/** Clear the page pool (a light weight flush). */
3791#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3792#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3793/** @} */
3794
3795
3796RT_C_DECLS_BEGIN
3797
3798int pgmLock(PVM pVM);
3799void pgmUnlock(PVM pVM);
3800
3801int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3802int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3803int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3804PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3805int pgmMapResolveConflicts(PVM pVM);
3806DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3807
3808void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3809bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3810void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3811int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3812DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3813#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3814void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3815#else
3816# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3817#endif
3818DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3819int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3820
3821int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3822int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3823int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3824int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
3825int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3826void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3827int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3828int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3829int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3830int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3831int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3832int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3833int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3834VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3835VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3836int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3837void pgmPhysInvalidRamRangeTlbs(PVM pVM);
3838PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3839PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3840PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3841int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3842int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3843
3844#ifdef IN_RING3
3845void pgmR3PhysRelinkRamRanges(PVM pVM);
3846int pgmR3PhysRamPreAllocate(PVM pVM);
3847int pgmR3PhysRamReset(PVM pVM);
3848int pgmR3PhysRomReset(PVM pVM);
3849int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3850int pgmR3PhysRamTerm(PVM pVM);
3851void pgmR3PhysRomTerm(PVM pVM);
3852
3853int pgmR3PoolInit(PVM pVM);
3854void pgmR3PoolRelocate(PVM pVM);
3855void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3856void pgmR3PoolReset(PVM pVM);
3857void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3858DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3859void pgmR3PoolWriteProtectPages(PVM pVM);
3860
3861#endif /* IN_RING3 */
3862#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3863int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3864int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3865# ifdef LOG_ENABLED
3866void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3867# else
3868void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3869# endif
3870#endif
3871int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3872 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3873
3874DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3875 PPPGMPOOLPAGE ppPage)
3876{
3877 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3878}
3879
3880void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3881void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3882int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3883void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3884PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3885PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3886int pgmPoolSyncCR3(PVMCPU pVCpu);
3887bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3888void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3889int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3890void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3891uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3892void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3893void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3894int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3895void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3896
3897void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3898void pgmPoolResetDirtyPages(PVM pVM);
3899void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3900
3901int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3902int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3903
3904void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3905void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3906int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3907int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3908
3909int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3910int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3911
3912int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3913int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3914int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3915int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3916
3917# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3918DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3919DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3920# endif
3921
3922RT_C_DECLS_END
3923
3924/** @} */
3925
3926#endif
3927
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