VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 36938

Last change on this file since 36938 was 36938, checked in by vboxsync, 14 years ago

PGMPAGE: Moved the union a level up (PGMPAGE) and rename the 'bit' struct to 's'.
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1/* $Id: PGMInternal.h 36938 2011-05-03 14:16:56Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pvPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pvPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef union PGMPAGE
692{
693 /** Structured view. */
694 struct
695 {
696 /** The physical address and the Page ID. */
697 RTHCPHYS HCPhysAndPageID;
698
699 /** 7:0 - The physical handler state
700 * (PGM_PAGE_HNDL_PHYS_STATE_*). */
701 uint32_t u2HandlerPhysStateY : 8;
702 /*uint32_t u6Reserved : 6;*/
703 /** 9:8 - The physical handler state
704 * (PGM_PAGE_HNDL_VIRT_STATE_*). */
705 uint32_t u2HandlerVirtStateY : 2;
706 /** 10 - Indicator of dirty page for fault tolerance
707 * tracking. */
708 uint32_t fFTDirtyY : 1;
709 /** 12:11 - Currently unused. */
710 uint32_t u2Unused2 : 2;
711 /** 14:13 - Paging structure needed to map the page
712 * (PGM_PAGE_PDE_TYPE_*). */
713 uint32_t u2PDETypeY : 2;
714 /** 15 - Flag indicating that a write monitored page was written
715 * to when set. */
716 uint32_t fWrittenToY : 1;
717 /** 18:16 - The page state. */
718 uint32_t uStateY : 3;
719 /** 21:19 - The page type (PGMPAGETYPE). */
720 uint32_t uTypeY : 3;
721 /** 31:22 - PTE index for usage tracking (page pool). */
722 uint32_t u10PteIdx : 10;
723
724 /** Usage tracking (page pool). */
725 uint16_t u16TrackingY;
726 /** The number of read locks on this page. */
727 uint8_t cReadLocksY;
728 /** The number of write locks on this page. */
729 uint8_t cWriteLocksY;
730 } s;
731
732 /** 64-bit integer view. */
733 uint64_t au64[2];
734 /** 16-bit view. */
735 uint32_t au32[4];
736 /** 16-bit view. */
737 uint16_t au16[8];
738 /** 8-bit view. */
739 uint8_t au8[16];
740} PGMPAGE;
741AssertCompileSize(PGMPAGE, 16);
742/** Pointer to a physical guest page. */
743typedef PGMPAGE *PPGMPAGE;
744/** Pointer to a const physical guest page. */
745typedef const PGMPAGE *PCPGMPAGE;
746/** Pointer to a physical guest page pointer. */
747typedef PPGMPAGE *PPPGMPAGE;
748
749
750/**
751 * Clears the page structure.
752 * @param a_pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_CLEAR(a_pPage) \
755 do { \
756 (a_pPage)->au64[0] = 0; \
757 (a_pPage)->au64[1] = 0; \
758 } while (0)
759
760/**
761 * Initializes the page structure.
762 * @param a_pPage Pointer to the physical guest page tracking structure.
763 */
764#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
765 do { \
766 (a_pPage)->au64[1] = 0; \
767 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
768 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
769 (a_pPage)->s.HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((a_idPage) & UINT32_C(0x0fffffff)); \
770 (a_pPage)->s.uStateY = (a_uState); \
771 (a_pPage)->s.uTypeY = (a_uType); \
772 } while (0)
773
774/**
775 * Initializes the page structure of a ZERO page.
776 * @param a_pPage Pointer to the physical guest page tracking structure.
777 * @param a_pVM The VM handle (for getting the zero page address).
778 * @param a_uType The page type (PGMPAGETYPE).
779 */
780#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
781 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
782
783
784/** @name The Page state, PGMPAGE::uStateY.
785 * @{ */
786/** The zero page.
787 * This is a per-VM page that's never ever mapped writable. */
788#define PGM_PAGE_STATE_ZERO 0
789/** A allocated page.
790 * This is a per-VM page allocated from the page pool (or wherever
791 * we get MMIO2 pages from if the type is MMIO2).
792 */
793#define PGM_PAGE_STATE_ALLOCATED 1
794/** A allocated page that's being monitored for writes.
795 * The shadow page table mappings are read-only. When a write occurs, the
796 * fWrittenTo member is set, the page remapped as read-write and the state
797 * moved back to allocated. */
798#define PGM_PAGE_STATE_WRITE_MONITORED 2
799/** The page is shared, aka. copy-on-write.
800 * This is a page that's shared with other VMs. */
801#define PGM_PAGE_STATE_SHARED 3
802/** The page is ballooned, so no longer available for this VM. */
803#define PGM_PAGE_STATE_BALLOONED 4
804/** @} */
805
806
807/**
808 * Gets the page state.
809 * @returns page state (PGM_PAGE_STATE_*).
810 * @param a_pPage Pointer to the physical guest page tracking structure.
811 */
812#define PGM_PAGE_GET_STATE(a_pPage) ( (a_pPage)->s.uStateY )
813
814/**
815 * Sets the page state.
816 * @param a_pPage Pointer to the physical guest page tracking structure.
817 * @param a_uState The new page state.
818 */
819#define PGM_PAGE_SET_STATE(a_pPage, a_uState) do { (a_pPage)->s.uStateY = (a_uState); } while (0)
820
821
822/**
823 * Gets the host physical address of the guest page.
824 * @returns host physical address (RTHCPHYS).
825 * @param a_pPage Pointer to the physical guest page tracking structure.
826 */
827#define PGM_PAGE_GET_HCPHYS(a_pPage) ( ((a_pPage)->s.HCPhysAndPageID >> 28) << 12 )
828
829/**
830 * Sets the host physical address of the guest page.
831 * @param a_pPage Pointer to the physical guest page tracking structure.
832 * @param a_HCPhys The new host physical address.
833 */
834#define PGM_PAGE_SET_HCPHYS(a_pPage, a_HCPhys) \
835 do { \
836 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
837 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
838 (a_pPage)->s.HCPhysAndPageID = ((a_pPage)->s.HCPhysAndPageID & UINT32_C(0x0fffffff)) \
839 | (SetHCPhysTmp << (28-12)); \
840 } while (0)
841
842/**
843 * Get the Page ID.
844 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
845 * @param a_pPage Pointer to the physical guest page tracking structure.
846 */
847#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)((a_pPage)->s.HCPhysAndPageID & UINT32_C(0x0fffffff)) )
848
849/**
850 * Sets the Page ID.
851 * @param a_pPage Pointer to the physical guest page tracking structure.
852 * @param a_idPage The new page ID.
853 */
854#define PGM_PAGE_SET_PAGEID(a_pPage, a_idPage) \
855 do { \
856 (a_pPage)->s.HCPhysAndPageID = (((a_pPage)->s.HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
857 | ((a_idPage) & UINT32_C(0x0fffffff)); \
858 } while (0)
859
860/**
861 * Get the Chunk ID.
862 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
863 * @param a_pPage Pointer to the physical guest page tracking structure.
864 */
865#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
866
867/**
868 * Get the index of the page within the allocation chunk.
869 * @returns The page index.
870 * @param a_pPage Pointer to the physical guest page tracking structure.
871 */
872#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( (uint32_t)((a_pPage)->s.HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
873
874/**
875 * Gets the page type.
876 * @returns The page type.
877 * @param a_pPage Pointer to the physical guest page tracking structure.
878 */
879#define PGM_PAGE_GET_TYPE(a_pPage) ( (a_pPage)->s.uTypeY )
880
881/**
882 * Sets the page type.
883 * @param a_pPage Pointer to the physical guest page tracking structure.
884 * @param a_enmType The new page type (PGMPAGETYPE).
885 */
886#define PGM_PAGE_SET_TYPE(a_pPage, a_enmType) do { (a_pPage)->s.uTypeY = (a_enmType); } while (0)
887
888/**
889 * Gets the page table index
890 * @returns The page table index.
891 * @param a_pPage Pointer to the physical guest page tracking structure.
892 */
893#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
894
895/**
896 * Sets the page table index.
897 * @param a_pPage Pointer to the physical guest page tracking structure.
898 * @param a_iPte New page table index.
899 */
900#define PGM_PAGE_SET_PTE_INDEX(a_pPage, a_iPte) do { (a_pPage)->s.u10PteIdx = (a_iPte); } while (0)
901
902/**
903 * Checks if the page is marked for MMIO.
904 * @returns true/false.
905 * @param a_pPage Pointer to the physical guest page tracking structure.
906 */
907#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
908
909/**
910 * Checks if the page is backed by the ZERO page.
911 * @returns true/false.
912 * @param a_pPage Pointer to the physical guest page tracking structure.
913 */
914#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
915
916/**
917 * Checks if the page is backed by a SHARED page.
918 * @returns true/false.
919 * @param a_pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
922
923/**
924 * Checks if the page is ballooned.
925 * @returns true/false.
926 * @param a_pPage Pointer to the physical guest page tracking structure.
927 */
928#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
929
930/**
931 * Checks if the page is allocated.
932 * @returns true/false.
933 * @param a_pPage Pointer to the physical guest page tracking structure.
934 */
935#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
936
937/**
938 * Marks the page as written to (for GMM change monitoring).
939 * @param a_pPage Pointer to the physical guest page tracking structure.
940 */
941#define PGM_PAGE_SET_WRITTEN_TO(a_pPage) do { (a_pPage)->au8[1] |= UINT8_C(0x80); } while (0) /// FIXME FIXME
942
943/**
944 * Clears the written-to indicator.
945 * @param a_pPage Pointer to the physical guest page tracking structure.
946 */
947#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pPage) do { (a_pPage)->s.fWrittenToY = 0; } while (0)
948
949/**
950 * Checks if the page was marked as written-to.
951 * @returns true/false.
952 * @param a_pPage Pointer to the physical guest page tracking structure.
953 */
954#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
955
956/**
957 * Marks the page as dirty for FTM
958 * @param a_pPage Pointer to the physical guest page tracking structure.
959 */
960#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
961
962/**
963 * Clears the FTM dirty indicator
964 * @param a_pPage Pointer to the physical guest page tracking structure.
965 */
966#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
967
968/**
969 * Checks if the page was marked as dirty for FTM
970 * @returns true/false.
971 * @param a_pPage Pointer to the physical guest page tracking structure.
972 */
973#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
974
975
976/** @name PT usage values (PGMPAGE::u2PDEType).
977 *
978 * @{ */
979/** Either as a PT or PDE. */
980#define PGM_PAGE_PDE_TYPE_DONTCARE 0
981/** Must use a page table to map the range. */
982#define PGM_PAGE_PDE_TYPE_PT 1
983/** Can use a page directory entry to map the continuous range. */
984#define PGM_PAGE_PDE_TYPE_PDE 2
985/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
986#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
987/** @} */
988
989/**
990 * Set the PDE type of the page
991 * @param a_pPage Pointer to the physical guest page tracking structure.
992 * @param a_uType PGM_PAGE_PDE_TYPE_*.
993 */
994#define PGM_PAGE_SET_PDE_TYPE(a_pPage, a_uType) \
995 do { (a_pPage)->s.u2PDETypeY = (a_uType); } while (0)
996
997/**
998 * Checks if the page was marked being part of a large page
999 * @returns true/false.
1000 * @param a_pPage Pointer to the physical guest page tracking structure.
1001 */
1002#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1003
1004/** Enabled optimized access handler tests.
1005 * These optimizations makes ASSUMPTIONS about the state values and the s1
1006 * layout. When enabled, the compiler should normally generate more compact
1007 * code.
1008 */
1009#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1010
1011/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1012 *
1013 * @remarks The values are assigned in order of priority, so we can calculate
1014 * the correct state for a page with different handlers installed.
1015 * @{ */
1016/** No handler installed. */
1017#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1018/** Monitoring is temporarily disabled. */
1019#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1020/** Write access is monitored. */
1021#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1022/** All access is monitored. */
1023#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1024/** @} */
1025
1026/**
1027 * Gets the physical access handler state of a page.
1028 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1029 * @param a_pPage Pointer to the physical guest page tracking structure.
1030 */
1031#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1032
1033/**
1034 * Sets the physical access handler state of a page.
1035 * @param a_pPage Pointer to the physical guest page tracking structure.
1036 * @param a_uState The new state value.
1037 */
1038#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1039 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1040
1041/**
1042 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1043 * @returns true/false
1044 * @param a_pPage Pointer to the physical guest page tracking structure.
1045 */
1046#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1047 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1048
1049/**
1050 * Checks if the page has any active physical access handlers.
1051 * @returns true/false
1052 * @param a_pPage Pointer to the physical guest page tracking structure.
1053 */
1054#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1055 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1056
1057
1058/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1059 *
1060 * @remarks The values are assigned in order of priority, so we can calculate
1061 * the correct state for a page with different handlers installed.
1062 * @{ */
1063/** No handler installed. */
1064#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1065/* 1 is reserved so the lineup is identical with the physical ones. */
1066/** Write access is monitored. */
1067#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1068/** All access is monitored. */
1069#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1070/** @} */
1071
1072/**
1073 * Gets the virtual access handler state of a page.
1074 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1075 * @param a_pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1078
1079/**
1080 * Sets the virtual access handler state of a page.
1081 * @param a_pPage Pointer to the physical guest page tracking structure.
1082 * @param a_uState The new state value.
1083 */
1084#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1085 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1086
1087/**
1088 * Checks if the page has any virtual access handlers.
1089 * @returns true/false
1090 * @param a_pPage Pointer to the physical guest page tracking structure.
1091 */
1092#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1093 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1094
1095/**
1096 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1097 * virtual handlers.
1098 * @returns true/false
1099 * @param a_pPage Pointer to the physical guest page tracking structure.
1100 */
1101#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1102 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1103
1104
1105/**
1106 * Checks if the page has any access handlers, including temporarily disabled ones.
1107 * @returns true/false
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 */
1110#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1111# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1112 ( ((a_pPage)->au32[2] & UINT16_C(0x0303)) != 0 )
1113#else
1114# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1115 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1116 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1117#endif
1118
1119/**
1120 * Checks if the page has any active access handlers.
1121 * @returns true/false
1122 * @param a_pPage Pointer to the physical guest page tracking structure.
1123 */
1124#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1125# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1126 ( ((a_pPage)->au32[2] & UINT16_C(0x0202)) != 0 )
1127#else
1128# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1129 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1130 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1131#endif
1132
1133/**
1134 * Checks if the page has any active access handlers catching all accesses.
1135 * @returns true/false
1136 * @param a_pPage Pointer to the physical guest page tracking structure.
1137 */
1138#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1139# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1140 ( ( ((a_pPage)->au8[8] | (a_pPage)->au8[9]) & UINT8_C(0x3) ) \
1141 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1142#else
1143# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1144 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1145 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1146#endif
1147
1148
1149/** @def PGM_PAGE_GET_TRACKING
1150 * Gets the packed shadow page pool tracking data associated with a guest page.
1151 * @returns uint16_t containing the data.
1152 * @param a_pPage Pointer to the physical guest page tracking structure.
1153 */
1154#define PGM_PAGE_GET_TRACKING(a_pPage) ( (a_pPage)->s.u16TrackingY )
1155
1156/** @def PGM_PAGE_SET_TRACKING
1157 * Sets the packed shadow page pool tracking data associated with a guest page.
1158 * @param a_pPage Pointer to the physical guest page tracking structure.
1159 * @param a_u16TrackingData The tracking data to store.
1160 */
1161#define PGM_PAGE_SET_TRACKING(a_pPage, a_u16TrackingData) \
1162 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); } while (0)
1163
1164/** @def PGM_PAGE_GET_TD_CREFS
1165 * Gets the @a cRefs tracking data member.
1166 * @returns cRefs.
1167 * @param a_pPage Pointer to the physical guest page tracking structure.
1168 */
1169#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1170 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1171
1172/** @def PGM_PAGE_GET_TD_IDX
1173 * Gets the @a idx tracking data member.
1174 * @returns idx.
1175 * @param a_pPage Pointer to the physical guest page tracking structure.
1176 */
1177#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1178 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1179
1180
1181/** Max number of locks on a page. */
1182#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1183
1184/** Get the read lock count.
1185 * @returns count.
1186 * @param a_pPage Pointer to the physical guest page tracking structure.
1187 */
1188#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1189
1190/** Get the write lock count.
1191 * @returns count.
1192 * @param a_pPage Pointer to the physical guest page tracking structure.
1193 */
1194#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1195
1196/** Decrement the read lock counter.
1197 * @param a_pPage Pointer to the physical guest page tracking structure.
1198 */
1199#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1200
1201/** Decrement the write lock counter.
1202 * @param a_pPage Pointer to the physical guest page tracking structure.
1203 */
1204#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1205
1206/** Increment the read lock counter.
1207 * @param a_pPage Pointer to the physical guest page tracking structure.
1208 */
1209#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1210
1211/** Increment the write lock counter.
1212 * @param a_pPage Pointer to the physical guest page tracking structure.
1213 */
1214#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1215
1216
1217#if 0
1218/** Enables sanity checking of write monitoring using CRC-32. */
1219# define PGMLIVESAVERAMPAGE_WITH_CRC32
1220#endif
1221
1222/**
1223 * Per page live save tracking data.
1224 */
1225typedef struct PGMLIVESAVERAMPAGE
1226{
1227 /** Number of times it has been dirtied. */
1228 uint32_t cDirtied : 24;
1229 /** Whether it is currently dirty. */
1230 uint32_t fDirty : 1;
1231 /** Ignore the page.
1232 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1233 * deal with these after pausing the VM and DevPCI have said it bit about
1234 * remappings. */
1235 uint32_t fIgnore : 1;
1236 /** Was a ZERO page last time around. */
1237 uint32_t fZero : 1;
1238 /** Was a SHARED page last time around. */
1239 uint32_t fShared : 1;
1240 /** Whether the page is/was write monitored in a previous pass. */
1241 uint32_t fWriteMonitored : 1;
1242 /** Whether the page is/was write monitored earlier in this pass. */
1243 uint32_t fWriteMonitoredJustNow : 1;
1244 /** Bits reserved for future use. */
1245 uint32_t u2Reserved : 2;
1246#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1247 /** CRC-32 for the page. This is for internal consistency checks. */
1248 uint32_t u32Crc;
1249#endif
1250} PGMLIVESAVERAMPAGE;
1251#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1252AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1253#else
1254AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1255#endif
1256/** Pointer to the per page live save tracking data. */
1257typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1258
1259/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1260#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1261
1262
1263/** Enables the RAM range search trees. */
1264#define PGM_USE_RAMRANGE_SEARCH_TREES
1265
1266/**
1267 * RAM range for GC Phys to HC Phys conversion.
1268 *
1269 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1270 * conversions too, but we'll let MM handle that for now.
1271 *
1272 * This structure is used by linked lists in both GC and HC.
1273 */
1274typedef struct PGMRAMRANGE
1275{
1276 /** Start of the range. Page aligned. */
1277 RTGCPHYS GCPhys;
1278 /** Size of the range. (Page aligned of course). */
1279 RTGCPHYS cb;
1280 /** Pointer to the next RAM range - for R3. */
1281 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1282 /** Pointer to the next RAM range - for R0. */
1283 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1284 /** Pointer to the next RAM range - for RC. */
1285 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1286 /** PGM_RAM_RANGE_FLAGS_* flags. */
1287 uint32_t fFlags;
1288 /** Last address in the range (inclusive). Page aligned (-1). */
1289 RTGCPHYS GCPhysLast;
1290 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1291 R3PTRTYPE(void *) pvR3;
1292 /** Live save per page tracking data. */
1293 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1294 /** The range description. */
1295 R3PTRTYPE(const char *) pszDesc;
1296 /** Pointer to self - R0 pointer. */
1297 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1298 /** Pointer to self - RC pointer. */
1299 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1300
1301#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1302 /** Alignment padding. */
1303 RTRCPTR Alignment0;
1304 /** Pointer to the left search three node - ring-3 context. */
1305 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1306 /** Pointer to the right search three node - ring-3 context. */
1307 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1308 /** Pointer to the left search three node - ring-0 context. */
1309 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1310 /** Pointer to the right search three node - ring-0 context. */
1311 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1312 /** Pointer to the left search three node - raw-mode context. */
1313 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1314 /** Pointer to the right search three node - raw-mode context. */
1315 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1316#endif
1317
1318 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1319#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1320# if HC_ARCH_BITS == 32
1321 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1322# endif
1323#else
1324 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1325#endif
1326 /** Array of physical guest page tracking structures. */
1327 PGMPAGE aPages[1];
1328} PGMRAMRANGE;
1329/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1330typedef PGMRAMRANGE *PPGMRAMRANGE;
1331
1332/** @name PGMRAMRANGE::fFlags
1333 * @{ */
1334/** The RAM range is floating around as an independent guest mapping. */
1335#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1336/** Ad hoc RAM range for an ROM mapping. */
1337#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1338/** Ad hoc RAM range for an MMIO mapping. */
1339#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1340/** Ad hoc RAM range for an MMIO2 mapping. */
1341#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1342/** @} */
1343
1344/** Tests if a RAM range is an ad hoc one or not.
1345 * @returns true/false.
1346 * @param pRam The RAM range.
1347 */
1348#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1349 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1350
1351/** The number of entries in the RAM range TLBs (there is one for each
1352 * context). Must be a power of two. */
1353#define PGM_RAMRANGE_TLB_ENTRIES 8
1354
1355/**
1356 * Calculates the RAM range TLB index for the physical address.
1357 *
1358 * @returns RAM range TLB index.
1359 * @param GCPhys The guest physical address.
1360 */
1361#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1362
1363
1364
1365/**
1366 * Per page tracking structure for ROM image.
1367 *
1368 * A ROM image may have a shadow page, in which case we may have two pages
1369 * backing it. This structure contains the PGMPAGE for both while
1370 * PGMRAMRANGE have a copy of the active one. It is important that these
1371 * aren't out of sync in any regard other than page pool tracking data.
1372 */
1373typedef struct PGMROMPAGE
1374{
1375 /** The page structure for the virgin ROM page. */
1376 PGMPAGE Virgin;
1377 /** The page structure for the shadow RAM page. */
1378 PGMPAGE Shadow;
1379 /** The current protection setting. */
1380 PGMROMPROT enmProt;
1381 /** Live save status information. Makes use of unused alignment space. */
1382 struct
1383 {
1384 /** The previous protection value. */
1385 uint8_t u8Prot;
1386 /** Written to flag set by the handler. */
1387 bool fWrittenTo;
1388 /** Whether the shadow page is dirty or not. */
1389 bool fDirty;
1390 /** Whether it was dirtied in the recently. */
1391 bool fDirtiedRecently;
1392 } LiveSave;
1393} PGMROMPAGE;
1394AssertCompileSizeAlignment(PGMROMPAGE, 8);
1395/** Pointer to a ROM page tracking structure. */
1396typedef PGMROMPAGE *PPGMROMPAGE;
1397
1398
1399/**
1400 * A registered ROM image.
1401 *
1402 * This is needed to keep track of ROM image since they generally intrude
1403 * into a PGMRAMRANGE. It also keeps track of additional info like the
1404 * two page sets (read-only virgin and read-write shadow), the current
1405 * state of each page.
1406 *
1407 * Because access handlers cannot easily be executed in a different
1408 * context, the ROM ranges needs to be accessible and in all contexts.
1409 */
1410typedef struct PGMROMRANGE
1411{
1412 /** Pointer to the next range - R3. */
1413 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1414 /** Pointer to the next range - R0. */
1415 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1416 /** Pointer to the next range - RC. */
1417 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1418 /** Pointer alignment */
1419 RTRCPTR RCPtrAlignment;
1420 /** Address of the range. */
1421 RTGCPHYS GCPhys;
1422 /** Address of the last byte in the range. */
1423 RTGCPHYS GCPhysLast;
1424 /** Size of the range. */
1425 RTGCPHYS cb;
1426 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1427 uint32_t fFlags;
1428 /** The saved state range ID. */
1429 uint8_t idSavedState;
1430 /** Alignment padding. */
1431 uint8_t au8Alignment[3];
1432 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1433 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1434 /** The size bits pvOriginal points to. */
1435 uint32_t cbOriginal;
1436 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1437 * This is used for strictness checks. */
1438 R3PTRTYPE(const void *) pvOriginal;
1439 /** The ROM description. */
1440 R3PTRTYPE(const char *) pszDesc;
1441 /** The per page tracking structures. */
1442 PGMROMPAGE aPages[1];
1443} PGMROMRANGE;
1444/** Pointer to a ROM range. */
1445typedef PGMROMRANGE *PPGMROMRANGE;
1446
1447
1448/**
1449 * Live save per page data for an MMIO2 page.
1450 *
1451 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1452 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1453 * CRC-32 for detecting changes as well as special handling of zero pages. This
1454 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1455 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1456 * because of speed (2.5x and 6x slower).)
1457 *
1458 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1459 * save but normally is disabled. Since we can write monitor guest
1460 * accesses on our own, we only need this for host accesses. Shouldn't be
1461 * too difficult for DevVGA, VMMDev might be doable, the planned
1462 * networking fun will be fun since it involves ring-0.
1463 */
1464typedef struct PGMLIVESAVEMMIO2PAGE
1465{
1466 /** Set if the page is considered dirty. */
1467 bool fDirty;
1468 /** The number of scans this page has remained unchanged for.
1469 * Only updated for dirty pages. */
1470 uint8_t cUnchangedScans;
1471 /** Whether this page was zero at the last scan. */
1472 bool fZero;
1473 /** Alignment padding. */
1474 bool fReserved;
1475 /** CRC-32 for the first half of the page.
1476 * This is used together with u32CrcH2 to quickly detect changes in the page
1477 * during the non-final passes. */
1478 uint32_t u32CrcH1;
1479 /** CRC-32 for the second half of the page. */
1480 uint32_t u32CrcH2;
1481 /** SHA-1 for the saved page.
1482 * This is used in the final pass to skip pages without changes. */
1483 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1484} PGMLIVESAVEMMIO2PAGE;
1485/** Pointer to a live save status data for an MMIO2 page. */
1486typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1487
1488/**
1489 * A registered MMIO2 (= Device RAM) range.
1490 *
1491 * There are a few reason why we need to keep track of these
1492 * registrations. One of them is the deregistration & cleanup stuff,
1493 * while another is that the PGMRAMRANGE associated with such a region may
1494 * have to be removed from the ram range list.
1495 *
1496 * Overlapping with a RAM range has to be 100% or none at all. The pages
1497 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1498 * will be raised if a partial overlap or an overlap of ROM pages is
1499 * encountered. On an overlap we will free all the existing RAM pages and
1500 * put in the ram range pages instead.
1501 */
1502typedef struct PGMMMIO2RANGE
1503{
1504 /** The owner of the range. (a device) */
1505 PPDMDEVINSR3 pDevInsR3;
1506 /** Pointer to the ring-3 mapping of the allocation. */
1507 RTR3PTR pvR3;
1508 /** Pointer to the next range - R3. */
1509 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1510 /** Whether it's mapped or not. */
1511 bool fMapped;
1512 /** Whether it's overlapping or not. */
1513 bool fOverlapping;
1514 /** The PCI region number.
1515 * @remarks This ASSUMES that nobody will ever really need to have multiple
1516 * PCI devices with matching MMIO region numbers on a single device. */
1517 uint8_t iRegion;
1518 /** The saved state range ID. */
1519 uint8_t idSavedState;
1520 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1521 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1522 /** Live save per page tracking data. */
1523 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1524 /** The associated RAM range. */
1525 PGMRAMRANGE RamRange;
1526} PGMMMIO2RANGE;
1527/** Pointer to a MMIO2 range. */
1528typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1529
1530
1531
1532
1533/**
1534 * PGMPhysRead/Write cache entry
1535 */
1536typedef struct PGMPHYSCACHEENTRY
1537{
1538 /** R3 pointer to physical page. */
1539 R3PTRTYPE(uint8_t *) pbR3;
1540 /** GC Physical address for cache entry */
1541 RTGCPHYS GCPhys;
1542#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1543 RTGCPHYS u32Padding0; /**< alignment padding. */
1544#endif
1545} PGMPHYSCACHEENTRY;
1546
1547/**
1548 * PGMPhysRead/Write cache to reduce REM memory access overhead
1549 */
1550typedef struct PGMPHYSCACHE
1551{
1552 /** Bitmap of valid cache entries */
1553 uint64_t aEntries;
1554 /** Cache entries */
1555 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1556} PGMPHYSCACHE;
1557
1558
1559/** Pointer to an allocation chunk ring-3 mapping. */
1560typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1561/** Pointer to an allocation chunk ring-3 mapping pointer. */
1562typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1563
1564/**
1565 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1566 *
1567 * The primary tree (Core) uses the chunk id as key.
1568 */
1569typedef struct PGMCHUNKR3MAP
1570{
1571 /** The key is the chunk id. */
1572 AVLU32NODECORE Core;
1573 /** The current age thingy. */
1574 uint32_t iAge;
1575 /** The current reference count. */
1576 uint32_t volatile cRefs;
1577 /** The current permanent reference count. */
1578 uint32_t volatile cPermRefs;
1579 /** The mapping address. */
1580 void *pv;
1581} PGMCHUNKR3MAP;
1582
1583/**
1584 * Allocation chunk ring-3 mapping TLB entry.
1585 */
1586typedef struct PGMCHUNKR3MAPTLBE
1587{
1588 /** The chunk id. */
1589 uint32_t volatile idChunk;
1590#if HC_ARCH_BITS == 64
1591 uint32_t u32Padding; /**< alignment padding. */
1592#endif
1593 /** The chunk map. */
1594#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1595 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1596#else
1597 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1598#endif
1599} PGMCHUNKR3MAPTLBE;
1600/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1601typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1602
1603/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1604 * @remark Must be a power of two value. */
1605#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1606
1607/**
1608 * Allocation chunk ring-3 mapping TLB.
1609 *
1610 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1611 * At first glance this might look kinda odd since AVL trees are
1612 * supposed to give the most optimal lookup times of all trees
1613 * due to their balancing. However, take a tree with 1023 nodes
1614 * in it, that's 10 levels, meaning that most searches has to go
1615 * down 9 levels before they find what they want. This isn't fast
1616 * compared to a TLB hit. There is the factor of cache misses,
1617 * and of course the problem with trees and branch prediction.
1618 * This is why we use TLBs in front of most of the trees.
1619 *
1620 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1621 * difficult when we switch to the new inlined AVL trees (from kStuff).
1622 */
1623typedef struct PGMCHUNKR3MAPTLB
1624{
1625 /** The TLB entries. */
1626 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1627} PGMCHUNKR3MAPTLB;
1628
1629/**
1630 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1631 * @returns Chunk TLB index.
1632 * @param idChunk The Chunk ID.
1633 */
1634#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1635
1636
1637/**
1638 * Ring-3 guest page mapping TLB entry.
1639 * @remarks used in ring-0 as well at the moment.
1640 */
1641typedef struct PGMPAGER3MAPTLBE
1642{
1643 /** Address of the page. */
1644 RTGCPHYS volatile GCPhys;
1645 /** The guest page. */
1646#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1647 R3PTRTYPE(PPGMPAGE) volatile pPage;
1648#else
1649 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1650#endif
1651 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1652#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1653 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1654#else
1655 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1656#endif
1657 /** The address */
1658#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1659 R3PTRTYPE(void *) volatile pv;
1660#else
1661 R3R0PTRTYPE(void *) volatile pv;
1662#endif
1663#if HC_ARCH_BITS == 32
1664 uint32_t u32Padding; /**< alignment padding. */
1665#endif
1666} PGMPAGER3MAPTLBE;
1667/** Pointer to an entry in the HC physical TLB. */
1668typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1669
1670
1671/** The number of entries in the ring-3 guest page mapping TLB.
1672 * @remarks The value must be a power of two. */
1673#define PGM_PAGER3MAPTLB_ENTRIES 256
1674
1675/**
1676 * Ring-3 guest page mapping TLB.
1677 * @remarks used in ring-0 as well at the moment.
1678 */
1679typedef struct PGMPAGER3MAPTLB
1680{
1681 /** The TLB entries. */
1682 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1683} PGMPAGER3MAPTLB;
1684/** Pointer to the ring-3 guest page mapping TLB. */
1685typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1686
1687/**
1688 * Calculates the index of the TLB entry for the specified guest page.
1689 * @returns Physical TLB index.
1690 * @param GCPhys The guest physical address.
1691 */
1692#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1693
1694
1695/**
1696 * Raw-mode context dynamic mapping cache entry.
1697 *
1698 * Because of raw-mode context being reloctable and all relocations are applied
1699 * in ring-3, this has to be defined here and be RC specific.
1700 *
1701 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1702 */
1703typedef struct PGMRCDYNMAPENTRY
1704{
1705 /** The physical address of the currently mapped page.
1706 * This is duplicate for three reasons: cache locality, cache policy of the PT
1707 * mappings and sanity checks. */
1708 RTHCPHYS HCPhys;
1709 /** Pointer to the page. */
1710 RTRCPTR pvPage;
1711 /** The number of references. */
1712 int32_t volatile cRefs;
1713 /** PTE pointer union. */
1714 struct PGMRCDYNMAPENTRY_PPTE
1715 {
1716 /** PTE pointer, 32-bit legacy version. */
1717 RCPTRTYPE(PX86PTE) pLegacy;
1718 /** PTE pointer, PAE version. */
1719 RCPTRTYPE(PX86PTEPAE) pPae;
1720 } uPte;
1721} PGMRCDYNMAPENTRY;
1722/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1723typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1724
1725
1726/**
1727 * Dynamic mapping cache for the raw-mode context.
1728 *
1729 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1730 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1731 * so that we can perform relocations from PGMR3Relocate. This has the
1732 * consequence that we must have separate ring-0 and raw-mode context versions
1733 * of this struct even if they share the basic elements.
1734 *
1735 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1736 */
1737typedef struct PGMRCDYNMAP
1738{
1739 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1740 uint32_t u32Magic;
1741 /** Array for tracking and managing the pages. */
1742 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1743 /** The cache size given as a number of pages. */
1744 uint32_t cPages;
1745 /** The current load.
1746 * This does not include guard pages. */
1747 uint32_t cLoad;
1748 /** The max load ever.
1749 * This is maintained to get trigger adding of more mapping space. */
1750 uint32_t cMaxLoad;
1751 /** The number of guard pages. */
1752 uint32_t cGuardPages;
1753 /** The number of users (protected by hInitLock). */
1754 uint32_t cUsers;
1755} PGMRCDYNMAP;
1756/** Pointer to the dynamic cache for the raw-mode context. */
1757typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1758
1759
1760/**
1761 * Mapping cache usage set entry.
1762 *
1763 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1764 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1765 * cache. If it's extended to include ring-3, well, then something
1766 * will have be changed here...
1767 */
1768typedef struct PGMMAPSETENTRY
1769{
1770 /** Pointer to the page. */
1771#ifndef IN_RC
1772 RTR0PTR pvPage;
1773#else
1774 RTRCPTR pvPage;
1775# if HC_ARCH_BITS == 64
1776 uint32_t u32Alignment2;
1777# endif
1778#endif
1779 /** The mapping cache index. */
1780 uint16_t iPage;
1781 /** The number of references.
1782 * The max is UINT16_MAX - 1. */
1783 uint16_t cRefs;
1784 /** The number inlined references.
1785 * The max is UINT16_MAX - 1. */
1786 uint16_t cInlinedRefs;
1787 /** Unreferences. */
1788 uint16_t cUnrefs;
1789
1790#if HC_ARCH_BITS == 32
1791 uint32_t u32Alignment1;
1792#endif
1793 /** The physical address for this entry. */
1794 RTHCPHYS HCPhys;
1795} PGMMAPSETENTRY;
1796AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1797AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1798/** Pointer to a mapping cache usage set entry. */
1799typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1800
1801/**
1802 * Mapping cache usage set.
1803 *
1804 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1805 * done during exits / traps. The set is
1806 */
1807typedef struct PGMMAPSET
1808{
1809 /** The number of occupied entries.
1810 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1811 * dynamic mappings. */
1812 uint32_t cEntries;
1813 /** The start of the current subset.
1814 * This is UINT32_MAX if no subset is currently open. */
1815 uint32_t iSubset;
1816 /** The index of the current CPU, only valid if the set is open. */
1817 int32_t iCpu;
1818 uint32_t alignment;
1819 /** The entries. */
1820 PGMMAPSETENTRY aEntries[64];
1821 /** HCPhys -> iEntry fast lookup table.
1822 * Use PGMMAPSET_HASH for hashing.
1823 * The entries may or may not be valid, check against cEntries. */
1824 uint8_t aiHashTable[128];
1825} PGMMAPSET;
1826AssertCompileSizeAlignment(PGMMAPSET, 8);
1827/** Pointer to the mapping cache set. */
1828typedef PGMMAPSET *PPGMMAPSET;
1829
1830/** PGMMAPSET::cEntries value for a closed set. */
1831#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1832
1833/** Hash function for aiHashTable. */
1834#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1835
1836
1837/** @name Context neutral page mapper TLB.
1838 *
1839 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1840 * code is writting in a kind of context neutral way. Time will show whether
1841 * this actually makes sense or not...
1842 *
1843 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1844 * context ends up using a global mapping cache on some platforms
1845 * (darwin).
1846 *
1847 * @{ */
1848/** @typedef PPGMPAGEMAPTLB
1849 * The page mapper TLB pointer type for the current context. */
1850/** @typedef PPGMPAGEMAPTLB
1851 * The page mapper TLB entry pointer type for the current context. */
1852/** @typedef PPGMPAGEMAPTLB
1853 * The page mapper TLB entry pointer pointer type for the current context. */
1854/** @def PGM_PAGEMAPTLB_ENTRIES
1855 * The number of TLB entries in the page mapper TLB for the current context. */
1856/** @def PGM_PAGEMAPTLB_IDX
1857 * Calculate the TLB index for a guest physical address.
1858 * @returns The TLB index.
1859 * @param GCPhys The guest physical address. */
1860/** @typedef PPGMPAGEMAP
1861 * Pointer to a page mapper unit for current context. */
1862/** @typedef PPPGMPAGEMAP
1863 * Pointer to a page mapper unit pointer for current context. */
1864#ifdef IN_RC
1865// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1866// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1867// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1868# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1869# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1870 typedef void * PPGMPAGEMAP;
1871 typedef void ** PPPGMPAGEMAP;
1872//#elif IN_RING0
1873// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1874// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1875// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1876//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1877//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1878// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1879// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1880#else
1881 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1882 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1883 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1884# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1885# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1886 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1887 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1888#endif
1889/** @} */
1890
1891
1892/** @name PGM Pool Indexes.
1893 * Aka. the unique shadow page identifier.
1894 * @{ */
1895/** NIL page pool IDX. */
1896#define NIL_PGMPOOL_IDX 0
1897/** The first normal index. */
1898#define PGMPOOL_IDX_FIRST_SPECIAL 1
1899/** Page directory (32-bit root). */
1900#define PGMPOOL_IDX_PD 1
1901/** Page Directory Pointer Table (PAE root). */
1902#define PGMPOOL_IDX_PDPT 2
1903/** AMD64 CR3 level index.*/
1904#define PGMPOOL_IDX_AMD64_CR3 3
1905/** Nested paging root.*/
1906#define PGMPOOL_IDX_NESTED_ROOT 4
1907/** The first normal index. */
1908#define PGMPOOL_IDX_FIRST 5
1909/** The last valid index. (inclusive, 14 bits) */
1910#define PGMPOOL_IDX_LAST 0x3fff
1911/** @} */
1912
1913/** The NIL index for the parent chain. */
1914#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1915#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1916
1917/**
1918 * Node in the chain linking a shadowed page to it's parent (user).
1919 */
1920#pragma pack(1)
1921typedef struct PGMPOOLUSER
1922{
1923 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1924 uint16_t iNext;
1925 /** The user page index. */
1926 uint16_t iUser;
1927 /** Index into the user table. */
1928 uint32_t iUserTable;
1929} PGMPOOLUSER, *PPGMPOOLUSER;
1930typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1931#pragma pack()
1932
1933
1934/** The NIL index for the phys ext chain. */
1935#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1936/** The NIL pte index for a phys ext chain slot. */
1937#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1938
1939/**
1940 * Node in the chain of physical cross reference extents.
1941 * @todo Calling this an 'extent' is not quite right, find a better name.
1942 * @todo find out the optimal size of the aidx array
1943 */
1944#pragma pack(1)
1945typedef struct PGMPOOLPHYSEXT
1946{
1947 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1948 uint16_t iNext;
1949 /** Alignment. */
1950 uint16_t u16Align;
1951 /** The user page index. */
1952 uint16_t aidx[3];
1953 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1954 uint16_t apte[3];
1955} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1956typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1957#pragma pack()
1958
1959
1960/**
1961 * The kind of page that's being shadowed.
1962 */
1963typedef enum PGMPOOLKIND
1964{
1965 /** The virtual invalid 0 entry. */
1966 PGMPOOLKIND_INVALID = 0,
1967 /** The entry is free (=unused). */
1968 PGMPOOLKIND_FREE,
1969
1970 /** Shw: 32-bit page table; Gst: no paging */
1971 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1972 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1973 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1974 /** Shw: 32-bit page table; Gst: 4MB page. */
1975 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1976 /** Shw: PAE page table; Gst: no paging */
1977 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1978 /** Shw: PAE page table; Gst: 32-bit page table. */
1979 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1980 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1981 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1982 /** Shw: PAE page table; Gst: PAE page table. */
1983 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1984 /** Shw: PAE page table; Gst: 2MB page. */
1985 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1986
1987 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1988 PGMPOOLKIND_32BIT_PD,
1989 /** Shw: 32-bit page directory. Gst: no paging. */
1990 PGMPOOLKIND_32BIT_PD_PHYS,
1991 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1992 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1993 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1994 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1995 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1996 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1997 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1998 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1999 /** Shw: PAE page directory; Gst: PAE page directory. */
2000 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2001 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2002 PGMPOOLKIND_PAE_PD_PHYS,
2003
2004 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2005 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2006 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2007 PGMPOOLKIND_PAE_PDPT,
2008 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2009 PGMPOOLKIND_PAE_PDPT_PHYS,
2010
2011 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2012 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2013 /** Shw: 64-bit page directory pointer table; Gst: no paging */
2014 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2015 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2016 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2017 /** Shw: 64-bit page directory table; Gst: no paging */
2018 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2019
2020 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2021 PGMPOOLKIND_64BIT_PML4,
2022
2023 /** Shw: EPT page directory pointer table; Gst: no paging */
2024 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2025 /** Shw: EPT page directory table; Gst: no paging */
2026 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2027 /** Shw: EPT page table; Gst: no paging */
2028 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2029
2030 /** Shw: Root Nested paging table. */
2031 PGMPOOLKIND_ROOT_NESTED,
2032
2033 /** The last valid entry. */
2034 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2035} PGMPOOLKIND;
2036
2037/**
2038 * The access attributes of the page; only applies to big pages.
2039 */
2040typedef enum
2041{
2042 PGMPOOLACCESS_DONTCARE = 0,
2043 PGMPOOLACCESS_USER_RW,
2044 PGMPOOLACCESS_USER_R,
2045 PGMPOOLACCESS_USER_RW_NX,
2046 PGMPOOLACCESS_USER_R_NX,
2047 PGMPOOLACCESS_SUPERVISOR_RW,
2048 PGMPOOLACCESS_SUPERVISOR_R,
2049 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2050 PGMPOOLACCESS_SUPERVISOR_R_NX
2051} PGMPOOLACCESS;
2052
2053/**
2054 * The tracking data for a page in the pool.
2055 */
2056typedef struct PGMPOOLPAGE
2057{
2058 /** AVL node code with the (R3) physical address of this page. */
2059 AVLOHCPHYSNODECORE Core;
2060 /** Pointer to the R3 mapping of the page. */
2061#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2062 R3PTRTYPE(void *) pvPageR3;
2063#else
2064 R3R0PTRTYPE(void *) pvPageR3;
2065#endif
2066 /** The guest physical address. */
2067#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2068 uint32_t Alignment0;
2069#endif
2070 RTGCPHYS GCPhys;
2071
2072 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2073 RTGCPTR pvLastAccessHandlerRip;
2074 RTGCPTR pvLastAccessHandlerFault;
2075 uint64_t cLastAccessHandlerCount;
2076
2077 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2078 uint8_t enmKind;
2079 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2080 uint8_t enmAccess;
2081 /** The index of this page. */
2082 uint16_t idx;
2083 /** The next entry in the list this page currently resides in.
2084 * It's either in the free list or in the GCPhys hash. */
2085 uint16_t iNext;
2086 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2087 uint16_t iUserHead;
2088 /** The number of present entries. */
2089 uint16_t cPresent;
2090 /** The first entry in the table which is present. */
2091 uint16_t iFirstPresent;
2092 /** The number of modifications to the monitored page. */
2093 uint16_t cModifications;
2094 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2095 uint16_t iModifiedNext;
2096 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2097 uint16_t iModifiedPrev;
2098 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2099 uint16_t iMonitoredNext;
2100 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2101 uint16_t iMonitoredPrev;
2102 /** The next page in the age list. */
2103 uint16_t iAgeNext;
2104 /** The previous page in the age list. */
2105 uint16_t iAgePrev;
2106 /** Used to indicate that the page is zeroed. */
2107 bool fZeroed;
2108 /** Used to indicate that a PT has non-global entries. */
2109 bool fSeenNonGlobal;
2110 /** Used to indicate that we're monitoring writes to the guest page. */
2111 bool fMonitored;
2112 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2113 * (All pages are in the age list.) */
2114 bool fCached;
2115 /** This is used by the R3 access handlers when invoked by an async thread.
2116 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2117 bool volatile fReusedFlushPending;
2118 /** Used to mark the page as dirty (write monitoring is temporarily
2119 * off). */
2120 bool fDirty;
2121
2122 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2123 uint32_t cLocked;
2124 uint32_t idxDirty;
2125 RTGCPTR pvDirtyFault;
2126} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2127/** Pointer to a const pool page. */
2128typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2129
2130
2131/** The hash table size. */
2132# define PGMPOOL_HASH_SIZE 0x40
2133/** The hash function. */
2134# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2135
2136
2137/**
2138 * The shadow page pool instance data.
2139 *
2140 * It's all one big allocation made at init time, except for the
2141 * pages that is. The user nodes follows immediately after the
2142 * page structures.
2143 */
2144typedef struct PGMPOOL
2145{
2146 /** The VM handle - R3 Ptr. */
2147 PVMR3 pVMR3;
2148 /** The VM handle - R0 Ptr. */
2149 PVMR0 pVMR0;
2150 /** The VM handle - RC Ptr. */
2151 PVMRC pVMRC;
2152 /** The max pool size. This includes the special IDs. */
2153 uint16_t cMaxPages;
2154 /** The current pool size. */
2155 uint16_t cCurPages;
2156 /** The head of the free page list. */
2157 uint16_t iFreeHead;
2158 /* Padding. */
2159 uint16_t u16Padding;
2160 /** Head of the chain of free user nodes. */
2161 uint16_t iUserFreeHead;
2162 /** The number of user nodes we've allocated. */
2163 uint16_t cMaxUsers;
2164 /** The number of present page table entries in the entire pool. */
2165 uint32_t cPresent;
2166 /** Pointer to the array of user nodes - RC pointer. */
2167 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2168 /** Pointer to the array of user nodes - R3 pointer. */
2169 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2170 /** Pointer to the array of user nodes - R0 pointer. */
2171 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2172 /** Head of the chain of free phys ext nodes. */
2173 uint16_t iPhysExtFreeHead;
2174 /** The number of user nodes we've allocated. */
2175 uint16_t cMaxPhysExts;
2176 /** Pointer to the array of physical xref extent - RC pointer. */
2177 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2178 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2179 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2180 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2181 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2182 /** Hash table for GCPhys addresses. */
2183 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2184 /** The head of the age list. */
2185 uint16_t iAgeHead;
2186 /** The tail of the age list. */
2187 uint16_t iAgeTail;
2188 /** Set if the cache is enabled. */
2189 bool fCacheEnabled;
2190 /** Alignment padding. */
2191 bool afPadding1[3];
2192 /** Head of the list of modified pages. */
2193 uint16_t iModifiedHead;
2194 /** The current number of modified pages. */
2195 uint16_t cModifiedPages;
2196 /** Access handler, RC. */
2197 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2198 /** Access handler, R0. */
2199 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2200 /** Access handler, R3. */
2201 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2202 /** The access handler description (R3 ptr). */
2203 R3PTRTYPE(const char *) pszAccessHandler;
2204# if HC_ARCH_BITS == 32
2205 /** Alignment padding. */
2206 uint32_t u32Padding2;
2207# endif
2208 /* Next available slot. */
2209 uint32_t idxFreeDirtyPage;
2210 /* Number of active dirty pages. */
2211 uint32_t cDirtyPages;
2212 /* Array of current dirty pgm pool page indices. */
2213 struct
2214 {
2215 uint16_t uIdx;
2216 uint16_t Alignment[3];
2217 uint64_t aPage[512];
2218 } aDirtyPages[16];
2219 /** The number of pages currently in use. */
2220 uint16_t cUsedPages;
2221#ifdef VBOX_WITH_STATISTICS
2222 /** The high water mark for cUsedPages. */
2223 uint16_t cUsedPagesHigh;
2224 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2225 /** Profiling pgmPoolAlloc(). */
2226 STAMPROFILEADV StatAlloc;
2227 /** Profiling pgmR3PoolClearDoIt(). */
2228 STAMPROFILE StatClearAll;
2229 /** Profiling pgmR3PoolReset(). */
2230 STAMPROFILE StatR3Reset;
2231 /** Profiling pgmPoolFlushPage(). */
2232 STAMPROFILE StatFlushPage;
2233 /** Profiling pgmPoolFree(). */
2234 STAMPROFILE StatFree;
2235 /** Counting explicit flushes by PGMPoolFlushPage(). */
2236 STAMCOUNTER StatForceFlushPage;
2237 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2238 STAMCOUNTER StatForceFlushDirtyPage;
2239 /** Counting flushes for reused pages. */
2240 STAMCOUNTER StatForceFlushReused;
2241 /** Profiling time spent zeroing pages. */
2242 STAMPROFILE StatZeroPage;
2243 /** Profiling of pgmPoolTrackDeref. */
2244 STAMPROFILE StatTrackDeref;
2245 /** Profiling pgmTrackFlushGCPhysPT. */
2246 STAMPROFILE StatTrackFlushGCPhysPT;
2247 /** Profiling pgmTrackFlushGCPhysPTs. */
2248 STAMPROFILE StatTrackFlushGCPhysPTs;
2249 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2250 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2251 /** Number of times we've been out of user records. */
2252 STAMCOUNTER StatTrackFreeUpOneUser;
2253 /** Nr of flushed entries. */
2254 STAMCOUNTER StatTrackFlushEntry;
2255 /** Nr of updated entries. */
2256 STAMCOUNTER StatTrackFlushEntryKeep;
2257 /** Profiling deref activity related tracking GC physical pages. */
2258 STAMPROFILE StatTrackDerefGCPhys;
2259 /** Number of linear searches for a HCPhys in the ram ranges. */
2260 STAMCOUNTER StatTrackLinearRamSearches;
2261 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2262 STAMCOUNTER StamTrackPhysExtAllocFailures;
2263 /** Profiling the RC/R0 access handler. */
2264 STAMPROFILE StatMonitorRZ;
2265 /** Times we've failed interpreting the instruction. */
2266 STAMCOUNTER StatMonitorRZEmulateInstr;
2267 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2268 STAMPROFILE StatMonitorRZFlushPage;
2269 /* Times we've detected a page table reinit. */
2270 STAMCOUNTER StatMonitorRZFlushReinit;
2271 /** Counting flushes for pages that are modified too often. */
2272 STAMCOUNTER StatMonitorRZFlushModOverflow;
2273 /** Times we've detected fork(). */
2274 STAMCOUNTER StatMonitorRZFork;
2275 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2276 STAMPROFILE StatMonitorRZHandled;
2277 /** Times we've failed interpreting a patch code instruction. */
2278 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2279 /** Times we've failed interpreting a patch code instruction during flushing. */
2280 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2281 /** The number of times we've seen rep prefixes we can't handle. */
2282 STAMCOUNTER StatMonitorRZRepPrefix;
2283 /** Profiling the REP STOSD cases we've handled. */
2284 STAMPROFILE StatMonitorRZRepStosd;
2285 /** Nr of handled PT faults. */
2286 STAMCOUNTER StatMonitorRZFaultPT;
2287 /** Nr of handled PD faults. */
2288 STAMCOUNTER StatMonitorRZFaultPD;
2289 /** Nr of handled PDPT faults. */
2290 STAMCOUNTER StatMonitorRZFaultPDPT;
2291 /** Nr of handled PML4 faults. */
2292 STAMCOUNTER StatMonitorRZFaultPML4;
2293
2294 /** Profiling the R3 access handler. */
2295 STAMPROFILE StatMonitorR3;
2296 /** Times we've failed interpreting the instruction. */
2297 STAMCOUNTER StatMonitorR3EmulateInstr;
2298 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2299 STAMPROFILE StatMonitorR3FlushPage;
2300 /* Times we've detected a page table reinit. */
2301 STAMCOUNTER StatMonitorR3FlushReinit;
2302 /** Counting flushes for pages that are modified too often. */
2303 STAMCOUNTER StatMonitorR3FlushModOverflow;
2304 /** Times we've detected fork(). */
2305 STAMCOUNTER StatMonitorR3Fork;
2306 /** Profiling the R3 access we've handled (except REP STOSD). */
2307 STAMPROFILE StatMonitorR3Handled;
2308 /** The number of times we've seen rep prefixes we can't handle. */
2309 STAMCOUNTER StatMonitorR3RepPrefix;
2310 /** Profiling the REP STOSD cases we've handled. */
2311 STAMPROFILE StatMonitorR3RepStosd;
2312 /** Nr of handled PT faults. */
2313 STAMCOUNTER StatMonitorR3FaultPT;
2314 /** Nr of handled PD faults. */
2315 STAMCOUNTER StatMonitorR3FaultPD;
2316 /** Nr of handled PDPT faults. */
2317 STAMCOUNTER StatMonitorR3FaultPDPT;
2318 /** Nr of handled PML4 faults. */
2319 STAMCOUNTER StatMonitorR3FaultPML4;
2320 /** The number of times we're called in an async thread an need to flush. */
2321 STAMCOUNTER StatMonitorR3Async;
2322 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2323 STAMCOUNTER StatResetDirtyPages;
2324 /** Times we've called pgmPoolAddDirtyPage. */
2325 STAMCOUNTER StatDirtyPage;
2326 /** Times we've had to flush duplicates for dirty page management. */
2327 STAMCOUNTER StatDirtyPageDupFlush;
2328 /** Times we've had to flush because of overflow. */
2329 STAMCOUNTER StatDirtyPageOverFlowFlush;
2330
2331 /** The high water mark for cModifiedPages. */
2332 uint16_t cModifiedPagesHigh;
2333 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2334
2335 /** The number of cache hits. */
2336 STAMCOUNTER StatCacheHits;
2337 /** The number of cache misses. */
2338 STAMCOUNTER StatCacheMisses;
2339 /** The number of times we've got a conflict of 'kind' in the cache. */
2340 STAMCOUNTER StatCacheKindMismatches;
2341 /** Number of times we've been out of pages. */
2342 STAMCOUNTER StatCacheFreeUpOne;
2343 /** The number of cacheable allocations. */
2344 STAMCOUNTER StatCacheCacheable;
2345 /** The number of uncacheable allocations. */
2346 STAMCOUNTER StatCacheUncacheable;
2347#else
2348 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2349#endif
2350 /** The AVL tree for looking up a page by its HC physical address. */
2351 AVLOHCPHYSTREE HCPhysTree;
2352 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2353 /** Array of pages. (cMaxPages in length)
2354 * The Id is the index into thist array.
2355 */
2356 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2357} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2358AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2359AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2360AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2361#ifdef VBOX_WITH_STATISTICS
2362AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2363#endif
2364AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2365
2366
2367/** @def PGMPOOL_PAGE_2_PTR
2368 * Maps a pool page pool into the current context.
2369 *
2370 * @returns VBox status code.
2371 * @param a_pVM The VM handle.
2372 * @param a_pPage The pool page.
2373 *
2374 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2375 * small page window employeed by that function. Be careful.
2376 * @remark There is no need to assert on the result.
2377 */
2378#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2379# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2380#elif defined(VBOX_STRICT)
2381# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage)
2382DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage)
2383{
2384 Assert(a_pPage && a_pPage->pvPageR3);
2385 return a_pPage->pvPageR3;
2386}
2387#else
2388# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2389#endif
2390
2391
2392/** @def PGMPOOL_PAGE_2_PTR_V2
2393 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2394 *
2395 * @returns VBox status code.
2396 * @param a_pVM The VM handle.
2397 * @param a_pVCpu The current CPU.
2398 * @param a_pPage The pool page.
2399 *
2400 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2401 * small page window employeed by that function. Be careful.
2402 * @remark There is no need to assert on the result.
2403 */
2404#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2405# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2406#else
2407# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2408#endif
2409
2410
2411/** @name Per guest page tracking data.
2412 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2413 * is to use more bits for it and split it up later on. But for now we'll play
2414 * safe and change as little as possible.
2415 *
2416 * The 16-bit word has two parts:
2417 *
2418 * The first 14-bit forms the @a idx field. It is either the index of a page in
2419 * the shadow page pool, or and index into the extent list.
2420 *
2421 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2422 * shadow page pool references to the page. If cRefs equals
2423 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2424 * (misnomer) table and not the shadow page pool.
2425 *
2426 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2427 * the 16-bit word.
2428 *
2429 * @{ */
2430/** The shift count for getting to the cRefs part. */
2431#define PGMPOOL_TD_CREFS_SHIFT 14
2432/** The mask applied after shifting the tracking data down by
2433 * PGMPOOL_TD_CREFS_SHIFT. */
2434#define PGMPOOL_TD_CREFS_MASK 0x3
2435/** The cRefs value used to indicate that the idx is the head of a
2436 * physical cross reference list. */
2437#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2438/** The shift used to get idx. */
2439#define PGMPOOL_TD_IDX_SHIFT 0
2440/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2441#define PGMPOOL_TD_IDX_MASK 0x3fff
2442/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2443 * simply too many mappings of this page. */
2444#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2445
2446/** @def PGMPOOL_TD_MAKE
2447 * Makes a 16-bit tracking data word.
2448 *
2449 * @returns tracking data.
2450 * @param cRefs The @a cRefs field. Must be within bounds!
2451 * @param idx The @a idx field. Must also be within bounds! */
2452#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2453
2454/** @def PGMPOOL_TD_GET_CREFS
2455 * Get the @a cRefs field from a tracking data word.
2456 *
2457 * @returns The @a cRefs field
2458 * @param u16 The tracking data word.
2459 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2460 * non-zero @a u16. */
2461#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2462
2463/** @def PGMPOOL_TD_GET_IDX
2464 * Get the @a idx field from a tracking data word.
2465 *
2466 * @returns The @a idx field
2467 * @param u16 The tracking data word. */
2468#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2469/** @} */
2470
2471
2472/**
2473 * Trees are using self relative offsets as pointers.
2474 * So, all its data, including the root pointer, must be in the heap for HC and GC
2475 * to have the same layout.
2476 */
2477typedef struct PGMTREES
2478{
2479 /** Physical access handlers (AVL range+offsetptr tree). */
2480 AVLROGCPHYSTREE PhysHandlers;
2481 /** Virtual access handlers (AVL range + GC ptr tree). */
2482 AVLROGCPTRTREE VirtHandlers;
2483 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2484 AVLROGCPHYSTREE PhysToVirtHandlers;
2485 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2486 AVLROGCPTRTREE HyperVirtHandlers;
2487} PGMTREES;
2488/** Pointer to PGM trees. */
2489typedef PGMTREES *PPGMTREES;
2490
2491
2492/**
2493 * Page fault guest state for the AMD64 paging mode.
2494 */
2495typedef struct PGMPTWALKCORE
2496{
2497 /** The guest virtual address that is being resolved by the walk
2498 * (input). */
2499 RTGCPTR GCPtr;
2500
2501 /** The guest physical address that is the result of the walk.
2502 * @remarks only valid if fSucceeded is set. */
2503 RTGCPHYS GCPhys;
2504
2505 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2506 bool fSucceeded;
2507 /** The level problem arrised at.
2508 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2509 * level 8. This is 0 on success. */
2510 uint8_t uLevel;
2511 /** Set if the page isn't present. */
2512 bool fNotPresent;
2513 /** Encountered a bad physical address. */
2514 bool fBadPhysAddr;
2515 /** Set if there was reserved bit violations. */
2516 bool fRsvdError;
2517 /** Set if it involves a big page (2/4 MB). */
2518 bool fBigPage;
2519 /** Set if it involves a gigantic page (1 GB). */
2520 bool fGigantPage;
2521 /** The effect X86_PTE_US flag for the address. */
2522 bool fEffectiveUS;
2523 /** The effect X86_PTE_RW flag for the address. */
2524 bool fEffectiveRW;
2525 /** The effect X86_PTE_NX flag for the address. */
2526 bool fEffectiveNX;
2527} PGMPTWALKCORE;
2528
2529
2530/**
2531 * Guest page table walk for the AMD64 mode.
2532 */
2533typedef struct PGMPTWALKGSTAMD64
2534{
2535 /** The common core. */
2536 PGMPTWALKCORE Core;
2537
2538 PX86PML4 pPml4;
2539 PX86PML4E pPml4e;
2540 X86PML4E Pml4e;
2541
2542 PX86PDPT pPdpt;
2543 PX86PDPE pPdpe;
2544 X86PDPE Pdpe;
2545
2546 PX86PDPAE pPd;
2547 PX86PDEPAE pPde;
2548 X86PDEPAE Pde;
2549
2550 PX86PTPAE pPt;
2551 PX86PTEPAE pPte;
2552 X86PTEPAE Pte;
2553} PGMPTWALKGSTAMD64;
2554/** Pointer to a AMD64 guest page table walk. */
2555typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2556/** Pointer to a const AMD64 guest page table walk. */
2557typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2558
2559/**
2560 * Guest page table walk for the PAE mode.
2561 */
2562typedef struct PGMPTWALKGSTPAE
2563{
2564 /** The common core. */
2565 PGMPTWALKCORE Core;
2566
2567 PX86PDPT pPdpt;
2568 PX86PDPE pPdpe;
2569 X86PDPE Pdpe;
2570
2571 PX86PDPAE pPd;
2572 PX86PDEPAE pPde;
2573 X86PDEPAE Pde;
2574
2575 PX86PTPAE pPt;
2576 PX86PTEPAE pPte;
2577 X86PTEPAE Pte;
2578} PGMPTWALKGSTPAE;
2579/** Pointer to a PAE guest page table walk. */
2580typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2581/** Pointer to a const AMD64 guest page table walk. */
2582typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2583
2584/**
2585 * Guest page table walk for the 32-bit mode.
2586 */
2587typedef struct PGMPTWALKGST32BIT
2588{
2589 /** The common core. */
2590 PGMPTWALKCORE Core;
2591
2592 PX86PD pPd;
2593 PX86PDE pPde;
2594 X86PDE Pde;
2595
2596 PX86PT pPt;
2597 PX86PTE pPte;
2598 X86PTE Pte;
2599} PGMPTWALKGST32BIT;
2600/** Pointer to a 32-bit guest page table walk. */
2601typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2602/** Pointer to a const 32-bit guest page table walk. */
2603typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2604
2605
2606/** @name Paging mode macros
2607 * @{
2608 */
2609#ifdef IN_RC
2610# define PGM_CTX(a,b) a##RC##b
2611# define PGM_CTX_STR(a,b) a "GC" b
2612# define PGM_CTX_DECL(type) VMMRCDECL(type)
2613#else
2614# ifdef IN_RING3
2615# define PGM_CTX(a,b) a##R3##b
2616# define PGM_CTX_STR(a,b) a "R3" b
2617# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2618# else
2619# define PGM_CTX(a,b) a##R0##b
2620# define PGM_CTX_STR(a,b) a "R0" b
2621# define PGM_CTX_DECL(type) VMMDECL(type)
2622# endif
2623#endif
2624
2625#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2626#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2627#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2628#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2629#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2630#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2631#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2632#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2633#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2634#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2635#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2636#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2637#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2638#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2639#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2640#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2641#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2642
2643#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2644#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2645#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2646#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2647#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2648#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2649#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2650#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2651#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2652#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2653#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2654#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2655#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2656#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2657#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2658#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2659#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2660
2661/* Shw_Gst */
2662#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2663#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2664#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2665#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2666#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2667#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2668#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2669#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2670#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2671#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2672#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2673#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2674#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2675#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2676#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2677#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2678#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2679#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2680#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2681
2682#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2683#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2684#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2685#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2686#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2687#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2688#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2689#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2690#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2691#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2692#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2693#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2694#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2695#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2696#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2697#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2698#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2699#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2700#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2701#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2702#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2703#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2704#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2705#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2706#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2707#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2708#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2709#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2710#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2711#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2712#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2713#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2714#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2715#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2716#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2717#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2718#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2719
2720#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2721#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2722/** @} */
2723
2724/**
2725 * Data for each paging mode.
2726 */
2727typedef struct PGMMODEDATA
2728{
2729 /** The guest mode type. */
2730 uint32_t uGstType;
2731 /** The shadow mode type. */
2732 uint32_t uShwType;
2733
2734 /** @name Function pointers for Shadow paging.
2735 * @{
2736 */
2737 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2738 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2739 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2740 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2741
2742 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2743 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2744
2745 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2746 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2747 /** @} */
2748
2749 /** @name Function pointers for Guest paging.
2750 * @{
2751 */
2752 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2753 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2754 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2755 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2756 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2757 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2758 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2759 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2760 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2761 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2762 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2763 /** @} */
2764
2765 /** @name Function pointers for Both Shadow and Guest paging.
2766 * @{
2767 */
2768 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2769 /* no pfnR3BthTrap0eHandler */
2770 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2771 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2772 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2773 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2774#ifdef VBOX_STRICT
2775 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2776#endif
2777 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2778 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2779
2780 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2781 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2782 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2783 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2784 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2785#ifdef VBOX_STRICT
2786 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2787#endif
2788 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2789 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2790
2791 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2792 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2793 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2794 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2795 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2796#ifdef VBOX_STRICT
2797 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2798#endif
2799 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2800 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2801 /** @} */
2802} PGMMODEDATA, *PPGMMODEDATA;
2803
2804
2805#ifdef VBOX_WITH_STATISTICS
2806/**
2807 * PGM statistics.
2808 *
2809 * These lives on the heap when compiled in as they would otherwise waste
2810 * unnecessary space in release builds.
2811 */
2812typedef struct PGMSTATS
2813{
2814 /* R3 only: */
2815 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2816 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2817
2818 /* R3+RZ */
2819 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2820 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2821 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2822 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2823 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2824 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2825 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2826 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2827 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2828 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2829 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2830 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2831 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2832 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2833 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2834 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2835 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2836 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2837 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2838 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2839 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2840 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2841 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2842 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2843 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2844 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2845 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2846 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2847/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2848 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2849 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2850/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2851
2852 /* RC only: */
2853 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2854 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2855
2856 STAMCOUNTER StatRZPhysRead;
2857 STAMCOUNTER StatRZPhysReadBytes;
2858 STAMCOUNTER StatRZPhysWrite;
2859 STAMCOUNTER StatRZPhysWriteBytes;
2860 STAMCOUNTER StatR3PhysRead;
2861 STAMCOUNTER StatR3PhysReadBytes;
2862 STAMCOUNTER StatR3PhysWrite;
2863 STAMCOUNTER StatR3PhysWriteBytes;
2864 STAMCOUNTER StatRCPhysRead;
2865 STAMCOUNTER StatRCPhysReadBytes;
2866 STAMCOUNTER StatRCPhysWrite;
2867 STAMCOUNTER StatRCPhysWriteBytes;
2868
2869 STAMCOUNTER StatRZPhysSimpleRead;
2870 STAMCOUNTER StatRZPhysSimpleReadBytes;
2871 STAMCOUNTER StatRZPhysSimpleWrite;
2872 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2873 STAMCOUNTER StatR3PhysSimpleRead;
2874 STAMCOUNTER StatR3PhysSimpleReadBytes;
2875 STAMCOUNTER StatR3PhysSimpleWrite;
2876 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2877 STAMCOUNTER StatRCPhysSimpleRead;
2878 STAMCOUNTER StatRCPhysSimpleReadBytes;
2879 STAMCOUNTER StatRCPhysSimpleWrite;
2880 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2881
2882 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2883 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2884 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2885 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2886 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2887 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2888 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2889
2890 /** Time spent by the host OS for large page allocation. */
2891 STAMPROFILE StatAllocLargePage;
2892 /** Time spent clearing the newly allocated large pages. */
2893 STAMPROFILE StatClearLargePage;
2894 /** The number of times allocating a large pages takes more than the allowed period. */
2895 STAMCOUNTER StatLargePageOverflow;
2896 /** pgmPhysIsValidLargePage profiling - R3 */
2897 STAMPROFILE StatR3IsValidLargePage;
2898 /** pgmPhysIsValidLargePage profiling - RZ*/
2899 STAMPROFILE StatRZIsValidLargePage;
2900
2901 STAMPROFILE StatChunkAging;
2902 STAMPROFILE StatChunkFindCandidate;
2903 STAMPROFILE StatChunkUnmap;
2904 STAMPROFILE StatChunkMap;
2905} PGMSTATS;
2906#endif /* VBOX_WITH_STATISTICS */
2907
2908
2909/**
2910 * Converts a PGM pointer into a VM pointer.
2911 * @returns Pointer to the VM structure the PGM is part of.
2912 * @param pPGM Pointer to PGM instance data.
2913 */
2914#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2915
2916/**
2917 * PGM Data (part of VM)
2918 */
2919typedef struct PGM
2920{
2921 /** Offset to the VM structure. */
2922 int32_t offVM;
2923 /** Offset of the PGMCPU structure relative to VMCPU. */
2924 int32_t offVCpuPGM;
2925
2926 /** @cfgm{RamPreAlloc, boolean, false}
2927 * Indicates whether the base RAM should all be allocated before starting
2928 * the VM (default), or if it should be allocated when first written to.
2929 */
2930 bool fRamPreAlloc;
2931 /** Indicates whether write monitoring is currently in use.
2932 * This is used to prevent conflicts between live saving and page sharing
2933 * detection. */
2934 bool fPhysWriteMonitoringEngaged;
2935 /** Set if the CPU has less than 52-bit physical address width.
2936 * This is used */
2937 bool fLessThan52PhysicalAddressBits;
2938 /** Set when nested paging is active.
2939 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2940 * compilers optimize the code better. Whether we use nested paging or
2941 * not is something we find out during VMM initialization and we won't
2942 * change this later on. */
2943 bool fNestedPaging;
2944 /** The host paging mode. (This is what SUPLib reports.) */
2945 SUPPAGINGMODE enmHostMode;
2946 /** We're not in a state which permits writes to guest memory.
2947 * (Only used in strict builds.) */
2948 bool fNoMorePhysWrites;
2949 /** Set if PCI passthrough is enabled. */
2950 bool fPciPassthrough;
2951 /** Alignment padding that makes the next member start on a 8 byte boundary. */
2952 bool afAlignment1[2];
2953
2954 /** Indicates that PGMR3FinalizeMappings has been called and that further
2955 * PGMR3MapIntermediate calls will be rejected. */
2956 bool fFinalizedMappings;
2957 /** If set no conflict checks are required. */
2958 bool fMappingsFixed;
2959 /** If set if restored as fixed but we were unable to re-fixate at the old
2960 * location because of room or address incompatibilities. */
2961 bool fMappingsFixedRestored;
2962 /** If set, then no mappings are put into the shadow page table.
2963 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2964 bool fMappingsDisabled;
2965 /** Size of fixed mapping.
2966 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2967 uint32_t cbMappingFixed;
2968 /** Generation ID for the RAM ranges. This member is incremented everytime
2969 * a RAM range is linked or unlinked. */
2970 uint32_t volatile idRamRangesGen;
2971
2972 /** Base address (GC) of fixed mapping.
2973 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2974 RTGCPTR GCPtrMappingFixed;
2975 /** The address of the previous RAM range mapping. */
2976 RTGCPTR GCPtrPrevRamRangeMapping;
2977
2978 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2979 RTGCPHYS GCPhys4MBPSEMask;
2980 /** Mask containing the invalid bits of a guest physical address.
2981 * @remarks this does not stop at bit 52. */
2982 RTGCPHYS GCPhysInvAddrMask;
2983
2984
2985 /** RAM range TLB for R3. */
2986 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2987 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2988 * This is sorted by physical address and contains no overlapping ranges. */
2989 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2990 /** Root of the RAM range search tree for ring-3. */
2991 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2992 /** PGM offset based trees - R3 Ptr. */
2993 R3PTRTYPE(PPGMTREES) pTreesR3;
2994 /** Caching the last physical handler we looked up in R3. */
2995 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2996 /** Shadow Page Pool - R3 Ptr. */
2997 R3PTRTYPE(PPGMPOOL) pPoolR3;
2998 /** Linked list of GC mappings - for HC.
2999 * The list is sorted ascending on address. */
3000 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3001 /** Pointer to the list of ROM ranges - for R3.
3002 * This is sorted by physical address and contains no overlapping ranges. */
3003 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3004 /** Pointer to the list of MMIO2 ranges - for R3.
3005 * Registration order. */
3006 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3007 /** Pointer to SHW+GST mode data (function pointers).
3008 * The index into this table is made up from */
3009 R3PTRTYPE(PPGMMODEDATA) paModeData;
3010 RTR3PTR R3PtrAlignment0;
3011
3012 /** RAM range TLB for R0. */
3013 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3014 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3015 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3016 /** Root of the RAM range search tree for ring-0. */
3017 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3018 /** PGM offset based trees - R0 Ptr. */
3019 R0PTRTYPE(PPGMTREES) pTreesR0;
3020 /** Caching the last physical handler we looked up in R0. */
3021 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3022 /** Shadow Page Pool - R0 Ptr. */
3023 R0PTRTYPE(PPGMPOOL) pPoolR0;
3024 /** Linked list of GC mappings - for R0.
3025 * The list is sorted ascending on address. */
3026 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3027 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3028 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3029 RTR0PTR R0PtrAlignment0;
3030
3031
3032 /** RAM range TLB for RC. */
3033 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3034 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3035 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3036 /** Root of the RAM range search tree for raw-mode context. */
3037 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3038 /** PGM offset based trees - RC Ptr. */
3039 RCPTRTYPE(PPGMTREES) pTreesRC;
3040 /** Caching the last physical handler we looked up in RC. */
3041 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3042 /** Shadow Page Pool - RC Ptr. */
3043 RCPTRTYPE(PPGMPOOL) pPoolRC;
3044 /** Linked list of GC mappings - for RC.
3045 * The list is sorted ascending on address. */
3046 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3047 /** RC pointer corresponding to PGM::pRomRangesR3. */
3048 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3049 RTRCPTR RCPtrAlignment0;
3050 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3051 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3052 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3053 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3054
3055
3056 /** Pointer to the 5 page CR3 content mapping.
3057 * The first page is always the CR3 (in some form) while the 4 other pages
3058 * are used of the PDs in PAE mode. */
3059 RTGCPTR GCPtrCR3Mapping;
3060
3061 /** @name Intermediate Context
3062 * @{ */
3063 /** Pointer to the intermediate page directory - Normal. */
3064 R3PTRTYPE(PX86PD) pInterPD;
3065 /** Pointer to the intermediate page tables - Normal.
3066 * There are two page tables, one for the identity mapping and one for
3067 * the host context mapping (of the core code). */
3068 R3PTRTYPE(PX86PT) apInterPTs[2];
3069 /** Pointer to the intermediate page tables - PAE. */
3070 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3071 /** Pointer to the intermediate page directory - PAE. */
3072 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3073 /** Pointer to the intermediate page directory - PAE. */
3074 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3075 /** Pointer to the intermediate page-map level 4 - AMD64. */
3076 R3PTRTYPE(PX86PML4) pInterPaePML4;
3077 /** Pointer to the intermediate page directory - AMD64. */
3078 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3079 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3080 RTHCPHYS HCPhysInterPD;
3081 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3082 RTHCPHYS HCPhysInterPaePDPT;
3083 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3084 RTHCPHYS HCPhysInterPaePML4;
3085 /** @} */
3086
3087 /** Base address of the dynamic page mapping area.
3088 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3089 *
3090 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3091 * work out. Some cleaning up of the initialization that would
3092 * remove this memory is yet to be done...
3093 */
3094 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3095 /** The address of the raw-mode context mapping cache. */
3096 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3097 /** The address of the ring-0 mapping cache if we're making use of it. */
3098 RTR0PTR pvR0DynMapUsed;
3099#if HC_ARCH_BITS == 32
3100 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3101 uint32_t u32Alignment2;
3102#endif
3103
3104 /** PGM critical section.
3105 * This protects the physical & virtual access handlers, ram ranges,
3106 * and the page flag updating (some of it anyway).
3107 */
3108 PDMCRITSECT CritSect;
3109
3110 /**
3111 * Data associated with managing the ring-3 mappings of the allocation chunks.
3112 */
3113 struct
3114 {
3115 /** The chunk tree, ordered by chunk id. */
3116#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3117 R3PTRTYPE(PAVLU32NODECORE) pTree;
3118#else
3119 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3120#endif
3121#if HC_ARCH_BITS == 32
3122 uint32_t u32Alignment;
3123#endif
3124 /** The chunk mapping TLB. */
3125 PGMCHUNKR3MAPTLB Tlb;
3126 /** The number of mapped chunks. */
3127 uint32_t c;
3128 /** The maximum number of mapped chunks.
3129 * @cfgm PGM/MaxRing3Chunks */
3130 uint32_t cMax;
3131 /** The current time. */
3132 uint32_t iNow;
3133 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3134 uint32_t AgeingCountdown;
3135 } ChunkR3Map;
3136
3137 /**
3138 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3139 */
3140 PGMPAGER3MAPTLB PhysTlbHC;
3141
3142 /** @name The zero page.
3143 * @{ */
3144 /** The host physical address of the zero page. */
3145 RTHCPHYS HCPhysZeroPg;
3146 /** The ring-3 mapping of the zero page. */
3147 RTR3PTR pvZeroPgR3;
3148 /** The ring-0 mapping of the zero page. */
3149 RTR0PTR pvZeroPgR0;
3150 /** The GC mapping of the zero page. */
3151 RTRCPTR pvZeroPgRC;
3152 RTRCPTR RCPtrAlignment3;
3153 /** @}*/
3154
3155 /** @name The Invalid MMIO page.
3156 * This page is filled with 0xfeedface.
3157 * @{ */
3158 /** The host physical address of the invalid MMIO page. */
3159 RTHCPHYS HCPhysMmioPg;
3160 /** The host pysical address of the invalid MMIO page plus all invalid
3161 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3162 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3163 RTHCPHYS HCPhysInvMmioPg;
3164 /** The ring-3 mapping of the invalid MMIO page. */
3165 RTR3PTR pvMmioPgR3;
3166#if HC_ARCH_BITS == 32
3167 RTR3PTR R3PtrAlignment4;
3168#endif
3169 /** @} */
3170
3171
3172 /** The number of handy pages. */
3173 uint32_t cHandyPages;
3174
3175 /** The number of large handy pages. */
3176 uint32_t cLargeHandyPages;
3177
3178 /**
3179 * Array of handy pages.
3180 *
3181 * This array is used in a two way communication between pgmPhysAllocPage
3182 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3183 * an intermediary.
3184 *
3185 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3186 * (The current size of 32 pages, means 128 KB of handy memory.)
3187 */
3188 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3189
3190 /**
3191 * Array of large handy pages. (currently size 1)
3192 *
3193 * This array is used in a two way communication between pgmPhysAllocLargePage
3194 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3195 * an intermediary.
3196 */
3197 GMMPAGEDESC aLargeHandyPage[1];
3198
3199 /**
3200 * Live save data.
3201 */
3202 struct
3203 {
3204 /** Per type statistics. */
3205 struct
3206 {
3207 /** The number of ready pages. */
3208 uint32_t cReadyPages;
3209 /** The number of dirty pages. */
3210 uint32_t cDirtyPages;
3211 /** The number of ready zero pages. */
3212 uint32_t cZeroPages;
3213 /** The number of write monitored pages. */
3214 uint32_t cMonitoredPages;
3215 } Rom,
3216 Mmio2,
3217 Ram;
3218 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3219 uint32_t cIgnoredPages;
3220 /** Indicates that a live save operation is active. */
3221 bool fActive;
3222 /** Padding. */
3223 bool afReserved[2];
3224 /** The next history index. */
3225 uint8_t iDirtyPagesHistory;
3226 /** History of the total amount of dirty pages. */
3227 uint32_t acDirtyPagesHistory[64];
3228 /** Short term dirty page average. */
3229 uint32_t cDirtyPagesShort;
3230 /** Long term dirty page average. */
3231 uint32_t cDirtyPagesLong;
3232 /** The number of saved pages. This is used to get some kind of estimate of the
3233 * link speed so we can decide when we're done. It is reset after the first
3234 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3235 * zero pages. */
3236 uint64_t cSavedPages;
3237 /** The nanosecond timestamp when cSavedPages was 0. */
3238 uint64_t uSaveStartNS;
3239 /** Pages per second (for statistics). */
3240 uint32_t cPagesPerSecond;
3241 uint32_t cAlignment;
3242 } LiveSave;
3243
3244 /** @name Error injection.
3245 * @{ */
3246 /** Inject handy page allocation errors pretending we're completely out of
3247 * memory. */
3248 bool volatile fErrInjHandyPages;
3249 /** Padding. */
3250 bool afReserved[3];
3251 /** @} */
3252
3253 /** @name Release Statistics
3254 * @{ */
3255 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3256 uint32_t cPrivatePages; /**< The number of private pages. */
3257 uint32_t cSharedPages; /**< The number of shared pages. */
3258 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3259 uint32_t cZeroPages; /**< The number of zero backed pages. */
3260 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3261 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3262 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3263 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3264 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3265 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3266 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3267 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3268 uint32_t cLargePages; /**< The number of large pages. */
3269 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3270/* uint32_t aAlignment4[1]; */
3271
3272 /** The number of times we were forced to change the hypervisor region location. */
3273 STAMCOUNTER cRelocations;
3274
3275 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3276 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3277 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3278 /** @} */
3279
3280#ifdef VBOX_WITH_STATISTICS
3281 /** @name Statistics on the heap.
3282 * @{ */
3283 R3PTRTYPE(PGMSTATS *) pStatsR3;
3284 R0PTRTYPE(PGMSTATS *) pStatsR0;
3285 RCPTRTYPE(PGMSTATS *) pStatsRC;
3286 RTRCPTR RCPtrAlignment;
3287 /** @} */
3288#endif
3289} PGM;
3290#ifndef IN_TSTVMSTRUCTGC /* HACK */
3291AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3292AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3293AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3294AssertCompileMemberAlignment(PGM, CritSect, 8);
3295AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3296AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3297AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3298AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3299AssertCompileMemberAlignment(PGM, cRelocations, 8);
3300#endif /* !IN_TSTVMSTRUCTGC */
3301/** Pointer to the PGM instance data. */
3302typedef PGM *PPGM;
3303
3304
3305
3306typedef struct PGMCPUSTATS
3307{
3308 /* Common */
3309 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3310 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3311
3312 /* R0 only: */
3313 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3314 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3315
3316 /* RZ only: */
3317 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3318 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3319 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3320 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3321 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3322 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3323 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3324 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3325 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3326 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3327 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3328 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3329 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3330 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3331 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3332 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3333 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3334 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3335 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3336 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3337 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3338 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3339 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3340 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3341 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3342 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3343 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3344 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3345 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3346 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3347 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3348 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3349 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3350 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3351 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3352 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3353 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3354 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3355 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3356 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3357 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3358 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3359 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3360 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3361 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3362 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3363 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3364 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3365 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3366 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3367 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3368 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3369 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3370 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3371 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3372 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3373 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3374 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3375 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3376 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3377 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3378 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3379 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3380 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3381 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3382 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3383 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3384 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3385 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3386 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3387 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3388 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3389 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3390 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3391 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3392 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3393
3394 /* HC - R3 and (maybe) R0: */
3395
3396 /* RZ & R3: */
3397 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3398 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3399 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3400 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3401 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3402 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3403 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3404 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3405 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3406 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3407 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3408 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3409 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3410 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3411 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3412 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3413 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3414 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3415 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3416 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3417 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3418 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3419 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3420 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3421 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3422 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3423 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3424 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3425 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3426 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3427 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3428 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3429 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3430 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3431 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3432 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3433 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3434 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3435 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3436 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3437 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3438 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3439 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3440 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3441 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3442 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3443 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3444
3445 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3446 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3447 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3448 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3449 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3450 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3451 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3452 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3453 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3454 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3455 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3456 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3457 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3458 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3459 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3460 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3461 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3462 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3463 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3464 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3465 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3466 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3467 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3468 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3469 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3470 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3471 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3472 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3473 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3474 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3475 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3476 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3477 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3478 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3479 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3480 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3481 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3482 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3483 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3484 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3485 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3486 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3487 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3488 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3489 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3490 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3491 /** @} */
3492} PGMCPUSTATS;
3493
3494
3495/**
3496 * Converts a PGMCPU pointer into a VM pointer.
3497 * @returns Pointer to the VM structure the PGM is part of.
3498 * @param pPGM Pointer to PGMCPU instance data.
3499 */
3500#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3501
3502/**
3503 * Converts a PGMCPU pointer into a PGM pointer.
3504 * @returns Pointer to the VM structure the PGM is part of.
3505 * @param pPGM Pointer to PGMCPU instance data.
3506 */
3507#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3508
3509/**
3510 * PGMCPU Data (part of VMCPU).
3511 */
3512typedef struct PGMCPU
3513{
3514 /** Offset to the VM structure. */
3515 int32_t offVM;
3516 /** Offset to the VMCPU structure. */
3517 int32_t offVCpu;
3518 /** Offset of the PGM structure relative to VMCPU. */
3519 int32_t offPGM;
3520 uint32_t uPadding0; /**< structure size alignment. */
3521
3522#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3523 /** Automatically tracked physical memory mapping set.
3524 * Ring-0 and strict raw-mode builds. */
3525 PGMMAPSET AutoSet;
3526#endif
3527
3528 /** A20 gate mask.
3529 * Our current approach to A20 emulation is to let REM do it and don't bother
3530 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3531 * But whould need arrise, we'll subject physical addresses to this mask. */
3532 RTGCPHYS GCPhysA20Mask;
3533 /** A20 gate state - boolean! */
3534 bool fA20Enabled;
3535 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3536 bool fNoExecuteEnabled;
3537 /** Unused bits. */
3538 bool afUnused[2];
3539
3540 /** What needs syncing (PGM_SYNC_*).
3541 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3542 * PGMFlushTLB, and PGMR3Load. */
3543 RTUINT fSyncFlags;
3544
3545 /** The shadow paging mode. */
3546 PGMMODE enmShadowMode;
3547 /** The guest paging mode. */
3548 PGMMODE enmGuestMode;
3549
3550 /** The current physical address representing in the guest CR3 register. */
3551 RTGCPHYS GCPhysCR3;
3552
3553 /** @name 32-bit Guest Paging.
3554 * @{ */
3555 /** The guest's page directory, R3 pointer. */
3556 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3557#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3558 /** The guest's page directory, R0 pointer. */
3559 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3560#endif
3561 /** The guest's page directory, static RC mapping. */
3562 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3563 /** Mask containing the MBZ bits of a big page PDE. */
3564 uint32_t fGst32BitMbzBigPdeMask;
3565 /** Set if the page size extension (PSE) is enabled. */
3566 bool fGst32BitPageSizeExtension;
3567 /** Alignment padding. */
3568 bool afAlignment2[3];
3569 /** @} */
3570
3571 /** @name PAE Guest Paging.
3572 * @{ */
3573 /** The guest's page directory pointer table, static RC mapping. */
3574 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3575 /** The guest's page directory pointer table, R3 pointer. */
3576 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3577#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3578 /** The guest's page directory pointer table, R0 pointer. */
3579 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3580#endif
3581
3582 /** The guest's page directories, R3 pointers.
3583 * These are individual pointers and don't have to be adjacent.
3584 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3585 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3586 /** The guest's page directories, R0 pointers.
3587 * Same restrictions as apGstPaePDsR3. */
3588#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3589 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3590#endif
3591 /** The guest's page directories, static GC mapping.
3592 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3593 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3594 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3595 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3596 RTGCPHYS aGCPhysGstPaePDs[4];
3597 /** The physical addresses of the monitored guest page directories (PAE). */
3598 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3599 /** Mask containing the MBZ PTE bits. */
3600 uint64_t fGstPaeMbzPteMask;
3601 /** Mask containing the MBZ PDE bits. */
3602 uint64_t fGstPaeMbzPdeMask;
3603 /** Mask containing the MBZ big page PDE bits. */
3604 uint64_t fGstPaeMbzBigPdeMask;
3605 /** Mask containing the MBZ PDPE bits. */
3606 uint64_t fGstPaeMbzPdpeMask;
3607 /** @} */
3608
3609 /** @name AMD64 Guest Paging.
3610 * @{ */
3611 /** The guest's page directory pointer table, R3 pointer. */
3612 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3613#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3614 /** The guest's page directory pointer table, R0 pointer. */
3615 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3616#else
3617 RTR0PTR alignment6b; /**< alignment equalizer. */
3618#endif
3619 /** Mask containing the MBZ PTE bits. */
3620 uint64_t fGstAmd64MbzPteMask;
3621 /** Mask containing the MBZ PDE bits. */
3622 uint64_t fGstAmd64MbzPdeMask;
3623 /** Mask containing the MBZ big page PDE bits. */
3624 uint64_t fGstAmd64MbzBigPdeMask;
3625 /** Mask containing the MBZ PDPE bits. */
3626 uint64_t fGstAmd64MbzPdpeMask;
3627 /** Mask containing the MBZ big page PDPE bits. */
3628 uint64_t fGstAmd64MbzBigPdpeMask;
3629 /** Mask containing the MBZ PML4E bits. */
3630 uint64_t fGstAmd64MbzPml4eMask;
3631 /** Mask containing the PDPE bits that we shadow. */
3632 uint64_t fGstAmd64ShadowedPdpeMask;
3633 /** Mask containing the PML4E bits that we shadow. */
3634 uint64_t fGstAmd64ShadowedPml4eMask;
3635 /** @} */
3636
3637 /** @name PAE and AMD64 Guest Paging.
3638 * @{ */
3639 /** Mask containing the PTE bits that we shadow. */
3640 uint64_t fGst64ShadowedPteMask;
3641 /** Mask containing the PDE bits that we shadow. */
3642 uint64_t fGst64ShadowedPdeMask;
3643 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3644 uint64_t fGst64ShadowedBigPdeMask;
3645 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3646 uint64_t fGst64ShadowedBigPde4PteMask;
3647 /** @} */
3648
3649 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3650 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3651 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3652 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3653 /** Pointer to the page of the current active CR3 - RC Ptr. */
3654 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3655 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3656 uint32_t iShwUser;
3657 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3658 uint32_t iShwUserTable;
3659# if HC_ARCH_BITS == 64
3660 RTRCPTR alignment6; /**< structure size alignment. */
3661# endif
3662 /** @} */
3663
3664 /** @name Function pointers for Shadow paging.
3665 * @{
3666 */
3667 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3668 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3669 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3670 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3671
3672 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3673 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3674
3675 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3676 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3677
3678 /** @} */
3679
3680 /** @name Function pointers for Guest paging.
3681 * @{
3682 */
3683 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3684 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3685 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3686 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3687 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3688 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3689 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3690 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3691#if HC_ARCH_BITS == 64
3692 RTRCPTR alignment3; /**< structure size alignment. */
3693#endif
3694
3695 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3696 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3697 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3698 /** @} */
3699
3700 /** @name Function pointers for Both Shadow and Guest paging.
3701 * @{
3702 */
3703 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3704 /* no pfnR3BthTrap0eHandler */
3705 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3706 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3707 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3708 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3709 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3710 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3711 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3712
3713 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3714 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3715 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3716 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3717 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3718 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3719 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3720 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3721
3722 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3723 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3724 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3725 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3726 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3727 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3728 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3729 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3730#if 0
3731 RTRCPTR alignment2; /**< structure size alignment. */
3732#endif
3733 /** @} */
3734
3735 /** For saving stack space, the disassembler state is allocated here instead of
3736 * on the stack.
3737 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3738 union
3739 {
3740 /** The disassembler scratch space. */
3741 DISCPUSTATE DisState;
3742 /** Padding. */
3743 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3744 };
3745
3746 /** Count the number of pgm pool access handler calls. */
3747 uint64_t cPoolAccessHandler;
3748
3749 /** @name Release Statistics
3750 * @{ */
3751 /** The number of times the guest has switched mode since last reset or statistics reset. */
3752 STAMCOUNTER cGuestModeChanges;
3753 /** @} */
3754
3755#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3756 /** @name Statistics
3757 * @{ */
3758 /** RC: Pointer to the statistics. */
3759 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3760 /** RC: Which statistic this \#PF should be attributed to. */
3761 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3762 /** R0: Pointer to the statistics. */
3763 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3764 /** R0: Which statistic this \#PF should be attributed to. */
3765 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3766 /** R3: Pointer to the statistics. */
3767 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3768 /** Alignment padding. */
3769 RTR3PTR pPaddingR3;
3770 /** @} */
3771#endif /* VBOX_WITH_STATISTICS */
3772} PGMCPU;
3773/** Pointer to the per-cpu PGM data. */
3774typedef PGMCPU *PPGMCPU;
3775
3776
3777/** @name PGM::fSyncFlags Flags
3778 * @{
3779 */
3780/** Updates the virtual access handler state bit in PGMPAGE. */
3781#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3782/** Always sync CR3. */
3783#define PGM_SYNC_ALWAYS RT_BIT(1)
3784/** Check monitoring on next CR3 (re)load and invalidate page.
3785 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3786#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3787/** Check guest mapping in SyncCR3. */
3788#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3789/** Clear the page pool (a light weight flush). */
3790#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3791#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3792/** @} */
3793
3794
3795RT_C_DECLS_BEGIN
3796
3797int pgmLock(PVM pVM);
3798void pgmUnlock(PVM pVM);
3799
3800int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3801int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3802int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3803PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3804int pgmMapResolveConflicts(PVM pVM);
3805DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3806
3807void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3808bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3809void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3810int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3811DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3812#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3813void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3814#else
3815# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3816#endif
3817DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3818int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3819
3820int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3821int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3822int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3823int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
3824int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3825void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3826int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3827int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3828int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3829int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3830int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3831int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3832int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3833VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3834VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3835int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3836void pgmPhysInvalidRamRangeTlbs(PVM pVM);
3837PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3838PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3839PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3840int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3841int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3842
3843#ifdef IN_RING3
3844void pgmR3PhysRelinkRamRanges(PVM pVM);
3845int pgmR3PhysRamPreAllocate(PVM pVM);
3846int pgmR3PhysRamReset(PVM pVM);
3847int pgmR3PhysRomReset(PVM pVM);
3848int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3849int pgmR3PhysRamTerm(PVM pVM);
3850void pgmR3PhysRomTerm(PVM pVM);
3851
3852int pgmR3PoolInit(PVM pVM);
3853void pgmR3PoolRelocate(PVM pVM);
3854void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3855void pgmR3PoolReset(PVM pVM);
3856void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3857DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3858void pgmR3PoolWriteProtectPages(PVM pVM);
3859
3860#endif /* IN_RING3 */
3861#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3862int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3863int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3864# ifdef LOG_ENABLED
3865void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3866# else
3867void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3868# endif
3869#endif
3870int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3871 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3872
3873DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3874 PPPGMPOOLPAGE ppPage)
3875{
3876 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3877}
3878
3879void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3880void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3881int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3882void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3883PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3884PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3885int pgmPoolSyncCR3(PVMCPU pVCpu);
3886bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3887void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3888int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3889void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3890uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3891void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3892void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3893int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3894void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3895
3896void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3897void pgmPoolResetDirtyPages(PVM pVM);
3898void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3899
3900int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3901int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3902
3903void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3904void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3905int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3906int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3907
3908int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3909int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3910
3911int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3912int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3913int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3914int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3915
3916# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3917DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3918DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3919# endif
3920
3921RT_C_DECLS_END
3922
3923/** @} */
3924
3925#endif
3926
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