PGMInternal.h@ 36940

Last change on this file since 36940 was 36940, checked in by vboxsync, 14 years ago
PGMPAGE: Finally, idPage is 32-bit. The physical address can now be masked out, instead of shifted and masked.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 177.3 KB

Line
1	/* $Id: PGMInternal.h 36940 2011-05-03 14:55:19Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hwaccm.h>
36	#include <VBox/vmm/hwacc_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/sha.h>
43
44
45
46	/** @defgroup grp_pgm_int Internals
47	* @ingroup grp_pgm
48	* @internal
49	* @{
50	*/
51
52
53	/** @name PGM Compile Time Config
54	* @{
55	*/
56
57	/**
58	* Indicates that there are no guest mappings to care about.
59	* Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60	*/
61	#if defined(IN_RING0) \|\| !defined(VBOX_WITH_RAW_MODE)
62	# define PGM_WITHOUT_MAPPINGS
63	#endif
64
65	/**
66	* Check and skip global PDEs for non-global flushes
67	*/
68	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70	/**
71	* Optimization for PAE page tables that are modified often
72	*/
73	//#if 0 /* disabled again while debugging */
74	#ifndef IN_RC
75	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76	#endif
77	//#endif
78
79	/**
80	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
81	*/
82	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83	# define PGM_WITH_LARGE_PAGES
84	#endif
85
86	/**
87	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88	* VMX_EXIT_EPT_MISCONFIG.
89	*/
90	#if 1 /* testing */
91	# define PGM_WITH_MMIO_OPTIMIZATIONS
92	#endif
93
94	/**
95	* Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96	*/
97	#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98	# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99	#endif
100
101	/**
102	* Sync N pages instead of a whole page table
103	*/
104	#define PGM_SYNC_N_PAGES
105
106	/**
107	* Number of pages to sync during a page fault
108	*
109	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111	*
112	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113	* world switch overhead, so let's sync more.
114	*/
115	# ifdef IN_RING0
116	/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118	* but ~5% fewer faults.
119	*/
120	# define PGM_SYNC_NR_PAGES 32
121	#else
122	# define PGM_SYNC_NR_PAGES 8
123	#endif
124
125	/**
126	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127	*/
128	#define PGM_MAX_PHYSCACHE_ENTRIES 64
129	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132	/** @def PGMPOOL_CFG_MAX_GROW
133	* The maximum number of pages to add to the pool in one go.
134	*/
135	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
139	*/
140	#ifdef VBOX_STRICT
141	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142	#endif
143
144	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145	* Enables the experimental lazy page allocation code. */
146	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
147
148	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149	* Enables real write monitoring of pages, i.e. mapping them read-only and
150	* only making them writable when getting a write access #PF. */
151	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153	/** @} */
154
155
156	/** @name PDPT and PML4 flags.
157	* These are placed in the three bits available for system programs in
158	* the PDPT and PML4 entries.
159	* @{ */
160	/** The entry is a permanent one and it's must always be present.
161	* Never free such an entry. */
162	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163	/** Mapping (hypervisor allocated pagetable). */
164	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165	/** @} */
166
167	/** @name Page directory flags.
168	* These are placed in the three bits available for system programs in
169	* the page directory entries.
170	* @{ */
171	/** Mapping (hypervisor allocated pagetable). */
172	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173	/** Made read-only to facilitate dirty bit tracking. */
174	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175	/** @} */
176
177	/** @name Page flags.
178	* These are placed in the three bits available for system programs in
179	* the page entries.
180	* @{ */
181	/** Made read-only to facilitate dirty bit tracking. */
182	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185	/** Scanned and approved by CSAM (tm).
186	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
187	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189	#endif
190
191	/** @} */
192
193	/** @name Defines used to indicate the shadow and guest paging in the templates.
194	* @{ */
195	#define PGM_TYPE_REAL 1
196	#define PGM_TYPE_PROT 2
197	#define PGM_TYPE_32BIT 3
198	#define PGM_TYPE_PAE 4
199	#define PGM_TYPE_AMD64 5
200	#define PGM_TYPE_NESTED 6
201	#define PGM_TYPE_EPT 7
202	#define PGM_TYPE_MAX PGM_TYPE_EPT
203	/** @} */
204
205	/** Macro for checking if the guest is using paging.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_PAGING(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_32BIT \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215	/** Macro for checking if the guest supports the NX bit.
216	* @param uGstType PGM_TYPE_*
217	* @param uShwType PGM_TYPE_*
218	* @remark ASSUMES certain order of the PGM_TYPE_* values.
219	*/
220	#define PGM_WITH_NX(uGstType, uShwType) \
221	( (uGstType) >= PGM_TYPE_PAE \
222	&& (uShwType) != PGM_TYPE_NESTED \
223	&& (uShwType) != PGM_TYPE_EPT)
224
225
226	/** @def PGM_HCPHYS_2_PTR
227	* Maps a HC physical page pool address to a virtual address.
228	*
229	* @returns VBox status code.
230	* @param pVM The VM handle.
231	* @param pVCpu The current CPU.
232	* @param HCPhys The HC physical address to map to a virtual one.
233	* @param ppv Where to store the virtual address. No need to cast
234	* this.
235	*
236	* @remark Use with care as we don't have so much dynamic mapping space in
237	* ring-0 on 32-bit darwin and in RC.
238	* @remark There is no need to assert on the result.
239	*/
240	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
241	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243	#else
244	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246	#endif
247
248	/** @def PGM_GCPHYS_2_PTR_V2
249	* Maps a GC physical page address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pVM The VM handle.
253	* @param pVCpu The current CPU.
254	* @param GCPhys The GC physical address to map to a virtual one.
255	* @param ppv Where to store the virtual address. No need to cast this.
256	*
257	* @remark Use with care as we don't have so much dynamic mapping space in
258	* ring-0 on 32-bit darwin and in RC.
259	* @remark There is no need to assert on the result.
260	*/
261	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
262	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264	#else
265	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267	#endif
268
269	/** @def PGM_GCPHYS_2_PTR
270	* Maps a GC physical page address to a virtual address.
271	*
272	* @returns VBox status code.
273	* @param pVM The VM handle.
274	* @param GCPhys The GC physical address to map to a virtual one.
275	* @param ppv Where to store the virtual address. No need to cast this.
276	*
277	* @remark Use with care as we don't have so much dynamic mapping space in
278	* ring-0 on 32-bit darwin and in RC.
279	* @remark There is no need to assert on the result.
280	*/
281	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284	* Maps a GC physical page address to a virtual address.
285	*
286	* @returns VBox status code.
287	* @param pVCpu The current CPU.
288	* @param GCPhys The GC physical address to map to a virtual one.
289	* @param ppv Where to store the virtual address. No need to cast this.
290	*
291	* @remark Use with care as we don't have so much dynamic mapping space in
292	* ring-0 on 32-bit darwin and in RC.
293	* @remark There is no need to assert on the result.
294	*/
295	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297	/** @def PGM_GCPHYS_2_PTR_EX
298	* Maps a unaligned GC physical page address to a virtual address.
299	*
300	* @returns VBox status code.
301	* @param pVM The VM handle.
302	* @param GCPhys The GC physical address to map to a virtual one.
303	* @param ppv Where to store the virtual address. No need to cast this.
304	*
305	* @remark Use with care as we don't have so much dynamic mapping space in
306	* ring-0 on 32-bit darwin and in RC.
307	* @remark There is no need to assert on the result.
308	*/
309	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312	#else
313	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315	#endif
316
317	/** @def PGM_DYNMAP_UNUSED_HINT
318	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319	* is no longer used.
320	*
321	* For best effect only apply this to the page that was mapped most recently.
322	*
323	* @param pVCpu The current CPU.
324	* @param pvPage The pool page.
325	*/
326	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327	# ifdef LOG_ENABLED
328	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329	# else
330	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331	# endif
332	#else
333	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334	#endif
335
336	/** @def PGM_DYNMAP_UNUSED_HINT_VM
337	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338	* is no longer used.
339	*
340	* For best effect only apply this to the page that was mapped most recently.
341	*
342	* @param pVM The VM handle.
343	* @param pvPage The pool page.
344	*/
345	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348	/** @def PGM_INVL_PG
349	* Invalidates a page.
350	*
351	* @param pVCpu The VMCPU handle.
352	* @param GCVirt The virtual address of the page to invalidate.
353	*/
354	#ifdef IN_RC
355	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356	#elif defined(IN_RING0)
357	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358	#else
359	# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360	#endif
361
362	/** @def PGM_INVL_PG_ALL_VCPU
363	* Invalidates a page on all VCPUs
364	*
365	* @param pVM The VM handle.
366	* @param GCVirt The virtual address of the page to invalidate.
367	*/
368	#ifdef IN_RC
369	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370	#elif defined(IN_RING0)
371	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372	#else
373	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374	#endif
375
376	/** @def PGM_INVL_BIG_PG
377	* Invalidates a 4MB page directory entry.
378	*
379	* @param pVCpu The VMCPU handle.
380	* @param GCVirt The virtual address within the page directory to invalidate.
381	*/
382	#ifdef IN_RC
383	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384	#elif defined(IN_RING0)
385	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386	#else
387	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388	#endif
389
390	/** @def PGM_INVL_VCPU_TLBS()
391	* Invalidates the TLBs of the specified VCPU
392	*
393	* @param pVCpu The VMCPU handle.
394	*/
395	#ifdef IN_RC
396	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397	#elif defined(IN_RING0)
398	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399	#else
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401	#endif
402
403	/** @def PGM_INVL_ALL_VCPU_TLBS()
404	* Invalidates the TLBs of all VCPUs
405	*
406	* @param pVM The VM handle.
407	*/
408	#ifdef IN_RC
409	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410	#elif defined(IN_RING0)
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** Size of the GCPtrConflict array in PGMMAPPING.
498	* @remarks Must be a power of two. */
499	#define PGMMAPPING_CONFLICT_MAX 8
500
501	/**
502	* Structure for tracking GC Mappings.
503	*
504	* This structure is used by linked list in both GC and HC.
505	*/
506	typedef struct PGMMAPPING
507	{
508	/** Pointer to next entry. */
509	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510	/** Pointer to next entry. */
511	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512	/** Pointer to next entry. */
513	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514	/** Indicate whether this entry is finalized. */
515	bool fFinalized;
516	/** Start Virtual address. */
517	RTGCPTR GCPtr;
518	/** Last Virtual address (inclusive). */
519	RTGCPTR GCPtrLast;
520	/** Range size (bytes). */
521	RTGCPTR cb;
522	/** Pointer to relocation callback function. */
523	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524	/** User argument to the callback. */
525	R3PTRTYPE(void *) pvUser;
526	/** Mapping description / name. For easing debugging. */
527	R3PTRTYPE(const char *) pszDesc;
528	/** Last 8 addresses that caused conflicts. */
529	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530	/** Number of conflicts for this hypervisor mapping. */
531	uint32_t cConflicts;
532	/** Number of page tables. */
533	uint32_t cPTs;
534
535	/** Array of page table mapping data. Each entry
536	* describes one page table. The array can be longer
537	* than the declared length.
538	*/
539	struct
540	{
541	/** The HC physical address of the page table. */
542	RTHCPHYS HCPhysPT;
543	/** The HC physical address of the first PAE page table. */
544	RTHCPHYS HCPhysPaePT0;
545	/** The HC physical address of the second PAE page table. */
546	RTHCPHYS HCPhysPaePT1;
547	/** The HC virtual address of the 32-bit page table. */
548	R3PTRTYPE(PX86PT) pPTR3;
549	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551	/** The RC virtual address of the 32-bit page table. */
552	RCPTRTYPE(PX86PT) pPTRC;
553	/** The RC virtual address of the two PAE page table. */
554	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555	/** The R0 virtual address of the 32-bit page table. */
556	R0PTRTYPE(PX86PT) pPTR0;
557	/** The R0 virtual address of the two PAE page table. */
558	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559	} aPTs[1];
560	} PGMMAPPING;
561	/** Pointer to structure for tracking GC Mappings. */
562	typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565	/**
566	* Physical page access handler structure.
567	*
568	* This is used to keep track of physical address ranges
569	* which are being monitored in some kind of way.
570	*/
571	typedef struct PGMPHYSHANDLER
572	{
573	AVLROGCPHYSNODECORE Core;
574	/** Access type. */
575	PGMPHYSHANDLERTYPE enmType;
576	/** Number of pages to update. */
577	uint32_t cPages;
578	/** Set if we have pages that have been aliased. */
579	uint32_t cAliasedPages;
580	/** Set if we have pages that have temporarily been disabled. */
581	uint32_t cTmpOffPages;
582	/** Pointer to R3 callback function. */
583	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584	/** User argument for R3 handlers. */
585	R3PTRTYPE(void *) pvUserR3;
586	/** Pointer to R0 callback function. */
587	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588	/** User argument for R0 handlers. */
589	R0PTRTYPE(void *) pvUserR0;
590	/** Pointer to RC callback function. */
591	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592	/** User argument for RC handlers. */
593	RCPTRTYPE(void *) pvUserRC;
594	/** Description / Name. For easing debugging. */
595	R3PTRTYPE(const char *) pszDesc;
596	#ifdef VBOX_WITH_STATISTICS
597	/** Profiling of this handler. */
598	STAMPROFILE Stat;
599	#endif
600	} PGMPHYSHANDLER;
601	/** Pointer to a physical page access handler structure. */
602	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605	/**
606	* Cache node for the physical addresses covered by a virtual handler.
607	*/
608	typedef struct PGMPHYS2VIRTHANDLER
609	{
610	/** Core node for the tree based on physical ranges. */
611	AVLROGCPHYSNODECORE Core;
612	/** Offset from this struct to the PGMVIRTHANDLER structure. */
613	int32_t offVirtHandler;
614	/** Offset of the next alias relative to this one.
615	* Bit 0 is used for indicating whether we're in the tree.
616	* Bit 1 is used for indicating that we're the head node.
617	*/
618	int32_t offNextAlias;
619	} PGMPHYS2VIRTHANDLER;
620	/** Pointer to a phys to virtual handler structure. */
621	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624	* node is in the tree. */
625	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627	* node is in the head of an alias chain.
628	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634	/**
635	* Virtual page access handler structure.
636	*
637	* This is used to keep track of virtual address ranges
638	* which are being monitored in some kind of way.
639	*/
640	typedef struct PGMVIRTHANDLER
641	{
642	/** Core node for the tree based on virtual ranges. */
643	AVLROGCPTRNODECORE Core;
644	/** Size of the range (in bytes). */
645	RTGCPTR cb;
646	/** Number of cache pages. */
647	uint32_t cPages;
648	/** Access type. */
649	PGMVIRTHANDLERTYPE enmType;
650	/** Pointer to the RC callback function. */
651	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652	#if HC_ARCH_BITS == 64
653	RTRCPTR padding;
654	#endif
655	/** Pointer to the R3 callback function for invalidation. */
656	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657	/** Pointer to the R3 callback function. */
658	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659	/** Description / Name. For easing debugging. */
660	R3PTRTYPE(const char *) pszDesc;
661	#ifdef VBOX_WITH_STATISTICS
662	/** Profiling of this handler. */
663	STAMPROFILE Stat;
664	#endif
665	/** Array of cached physical addresses for the monitored ranged. */
666	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667	} PGMVIRTHANDLER;
668	/** Pointer to a virtual page access handler structure. */
669	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672	/** @name Page type predicates.
673	* @{ */
674	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679	/** @} */
680
681
682	/**
683	* A Physical Guest Page tracking structure.
684	*
685	* The format of this structure is complicated because we have to fit a lot
686	* of information into as few bits as possible. The format is also subject
687	* to change (there is one coming up soon). Which means that for we'll be
688	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
689	* accesses to the structure.
690	*/
691	typedef union PGMPAGE
692	{
693	/** Structured view. */
694	struct
695	{
696	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
697	uint64_t u2HandlerPhysStateY : 2;
698	/** 3:2 - Paging structure needed to map the page
699	* (PGM_PAGE_PDE_TYPE_). /
700	uint64_t u2PDETypeY : 2;
701	/** 4 - Indicator of dirty page for fault tolerance tracking. */
702	uint64_t fFTDirtyY : 1;
703	/** 5 - Flag indicating that a write monitored page was written to
704	* when set. */
705	uint64_t fWrittenToY : 1;
706	/** 7:6 - Unused. */
707	uint64_t u2Unused0 : 2;
708	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
709	uint64_t u2HandlerVirtStateY : 2;
710	/** 11:10 - Unused. */
711	uint64_t u2Unused1 : 2;
712	/** 12:48 - The host physical frame number (shift left to get the
713	* address). */
714	uint64_t HCPhysFN : 36;
715	/** 50:48 - The page state. */
716	uint64_t uStateY : 3;
717	/** 51:53 - The page type (PGMPAGETYPE). */
718	uint64_t uTypeY : 3;
719	/** 63:54 - PTE index for usage tracking (page pool). */
720	uint64_t u10PteIdx : 10;
721
722	/** The GMM page ID. */
723	uint32_t idPage;
724	/** Usage tracking (page pool). */
725	uint16_t u16TrackingY;
726	/** The number of read locks on this page. */
727	uint8_t cReadLocksY;
728	/** The number of write locks on this page. */
729	uint8_t cWriteLocksY;
730	} s;
731
732	/** 64-bit integer view. */
733	uint64_t au64[2];
734	/** 16-bit view. */
735	uint32_t au32[4];
736	/** 16-bit view. */
737	uint16_t au16[8];
738	/** 8-bit view. */
739	uint8_t au8[16];
740	} PGMPAGE;
741	AssertCompileSize(PGMPAGE, 16);
742	/** Pointer to a physical guest page. */
743	typedef PGMPAGE *PPGMPAGE;
744	/** Pointer to a const physical guest page. */
745	typedef const PGMPAGE *PCPGMPAGE;
746	/** Pointer to a physical guest page pointer. */
747	typedef PPGMPAGE *PPPGMPAGE;
748
749
750	/**
751	* Clears the page structure.
752	* @param a_pPage Pointer to the physical guest page tracking structure.
753	*/
754	#define PGM_PAGE_CLEAR(a_pPage) \
755	do { \
756	(a_pPage)->au64[0] = 0; \
757	(a_pPage)->au64[1] = 0; \
758	} while (0)
759
760	/**
761	* Initializes the page structure.
762	* @param a_pPage Pointer to the physical guest page tracking structure.
763	*/
764	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
765	do { \
766	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
767	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
768	(a_pPage)->au64[0] = SetHCPhysTmp; \
769	(a_pPage)->au64[1] = 0; \
770	(a_pPage)->s.idPage = (a_idPage); \
771	(a_pPage)->s.uStateY = (a_uState); \
772	(a_pPage)->s.uTypeY = (a_uType); \
773	} while (0)
774
775	/**
776	* Initializes the page structure of a ZERO page.
777	* @param a_pPage Pointer to the physical guest page tracking structure.
778	* @param a_pVM The VM handle (for getting the zero page address).
779	* @param a_uType The page type (PGMPAGETYPE).
780	*/
781	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
782	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
783
784
785	/** @name The Page state, PGMPAGE::uStateY.
786	* @{ */
787	/** The zero page.
788	* This is a per-VM page that's never ever mapped writable. */
789	#define PGM_PAGE_STATE_ZERO 0
790	/** A allocated page.
791	* This is a per-VM page allocated from the page pool (or wherever
792	* we get MMIO2 pages from if the type is MMIO2).
793	*/
794	#define PGM_PAGE_STATE_ALLOCATED 1
795	/** A allocated page that's being monitored for writes.
796	* The shadow page table mappings are read-only. When a write occurs, the
797	* fWrittenTo member is set, the page remapped as read-write and the state
798	* moved back to allocated. */
799	#define PGM_PAGE_STATE_WRITE_MONITORED 2
800	/** The page is shared, aka. copy-on-write.
801	* This is a page that's shared with other VMs. */
802	#define PGM_PAGE_STATE_SHARED 3
803	/** The page is ballooned, so no longer available for this VM. */
804	#define PGM_PAGE_STATE_BALLOONED 4
805	/** @} */
806
807
808	/**
809	* Gets the page state.
810	* @returns page state (PGM_PAGE_STATE_*).
811	* @param a_pPage Pointer to the physical guest page tracking structure.
812	*/
813	#define PGM_PAGE_GET_STATE(a_pPage) ( (a_pPage)->s.uStateY )
814
815	/**
816	* Sets the page state.
817	* @param a_pPage Pointer to the physical guest page tracking structure.
818	* @param a_uState The new page state.
819	*/
820	#define PGM_PAGE_SET_STATE(a_pPage, a_uState) do { (a_pPage)->s.uStateY = (a_uState); } while (0)
821
822
823	/**
824	* Gets the host physical address of the guest page.
825	* @returns host physical address (RTHCPHYS).
826	* @param a_pPage Pointer to the physical guest page tracking structure.
827	*/
828	#if 0
829	#define PGM_PAGE_GET_HCPHYS(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
830	#else
831	#define PGM_PAGE_GET_HCPHYS(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
832	#endif
833
834	/**
835	* Sets the host physical address of the guest page.
836	* @param a_pPage Pointer to the physical guest page tracking structure.
837	* @param a_HCPhys The new host physical address.
838	*/
839	#define PGM_PAGE_SET_HCPHYS(a_pPage, a_HCPhys) \
840	do { \
841	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
842	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
843	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
844	} while (0)
845
846	/**
847	* Get the Page ID.
848	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
849	* @param a_pPage Pointer to the physical guest page tracking structure.
850	*/
851	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
852
853	/**
854	* Sets the Page ID.
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	* @param a_idPage The new page ID.
857	*/
858	#define PGM_PAGE_SET_PAGEID(a_pPage, a_idPage) \
859	do { \
860	(a_pPage)->s.idPage = (a_idPage); \
861	} while (0)
862
863	/**
864	* Get the Chunk ID.
865	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
866	* @param a_pPage Pointer to the physical guest page tracking structure.
867	*/
868	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
869
870	/**
871	* Get the index of the page within the allocation chunk.
872	* @returns The page index.
873	* @param a_pPage Pointer to the physical guest page tracking structure.
874	*/
875	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
876
877	/**
878	* Gets the page type.
879	* @returns The page type.
880	* @param a_pPage Pointer to the physical guest page tracking structure.
881	*/
882	#define PGM_PAGE_GET_TYPE(a_pPage) ( (a_pPage)->s.uTypeY )
883
884	/**
885	* Sets the page type.
886	* @param a_pPage Pointer to the physical guest page tracking structure.
887	* @param a_enmType The new page type (PGMPAGETYPE).
888	*/
889	#define PGM_PAGE_SET_TYPE(a_pPage, a_enmType) do { (a_pPage)->s.uTypeY = (a_enmType); } while (0)
890
891	/**
892	* Gets the page table index
893	* @returns The page table index.
894	* @param a_pPage Pointer to the physical guest page tracking structure.
895	*/
896	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
897
898	/**
899	* Sets the page table index.
900	* @param a_pPage Pointer to the physical guest page tracking structure.
901	* @param a_iPte New page table index.
902	*/
903	#define PGM_PAGE_SET_PTE_INDEX(a_pPage, a_iPte) do { (a_pPage)->s.u10PteIdx = (a_iPte); } while (0)
904
905	/**
906	* Checks if the page is marked for MMIO.
907	* @returns true/false.
908	* @param a_pPage Pointer to the physical guest page tracking structure.
909	*/
910	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
911
912	/**
913	* Checks if the page is backed by the ZERO page.
914	* @returns true/false.
915	* @param a_pPage Pointer to the physical guest page tracking structure.
916	*/
917	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
918
919	/**
920	* Checks if the page is backed by a SHARED page.
921	* @returns true/false.
922	* @param a_pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
925
926	/**
927	* Checks if the page is ballooned.
928	* @returns true/false.
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*/
931	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
932
933	/**
934	* Checks if the page is allocated.
935	* @returns true/false.
936	* @param a_pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
939
940	/**
941	* Marks the page as written to (for GMM change monitoring).
942	* @param a_pPage Pointer to the physical guest page tracking structure.
943	*/
944	#define PGM_PAGE_SET_WRITTEN_TO(a_pPage) do { (a_pPage)->au8[1] \|= UINT8_C(0x80); } while (0) /// FIXME FIXME
945
946	/**
947	* Clears the written-to indicator.
948	* @param a_pPage Pointer to the physical guest page tracking structure.
949	*/
950	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pPage) do { (a_pPage)->s.fWrittenToY = 0; } while (0)
951
952	/**
953	* Checks if the page was marked as written-to.
954	* @returns true/false.
955	* @param a_pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
958
959	/**
960	* Marks the page as dirty for FTM
961	* @param a_pPage Pointer to the physical guest page tracking structure.
962	*/
963	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
964
965	/**
966	* Clears the FTM dirty indicator
967	* @param a_pPage Pointer to the physical guest page tracking structure.
968	*/
969	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
970
971	/**
972	* Checks if the page was marked as dirty for FTM
973	* @returns true/false.
974	* @param a_pPage Pointer to the physical guest page tracking structure.
975	*/
976	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
977
978
979	/** @name PT usage values (PGMPAGE::u2PDEType).
980	*
981	* @{ */
982	/** Either as a PT or PDE. */
983	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
984	/** Must use a page table to map the range. */
985	#define PGM_PAGE_PDE_TYPE_PT 1
986	/** Can use a page directory entry to map the continuous range. */
987	#define PGM_PAGE_PDE_TYPE_PDE 2
988	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
989	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
990	/** @} */
991
992	/**
993	* Set the PDE type of the page
994	* @param a_pPage Pointer to the physical guest page tracking structure.
995	* @param a_uType PGM_PAGE_PDE_TYPE_*.
996	*/
997	#define PGM_PAGE_SET_PDE_TYPE(a_pPage, a_uType) \
998	do { (a_pPage)->s.u2PDETypeY = (a_uType); } while (0)
999
1000	/**
1001	* Checks if the page was marked being part of a large page
1002	* @returns true/false.
1003	* @param a_pPage Pointer to the physical guest page tracking structure.
1004	*/
1005	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1006
1007	/** Enabled optimized access handler tests.
1008	* These optimizations makes ASSUMPTIONS about the state values and the s1
1009	* layout. When enabled, the compiler should normally generate more compact
1010	* code.
1011	*/
1012	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1013
1014	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1015	*
1016	* @remarks The values are assigned in order of priority, so we can calculate
1017	* the correct state for a page with different handlers installed.
1018	* @{ */
1019	/** No handler installed. */
1020	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1021	/** Monitoring is temporarily disabled. */
1022	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1023	/** Write access is monitored. */
1024	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1025	/** All access is monitored. */
1026	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1027	/** @} */
1028
1029	/**
1030	* Gets the physical access handler state of a page.
1031	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1032	* @param a_pPage Pointer to the physical guest page tracking structure.
1033	*/
1034	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1035
1036	/**
1037	* Sets the physical access handler state of a page.
1038	* @param a_pPage Pointer to the physical guest page tracking structure.
1039	* @param a_uState The new state value.
1040	*/
1041	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1042	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1043
1044	/**
1045	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1046	* @returns true/false
1047	* @param a_pPage Pointer to the physical guest page tracking structure.
1048	*/
1049	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1050	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1051
1052	/**
1053	* Checks if the page has any active physical access handlers.
1054	* @returns true/false
1055	* @param a_pPage Pointer to the physical guest page tracking structure.
1056	*/
1057	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1058	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1059
1060
1061	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1062	*
1063	* @remarks The values are assigned in order of priority, so we can calculate
1064	* the correct state for a page with different handlers installed.
1065	* @{ */
1066	/** No handler installed. */
1067	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1068	/* 1 is reserved so the lineup is identical with the physical ones. */
1069	/** Write access is monitored. */
1070	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1071	/** All access is monitored. */
1072	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1073	/** @} */
1074
1075	/**
1076	* Gets the virtual access handler state of a page.
1077	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1078	* @param a_pPage Pointer to the physical guest page tracking structure.
1079	*/
1080	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1081
1082	/**
1083	* Sets the virtual access handler state of a page.
1084	* @param a_pPage Pointer to the physical guest page tracking structure.
1085	* @param a_uState The new state value.
1086	*/
1087	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1088	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1089
1090	/**
1091	* Checks if the page has any virtual access handlers.
1092	* @returns true/false
1093	* @param a_pPage Pointer to the physical guest page tracking structure.
1094	*/
1095	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1096	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1097
1098	/**
1099	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1100	* virtual handlers.
1101	* @returns true/false
1102	* @param a_pPage Pointer to the physical guest page tracking structure.
1103	*/
1104	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1105	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1106
1107
1108	/**
1109	* Checks if the page has any access handlers, including temporarily disabled ones.
1110	* @returns true/false
1111	* @param a_pPage Pointer to the physical guest page tracking structure.
1112	*/
1113	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1114	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1115	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1116	#else
1117	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1118	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1119	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1120	#endif
1121
1122	/**
1123	* Checks if the page has any active access handlers.
1124	* @returns true/false
1125	* @param a_pPage Pointer to the physical guest page tracking structure.
1126	*/
1127	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1128	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1129	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1130	#else
1131	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1132	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1133	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1134	#endif
1135
1136	/**
1137	* Checks if the page has any active access handlers catching all accesses.
1138	* @returns true/false
1139	* @param a_pPage Pointer to the physical guest page tracking structure.
1140	*/
1141	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1142	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1143	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1144	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1145	#else
1146	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1147	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1148	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1149	#endif
1150
1151
1152	/** @def PGM_PAGE_GET_TRACKING
1153	* Gets the packed shadow page pool tracking data associated with a guest page.
1154	* @returns uint16_t containing the data.
1155	* @param a_pPage Pointer to the physical guest page tracking structure.
1156	*/
1157	#define PGM_PAGE_GET_TRACKING(a_pPage) ( (a_pPage)->s.u16TrackingY )
1158
1159	/** @def PGM_PAGE_SET_TRACKING
1160	* Sets the packed shadow page pool tracking data associated with a guest page.
1161	* @param a_pPage Pointer to the physical guest page tracking structure.
1162	* @param a_u16TrackingData The tracking data to store.
1163	*/
1164	#define PGM_PAGE_SET_TRACKING(a_pPage, a_u16TrackingData) \
1165	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); } while (0)
1166
1167	/** @def PGM_PAGE_GET_TD_CREFS
1168	* Gets the @a cRefs tracking data member.
1169	* @returns cRefs.
1170	* @param a_pPage Pointer to the physical guest page tracking structure.
1171	*/
1172	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1173	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1174
1175	/** @def PGM_PAGE_GET_TD_IDX
1176	* Gets the @a idx tracking data member.
1177	* @returns idx.
1178	* @param a_pPage Pointer to the physical guest page tracking structure.
1179	*/
1180	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1181	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1182
1183
1184	/** Max number of locks on a page. */
1185	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1186
1187	/** Get the read lock count.
1188	* @returns count.
1189	* @param a_pPage Pointer to the physical guest page tracking structure.
1190	*/
1191	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1192
1193	/** Get the write lock count.
1194	* @returns count.
1195	* @param a_pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1198
1199	/** Decrement the read lock counter.
1200	* @param a_pPage Pointer to the physical guest page tracking structure.
1201	*/
1202	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1203
1204	/** Decrement the write lock counter.
1205	* @param a_pPage Pointer to the physical guest page tracking structure.
1206	*/
1207	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1208
1209	/** Increment the read lock counter.
1210	* @param a_pPage Pointer to the physical guest page tracking structure.
1211	*/
1212	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1213
1214	/** Increment the write lock counter.
1215	* @param a_pPage Pointer to the physical guest page tracking structure.
1216	*/
1217	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1218
1219
1220	#if 0
1221	/** Enables sanity checking of write monitoring using CRC-32. */
1222	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1223	#endif
1224
1225	/**
1226	* Per page live save tracking data.
1227	*/
1228	typedef struct PGMLIVESAVERAMPAGE
1229	{
1230	/** Number of times it has been dirtied. */
1231	uint32_t cDirtied : 24;
1232	/** Whether it is currently dirty. */
1233	uint32_t fDirty : 1;
1234	/** Ignore the page.
1235	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1236	* deal with these after pausing the VM and DevPCI have said it bit about
1237	* remappings. */
1238	uint32_t fIgnore : 1;
1239	/** Was a ZERO page last time around. */
1240	uint32_t fZero : 1;
1241	/** Was a SHARED page last time around. */
1242	uint32_t fShared : 1;
1243	/** Whether the page is/was write monitored in a previous pass. */
1244	uint32_t fWriteMonitored : 1;
1245	/** Whether the page is/was write monitored earlier in this pass. */
1246	uint32_t fWriteMonitoredJustNow : 1;
1247	/** Bits reserved for future use. */
1248	uint32_t u2Reserved : 2;
1249	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250	/** CRC-32 for the page. This is for internal consistency checks. */
1251	uint32_t u32Crc;
1252	#endif
1253	} PGMLIVESAVERAMPAGE;
1254	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1255	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1256	#else
1257	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1258	#endif
1259	/** Pointer to the per page live save tracking data. */
1260	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1261
1262	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1263	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1264
1265
1266	/** Enables the RAM range search trees. */
1267	#define PGM_USE_RAMRANGE_SEARCH_TREES
1268
1269	/**
1270	* RAM range for GC Phys to HC Phys conversion.
1271	*
1272	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1273	* conversions too, but we'll let MM handle that for now.
1274	*
1275	* This structure is used by linked lists in both GC and HC.
1276	*/
1277	typedef struct PGMRAMRANGE
1278	{
1279	/** Start of the range. Page aligned. */
1280	RTGCPHYS GCPhys;
1281	/** Size of the range. (Page aligned of course). */
1282	RTGCPHYS cb;
1283	/** Pointer to the next RAM range - for R3. */
1284	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1285	/** Pointer to the next RAM range - for R0. */
1286	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1287	/** Pointer to the next RAM range - for RC. */
1288	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1289	/** PGM_RAM_RANGE_FLAGS_* flags. */
1290	uint32_t fFlags;
1291	/** Last address in the range (inclusive). Page aligned (-1). */
1292	RTGCPHYS GCPhysLast;
1293	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1294	R3PTRTYPE(void *) pvR3;
1295	/** Live save per page tracking data. */
1296	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1297	/** The range description. */
1298	R3PTRTYPE(const char *) pszDesc;
1299	/** Pointer to self - R0 pointer. */
1300	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1301	/** Pointer to self - RC pointer. */
1302	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1303
1304	#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1305	/** Alignment padding. */
1306	RTRCPTR Alignment0;
1307	/** Pointer to the left search three node - ring-3 context. */
1308	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1309	/** Pointer to the right search three node - ring-3 context. */
1310	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1311	/** Pointer to the left search three node - ring-0 context. */
1312	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1313	/** Pointer to the right search three node - ring-0 context. */
1314	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1315	/** Pointer to the left search three node - raw-mode context. */
1316	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1317	/** Pointer to the right search three node - raw-mode context. */
1318	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1319	#endif
1320
1321	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1322	#ifdef PGM_USE_RAMRANGE_SEARCH_TREES
1323	# if HC_ARCH_BITS == 32
1324	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1325	# endif
1326	#else
1327	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1328	#endif
1329	/** Array of physical guest page tracking structures. */
1330	PGMPAGE aPages[1];
1331	} PGMRAMRANGE;
1332	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1333	typedef PGMRAMRANGE *PPGMRAMRANGE;
1334
1335	/** @name PGMRAMRANGE::fFlags
1336	* @{ */
1337	/** The RAM range is floating around as an independent guest mapping. */
1338	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1339	/** Ad hoc RAM range for an ROM mapping. */
1340	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1341	/** Ad hoc RAM range for an MMIO mapping. */
1342	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1343	/** Ad hoc RAM range for an MMIO2 mapping. */
1344	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1345	/** @} */
1346
1347	/** Tests if a RAM range is an ad hoc one or not.
1348	* @returns true/false.
1349	* @param pRam The RAM range.
1350	*/
1351	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1352	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1353
1354	/** The number of entries in the RAM range TLBs (there is one for each
1355	* context). Must be a power of two. */
1356	#define PGM_RAMRANGE_TLB_ENTRIES 8
1357
1358	/**
1359	* Calculates the RAM range TLB index for the physical address.
1360	*
1361	* @returns RAM range TLB index.
1362	* @param GCPhys The guest physical address.
1363	*/
1364	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1365
1366
1367
1368	/**
1369	* Per page tracking structure for ROM image.
1370	*
1371	* A ROM image may have a shadow page, in which case we may have two pages
1372	* backing it. This structure contains the PGMPAGE for both while
1373	* PGMRAMRANGE have a copy of the active one. It is important that these
1374	* aren't out of sync in any regard other than page pool tracking data.
1375	*/
1376	typedef struct PGMROMPAGE
1377	{
1378	/** The page structure for the virgin ROM page. */
1379	PGMPAGE Virgin;
1380	/** The page structure for the shadow RAM page. */
1381	PGMPAGE Shadow;
1382	/** The current protection setting. */
1383	PGMROMPROT enmProt;
1384	/** Live save status information. Makes use of unused alignment space. */
1385	struct
1386	{
1387	/** The previous protection value. */
1388	uint8_t u8Prot;
1389	/** Written to flag set by the handler. */
1390	bool fWrittenTo;
1391	/** Whether the shadow page is dirty or not. */
1392	bool fDirty;
1393	/** Whether it was dirtied in the recently. */
1394	bool fDirtiedRecently;
1395	} LiveSave;
1396	} PGMROMPAGE;
1397	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1398	/** Pointer to a ROM page tracking structure. */
1399	typedef PGMROMPAGE *PPGMROMPAGE;
1400
1401
1402	/**
1403	* A registered ROM image.
1404	*
1405	* This is needed to keep track of ROM image since they generally intrude
1406	* into a PGMRAMRANGE. It also keeps track of additional info like the
1407	* two page sets (read-only virgin and read-write shadow), the current
1408	* state of each page.
1409	*
1410	* Because access handlers cannot easily be executed in a different
1411	* context, the ROM ranges needs to be accessible and in all contexts.
1412	*/
1413	typedef struct PGMROMRANGE
1414	{
1415	/** Pointer to the next range - R3. */
1416	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1417	/** Pointer to the next range - R0. */
1418	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1419	/** Pointer to the next range - RC. */
1420	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1421	/** Pointer alignment */
1422	RTRCPTR RCPtrAlignment;
1423	/** Address of the range. */
1424	RTGCPHYS GCPhys;
1425	/** Address of the last byte in the range. */
1426	RTGCPHYS GCPhysLast;
1427	/** Size of the range. */
1428	RTGCPHYS cb;
1429	/** The flags (PGMPHYS_ROM_FLAGS_). /
1430	uint32_t fFlags;
1431	/** The saved state range ID. */
1432	uint8_t idSavedState;
1433	/** Alignment padding. */
1434	uint8_t au8Alignment[3];
1435	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1436	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1437	/** The size bits pvOriginal points to. */
1438	uint32_t cbOriginal;
1439	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1440	* This is used for strictness checks. */
1441	R3PTRTYPE(const void *) pvOriginal;
1442	/** The ROM description. */
1443	R3PTRTYPE(const char *) pszDesc;
1444	/** The per page tracking structures. */
1445	PGMROMPAGE aPages[1];
1446	} PGMROMRANGE;
1447	/** Pointer to a ROM range. */
1448	typedef PGMROMRANGE *PPGMROMRANGE;
1449
1450
1451	/**
1452	* Live save per page data for an MMIO2 page.
1453	*
1454	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1455	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1456	* CRC-32 for detecting changes as well as special handling of zero pages. This
1457	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1458	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1459	* because of speed (2.5x and 6x slower).)
1460	*
1461	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1462	* save but normally is disabled. Since we can write monitor guest
1463	* accesses on our own, we only need this for host accesses. Shouldn't be
1464	* too difficult for DevVGA, VMMDev might be doable, the planned
1465	* networking fun will be fun since it involves ring-0.
1466	*/
1467	typedef struct PGMLIVESAVEMMIO2PAGE
1468	{
1469	/** Set if the page is considered dirty. */
1470	bool fDirty;
1471	/** The number of scans this page has remained unchanged for.
1472	* Only updated for dirty pages. */
1473	uint8_t cUnchangedScans;
1474	/** Whether this page was zero at the last scan. */
1475	bool fZero;
1476	/** Alignment padding. */
1477	bool fReserved;
1478	/** CRC-32 for the first half of the page.
1479	* This is used together with u32CrcH2 to quickly detect changes in the page
1480	* during the non-final passes. */
1481	uint32_t u32CrcH1;
1482	/** CRC-32 for the second half of the page. */
1483	uint32_t u32CrcH2;
1484	/** SHA-1 for the saved page.
1485	* This is used in the final pass to skip pages without changes. */
1486	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1487	} PGMLIVESAVEMMIO2PAGE;
1488	/** Pointer to a live save status data for an MMIO2 page. */
1489	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1490
1491	/**
1492	* A registered MMIO2 (= Device RAM) range.
1493	*
1494	* There are a few reason why we need to keep track of these
1495	* registrations. One of them is the deregistration & cleanup stuff,
1496	* while another is that the PGMRAMRANGE associated with such a region may
1497	* have to be removed from the ram range list.
1498	*
1499	* Overlapping with a RAM range has to be 100% or none at all. The pages
1500	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1501	* will be raised if a partial overlap or an overlap of ROM pages is
1502	* encountered. On an overlap we will free all the existing RAM pages and
1503	* put in the ram range pages instead.
1504	*/
1505	typedef struct PGMMMIO2RANGE
1506	{
1507	/** The owner of the range. (a device) */
1508	PPDMDEVINSR3 pDevInsR3;
1509	/** Pointer to the ring-3 mapping of the allocation. */
1510	RTR3PTR pvR3;
1511	/** Pointer to the next range - R3. */
1512	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1513	/** Whether it's mapped or not. */
1514	bool fMapped;
1515	/** Whether it's overlapping or not. */
1516	bool fOverlapping;
1517	/** The PCI region number.
1518	* @remarks This ASSUMES that nobody will ever really need to have multiple
1519	* PCI devices with matching MMIO region numbers on a single device. */
1520	uint8_t iRegion;
1521	/** The saved state range ID. */
1522	uint8_t idSavedState;
1523	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1524	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1525	/** Live save per page tracking data. */
1526	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1527	/** The associated RAM range. */
1528	PGMRAMRANGE RamRange;
1529	} PGMMMIO2RANGE;
1530	/** Pointer to a MMIO2 range. */
1531	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1532
1533
1534
1535
1536	/**
1537	* PGMPhysRead/Write cache entry
1538	*/
1539	typedef struct PGMPHYSCACHEENTRY
1540	{
1541	/** R3 pointer to physical page. */
1542	R3PTRTYPE(uint8_t *) pbR3;
1543	/** GC Physical address for cache entry */
1544	RTGCPHYS GCPhys;
1545	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1546	RTGCPHYS u32Padding0; /*< alignment padding. /
1547	#endif
1548	} PGMPHYSCACHEENTRY;
1549
1550	/**
1551	* PGMPhysRead/Write cache to reduce REM memory access overhead
1552	*/
1553	typedef struct PGMPHYSCACHE
1554	{
1555	/** Bitmap of valid cache entries */
1556	uint64_t aEntries;
1557	/** Cache entries */
1558	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1559	} PGMPHYSCACHE;
1560
1561
1562	/** Pointer to an allocation chunk ring-3 mapping. */
1563	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1564	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1565	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1566
1567	/**
1568	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1569	*
1570	* The primary tree (Core) uses the chunk id as key.
1571	*/
1572	typedef struct PGMCHUNKR3MAP
1573	{
1574	/** The key is the chunk id. */
1575	AVLU32NODECORE Core;
1576	/** The current age thingy. */
1577	uint32_t iAge;
1578	/** The current reference count. */
1579	uint32_t volatile cRefs;
1580	/** The current permanent reference count. */
1581	uint32_t volatile cPermRefs;
1582	/** The mapping address. */
1583	void *pv;
1584	} PGMCHUNKR3MAP;
1585
1586	/**
1587	* Allocation chunk ring-3 mapping TLB entry.
1588	*/
1589	typedef struct PGMCHUNKR3MAPTLBE
1590	{
1591	/** The chunk id. */
1592	uint32_t volatile idChunk;
1593	#if HC_ARCH_BITS == 64
1594	uint32_t u32Padding; /*< alignment padding. /
1595	#endif
1596	/** The chunk map. */
1597	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1598	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1599	#else
1600	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1601	#endif
1602	} PGMCHUNKR3MAPTLBE;
1603	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1604	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1605
1606	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1607	* @remark Must be a power of two value. */
1608	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1609
1610	/**
1611	* Allocation chunk ring-3 mapping TLB.
1612	*
1613	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1614	* At first glance this might look kinda odd since AVL trees are
1615	* supposed to give the most optimal lookup times of all trees
1616	* due to their balancing. However, take a tree with 1023 nodes
1617	* in it, that's 10 levels, meaning that most searches has to go
1618	* down 9 levels before they find what they want. This isn't fast
1619	* compared to a TLB hit. There is the factor of cache misses,
1620	* and of course the problem with trees and branch prediction.
1621	* This is why we use TLBs in front of most of the trees.
1622	*
1623	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1624	* difficult when we switch to the new inlined AVL trees (from kStuff).
1625	*/
1626	typedef struct PGMCHUNKR3MAPTLB
1627	{
1628	/** The TLB entries. */
1629	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1630	} PGMCHUNKR3MAPTLB;
1631
1632	/**
1633	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1634	* @returns Chunk TLB index.
1635	* @param idChunk The Chunk ID.
1636	*/
1637	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1638
1639
1640	/**
1641	* Ring-3 guest page mapping TLB entry.
1642	* @remarks used in ring-0 as well at the moment.
1643	*/
1644	typedef struct PGMPAGER3MAPTLBE
1645	{
1646	/** Address of the page. */
1647	RTGCPHYS volatile GCPhys;
1648	/** The guest page. */
1649	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1650	R3PTRTYPE(PPGMPAGE) volatile pPage;
1651	#else
1652	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1653	#endif
1654	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1655	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1656	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1657	#else
1658	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1659	#endif
1660	/** The address */
1661	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1662	R3PTRTYPE(void *) volatile pv;
1663	#else
1664	R3R0PTRTYPE(void *) volatile pv;
1665	#endif
1666	#if HC_ARCH_BITS == 32
1667	uint32_t u32Padding; /*< alignment padding. /
1668	#endif
1669	} PGMPAGER3MAPTLBE;
1670	/** Pointer to an entry in the HC physical TLB. */
1671	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1672
1673
1674	/** The number of entries in the ring-3 guest page mapping TLB.
1675	* @remarks The value must be a power of two. */
1676	#define PGM_PAGER3MAPTLB_ENTRIES 256
1677
1678	/**
1679	* Ring-3 guest page mapping TLB.
1680	* @remarks used in ring-0 as well at the moment.
1681	*/
1682	typedef struct PGMPAGER3MAPTLB
1683	{
1684	/** The TLB entries. */
1685	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1686	} PGMPAGER3MAPTLB;
1687	/** Pointer to the ring-3 guest page mapping TLB. */
1688	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1689
1690	/**
1691	* Calculates the index of the TLB entry for the specified guest page.
1692	* @returns Physical TLB index.
1693	* @param GCPhys The guest physical address.
1694	*/
1695	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1696
1697
1698	/**
1699	* Raw-mode context dynamic mapping cache entry.
1700	*
1701	* Because of raw-mode context being reloctable and all relocations are applied
1702	* in ring-3, this has to be defined here and be RC specific.
1703	*
1704	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1705	*/
1706	typedef struct PGMRCDYNMAPENTRY
1707	{
1708	/** The physical address of the currently mapped page.
1709	* This is duplicate for three reasons: cache locality, cache policy of the PT
1710	* mappings and sanity checks. */
1711	RTHCPHYS HCPhys;
1712	/** Pointer to the page. */
1713	RTRCPTR pvPage;
1714	/** The number of references. */
1715	int32_t volatile cRefs;
1716	/** PTE pointer union. */
1717	struct PGMRCDYNMAPENTRY_PPTE
1718	{
1719	/** PTE pointer, 32-bit legacy version. */
1720	RCPTRTYPE(PX86PTE) pLegacy;
1721	/** PTE pointer, PAE version. */
1722	RCPTRTYPE(PX86PTEPAE) pPae;
1723	} uPte;
1724	} PGMRCDYNMAPENTRY;
1725	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1726	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1727
1728
1729	/**
1730	* Dynamic mapping cache for the raw-mode context.
1731	*
1732	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1733	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1734	* so that we can perform relocations from PGMR3Relocate. This has the
1735	* consequence that we must have separate ring-0 and raw-mode context versions
1736	* of this struct even if they share the basic elements.
1737	*
1738	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1739	*/
1740	typedef struct PGMRCDYNMAP
1741	{
1742	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1743	uint32_t u32Magic;
1744	/** Array for tracking and managing the pages. */
1745	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1746	/** The cache size given as a number of pages. */
1747	uint32_t cPages;
1748	/** The current load.
1749	* This does not include guard pages. */
1750	uint32_t cLoad;
1751	/** The max load ever.
1752	* This is maintained to get trigger adding of more mapping space. */
1753	uint32_t cMaxLoad;
1754	/** The number of guard pages. */
1755	uint32_t cGuardPages;
1756	/** The number of users (protected by hInitLock). */
1757	uint32_t cUsers;
1758	} PGMRCDYNMAP;
1759	/** Pointer to the dynamic cache for the raw-mode context. */
1760	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1761
1762
1763	/**
1764	* Mapping cache usage set entry.
1765	*
1766	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1767	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1768	* cache. If it's extended to include ring-3, well, then something
1769	* will have be changed here...
1770	*/
1771	typedef struct PGMMAPSETENTRY
1772	{
1773	/** Pointer to the page. */
1774	#ifndef IN_RC
1775	RTR0PTR pvPage;
1776	#else
1777	RTRCPTR pvPage;
1778	# if HC_ARCH_BITS == 64
1779	uint32_t u32Alignment2;
1780	# endif
1781	#endif
1782	/** The mapping cache index. */
1783	uint16_t iPage;
1784	/** The number of references.
1785	* The max is UINT16_MAX - 1. */
1786	uint16_t cRefs;
1787	/** The number inlined references.
1788	* The max is UINT16_MAX - 1. */
1789	uint16_t cInlinedRefs;
1790	/** Unreferences. */
1791	uint16_t cUnrefs;
1792
1793	#if HC_ARCH_BITS == 32
1794	uint32_t u32Alignment1;
1795	#endif
1796	/** The physical address for this entry. */
1797	RTHCPHYS HCPhys;
1798	} PGMMAPSETENTRY;
1799	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1800	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1801	/** Pointer to a mapping cache usage set entry. */
1802	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1803
1804	/**
1805	* Mapping cache usage set.
1806	*
1807	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1808	* done during exits / traps. The set is
1809	*/
1810	typedef struct PGMMAPSET
1811	{
1812	/** The number of occupied entries.
1813	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1814	* dynamic mappings. */
1815	uint32_t cEntries;
1816	/** The start of the current subset.
1817	* This is UINT32_MAX if no subset is currently open. */
1818	uint32_t iSubset;
1819	/** The index of the current CPU, only valid if the set is open. */
1820	int32_t iCpu;
1821	uint32_t alignment;
1822	/** The entries. */
1823	PGMMAPSETENTRY aEntries[64];
1824	/** HCPhys -> iEntry fast lookup table.
1825	* Use PGMMAPSET_HASH for hashing.
1826	* The entries may or may not be valid, check against cEntries. */
1827	uint8_t aiHashTable[128];
1828	} PGMMAPSET;
1829	AssertCompileSizeAlignment(PGMMAPSET, 8);
1830	/** Pointer to the mapping cache set. */
1831	typedef PGMMAPSET *PPGMMAPSET;
1832
1833	/** PGMMAPSET::cEntries value for a closed set. */
1834	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1835
1836	/** Hash function for aiHashTable. */
1837	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1838
1839
1840	/** @name Context neutral page mapper TLB.
1841	*
1842	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1843	* code is writting in a kind of context neutral way. Time will show whether
1844	* this actually makes sense or not...
1845	*
1846	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1847	* context ends up using a global mapping cache on some platforms
1848	* (darwin).
1849	*
1850	* @{ */
1851	/** @typedef PPGMPAGEMAPTLB
1852	* The page mapper TLB pointer type for the current context. */
1853	/** @typedef PPGMPAGEMAPTLB
1854	* The page mapper TLB entry pointer type for the current context. */
1855	/** @typedef PPGMPAGEMAPTLB
1856	* The page mapper TLB entry pointer pointer type for the current context. */
1857	/** @def PGM_PAGEMAPTLB_ENTRIES
1858	* The number of TLB entries in the page mapper TLB for the current context. */
1859	/** @def PGM_PAGEMAPTLB_IDX
1860	* Calculate the TLB index for a guest physical address.
1861	* @returns The TLB index.
1862	* @param GCPhys The guest physical address. */
1863	/** @typedef PPGMPAGEMAP
1864	* Pointer to a page mapper unit for current context. */
1865	/** @typedef PPPGMPAGEMAP
1866	* Pointer to a page mapper unit pointer for current context. */
1867	#ifdef IN_RC
1868	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1869	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1870	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1871	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1872	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1873	typedef void * PPGMPAGEMAP;
1874	typedef void ** PPPGMPAGEMAP;
1875	//#elif IN_RING0
1876	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1877	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1878	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1879	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1880	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1881	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1882	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1883	#else
1884	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1885	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1886	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1887	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1888	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1889	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1890	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1891	#endif
1892	/** @} */
1893
1894
1895	/** @name PGM Pool Indexes.
1896	* Aka. the unique shadow page identifier.
1897	* @{ */
1898	/** NIL page pool IDX. */
1899	#define NIL_PGMPOOL_IDX 0
1900	/** The first normal index. */
1901	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1902	/** Page directory (32-bit root). */
1903	#define PGMPOOL_IDX_PD 1
1904	/** Page Directory Pointer Table (PAE root). */
1905	#define PGMPOOL_IDX_PDPT 2
1906	/** AMD64 CR3 level index.*/
1907	#define PGMPOOL_IDX_AMD64_CR3 3
1908	/** Nested paging root.*/
1909	#define PGMPOOL_IDX_NESTED_ROOT 4
1910	/** The first normal index. */
1911	#define PGMPOOL_IDX_FIRST 5
1912	/** The last valid index. (inclusive, 14 bits) */
1913	#define PGMPOOL_IDX_LAST 0x3fff
1914	/** @} */
1915
1916	/** The NIL index for the parent chain. */
1917	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1918	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1919
1920	/**
1921	* Node in the chain linking a shadowed page to it's parent (user).
1922	*/
1923	#pragma pack(1)
1924	typedef struct PGMPOOLUSER
1925	{
1926	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1927	uint16_t iNext;
1928	/** The user page index. */
1929	uint16_t iUser;
1930	/** Index into the user table. */
1931	uint32_t iUserTable;
1932	} PGMPOOLUSER, *PPGMPOOLUSER;
1933	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1934	#pragma pack()
1935
1936
1937	/** The NIL index for the phys ext chain. */
1938	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1939	/** The NIL pte index for a phys ext chain slot. */
1940	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1941
1942	/**
1943	* Node in the chain of physical cross reference extents.
1944	* @todo Calling this an 'extent' is not quite right, find a better name.
1945	* @todo find out the optimal size of the aidx array
1946	*/
1947	#pragma pack(1)
1948	typedef struct PGMPOOLPHYSEXT
1949	{
1950	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1951	uint16_t iNext;
1952	/** Alignment. */
1953	uint16_t u16Align;
1954	/** The user page index. */
1955	uint16_t aidx[3];
1956	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1957	uint16_t apte[3];
1958	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1959	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1960	#pragma pack()
1961
1962
1963	/**
1964	* The kind of page that's being shadowed.
1965	*/
1966	typedef enum PGMPOOLKIND
1967	{
1968	/** The virtual invalid 0 entry. */
1969	PGMPOOLKIND_INVALID = 0,
1970	/** The entry is free (=unused). */
1971	PGMPOOLKIND_FREE,
1972
1973	/** Shw: 32-bit page table; Gst: no paging */
1974	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1975	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1976	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1977	/** Shw: 32-bit page table; Gst: 4MB page. */
1978	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1979	/** Shw: PAE page table; Gst: no paging */
1980	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1981	/** Shw: PAE page table; Gst: 32-bit page table. */
1982	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1983	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1984	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1985	/** Shw: PAE page table; Gst: PAE page table. */
1986	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1987	/** Shw: PAE page table; Gst: 2MB page. */
1988	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1989
1990	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1991	PGMPOOLKIND_32BIT_PD,
1992	/** Shw: 32-bit page directory. Gst: no paging. */
1993	PGMPOOLKIND_32BIT_PD_PHYS,
1994	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1995	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1996	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1997	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1998	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1999	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2000	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2001	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2002	/** Shw: PAE page directory; Gst: PAE page directory. */
2003	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2004	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2005	PGMPOOLKIND_PAE_PD_PHYS,
2006
2007	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2008	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2009	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2010	PGMPOOLKIND_PAE_PDPT,
2011	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2012	PGMPOOLKIND_PAE_PDPT_PHYS,
2013
2014	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2015	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2016	/** Shw: 64-bit page directory pointer table; Gst: no paging */
2017	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2018	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2019	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2020	/** Shw: 64-bit page directory table; Gst: no paging */
2021	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2022
2023	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2024	PGMPOOLKIND_64BIT_PML4,
2025
2026	/** Shw: EPT page directory pointer table; Gst: no paging */
2027	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2028	/** Shw: EPT page directory table; Gst: no paging */
2029	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2030	/** Shw: EPT page table; Gst: no paging */
2031	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2032
2033	/** Shw: Root Nested paging table. */
2034	PGMPOOLKIND_ROOT_NESTED,
2035
2036	/** The last valid entry. */
2037	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2038	} PGMPOOLKIND;
2039
2040	/**
2041	* The access attributes of the page; only applies to big pages.
2042	*/
2043	typedef enum
2044	{
2045	PGMPOOLACCESS_DONTCARE = 0,
2046	PGMPOOLACCESS_USER_RW,
2047	PGMPOOLACCESS_USER_R,
2048	PGMPOOLACCESS_USER_RW_NX,
2049	PGMPOOLACCESS_USER_R_NX,
2050	PGMPOOLACCESS_SUPERVISOR_RW,
2051	PGMPOOLACCESS_SUPERVISOR_R,
2052	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2053	PGMPOOLACCESS_SUPERVISOR_R_NX
2054	} PGMPOOLACCESS;
2055
2056	/**
2057	* The tracking data for a page in the pool.
2058	*/
2059	typedef struct PGMPOOLPAGE
2060	{
2061	/** AVL node code with the (R3) physical address of this page. */
2062	AVLOHCPHYSNODECORE Core;
2063	/** Pointer to the R3 mapping of the page. */
2064	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2065	R3PTRTYPE(void *) pvPageR3;
2066	#else
2067	R3R0PTRTYPE(void *) pvPageR3;
2068	#endif
2069	/** The guest physical address. */
2070	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2071	uint32_t Alignment0;
2072	#endif
2073	RTGCPHYS GCPhys;
2074
2075	/** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2076	RTGCPTR pvLastAccessHandlerRip;
2077	RTGCPTR pvLastAccessHandlerFault;
2078	uint64_t cLastAccessHandlerCount;
2079
2080	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2081	uint8_t enmKind;
2082	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2083	uint8_t enmAccess;
2084	/** The index of this page. */
2085	uint16_t idx;
2086	/** The next entry in the list this page currently resides in.
2087	* It's either in the free list or in the GCPhys hash. */
2088	uint16_t iNext;
2089	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2090	uint16_t iUserHead;
2091	/** The number of present entries. */
2092	uint16_t cPresent;
2093	/** The first entry in the table which is present. */
2094	uint16_t iFirstPresent;
2095	/** The number of modifications to the monitored page. */
2096	uint16_t cModifications;
2097	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2098	uint16_t iModifiedNext;
2099	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2100	uint16_t iModifiedPrev;
2101	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2102	uint16_t iMonitoredNext;
2103	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2104	uint16_t iMonitoredPrev;
2105	/** The next page in the age list. */
2106	uint16_t iAgeNext;
2107	/** The previous page in the age list. */
2108	uint16_t iAgePrev;
2109	/** Used to indicate that the page is zeroed. */
2110	bool fZeroed;
2111	/** Used to indicate that a PT has non-global entries. */
2112	bool fSeenNonGlobal;
2113	/** Used to indicate that we're monitoring writes to the guest page. */
2114	bool fMonitored;
2115	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2116	* (All pages are in the age list.) */
2117	bool fCached;
2118	/** This is used by the R3 access handlers when invoked by an async thread.
2119	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2120	bool volatile fReusedFlushPending;
2121	/** Used to mark the page as dirty (write monitoring is temporarily
2122	* off). */
2123	bool fDirty;
2124
2125	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2126	uint32_t cLocked;
2127	uint32_t idxDirty;
2128	RTGCPTR pvDirtyFault;
2129	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
2130	/** Pointer to a const pool page. */
2131	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2132
2133
2134	/** The hash table size. */
2135	# define PGMPOOL_HASH_SIZE 0x40
2136	/** The hash function. */
2137	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2138
2139
2140	/**
2141	* The shadow page pool instance data.
2142	*
2143	* It's all one big allocation made at init time, except for the
2144	* pages that is. The user nodes follows immediately after the
2145	* page structures.
2146	*/
2147	typedef struct PGMPOOL
2148	{
2149	/** The VM handle - R3 Ptr. */
2150	PVMR3 pVMR3;
2151	/** The VM handle - R0 Ptr. */
2152	PVMR0 pVMR0;
2153	/** The VM handle - RC Ptr. */
2154	PVMRC pVMRC;
2155	/** The max pool size. This includes the special IDs. */
2156	uint16_t cMaxPages;
2157	/** The current pool size. */
2158	uint16_t cCurPages;
2159	/** The head of the free page list. */
2160	uint16_t iFreeHead;
2161	/* Padding. */
2162	uint16_t u16Padding;
2163	/** Head of the chain of free user nodes. */
2164	uint16_t iUserFreeHead;
2165	/** The number of user nodes we've allocated. */
2166	uint16_t cMaxUsers;
2167	/** The number of present page table entries in the entire pool. */
2168	uint32_t cPresent;
2169	/** Pointer to the array of user nodes - RC pointer. */
2170	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2171	/** Pointer to the array of user nodes - R3 pointer. */
2172	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2173	/** Pointer to the array of user nodes - R0 pointer. */
2174	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2175	/** Head of the chain of free phys ext nodes. */
2176	uint16_t iPhysExtFreeHead;
2177	/** The number of user nodes we've allocated. */
2178	uint16_t cMaxPhysExts;
2179	/** Pointer to the array of physical xref extent - RC pointer. */
2180	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2181	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2182	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2183	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2184	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2185	/** Hash table for GCPhys addresses. */
2186	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2187	/** The head of the age list. */
2188	uint16_t iAgeHead;
2189	/** The tail of the age list. */
2190	uint16_t iAgeTail;
2191	/** Set if the cache is enabled. */
2192	bool fCacheEnabled;
2193	/** Alignment padding. */
2194	bool afPadding1[3];
2195	/** Head of the list of modified pages. */
2196	uint16_t iModifiedHead;
2197	/** The current number of modified pages. */
2198	uint16_t cModifiedPages;
2199	/** Access handler, RC. */
2200	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2201	/** Access handler, R0. */
2202	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2203	/** Access handler, R3. */
2204	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2205	/** The access handler description (R3 ptr). */
2206	R3PTRTYPE(const char *) pszAccessHandler;
2207	# if HC_ARCH_BITS == 32
2208	/** Alignment padding. */
2209	uint32_t u32Padding2;
2210	# endif
2211	/* Next available slot. */
2212	uint32_t idxFreeDirtyPage;
2213	/* Number of active dirty pages. */
2214	uint32_t cDirtyPages;
2215	/* Array of current dirty pgm pool page indices. */
2216	struct
2217	{
2218	uint16_t uIdx;
2219	uint16_t Alignment[3];
2220	uint64_t aPage[512];
2221	} aDirtyPages[16];
2222	/** The number of pages currently in use. */
2223	uint16_t cUsedPages;
2224	#ifdef VBOX_WITH_STATISTICS
2225	/** The high water mark for cUsedPages. */
2226	uint16_t cUsedPagesHigh;
2227	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2228	/** Profiling pgmPoolAlloc(). */
2229	STAMPROFILEADV StatAlloc;
2230	/** Profiling pgmR3PoolClearDoIt(). */
2231	STAMPROFILE StatClearAll;
2232	/** Profiling pgmR3PoolReset(). */
2233	STAMPROFILE StatR3Reset;
2234	/** Profiling pgmPoolFlushPage(). */
2235	STAMPROFILE StatFlushPage;
2236	/** Profiling pgmPoolFree(). */
2237	STAMPROFILE StatFree;
2238	/** Counting explicit flushes by PGMPoolFlushPage(). */
2239	STAMCOUNTER StatForceFlushPage;
2240	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2241	STAMCOUNTER StatForceFlushDirtyPage;
2242	/** Counting flushes for reused pages. */
2243	STAMCOUNTER StatForceFlushReused;
2244	/** Profiling time spent zeroing pages. */
2245	STAMPROFILE StatZeroPage;
2246	/** Profiling of pgmPoolTrackDeref. */
2247	STAMPROFILE StatTrackDeref;
2248	/** Profiling pgmTrackFlushGCPhysPT. */
2249	STAMPROFILE StatTrackFlushGCPhysPT;
2250	/** Profiling pgmTrackFlushGCPhysPTs. */
2251	STAMPROFILE StatTrackFlushGCPhysPTs;
2252	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2253	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2254	/** Number of times we've been out of user records. */
2255	STAMCOUNTER StatTrackFreeUpOneUser;
2256	/** Nr of flushed entries. */
2257	STAMCOUNTER StatTrackFlushEntry;
2258	/** Nr of updated entries. */
2259	STAMCOUNTER StatTrackFlushEntryKeep;
2260	/** Profiling deref activity related tracking GC physical pages. */
2261	STAMPROFILE StatTrackDerefGCPhys;
2262	/** Number of linear searches for a HCPhys in the ram ranges. */
2263	STAMCOUNTER StatTrackLinearRamSearches;
2264	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2265	STAMCOUNTER StamTrackPhysExtAllocFailures;
2266	/** Profiling the RC/R0 access handler. */
2267	STAMPROFILE StatMonitorRZ;
2268	/** Times we've failed interpreting the instruction. */
2269	STAMCOUNTER StatMonitorRZEmulateInstr;
2270	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2271	STAMPROFILE StatMonitorRZFlushPage;
2272	/* Times we've detected a page table reinit. */
2273	STAMCOUNTER StatMonitorRZFlushReinit;
2274	/** Counting flushes for pages that are modified too often. */
2275	STAMCOUNTER StatMonitorRZFlushModOverflow;
2276	/** Times we've detected fork(). */
2277	STAMCOUNTER StatMonitorRZFork;
2278	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2279	STAMPROFILE StatMonitorRZHandled;
2280	/** Times we've failed interpreting a patch code instruction. */
2281	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2282	/** Times we've failed interpreting a patch code instruction during flushing. */
2283	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2284	/** The number of times we've seen rep prefixes we can't handle. */
2285	STAMCOUNTER StatMonitorRZRepPrefix;
2286	/** Profiling the REP STOSD cases we've handled. */
2287	STAMPROFILE StatMonitorRZRepStosd;
2288	/** Nr of handled PT faults. */
2289	STAMCOUNTER StatMonitorRZFaultPT;
2290	/** Nr of handled PD faults. */
2291	STAMCOUNTER StatMonitorRZFaultPD;
2292	/** Nr of handled PDPT faults. */
2293	STAMCOUNTER StatMonitorRZFaultPDPT;
2294	/** Nr of handled PML4 faults. */
2295	STAMCOUNTER StatMonitorRZFaultPML4;
2296
2297	/** Profiling the R3 access handler. */
2298	STAMPROFILE StatMonitorR3;
2299	/** Times we've failed interpreting the instruction. */
2300	STAMCOUNTER StatMonitorR3EmulateInstr;
2301	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2302	STAMPROFILE StatMonitorR3FlushPage;
2303	/* Times we've detected a page table reinit. */
2304	STAMCOUNTER StatMonitorR3FlushReinit;
2305	/** Counting flushes for pages that are modified too often. */
2306	STAMCOUNTER StatMonitorR3FlushModOverflow;
2307	/** Times we've detected fork(). */
2308	STAMCOUNTER StatMonitorR3Fork;
2309	/** Profiling the R3 access we've handled (except REP STOSD). */
2310	STAMPROFILE StatMonitorR3Handled;
2311	/** The number of times we've seen rep prefixes we can't handle. */
2312	STAMCOUNTER StatMonitorR3RepPrefix;
2313	/** Profiling the REP STOSD cases we've handled. */
2314	STAMPROFILE StatMonitorR3RepStosd;
2315	/** Nr of handled PT faults. */
2316	STAMCOUNTER StatMonitorR3FaultPT;
2317	/** Nr of handled PD faults. */
2318	STAMCOUNTER StatMonitorR3FaultPD;
2319	/** Nr of handled PDPT faults. */
2320	STAMCOUNTER StatMonitorR3FaultPDPT;
2321	/** Nr of handled PML4 faults. */
2322	STAMCOUNTER StatMonitorR3FaultPML4;
2323	/** The number of times we're called in an async thread an need to flush. */
2324	STAMCOUNTER StatMonitorR3Async;
2325	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2326	STAMCOUNTER StatResetDirtyPages;
2327	/** Times we've called pgmPoolAddDirtyPage. */
2328	STAMCOUNTER StatDirtyPage;
2329	/** Times we've had to flush duplicates for dirty page management. */
2330	STAMCOUNTER StatDirtyPageDupFlush;
2331	/** Times we've had to flush because of overflow. */
2332	STAMCOUNTER StatDirtyPageOverFlowFlush;
2333
2334	/** The high water mark for cModifiedPages. */
2335	uint16_t cModifiedPagesHigh;
2336	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2337
2338	/** The number of cache hits. */
2339	STAMCOUNTER StatCacheHits;
2340	/** The number of cache misses. */
2341	STAMCOUNTER StatCacheMisses;
2342	/** The number of times we've got a conflict of 'kind' in the cache. */
2343	STAMCOUNTER StatCacheKindMismatches;
2344	/** Number of times we've been out of pages. */
2345	STAMCOUNTER StatCacheFreeUpOne;
2346	/** The number of cacheable allocations. */
2347	STAMCOUNTER StatCacheCacheable;
2348	/** The number of uncacheable allocations. */
2349	STAMCOUNTER StatCacheUncacheable;
2350	#else
2351	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2352	#endif
2353	/** The AVL tree for looking up a page by its HC physical address. */
2354	AVLOHCPHYSTREE HCPhysTree;
2355	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2356	/** Array of pages. (cMaxPages in length)
2357	* The Id is the index into thist array.
2358	*/
2359	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2360	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2361	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2362	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2363	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2364	#ifdef VBOX_WITH_STATISTICS
2365	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2366	#endif
2367	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2368
2369
2370	/** @def PGMPOOL_PAGE_2_PTR
2371	* Maps a pool page pool into the current context.
2372	*
2373	* @returns VBox status code.
2374	* @param a_pVM The VM handle.
2375	* @param a_pPage The pool page.
2376	*
2377	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2378	* small page window employeed by that function. Be careful.
2379	* @remark There is no need to assert on the result.
2380	*/
2381	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2382	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2383	#elif defined(VBOX_STRICT)
2384	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage)
2385	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage)
2386	{
2387	Assert(a_pPage && a_pPage->pvPageR3);
2388	return a_pPage->pvPageR3;
2389	}
2390	#else
2391	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2392	#endif
2393
2394
2395	/** @def PGMPOOL_PAGE_2_PTR_V2
2396	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2397	*
2398	* @returns VBox status code.
2399	* @param a_pVM The VM handle.
2400	* @param a_pVCpu The current CPU.
2401	* @param a_pPage The pool page.
2402	*
2403	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2404	* small page window employeed by that function. Be careful.
2405	* @remark There is no need to assert on the result.
2406	*/
2407	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2408	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2409	#else
2410	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2411	#endif
2412
2413
2414	/** @name Per guest page tracking data.
2415	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2416	* is to use more bits for it and split it up later on. But for now we'll play
2417	* safe and change as little as possible.
2418	*
2419	* The 16-bit word has two parts:
2420	*
2421	* The first 14-bit forms the @a idx field. It is either the index of a page in
2422	* the shadow page pool, or and index into the extent list.
2423	*
2424	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2425	* shadow page pool references to the page. If cRefs equals
2426	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2427	* (misnomer) table and not the shadow page pool.
2428	*
2429	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2430	* the 16-bit word.
2431	*
2432	* @{ */
2433	/** The shift count for getting to the cRefs part. */
2434	#define PGMPOOL_TD_CREFS_SHIFT 14
2435	/** The mask applied after shifting the tracking data down by
2436	* PGMPOOL_TD_CREFS_SHIFT. */
2437	#define PGMPOOL_TD_CREFS_MASK 0x3
2438	/** The cRefs value used to indicate that the idx is the head of a
2439	* physical cross reference list. */
2440	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2441	/** The shift used to get idx. */
2442	#define PGMPOOL_TD_IDX_SHIFT 0
2443	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2444	#define PGMPOOL_TD_IDX_MASK 0x3fff
2445	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2446	* simply too many mappings of this page. */
2447	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2448
2449	/** @def PGMPOOL_TD_MAKE
2450	* Makes a 16-bit tracking data word.
2451	*
2452	* @returns tracking data.
2453	* @param cRefs The @a cRefs field. Must be within bounds!
2454	* @param idx The @a idx field. Must also be within bounds! */
2455	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2456
2457	/** @def PGMPOOL_TD_GET_CREFS
2458	* Get the @a cRefs field from a tracking data word.
2459	*
2460	* @returns The @a cRefs field
2461	* @param u16 The tracking data word.
2462	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2463	* non-zero @a u16. */
2464	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2465
2466	/** @def PGMPOOL_TD_GET_IDX
2467	* Get the @a idx field from a tracking data word.
2468	*
2469	* @returns The @a idx field
2470	* @param u16 The tracking data word. */
2471	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2472	/** @} */
2473
2474
2475	/**
2476	* Trees are using self relative offsets as pointers.
2477	* So, all its data, including the root pointer, must be in the heap for HC and GC
2478	* to have the same layout.
2479	*/
2480	typedef struct PGMTREES
2481	{
2482	/** Physical access handlers (AVL range+offsetptr tree). */
2483	AVLROGCPHYSTREE PhysHandlers;
2484	/** Virtual access handlers (AVL range + GC ptr tree). */
2485	AVLROGCPTRTREE VirtHandlers;
2486	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2487	AVLROGCPHYSTREE PhysToVirtHandlers;
2488	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2489	AVLROGCPTRTREE HyperVirtHandlers;
2490	} PGMTREES;
2491	/** Pointer to PGM trees. */
2492	typedef PGMTREES *PPGMTREES;
2493
2494
2495	/**
2496	* Page fault guest state for the AMD64 paging mode.
2497	*/
2498	typedef struct PGMPTWALKCORE
2499	{
2500	/** The guest virtual address that is being resolved by the walk
2501	* (input). */
2502	RTGCPTR GCPtr;
2503
2504	/** The guest physical address that is the result of the walk.
2505	* @remarks only valid if fSucceeded is set. */
2506	RTGCPHYS GCPhys;
2507
2508	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2509	bool fSucceeded;
2510	/** The level problem arrised at.
2511	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2512	* level 8. This is 0 on success. */
2513	uint8_t uLevel;
2514	/** Set if the page isn't present. */
2515	bool fNotPresent;
2516	/** Encountered a bad physical address. */
2517	bool fBadPhysAddr;
2518	/** Set if there was reserved bit violations. */
2519	bool fRsvdError;
2520	/** Set if it involves a big page (2/4 MB). */
2521	bool fBigPage;
2522	/** Set if it involves a gigantic page (1 GB). */
2523	bool fGigantPage;
2524	/** The effect X86_PTE_US flag for the address. */
2525	bool fEffectiveUS;
2526	/** The effect X86_PTE_RW flag for the address. */
2527	bool fEffectiveRW;
2528	/** The effect X86_PTE_NX flag for the address. */
2529	bool fEffectiveNX;
2530	} PGMPTWALKCORE;
2531
2532
2533	/**
2534	* Guest page table walk for the AMD64 mode.
2535	*/
2536	typedef struct PGMPTWALKGSTAMD64
2537	{
2538	/** The common core. */
2539	PGMPTWALKCORE Core;
2540
2541	PX86PML4 pPml4;
2542	PX86PML4E pPml4e;
2543	X86PML4E Pml4e;
2544
2545	PX86PDPT pPdpt;
2546	PX86PDPE pPdpe;
2547	X86PDPE Pdpe;
2548
2549	PX86PDPAE pPd;
2550	PX86PDEPAE pPde;
2551	X86PDEPAE Pde;
2552
2553	PX86PTPAE pPt;
2554	PX86PTEPAE pPte;
2555	X86PTEPAE Pte;
2556	} PGMPTWALKGSTAMD64;
2557	/** Pointer to a AMD64 guest page table walk. */
2558	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2559	/** Pointer to a const AMD64 guest page table walk. */
2560	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2561
2562	/**
2563	* Guest page table walk for the PAE mode.
2564	*/
2565	typedef struct PGMPTWALKGSTPAE
2566	{
2567	/** The common core. */
2568	PGMPTWALKCORE Core;
2569
2570	PX86PDPT pPdpt;
2571	PX86PDPE pPdpe;
2572	X86PDPE Pdpe;
2573
2574	PX86PDPAE pPd;
2575	PX86PDEPAE pPde;
2576	X86PDEPAE Pde;
2577
2578	PX86PTPAE pPt;
2579	PX86PTEPAE pPte;
2580	X86PTEPAE Pte;
2581	} PGMPTWALKGSTPAE;
2582	/** Pointer to a PAE guest page table walk. */
2583	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2584	/** Pointer to a const AMD64 guest page table walk. */
2585	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2586
2587	/**
2588	* Guest page table walk for the 32-bit mode.
2589	*/
2590	typedef struct PGMPTWALKGST32BIT
2591	{
2592	/** The common core. */
2593	PGMPTWALKCORE Core;
2594
2595	PX86PD pPd;
2596	PX86PDE pPde;
2597	X86PDE Pde;
2598
2599	PX86PT pPt;
2600	PX86PTE pPte;
2601	X86PTE Pte;
2602	} PGMPTWALKGST32BIT;
2603	/** Pointer to a 32-bit guest page table walk. */
2604	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2605	/** Pointer to a const 32-bit guest page table walk. */
2606	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2607
2608
2609	/** @name Paging mode macros
2610	* @{
2611	*/
2612	#ifdef IN_RC
2613	# define PGM_CTX(a,b) a##RC##b
2614	# define PGM_CTX_STR(a,b) a "GC" b
2615	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2616	#else
2617	# ifdef IN_RING3
2618	# define PGM_CTX(a,b) a##R3##b
2619	# define PGM_CTX_STR(a,b) a "R3" b
2620	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2621	# else
2622	# define PGM_CTX(a,b) a##R0##b
2623	# define PGM_CTX_STR(a,b) a "R0" b
2624	# define PGM_CTX_DECL(type) VMMDECL(type)
2625	# endif
2626	#endif
2627
2628	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2629	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2630	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2631	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2632	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2633	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2634	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2635	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2636	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2637	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2638	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2639	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2640	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2641	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2642	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2643	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2644	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2645
2646	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2647	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2648	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2649	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2650	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2651	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2652	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2653	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2654	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2655	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2656	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2657	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2658	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2659	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2660	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2661	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2662	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2663
2664	/* Shw_Gst */
2665	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2666	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2667	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2668	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2669	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2670	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2671	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2672	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2673	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2674	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2675	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2676	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2677	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2678	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2679	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2680	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2681	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2682	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2683	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2684
2685	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2686	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2687	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2688	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2689	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2690	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2691	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2692	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2693	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2694	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2695	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2696	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2697	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2698	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2699	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2700	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2701	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2702	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2703	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2704	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2705	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2706	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2707	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2708	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2709	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2710	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2711	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2712	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2713	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2714	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2715	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2716	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2717	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2718	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2719	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2720	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2721	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2722
2723	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2724	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2725	/** @} */
2726
2727	/**
2728	* Data for each paging mode.
2729	*/
2730	typedef struct PGMMODEDATA
2731	{
2732	/** The guest mode type. */
2733	uint32_t uGstType;
2734	/** The shadow mode type. */
2735	uint32_t uShwType;
2736
2737	/** @name Function pointers for Shadow paging.
2738	* @{
2739	*/
2740	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2741	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2742	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2743	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2744
2745	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2746	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2747
2748	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2749	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2750	/** @} */
2751
2752	/** @name Function pointers for Guest paging.
2753	* @{
2754	*/
2755	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2756	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2757	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2758	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2759	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2760	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2761	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2762	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2763	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2764	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2765	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2766	/** @} */
2767
2768	/** @name Function pointers for Both Shadow and Guest paging.
2769	* @{
2770	*/
2771	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2772	/* no pfnR3BthTrap0eHandler */
2773	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2774	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2775	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2776	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2777	#ifdef VBOX_STRICT
2778	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2779	#endif
2780	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2781	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2782
2783	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2784	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2785	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2786	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2787	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2788	#ifdef VBOX_STRICT
2789	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2790	#endif
2791	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2792	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2793
2794	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2795	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2796	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2797	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2798	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2799	#ifdef VBOX_STRICT
2800	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2801	#endif
2802	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2803	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2804	/** @} */
2805	} PGMMODEDATA, *PPGMMODEDATA;
2806
2807
2808	#ifdef VBOX_WITH_STATISTICS
2809	/**
2810	* PGM statistics.
2811	*
2812	* These lives on the heap when compiled in as they would otherwise waste
2813	* unnecessary space in release builds.
2814	*/
2815	typedef struct PGMSTATS
2816	{
2817	/* R3 only: */
2818	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2819	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2820
2821	/* R3+RZ */
2822	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2823	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2824	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2825	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2826	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2827	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2828	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2829	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2830	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2831	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2832	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2833	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2834	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2835	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2836	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2837	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2838	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2839	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2840	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2841	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2842	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2843	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2844	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2845	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2846	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2847	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2848	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2849	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2850	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2851	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2852	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2853	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2854
2855	/* RC only: */
2856	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2857	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2858
2859	STAMCOUNTER StatRZPhysRead;
2860	STAMCOUNTER StatRZPhysReadBytes;
2861	STAMCOUNTER StatRZPhysWrite;
2862	STAMCOUNTER StatRZPhysWriteBytes;
2863	STAMCOUNTER StatR3PhysRead;
2864	STAMCOUNTER StatR3PhysReadBytes;
2865	STAMCOUNTER StatR3PhysWrite;
2866	STAMCOUNTER StatR3PhysWriteBytes;
2867	STAMCOUNTER StatRCPhysRead;
2868	STAMCOUNTER StatRCPhysReadBytes;
2869	STAMCOUNTER StatRCPhysWrite;
2870	STAMCOUNTER StatRCPhysWriteBytes;
2871
2872	STAMCOUNTER StatRZPhysSimpleRead;
2873	STAMCOUNTER StatRZPhysSimpleReadBytes;
2874	STAMCOUNTER StatRZPhysSimpleWrite;
2875	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2876	STAMCOUNTER StatR3PhysSimpleRead;
2877	STAMCOUNTER StatR3PhysSimpleReadBytes;
2878	STAMCOUNTER StatR3PhysSimpleWrite;
2879	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2880	STAMCOUNTER StatRCPhysSimpleRead;
2881	STAMCOUNTER StatRCPhysSimpleReadBytes;
2882	STAMCOUNTER StatRCPhysSimpleWrite;
2883	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2884
2885	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2886	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2887	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2888	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2889	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2890	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2891	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2892
2893	/** Time spent by the host OS for large page allocation. */
2894	STAMPROFILE StatAllocLargePage;
2895	/** Time spent clearing the newly allocated large pages. */
2896	STAMPROFILE StatClearLargePage;
2897	/** The number of times allocating a large pages takes more than the allowed period. */
2898	STAMCOUNTER StatLargePageOverflow;
2899	/** pgmPhysIsValidLargePage profiling - R3 */
2900	STAMPROFILE StatR3IsValidLargePage;
2901	/** pgmPhysIsValidLargePage profiling - RZ*/
2902	STAMPROFILE StatRZIsValidLargePage;
2903
2904	STAMPROFILE StatChunkAging;
2905	STAMPROFILE StatChunkFindCandidate;
2906	STAMPROFILE StatChunkUnmap;
2907	STAMPROFILE StatChunkMap;
2908	} PGMSTATS;
2909	#endif /* VBOX_WITH_STATISTICS */
2910
2911
2912	/**
2913	* Converts a PGM pointer into a VM pointer.
2914	* @returns Pointer to the VM structure the PGM is part of.
2915	* @param pPGM Pointer to PGM instance data.
2916	*/
2917	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2918
2919	/**
2920	* PGM Data (part of VM)
2921	*/
2922	typedef struct PGM
2923	{
2924	/** Offset to the VM structure. */
2925	int32_t offVM;
2926	/** Offset of the PGMCPU structure relative to VMCPU. */
2927	int32_t offVCpuPGM;
2928
2929	/** @cfgm{RamPreAlloc, boolean, false}
2930	* Indicates whether the base RAM should all be allocated before starting
2931	* the VM (default), or if it should be allocated when first written to.
2932	*/
2933	bool fRamPreAlloc;
2934	/** Indicates whether write monitoring is currently in use.
2935	* This is used to prevent conflicts between live saving and page sharing
2936	* detection. */
2937	bool fPhysWriteMonitoringEngaged;
2938	/** Set if the CPU has less than 52-bit physical address width.
2939	* This is used */
2940	bool fLessThan52PhysicalAddressBits;
2941	/** Set when nested paging is active.
2942	* This is meant to save calls to HWACCMIsNestedPagingActive and let the
2943	* compilers optimize the code better. Whether we use nested paging or
2944	* not is something we find out during VMM initialization and we won't
2945	* change this later on. */
2946	bool fNestedPaging;
2947	/** The host paging mode. (This is what SUPLib reports.) */
2948	SUPPAGINGMODE enmHostMode;
2949	/** We're not in a state which permits writes to guest memory.
2950	* (Only used in strict builds.) */
2951	bool fNoMorePhysWrites;
2952	/** Set if PCI passthrough is enabled. */
2953	bool fPciPassthrough;
2954	/** Alignment padding that makes the next member start on a 8 byte boundary. */
2955	bool afAlignment1[2];
2956
2957	/** Indicates that PGMR3FinalizeMappings has been called and that further
2958	* PGMR3MapIntermediate calls will be rejected. */
2959	bool fFinalizedMappings;
2960	/** If set no conflict checks are required. */
2961	bool fMappingsFixed;
2962	/** If set if restored as fixed but we were unable to re-fixate at the old
2963	* location because of room or address incompatibilities. */
2964	bool fMappingsFixedRestored;
2965	/** If set, then no mappings are put into the shadow page table.
2966	* Use pgmMapAreMappingsEnabled() instead of direct access. */
2967	bool fMappingsDisabled;
2968	/** Size of fixed mapping.
2969	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2970	uint32_t cbMappingFixed;
2971	/** Generation ID for the RAM ranges. This member is incremented everytime
2972	* a RAM range is linked or unlinked. */
2973	uint32_t volatile idRamRangesGen;
2974
2975	/** Base address (GC) of fixed mapping.
2976	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2977	RTGCPTR GCPtrMappingFixed;
2978	/** The address of the previous RAM range mapping. */
2979	RTGCPTR GCPtrPrevRamRangeMapping;
2980
2981	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2982	RTGCPHYS GCPhys4MBPSEMask;
2983	/** Mask containing the invalid bits of a guest physical address.
2984	* @remarks this does not stop at bit 52. */
2985	RTGCPHYS GCPhysInvAddrMask;
2986
2987
2988	/** RAM range TLB for R3. */
2989	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2990	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2991	* This is sorted by physical address and contains no overlapping ranges. */
2992	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2993	/** Root of the RAM range search tree for ring-3. */
2994	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2995	/** PGM offset based trees - R3 Ptr. */
2996	R3PTRTYPE(PPGMTREES) pTreesR3;
2997	/** Caching the last physical handler we looked up in R3. */
2998	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2999	/** Shadow Page Pool - R3 Ptr. */
3000	R3PTRTYPE(PPGMPOOL) pPoolR3;
3001	/** Linked list of GC mappings - for HC.
3002	* The list is sorted ascending on address. */
3003	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3004	/** Pointer to the list of ROM ranges - for R3.
3005	* This is sorted by physical address and contains no overlapping ranges. */
3006	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3007	/** Pointer to the list of MMIO2 ranges - for R3.
3008	* Registration order. */
3009	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3010	/** Pointer to SHW+GST mode data (function pointers).
3011	* The index into this table is made up from */
3012	R3PTRTYPE(PPGMMODEDATA) paModeData;
3013	RTR3PTR R3PtrAlignment0;
3014
3015	/** RAM range TLB for R0. */
3016	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3017	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3018	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3019	/** Root of the RAM range search tree for ring-0. */
3020	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3021	/** PGM offset based trees - R0 Ptr. */
3022	R0PTRTYPE(PPGMTREES) pTreesR0;
3023	/** Caching the last physical handler we looked up in R0. */
3024	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3025	/** Shadow Page Pool - R0 Ptr. */
3026	R0PTRTYPE(PPGMPOOL) pPoolR0;
3027	/** Linked list of GC mappings - for R0.
3028	* The list is sorted ascending on address. */
3029	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3030	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3031	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3032	RTR0PTR R0PtrAlignment0;
3033
3034
3035	/** RAM range TLB for RC. */
3036	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3037	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3038	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3039	/** Root of the RAM range search tree for raw-mode context. */
3040	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3041	/** PGM offset based trees - RC Ptr. */
3042	RCPTRTYPE(PPGMTREES) pTreesRC;
3043	/** Caching the last physical handler we looked up in RC. */
3044	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3045	/** Shadow Page Pool - RC Ptr. */
3046	RCPTRTYPE(PPGMPOOL) pPoolRC;
3047	/** Linked list of GC mappings - for RC.
3048	* The list is sorted ascending on address. */
3049	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3050	/** RC pointer corresponding to PGM::pRomRangesR3. */
3051	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3052	RTRCPTR RCPtrAlignment0;
3053	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3054	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3055	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3056	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3057
3058
3059	/** Pointer to the 5 page CR3 content mapping.
3060	* The first page is always the CR3 (in some form) while the 4 other pages
3061	* are used of the PDs in PAE mode. */
3062	RTGCPTR GCPtrCR3Mapping;
3063
3064	/** @name Intermediate Context
3065	* @{ */
3066	/** Pointer to the intermediate page directory - Normal. */
3067	R3PTRTYPE(PX86PD) pInterPD;
3068	/** Pointer to the intermediate page tables - Normal.
3069	* There are two page tables, one for the identity mapping and one for
3070	* the host context mapping (of the core code). */
3071	R3PTRTYPE(PX86PT) apInterPTs[2];
3072	/** Pointer to the intermediate page tables - PAE. */
3073	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3074	/** Pointer to the intermediate page directory - PAE. */
3075	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3076	/** Pointer to the intermediate page directory - PAE. */
3077	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3078	/** Pointer to the intermediate page-map level 4 - AMD64. */
3079	R3PTRTYPE(PX86PML4) pInterPaePML4;
3080	/** Pointer to the intermediate page directory - AMD64. */
3081	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3082	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3083	RTHCPHYS HCPhysInterPD;
3084	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3085	RTHCPHYS HCPhysInterPaePDPT;
3086	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3087	RTHCPHYS HCPhysInterPaePML4;
3088	/** @} */
3089
3090	/** Base address of the dynamic page mapping area.
3091	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3092	*
3093	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3094	* work out. Some cleaning up of the initialization that would
3095	* remove this memory is yet to be done...
3096	*/
3097	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3098	/** The address of the raw-mode context mapping cache. */
3099	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3100	/** The address of the ring-0 mapping cache if we're making use of it. */
3101	RTR0PTR pvR0DynMapUsed;
3102	#if HC_ARCH_BITS == 32
3103	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3104	uint32_t u32Alignment2;
3105	#endif
3106
3107	/** PGM critical section.
3108	* This protects the physical & virtual access handlers, ram ranges,
3109	* and the page flag updating (some of it anyway).
3110	*/
3111	PDMCRITSECT CritSect;
3112
3113	/**
3114	* Data associated with managing the ring-3 mappings of the allocation chunks.
3115	*/
3116	struct
3117	{
3118	/** The chunk tree, ordered by chunk id. */
3119	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3120	R3PTRTYPE(PAVLU32NODECORE) pTree;
3121	#else
3122	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3123	#endif
3124	#if HC_ARCH_BITS == 32
3125	uint32_t u32Alignment;
3126	#endif
3127	/** The chunk mapping TLB. */
3128	PGMCHUNKR3MAPTLB Tlb;
3129	/** The number of mapped chunks. */
3130	uint32_t c;
3131	/** The maximum number of mapped chunks.
3132	* @cfgm PGM/MaxRing3Chunks */
3133	uint32_t cMax;
3134	/** The current time. */
3135	uint32_t iNow;
3136	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3137	uint32_t AgeingCountdown;
3138	} ChunkR3Map;
3139
3140	/**
3141	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3142	*/
3143	PGMPAGER3MAPTLB PhysTlbHC;
3144
3145	/** @name The zero page.
3146	* @{ */
3147	/** The host physical address of the zero page. */
3148	RTHCPHYS HCPhysZeroPg;
3149	/** The ring-3 mapping of the zero page. */
3150	RTR3PTR pvZeroPgR3;
3151	/** The ring-0 mapping of the zero page. */
3152	RTR0PTR pvZeroPgR0;
3153	/** The GC mapping of the zero page. */
3154	RTRCPTR pvZeroPgRC;
3155	RTRCPTR RCPtrAlignment3;
3156	/** @}*/
3157
3158	/** @name The Invalid MMIO page.
3159	* This page is filled with 0xfeedface.
3160	* @{ */
3161	/** The host physical address of the invalid MMIO page. */
3162	RTHCPHYS HCPhysMmioPg;
3163	/** The host pysical address of the invalid MMIO page plus all invalid
3164	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3165	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3166	RTHCPHYS HCPhysInvMmioPg;
3167	/** The ring-3 mapping of the invalid MMIO page. */
3168	RTR3PTR pvMmioPgR3;
3169	#if HC_ARCH_BITS == 32
3170	RTR3PTR R3PtrAlignment4;
3171	#endif
3172	/** @} */
3173
3174
3175	/** The number of handy pages. */
3176	uint32_t cHandyPages;
3177
3178	/** The number of large handy pages. */
3179	uint32_t cLargeHandyPages;
3180
3181	/**
3182	* Array of handy pages.
3183	*
3184	* This array is used in a two way communication between pgmPhysAllocPage
3185	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3186	* an intermediary.
3187	*
3188	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3189	* (The current size of 32 pages, means 128 KB of handy memory.)
3190	*/
3191	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3192
3193	/**
3194	* Array of large handy pages. (currently size 1)
3195	*
3196	* This array is used in a two way communication between pgmPhysAllocLargePage
3197	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3198	* an intermediary.
3199	*/
3200	GMMPAGEDESC aLargeHandyPage[1];
3201
3202	/**
3203	* Live save data.
3204	*/
3205	struct
3206	{
3207	/** Per type statistics. */
3208	struct
3209	{
3210	/** The number of ready pages. */
3211	uint32_t cReadyPages;
3212	/** The number of dirty pages. */
3213	uint32_t cDirtyPages;
3214	/** The number of ready zero pages. */
3215	uint32_t cZeroPages;
3216	/** The number of write monitored pages. */
3217	uint32_t cMonitoredPages;
3218	} Rom,
3219	Mmio2,
3220	Ram;
3221	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3222	uint32_t cIgnoredPages;
3223	/** Indicates that a live save operation is active. */
3224	bool fActive;
3225	/** Padding. */
3226	bool afReserved[2];
3227	/** The next history index. */
3228	uint8_t iDirtyPagesHistory;
3229	/** History of the total amount of dirty pages. */
3230	uint32_t acDirtyPagesHistory[64];
3231	/** Short term dirty page average. */
3232	uint32_t cDirtyPagesShort;
3233	/** Long term dirty page average. */
3234	uint32_t cDirtyPagesLong;
3235	/** The number of saved pages. This is used to get some kind of estimate of the
3236	* link speed so we can decide when we're done. It is reset after the first
3237	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3238	* zero pages. */
3239	uint64_t cSavedPages;
3240	/** The nanosecond timestamp when cSavedPages was 0. */
3241	uint64_t uSaveStartNS;
3242	/** Pages per second (for statistics). */
3243	uint32_t cPagesPerSecond;
3244	uint32_t cAlignment;
3245	} LiveSave;
3246
3247	/** @name Error injection.
3248	* @{ */
3249	/** Inject handy page allocation errors pretending we're completely out of
3250	* memory. */
3251	bool volatile fErrInjHandyPages;
3252	/** Padding. */
3253	bool afReserved[3];
3254	/** @} */
3255
3256	/** @name Release Statistics
3257	* @{ */
3258	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3259	uint32_t cPrivatePages; /*< The number of private pages. /
3260	uint32_t cSharedPages; /*< The number of shared pages. /
3261	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3262	uint32_t cZeroPages; /*< The number of zero backed pages. /
3263	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3264	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3265	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3266	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3267	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3268	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3269	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3270	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3271	uint32_t cLargePages; /*< The number of large pages. /
3272	uint32_t cLargePagesDisabled;/*< The number of disabled large pages. /
3273	/* uint32_t aAlignment4[1]; */
3274
3275	/** The number of times we were forced to change the hypervisor region location. */
3276	STAMCOUNTER cRelocations;
3277
3278	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3279	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3280	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3281	/** @} */
3282
3283	#ifdef VBOX_WITH_STATISTICS
3284	/** @name Statistics on the heap.
3285	* @{ */
3286	R3PTRTYPE(PGMSTATS *) pStatsR3;
3287	R0PTRTYPE(PGMSTATS *) pStatsR0;
3288	RCPTRTYPE(PGMSTATS *) pStatsRC;
3289	RTRCPTR RCPtrAlignment;
3290	/** @} */
3291	#endif
3292	} PGM;
3293	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3294	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3295	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3296	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3297	AssertCompileMemberAlignment(PGM, CritSect, 8);
3298	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3299	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3300	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3301	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3302	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3303	#endif /* !IN_TSTVMSTRUCTGC */
3304	/** Pointer to the PGM instance data. */
3305	typedef PGM *PPGM;
3306
3307
3308
3309	typedef struct PGMCPUSTATS
3310	{
3311	/* Common */
3312	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3313	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3314
3315	/* R0 only: */
3316	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3317	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3318
3319	/* RZ only: */
3320	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3321	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3322	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3323	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3324	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3325	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3326	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3327	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3328	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3329	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3330	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3331	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3332	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3333	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3334	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3335	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3336	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3337	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3338	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3339	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3340	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3341	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3342	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3343	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3344	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3345	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3346	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3347	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3348	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3349	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3350	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3351	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3352	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3353	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3354	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3355	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3356	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3357	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3358	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3359	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3360	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3361	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3362	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3363	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3364	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3365	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3366	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3367	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3368	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3369	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3370	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3371	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3372	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3373	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3374	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3375	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3376	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3377	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3378	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3379	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3380	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3381	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3382	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3383	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3384	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3385	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3386	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3387	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3388	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3389	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3390	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3391	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3392	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3393	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3394	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3395	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3396
3397	/* HC - R3 and (maybe) R0: */
3398
3399	/* RZ & R3: */
3400	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3401	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3402	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3403	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3404	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3405	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3406	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3407	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3408	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3409	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3410	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3411	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3412	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3413	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3414	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3415	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3416	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3417	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3418	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3419	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3420	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3421	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3422	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3423	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3424	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3425	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3426	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3427	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3428	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3429	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3430	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3431	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3432	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3433	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3434	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3435	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3436	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3437	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3438	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3439	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3440	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3441	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3442	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3443	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3444	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3445	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3446	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3447
3448	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3449	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3450	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3451	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3452	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3453	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3454	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3455	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3456	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3457	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3458	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3459	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3460	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3461	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3462	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3463	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3464	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3465	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3466	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3467	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3468	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3469	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3470	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3471	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3472	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3473	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3474	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3475	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3476	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3477	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3478	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3479	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3480	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3481	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3482	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3483	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3484	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3485	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3486	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3487	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3488	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3489	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3490	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3491	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3492	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3493	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3494	/** @} */
3495	} PGMCPUSTATS;
3496
3497
3498	/**
3499	* Converts a PGMCPU pointer into a VM pointer.
3500	* @returns Pointer to the VM structure the PGM is part of.
3501	* @param pPGM Pointer to PGMCPU instance data.
3502	*/
3503	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3504
3505	/**
3506	* Converts a PGMCPU pointer into a PGM pointer.
3507	* @returns Pointer to the VM structure the PGM is part of.
3508	* @param pPGM Pointer to PGMCPU instance data.
3509	*/
3510	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3511
3512	/**
3513	* PGMCPU Data (part of VMCPU).
3514	*/
3515	typedef struct PGMCPU
3516	{
3517	/** Offset to the VM structure. */
3518	int32_t offVM;
3519	/** Offset to the VMCPU structure. */
3520	int32_t offVCpu;
3521	/** Offset of the PGM structure relative to VMCPU. */
3522	int32_t offPGM;
3523	uint32_t uPadding0; /*< structure size alignment. /
3524
3525	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3526	/** Automatically tracked physical memory mapping set.
3527	* Ring-0 and strict raw-mode builds. */
3528	PGMMAPSET AutoSet;
3529	#endif
3530
3531	/** A20 gate mask.
3532	* Our current approach to A20 emulation is to let REM do it and don't bother
3533	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3534	* But whould need arrise, we'll subject physical addresses to this mask. */
3535	RTGCPHYS GCPhysA20Mask;
3536	/** A20 gate state - boolean! */
3537	bool fA20Enabled;
3538	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3539	bool fNoExecuteEnabled;
3540	/** Unused bits. */
3541	bool afUnused[2];
3542
3543	/** What needs syncing (PGM_SYNC_*).
3544	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3545	* PGMFlushTLB, and PGMR3Load. */
3546	RTUINT fSyncFlags;
3547
3548	/** The shadow paging mode. */
3549	PGMMODE enmShadowMode;
3550	/** The guest paging mode. */
3551	PGMMODE enmGuestMode;
3552
3553	/** The current physical address representing in the guest CR3 register. */
3554	RTGCPHYS GCPhysCR3;
3555
3556	/** @name 32-bit Guest Paging.
3557	* @{ */
3558	/** The guest's page directory, R3 pointer. */
3559	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3560	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3561	/** The guest's page directory, R0 pointer. */
3562	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3563	#endif
3564	/** The guest's page directory, static RC mapping. */
3565	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3566	/** Mask containing the MBZ bits of a big page PDE. */
3567	uint32_t fGst32BitMbzBigPdeMask;
3568	/** Set if the page size extension (PSE) is enabled. */
3569	bool fGst32BitPageSizeExtension;
3570	/** Alignment padding. */
3571	bool afAlignment2[3];
3572	/** @} */
3573
3574	/** @name PAE Guest Paging.
3575	* @{ */
3576	/** The guest's page directory pointer table, static RC mapping. */
3577	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3578	/** The guest's page directory pointer table, R3 pointer. */
3579	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3580	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3581	/** The guest's page directory pointer table, R0 pointer. */
3582	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3583	#endif
3584
3585	/** The guest's page directories, R3 pointers.
3586	* These are individual pointers and don't have to be adjacent.
3587	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3588	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3589	/** The guest's page directories, R0 pointers.
3590	* Same restrictions as apGstPaePDsR3. */
3591	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3592	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3593	#endif
3594	/** The guest's page directories, static GC mapping.
3595	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3596	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3597	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3598	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3599	RTGCPHYS aGCPhysGstPaePDs[4];
3600	/** The physical addresses of the monitored guest page directories (PAE). */
3601	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3602	/** Mask containing the MBZ PTE bits. */
3603	uint64_t fGstPaeMbzPteMask;
3604	/** Mask containing the MBZ PDE bits. */
3605	uint64_t fGstPaeMbzPdeMask;
3606	/** Mask containing the MBZ big page PDE bits. */
3607	uint64_t fGstPaeMbzBigPdeMask;
3608	/** Mask containing the MBZ PDPE bits. */
3609	uint64_t fGstPaeMbzPdpeMask;
3610	/** @} */
3611
3612	/** @name AMD64 Guest Paging.
3613	* @{ */
3614	/** The guest's page directory pointer table, R3 pointer. */
3615	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3616	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3617	/** The guest's page directory pointer table, R0 pointer. */
3618	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3619	#else
3620	RTR0PTR alignment6b; /*< alignment equalizer. /
3621	#endif
3622	/** Mask containing the MBZ PTE bits. */
3623	uint64_t fGstAmd64MbzPteMask;
3624	/** Mask containing the MBZ PDE bits. */
3625	uint64_t fGstAmd64MbzPdeMask;
3626	/** Mask containing the MBZ big page PDE bits. */
3627	uint64_t fGstAmd64MbzBigPdeMask;
3628	/** Mask containing the MBZ PDPE bits. */
3629	uint64_t fGstAmd64MbzPdpeMask;
3630	/** Mask containing the MBZ big page PDPE bits. */
3631	uint64_t fGstAmd64MbzBigPdpeMask;
3632	/** Mask containing the MBZ PML4E bits. */
3633	uint64_t fGstAmd64MbzPml4eMask;
3634	/** Mask containing the PDPE bits that we shadow. */
3635	uint64_t fGstAmd64ShadowedPdpeMask;
3636	/** Mask containing the PML4E bits that we shadow. */
3637	uint64_t fGstAmd64ShadowedPml4eMask;
3638	/** @} */
3639
3640	/** @name PAE and AMD64 Guest Paging.
3641	* @{ */
3642	/** Mask containing the PTE bits that we shadow. */
3643	uint64_t fGst64ShadowedPteMask;
3644	/** Mask containing the PDE bits that we shadow. */
3645	uint64_t fGst64ShadowedPdeMask;
3646	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3647	uint64_t fGst64ShadowedBigPdeMask;
3648	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3649	uint64_t fGst64ShadowedBigPde4PteMask;
3650	/** @} */
3651
3652	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3653	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3654	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3655	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3656	/** Pointer to the page of the current active CR3 - RC Ptr. */
3657	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3658	/* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3659	uint32_t iShwUser;
3660	/* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3661	uint32_t iShwUserTable;
3662	# if HC_ARCH_BITS == 64
3663	RTRCPTR alignment6; /*< structure size alignment. /
3664	# endif
3665	/** @} */
3666
3667	/** @name Function pointers for Shadow paging.
3668	* @{
3669	*/
3670	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3671	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3672	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3673	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3674
3675	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3676	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3677
3678	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3679	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3680
3681	/** @} */
3682
3683	/** @name Function pointers for Guest paging.
3684	* @{
3685	*/
3686	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3687	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3688	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3689	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3690	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3691	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3692	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3693	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3694	#if HC_ARCH_BITS == 64
3695	RTRCPTR alignment3; /*< structure size alignment. /
3696	#endif
3697
3698	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3699	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3700	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3701	/** @} */
3702
3703	/** @name Function pointers for Both Shadow and Guest paging.
3704	* @{
3705	*/
3706	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3707	/* no pfnR3BthTrap0eHandler */
3708	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3709	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3710	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3711	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3712	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3713	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3714	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3715
3716	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3717	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3718	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3719	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3720	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3721	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3722	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3723	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3724
3725	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3726	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3727	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3728	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3729	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3730	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3731	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3732	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3733	#if 0
3734	RTRCPTR alignment2; /*< structure size alignment. /
3735	#endif
3736	/** @} */
3737
3738	/** For saving stack space, the disassembler state is allocated here instead of
3739	* on the stack.
3740	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3741	union
3742	{
3743	/** The disassembler scratch space. */
3744	DISCPUSTATE DisState;
3745	/** Padding. */
3746	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3747	};
3748
3749	/** Count the number of pgm pool access handler calls. */
3750	uint64_t cPoolAccessHandler;
3751
3752	/** @name Release Statistics
3753	* @{ */
3754	/** The number of times the guest has switched mode since last reset or statistics reset. */
3755	STAMCOUNTER cGuestModeChanges;
3756	/** @} */
3757
3758	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3759	/** @name Statistics
3760	* @{ */
3761	/** RC: Pointer to the statistics. */
3762	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3763	/** RC: Which statistic this \#PF should be attributed to. */
3764	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3765	/** R0: Pointer to the statistics. */
3766	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3767	/** R0: Which statistic this \#PF should be attributed to. */
3768	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3769	/** R3: Pointer to the statistics. */
3770	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3771	/** Alignment padding. */
3772	RTR3PTR pPaddingR3;
3773	/** @} */
3774	#endif /* VBOX_WITH_STATISTICS */
3775	} PGMCPU;
3776	/** Pointer to the per-cpu PGM data. */
3777	typedef PGMCPU *PPGMCPU;
3778
3779
3780	/** @name PGM::fSyncFlags Flags
3781	* @{
3782	*/
3783	/** Updates the virtual access handler state bit in PGMPAGE. */
3784	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3785	/** Always sync CR3. */
3786	#define PGM_SYNC_ALWAYS RT_BIT(1)
3787	/** Check monitoring on next CR3 (re)load and invalidate page.
3788	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3789	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3790	/** Check guest mapping in SyncCR3. */
3791	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3792	/** Clear the page pool (a light weight flush). */
3793	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3794	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3795	/** @} */
3796
3797
3798	RT_C_DECLS_BEGIN
3799
3800	int pgmLock(PVM pVM);
3801	void pgmUnlock(PVM pVM);
3802
3803	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3804	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3805	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3806	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3807	int pgmMapResolveConflicts(PVM pVM);
3808	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3809
3810	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3811	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3812	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3813	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
3814	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3815	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3816	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3817	#else
3818	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3819	#endif
3820	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3821	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3822
3823	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3824	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3825	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3826	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
3827	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3828	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3829	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3830	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3831	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3832	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3833	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3834	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3835	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3836	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3837	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3838	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3839	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
3840	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3841	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3842	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3843	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3844	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3845
3846	#ifdef IN_RING3
3847	void pgmR3PhysRelinkRamRanges(PVM pVM);
3848	int pgmR3PhysRamPreAllocate(PVM pVM);
3849	int pgmR3PhysRamReset(PVM pVM);
3850	int pgmR3PhysRomReset(PVM pVM);
3851	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3852	int pgmR3PhysRamTerm(PVM pVM);
3853	void pgmR3PhysRomTerm(PVM pVM);
3854
3855	int pgmR3PoolInit(PVM pVM);
3856	void pgmR3PoolRelocate(PVM pVM);
3857	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3858	void pgmR3PoolReset(PVM pVM);
3859	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3860	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3861	void pgmR3PoolWriteProtectPages(PVM pVM);
3862
3863	#endif /* IN_RING3 */
3864	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
3865	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3866	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3867	# ifdef LOG_ENABLED
3868	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3869	# else
3870	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3871	# endif
3872	#endif
3873	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3874	uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3875
3876	DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3877	PPPGMPOOLPAGE ppPage)
3878	{
3879	return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3880	}
3881
3882	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3883	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3884	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3885	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3886	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3887	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3888	int pgmPoolSyncCR3(PVMCPU pVCpu);
3889	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3890	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3891	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3892	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3893	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3894	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3895	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3896	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3897	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3898
3899	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3900	void pgmPoolResetDirtyPages(PVM pVM);
3901	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3902
3903	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3904	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3905
3906	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3907	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3908	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3909	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3910
3911	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3912	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3913
3914	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3915	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3916	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3917	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3918
3919	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3920	DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3921	DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3922	# endif
3923
3924	RT_C_DECLS_END
3925
3926	/** @} */
3927
3928	#endif
3929

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 36940

Download in other formats: