VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 37182

Last change on this file since 37182 was 37137, checked in by vboxsync, 14 years ago

Remvoed the non-PGM_USE_RAMRANGE_SEARCH_TREES code.
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File size: 177.1 KB
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1/* $Id: PGMInternal.h 37137 2011-05-18 14:49:39Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pvPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pvPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef union PGMPAGE
692{
693 /** Structured view. */
694 struct
695 {
696 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
697 uint64_t u2HandlerPhysStateY : 2;
698 /** 3:2 - Paging structure needed to map the page
699 * (PGM_PAGE_PDE_TYPE_*). */
700 uint64_t u2PDETypeY : 2;
701 /** 4 - Indicator of dirty page for fault tolerance tracking. */
702 uint64_t fFTDirtyY : 1;
703 /** 5 - Flag indicating that a write monitored page was written to
704 * when set. */
705 uint64_t fWrittenToY : 1;
706 /** 7:6 - Unused. */
707 uint64_t u2Unused0 : 2;
708 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
709 uint64_t u2HandlerVirtStateY : 2;
710 /** 11:10 - Unused. */
711 uint64_t u2Unused1 : 2;
712 /** 12:48 - The host physical frame number (shift left to get the
713 * address). */
714 uint64_t HCPhysFN : 36;
715 /** 50:48 - The page state. */
716 uint64_t uStateY : 3;
717 /** 51:53 - The page type (PGMPAGETYPE). */
718 uint64_t uTypeY : 3;
719 /** 63:54 - PTE index for usage tracking (page pool). */
720 uint64_t u10PteIdx : 10;
721
722 /** The GMM page ID. */
723 uint32_t idPage;
724 /** Usage tracking (page pool). */
725 uint16_t u16TrackingY;
726 /** The number of read locks on this page. */
727 uint8_t cReadLocksY;
728 /** The number of write locks on this page. */
729 uint8_t cWriteLocksY;
730 } s;
731
732 /** 64-bit integer view. */
733 uint64_t au64[2];
734 /** 16-bit view. */
735 uint32_t au32[4];
736 /** 16-bit view. */
737 uint16_t au16[8];
738 /** 8-bit view. */
739 uint8_t au8[16];
740} PGMPAGE;
741AssertCompileSize(PGMPAGE, 16);
742/** Pointer to a physical guest page. */
743typedef PGMPAGE *PPGMPAGE;
744/** Pointer to a const physical guest page. */
745typedef const PGMPAGE *PCPGMPAGE;
746/** Pointer to a physical guest page pointer. */
747typedef PPGMPAGE *PPPGMPAGE;
748
749
750/**
751 * Clears the page structure.
752 * @param a_pPage Pointer to the physical guest page tracking structure.
753 */
754#define PGM_PAGE_CLEAR(a_pPage) \
755 do { \
756 (a_pPage)->au64[0] = 0; \
757 (a_pPage)->au64[1] = 0; \
758 } while (0)
759
760/**
761 * Initializes the page structure.
762 * @param a_pPage Pointer to the physical guest page tracking structure.
763 */
764#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
765 do { \
766 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
767 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
768 (a_pPage)->au64[0] = SetHCPhysTmp; \
769 (a_pPage)->au64[1] = 0; \
770 (a_pPage)->s.idPage = (a_idPage); \
771 (a_pPage)->s.uStateY = (a_uState); \
772 (a_pPage)->s.uTypeY = (a_uType); \
773 } while (0)
774
775/**
776 * Initializes the page structure of a ZERO page.
777 * @param a_pPage Pointer to the physical guest page tracking structure.
778 * @param a_pVM The VM handle (for getting the zero page address).
779 * @param a_uType The page type (PGMPAGETYPE).
780 */
781#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
782 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
783
784
785/** @name The Page state, PGMPAGE::uStateY.
786 * @{ */
787/** The zero page.
788 * This is a per-VM page that's never ever mapped writable. */
789#define PGM_PAGE_STATE_ZERO 0
790/** A allocated page.
791 * This is a per-VM page allocated from the page pool (or wherever
792 * we get MMIO2 pages from if the type is MMIO2).
793 */
794#define PGM_PAGE_STATE_ALLOCATED 1
795/** A allocated page that's being monitored for writes.
796 * The shadow page table mappings are read-only. When a write occurs, the
797 * fWrittenTo member is set, the page remapped as read-write and the state
798 * moved back to allocated. */
799#define PGM_PAGE_STATE_WRITE_MONITORED 2
800/** The page is shared, aka. copy-on-write.
801 * This is a page that's shared with other VMs. */
802#define PGM_PAGE_STATE_SHARED 3
803/** The page is ballooned, so no longer available for this VM. */
804#define PGM_PAGE_STATE_BALLOONED 4
805/** @} */
806
807
808/**
809 * Gets the page state.
810 * @returns page state (PGM_PAGE_STATE_*).
811 * @param a_pPage Pointer to the physical guest page tracking structure.
812 */
813#define PGM_PAGE_GET_STATE(a_pPage) ( (a_pPage)->s.uStateY )
814
815/**
816 * Sets the page state.
817 * @param a_pPage Pointer to the physical guest page tracking structure.
818 * @param a_uState The new page state.
819 */
820#define PGM_PAGE_SET_STATE(a_pPage, a_uState) do { (a_pPage)->s.uStateY = (a_uState); } while (0)
821
822
823/**
824 * Gets the host physical address of the guest page.
825 * @returns host physical address (RTHCPHYS).
826 * @param a_pPage Pointer to the physical guest page tracking structure.
827 */
828#if 0
829#define PGM_PAGE_GET_HCPHYS(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
830#else
831#define PGM_PAGE_GET_HCPHYS(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
832#endif
833
834/**
835 * Sets the host physical address of the guest page.
836 * @param a_pPage Pointer to the physical guest page tracking structure.
837 * @param a_HCPhys The new host physical address.
838 */
839#define PGM_PAGE_SET_HCPHYS(a_pPage, a_HCPhys) \
840 do { \
841 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
842 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
843 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
844 } while (0)
845
846/**
847 * Get the Page ID.
848 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
849 * @param a_pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
852
853/**
854 * Sets the Page ID.
855 * @param a_pPage Pointer to the physical guest page tracking structure.
856 * @param a_idPage The new page ID.
857 */
858#define PGM_PAGE_SET_PAGEID(a_pPage, a_idPage) \
859 do { \
860 (a_pPage)->s.idPage = (a_idPage); \
861 } while (0)
862
863/**
864 * Get the Chunk ID.
865 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
866 * @param a_pPage Pointer to the physical guest page tracking structure.
867 */
868#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
869
870/**
871 * Get the index of the page within the allocation chunk.
872 * @returns The page index.
873 * @param a_pPage Pointer to the physical guest page tracking structure.
874 */
875#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
876
877/**
878 * Gets the page type.
879 * @returns The page type.
880 * @param a_pPage Pointer to the physical guest page tracking structure.
881 */
882#define PGM_PAGE_GET_TYPE(a_pPage) ( (a_pPage)->s.uTypeY )
883
884/**
885 * Sets the page type.
886 * @param a_pPage Pointer to the physical guest page tracking structure.
887 * @param a_enmType The new page type (PGMPAGETYPE).
888 */
889#define PGM_PAGE_SET_TYPE(a_pPage, a_enmType) do { (a_pPage)->s.uTypeY = (a_enmType); } while (0)
890
891/**
892 * Gets the page table index
893 * @returns The page table index.
894 * @param a_pPage Pointer to the physical guest page tracking structure.
895 */
896#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
897
898/**
899 * Sets the page table index.
900 * @param a_pPage Pointer to the physical guest page tracking structure.
901 * @param a_iPte New page table index.
902 */
903#define PGM_PAGE_SET_PTE_INDEX(a_pPage, a_iPte) do { (a_pPage)->s.u10PteIdx = (a_iPte); } while (0)
904
905/**
906 * Checks if the page is marked for MMIO.
907 * @returns true/false.
908 * @param a_pPage Pointer to the physical guest page tracking structure.
909 */
910#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
911
912/**
913 * Checks if the page is backed by the ZERO page.
914 * @returns true/false.
915 * @param a_pPage Pointer to the physical guest page tracking structure.
916 */
917#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
918
919/**
920 * Checks if the page is backed by a SHARED page.
921 * @returns true/false.
922 * @param a_pPage Pointer to the physical guest page tracking structure.
923 */
924#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
925
926/**
927 * Checks if the page is ballooned.
928 * @returns true/false.
929 * @param a_pPage Pointer to the physical guest page tracking structure.
930 */
931#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
932
933/**
934 * Checks if the page is allocated.
935 * @returns true/false.
936 * @param a_pPage Pointer to the physical guest page tracking structure.
937 */
938#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
939
940/**
941 * Marks the page as written to (for GMM change monitoring).
942 * @param a_pPage Pointer to the physical guest page tracking structure.
943 */
944#define PGM_PAGE_SET_WRITTEN_TO(a_pPage) do { (a_pPage)->au8[1] |= UINT8_C(0x80); } while (0) /// FIXME FIXME
945
946/**
947 * Clears the written-to indicator.
948 * @param a_pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pPage) do { (a_pPage)->s.fWrittenToY = 0; } while (0)
951
952/**
953 * Checks if the page was marked as written-to.
954 * @returns true/false.
955 * @param a_pPage Pointer to the physical guest page tracking structure.
956 */
957#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
958
959/**
960 * Marks the page as dirty for FTM
961 * @param a_pPage Pointer to the physical guest page tracking structure.
962 */
963#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
964
965/**
966 * Clears the FTM dirty indicator
967 * @param a_pPage Pointer to the physical guest page tracking structure.
968 */
969#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
970
971/**
972 * Checks if the page was marked as dirty for FTM
973 * @returns true/false.
974 * @param a_pPage Pointer to the physical guest page tracking structure.
975 */
976#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
977
978
979/** @name PT usage values (PGMPAGE::u2PDEType).
980 *
981 * @{ */
982/** Either as a PT or PDE. */
983#define PGM_PAGE_PDE_TYPE_DONTCARE 0
984/** Must use a page table to map the range. */
985#define PGM_PAGE_PDE_TYPE_PT 1
986/** Can use a page directory entry to map the continuous range. */
987#define PGM_PAGE_PDE_TYPE_PDE 2
988/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
989#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
990/** @} */
991
992/**
993 * Set the PDE type of the page
994 * @param a_pPage Pointer to the physical guest page tracking structure.
995 * @param a_uType PGM_PAGE_PDE_TYPE_*.
996 */
997#define PGM_PAGE_SET_PDE_TYPE(a_pPage, a_uType) \
998 do { (a_pPage)->s.u2PDETypeY = (a_uType); } while (0)
999
1000/**
1001 * Checks if the page was marked being part of a large page
1002 * @returns true/false.
1003 * @param a_pPage Pointer to the physical guest page tracking structure.
1004 */
1005#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1006
1007/** Enabled optimized access handler tests.
1008 * These optimizations makes ASSUMPTIONS about the state values and the s1
1009 * layout. When enabled, the compiler should normally generate more compact
1010 * code.
1011 */
1012#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1013
1014/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1015 *
1016 * @remarks The values are assigned in order of priority, so we can calculate
1017 * the correct state for a page with different handlers installed.
1018 * @{ */
1019/** No handler installed. */
1020#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1021/** Monitoring is temporarily disabled. */
1022#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1023/** Write access is monitored. */
1024#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1025/** All access is monitored. */
1026#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1027/** @} */
1028
1029/**
1030 * Gets the physical access handler state of a page.
1031 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1032 * @param a_pPage Pointer to the physical guest page tracking structure.
1033 */
1034#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1035
1036/**
1037 * Sets the physical access handler state of a page.
1038 * @param a_pPage Pointer to the physical guest page tracking structure.
1039 * @param a_uState The new state value.
1040 */
1041#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1042 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1043
1044/**
1045 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1046 * @returns true/false
1047 * @param a_pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1050 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1051
1052/**
1053 * Checks if the page has any active physical access handlers.
1054 * @returns true/false
1055 * @param a_pPage Pointer to the physical guest page tracking structure.
1056 */
1057#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1058 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1059
1060
1061/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1062 *
1063 * @remarks The values are assigned in order of priority, so we can calculate
1064 * the correct state for a page with different handlers installed.
1065 * @{ */
1066/** No handler installed. */
1067#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1068/* 1 is reserved so the lineup is identical with the physical ones. */
1069/** Write access is monitored. */
1070#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1071/** All access is monitored. */
1072#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1073/** @} */
1074
1075/**
1076 * Gets the virtual access handler state of a page.
1077 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1078 * @param a_pPage Pointer to the physical guest page tracking structure.
1079 */
1080#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1081
1082/**
1083 * Sets the virtual access handler state of a page.
1084 * @param a_pPage Pointer to the physical guest page tracking structure.
1085 * @param a_uState The new state value.
1086 */
1087#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1088 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1089
1090/**
1091 * Checks if the page has any virtual access handlers.
1092 * @returns true/false
1093 * @param a_pPage Pointer to the physical guest page tracking structure.
1094 */
1095#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1096 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1097
1098/**
1099 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1100 * virtual handlers.
1101 * @returns true/false
1102 * @param a_pPage Pointer to the physical guest page tracking structure.
1103 */
1104#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1105 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1106
1107
1108/**
1109 * Checks if the page has any access handlers, including temporarily disabled ones.
1110 * @returns true/false
1111 * @param a_pPage Pointer to the physical guest page tracking structure.
1112 */
1113#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1114# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1115 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1116#else
1117# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1118 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1119 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1120#endif
1121
1122/**
1123 * Checks if the page has any active access handlers.
1124 * @returns true/false
1125 * @param a_pPage Pointer to the physical guest page tracking structure.
1126 */
1127#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1128# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1129 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1130#else
1131# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1132 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1133 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1134#endif
1135
1136/**
1137 * Checks if the page has any active access handlers catching all accesses.
1138 * @returns true/false
1139 * @param a_pPage Pointer to the physical guest page tracking structure.
1140 */
1141#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1142# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1143 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1144 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1145#else
1146# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1147 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1148 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1149#endif
1150
1151
1152/** @def PGM_PAGE_GET_TRACKING
1153 * Gets the packed shadow page pool tracking data associated with a guest page.
1154 * @returns uint16_t containing the data.
1155 * @param a_pPage Pointer to the physical guest page tracking structure.
1156 */
1157#define PGM_PAGE_GET_TRACKING(a_pPage) ( (a_pPage)->s.u16TrackingY )
1158
1159/** @def PGM_PAGE_SET_TRACKING
1160 * Sets the packed shadow page pool tracking data associated with a guest page.
1161 * @param a_pPage Pointer to the physical guest page tracking structure.
1162 * @param a_u16TrackingData The tracking data to store.
1163 */
1164#define PGM_PAGE_SET_TRACKING(a_pPage, a_u16TrackingData) \
1165 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); } while (0)
1166
1167/** @def PGM_PAGE_GET_TD_CREFS
1168 * Gets the @a cRefs tracking data member.
1169 * @returns cRefs.
1170 * @param a_pPage Pointer to the physical guest page tracking structure.
1171 */
1172#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1173 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1174
1175/** @def PGM_PAGE_GET_TD_IDX
1176 * Gets the @a idx tracking data member.
1177 * @returns idx.
1178 * @param a_pPage Pointer to the physical guest page tracking structure.
1179 */
1180#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1181 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1182
1183
1184/** Max number of locks on a page. */
1185#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1186
1187/** Get the read lock count.
1188 * @returns count.
1189 * @param a_pPage Pointer to the physical guest page tracking structure.
1190 */
1191#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1192
1193/** Get the write lock count.
1194 * @returns count.
1195 * @param a_pPage Pointer to the physical guest page tracking structure.
1196 */
1197#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1198
1199/** Decrement the read lock counter.
1200 * @param a_pPage Pointer to the physical guest page tracking structure.
1201 */
1202#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1203
1204/** Decrement the write lock counter.
1205 * @param a_pPage Pointer to the physical guest page tracking structure.
1206 */
1207#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1208
1209/** Increment the read lock counter.
1210 * @param a_pPage Pointer to the physical guest page tracking structure.
1211 */
1212#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1213
1214/** Increment the write lock counter.
1215 * @param a_pPage Pointer to the physical guest page tracking structure.
1216 */
1217#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1218
1219
1220#if 0
1221/** Enables sanity checking of write monitoring using CRC-32. */
1222# define PGMLIVESAVERAMPAGE_WITH_CRC32
1223#endif
1224
1225/**
1226 * Per page live save tracking data.
1227 */
1228typedef struct PGMLIVESAVERAMPAGE
1229{
1230 /** Number of times it has been dirtied. */
1231 uint32_t cDirtied : 24;
1232 /** Whether it is currently dirty. */
1233 uint32_t fDirty : 1;
1234 /** Ignore the page.
1235 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1236 * deal with these after pausing the VM and DevPCI have said it bit about
1237 * remappings. */
1238 uint32_t fIgnore : 1;
1239 /** Was a ZERO page last time around. */
1240 uint32_t fZero : 1;
1241 /** Was a SHARED page last time around. */
1242 uint32_t fShared : 1;
1243 /** Whether the page is/was write monitored in a previous pass. */
1244 uint32_t fWriteMonitored : 1;
1245 /** Whether the page is/was write monitored earlier in this pass. */
1246 uint32_t fWriteMonitoredJustNow : 1;
1247 /** Bits reserved for future use. */
1248 uint32_t u2Reserved : 2;
1249#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1250 /** CRC-32 for the page. This is for internal consistency checks. */
1251 uint32_t u32Crc;
1252#endif
1253} PGMLIVESAVERAMPAGE;
1254#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1255AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1256#else
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1258#endif
1259/** Pointer to the per page live save tracking data. */
1260typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1261
1262/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1263#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1264
1265
1266/**
1267 * RAM range for GC Phys to HC Phys conversion.
1268 *
1269 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1270 * conversions too, but we'll let MM handle that for now.
1271 *
1272 * This structure is used by linked lists in both GC and HC.
1273 */
1274typedef struct PGMRAMRANGE
1275{
1276 /** Start of the range. Page aligned. */
1277 RTGCPHYS GCPhys;
1278 /** Size of the range. (Page aligned of course). */
1279 RTGCPHYS cb;
1280 /** Pointer to the next RAM range - for R3. */
1281 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1282 /** Pointer to the next RAM range - for R0. */
1283 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1284 /** Pointer to the next RAM range - for RC. */
1285 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1286 /** PGM_RAM_RANGE_FLAGS_* flags. */
1287 uint32_t fFlags;
1288 /** Last address in the range (inclusive). Page aligned (-1). */
1289 RTGCPHYS GCPhysLast;
1290 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1291 R3PTRTYPE(void *) pvR3;
1292 /** Live save per page tracking data. */
1293 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1294 /** The range description. */
1295 R3PTRTYPE(const char *) pszDesc;
1296 /** Pointer to self - R0 pointer. */
1297 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1298 /** Pointer to self - RC pointer. */
1299 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1300
1301 /** Alignment padding. */
1302 RTRCPTR Alignment0;
1303 /** Pointer to the left search three node - ring-3 context. */
1304 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1305 /** Pointer to the right search three node - ring-3 context. */
1306 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1307 /** Pointer to the left search three node - ring-0 context. */
1308 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1309 /** Pointer to the right search three node - ring-0 context. */
1310 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1311 /** Pointer to the left search three node - raw-mode context. */
1312 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1313 /** Pointer to the right search three node - raw-mode context. */
1314 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1315
1316 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1317#if HC_ARCH_BITS == 32
1318 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1319#endif
1320 /** Array of physical guest page tracking structures. */
1321 PGMPAGE aPages[1];
1322} PGMRAMRANGE;
1323/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1324typedef PGMRAMRANGE *PPGMRAMRANGE;
1325
1326/** @name PGMRAMRANGE::fFlags
1327 * @{ */
1328/** The RAM range is floating around as an independent guest mapping. */
1329#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1330/** Ad hoc RAM range for an ROM mapping. */
1331#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1332/** Ad hoc RAM range for an MMIO mapping. */
1333#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1334/** Ad hoc RAM range for an MMIO2 mapping. */
1335#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1336/** @} */
1337
1338/** Tests if a RAM range is an ad hoc one or not.
1339 * @returns true/false.
1340 * @param pRam The RAM range.
1341 */
1342#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1343 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1344
1345/** The number of entries in the RAM range TLBs (there is one for each
1346 * context). Must be a power of two. */
1347#define PGM_RAMRANGE_TLB_ENTRIES 8
1348
1349/**
1350 * Calculates the RAM range TLB index for the physical address.
1351 *
1352 * @returns RAM range TLB index.
1353 * @param GCPhys The guest physical address.
1354 */
1355#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1356
1357
1358
1359/**
1360 * Per page tracking structure for ROM image.
1361 *
1362 * A ROM image may have a shadow page, in which case we may have two pages
1363 * backing it. This structure contains the PGMPAGE for both while
1364 * PGMRAMRANGE have a copy of the active one. It is important that these
1365 * aren't out of sync in any regard other than page pool tracking data.
1366 */
1367typedef struct PGMROMPAGE
1368{
1369 /** The page structure for the virgin ROM page. */
1370 PGMPAGE Virgin;
1371 /** The page structure for the shadow RAM page. */
1372 PGMPAGE Shadow;
1373 /** The current protection setting. */
1374 PGMROMPROT enmProt;
1375 /** Live save status information. Makes use of unused alignment space. */
1376 struct
1377 {
1378 /** The previous protection value. */
1379 uint8_t u8Prot;
1380 /** Written to flag set by the handler. */
1381 bool fWrittenTo;
1382 /** Whether the shadow page is dirty or not. */
1383 bool fDirty;
1384 /** Whether it was dirtied in the recently. */
1385 bool fDirtiedRecently;
1386 } LiveSave;
1387} PGMROMPAGE;
1388AssertCompileSizeAlignment(PGMROMPAGE, 8);
1389/** Pointer to a ROM page tracking structure. */
1390typedef PGMROMPAGE *PPGMROMPAGE;
1391
1392
1393/**
1394 * A registered ROM image.
1395 *
1396 * This is needed to keep track of ROM image since they generally intrude
1397 * into a PGMRAMRANGE. It also keeps track of additional info like the
1398 * two page sets (read-only virgin and read-write shadow), the current
1399 * state of each page.
1400 *
1401 * Because access handlers cannot easily be executed in a different
1402 * context, the ROM ranges needs to be accessible and in all contexts.
1403 */
1404typedef struct PGMROMRANGE
1405{
1406 /** Pointer to the next range - R3. */
1407 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1408 /** Pointer to the next range - R0. */
1409 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1410 /** Pointer to the next range - RC. */
1411 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1412 /** Pointer alignment */
1413 RTRCPTR RCPtrAlignment;
1414 /** Address of the range. */
1415 RTGCPHYS GCPhys;
1416 /** Address of the last byte in the range. */
1417 RTGCPHYS GCPhysLast;
1418 /** Size of the range. */
1419 RTGCPHYS cb;
1420 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1421 uint32_t fFlags;
1422 /** The saved state range ID. */
1423 uint8_t idSavedState;
1424 /** Alignment padding. */
1425 uint8_t au8Alignment[3];
1426 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1427 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1428 /** The size bits pvOriginal points to. */
1429 uint32_t cbOriginal;
1430 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1431 * This is used for strictness checks. */
1432 R3PTRTYPE(const void *) pvOriginal;
1433 /** The ROM description. */
1434 R3PTRTYPE(const char *) pszDesc;
1435 /** The per page tracking structures. */
1436 PGMROMPAGE aPages[1];
1437} PGMROMRANGE;
1438/** Pointer to a ROM range. */
1439typedef PGMROMRANGE *PPGMROMRANGE;
1440
1441
1442/**
1443 * Live save per page data for an MMIO2 page.
1444 *
1445 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1446 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1447 * CRC-32 for detecting changes as well as special handling of zero pages. This
1448 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1449 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1450 * because of speed (2.5x and 6x slower).)
1451 *
1452 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1453 * save but normally is disabled. Since we can write monitor guest
1454 * accesses on our own, we only need this for host accesses. Shouldn't be
1455 * too difficult for DevVGA, VMMDev might be doable, the planned
1456 * networking fun will be fun since it involves ring-0.
1457 */
1458typedef struct PGMLIVESAVEMMIO2PAGE
1459{
1460 /** Set if the page is considered dirty. */
1461 bool fDirty;
1462 /** The number of scans this page has remained unchanged for.
1463 * Only updated for dirty pages. */
1464 uint8_t cUnchangedScans;
1465 /** Whether this page was zero at the last scan. */
1466 bool fZero;
1467 /** Alignment padding. */
1468 bool fReserved;
1469 /** CRC-32 for the first half of the page.
1470 * This is used together with u32CrcH2 to quickly detect changes in the page
1471 * during the non-final passes. */
1472 uint32_t u32CrcH1;
1473 /** CRC-32 for the second half of the page. */
1474 uint32_t u32CrcH2;
1475 /** SHA-1 for the saved page.
1476 * This is used in the final pass to skip pages without changes. */
1477 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1478} PGMLIVESAVEMMIO2PAGE;
1479/** Pointer to a live save status data for an MMIO2 page. */
1480typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1481
1482/**
1483 * A registered MMIO2 (= Device RAM) range.
1484 *
1485 * There are a few reason why we need to keep track of these
1486 * registrations. One of them is the deregistration & cleanup stuff,
1487 * while another is that the PGMRAMRANGE associated with such a region may
1488 * have to be removed from the ram range list.
1489 *
1490 * Overlapping with a RAM range has to be 100% or none at all. The pages
1491 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1492 * will be raised if a partial overlap or an overlap of ROM pages is
1493 * encountered. On an overlap we will free all the existing RAM pages and
1494 * put in the ram range pages instead.
1495 */
1496typedef struct PGMMMIO2RANGE
1497{
1498 /** The owner of the range. (a device) */
1499 PPDMDEVINSR3 pDevInsR3;
1500 /** Pointer to the ring-3 mapping of the allocation. */
1501 RTR3PTR pvR3;
1502 /** Pointer to the next range - R3. */
1503 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1504 /** Whether it's mapped or not. */
1505 bool fMapped;
1506 /** Whether it's overlapping or not. */
1507 bool fOverlapping;
1508 /** The PCI region number.
1509 * @remarks This ASSUMES that nobody will ever really need to have multiple
1510 * PCI devices with matching MMIO region numbers on a single device. */
1511 uint8_t iRegion;
1512 /** The saved state range ID. */
1513 uint8_t idSavedState;
1514 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1515 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1516 /** Live save per page tracking data. */
1517 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1518 /** The associated RAM range. */
1519 PGMRAMRANGE RamRange;
1520} PGMMMIO2RANGE;
1521/** Pointer to a MMIO2 range. */
1522typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1523
1524
1525
1526
1527/**
1528 * PGMPhysRead/Write cache entry
1529 */
1530typedef struct PGMPHYSCACHEENTRY
1531{
1532 /** R3 pointer to physical page. */
1533 R3PTRTYPE(uint8_t *) pbR3;
1534 /** GC Physical address for cache entry */
1535 RTGCPHYS GCPhys;
1536#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1537 RTGCPHYS u32Padding0; /**< alignment padding. */
1538#endif
1539} PGMPHYSCACHEENTRY;
1540
1541/**
1542 * PGMPhysRead/Write cache to reduce REM memory access overhead
1543 */
1544typedef struct PGMPHYSCACHE
1545{
1546 /** Bitmap of valid cache entries */
1547 uint64_t aEntries;
1548 /** Cache entries */
1549 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1550} PGMPHYSCACHE;
1551
1552
1553/** Pointer to an allocation chunk ring-3 mapping. */
1554typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1555/** Pointer to an allocation chunk ring-3 mapping pointer. */
1556typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1557
1558/**
1559 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1560 *
1561 * The primary tree (Core) uses the chunk id as key.
1562 */
1563typedef struct PGMCHUNKR3MAP
1564{
1565 /** The key is the chunk id. */
1566 AVLU32NODECORE Core;
1567 /** The current age thingy. */
1568 uint32_t iAge;
1569 /** The current reference count. */
1570 uint32_t volatile cRefs;
1571 /** The current permanent reference count. */
1572 uint32_t volatile cPermRefs;
1573 /** The mapping address. */
1574 void *pv;
1575} PGMCHUNKR3MAP;
1576
1577/**
1578 * Allocation chunk ring-3 mapping TLB entry.
1579 */
1580typedef struct PGMCHUNKR3MAPTLBE
1581{
1582 /** The chunk id. */
1583 uint32_t volatile idChunk;
1584#if HC_ARCH_BITS == 64
1585 uint32_t u32Padding; /**< alignment padding. */
1586#endif
1587 /** The chunk map. */
1588#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1589 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1590#else
1591 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1592#endif
1593} PGMCHUNKR3MAPTLBE;
1594/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1595typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1596
1597/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1598 * @remark Must be a power of two value. */
1599#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1600
1601/**
1602 * Allocation chunk ring-3 mapping TLB.
1603 *
1604 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1605 * At first glance this might look kinda odd since AVL trees are
1606 * supposed to give the most optimal lookup times of all trees
1607 * due to their balancing. However, take a tree with 1023 nodes
1608 * in it, that's 10 levels, meaning that most searches has to go
1609 * down 9 levels before they find what they want. This isn't fast
1610 * compared to a TLB hit. There is the factor of cache misses,
1611 * and of course the problem with trees and branch prediction.
1612 * This is why we use TLBs in front of most of the trees.
1613 *
1614 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1615 * difficult when we switch to the new inlined AVL trees (from kStuff).
1616 */
1617typedef struct PGMCHUNKR3MAPTLB
1618{
1619 /** The TLB entries. */
1620 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1621} PGMCHUNKR3MAPTLB;
1622
1623/**
1624 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1625 * @returns Chunk TLB index.
1626 * @param idChunk The Chunk ID.
1627 */
1628#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1629
1630
1631/**
1632 * Ring-3 guest page mapping TLB entry.
1633 * @remarks used in ring-0 as well at the moment.
1634 */
1635typedef struct PGMPAGER3MAPTLBE
1636{
1637 /** Address of the page. */
1638 RTGCPHYS volatile GCPhys;
1639 /** The guest page. */
1640#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1641 R3PTRTYPE(PPGMPAGE) volatile pPage;
1642#else
1643 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1644#endif
1645 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1646#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1647 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1648#else
1649 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1650#endif
1651 /** The address */
1652#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1653 R3PTRTYPE(void *) volatile pv;
1654#else
1655 R3R0PTRTYPE(void *) volatile pv;
1656#endif
1657#if HC_ARCH_BITS == 32
1658 uint32_t u32Padding; /**< alignment padding. */
1659#endif
1660} PGMPAGER3MAPTLBE;
1661/** Pointer to an entry in the HC physical TLB. */
1662typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1663
1664
1665/** The number of entries in the ring-3 guest page mapping TLB.
1666 * @remarks The value must be a power of two. */
1667#define PGM_PAGER3MAPTLB_ENTRIES 256
1668
1669/**
1670 * Ring-3 guest page mapping TLB.
1671 * @remarks used in ring-0 as well at the moment.
1672 */
1673typedef struct PGMPAGER3MAPTLB
1674{
1675 /** The TLB entries. */
1676 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1677} PGMPAGER3MAPTLB;
1678/** Pointer to the ring-3 guest page mapping TLB. */
1679typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1680
1681/**
1682 * Calculates the index of the TLB entry for the specified guest page.
1683 * @returns Physical TLB index.
1684 * @param GCPhys The guest physical address.
1685 */
1686#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1687
1688
1689/**
1690 * Raw-mode context dynamic mapping cache entry.
1691 *
1692 * Because of raw-mode context being reloctable and all relocations are applied
1693 * in ring-3, this has to be defined here and be RC specific.
1694 *
1695 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1696 */
1697typedef struct PGMRCDYNMAPENTRY
1698{
1699 /** The physical address of the currently mapped page.
1700 * This is duplicate for three reasons: cache locality, cache policy of the PT
1701 * mappings and sanity checks. */
1702 RTHCPHYS HCPhys;
1703 /** Pointer to the page. */
1704 RTRCPTR pvPage;
1705 /** The number of references. */
1706 int32_t volatile cRefs;
1707 /** PTE pointer union. */
1708 struct PGMRCDYNMAPENTRY_PPTE
1709 {
1710 /** PTE pointer, 32-bit legacy version. */
1711 RCPTRTYPE(PX86PTE) pLegacy;
1712 /** PTE pointer, PAE version. */
1713 RCPTRTYPE(PX86PTEPAE) pPae;
1714 } uPte;
1715} PGMRCDYNMAPENTRY;
1716/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1717typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1718
1719
1720/**
1721 * Dynamic mapping cache for the raw-mode context.
1722 *
1723 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1724 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1725 * so that we can perform relocations from PGMR3Relocate. This has the
1726 * consequence that we must have separate ring-0 and raw-mode context versions
1727 * of this struct even if they share the basic elements.
1728 *
1729 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1730 */
1731typedef struct PGMRCDYNMAP
1732{
1733 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1734 uint32_t u32Magic;
1735 /** Array for tracking and managing the pages. */
1736 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1737 /** The cache size given as a number of pages. */
1738 uint32_t cPages;
1739 /** The current load.
1740 * This does not include guard pages. */
1741 uint32_t cLoad;
1742 /** The max load ever.
1743 * This is maintained to get trigger adding of more mapping space. */
1744 uint32_t cMaxLoad;
1745 /** The number of guard pages. */
1746 uint32_t cGuardPages;
1747 /** The number of users (protected by hInitLock). */
1748 uint32_t cUsers;
1749} PGMRCDYNMAP;
1750/** Pointer to the dynamic cache for the raw-mode context. */
1751typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1752
1753
1754/**
1755 * Mapping cache usage set entry.
1756 *
1757 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1758 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1759 * cache. If it's extended to include ring-3, well, then something
1760 * will have be changed here...
1761 */
1762typedef struct PGMMAPSETENTRY
1763{
1764 /** Pointer to the page. */
1765#ifndef IN_RC
1766 RTR0PTR pvPage;
1767#else
1768 RTRCPTR pvPage;
1769# if HC_ARCH_BITS == 64
1770 uint32_t u32Alignment2;
1771# endif
1772#endif
1773 /** The mapping cache index. */
1774 uint16_t iPage;
1775 /** The number of references.
1776 * The max is UINT16_MAX - 1. */
1777 uint16_t cRefs;
1778 /** The number inlined references.
1779 * The max is UINT16_MAX - 1. */
1780 uint16_t cInlinedRefs;
1781 /** Unreferences. */
1782 uint16_t cUnrefs;
1783
1784#if HC_ARCH_BITS == 32
1785 uint32_t u32Alignment1;
1786#endif
1787 /** The physical address for this entry. */
1788 RTHCPHYS HCPhys;
1789} PGMMAPSETENTRY;
1790AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1791AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1792/** Pointer to a mapping cache usage set entry. */
1793typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1794
1795/**
1796 * Mapping cache usage set.
1797 *
1798 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1799 * done during exits / traps. The set is
1800 */
1801typedef struct PGMMAPSET
1802{
1803 /** The number of occupied entries.
1804 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1805 * dynamic mappings. */
1806 uint32_t cEntries;
1807 /** The start of the current subset.
1808 * This is UINT32_MAX if no subset is currently open. */
1809 uint32_t iSubset;
1810 /** The index of the current CPU, only valid if the set is open. */
1811 int32_t iCpu;
1812 uint32_t alignment;
1813 /** The entries. */
1814 PGMMAPSETENTRY aEntries[64];
1815 /** HCPhys -> iEntry fast lookup table.
1816 * Use PGMMAPSET_HASH for hashing.
1817 * The entries may or may not be valid, check against cEntries. */
1818 uint8_t aiHashTable[128];
1819} PGMMAPSET;
1820AssertCompileSizeAlignment(PGMMAPSET, 8);
1821/** Pointer to the mapping cache set. */
1822typedef PGMMAPSET *PPGMMAPSET;
1823
1824/** PGMMAPSET::cEntries value for a closed set. */
1825#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1826
1827/** Hash function for aiHashTable. */
1828#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1829
1830
1831/** @name Context neutral page mapper TLB.
1832 *
1833 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1834 * code is writting in a kind of context neutral way. Time will show whether
1835 * this actually makes sense or not...
1836 *
1837 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1838 * context ends up using a global mapping cache on some platforms
1839 * (darwin).
1840 *
1841 * @{ */
1842/** @typedef PPGMPAGEMAPTLB
1843 * The page mapper TLB pointer type for the current context. */
1844/** @typedef PPGMPAGEMAPTLB
1845 * The page mapper TLB entry pointer type for the current context. */
1846/** @typedef PPGMPAGEMAPTLB
1847 * The page mapper TLB entry pointer pointer type for the current context. */
1848/** @def PGM_PAGEMAPTLB_ENTRIES
1849 * The number of TLB entries in the page mapper TLB for the current context. */
1850/** @def PGM_PAGEMAPTLB_IDX
1851 * Calculate the TLB index for a guest physical address.
1852 * @returns The TLB index.
1853 * @param GCPhys The guest physical address. */
1854/** @typedef PPGMPAGEMAP
1855 * Pointer to a page mapper unit for current context. */
1856/** @typedef PPPGMPAGEMAP
1857 * Pointer to a page mapper unit pointer for current context. */
1858#ifdef IN_RC
1859// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1860// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1861// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1862# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1863# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1864 typedef void * PPGMPAGEMAP;
1865 typedef void ** PPPGMPAGEMAP;
1866//#elif IN_RING0
1867// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1868// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1869// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1870//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1871//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1872// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1873// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1874#else
1875 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1876 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1877 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1878# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1879# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1880 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1881 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1882#endif
1883/** @} */
1884
1885
1886/** @name PGM Pool Indexes.
1887 * Aka. the unique shadow page identifier.
1888 * @{ */
1889/** NIL page pool IDX. */
1890#define NIL_PGMPOOL_IDX 0
1891/** The first normal index. */
1892#define PGMPOOL_IDX_FIRST_SPECIAL 1
1893/** Page directory (32-bit root). */
1894#define PGMPOOL_IDX_PD 1
1895/** Page Directory Pointer Table (PAE root). */
1896#define PGMPOOL_IDX_PDPT 2
1897/** AMD64 CR3 level index.*/
1898#define PGMPOOL_IDX_AMD64_CR3 3
1899/** Nested paging root.*/
1900#define PGMPOOL_IDX_NESTED_ROOT 4
1901/** The first normal index. */
1902#define PGMPOOL_IDX_FIRST 5
1903/** The last valid index. (inclusive, 14 bits) */
1904#define PGMPOOL_IDX_LAST 0x3fff
1905/** @} */
1906
1907/** The NIL index for the parent chain. */
1908#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1909#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1910
1911/**
1912 * Node in the chain linking a shadowed page to it's parent (user).
1913 */
1914#pragma pack(1)
1915typedef struct PGMPOOLUSER
1916{
1917 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1918 uint16_t iNext;
1919 /** The user page index. */
1920 uint16_t iUser;
1921 /** Index into the user table. */
1922 uint32_t iUserTable;
1923} PGMPOOLUSER, *PPGMPOOLUSER;
1924typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1925#pragma pack()
1926
1927
1928/** The NIL index for the phys ext chain. */
1929#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1930/** The NIL pte index for a phys ext chain slot. */
1931#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1932
1933/**
1934 * Node in the chain of physical cross reference extents.
1935 * @todo Calling this an 'extent' is not quite right, find a better name.
1936 * @todo find out the optimal size of the aidx array
1937 */
1938#pragma pack(1)
1939typedef struct PGMPOOLPHYSEXT
1940{
1941 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1942 uint16_t iNext;
1943 /** Alignment. */
1944 uint16_t u16Align;
1945 /** The user page index. */
1946 uint16_t aidx[3];
1947 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1948 uint16_t apte[3];
1949} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1950typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1951#pragma pack()
1952
1953
1954/**
1955 * The kind of page that's being shadowed.
1956 */
1957typedef enum PGMPOOLKIND
1958{
1959 /** The virtual invalid 0 entry. */
1960 PGMPOOLKIND_INVALID = 0,
1961 /** The entry is free (=unused). */
1962 PGMPOOLKIND_FREE,
1963
1964 /** Shw: 32-bit page table; Gst: no paging */
1965 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1966 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1967 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1968 /** Shw: 32-bit page table; Gst: 4MB page. */
1969 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1970 /** Shw: PAE page table; Gst: no paging */
1971 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1972 /** Shw: PAE page table; Gst: 32-bit page table. */
1973 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1974 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1975 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1976 /** Shw: PAE page table; Gst: PAE page table. */
1977 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1978 /** Shw: PAE page table; Gst: 2MB page. */
1979 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1980
1981 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1982 PGMPOOLKIND_32BIT_PD,
1983 /** Shw: 32-bit page directory. Gst: no paging. */
1984 PGMPOOLKIND_32BIT_PD_PHYS,
1985 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1986 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1987 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1988 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1989 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1990 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1991 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1992 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1993 /** Shw: PAE page directory; Gst: PAE page directory. */
1994 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1995 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1996 PGMPOOLKIND_PAE_PD_PHYS,
1997
1998 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1999 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2000 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2001 PGMPOOLKIND_PAE_PDPT,
2002 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2003 PGMPOOLKIND_PAE_PDPT_PHYS,
2004
2005 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2006 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2007 /** Shw: 64-bit page directory pointer table; Gst: no paging */
2008 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2009 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2010 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2011 /** Shw: 64-bit page directory table; Gst: no paging */
2012 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
2013
2014 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2015 PGMPOOLKIND_64BIT_PML4,
2016
2017 /** Shw: EPT page directory pointer table; Gst: no paging */
2018 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2019 /** Shw: EPT page directory table; Gst: no paging */
2020 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2021 /** Shw: EPT page table; Gst: no paging */
2022 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2023
2024 /** Shw: Root Nested paging table. */
2025 PGMPOOLKIND_ROOT_NESTED,
2026
2027 /** The last valid entry. */
2028 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2029} PGMPOOLKIND;
2030
2031/**
2032 * The access attributes of the page; only applies to big pages.
2033 */
2034typedef enum
2035{
2036 PGMPOOLACCESS_DONTCARE = 0,
2037 PGMPOOLACCESS_USER_RW,
2038 PGMPOOLACCESS_USER_R,
2039 PGMPOOLACCESS_USER_RW_NX,
2040 PGMPOOLACCESS_USER_R_NX,
2041 PGMPOOLACCESS_SUPERVISOR_RW,
2042 PGMPOOLACCESS_SUPERVISOR_R,
2043 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2044 PGMPOOLACCESS_SUPERVISOR_R_NX
2045} PGMPOOLACCESS;
2046
2047/**
2048 * The tracking data for a page in the pool.
2049 */
2050typedef struct PGMPOOLPAGE
2051{
2052 /** AVL node code with the (R3) physical address of this page. */
2053 AVLOHCPHYSNODECORE Core;
2054 /** Pointer to the R3 mapping of the page. */
2055#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2056 R3PTRTYPE(void *) pvPageR3;
2057#else
2058 R3R0PTRTYPE(void *) pvPageR3;
2059#endif
2060 /** The guest physical address. */
2061#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2062 uint32_t Alignment0;
2063#endif
2064 RTGCPHYS GCPhys;
2065
2066 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2067 RTGCPTR pvLastAccessHandlerRip;
2068 RTGCPTR pvLastAccessHandlerFault;
2069 uint64_t cLastAccessHandlerCount;
2070
2071 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2072 uint8_t enmKind;
2073 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2074 uint8_t enmAccess;
2075 /** The index of this page. */
2076 uint16_t idx;
2077 /** The next entry in the list this page currently resides in.
2078 * It's either in the free list or in the GCPhys hash. */
2079 uint16_t iNext;
2080 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2081 uint16_t iUserHead;
2082 /** The number of present entries. */
2083 uint16_t cPresent;
2084 /** The first entry in the table which is present. */
2085 uint16_t iFirstPresent;
2086 /** The number of modifications to the monitored page. */
2087 uint16_t cModifications;
2088 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2089 uint16_t iModifiedNext;
2090 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2091 uint16_t iModifiedPrev;
2092 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2093 uint16_t iMonitoredNext;
2094 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2095 uint16_t iMonitoredPrev;
2096 /** The next page in the age list. */
2097 uint16_t iAgeNext;
2098 /** The previous page in the age list. */
2099 uint16_t iAgePrev;
2100 /** Used to indicate that the page is zeroed. */
2101 bool fZeroed;
2102 /** Used to indicate that a PT has non-global entries. */
2103 bool fSeenNonGlobal;
2104 /** Used to indicate that we're monitoring writes to the guest page. */
2105 bool fMonitored;
2106 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2107 * (All pages are in the age list.) */
2108 bool fCached;
2109 /** This is used by the R3 access handlers when invoked by an async thread.
2110 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2111 bool volatile fReusedFlushPending;
2112 /** Used to mark the page as dirty (write monitoring is temporarily
2113 * off). */
2114 bool fDirty;
2115
2116 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2117 uint32_t cLocked;
2118 uint32_t idxDirty;
2119 RTGCPTR pvDirtyFault;
2120} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2121/** Pointer to a const pool page. */
2122typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2123
2124
2125/** The hash table size. */
2126# define PGMPOOL_HASH_SIZE 0x40
2127/** The hash function. */
2128# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2129
2130
2131/**
2132 * The shadow page pool instance data.
2133 *
2134 * It's all one big allocation made at init time, except for the
2135 * pages that is. The user nodes follows immediately after the
2136 * page structures.
2137 */
2138typedef struct PGMPOOL
2139{
2140 /** The VM handle - R3 Ptr. */
2141 PVMR3 pVMR3;
2142 /** The VM handle - R0 Ptr. */
2143 PVMR0 pVMR0;
2144 /** The VM handle - RC Ptr. */
2145 PVMRC pVMRC;
2146 /** The max pool size. This includes the special IDs. */
2147 uint16_t cMaxPages;
2148 /** The current pool size. */
2149 uint16_t cCurPages;
2150 /** The head of the free page list. */
2151 uint16_t iFreeHead;
2152 /* Padding. */
2153 uint16_t u16Padding;
2154 /** Head of the chain of free user nodes. */
2155 uint16_t iUserFreeHead;
2156 /** The number of user nodes we've allocated. */
2157 uint16_t cMaxUsers;
2158 /** The number of present page table entries in the entire pool. */
2159 uint32_t cPresent;
2160 /** Pointer to the array of user nodes - RC pointer. */
2161 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2162 /** Pointer to the array of user nodes - R3 pointer. */
2163 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2164 /** Pointer to the array of user nodes - R0 pointer. */
2165 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2166 /** Head of the chain of free phys ext nodes. */
2167 uint16_t iPhysExtFreeHead;
2168 /** The number of user nodes we've allocated. */
2169 uint16_t cMaxPhysExts;
2170 /** Pointer to the array of physical xref extent - RC pointer. */
2171 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2172 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2173 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2174 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2175 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2176 /** Hash table for GCPhys addresses. */
2177 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2178 /** The head of the age list. */
2179 uint16_t iAgeHead;
2180 /** The tail of the age list. */
2181 uint16_t iAgeTail;
2182 /** Set if the cache is enabled. */
2183 bool fCacheEnabled;
2184 /** Alignment padding. */
2185 bool afPadding1[3];
2186 /** Head of the list of modified pages. */
2187 uint16_t iModifiedHead;
2188 /** The current number of modified pages. */
2189 uint16_t cModifiedPages;
2190 /** Access handler, RC. */
2191 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2192 /** Access handler, R0. */
2193 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2194 /** Access handler, R3. */
2195 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2196 /** The access handler description (R3 ptr). */
2197 R3PTRTYPE(const char *) pszAccessHandler;
2198# if HC_ARCH_BITS == 32
2199 /** Alignment padding. */
2200 uint32_t u32Padding2;
2201# endif
2202 /* Next available slot. */
2203 uint32_t idxFreeDirtyPage;
2204 /* Number of active dirty pages. */
2205 uint32_t cDirtyPages;
2206 /* Array of current dirty pgm pool page indices. */
2207 struct
2208 {
2209 uint16_t uIdx;
2210 uint16_t Alignment[3];
2211 uint64_t aPage[512];
2212 } aDirtyPages[16];
2213 /** The number of pages currently in use. */
2214 uint16_t cUsedPages;
2215#ifdef VBOX_WITH_STATISTICS
2216 /** The high water mark for cUsedPages. */
2217 uint16_t cUsedPagesHigh;
2218 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2219 /** Profiling pgmPoolAlloc(). */
2220 STAMPROFILEADV StatAlloc;
2221 /** Profiling pgmR3PoolClearDoIt(). */
2222 STAMPROFILE StatClearAll;
2223 /** Profiling pgmR3PoolReset(). */
2224 STAMPROFILE StatR3Reset;
2225 /** Profiling pgmPoolFlushPage(). */
2226 STAMPROFILE StatFlushPage;
2227 /** Profiling pgmPoolFree(). */
2228 STAMPROFILE StatFree;
2229 /** Counting explicit flushes by PGMPoolFlushPage(). */
2230 STAMCOUNTER StatForceFlushPage;
2231 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2232 STAMCOUNTER StatForceFlushDirtyPage;
2233 /** Counting flushes for reused pages. */
2234 STAMCOUNTER StatForceFlushReused;
2235 /** Profiling time spent zeroing pages. */
2236 STAMPROFILE StatZeroPage;
2237 /** Profiling of pgmPoolTrackDeref. */
2238 STAMPROFILE StatTrackDeref;
2239 /** Profiling pgmTrackFlushGCPhysPT. */
2240 STAMPROFILE StatTrackFlushGCPhysPT;
2241 /** Profiling pgmTrackFlushGCPhysPTs. */
2242 STAMPROFILE StatTrackFlushGCPhysPTs;
2243 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2244 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2245 /** Number of times we've been out of user records. */
2246 STAMCOUNTER StatTrackFreeUpOneUser;
2247 /** Nr of flushed entries. */
2248 STAMCOUNTER StatTrackFlushEntry;
2249 /** Nr of updated entries. */
2250 STAMCOUNTER StatTrackFlushEntryKeep;
2251 /** Profiling deref activity related tracking GC physical pages. */
2252 STAMPROFILE StatTrackDerefGCPhys;
2253 /** Number of linear searches for a HCPhys in the ram ranges. */
2254 STAMCOUNTER StatTrackLinearRamSearches;
2255 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2256 STAMCOUNTER StamTrackPhysExtAllocFailures;
2257 /** Profiling the RC/R0 access handler. */
2258 STAMPROFILE StatMonitorRZ;
2259 /** Times we've failed interpreting the instruction. */
2260 STAMCOUNTER StatMonitorRZEmulateInstr;
2261 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2262 STAMPROFILE StatMonitorRZFlushPage;
2263 /* Times we've detected a page table reinit. */
2264 STAMCOUNTER StatMonitorRZFlushReinit;
2265 /** Counting flushes for pages that are modified too often. */
2266 STAMCOUNTER StatMonitorRZFlushModOverflow;
2267 /** Times we've detected fork(). */
2268 STAMCOUNTER StatMonitorRZFork;
2269 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2270 STAMPROFILE StatMonitorRZHandled;
2271 /** Times we've failed interpreting a patch code instruction. */
2272 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2273 /** Times we've failed interpreting a patch code instruction during flushing. */
2274 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2275 /** The number of times we've seen rep prefixes we can't handle. */
2276 STAMCOUNTER StatMonitorRZRepPrefix;
2277 /** Profiling the REP STOSD cases we've handled. */
2278 STAMPROFILE StatMonitorRZRepStosd;
2279 /** Nr of handled PT faults. */
2280 STAMCOUNTER StatMonitorRZFaultPT;
2281 /** Nr of handled PD faults. */
2282 STAMCOUNTER StatMonitorRZFaultPD;
2283 /** Nr of handled PDPT faults. */
2284 STAMCOUNTER StatMonitorRZFaultPDPT;
2285 /** Nr of handled PML4 faults. */
2286 STAMCOUNTER StatMonitorRZFaultPML4;
2287
2288 /** Profiling the R3 access handler. */
2289 STAMPROFILE StatMonitorR3;
2290 /** Times we've failed interpreting the instruction. */
2291 STAMCOUNTER StatMonitorR3EmulateInstr;
2292 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2293 STAMPROFILE StatMonitorR3FlushPage;
2294 /* Times we've detected a page table reinit. */
2295 STAMCOUNTER StatMonitorR3FlushReinit;
2296 /** Counting flushes for pages that are modified too often. */
2297 STAMCOUNTER StatMonitorR3FlushModOverflow;
2298 /** Times we've detected fork(). */
2299 STAMCOUNTER StatMonitorR3Fork;
2300 /** Profiling the R3 access we've handled (except REP STOSD). */
2301 STAMPROFILE StatMonitorR3Handled;
2302 /** The number of times we've seen rep prefixes we can't handle. */
2303 STAMCOUNTER StatMonitorR3RepPrefix;
2304 /** Profiling the REP STOSD cases we've handled. */
2305 STAMPROFILE StatMonitorR3RepStosd;
2306 /** Nr of handled PT faults. */
2307 STAMCOUNTER StatMonitorR3FaultPT;
2308 /** Nr of handled PD faults. */
2309 STAMCOUNTER StatMonitorR3FaultPD;
2310 /** Nr of handled PDPT faults. */
2311 STAMCOUNTER StatMonitorR3FaultPDPT;
2312 /** Nr of handled PML4 faults. */
2313 STAMCOUNTER StatMonitorR3FaultPML4;
2314 /** The number of times we're called in an async thread an need to flush. */
2315 STAMCOUNTER StatMonitorR3Async;
2316 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2317 STAMCOUNTER StatResetDirtyPages;
2318 /** Times we've called pgmPoolAddDirtyPage. */
2319 STAMCOUNTER StatDirtyPage;
2320 /** Times we've had to flush duplicates for dirty page management. */
2321 STAMCOUNTER StatDirtyPageDupFlush;
2322 /** Times we've had to flush because of overflow. */
2323 STAMCOUNTER StatDirtyPageOverFlowFlush;
2324
2325 /** The high water mark for cModifiedPages. */
2326 uint16_t cModifiedPagesHigh;
2327 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2328
2329 /** The number of cache hits. */
2330 STAMCOUNTER StatCacheHits;
2331 /** The number of cache misses. */
2332 STAMCOUNTER StatCacheMisses;
2333 /** The number of times we've got a conflict of 'kind' in the cache. */
2334 STAMCOUNTER StatCacheKindMismatches;
2335 /** Number of times we've been out of pages. */
2336 STAMCOUNTER StatCacheFreeUpOne;
2337 /** The number of cacheable allocations. */
2338 STAMCOUNTER StatCacheCacheable;
2339 /** The number of uncacheable allocations. */
2340 STAMCOUNTER StatCacheUncacheable;
2341#else
2342 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2343#endif
2344 /** The AVL tree for looking up a page by its HC physical address. */
2345 AVLOHCPHYSTREE HCPhysTree;
2346 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2347 /** Array of pages. (cMaxPages in length)
2348 * The Id is the index into thist array.
2349 */
2350 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2351} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2352AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2353AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2354AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2355#ifdef VBOX_WITH_STATISTICS
2356AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2357#endif
2358AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2359
2360
2361/** @def PGMPOOL_PAGE_2_PTR
2362 * Maps a pool page pool into the current context.
2363 *
2364 * @returns VBox status code.
2365 * @param a_pVM The VM handle.
2366 * @param a_pPage The pool page.
2367 *
2368 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2369 * small page window employeed by that function. Be careful.
2370 * @remark There is no need to assert on the result.
2371 */
2372#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2373# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2374#elif defined(VBOX_STRICT)
2375# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage)
2376DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage)
2377{
2378 Assert(a_pPage && a_pPage->pvPageR3);
2379 return a_pPage->pvPageR3;
2380}
2381#else
2382# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2383#endif
2384
2385
2386/** @def PGMPOOL_PAGE_2_PTR_V2
2387 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2388 *
2389 * @returns VBox status code.
2390 * @param a_pVM The VM handle.
2391 * @param a_pVCpu The current CPU.
2392 * @param a_pPage The pool page.
2393 *
2394 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2395 * small page window employeed by that function. Be careful.
2396 * @remark There is no need to assert on the result.
2397 */
2398#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2399# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2400#else
2401# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2402#endif
2403
2404
2405/** @name Per guest page tracking data.
2406 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2407 * is to use more bits for it and split it up later on. But for now we'll play
2408 * safe and change as little as possible.
2409 *
2410 * The 16-bit word has two parts:
2411 *
2412 * The first 14-bit forms the @a idx field. It is either the index of a page in
2413 * the shadow page pool, or and index into the extent list.
2414 *
2415 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2416 * shadow page pool references to the page. If cRefs equals
2417 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2418 * (misnomer) table and not the shadow page pool.
2419 *
2420 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2421 * the 16-bit word.
2422 *
2423 * @{ */
2424/** The shift count for getting to the cRefs part. */
2425#define PGMPOOL_TD_CREFS_SHIFT 14
2426/** The mask applied after shifting the tracking data down by
2427 * PGMPOOL_TD_CREFS_SHIFT. */
2428#define PGMPOOL_TD_CREFS_MASK 0x3
2429/** The cRefs value used to indicate that the idx is the head of a
2430 * physical cross reference list. */
2431#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2432/** The shift used to get idx. */
2433#define PGMPOOL_TD_IDX_SHIFT 0
2434/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2435#define PGMPOOL_TD_IDX_MASK 0x3fff
2436/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2437 * simply too many mappings of this page. */
2438#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2439
2440/** @def PGMPOOL_TD_MAKE
2441 * Makes a 16-bit tracking data word.
2442 *
2443 * @returns tracking data.
2444 * @param cRefs The @a cRefs field. Must be within bounds!
2445 * @param idx The @a idx field. Must also be within bounds! */
2446#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2447
2448/** @def PGMPOOL_TD_GET_CREFS
2449 * Get the @a cRefs field from a tracking data word.
2450 *
2451 * @returns The @a cRefs field
2452 * @param u16 The tracking data word.
2453 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2454 * non-zero @a u16. */
2455#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2456
2457/** @def PGMPOOL_TD_GET_IDX
2458 * Get the @a idx field from a tracking data word.
2459 *
2460 * @returns The @a idx field
2461 * @param u16 The tracking data word. */
2462#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2463/** @} */
2464
2465
2466/**
2467 * Trees are using self relative offsets as pointers.
2468 * So, all its data, including the root pointer, must be in the heap for HC and GC
2469 * to have the same layout.
2470 */
2471typedef struct PGMTREES
2472{
2473 /** Physical access handlers (AVL range+offsetptr tree). */
2474 AVLROGCPHYSTREE PhysHandlers;
2475 /** Virtual access handlers (AVL range + GC ptr tree). */
2476 AVLROGCPTRTREE VirtHandlers;
2477 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2478 AVLROGCPHYSTREE PhysToVirtHandlers;
2479 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2480 AVLROGCPTRTREE HyperVirtHandlers;
2481} PGMTREES;
2482/** Pointer to PGM trees. */
2483typedef PGMTREES *PPGMTREES;
2484
2485
2486/**
2487 * Page fault guest state for the AMD64 paging mode.
2488 */
2489typedef struct PGMPTWALKCORE
2490{
2491 /** The guest virtual address that is being resolved by the walk
2492 * (input). */
2493 RTGCPTR GCPtr;
2494
2495 /** The guest physical address that is the result of the walk.
2496 * @remarks only valid if fSucceeded is set. */
2497 RTGCPHYS GCPhys;
2498
2499 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2500 bool fSucceeded;
2501 /** The level problem arrised at.
2502 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2503 * level 8. This is 0 on success. */
2504 uint8_t uLevel;
2505 /** Set if the page isn't present. */
2506 bool fNotPresent;
2507 /** Encountered a bad physical address. */
2508 bool fBadPhysAddr;
2509 /** Set if there was reserved bit violations. */
2510 bool fRsvdError;
2511 /** Set if it involves a big page (2/4 MB). */
2512 bool fBigPage;
2513 /** Set if it involves a gigantic page (1 GB). */
2514 bool fGigantPage;
2515 /** The effect X86_PTE_US flag for the address. */
2516 bool fEffectiveUS;
2517 /** The effect X86_PTE_RW flag for the address. */
2518 bool fEffectiveRW;
2519 /** The effect X86_PTE_NX flag for the address. */
2520 bool fEffectiveNX;
2521} PGMPTWALKCORE;
2522
2523
2524/**
2525 * Guest page table walk for the AMD64 mode.
2526 */
2527typedef struct PGMPTWALKGSTAMD64
2528{
2529 /** The common core. */
2530 PGMPTWALKCORE Core;
2531
2532 PX86PML4 pPml4;
2533 PX86PML4E pPml4e;
2534 X86PML4E Pml4e;
2535
2536 PX86PDPT pPdpt;
2537 PX86PDPE pPdpe;
2538 X86PDPE Pdpe;
2539
2540 PX86PDPAE pPd;
2541 PX86PDEPAE pPde;
2542 X86PDEPAE Pde;
2543
2544 PX86PTPAE pPt;
2545 PX86PTEPAE pPte;
2546 X86PTEPAE Pte;
2547} PGMPTWALKGSTAMD64;
2548/** Pointer to a AMD64 guest page table walk. */
2549typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2550/** Pointer to a const AMD64 guest page table walk. */
2551typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2552
2553/**
2554 * Guest page table walk for the PAE mode.
2555 */
2556typedef struct PGMPTWALKGSTPAE
2557{
2558 /** The common core. */
2559 PGMPTWALKCORE Core;
2560
2561 PX86PDPT pPdpt;
2562 PX86PDPE pPdpe;
2563 X86PDPE Pdpe;
2564
2565 PX86PDPAE pPd;
2566 PX86PDEPAE pPde;
2567 X86PDEPAE Pde;
2568
2569 PX86PTPAE pPt;
2570 PX86PTEPAE pPte;
2571 X86PTEPAE Pte;
2572} PGMPTWALKGSTPAE;
2573/** Pointer to a PAE guest page table walk. */
2574typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2575/** Pointer to a const AMD64 guest page table walk. */
2576typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2577
2578/**
2579 * Guest page table walk for the 32-bit mode.
2580 */
2581typedef struct PGMPTWALKGST32BIT
2582{
2583 /** The common core. */
2584 PGMPTWALKCORE Core;
2585
2586 PX86PD pPd;
2587 PX86PDE pPde;
2588 X86PDE Pde;
2589
2590 PX86PT pPt;
2591 PX86PTE pPte;
2592 X86PTE Pte;
2593} PGMPTWALKGST32BIT;
2594/** Pointer to a 32-bit guest page table walk. */
2595typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2596/** Pointer to a const 32-bit guest page table walk. */
2597typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2598
2599
2600/** @name Paging mode macros
2601 * @{
2602 */
2603#ifdef IN_RC
2604# define PGM_CTX(a,b) a##RC##b
2605# define PGM_CTX_STR(a,b) a "GC" b
2606# define PGM_CTX_DECL(type) VMMRCDECL(type)
2607#else
2608# ifdef IN_RING3
2609# define PGM_CTX(a,b) a##R3##b
2610# define PGM_CTX_STR(a,b) a "R3" b
2611# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2612# else
2613# define PGM_CTX(a,b) a##R0##b
2614# define PGM_CTX_STR(a,b) a "R0" b
2615# define PGM_CTX_DECL(type) VMMDECL(type)
2616# endif
2617#endif
2618
2619#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2620#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2621#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2622#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2623#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2624#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2625#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2626#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2627#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2628#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2629#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2630#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2631#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2632#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2633#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2634#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2635#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2636
2637#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2638#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2639#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2640#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2641#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2642#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2643#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2644#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2645#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2646#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2647#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2648#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2649#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2650#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2651#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2652#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2653#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2654
2655/* Shw_Gst */
2656#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2657#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2658#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2659#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2660#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2661#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2662#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2663#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2664#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2665#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2666#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2667#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2668#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2669#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2670#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2671#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2672#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2673#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2674#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2675
2676#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2677#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2678#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2679#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2680#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2681#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2682#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2683#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2684#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2685#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2686#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2687#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2688#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2689#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2690#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2691#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2692#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2693#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2694#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2695#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2696#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2697#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2698#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2699#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2700#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2701#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2702#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2703#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2704#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2705#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2706#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2707#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2708#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2709#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2710#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2711#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2712#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2713
2714#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2715#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2716/** @} */
2717
2718/**
2719 * Data for each paging mode.
2720 */
2721typedef struct PGMMODEDATA
2722{
2723 /** The guest mode type. */
2724 uint32_t uGstType;
2725 /** The shadow mode type. */
2726 uint32_t uShwType;
2727
2728 /** @name Function pointers for Shadow paging.
2729 * @{
2730 */
2731 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2732 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2733 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2734 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2735
2736 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2737 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2738
2739 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2740 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2741 /** @} */
2742
2743 /** @name Function pointers for Guest paging.
2744 * @{
2745 */
2746 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2747 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2748 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2749 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2750 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2751 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2752 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2753 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2754 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2755 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2756 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2757 /** @} */
2758
2759 /** @name Function pointers for Both Shadow and Guest paging.
2760 * @{
2761 */
2762 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2763 /* no pfnR3BthTrap0eHandler */
2764 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2765 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2766 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2767 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2768#ifdef VBOX_STRICT
2769 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2770#endif
2771 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2772 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2773
2774 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2775 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2776 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2777 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2778 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2779#ifdef VBOX_STRICT
2780 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2781#endif
2782 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2783 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2784
2785 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2786 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2787 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2788 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2789 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2790#ifdef VBOX_STRICT
2791 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2792#endif
2793 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2794 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2795 /** @} */
2796} PGMMODEDATA, *PPGMMODEDATA;
2797
2798
2799#ifdef VBOX_WITH_STATISTICS
2800/**
2801 * PGM statistics.
2802 *
2803 * These lives on the heap when compiled in as they would otherwise waste
2804 * unnecessary space in release builds.
2805 */
2806typedef struct PGMSTATS
2807{
2808 /* R3 only: */
2809 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2810 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2811
2812 /* R3+RZ */
2813 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2814 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2815 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2816 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2817 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2818 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2819 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2820 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2821 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2822 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2823 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2824 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2825 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2826 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2827 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2828 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2829 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2830 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2831 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2832 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2833 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2834 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2835 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2836 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2837 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2838 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2839 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2840 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2841/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2842 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2843 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2844/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2845
2846 /* RC only: */
2847 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2848 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2849
2850 STAMCOUNTER StatRZPhysRead;
2851 STAMCOUNTER StatRZPhysReadBytes;
2852 STAMCOUNTER StatRZPhysWrite;
2853 STAMCOUNTER StatRZPhysWriteBytes;
2854 STAMCOUNTER StatR3PhysRead;
2855 STAMCOUNTER StatR3PhysReadBytes;
2856 STAMCOUNTER StatR3PhysWrite;
2857 STAMCOUNTER StatR3PhysWriteBytes;
2858 STAMCOUNTER StatRCPhysRead;
2859 STAMCOUNTER StatRCPhysReadBytes;
2860 STAMCOUNTER StatRCPhysWrite;
2861 STAMCOUNTER StatRCPhysWriteBytes;
2862
2863 STAMCOUNTER StatRZPhysSimpleRead;
2864 STAMCOUNTER StatRZPhysSimpleReadBytes;
2865 STAMCOUNTER StatRZPhysSimpleWrite;
2866 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2867 STAMCOUNTER StatR3PhysSimpleRead;
2868 STAMCOUNTER StatR3PhysSimpleReadBytes;
2869 STAMCOUNTER StatR3PhysSimpleWrite;
2870 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2871 STAMCOUNTER StatRCPhysSimpleRead;
2872 STAMCOUNTER StatRCPhysSimpleReadBytes;
2873 STAMCOUNTER StatRCPhysSimpleWrite;
2874 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2875
2876 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2877 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2878 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2879 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2880 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2881 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2882 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2883
2884 /** Time spent by the host OS for large page allocation. */
2885 STAMPROFILE StatAllocLargePage;
2886 /** Time spent clearing the newly allocated large pages. */
2887 STAMPROFILE StatClearLargePage;
2888 /** The number of times allocating a large pages takes more than the allowed period. */
2889 STAMCOUNTER StatLargePageOverflow;
2890 /** pgmPhysIsValidLargePage profiling - R3 */
2891 STAMPROFILE StatR3IsValidLargePage;
2892 /** pgmPhysIsValidLargePage profiling - RZ*/
2893 STAMPROFILE StatRZIsValidLargePage;
2894
2895 STAMPROFILE StatChunkAging;
2896 STAMPROFILE StatChunkFindCandidate;
2897 STAMPROFILE StatChunkUnmap;
2898 STAMPROFILE StatChunkMap;
2899} PGMSTATS;
2900#endif /* VBOX_WITH_STATISTICS */
2901
2902
2903/**
2904 * Converts a PGM pointer into a VM pointer.
2905 * @returns Pointer to the VM structure the PGM is part of.
2906 * @param pPGM Pointer to PGM instance data.
2907 */
2908#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2909
2910/**
2911 * PGM Data (part of VM)
2912 */
2913typedef struct PGM
2914{
2915 /** Offset to the VM structure. */
2916 int32_t offVM;
2917 /** Offset of the PGMCPU structure relative to VMCPU. */
2918 int32_t offVCpuPGM;
2919
2920 /** @cfgm{RamPreAlloc, boolean, false}
2921 * Indicates whether the base RAM should all be allocated before starting
2922 * the VM (default), or if it should be allocated when first written to.
2923 */
2924 bool fRamPreAlloc;
2925 /** Indicates whether write monitoring is currently in use.
2926 * This is used to prevent conflicts between live saving and page sharing
2927 * detection. */
2928 bool fPhysWriteMonitoringEngaged;
2929 /** Set if the CPU has less than 52-bit physical address width.
2930 * This is used */
2931 bool fLessThan52PhysicalAddressBits;
2932 /** Set when nested paging is active.
2933 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2934 * compilers optimize the code better. Whether we use nested paging or
2935 * not is something we find out during VMM initialization and we won't
2936 * change this later on. */
2937 bool fNestedPaging;
2938 /** The host paging mode. (This is what SUPLib reports.) */
2939 SUPPAGINGMODE enmHostMode;
2940 /** We're not in a state which permits writes to guest memory.
2941 * (Only used in strict builds.) */
2942 bool fNoMorePhysWrites;
2943 /** Set if PCI passthrough is enabled. */
2944 bool fPciPassthrough;
2945 /** Alignment padding that makes the next member start on a 8 byte boundary. */
2946 bool afAlignment1[2];
2947
2948 /** Indicates that PGMR3FinalizeMappings has been called and that further
2949 * PGMR3MapIntermediate calls will be rejected. */
2950 bool fFinalizedMappings;
2951 /** If set no conflict checks are required. */
2952 bool fMappingsFixed;
2953 /** If set if restored as fixed but we were unable to re-fixate at the old
2954 * location because of room or address incompatibilities. */
2955 bool fMappingsFixedRestored;
2956 /** If set, then no mappings are put into the shadow page table.
2957 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2958 bool fMappingsDisabled;
2959 /** Size of fixed mapping.
2960 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2961 uint32_t cbMappingFixed;
2962 /** Generation ID for the RAM ranges. This member is incremented everytime
2963 * a RAM range is linked or unlinked. */
2964 uint32_t volatile idRamRangesGen;
2965
2966 /** Base address (GC) of fixed mapping.
2967 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2968 RTGCPTR GCPtrMappingFixed;
2969 /** The address of the previous RAM range mapping. */
2970 RTGCPTR GCPtrPrevRamRangeMapping;
2971
2972 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2973 RTGCPHYS GCPhys4MBPSEMask;
2974 /** Mask containing the invalid bits of a guest physical address.
2975 * @remarks this does not stop at bit 52. */
2976 RTGCPHYS GCPhysInvAddrMask;
2977
2978
2979 /** RAM range TLB for R3. */
2980 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2981 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2982 * This is sorted by physical address and contains no overlapping ranges. */
2983 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2984 /** Root of the RAM range search tree for ring-3. */
2985 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2986 /** PGM offset based trees - R3 Ptr. */
2987 R3PTRTYPE(PPGMTREES) pTreesR3;
2988 /** Caching the last physical handler we looked up in R3. */
2989 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2990 /** Shadow Page Pool - R3 Ptr. */
2991 R3PTRTYPE(PPGMPOOL) pPoolR3;
2992 /** Linked list of GC mappings - for HC.
2993 * The list is sorted ascending on address. */
2994 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2995 /** Pointer to the list of ROM ranges - for R3.
2996 * This is sorted by physical address and contains no overlapping ranges. */
2997 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2998 /** Pointer to the list of MMIO2 ranges - for R3.
2999 * Registration order. */
3000 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3001 /** Pointer to SHW+GST mode data (function pointers).
3002 * The index into this table is made up from */
3003 R3PTRTYPE(PPGMMODEDATA) paModeData;
3004 RTR3PTR R3PtrAlignment0;
3005
3006 /** RAM range TLB for R0. */
3007 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3008 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3009 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3010 /** Root of the RAM range search tree for ring-0. */
3011 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3012 /** PGM offset based trees - R0 Ptr. */
3013 R0PTRTYPE(PPGMTREES) pTreesR0;
3014 /** Caching the last physical handler we looked up in R0. */
3015 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3016 /** Shadow Page Pool - R0 Ptr. */
3017 R0PTRTYPE(PPGMPOOL) pPoolR0;
3018 /** Linked list of GC mappings - for R0.
3019 * The list is sorted ascending on address. */
3020 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3021 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3022 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3023 RTR0PTR R0PtrAlignment0;
3024
3025
3026 /** RAM range TLB for RC. */
3027 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3028 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3029 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3030 /** Root of the RAM range search tree for raw-mode context. */
3031 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3032 /** PGM offset based trees - RC Ptr. */
3033 RCPTRTYPE(PPGMTREES) pTreesRC;
3034 /** Caching the last physical handler we looked up in RC. */
3035 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3036 /** Shadow Page Pool - RC Ptr. */
3037 RCPTRTYPE(PPGMPOOL) pPoolRC;
3038 /** Linked list of GC mappings - for RC.
3039 * The list is sorted ascending on address. */
3040 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3041 /** RC pointer corresponding to PGM::pRomRangesR3. */
3042 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3043 RTRCPTR RCPtrAlignment0;
3044 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3045 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3046 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3047 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3048
3049
3050 /** Pointer to the 5 page CR3 content mapping.
3051 * The first page is always the CR3 (in some form) while the 4 other pages
3052 * are used of the PDs in PAE mode. */
3053 RTGCPTR GCPtrCR3Mapping;
3054
3055 /** @name Intermediate Context
3056 * @{ */
3057 /** Pointer to the intermediate page directory - Normal. */
3058 R3PTRTYPE(PX86PD) pInterPD;
3059 /** Pointer to the intermediate page tables - Normal.
3060 * There are two page tables, one for the identity mapping and one for
3061 * the host context mapping (of the core code). */
3062 R3PTRTYPE(PX86PT) apInterPTs[2];
3063 /** Pointer to the intermediate page tables - PAE. */
3064 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3065 /** Pointer to the intermediate page directory - PAE. */
3066 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3067 /** Pointer to the intermediate page directory - PAE. */
3068 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3069 /** Pointer to the intermediate page-map level 4 - AMD64. */
3070 R3PTRTYPE(PX86PML4) pInterPaePML4;
3071 /** Pointer to the intermediate page directory - AMD64. */
3072 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3073 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3074 RTHCPHYS HCPhysInterPD;
3075 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3076 RTHCPHYS HCPhysInterPaePDPT;
3077 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3078 RTHCPHYS HCPhysInterPaePML4;
3079 /** @} */
3080
3081 /** Base address of the dynamic page mapping area.
3082 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3083 *
3084 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3085 * work out. Some cleaning up of the initialization that would
3086 * remove this memory is yet to be done...
3087 */
3088 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3089 /** The address of the raw-mode context mapping cache. */
3090 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3091 /** The address of the ring-0 mapping cache if we're making use of it. */
3092 RTR0PTR pvR0DynMapUsed;
3093#if HC_ARCH_BITS == 32
3094 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3095 uint32_t u32Alignment2;
3096#endif
3097
3098 /** PGM critical section.
3099 * This protects the physical & virtual access handlers, ram ranges,
3100 * and the page flag updating (some of it anyway).
3101 */
3102 PDMCRITSECT CritSect;
3103
3104 /**
3105 * Data associated with managing the ring-3 mappings of the allocation chunks.
3106 */
3107 struct
3108 {
3109 /** The chunk tree, ordered by chunk id. */
3110#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3111 R3PTRTYPE(PAVLU32NODECORE) pTree;
3112#else
3113 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3114#endif
3115#if HC_ARCH_BITS == 32
3116 uint32_t u32Alignment;
3117#endif
3118 /** The chunk mapping TLB. */
3119 PGMCHUNKR3MAPTLB Tlb;
3120 /** The number of mapped chunks. */
3121 uint32_t c;
3122 /** The maximum number of mapped chunks.
3123 * @cfgm PGM/MaxRing3Chunks */
3124 uint32_t cMax;
3125 /** The current time. */
3126 uint32_t iNow;
3127 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3128 uint32_t AgeingCountdown;
3129 } ChunkR3Map;
3130
3131 /**
3132 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3133 */
3134 PGMPAGER3MAPTLB PhysTlbHC;
3135
3136 /** @name The zero page.
3137 * @{ */
3138 /** The host physical address of the zero page. */
3139 RTHCPHYS HCPhysZeroPg;
3140 /** The ring-3 mapping of the zero page. */
3141 RTR3PTR pvZeroPgR3;
3142 /** The ring-0 mapping of the zero page. */
3143 RTR0PTR pvZeroPgR0;
3144 /** The GC mapping of the zero page. */
3145 RTRCPTR pvZeroPgRC;
3146 RTRCPTR RCPtrAlignment3;
3147 /** @}*/
3148
3149 /** @name The Invalid MMIO page.
3150 * This page is filled with 0xfeedface.
3151 * @{ */
3152 /** The host physical address of the invalid MMIO page. */
3153 RTHCPHYS HCPhysMmioPg;
3154 /** The host pysical address of the invalid MMIO page plus all invalid
3155 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3156 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3157 RTHCPHYS HCPhysInvMmioPg;
3158 /** The ring-3 mapping of the invalid MMIO page. */
3159 RTR3PTR pvMmioPgR3;
3160#if HC_ARCH_BITS == 32
3161 RTR3PTR R3PtrAlignment4;
3162#endif
3163 /** @} */
3164
3165
3166 /** The number of handy pages. */
3167 uint32_t cHandyPages;
3168
3169 /** The number of large handy pages. */
3170 uint32_t cLargeHandyPages;
3171
3172 /**
3173 * Array of handy pages.
3174 *
3175 * This array is used in a two way communication between pgmPhysAllocPage
3176 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3177 * an intermediary.
3178 *
3179 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3180 * (The current size of 32 pages, means 128 KB of handy memory.)
3181 */
3182 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3183
3184 /**
3185 * Array of large handy pages. (currently size 1)
3186 *
3187 * This array is used in a two way communication between pgmPhysAllocLargePage
3188 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3189 * an intermediary.
3190 */
3191 GMMPAGEDESC aLargeHandyPage[1];
3192
3193 /**
3194 * Live save data.
3195 */
3196 struct
3197 {
3198 /** Per type statistics. */
3199 struct
3200 {
3201 /** The number of ready pages. */
3202 uint32_t cReadyPages;
3203 /** The number of dirty pages. */
3204 uint32_t cDirtyPages;
3205 /** The number of ready zero pages. */
3206 uint32_t cZeroPages;
3207 /** The number of write monitored pages. */
3208 uint32_t cMonitoredPages;
3209 } Rom,
3210 Mmio2,
3211 Ram;
3212 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3213 uint32_t cIgnoredPages;
3214 /** Indicates that a live save operation is active. */
3215 bool fActive;
3216 /** Padding. */
3217 bool afReserved[2];
3218 /** The next history index. */
3219 uint8_t iDirtyPagesHistory;
3220 /** History of the total amount of dirty pages. */
3221 uint32_t acDirtyPagesHistory[64];
3222 /** Short term dirty page average. */
3223 uint32_t cDirtyPagesShort;
3224 /** Long term dirty page average. */
3225 uint32_t cDirtyPagesLong;
3226 /** The number of saved pages. This is used to get some kind of estimate of the
3227 * link speed so we can decide when we're done. It is reset after the first
3228 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3229 * zero pages. */
3230 uint64_t cSavedPages;
3231 /** The nanosecond timestamp when cSavedPages was 0. */
3232 uint64_t uSaveStartNS;
3233 /** Pages per second (for statistics). */
3234 uint32_t cPagesPerSecond;
3235 uint32_t cAlignment;
3236 } LiveSave;
3237
3238 /** @name Error injection.
3239 * @{ */
3240 /** Inject handy page allocation errors pretending we're completely out of
3241 * memory. */
3242 bool volatile fErrInjHandyPages;
3243 /** Padding. */
3244 bool afReserved[3];
3245 /** @} */
3246
3247 /** @name Release Statistics
3248 * @{ */
3249 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3250 uint32_t cPrivatePages; /**< The number of private pages. */
3251 uint32_t cSharedPages; /**< The number of shared pages. */
3252 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3253 uint32_t cZeroPages; /**< The number of zero backed pages. */
3254 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3255 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3256 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3257 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3258 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3259 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3260 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3261 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3262 uint32_t cLargePages; /**< The number of large pages. */
3263 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3264/* uint32_t aAlignment4[1]; */
3265
3266 /** The number of times we were forced to change the hypervisor region location. */
3267 STAMCOUNTER cRelocations;
3268
3269 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3270 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3271 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3272 /** @} */
3273
3274#ifdef VBOX_WITH_STATISTICS
3275 /** @name Statistics on the heap.
3276 * @{ */
3277 R3PTRTYPE(PGMSTATS *) pStatsR3;
3278 R0PTRTYPE(PGMSTATS *) pStatsR0;
3279 RCPTRTYPE(PGMSTATS *) pStatsRC;
3280 RTRCPTR RCPtrAlignment;
3281 /** @} */
3282#endif
3283} PGM;
3284#ifndef IN_TSTVMSTRUCTGC /* HACK */
3285AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3286AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3287AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3288AssertCompileMemberAlignment(PGM, CritSect, 8);
3289AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3290AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3291AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3292AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3293AssertCompileMemberAlignment(PGM, cRelocations, 8);
3294#endif /* !IN_TSTVMSTRUCTGC */
3295/** Pointer to the PGM instance data. */
3296typedef PGM *PPGM;
3297
3298
3299
3300typedef struct PGMCPUSTATS
3301{
3302 /* Common */
3303 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3304 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3305
3306 /* R0 only: */
3307 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3308 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3309
3310 /* RZ only: */
3311 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3312 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3313 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3314 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3315 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3316 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3317 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3318 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3319 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3320 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3321 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3322 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3323 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3324 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3325 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3326 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3327 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3328 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3329 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3330 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3331 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3332 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3333 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3334 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3335 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3336 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3337 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3338 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3339 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3340 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3341 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3342 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3343 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3344 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3345 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3346 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3347 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3348 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3349 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3350 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3351 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3352 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3353 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3354 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3355 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3356 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3357 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3358 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3359 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3360 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3361 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3362 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3363 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3364 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3365 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3366 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3367 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3368 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3369 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3370 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3371 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3372 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3373 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3374 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3375 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3376 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3377 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3378 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3379 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3380 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3381 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3382 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3383 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3384 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3385 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3386 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3387
3388 /* HC - R3 and (maybe) R0: */
3389
3390 /* RZ & R3: */
3391 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3392 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3393 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3394 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3395 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3396 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3397 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3398 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3399 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3400 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3401 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3402 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3403 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3404 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3405 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3406 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3407 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3408 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3409 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3410 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3411 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3412 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3413 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3414 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3415 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3416 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3417 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3418 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3419 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3420 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3421 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3422 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3423 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3424 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3425 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3426 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3427 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3428 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3429 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3430 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3431 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3432 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3433 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3434 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3435 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3436 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3437 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3438
3439 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3440 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3441 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3442 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3443 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3444 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3445 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3446 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3447 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3448 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3449 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3450 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3451 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3452 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3453 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3454 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3455 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3456 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3457 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3458 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3459 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3460 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3461 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3462 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3463 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3464 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3465 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3466 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3467 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3468 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3469 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3470 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3471 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3472 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3473 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3474 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3475 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3476 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3477 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3478 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3479 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3480 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3481 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3482 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3483 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3484 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3485 /** @} */
3486} PGMCPUSTATS;
3487
3488
3489/**
3490 * Converts a PGMCPU pointer into a VM pointer.
3491 * @returns Pointer to the VM structure the PGM is part of.
3492 * @param pPGM Pointer to PGMCPU instance data.
3493 */
3494#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3495
3496/**
3497 * Converts a PGMCPU pointer into a PGM pointer.
3498 * @returns Pointer to the VM structure the PGM is part of.
3499 * @param pPGM Pointer to PGMCPU instance data.
3500 */
3501#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3502
3503/**
3504 * PGMCPU Data (part of VMCPU).
3505 */
3506typedef struct PGMCPU
3507{
3508 /** Offset to the VM structure. */
3509 int32_t offVM;
3510 /** Offset to the VMCPU structure. */
3511 int32_t offVCpu;
3512 /** Offset of the PGM structure relative to VMCPU. */
3513 int32_t offPGM;
3514 uint32_t uPadding0; /**< structure size alignment. */
3515
3516#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3517 /** Automatically tracked physical memory mapping set.
3518 * Ring-0 and strict raw-mode builds. */
3519 PGMMAPSET AutoSet;
3520#endif
3521
3522 /** A20 gate mask.
3523 * Our current approach to A20 emulation is to let REM do it and don't bother
3524 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3525 * But whould need arrise, we'll subject physical addresses to this mask. */
3526 RTGCPHYS GCPhysA20Mask;
3527 /** A20 gate state - boolean! */
3528 bool fA20Enabled;
3529 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3530 bool fNoExecuteEnabled;
3531 /** Unused bits. */
3532 bool afUnused[2];
3533
3534 /** What needs syncing (PGM_SYNC_*).
3535 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3536 * PGMFlushTLB, and PGMR3Load. */
3537 RTUINT fSyncFlags;
3538
3539 /** The shadow paging mode. */
3540 PGMMODE enmShadowMode;
3541 /** The guest paging mode. */
3542 PGMMODE enmGuestMode;
3543
3544 /** The current physical address representing in the guest CR3 register. */
3545 RTGCPHYS GCPhysCR3;
3546
3547 /** @name 32-bit Guest Paging.
3548 * @{ */
3549 /** The guest's page directory, R3 pointer. */
3550 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3551#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3552 /** The guest's page directory, R0 pointer. */
3553 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3554#endif
3555 /** The guest's page directory, static RC mapping. */
3556 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3557 /** Mask containing the MBZ bits of a big page PDE. */
3558 uint32_t fGst32BitMbzBigPdeMask;
3559 /** Set if the page size extension (PSE) is enabled. */
3560 bool fGst32BitPageSizeExtension;
3561 /** Alignment padding. */
3562 bool afAlignment2[3];
3563 /** @} */
3564
3565 /** @name PAE Guest Paging.
3566 * @{ */
3567 /** The guest's page directory pointer table, static RC mapping. */
3568 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3569 /** The guest's page directory pointer table, R3 pointer. */
3570 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3571#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3572 /** The guest's page directory pointer table, R0 pointer. */
3573 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3574#endif
3575
3576 /** The guest's page directories, R3 pointers.
3577 * These are individual pointers and don't have to be adjacent.
3578 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3579 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3580 /** The guest's page directories, R0 pointers.
3581 * Same restrictions as apGstPaePDsR3. */
3582#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3583 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3584#endif
3585 /** The guest's page directories, static GC mapping.
3586 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3587 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3588 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3589 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3590 RTGCPHYS aGCPhysGstPaePDs[4];
3591 /** The physical addresses of the monitored guest page directories (PAE). */
3592 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3593 /** Mask containing the MBZ PTE bits. */
3594 uint64_t fGstPaeMbzPteMask;
3595 /** Mask containing the MBZ PDE bits. */
3596 uint64_t fGstPaeMbzPdeMask;
3597 /** Mask containing the MBZ big page PDE bits. */
3598 uint64_t fGstPaeMbzBigPdeMask;
3599 /** Mask containing the MBZ PDPE bits. */
3600 uint64_t fGstPaeMbzPdpeMask;
3601 /** @} */
3602
3603 /** @name AMD64 Guest Paging.
3604 * @{ */
3605 /** The guest's page directory pointer table, R3 pointer. */
3606 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3607#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3608 /** The guest's page directory pointer table, R0 pointer. */
3609 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3610#else
3611 RTR0PTR alignment6b; /**< alignment equalizer. */
3612#endif
3613 /** Mask containing the MBZ PTE bits. */
3614 uint64_t fGstAmd64MbzPteMask;
3615 /** Mask containing the MBZ PDE bits. */
3616 uint64_t fGstAmd64MbzPdeMask;
3617 /** Mask containing the MBZ big page PDE bits. */
3618 uint64_t fGstAmd64MbzBigPdeMask;
3619 /** Mask containing the MBZ PDPE bits. */
3620 uint64_t fGstAmd64MbzPdpeMask;
3621 /** Mask containing the MBZ big page PDPE bits. */
3622 uint64_t fGstAmd64MbzBigPdpeMask;
3623 /** Mask containing the MBZ PML4E bits. */
3624 uint64_t fGstAmd64MbzPml4eMask;
3625 /** Mask containing the PDPE bits that we shadow. */
3626 uint64_t fGstAmd64ShadowedPdpeMask;
3627 /** Mask containing the PML4E bits that we shadow. */
3628 uint64_t fGstAmd64ShadowedPml4eMask;
3629 /** @} */
3630
3631 /** @name PAE and AMD64 Guest Paging.
3632 * @{ */
3633 /** Mask containing the PTE bits that we shadow. */
3634 uint64_t fGst64ShadowedPteMask;
3635 /** Mask containing the PDE bits that we shadow. */
3636 uint64_t fGst64ShadowedPdeMask;
3637 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3638 uint64_t fGst64ShadowedBigPdeMask;
3639 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3640 uint64_t fGst64ShadowedBigPde4PteMask;
3641 /** @} */
3642
3643 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3644 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3645 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3646 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3647 /** Pointer to the page of the current active CR3 - RC Ptr. */
3648 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3649 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3650 uint32_t iShwUser;
3651 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3652 uint32_t iShwUserTable;
3653# if HC_ARCH_BITS == 64
3654 RTRCPTR alignment6; /**< structure size alignment. */
3655# endif
3656 /** @} */
3657
3658 /** @name Function pointers for Shadow paging.
3659 * @{
3660 */
3661 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3662 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3663 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3664 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3665
3666 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3667 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3668
3669 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3670 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3671
3672 /** @} */
3673
3674 /** @name Function pointers for Guest paging.
3675 * @{
3676 */
3677 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3678 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3679 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3680 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3681 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3682 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3683 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3684 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3685#if HC_ARCH_BITS == 64
3686 RTRCPTR alignment3; /**< structure size alignment. */
3687#endif
3688
3689 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3690 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3691 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3692 /** @} */
3693
3694 /** @name Function pointers for Both Shadow and Guest paging.
3695 * @{
3696 */
3697 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3698 /* no pfnR3BthTrap0eHandler */
3699 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3700 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3701 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3702 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3703 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3704 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3705 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3706
3707 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3708 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3709 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3710 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3711 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3712 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3713 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3714 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3715
3716 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3717 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3718 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3719 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3720 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3721 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3722 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3723 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3724#if 0
3725 RTRCPTR alignment2; /**< structure size alignment. */
3726#endif
3727 /** @} */
3728
3729 /** For saving stack space, the disassembler state is allocated here instead of
3730 * on the stack.
3731 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3732 union
3733 {
3734 /** The disassembler scratch space. */
3735 DISCPUSTATE DisState;
3736 /** Padding. */
3737 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3738 };
3739
3740 /** Count the number of pgm pool access handler calls. */
3741 uint64_t cPoolAccessHandler;
3742
3743 /** @name Release Statistics
3744 * @{ */
3745 /** The number of times the guest has switched mode since last reset or statistics reset. */
3746 STAMCOUNTER cGuestModeChanges;
3747 /** @} */
3748
3749#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3750 /** @name Statistics
3751 * @{ */
3752 /** RC: Pointer to the statistics. */
3753 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3754 /** RC: Which statistic this \#PF should be attributed to. */
3755 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3756 /** R0: Pointer to the statistics. */
3757 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3758 /** R0: Which statistic this \#PF should be attributed to. */
3759 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3760 /** R3: Pointer to the statistics. */
3761 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3762 /** Alignment padding. */
3763 RTR3PTR pPaddingR3;
3764 /** @} */
3765#endif /* VBOX_WITH_STATISTICS */
3766} PGMCPU;
3767/** Pointer to the per-cpu PGM data. */
3768typedef PGMCPU *PPGMCPU;
3769
3770
3771/** @name PGM::fSyncFlags Flags
3772 * @{
3773 */
3774/** Updates the virtual access handler state bit in PGMPAGE. */
3775#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3776/** Always sync CR3. */
3777#define PGM_SYNC_ALWAYS RT_BIT(1)
3778/** Check monitoring on next CR3 (re)load and invalidate page.
3779 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3780#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3781/** Check guest mapping in SyncCR3. */
3782#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3783/** Clear the page pool (a light weight flush). */
3784#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3785#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3786/** @} */
3787
3788
3789RT_C_DECLS_BEGIN
3790
3791int pgmLock(PVM pVM);
3792void pgmUnlock(PVM pVM);
3793
3794int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3795int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3796int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3797PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3798int pgmMapResolveConflicts(PVM pVM);
3799DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3800
3801void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3802bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3803void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3804int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3805DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3806#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3807void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3808#else
3809# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3810#endif
3811DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3812int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3813
3814int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3815int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3816int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3817int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
3818int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3819void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3820int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3821int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3822int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3823int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3824int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3825int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3826int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3827VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3828VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3829int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3830void pgmPhysInvalidRamRangeTlbs(PVM pVM);
3831PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3832PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3833PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3834int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3835int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3836
3837#ifdef IN_RING3
3838void pgmR3PhysRelinkRamRanges(PVM pVM);
3839int pgmR3PhysRamPreAllocate(PVM pVM);
3840int pgmR3PhysRamReset(PVM pVM);
3841int pgmR3PhysRomReset(PVM pVM);
3842int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3843int pgmR3PhysRamTerm(PVM pVM);
3844void pgmR3PhysRomTerm(PVM pVM);
3845
3846int pgmR3PoolInit(PVM pVM);
3847void pgmR3PoolRelocate(PVM pVM);
3848void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3849void pgmR3PoolReset(PVM pVM);
3850void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3851DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3852void pgmR3PoolWriteProtectPages(PVM pVM);
3853
3854#endif /* IN_RING3 */
3855#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3856int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3857int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3858# ifdef LOG_ENABLED
3859void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3860# else
3861void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3862# endif
3863#endif
3864int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3865 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3866
3867DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3868 PPPGMPOOLPAGE ppPage)
3869{
3870 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3871}
3872
3873void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3874void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3875int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3876void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3877PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3878PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3879int pgmPoolSyncCR3(PVMCPU pVCpu);
3880bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3881void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3882int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3883void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3884uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3885void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3886void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3887int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3888void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3889
3890void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3891void pgmPoolResetDirtyPages(PVM pVM);
3892void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3893
3894int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3895int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3896
3897void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3898void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3899int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3900int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3901
3902int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3903int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3904
3905int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3906int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3907int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3908int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3909
3910# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3911DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3912DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3913# endif
3914
3915RT_C_DECLS_END
3916
3917/** @} */
3918
3919#endif
3920
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