PGMInternal.h@ 55909

Last change on this file since 55909 was 55909, checked in by vboxsync, 10 years ago
PGM,++: Made the ring-3 physical access handler callbacks present in all contexts, where applicable. They are not yet registered or used. Taking things slowly.
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File size: 192.2 KB

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1	/* $Id: PGMInternal.h 55909 2015-05-18 13:09:16Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/list-off32.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings in the shadow tables.
60	*
61	* Note! In ring-3 the macro is also used to exclude the managment of the
62	* intermediate context page tables. On 32-bit systems we use the intermediate
63	* context to support 64-bit guest execution. Thus, we cannot fully make it
64	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
65	*
66	* In raw-mode context there are by design always guest mappings (the code is
67	* executed from one), while in ring-0 there are none at all. Neither context
68	* manages the page tables for intermediate switcher context, that's all done in
69	* ring-3.
70	*
71	* On 32-bit darwin (hybrid kernel) we do 64-bit guest support differently, so
72	* there we can safely work without mappings if we don't compile in raw-mode.
73	*/
74	#if defined(IN_RING0) \
75	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
76	&& ( HC_ARCH_BITS != 32 \
77	\|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# define PGM_WITHOUT_MAPPINGS
82	#endif
83
84	/**
85	* Check and skip global PDEs for non-global flushes
86	*/
87	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
88
89	/**
90	* Optimization for PAE page tables that are modified often
91	*/
92	//#if 0 /* disabled again while debugging */
93	#ifndef IN_RC
94	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	#endif
96	//#endif
97
98	/**
99	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
100	*/
101	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
102	# define PGM_WITH_LARGE_PAGES
103	#endif
104
105	/**
106	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
107	* VMX_EXIT_EPT_MISCONFIG.
108	*/
109	#if 1 /* testing */
110	# define PGM_WITH_MMIO_OPTIMIZATIONS
111	#endif
112
113	/**
114	* Sync N pages instead of a whole page table
115	*/
116	#define PGM_SYNC_N_PAGES
117
118	/**
119	* Number of pages to sync during a page fault
120	*
121	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
122	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
123	*
124	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
125	* world switch overhead, so let's sync more.
126	*/
127	# ifdef IN_RING0
128	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
129	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
130	* but ~5% fewer faults.
131	*/
132	# define PGM_SYNC_NR_PAGES 32
133	#else
134	# define PGM_SYNC_NR_PAGES 8
135	#endif
136
137	/**
138	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
139	*/
140	#define PGM_MAX_PHYSCACHE_ENTRIES 64
141	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
142
143
144	/** @def PGMPOOL_CFG_MAX_GROW
145	* The maximum number of pages to add to the pool in one go.
146	*/
147	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
148
149	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
150	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
151	*/
152	#ifdef VBOX_STRICT
153	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
154	#endif
155
156	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
157	* Enables the experimental lazy page allocation code. */
158	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
159
160	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161	* Enables real write monitoring of pages, i.e. mapping them read-only and
162	* only making them writable when getting a write access #PF. */
163	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165	/** @} */
166
167
168	/** @name PDPT and PML4 flags.
169	* These are placed in the three bits available for system programs in
170	* the PDPT and PML4 entries.
171	* @{ */
172	/** The entry is a permanent one and it's must always be present.
173	* Never free such an entry. */
174	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175	/** Mapping (hypervisor allocated pagetable). */
176	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED 6
213	#define PGM_TYPE_EPT 7
214	#define PGM_TYPE_MAX PGM_TYPE_EPT
215	/** @} */
216
217	/** Macro for checking if the guest is using paging.
218	* @param uGstType PGM_TYPE_*
219	* @param uShwType PGM_TYPE_*
220	* @remark ASSUMES certain order of the PGM_TYPE_* values.
221	*/
222	#define PGM_WITH_PAGING(uGstType, uShwType) \
223	( (uGstType) >= PGM_TYPE_32BIT \
224	&& (uShwType) != PGM_TYPE_NESTED \
225	&& (uShwType) != PGM_TYPE_EPT)
226
227	/** Macro for checking if the guest supports the NX bit.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_NX(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_PAE \
234	&& (uShwType) != PGM_TYPE_NESTED \
235	&& (uShwType) != PGM_TYPE_EPT)
236
237
238	/** @def PGM_HCPHYS_2_PTR
239	* Maps a HC physical page pool address to a virtual address.
240	*
241	* @returns VBox status code.
242	* @param pVM Pointer to the VM.
243	* @param pVCpu The current CPU.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast
246	* this.
247	*
248	* @remark Use with care as we don't have so much dynamic mapping space in
249	* ring-0 on 32-bit darwin and in RC.
250	* @remark There is no need to assert on the result.
251	*/
252	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
253	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
255	#else
256	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
257	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
258	#endif
259
260	/** @def PGM_GCPHYS_2_PTR_V2
261	* Maps a GC physical page address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM Pointer to the VM.
265	* @param pVCpu The current CPU.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark Use with care as we don't have so much dynamic mapping space in
270	* ring-0 on 32-bit darwin and in RC.
271	* @remark There is no need to assert on the result.
272	*/
273	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
274	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
276	#else
277	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
278	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
279	#endif
280
281	/** @def PGM_GCPHYS_2_PTR
282	* Maps a GC physical page address to a virtual address.
283	*
284	* @returns VBox status code.
285	* @param pVM Pointer to the VM.
286	* @param GCPhys The GC physical address to map to a virtual one.
287	* @param ppv Where to store the virtual address. No need to cast this.
288	*
289	* @remark Use with care as we don't have so much dynamic mapping space in
290	* ring-0 on 32-bit darwin and in RC.
291	* @remark There is no need to assert on the result.
292	*/
293	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
294
295	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
296	* Maps a GC physical page address to a virtual address.
297	*
298	* @returns VBox status code.
299	* @param pVCpu The current CPU.
300	* @param GCPhys The GC physical address to map to a virtual one.
301	* @param ppv Where to store the virtual address. No need to cast this.
302	*
303	* @remark Use with care as we don't have so much dynamic mapping space in
304	* ring-0 on 32-bit darwin and in RC.
305	* @remark There is no need to assert on the result.
306	*/
307	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM Pointer to the VM.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark Use with care as we don't have so much dynamic mapping space in
318	* ring-0 on 32-bit darwin and in RC.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327	#endif
328
329	/** @def PGM_DYNMAP_UNUSED_HINT
330	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
331	* is no longer used.
332	*
333	* For best effect only apply this to the page that was mapped most recently.
334	*
335	* @param pVCpu The current CPU.
336	* @param pvPage The pool page.
337	*/
338	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
339	# ifdef LOG_ENABLED
340	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
341	# else
342	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
343	# endif
344	#else
345	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
346	#endif
347
348	/** @def PGM_DYNMAP_UNUSED_HINT_VM
349	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
350	* is no longer used.
351	*
352	* For best effect only apply this to the page that was mapped most recently.
353	*
354	* @param pVM Pointer to the VM.
355	* @param pvPage The pool page.
356	*/
357	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
358
359
360	/** @def PGM_INVL_PG
361	* Invalidates a page.
362	*
363	* @param pVCpu Pointer to the VMCPU.
364	* @param GCVirt The virtual address of the page to invalidate.
365	*/
366	#ifdef IN_RC
367	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
368	#elif defined(IN_RING0)
369	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370	#else
371	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
372	#endif
373
374	/** @def PGM_INVL_PG_ALL_VCPU
375	* Invalidates a page on all VCPUs
376	*
377	* @param pVM Pointer to the VM.
378	* @param GCVirt The virtual address of the page to invalidate.
379	*/
380	#ifdef IN_RC
381	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
382	#elif defined(IN_RING0)
383	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384	#else
385	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
386	#endif
387
388	/** @def PGM_INVL_BIG_PG
389	* Invalidates a 4MB page directory entry.
390	*
391	* @param pVCpu Pointer to the VMCPU.
392	* @param GCVirt The virtual address within the page directory to invalidate.
393	*/
394	#ifdef IN_RC
395	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
396	#elif defined(IN_RING0)
397	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398	#else
399	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
400	#endif
401
402	/** @def PGM_INVL_VCPU_TLBS()
403	* Invalidates the TLBs of the specified VCPU
404	*
405	* @param pVCpu Pointer to the VMCPU.
406	*/
407	#ifdef IN_RC
408	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
409	#elif defined(IN_RING0)
410	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411	#else
412	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
413	#endif
414
415	/** @def PGM_INVL_ALL_VCPU_TLBS()
416	* Invalidates the TLBs of all VCPUs
417	*
418	* @param pVM Pointer to the VM.
419	*/
420	#ifdef IN_RC
421	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
422	#elif defined(IN_RING0)
423	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424	#else
425	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
426	#endif
427
428
429	/** @name Safer Shadow PAE PT/PTE
430	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
431	* present.
432	*
433	* @{
434	*/
435	#if 1
436	/**
437	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
438	* invalid entries for present.
439	* @sa X86PTEPAE.
440	*/
441	typedef union PGMSHWPTEPAE
442	{
443	/** Unsigned integer view */
444	X86PGPAEUINT uCareful;
445	/* Not other views. */
446	} PGMSHWPTEPAE;
447
448	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
449	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
450	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
451	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
452	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
453	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
454	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
455	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
456	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
457	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
458	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
459	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
461	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
462	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
463	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
464
465	/**
466	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
467	* invalid entries for present.
468	* @sa X86PTPAE.
469	*/
470	typedef struct PGMSHWPTPAE
471	{
472	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
473	} PGMSHWPTPAE;
474
475	#else
476	typedef X86PTEPAE PGMSHWPTEPAE;
477	typedef X86PTPAE PGMSHWPTPAE;
478	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
479	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
480	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
481	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
482	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
483	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
484	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
485	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
486	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
487	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
488	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
489	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
491	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
492	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
493	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
494
495	#endif
496
497	/** Pointer to a shadow PAE PTE. */
498	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
499	/** Pointer to a const shadow PAE PTE. */
500	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
501
502	/** Pointer to a shadow PAE page table. */
503	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
504	/** Pointer to a const shadow PAE page table. */
505	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
506	/** @} */
507
508
509	/** Size of the GCPtrConflict array in PGMMAPPING.
510	* @remarks Must be a power of two. */
511	#define PGMMAPPING_CONFLICT_MAX 8
512
513	/**
514	* Structure for tracking GC Mappings.
515	*
516	* This structure is used by linked list in both GC and HC.
517	*/
518	typedef struct PGMMAPPING
519	{
520	/** Pointer to next entry. */
521	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522	/** Pointer to next entry. */
523	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524	/** Pointer to next entry. */
525	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
526	/** Indicate whether this entry is finalized. */
527	bool fFinalized;
528	/** Start Virtual address. */
529	RTGCPTR GCPtr;
530	/** Last Virtual address (inclusive). */
531	RTGCPTR GCPtrLast;
532	/** Range size (bytes). */
533	RTGCPTR cb;
534	/** Pointer to relocation callback function. */
535	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
536	/** User argument to the callback. */
537	R3PTRTYPE(void *) pvUser;
538	/** Mapping description / name. For easing debugging. */
539	R3PTRTYPE(const char *) pszDesc;
540	/** Last 8 addresses that caused conflicts. */
541	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
542	/** Number of conflicts for this hypervisor mapping. */
543	uint32_t cConflicts;
544	/** Number of page tables. */
545	uint32_t cPTs;
546
547	/** Array of page table mapping data. Each entry
548	* describes one page table. The array can be longer
549	* than the declared length.
550	*/
551	struct
552	{
553	/** The HC physical address of the page table. */
554	RTHCPHYS HCPhysPT;
555	/** The HC physical address of the first PAE page table. */
556	RTHCPHYS HCPhysPaePT0;
557	/** The HC physical address of the second PAE page table. */
558	RTHCPHYS HCPhysPaePT1;
559	/** The HC virtual address of the 32-bit page table. */
560	R3PTRTYPE(PX86PT) pPTR3;
561	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
562	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
563	/** The RC virtual address of the 32-bit page table. */
564	RCPTRTYPE(PX86PT) pPTRC;
565	/** The RC virtual address of the two PAE page table. */
566	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
567	/** The R0 virtual address of the 32-bit page table. */
568	R0PTRTYPE(PX86PT) pPTR0;
569	/** The R0 virtual address of the two PAE page table. */
570	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571	} aPTs[1];
572	} PGMMAPPING;
573	/** Pointer to structure for tracking GC Mappings. */
574	typedef struct PGMMAPPING *PPGMMAPPING;
575
576
577	/**
578	* Physical page access handler type registration.
579	*/
580	typedef struct PGMPHYSHANDLERTYPEINT
581	{
582	/** Number of references. */
583	uint32_t volatile cRefs;
584	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
585	uint32_t u32Magic;
586	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
587	RTLISTOFF32NODE ListNode;
588	/** The kind of accesses we're handling. */
589	PGMPHYSHANDLERKIND enmKind;
590	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
591	uint32_t uState;
592	/** Pointer to RC callback function for \#PFs. */
593	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
594	/** Explicit alignment padding. */
595	RTRCPTR RCPtrPadding;
596	/** Pointer to R3 callback function. */
597	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
598	/** Pointer to R0 callback function for \#PFs. */
599	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
600	/** Description / Name. For easing debugging. */
601	R3PTRTYPE(const char *) pszDesc;
602	} PGMPHYSHANDLERTYPEINT;
603	/** Pointer to a physical access handler type registration. */
604	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
605	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
606	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
607	/** Magic value for the physical handler callbacks. */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
609
610	/**
611	* Converts a handle to a pointer.
612	* @returns PPGMPHYSHANDLERTYPEINT
613	* @param a_pVM Pointer to the cross context VM structure.
614	* @param a_hType Physical access handler type handle.
615	*/
616	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
617
618
619	/**
620	* Physical page access handler structure.
621	*
622	* This is used to keep track of physical address ranges
623	* which are being monitored in some kind of way.
624	*/
625	typedef struct PGMPHYSHANDLER
626	{
627	AVLROGCPHYSNODECORE Core;
628	/** Number of pages to update. */
629	uint32_t cPages;
630	/** Set if we have pages that have been aliased. */
631	uint32_t cAliasedPages;
632	/** Set if we have pages that have temporarily been disabled. */
633	uint32_t cTmpOffPages;
634	/** Registered handler type handle (heap offset). */
635	PGMPHYSHANDLERTYPE hType;
636	/** User argument for RC handlers. */
637	RCPTRTYPE(void *) pvUserRC;
638	#if HC_ARCH_BITS == 64
639	RTRCPTR Padding0; /*< Explicit alignment padding. /
640	#endif
641	/** User argument for R3 handlers. */
642	R3PTRTYPE(void *) pvUserR3;
643	/** User argument for R0 handlers. */
644	R0PTRTYPE(void *) pvUserR0;
645	/** Description / Name. For easing debugging. */
646	R3PTRTYPE(const char *) pszDesc;
647	#ifdef VBOX_WITH_STATISTICS
648	/** Profiling of this handler. */
649	STAMPROFILE Stat;
650	#endif
651	} PGMPHYSHANDLER;
652	/** Pointer to a physical page access handler structure. */
653	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
654
655	/**
656	* Gets the type record for a physical handler (no reference added).
657	* @returns PPGMPHYSHANDLERTYPEINT
658	* @param a_pVM Pointer to the cross context VM structure.
659	* @param a_pPhysHandler Pointer to the physical handler structure
660	* (PGMPHYSHANDLER).
661	*/
662	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
663
664
665	/**
666	* Cache node for the physical addresses covered by a virtual handler.
667	*/
668	typedef struct PGMPHYS2VIRTHANDLER
669	{
670	/** Core node for the tree based on physical ranges. */
671	AVLROGCPHYSNODECORE Core;
672	/** Offset from this struct to the PGMVIRTHANDLER structure. */
673	int32_t offVirtHandler;
674	/** Offset of the next alias relative to this one.
675	* Bit 0 is used for indicating whether we're in the tree.
676	* Bit 1 is used for indicating that we're the head node.
677	*/
678	int32_t offNextAlias;
679	} PGMPHYS2VIRTHANDLER;
680	/** Pointer to a phys to virtual handler structure. */
681	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
682
683	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
684	* node is in the tree. */
685	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
686	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
687	* node is in the head of an alias chain.
688	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
689	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
690	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
691	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
692
693
694	/**
695	* Virtual page access handler type registration.
696	*/
697	typedef struct PGMVIRTANDLERTYPEINT
698	{
699	/** Number of references. */
700	uint32_t volatile cRefs;
701	/** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
702	uint32_t u32Magic;
703	/** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
704	RTLISTOFF32NODE ListNode;
705	/** The kind of accesses we're handling. */
706	PGMVIRTHANDLERKIND enmKind;
707	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
708	uint32_t uState;
709	/** Whether the pvUserRC argument should be automatically relocated or not. */
710	bool fRelocUserRC;
711	bool afPadding[3];
712	/** Pointer to RC callback function for \#PFs. */
713	RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
714	/** Pointer to the R3 callback function for invalidation. */
715	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
716	/** Pointer to R3 callback function. */
717	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
718	/** Description / Name. For easing debugging. */
719	R3PTRTYPE(const char *) pszDesc;
720	} PGMVIRTHANDLERTYPEINT;
721	/** Pointer to a virtual access handler type registration. */
722	typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
723	/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
724	#define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
725	/** Magic value for the virtual handler callbacks. */
726	#define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
727
728	/**
729	* Converts a handle to a pointer.
730	* @returns PPGMVIRTHANDLERTYPEINT
731	* @param a_pVM Pointer to the cross context VM structure.
732	* @param a_hType Vitual access handler type handle.
733	*/
734	#define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
735
736
737	/**
738	* Virtual page access handler structure.
739	*
740	* This is used to keep track of virtual address ranges
741	* which are being monitored in some kind of way.
742	*/
743	typedef struct PGMVIRTHANDLER
744	{
745	/** Core node for the tree based on virtual ranges. */
746	AVLROGCPTRNODECORE Core;
747	/** Size of the range (in bytes). */
748	uint32_t cb;
749	/** Number of cache pages. */
750	uint32_t cPages;
751	/** Registered handler type handle (heap offset). */
752	PGMVIRTHANDLERTYPE hType;
753	/** User argument for RC handlers. */
754	RCPTRTYPE(void *) pvUserRC;
755	/** User argument for R3 handlers. */
756	R3PTRTYPE(void *) pvUserR3;
757	/** Description / Name. For easing debugging. */
758	R3PTRTYPE(const char *) pszDesc;
759	#ifdef VBOX_WITH_STATISTICS
760	/** Profiling of this handler. */
761	STAMPROFILE Stat;
762	#endif
763	/** Array of cached physical addresses for the monitored ranged. */
764	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
765	} PGMVIRTHANDLER;
766	/** Pointer to a virtual page access handler structure. */
767	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
768
769	/**
770	* Gets the type record for a virtual handler (no reference added).
771	* @returns PPGMVIRTHANDLERTYPEINT
772	* @param a_pVM Pointer to the cross context VM structure.
773	* @param a_pVirtHandler Pointer to the virtual handler structure
774	* (PGMVIRTHANDLER).
775	*/
776	#define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
777
778
779	/** @name Page type predicates.
780	* @{ */
781	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
782	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
783	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
784	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
785	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
786	/** @} */
787
788
789	/**
790	* A Physical Guest Page tracking structure.
791	*
792	* The format of this structure is complicated because we have to fit a lot
793	* of information into as few bits as possible. The format is also subject
794	* to change (there is one coming up soon). Which means that for we'll be
795	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
796	* accesses to the structure.
797	*/
798	typedef union PGMPAGE
799	{
800	/** Structured view. */
801	struct
802	{
803	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
804	uint64_t u2HandlerPhysStateY : 2;
805	/** 3:2 - Paging structure needed to map the page
806	* (PGM_PAGE_PDE_TYPE_). /
807	uint64_t u2PDETypeY : 2;
808	/** 4 - Indicator of dirty page for fault tolerance tracking. */
809	uint64_t fFTDirtyY : 1;
810	/** 5 - Flag indicating that a write monitored page was written to
811	* when set. */
812	uint64_t fWrittenToY : 1;
813	/** 7:6 - Unused. */
814	uint64_t u2Unused0 : 2;
815	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
816	uint64_t u2HandlerVirtStateY : 2;
817	/** 11:10 - Unused. */
818	uint64_t u2Unused1 : 2;
819	/** 12:48 - The host physical frame number (shift left to get the
820	* address). */
821	uint64_t HCPhysFN : 36;
822	/** 50:48 - The page state. */
823	uint64_t uStateY : 3;
824	/** 51:53 - The page type (PGMPAGETYPE). */
825	uint64_t uTypeY : 3;
826	/** 63:54 - PTE index for usage tracking (page pool). */
827	uint64_t u10PteIdx : 10;
828
829	/** The GMM page ID.
830	* @remarks In the current implementation, MMIO2 and pages aliased to
831	* MMIO2 pages will be exploiting this field to calculate the
832	* ring-3 mapping address corresponding to the page.
833	* Later we may consider including MMIO2 management into GMM. */
834	uint32_t idPage;
835	/** Usage tracking (page pool). */
836	uint16_t u16TrackingY;
837	/** The number of read locks on this page. */
838	uint8_t cReadLocksY;
839	/** The number of write locks on this page. */
840	uint8_t cWriteLocksY;
841	} s;
842
843	/** 64-bit integer view. */
844	uint64_t au64[2];
845	/** 16-bit view. */
846	uint32_t au32[4];
847	/** 16-bit view. */
848	uint16_t au16[8];
849	/** 8-bit view. */
850	uint8_t au8[16];
851	} PGMPAGE;
852	AssertCompileSize(PGMPAGE, 16);
853	/** Pointer to a physical guest page. */
854	typedef PGMPAGE *PPGMPAGE;
855	/** Pointer to a const physical guest page. */
856	typedef const PGMPAGE *PCPGMPAGE;
857	/** Pointer to a physical guest page pointer. */
858	typedef PPGMPAGE *PPPGMPAGE;
859
860
861	/**
862	* Clears the page structure.
863	* @param a_pPage Pointer to the physical guest page tracking structure.
864	*/
865	#define PGM_PAGE_CLEAR(a_pPage) \
866	do { \
867	(a_pPage)->au64[0] = 0; \
868	(a_pPage)->au64[1] = 0; \
869	} while (0)
870
871	/**
872	* Initializes the page structure.
873	* @param a_pPage Pointer to the physical guest page tracking structure.
874	*/
875	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
876	do { \
877	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
878	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
879	(a_pPage)->au64[0] = SetHCPhysTmp; \
880	(a_pPage)->au64[1] = 0; \
881	(a_pPage)->s.idPage = (a_idPage); \
882	(a_pPage)->s.uStateY = (a_uState); \
883	(a_pPage)->s.uTypeY = (a_uType); \
884	} while (0)
885
886	/**
887	* Initializes the page structure of a ZERO page.
888	* @param a_pPage Pointer to the physical guest page tracking structure.
889	* @param a_pVM The VM handle (for getting the zero page address).
890	* @param a_uType The page type (PGMPAGETYPE).
891	*/
892	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
893	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
894
895
896	/** @name The Page state, PGMPAGE::uStateY.
897	* @{ */
898	/** The zero page.
899	* This is a per-VM page that's never ever mapped writable. */
900	#define PGM_PAGE_STATE_ZERO 0
901	/** A allocated page.
902	* This is a per-VM page allocated from the page pool (or wherever
903	* we get MMIO2 pages from if the type is MMIO2).
904	*/
905	#define PGM_PAGE_STATE_ALLOCATED 1
906	/** A allocated page that's being monitored for writes.
907	* The shadow page table mappings are read-only. When a write occurs, the
908	* fWrittenTo member is set, the page remapped as read-write and the state
909	* moved back to allocated. */
910	#define PGM_PAGE_STATE_WRITE_MONITORED 2
911	/** The page is shared, aka. copy-on-write.
912	* This is a page that's shared with other VMs. */
913	#define PGM_PAGE_STATE_SHARED 3
914	/** The page is ballooned, so no longer available for this VM. */
915	#define PGM_PAGE_STATE_BALLOONED 4
916	/** @} */
917
918
919	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
920	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
921	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
922	#else
923	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
924	#endif
925
926	/**
927	* Gets the page state.
928	* @returns page state (PGM_PAGE_STATE_*).
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*
931	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
932	* builds.
933	*/
934	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
935	#if defined(__GNUC__) && defined(VBOX_STRICT)
936	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
937	#else
938	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
939	#endif
940
941	/**
942	* Sets the page state.
943	* @param a_pVM The VM handle, only used for lock ownership assertions.
944	* @param a_pPage Pointer to the physical guest page tracking structure.
945	* @param a_uState The new page state.
946	*/
947	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
948	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
949
950
951	/**
952	* Gets the host physical address of the guest page.
953	* @returns host physical address (RTHCPHYS).
954	* @param a_pPage Pointer to the physical guest page tracking structure.
955	*
956	* @remarks In strict builds on gcc platforms, this macro will make some ugly
957	* assumption about a valid pVM variable/parameter being in the
958	* current context. It will use this pVM variable to assert that the
959	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
960	* pVM is not around.
961	*/
962	#if 0
963	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
964	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
965	#else
966	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
967	# if defined(__GNUC__) && defined(VBOX_STRICT)
968	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
969	# else
970	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
971	# endif
972	#endif
973
974	/**
975	* Sets the host physical address of the guest page.
976	*
977	* @param a_pVM The VM handle, only used for lock ownership assertions.
978	* @param a_pPage Pointer to the physical guest page tracking structure.
979	* @param a_HCPhys The new host physical address.
980	*/
981	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
982	do { \
983	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
984	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
985	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
986	PGM_PAGE_ASSERT_LOCK(a_pVM); \
987	} while (0)
988
989	/**
990	* Get the Page ID.
991	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
992	* @param a_pPage Pointer to the physical guest page tracking structure.
993	*/
994	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
995
996	/**
997	* Sets the Page ID.
998	* @param a_pVM The VM handle, only used for lock ownership assertions.
999	* @param a_pPage Pointer to the physical guest page tracking structure.
1000	* @param a_idPage The new page ID.
1001	*/
1002	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1003	do { \
1004	(a_pPage)->s.idPage = (a_idPage); \
1005	PGM_PAGE_ASSERT_LOCK(a_pVM); \
1006	} while (0)
1007
1008	/**
1009	* Get the Chunk ID.
1010	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1011	* @param a_pPage Pointer to the physical guest page tracking structure.
1012	*/
1013	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1014
1015	/**
1016	* Get the index of the page within the allocation chunk.
1017	* @returns The page index.
1018	* @param a_pPage Pointer to the physical guest page tracking structure.
1019	*/
1020	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1021
1022	/**
1023	* Gets the page type.
1024	* @returns The page type.
1025	* @param a_pPage Pointer to the physical guest page tracking structure.
1026	*
1027	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1028	* builds.
1029	*/
1030	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1031	#if defined(__GNUC__) && defined(VBOX_STRICT)
1032	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1033	#else
1034	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1035	#endif
1036
1037	/**
1038	* Sets the page type.
1039	*
1040	* @param a_pVM The VM handle, only used for lock ownership assertions.
1041	* @param a_pPage Pointer to the physical guest page tracking structure.
1042	* @param a_enmType The new page type (PGMPAGETYPE).
1043	*/
1044	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1045	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1046
1047	/**
1048	* Gets the page table index
1049	* @returns The page table index.
1050	* @param a_pPage Pointer to the physical guest page tracking structure.
1051	*/
1052	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1053
1054	/**
1055	* Sets the page table index.
1056	* @param a_pVM The VM handle, only used for lock ownership assertions.
1057	* @param a_pPage Pointer to the physical guest page tracking structure.
1058	* @param a_iPte New page table index.
1059	*/
1060	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1061	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1062
1063	/**
1064	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1065	* @returns true/false.
1066	* @param a_pPage Pointer to the physical guest page tracking structure.
1067	*/
1068	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1069
1070	/**
1071	* Checks if the page is marked for MMIO, including both aliases.
1072	* @returns true/false.
1073	* @param a_pPage Pointer to the physical guest page tracking structure.
1074	*/
1075	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1076	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1077	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1078	)
1079
1080	/**
1081	* Checks if the page is marked for MMIO, including special aliases.
1082	* @returns true/false.
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1086	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1087
1088	/**
1089	* Checks if the page is a special aliased MMIO page.
1090	* @returns true/false.
1091	* @param a_pPage Pointer to the physical guest page tracking structure.
1092	*/
1093	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1094
1095	/**
1096	* Checks if the page is backed by the ZERO page.
1097	* @returns true/false.
1098	* @param a_pPage Pointer to the physical guest page tracking structure.
1099	*/
1100	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1101
1102	/**
1103	* Checks if the page is backed by a SHARED page.
1104	* @returns true/false.
1105	* @param a_pPage Pointer to the physical guest page tracking structure.
1106	*/
1107	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1108
1109	/**
1110	* Checks if the page is ballooned.
1111	* @returns true/false.
1112	* @param a_pPage Pointer to the physical guest page tracking structure.
1113	*/
1114	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1115
1116	/**
1117	* Checks if the page is allocated.
1118	* @returns true/false.
1119	* @param a_pPage Pointer to the physical guest page tracking structure.
1120	*/
1121	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1122
1123	/**
1124	* Marks the page as written to (for GMM change monitoring).
1125	* @param a_pVM The VM handle, only used for lock ownership assertions.
1126	* @param a_pPage Pointer to the physical guest page tracking structure.
1127	*/
1128	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1129	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1130
1131	/**
1132	* Clears the written-to indicator.
1133	* @param a_pVM The VM handle, only used for lock ownership assertions.
1134	* @param a_pPage Pointer to the physical guest page tracking structure.
1135	*/
1136	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1137	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1138
1139	/**
1140	* Checks if the page was marked as written-to.
1141	* @returns true/false.
1142	* @param a_pPage Pointer to the physical guest page tracking structure.
1143	*/
1144	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1145
1146	/**
1147	* Marks the page as dirty for FTM
1148	* @param a_pPage Pointer to the physical guest page tracking structure.
1149	*/
1150	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1151
1152	/**
1153	* Clears the FTM dirty indicator
1154	* @param a_pPage Pointer to the physical guest page tracking structure.
1155	*/
1156	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1157
1158	/**
1159	* Checks if the page was marked as dirty for FTM
1160	* @returns true/false.
1161	* @param a_pPage Pointer to the physical guest page tracking structure.
1162	*/
1163	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1164
1165
1166	/** @name PT usage values (PGMPAGE::u2PDEType).
1167	*
1168	* @{ */
1169	/** Either as a PT or PDE. */
1170	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1171	/** Must use a page table to map the range. */
1172	#define PGM_PAGE_PDE_TYPE_PT 1
1173	/** Can use a page directory entry to map the continuous range. */
1174	#define PGM_PAGE_PDE_TYPE_PDE 2
1175	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1176	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1177	/** @} */
1178
1179	/**
1180	* Set the PDE type of the page
1181	* @param a_pVM The VM handle, only used for lock ownership assertions.
1182	* @param a_pPage Pointer to the physical guest page tracking structure.
1183	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1184	*/
1185	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1186	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1187
1188	/**
1189	* Checks if the page was marked being part of a large page
1190	* @returns true/false.
1191	* @param a_pPage Pointer to the physical guest page tracking structure.
1192	*/
1193	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1194
1195	/** Enabled optimized access handler tests.
1196	* These optimizations makes ASSUMPTIONS about the state values and the s1
1197	* layout. When enabled, the compiler should normally generate more compact
1198	* code.
1199	*/
1200	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1201
1202	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1203	*
1204	* @remarks The values are assigned in order of priority, so we can calculate
1205	* the correct state for a page with different handlers installed.
1206	* @{ */
1207	/** No handler installed. */
1208	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1209	/** Monitoring is temporarily disabled. */
1210	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1211	/** Write access is monitored. */
1212	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1213	/** All access is monitored. */
1214	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1215	/** @} */
1216
1217	/**
1218	* Gets the physical access handler state of a page.
1219	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1220	* @param a_pPage Pointer to the physical guest page tracking structure.
1221	*/
1222	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1223
1224	/**
1225	* Sets the physical access handler state of a page.
1226	* @param a_pPage Pointer to the physical guest page tracking structure.
1227	* @param a_uState The new state value.
1228	*/
1229	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1230	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1231
1232	/**
1233	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1234	* @returns true/false
1235	* @param a_pPage Pointer to the physical guest page tracking structure.
1236	*/
1237	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1238	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1239
1240	/**
1241	* Checks if the page has any active physical access handlers.
1242	* @returns true/false
1243	* @param a_pPage Pointer to the physical guest page tracking structure.
1244	*/
1245	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1246	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1247
1248
1249	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1250	*
1251	* @remarks The values are assigned in order of priority, so we can calculate
1252	* the correct state for a page with different handlers installed.
1253	* @{ */
1254	/** No handler installed. */
1255	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1256	/* 1 is reserved so the lineup is identical with the physical ones. */
1257	/** Write access is monitored. */
1258	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1259	/** All access is monitored. */
1260	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1261	/** @} */
1262
1263	/**
1264	* Gets the virtual access handler state of a page.
1265	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1266	* @param a_pPage Pointer to the physical guest page tracking structure.
1267	*/
1268	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1269
1270	/**
1271	* Sets the virtual access handler state of a page.
1272	* @param a_pPage Pointer to the physical guest page tracking structure.
1273	* @param a_uState The new state value.
1274	*/
1275	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1276	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1277
1278	/**
1279	* Checks if the page has any virtual access handlers.
1280	* @returns true/false
1281	* @param a_pPage Pointer to the physical guest page tracking structure.
1282	*/
1283	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1284	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1285
1286	/**
1287	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1288	* virtual handlers.
1289	* @returns true/false
1290	* @param a_pPage Pointer to the physical guest page tracking structure.
1291	*/
1292	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1293	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1294
1295
1296	/**
1297	* Checks if the page has any access handlers, including temporarily disabled ones.
1298	* @returns true/false
1299	* @param a_pPage Pointer to the physical guest page tracking structure.
1300	*/
1301	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1302	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1303	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1304	#else
1305	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1306	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1307	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1308	#endif
1309
1310	/**
1311	* Checks if the page has any active access handlers.
1312	* @returns true/false
1313	* @param a_pPage Pointer to the physical guest page tracking structure.
1314	*/
1315	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1316	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1317	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1318	#else
1319	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1320	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1321	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1322	#endif
1323
1324	/**
1325	* Checks if the page has any active access handlers catching all accesses.
1326	* @returns true/false
1327	* @param a_pPage Pointer to the physical guest page tracking structure.
1328	*/
1329	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1330	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1331	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1332	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1333	#else
1334	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1335	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1336	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1337	#endif
1338
1339
1340	/** @def PGM_PAGE_GET_TRACKING
1341	* Gets the packed shadow page pool tracking data associated with a guest page.
1342	* @returns uint16_t containing the data.
1343	* @param a_pPage Pointer to the physical guest page tracking structure.
1344	*/
1345	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1346	#if defined(__GNUC__) && defined(VBOX_STRICT)
1347	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1348	#else
1349	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1350	#endif
1351
1352	/** @def PGM_PAGE_SET_TRACKING
1353	* Sets the packed shadow page pool tracking data associated with a guest page.
1354	* @param a_pVM The VM handle, only used for lock ownership assertions.
1355	* @param a_pPage Pointer to the physical guest page tracking structure.
1356	* @param a_u16TrackingData The tracking data to store.
1357	*/
1358	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1359	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1360
1361	/** @def PGM_PAGE_GET_TD_CREFS
1362	* Gets the @a cRefs tracking data member.
1363	* @returns cRefs.
1364	* @param a_pPage Pointer to the physical guest page tracking structure.
1365	*/
1366	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1367	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1368	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1369	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1370
1371	/** @def PGM_PAGE_GET_TD_IDX
1372	* Gets the @a idx tracking data member.
1373	* @returns idx.
1374	* @param a_pPage Pointer to the physical guest page tracking structure.
1375	*/
1376	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1377	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1378	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1379	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1380
1381
1382	/** Max number of locks on a page. */
1383	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1384
1385	/** Get the read lock count.
1386	* @returns count.
1387	* @param a_pPage Pointer to the physical guest page tracking structure.
1388	*/
1389	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1390
1391	/** Get the write lock count.
1392	* @returns count.
1393	* @param a_pPage Pointer to the physical guest page tracking structure.
1394	*/
1395	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1396
1397	/** Decrement the read lock counter.
1398	* @param a_pPage Pointer to the physical guest page tracking structure.
1399	*/
1400	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1401
1402	/** Decrement the write lock counter.
1403	* @param a_pPage Pointer to the physical guest page tracking structure.
1404	*/
1405	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1406
1407	/** Increment the read lock counter.
1408	* @param a_pPage Pointer to the physical guest page tracking structure.
1409	*/
1410	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1411
1412	/** Increment the write lock counter.
1413	* @param a_pPage Pointer to the physical guest page tracking structure.
1414	*/
1415	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1416
1417
1418	#if 0
1419	/** Enables sanity checking of write monitoring using CRC-32. */
1420	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1421	#endif
1422
1423	/**
1424	* Per page live save tracking data.
1425	*/
1426	typedef struct PGMLIVESAVERAMPAGE
1427	{
1428	/** Number of times it has been dirtied. */
1429	uint32_t cDirtied : 24;
1430	/** Whether it is currently dirty. */
1431	uint32_t fDirty : 1;
1432	/** Ignore the page.
1433	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1434	* deal with these after pausing the VM and DevPCI have said it bit about
1435	* remappings. */
1436	uint32_t fIgnore : 1;
1437	/** Was a ZERO page last time around. */
1438	uint32_t fZero : 1;
1439	/** Was a SHARED page last time around. */
1440	uint32_t fShared : 1;
1441	/** Whether the page is/was write monitored in a previous pass. */
1442	uint32_t fWriteMonitored : 1;
1443	/** Whether the page is/was write monitored earlier in this pass. */
1444	uint32_t fWriteMonitoredJustNow : 1;
1445	/** Bits reserved for future use. */
1446	uint32_t u2Reserved : 2;
1447	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1448	/** CRC-32 for the page. This is for internal consistency checks. */
1449	uint32_t u32Crc;
1450	#endif
1451	} PGMLIVESAVERAMPAGE;
1452	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1453	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1454	#else
1455	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1456	#endif
1457	/** Pointer to the per page live save tracking data. */
1458	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1459
1460	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1461	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1462
1463
1464	/**
1465	* RAM range for GC Phys to HC Phys conversion.
1466	*
1467	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1468	* conversions too, but we'll let MM handle that for now.
1469	*
1470	* This structure is used by linked lists in both GC and HC.
1471	*/
1472	typedef struct PGMRAMRANGE
1473	{
1474	/** Start of the range. Page aligned. */
1475	RTGCPHYS GCPhys;
1476	/** Size of the range. (Page aligned of course). */
1477	RTGCPHYS cb;
1478	/** Pointer to the next RAM range - for R3. */
1479	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1480	/** Pointer to the next RAM range - for R0. */
1481	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1482	/** Pointer to the next RAM range - for RC. */
1483	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1484	/** PGM_RAM_RANGE_FLAGS_* flags. */
1485	uint32_t fFlags;
1486	/** Last address in the range (inclusive). Page aligned (-1). */
1487	RTGCPHYS GCPhysLast;
1488	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1489	R3PTRTYPE(void *) pvR3;
1490	/** Live save per page tracking data. */
1491	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1492	/** The range description. */
1493	R3PTRTYPE(const char *) pszDesc;
1494	/** Pointer to self - R0 pointer. */
1495	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1496	/** Pointer to self - RC pointer. */
1497	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1498
1499	/** Alignment padding. */
1500	RTRCPTR Alignment0;
1501	/** Pointer to the left search three node - ring-3 context. */
1502	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1503	/** Pointer to the right search three node - ring-3 context. */
1504	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1505	/** Pointer to the left search three node - ring-0 context. */
1506	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1507	/** Pointer to the right search three node - ring-0 context. */
1508	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1509	/** Pointer to the left search three node - raw-mode context. */
1510	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1511	/** Pointer to the right search three node - raw-mode context. */
1512	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1513
1514	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1515	#if HC_ARCH_BITS == 32
1516	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1517	#endif
1518	/** Array of physical guest page tracking structures. */
1519	PGMPAGE aPages[1];
1520	} PGMRAMRANGE;
1521	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1522	typedef PGMRAMRANGE *PPGMRAMRANGE;
1523
1524	/** @name PGMRAMRANGE::fFlags
1525	* @{ */
1526	/** The RAM range is floating around as an independent guest mapping. */
1527	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1528	/** Ad hoc RAM range for an ROM mapping. */
1529	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1530	/** Ad hoc RAM range for an MMIO mapping. */
1531	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1532	/** Ad hoc RAM range for an MMIO2 mapping. */
1533	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1534	/** @} */
1535
1536	/** Tests if a RAM range is an ad hoc one or not.
1537	* @returns true/false.
1538	* @param pRam The RAM range.
1539	*/
1540	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1541	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1542
1543	/** The number of entries in the RAM range TLBs (there is one for each
1544	* context). Must be a power of two. */
1545	#define PGM_RAMRANGE_TLB_ENTRIES 8
1546
1547	/**
1548	* Calculates the RAM range TLB index for the physical address.
1549	*
1550	* @returns RAM range TLB index.
1551	* @param GCPhys The guest physical address.
1552	*/
1553	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1554
1555
1556
1557	/**
1558	* Per page tracking structure for ROM image.
1559	*
1560	* A ROM image may have a shadow page, in which case we may have two pages
1561	* backing it. This structure contains the PGMPAGE for both while
1562	* PGMRAMRANGE have a copy of the active one. It is important that these
1563	* aren't out of sync in any regard other than page pool tracking data.
1564	*/
1565	typedef struct PGMROMPAGE
1566	{
1567	/** The page structure for the virgin ROM page. */
1568	PGMPAGE Virgin;
1569	/** The page structure for the shadow RAM page. */
1570	PGMPAGE Shadow;
1571	/** The current protection setting. */
1572	PGMROMPROT enmProt;
1573	/** Live save status information. Makes use of unused alignment space. */
1574	struct
1575	{
1576	/** The previous protection value. */
1577	uint8_t u8Prot;
1578	/** Written to flag set by the handler. */
1579	bool fWrittenTo;
1580	/** Whether the shadow page is dirty or not. */
1581	bool fDirty;
1582	/** Whether it was dirtied in the recently. */
1583	bool fDirtiedRecently;
1584	} LiveSave;
1585	} PGMROMPAGE;
1586	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1587	/** Pointer to a ROM page tracking structure. */
1588	typedef PGMROMPAGE *PPGMROMPAGE;
1589
1590
1591	/**
1592	* A registered ROM image.
1593	*
1594	* This is needed to keep track of ROM image since they generally intrude
1595	* into a PGMRAMRANGE. It also keeps track of additional info like the
1596	* two page sets (read-only virgin and read-write shadow), the current
1597	* state of each page.
1598	*
1599	* Because access handlers cannot easily be executed in a different
1600	* context, the ROM ranges needs to be accessible and in all contexts.
1601	*/
1602	typedef struct PGMROMRANGE
1603	{
1604	/** Pointer to the next range - R3. */
1605	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1606	/** Pointer to the next range - R0. */
1607	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1608	/** Pointer to the next range - RC. */
1609	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1610	/** Pointer alignment */
1611	RTRCPTR RCPtrAlignment;
1612	/** Address of the range. */
1613	RTGCPHYS GCPhys;
1614	/** Address of the last byte in the range. */
1615	RTGCPHYS GCPhysLast;
1616	/** Size of the range. */
1617	RTGCPHYS cb;
1618	/** The flags (PGMPHYS_ROM_FLAGS_). /
1619	uint32_t fFlags;
1620	/** The saved state range ID. */
1621	uint8_t idSavedState;
1622	/** Alignment padding. */
1623	uint8_t au8Alignment[3];
1624	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1625	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1626	/** The size bits pvOriginal points to. */
1627	uint32_t cbOriginal;
1628	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1629	* This is used for strictness checks. */
1630	R3PTRTYPE(const void *) pvOriginal;
1631	/** The ROM description. */
1632	R3PTRTYPE(const char *) pszDesc;
1633	/** The per page tracking structures. */
1634	PGMROMPAGE aPages[1];
1635	} PGMROMRANGE;
1636	/** Pointer to a ROM range. */
1637	typedef PGMROMRANGE *PPGMROMRANGE;
1638
1639
1640	/**
1641	* Live save per page data for an MMIO2 page.
1642	*
1643	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1644	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1645	* CRC-32 for detecting changes as well as special handling of zero pages. This
1646	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1647	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1648	* because of speed (2.5x and 6x slower).)
1649	*
1650	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1651	* save but normally is disabled. Since we can write monitor guest
1652	* accesses on our own, we only need this for host accesses. Shouldn't be
1653	* too difficult for DevVGA, VMMDev might be doable, the planned
1654	* networking fun will be fun since it involves ring-0.
1655	*/
1656	typedef struct PGMLIVESAVEMMIO2PAGE
1657	{
1658	/** Set if the page is considered dirty. */
1659	bool fDirty;
1660	/** The number of scans this page has remained unchanged for.
1661	* Only updated for dirty pages. */
1662	uint8_t cUnchangedScans;
1663	/** Whether this page was zero at the last scan. */
1664	bool fZero;
1665	/** Alignment padding. */
1666	bool fReserved;
1667	/** CRC-32 for the first half of the page.
1668	* This is used together with u32CrcH2 to quickly detect changes in the page
1669	* during the non-final passes. */
1670	uint32_t u32CrcH1;
1671	/** CRC-32 for the second half of the page. */
1672	uint32_t u32CrcH2;
1673	/** SHA-1 for the saved page.
1674	* This is used in the final pass to skip pages without changes. */
1675	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1676	} PGMLIVESAVEMMIO2PAGE;
1677	/** Pointer to a live save status data for an MMIO2 page. */
1678	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1679
1680	/**
1681	* A registered MMIO2 (= Device RAM) range.
1682	*
1683	* There are a few reason why we need to keep track of these
1684	* registrations. One of them is the deregistration & cleanup stuff,
1685	* while another is that the PGMRAMRANGE associated with such a region may
1686	* have to be removed from the ram range list.
1687	*
1688	* Overlapping with a RAM range has to be 100% or none at all. The pages
1689	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1690	* will be raised if a partial overlap or an overlap of ROM pages is
1691	* encountered. On an overlap we will free all the existing RAM pages and
1692	* put in the ram range pages instead.
1693	*/
1694	typedef struct PGMMMIO2RANGE
1695	{
1696	/** The owner of the range. (a device) */
1697	PPDMDEVINSR3 pDevInsR3;
1698	/** Pointer to the ring-3 mapping of the allocation. */
1699	RTR3PTR pvR3;
1700	/** Pointer to the next range - R3. */
1701	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1702	/** Whether it's mapped or not. */
1703	bool fMapped;
1704	/** Whether it's overlapping or not. */
1705	bool fOverlapping;
1706	/** The PCI region number.
1707	* @remarks This ASSUMES that nobody will ever really need to have multiple
1708	* PCI devices with matching MMIO region numbers on a single device. */
1709	uint8_t iRegion;
1710	/** The saved state range ID. */
1711	uint8_t idSavedState;
1712	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1713	uint8_t idMmio2;
1714	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1715	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1716	/** Live save per page tracking data. */
1717	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1718	/** The associated RAM range. */
1719	PGMRAMRANGE RamRange;
1720	} PGMMMIO2RANGE;
1721	/** Pointer to a MMIO2 range. */
1722	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1723
1724	/** @name Intenal MMIO2 constants.
1725	* @{ */
1726	/** The maximum number of MMIO2 ranges. */
1727	#define PGM_MMIO2_MAX_RANGES 8
1728	/** The maximum number of pages in a MMIO2 range. */
1729	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1730	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1731	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1732	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1733	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1734	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1735	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1736	/** @} */
1737
1738
1739
1740	/**
1741	* PGMPhysRead/Write cache entry
1742	*/
1743	typedef struct PGMPHYSCACHEENTRY
1744	{
1745	/** R3 pointer to physical page. */
1746	R3PTRTYPE(uint8_t *) pbR3;
1747	/** GC Physical address for cache entry */
1748	RTGCPHYS GCPhys;
1749	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1750	RTGCPHYS u32Padding0; /*< alignment padding. /
1751	#endif
1752	} PGMPHYSCACHEENTRY;
1753
1754	/**
1755	* PGMPhysRead/Write cache to reduce REM memory access overhead
1756	*/
1757	typedef struct PGMPHYSCACHE
1758	{
1759	/** Bitmap of valid cache entries */
1760	uint64_t aEntries;
1761	/** Cache entries */
1762	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1763	} PGMPHYSCACHE;
1764
1765
1766	/** Pointer to an allocation chunk ring-3 mapping. */
1767	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1768	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1769	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1770
1771	/**
1772	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1773	*
1774	* The primary tree (Core) uses the chunk id as key.
1775	*/
1776	typedef struct PGMCHUNKR3MAP
1777	{
1778	/** The key is the chunk id. */
1779	AVLU32NODECORE Core;
1780	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1781	* selection. */
1782	uint32_t iLastUsed;
1783	/** The current reference count. */
1784	uint32_t volatile cRefs;
1785	/** The current permanent reference count. */
1786	uint32_t volatile cPermRefs;
1787	/** The mapping address. */
1788	void *pv;
1789	} PGMCHUNKR3MAP;
1790
1791	/**
1792	* Allocation chunk ring-3 mapping TLB entry.
1793	*/
1794	typedef struct PGMCHUNKR3MAPTLBE
1795	{
1796	/** The chunk id. */
1797	uint32_t volatile idChunk;
1798	#if HC_ARCH_BITS == 64
1799	uint32_t u32Padding; /*< alignment padding. /
1800	#endif
1801	/** The chunk map. */
1802	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1803	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1804	#else
1805	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1806	#endif
1807	} PGMCHUNKR3MAPTLBE;
1808	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1809	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1810
1811	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1812	* @remark Must be a power of two value. */
1813	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1814
1815	/**
1816	* Allocation chunk ring-3 mapping TLB.
1817	*
1818	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1819	* At first glance this might look kinda odd since AVL trees are
1820	* supposed to give the most optimal lookup times of all trees
1821	* due to their balancing. However, take a tree with 1023 nodes
1822	* in it, that's 10 levels, meaning that most searches has to go
1823	* down 9 levels before they find what they want. This isn't fast
1824	* compared to a TLB hit. There is the factor of cache misses,
1825	* and of course the problem with trees and branch prediction.
1826	* This is why we use TLBs in front of most of the trees.
1827	*
1828	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1829	* difficult when we switch to the new inlined AVL trees (from kStuff).
1830	*/
1831	typedef struct PGMCHUNKR3MAPTLB
1832	{
1833	/** The TLB entries. */
1834	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1835	} PGMCHUNKR3MAPTLB;
1836
1837	/**
1838	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1839	* @returns Chunk TLB index.
1840	* @param idChunk The Chunk ID.
1841	*/
1842	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1843
1844
1845	/**
1846	* Ring-3 guest page mapping TLB entry.
1847	* @remarks used in ring-0 as well at the moment.
1848	*/
1849	typedef struct PGMPAGER3MAPTLBE
1850	{
1851	/** Address of the page. */
1852	RTGCPHYS volatile GCPhys;
1853	/** The guest page. */
1854	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1855	R3PTRTYPE(PPGMPAGE) volatile pPage;
1856	#else
1857	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1858	#endif
1859	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1860	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1861	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1862	#else
1863	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1864	#endif
1865	/** The address */
1866	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1867	R3PTRTYPE(void *) volatile pv;
1868	#else
1869	R3R0PTRTYPE(void *) volatile pv;
1870	#endif
1871	#if HC_ARCH_BITS == 32
1872	uint32_t u32Padding; /*< alignment padding. /
1873	#endif
1874	} PGMPAGER3MAPTLBE;
1875	/** Pointer to an entry in the HC physical TLB. */
1876	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1877
1878
1879	/** The number of entries in the ring-3 guest page mapping TLB.
1880	* @remarks The value must be a power of two. */
1881	#define PGM_PAGER3MAPTLB_ENTRIES 256
1882
1883	/**
1884	* Ring-3 guest page mapping TLB.
1885	* @remarks used in ring-0 as well at the moment.
1886	*/
1887	typedef struct PGMPAGER3MAPTLB
1888	{
1889	/** The TLB entries. */
1890	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1891	} PGMPAGER3MAPTLB;
1892	/** Pointer to the ring-3 guest page mapping TLB. */
1893	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1894
1895	/**
1896	* Calculates the index of the TLB entry for the specified guest page.
1897	* @returns Physical TLB index.
1898	* @param GCPhys The guest physical address.
1899	*/
1900	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1901
1902
1903	/**
1904	* Raw-mode context dynamic mapping cache entry.
1905	*
1906	* Because of raw-mode context being reloctable and all relocations are applied
1907	* in ring-3, this has to be defined here and be RC specific.
1908	*
1909	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1910	*/
1911	typedef struct PGMRCDYNMAPENTRY
1912	{
1913	/** The physical address of the currently mapped page.
1914	* This is duplicate for three reasons: cache locality, cache policy of the PT
1915	* mappings and sanity checks. */
1916	RTHCPHYS HCPhys;
1917	/** Pointer to the page. */
1918	RTRCPTR pvPage;
1919	/** The number of references. */
1920	int32_t volatile cRefs;
1921	/** PTE pointer union. */
1922	struct PGMRCDYNMAPENTRY_PPTE
1923	{
1924	/** PTE pointer, 32-bit legacy version. */
1925	RCPTRTYPE(PX86PTE) pLegacy;
1926	/** PTE pointer, PAE version. */
1927	RCPTRTYPE(PX86PTEPAE) pPae;
1928	} uPte;
1929	} PGMRCDYNMAPENTRY;
1930	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1931	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1932
1933
1934	/**
1935	* Dynamic mapping cache for the raw-mode context.
1936	*
1937	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1938	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1939	* so that we can perform relocations from PGMR3Relocate. This has the
1940	* consequence that we must have separate ring-0 and raw-mode context versions
1941	* of this struct even if they share the basic elements.
1942	*
1943	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1944	*/
1945	typedef struct PGMRCDYNMAP
1946	{
1947	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1948	uint32_t u32Magic;
1949	/** Array for tracking and managing the pages. */
1950	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1951	/** The cache size given as a number of pages. */
1952	uint32_t cPages;
1953	/** The current load.
1954	* This does not include guard pages. */
1955	uint32_t cLoad;
1956	/** The max load ever.
1957	* This is maintained to get trigger adding of more mapping space. */
1958	uint32_t cMaxLoad;
1959	/** The number of guard pages. */
1960	uint32_t cGuardPages;
1961	/** The number of users (protected by hInitLock). */
1962	uint32_t cUsers;
1963	} PGMRCDYNMAP;
1964	/** Pointer to the dynamic cache for the raw-mode context. */
1965	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1966
1967
1968	/**
1969	* Mapping cache usage set entry.
1970	*
1971	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1972	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1973	* cache. If it's extended to include ring-3, well, then something
1974	* will have be changed here...
1975	*/
1976	typedef struct PGMMAPSETENTRY
1977	{
1978	/** Pointer to the page. */
1979	#ifndef IN_RC
1980	RTR0PTR pvPage;
1981	#else
1982	RTRCPTR pvPage;
1983	# if HC_ARCH_BITS == 64
1984	uint32_t u32Alignment2;
1985	# endif
1986	#endif
1987	/** The mapping cache index. */
1988	uint16_t iPage;
1989	/** The number of references.
1990	* The max is UINT16_MAX - 1. */
1991	uint16_t cRefs;
1992	/** The number inlined references.
1993	* The max is UINT16_MAX - 1. */
1994	uint16_t cInlinedRefs;
1995	/** Unreferences. */
1996	uint16_t cUnrefs;
1997
1998	#if HC_ARCH_BITS == 32
1999	uint32_t u32Alignment1;
2000	#endif
2001	/** The physical address for this entry. */
2002	RTHCPHYS HCPhys;
2003	} PGMMAPSETENTRY;
2004	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2005	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2006	/** Pointer to a mapping cache usage set entry. */
2007	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2008
2009	/**
2010	* Mapping cache usage set.
2011	*
2012	* This is used in ring-0 and the raw-mode context to track dynamic mappings
2013	* done during exits / traps. The set is
2014	*/
2015	typedef struct PGMMAPSET
2016	{
2017	/** The number of occupied entries.
2018	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2019	* dynamic mappings. */
2020	uint32_t cEntries;
2021	/** The start of the current subset.
2022	* This is UINT32_MAX if no subset is currently open. */
2023	uint32_t iSubset;
2024	/** The index of the current CPU, only valid if the set is open. */
2025	int32_t iCpu;
2026	uint32_t alignment;
2027	/** The entries. */
2028	PGMMAPSETENTRY aEntries[64];
2029	/** HCPhys -> iEntry fast lookup table.
2030	* Use PGMMAPSET_HASH for hashing.
2031	* The entries may or may not be valid, check against cEntries. */
2032	uint8_t aiHashTable[128];
2033	} PGMMAPSET;
2034	AssertCompileSizeAlignment(PGMMAPSET, 8);
2035	/** Pointer to the mapping cache set. */
2036	typedef PGMMAPSET *PPGMMAPSET;
2037
2038	/** PGMMAPSET::cEntries value for a closed set. */
2039	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2040
2041	/** Hash function for aiHashTable. */
2042	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2043
2044
2045	/** @name Context neutral page mapper TLB.
2046	*
2047	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2048	* code is writting in a kind of context neutral way. Time will show whether
2049	* this actually makes sense or not...
2050	*
2051	* @todo this needs to be reconsidered and dropped/redone since the ring-0
2052	* context ends up using a global mapping cache on some platforms
2053	* (darwin).
2054	*
2055	* @{ */
2056	/** @typedef PPGMPAGEMAPTLB
2057	* The page mapper TLB pointer type for the current context. */
2058	/** @typedef PPGMPAGEMAPTLB
2059	* The page mapper TLB entry pointer type for the current context. */
2060	/** @typedef PPGMPAGEMAPTLB
2061	* The page mapper TLB entry pointer pointer type for the current context. */
2062	/** @def PGM_PAGEMAPTLB_ENTRIES
2063	* The number of TLB entries in the page mapper TLB for the current context. */
2064	/** @def PGM_PAGEMAPTLB_IDX
2065	* Calculate the TLB index for a guest physical address.
2066	* @returns The TLB index.
2067	* @param GCPhys The guest physical address. */
2068	/** @typedef PPGMPAGEMAP
2069	* Pointer to a page mapper unit for current context. */
2070	/** @typedef PPPGMPAGEMAP
2071	* Pointer to a page mapper unit pointer for current context. */
2072	#ifdef IN_RC
2073	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2074	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2075	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2076	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2077	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2078	typedef void * PPGMPAGEMAP;
2079	typedef void ** PPPGMPAGEMAP;
2080	//#elif IN_RING0
2081	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2082	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2083	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2084	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2085	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2086	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2087	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2088	#else
2089	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2090	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2091	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2092	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2093	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2094	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2095	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2096	#endif
2097	/** @} */
2098
2099
2100	/** @name PGM Pool Indexes.
2101	* Aka. the unique shadow page identifier.
2102	* @{ */
2103	/** NIL page pool IDX. */
2104	#define NIL_PGMPOOL_IDX 0
2105	/** The first normal index. There used to be 5 fictive pages up front, now
2106	* there is only the NIL page. */
2107	#define PGMPOOL_IDX_FIRST 1
2108	/** The last valid index. (inclusive, 14 bits) */
2109	#define PGMPOOL_IDX_LAST 0x3fff
2110	/** @} */
2111
2112	/** The NIL index for the parent chain. */
2113	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2114	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2115
2116	/**
2117	* Node in the chain linking a shadowed page to it's parent (user).
2118	*/
2119	#pragma pack(1)
2120	typedef struct PGMPOOLUSER
2121	{
2122	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2123	uint16_t iNext;
2124	/** The user page index. */
2125	uint16_t iUser;
2126	/** Index into the user table. */
2127	uint32_t iUserTable;
2128	} PGMPOOLUSER, *PPGMPOOLUSER;
2129	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2130	#pragma pack()
2131
2132
2133	/** The NIL index for the phys ext chain. */
2134	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2135	/** The NIL pte index for a phys ext chain slot. */
2136	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2137
2138	/**
2139	* Node in the chain of physical cross reference extents.
2140	* @todo Calling this an 'extent' is not quite right, find a better name.
2141	* @todo find out the optimal size of the aidx array
2142	*/
2143	#pragma pack(1)
2144	typedef struct PGMPOOLPHYSEXT
2145	{
2146	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2147	uint16_t iNext;
2148	/** Alignment. */
2149	uint16_t u16Align;
2150	/** The user page index. */
2151	uint16_t aidx[3];
2152	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2153	uint16_t apte[3];
2154	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2155	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2156	#pragma pack()
2157
2158
2159	/**
2160	* The kind of page that's being shadowed.
2161	*/
2162	typedef enum PGMPOOLKIND
2163	{
2164	/** The virtual invalid 0 entry. */
2165	PGMPOOLKIND_INVALID = 0,
2166	/** The entry is free (=unused). */
2167	PGMPOOLKIND_FREE,
2168
2169	/** Shw: 32-bit page table; Gst: no paging. */
2170	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2171	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2172	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2173	/** Shw: 32-bit page table; Gst: 4MB page. */
2174	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2175	/** Shw: PAE page table; Gst: no paging. */
2176	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2177	/** Shw: PAE page table; Gst: 32-bit page table. */
2178	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2179	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2180	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2181	/** Shw: PAE page table; Gst: PAE page table. */
2182	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2183	/** Shw: PAE page table; Gst: 2MB page. */
2184	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2185
2186	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2187	PGMPOOLKIND_32BIT_PD,
2188	/** Shw: 32-bit page directory. Gst: no paging. */
2189	PGMPOOLKIND_32BIT_PD_PHYS,
2190	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2191	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2192	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2193	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2194	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2195	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2196	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2197	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2198	/** Shw: PAE page directory; Gst: PAE page directory. */
2199	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2200	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2201	PGMPOOLKIND_PAE_PD_PHYS,
2202
2203	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2204	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2205	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2206	PGMPOOLKIND_PAE_PDPT,
2207	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2208	PGMPOOLKIND_PAE_PDPT_PHYS,
2209
2210	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2211	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2212	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2213	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2214	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2215	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2216	/** Shw: 64-bit page directory table; Gst: no paging. */
2217	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2218
2219	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2220	PGMPOOLKIND_64BIT_PML4,
2221
2222	/** Shw: EPT page directory pointer table; Gst: no paging. */
2223	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2224	/** Shw: EPT page directory table; Gst: no paging. */
2225	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2226	/** Shw: EPT page table; Gst: no paging. */
2227	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2228
2229	/** Shw: Root Nested paging table. */
2230	PGMPOOLKIND_ROOT_NESTED,
2231
2232	/** The last valid entry. */
2233	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2234	} PGMPOOLKIND;
2235
2236	/**
2237	* The access attributes of the page; only applies to big pages.
2238	*/
2239	typedef enum
2240	{
2241	PGMPOOLACCESS_DONTCARE = 0,
2242	PGMPOOLACCESS_USER_RW,
2243	PGMPOOLACCESS_USER_R,
2244	PGMPOOLACCESS_USER_RW_NX,
2245	PGMPOOLACCESS_USER_R_NX,
2246	PGMPOOLACCESS_SUPERVISOR_RW,
2247	PGMPOOLACCESS_SUPERVISOR_R,
2248	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2249	PGMPOOLACCESS_SUPERVISOR_R_NX
2250	} PGMPOOLACCESS;
2251
2252	/**
2253	* The tracking data for a page in the pool.
2254	*/
2255	typedef struct PGMPOOLPAGE
2256	{
2257	/** AVL node code with the (HC) physical address of this page. */
2258	AVLOHCPHYSNODECORE Core;
2259	/** Pointer to the R3 mapping of the page. */
2260	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2261	R3PTRTYPE(void *) pvPageR3;
2262	#else
2263	R3R0PTRTYPE(void *) pvPageR3;
2264	#endif
2265	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2266	uint32_t Alignment0;
2267	#endif
2268	/** The guest physical address. */
2269	RTGCPHYS GCPhys;
2270	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2271	uint8_t enmKind;
2272	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2273	uint8_t enmAccess;
2274	/** This supplements enmKind and enmAccess */
2275	bool fA20Enabled : 1;
2276
2277	/** Used to indicate that the page is zeroed. */
2278	bool fZeroed : 1;
2279	/** Used to indicate that a PT has non-global entries. */
2280	bool fSeenNonGlobal : 1;
2281	/** Used to indicate that we're monitoring writes to the guest page. */
2282	bool fMonitored : 1;
2283	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2284	* (All pages are in the age list.) */
2285	bool fCached : 1;
2286	/** This is used by the R3 access handlers when invoked by an async thread.
2287	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2288	bool volatile fReusedFlushPending : 1;
2289	/** Used to mark the page as dirty (write monitoring is temporarily
2290	* off). */
2291	bool fDirty : 1;
2292	bool fPadding1 : 1;
2293	bool fPadding2;
2294
2295	/** The index of this page. */
2296	uint16_t idx;
2297	/** The next entry in the list this page currently resides in.
2298	* It's either in the free list or in the GCPhys hash. */
2299	uint16_t iNext;
2300	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2301	uint16_t iUserHead;
2302	/** The number of present entries. */
2303	uint16_t cPresent;
2304	/** The first entry in the table which is present. */
2305	uint16_t iFirstPresent;
2306	/** The number of modifications to the monitored page. */
2307	uint16_t cModifications;
2308	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2309	uint16_t iModifiedNext;
2310	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2311	uint16_t iModifiedPrev;
2312	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2313	uint16_t iMonitoredNext;
2314	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2315	uint16_t iMonitoredPrev;
2316	/** The next page in the age list. */
2317	uint16_t iAgeNext;
2318	/** The previous page in the age list. */
2319	uint16_t iAgePrev;
2320	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2321	uint8_t idxDirtyEntry;
2322
2323	/** @name Access handler statistics to determine whether the guest is
2324	* (re)initializing a page table.
2325	* @{ */
2326	RTGCPTR GCPtrLastAccessHandlerRip;
2327	RTGCPTR GCPtrLastAccessHandlerFault;
2328	uint64_t cLastAccessHandler;
2329	/** @} */
2330	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2331	uint32_t volatile cLocked;
2332	#if GC_ARCH_BITS == 64
2333	uint32_t u32Alignment3;
2334	#endif
2335	# ifdef VBOX_STRICT
2336	RTGCPTR GCPtrDirtyFault;
2337	# endif
2338	} PGMPOOLPAGE;
2339	/** Pointer to a pool page. */
2340	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2341	/** Pointer to a const pool page. */
2342	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2343	/** Pointer to a pool page pointer. */
2344	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2345
2346
2347	/** The hash table size. */
2348	# define PGMPOOL_HASH_SIZE 0x40
2349	/** The hash function. */
2350	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2351
2352
2353	/**
2354	* The shadow page pool instance data.
2355	*
2356	* It's all one big allocation made at init time, except for the
2357	* pages that is. The user nodes follows immediately after the
2358	* page structures.
2359	*/
2360	typedef struct PGMPOOL
2361	{
2362	/** The VM handle - R3 Ptr. */
2363	PVMR3 pVMR3;
2364	/** The VM handle - R0 Ptr. */
2365	PVMR0 pVMR0;
2366	/** The VM handle - RC Ptr. */
2367	PVMRC pVMRC;
2368	/** The max pool size. This includes the special IDs. */
2369	uint16_t cMaxPages;
2370	/** The current pool size. */
2371	uint16_t cCurPages;
2372	/** The head of the free page list. */
2373	uint16_t iFreeHead;
2374	/* Padding. */
2375	uint16_t u16Padding;
2376	/** Head of the chain of free user nodes. */
2377	uint16_t iUserFreeHead;
2378	/** The number of user nodes we've allocated. */
2379	uint16_t cMaxUsers;
2380	/** The number of present page table entries in the entire pool. */
2381	uint32_t cPresent;
2382	/** Pointer to the array of user nodes - RC pointer. */
2383	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2384	/** Pointer to the array of user nodes - R3 pointer. */
2385	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2386	/** Pointer to the array of user nodes - R0 pointer. */
2387	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2388	/** Head of the chain of free phys ext nodes. */
2389	uint16_t iPhysExtFreeHead;
2390	/** The number of user nodes we've allocated. */
2391	uint16_t cMaxPhysExts;
2392	/** Pointer to the array of physical xref extent - RC pointer. */
2393	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2394	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2395	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2396	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2397	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2398	/** Hash table for GCPhys addresses. */
2399	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2400	/** The head of the age list. */
2401	uint16_t iAgeHead;
2402	/** The tail of the age list. */
2403	uint16_t iAgeTail;
2404	/** Set if the cache is enabled. */
2405	bool fCacheEnabled;
2406	/** Alignment padding. */
2407	bool afPadding1[3];
2408	/** Head of the list of modified pages. */
2409	uint16_t iModifiedHead;
2410	/** The current number of modified pages. */
2411	uint16_t cModifiedPages;
2412	/** Physical access handler type registration handle. */
2413	PGMPHYSHANDLERTYPE hAccessHandlerType;
2414	/** Next available slot (in aDirtyPages). */
2415	uint32_t idxFreeDirtyPage;
2416	/** Number of active dirty pages. */
2417	uint32_t cDirtyPages;
2418	/** Array of current dirty pgm pool page indices. */
2419	struct
2420	{
2421	uint16_t uIdx;
2422	uint16_t Alignment[3];
2423	uint64_t aPage[512];
2424	} aDirtyPages[16];
2425	/** The number of pages currently in use. */
2426	uint16_t cUsedPages;
2427	#ifdef VBOX_WITH_STATISTICS
2428	/** The high water mark for cUsedPages. */
2429	uint16_t cUsedPagesHigh;
2430	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2431	/** Profiling pgmPoolAlloc(). */
2432	STAMPROFILEADV StatAlloc;
2433	/** Profiling pgmR3PoolClearDoIt(). */
2434	STAMPROFILE StatClearAll;
2435	/** Profiling pgmR3PoolReset(). */
2436	STAMPROFILE StatR3Reset;
2437	/** Profiling pgmPoolFlushPage(). */
2438	STAMPROFILE StatFlushPage;
2439	/** Profiling pgmPoolFree(). */
2440	STAMPROFILE StatFree;
2441	/** Counting explicit flushes by PGMPoolFlushPage(). */
2442	STAMCOUNTER StatForceFlushPage;
2443	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2444	STAMCOUNTER StatForceFlushDirtyPage;
2445	/** Counting flushes for reused pages. */
2446	STAMCOUNTER StatForceFlushReused;
2447	/** Profiling time spent zeroing pages. */
2448	STAMPROFILE StatZeroPage;
2449	/** Profiling of pgmPoolTrackDeref. */
2450	STAMPROFILE StatTrackDeref;
2451	/** Profiling pgmTrackFlushGCPhysPT. */
2452	STAMPROFILE StatTrackFlushGCPhysPT;
2453	/** Profiling pgmTrackFlushGCPhysPTs. */
2454	STAMPROFILE StatTrackFlushGCPhysPTs;
2455	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2456	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2457	/** Number of times we've been out of user records. */
2458	STAMCOUNTER StatTrackFreeUpOneUser;
2459	/** Nr of flushed entries. */
2460	STAMCOUNTER StatTrackFlushEntry;
2461	/** Nr of updated entries. */
2462	STAMCOUNTER StatTrackFlushEntryKeep;
2463	/** Profiling deref activity related tracking GC physical pages. */
2464	STAMPROFILE StatTrackDerefGCPhys;
2465	/** Number of linear searches for a HCPhys in the ram ranges. */
2466	STAMCOUNTER StatTrackLinearRamSearches;
2467	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2468	STAMCOUNTER StamTrackPhysExtAllocFailures;
2469	/** Profiling the RC/R0 access handler. */
2470	STAMPROFILE StatMonitorRZ;
2471	/** Times we've failed interpreting the instruction. */
2472	STAMCOUNTER StatMonitorRZEmulateInstr;
2473	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2474	STAMPROFILE StatMonitorRZFlushPage;
2475	/* Times we've detected a page table reinit. */
2476	STAMCOUNTER StatMonitorRZFlushReinit;
2477	/** Counting flushes for pages that are modified too often. */
2478	STAMCOUNTER StatMonitorRZFlushModOverflow;
2479	/** Times we've detected fork(). */
2480	STAMCOUNTER StatMonitorRZFork;
2481	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2482	STAMPROFILE StatMonitorRZHandled;
2483	/** Times we've failed interpreting a patch code instruction. */
2484	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2485	/** Times we've failed interpreting a patch code instruction during flushing. */
2486	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2487	/** The number of times we've seen rep prefixes we can't handle. */
2488	STAMCOUNTER StatMonitorRZRepPrefix;
2489	/** Profiling the REP STOSD cases we've handled. */
2490	STAMPROFILE StatMonitorRZRepStosd;
2491	/** Nr of handled PT faults. */
2492	STAMCOUNTER StatMonitorRZFaultPT;
2493	/** Nr of handled PD faults. */
2494	STAMCOUNTER StatMonitorRZFaultPD;
2495	/** Nr of handled PDPT faults. */
2496	STAMCOUNTER StatMonitorRZFaultPDPT;
2497	/** Nr of handled PML4 faults. */
2498	STAMCOUNTER StatMonitorRZFaultPML4;
2499
2500	/** Profiling the R3 access handler. */
2501	STAMPROFILE StatMonitorR3;
2502	/** Times we've failed interpreting the instruction. */
2503	STAMCOUNTER StatMonitorR3EmulateInstr;
2504	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2505	STAMPROFILE StatMonitorR3FlushPage;
2506	/* Times we've detected a page table reinit. */
2507	STAMCOUNTER StatMonitorR3FlushReinit;
2508	/** Counting flushes for pages that are modified too often. */
2509	STAMCOUNTER StatMonitorR3FlushModOverflow;
2510	/** Times we've detected fork(). */
2511	STAMCOUNTER StatMonitorR3Fork;
2512	/** Profiling the R3 access we've handled (except REP STOSD). */
2513	STAMPROFILE StatMonitorR3Handled;
2514	/** The number of times we've seen rep prefixes we can't handle. */
2515	STAMCOUNTER StatMonitorR3RepPrefix;
2516	/** Profiling the REP STOSD cases we've handled. */
2517	STAMPROFILE StatMonitorR3RepStosd;
2518	/** Nr of handled PT faults. */
2519	STAMCOUNTER StatMonitorR3FaultPT;
2520	/** Nr of handled PD faults. */
2521	STAMCOUNTER StatMonitorR3FaultPD;
2522	/** Nr of handled PDPT faults. */
2523	STAMCOUNTER StatMonitorR3FaultPDPT;
2524	/** Nr of handled PML4 faults. */
2525	STAMCOUNTER StatMonitorR3FaultPML4;
2526	/** The number of times we're called in an async thread an need to flush. */
2527	STAMCOUNTER StatMonitorR3Async;
2528	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2529	STAMCOUNTER StatResetDirtyPages;
2530	/** Times we've called pgmPoolAddDirtyPage. */
2531	STAMCOUNTER StatDirtyPage;
2532	/** Times we've had to flush duplicates for dirty page management. */
2533	STAMCOUNTER StatDirtyPageDupFlush;
2534	/** Times we've had to flush because of overflow. */
2535	STAMCOUNTER StatDirtyPageOverFlowFlush;
2536
2537	/** The high water mark for cModifiedPages. */
2538	uint16_t cModifiedPagesHigh;
2539	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2540
2541	/** The number of cache hits. */
2542	STAMCOUNTER StatCacheHits;
2543	/** The number of cache misses. */
2544	STAMCOUNTER StatCacheMisses;
2545	/** The number of times we've got a conflict of 'kind' in the cache. */
2546	STAMCOUNTER StatCacheKindMismatches;
2547	/** Number of times we've been out of pages. */
2548	STAMCOUNTER StatCacheFreeUpOne;
2549	/** The number of cacheable allocations. */
2550	STAMCOUNTER StatCacheCacheable;
2551	/** The number of uncacheable allocations. */
2552	STAMCOUNTER StatCacheUncacheable;
2553	#else
2554	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2555	#endif
2556	/** The AVL tree for looking up a page by its HC physical address. */
2557	AVLOHCPHYSTREE HCPhysTree;
2558	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2559	/** Array of pages. (cMaxPages in length)
2560	* The Id is the index into thist array.
2561	*/
2562	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2563	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2564	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2565	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2566	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2567	#ifdef VBOX_WITH_STATISTICS
2568	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2569	#endif
2570	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2571
2572
2573	/** @def PGMPOOL_PAGE_2_PTR
2574	* Maps a pool page pool into the current context.
2575	*
2576	* @returns VBox status code.
2577	* @param a_pVM Pointer to the VM.
2578	* @param a_pPage The pool page.
2579	*
2580	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2581	* small page window employeed by that function. Be careful.
2582	* @remark There is no need to assert on the result.
2583	*/
2584	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2585	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2586	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2587	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2588	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2589	{
2590	AssertPtr(a_pPage);
2591	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2592	return a_pPage->pvPageR3;
2593	}
2594	#else
2595	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2596	#endif
2597
2598
2599	/** @def PGMPOOL_PAGE_2_PTR_V2
2600	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2601	*
2602	* @returns VBox status code.
2603	* @param a_pVM Pointer to the VM.
2604	* @param a_pVCpu The current CPU.
2605	* @param a_pPage The pool page.
2606	*
2607	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2608	* small page window employeed by that function. Be careful.
2609	* @remark There is no need to assert on the result.
2610	*/
2611	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2612	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2613	#else
2614	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2615	#endif
2616
2617
2618	/** @name Per guest page tracking data.
2619	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2620	* is to use more bits for it and split it up later on. But for now we'll play
2621	* safe and change as little as possible.
2622	*
2623	* The 16-bit word has two parts:
2624	*
2625	* The first 14-bit forms the @a idx field. It is either the index of a page in
2626	* the shadow page pool, or and index into the extent list.
2627	*
2628	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2629	* shadow page pool references to the page. If cRefs equals
2630	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2631	* (misnomer) table and not the shadow page pool.
2632	*
2633	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2634	* the 16-bit word.
2635	*
2636	* @{ */
2637	/** The shift count for getting to the cRefs part. */
2638	#define PGMPOOL_TD_CREFS_SHIFT 14
2639	/** The mask applied after shifting the tracking data down by
2640	* PGMPOOL_TD_CREFS_SHIFT. */
2641	#define PGMPOOL_TD_CREFS_MASK 0x3
2642	/** The cRefs value used to indicate that the idx is the head of a
2643	* physical cross reference list. */
2644	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2645	/** The shift used to get idx. */
2646	#define PGMPOOL_TD_IDX_SHIFT 0
2647	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2648	#define PGMPOOL_TD_IDX_MASK 0x3fff
2649	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2650	* simply too many mappings of this page. */
2651	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2652
2653	/** @def PGMPOOL_TD_MAKE
2654	* Makes a 16-bit tracking data word.
2655	*
2656	* @returns tracking data.
2657	* @param cRefs The @a cRefs field. Must be within bounds!
2658	* @param idx The @a idx field. Must also be within bounds! */
2659	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2660
2661	/** @def PGMPOOL_TD_GET_CREFS
2662	* Get the @a cRefs field from a tracking data word.
2663	*
2664	* @returns The @a cRefs field
2665	* @param u16 The tracking data word.
2666	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2667	* non-zero @a u16. */
2668	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2669
2670	/** @def PGMPOOL_TD_GET_IDX
2671	* Get the @a idx field from a tracking data word.
2672	*
2673	* @returns The @a idx field
2674	* @param u16 The tracking data word. */
2675	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2676	/** @} */
2677
2678
2679
2680	/** @name A20 gate macros
2681	* @{ */
2682	#define PGM_WITH_A20
2683	#ifdef PGM_WITH_A20
2684	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2685	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2686	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2687	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2688	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2689	#else
2690	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2691	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2692	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2693	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2694	#endif
2695	/** @} */
2696
2697
2698	/**
2699	* Roots and anchors for trees and list employing self relative offsets as
2700	* pointers.
2701	*
2702	* When using self-relative offsets instead of pointers, the offsets needs to be
2703	* the same in all offsets. Thus the roots and anchors needs to live on the
2704	* hyper heap just like the nodes.
2705	*/
2706	typedef struct PGMTREES
2707	{
2708	/** Physical access handlers (AVL range+offsetptr tree). */
2709	AVLROGCPHYSTREE PhysHandlers;
2710	/** Virtual access handlers (AVL range + GC ptr tree). */
2711	AVLROGCPTRTREE VirtHandlers;
2712	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2713	AVLROGCPHYSTREE PhysToVirtHandlers;
2714	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2715	AVLROGCPTRTREE HyperVirtHandlers;
2716	/** List of physical access handler types (offset pointers) of type
2717	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2718	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2719	/** List of virtual access handler types (offset pointers) of type
2720	* PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2721	RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2722	} PGMTREES;
2723	/** Pointer to PGM trees. */
2724	typedef PGMTREES *PPGMTREES;
2725
2726
2727	/**
2728	* Page fault guest state for the AMD64 paging mode.
2729	*/
2730	typedef struct PGMPTWALKCORE
2731	{
2732	/** The guest virtual address that is being resolved by the walk
2733	* (input). */
2734	RTGCPTR GCPtr;
2735
2736	/** The guest physical address that is the result of the walk.
2737	* @remarks only valid if fSucceeded is set. */
2738	RTGCPHYS GCPhys;
2739
2740	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2741	bool fSucceeded;
2742	/** The level problem arrised at.
2743	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2744	* level 8. This is 0 on success. */
2745	uint8_t uLevel;
2746	/** Set if the page isn't present. */
2747	bool fNotPresent;
2748	/** Encountered a bad physical address. */
2749	bool fBadPhysAddr;
2750	/** Set if there was reserved bit violations. */
2751	bool fRsvdError;
2752	/** Set if it involves a big page (2/4 MB). */
2753	bool fBigPage;
2754	/** Set if it involves a gigantic page (1 GB). */
2755	bool fGigantPage;
2756	/** The effect X86_PTE_US flag for the address. */
2757	bool fEffectiveUS;
2758	/** The effect X86_PTE_RW flag for the address. */
2759	bool fEffectiveRW;
2760	/** The effect X86_PTE_NX flag for the address. */
2761	bool fEffectiveNX;
2762	} PGMPTWALKCORE;
2763
2764
2765	/**
2766	* Guest page table walk for the AMD64 mode.
2767	*/
2768	typedef struct PGMPTWALKGSTAMD64
2769	{
2770	/** The common core. */
2771	PGMPTWALKCORE Core;
2772
2773	PX86PML4 pPml4;
2774	PX86PML4E pPml4e;
2775	X86PML4E Pml4e;
2776
2777	PX86PDPT pPdpt;
2778	PX86PDPE pPdpe;
2779	X86PDPE Pdpe;
2780
2781	PX86PDPAE pPd;
2782	PX86PDEPAE pPde;
2783	X86PDEPAE Pde;
2784
2785	PX86PTPAE pPt;
2786	PX86PTEPAE pPte;
2787	X86PTEPAE Pte;
2788	} PGMPTWALKGSTAMD64;
2789	/** Pointer to a AMD64 guest page table walk. */
2790	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2791	/** Pointer to a const AMD64 guest page table walk. */
2792	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2793
2794	/**
2795	* Guest page table walk for the PAE mode.
2796	*/
2797	typedef struct PGMPTWALKGSTPAE
2798	{
2799	/** The common core. */
2800	PGMPTWALKCORE Core;
2801
2802	PX86PDPT pPdpt;
2803	PX86PDPE pPdpe;
2804	X86PDPE Pdpe;
2805
2806	PX86PDPAE pPd;
2807	PX86PDEPAE pPde;
2808	X86PDEPAE Pde;
2809
2810	PX86PTPAE pPt;
2811	PX86PTEPAE pPte;
2812	X86PTEPAE Pte;
2813	} PGMPTWALKGSTPAE;
2814	/** Pointer to a PAE guest page table walk. */
2815	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2816	/** Pointer to a const AMD64 guest page table walk. */
2817	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2818
2819	/**
2820	* Guest page table walk for the 32-bit mode.
2821	*/
2822	typedef struct PGMPTWALKGST32BIT
2823	{
2824	/** The common core. */
2825	PGMPTWALKCORE Core;
2826
2827	PX86PD pPd;
2828	PX86PDE pPde;
2829	X86PDE Pde;
2830
2831	PX86PT pPt;
2832	PX86PTE pPte;
2833	X86PTE Pte;
2834	} PGMPTWALKGST32BIT;
2835	/** Pointer to a 32-bit guest page table walk. */
2836	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2837	/** Pointer to a const 32-bit guest page table walk. */
2838	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2839
2840	/**
2841	* Which part of PGMPTWALKGST that is valid.
2842	*/
2843	typedef enum PGMPTWALKGSTTYPE
2844	{
2845	/** Customary invalid 0 value. */
2846	PGMPTWALKGSTTYPE_INVALID = 0,
2847	/** PGMPTWALKGST::u.Amd64 is valid. */
2848	PGMPTWALKGSTTYPE_AMD64,
2849	/** PGMPTWALKGST::u.Pae is valid. */
2850	PGMPTWALKGSTTYPE_PAE,
2851	/** PGMPTWALKGST::u.Legacy is valid. */
2852	PGMPTWALKGSTTYPE_32BIT,
2853	/** Customary 32-bit type hack. */
2854	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2855	} PGMPTWALKGSTTYPE;
2856
2857	/**
2858	* Combined guest page table walk result.
2859	*/
2860	typedef struct PGMPTWALKGST
2861	{
2862	union
2863	{
2864	/** The page walker core - always valid. */
2865	PGMPTWALKCORE Core;
2866	/** The page walker for AMD64. */
2867	PGMPTWALKGSTAMD64 Amd64;
2868	/** The page walker for PAE (32-bit). */
2869	PGMPTWALKGSTPAE Pae;
2870	/** The page walker for 32-bit paging (called legacy due to C naming
2871	* convension). */
2872	PGMPTWALKGST32BIT Legacy;
2873	} u;
2874	/** Indicates which part of the union is valid. */
2875	PGMPTWALKGSTTYPE enmType;
2876	} PGMPTWALKGST;
2877	/** Pointer to a combined guest page table walk result. */
2878	typedef PGMPTWALKGST *PPGMPTWALKGST;
2879	/** Pointer to a read-only combined guest page table walk result. */
2880	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2881
2882
2883	/** @name Paging mode macros
2884	* @{
2885	*/
2886	#ifdef IN_RC
2887	# define PGM_CTX(a,b) a##RC##b
2888	# define PGM_CTX_STR(a,b) a "GC" b
2889	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2890	#else
2891	# ifdef IN_RING3
2892	# define PGM_CTX(a,b) a##R3##b
2893	# define PGM_CTX_STR(a,b) a "R3" b
2894	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2895	# else
2896	# define PGM_CTX(a,b) a##R0##b
2897	# define PGM_CTX_STR(a,b) a "R0" b
2898	# define PGM_CTX_DECL(type) VMMDECL(type)
2899	# endif
2900	#endif
2901
2902	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2903	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2904	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2905	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2906	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2907	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2908	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2909	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2910	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2911	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2912	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2913	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2914	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2915	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2916	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2917	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2918	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2919
2920	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2921	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2922	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2923	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2924	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2925	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2926	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2927	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2928	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2929	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2930	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2931	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2932	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2933	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2934	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2935	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2936	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2937
2938	/* Shw_Gst */
2939	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2940	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2941	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2942	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2943	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2944	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2945	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2946	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2947	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2948	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2949	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2950	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2951	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2952	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2953	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2954	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2955	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2956	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2957	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2958
2959	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2960	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2961	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2962	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2963	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2964	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2965	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2966	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2967	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2968	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2969	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2970	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2971	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2972	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2973	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2974	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2975	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2976	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2977	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2978	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2979	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2980	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2981	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2982	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2983	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2984	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2985	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2986	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2987	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2988	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2989	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2990	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2991	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2992	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2993	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2994	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2995	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2996
2997	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2998	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2999	/** @} */
3000
3001	/**
3002	* Data for each paging mode.
3003	*/
3004	typedef struct PGMMODEDATA
3005	{
3006	/** The guest mode type. */
3007	uint32_t uGstType;
3008	/** The shadow mode type. */
3009	uint32_t uShwType;
3010
3011	/** @name Function pointers for Shadow paging.
3012	* @{
3013	*/
3014	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3015	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3016	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3017	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3018
3019	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3020	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3021
3022	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3023	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3024	/** @} */
3025
3026	/** @name Function pointers for Guest paging.
3027	* @{
3028	*/
3029	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3030	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3031	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3032	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3033	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3034	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3035	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3036	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3037	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3038	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3039	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3040	/** @} */
3041
3042	/** @name Function pointers for Both Shadow and Guest paging.
3043	* @{
3044	*/
3045	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3046	/* no pfnR3BthTrap0eHandler */
3047	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3048	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3049	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3050	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3051	#ifdef VBOX_STRICT
3052	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3053	#endif
3054	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3055	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3056
3057	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3058	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3059	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3060	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3061	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3062	#ifdef VBOX_STRICT
3063	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3064	#endif
3065	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3066	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3067
3068	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3069	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3070	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3071	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3072	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3073	#ifdef VBOX_STRICT
3074	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3075	#endif
3076	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3077	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3078	/** @} */
3079	} PGMMODEDATA, *PPGMMODEDATA;
3080
3081
3082	#ifdef VBOX_WITH_STATISTICS
3083	/**
3084	* PGM statistics.
3085	*
3086	* These lives on the heap when compiled in as they would otherwise waste
3087	* unnecessary space in release builds.
3088	*/
3089	typedef struct PGMSTATS
3090	{
3091	/* R3 only: */
3092	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3093	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3094
3095	/* R3+RZ */
3096	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3097	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3098	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3099	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3100	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3101	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3102	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3103	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3104	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3105	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3106	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3107	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3108	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3109	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3110	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3111	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3112	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3113	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3114	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3115	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3116	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3117	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3118	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3119	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3120	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3121	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3122	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3123	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3124	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3125	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3126	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3127	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3128
3129	/* RC only: */
3130	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3131	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3132
3133	STAMCOUNTER StatRZPhysRead;
3134	STAMCOUNTER StatRZPhysReadBytes;
3135	STAMCOUNTER StatRZPhysWrite;
3136	STAMCOUNTER StatRZPhysWriteBytes;
3137	STAMCOUNTER StatR3PhysRead;
3138	STAMCOUNTER StatR3PhysReadBytes;
3139	STAMCOUNTER StatR3PhysWrite;
3140	STAMCOUNTER StatR3PhysWriteBytes;
3141	STAMCOUNTER StatRCPhysRead;
3142	STAMCOUNTER StatRCPhysReadBytes;
3143	STAMCOUNTER StatRCPhysWrite;
3144	STAMCOUNTER StatRCPhysWriteBytes;
3145
3146	STAMCOUNTER StatRZPhysSimpleRead;
3147	STAMCOUNTER StatRZPhysSimpleReadBytes;
3148	STAMCOUNTER StatRZPhysSimpleWrite;
3149	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3150	STAMCOUNTER StatR3PhysSimpleRead;
3151	STAMCOUNTER StatR3PhysSimpleReadBytes;
3152	STAMCOUNTER StatR3PhysSimpleWrite;
3153	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3154	STAMCOUNTER StatRCPhysSimpleRead;
3155	STAMCOUNTER StatRCPhysSimpleReadBytes;
3156	STAMCOUNTER StatRCPhysSimpleWrite;
3157	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3158
3159	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3160	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3161	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3162	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3163	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3164	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3165	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3166
3167	/** Time spent by the host OS for large page allocation. */
3168	STAMPROFILE StatAllocLargePage;
3169	/** Time spent clearing the newly allocated large pages. */
3170	STAMPROFILE StatClearLargePage;
3171	/** The number of times allocating a large pages takes more than the allowed period. */
3172	STAMCOUNTER StatLargePageOverflow;
3173	/** pgmPhysIsValidLargePage profiling - R3 */
3174	STAMPROFILE StatR3IsValidLargePage;
3175	/** pgmPhysIsValidLargePage profiling - RZ*/
3176	STAMPROFILE StatRZIsValidLargePage;
3177
3178	STAMPROFILE StatChunkAging;
3179	STAMPROFILE StatChunkFindCandidate;
3180	STAMPROFILE StatChunkUnmap;
3181	STAMPROFILE StatChunkMap;
3182	} PGMSTATS;
3183	#endif /* VBOX_WITH_STATISTICS */
3184
3185
3186	/**
3187	* Converts a PGM pointer into a VM pointer.
3188	* @returns Pointer to the VM structure the PGM is part of.
3189	* @param pPGM Pointer to PGM instance data.
3190	*/
3191	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3192
3193	/**
3194	* PGM Data (part of VM)
3195	*/
3196	typedef struct PGM
3197	{
3198	/** Offset to the VM structure. */
3199	int32_t offVM;
3200	/** Offset of the PGMCPU structure relative to VMCPU. */
3201	int32_t offVCpuPGM;
3202
3203	/** @cfgm{/RamPreAlloc, boolean, false}
3204	* Indicates whether the base RAM should all be allocated before starting
3205	* the VM (default), or if it should be allocated when first written to.
3206	*/
3207	bool fRamPreAlloc;
3208	/** Indicates whether write monitoring is currently in use.
3209	* This is used to prevent conflicts between live saving and page sharing
3210	* detection. */
3211	bool fPhysWriteMonitoringEngaged;
3212	/** Set if the CPU has less than 52-bit physical address width.
3213	* This is used */
3214	bool fLessThan52PhysicalAddressBits;
3215	/** Set when nested paging is active.
3216	* This is meant to save calls to HMIsNestedPagingActive and let the
3217	* compilers optimize the code better. Whether we use nested paging or
3218	* not is something we find out during VMM initialization and we won't
3219	* change this later on. */
3220	bool fNestedPaging;
3221	/** The host paging mode. (This is what SUPLib reports.) */
3222	SUPPAGINGMODE enmHostMode;
3223	/** We're not in a state which permits writes to guest memory.
3224	* (Only used in strict builds.) */
3225	bool fNoMorePhysWrites;
3226	/** Set if PCI passthrough is enabled. */
3227	bool fPciPassthrough;
3228	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3229	uint8_t cMmio2Regions;
3230	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3231	bool afAlignment1[2];
3232
3233	/** Indicates that PGMR3FinalizeMappings has been called and that further
3234	* PGMR3MapIntermediate calls will be rejected. */
3235	bool fFinalizedMappings;
3236	/** If set no conflict checks are required. */
3237	bool fMappingsFixed;
3238	/** If set if restored as fixed but we were unable to re-fixate at the old
3239	* location because of room or address incompatibilities. */
3240	bool fMappingsFixedRestored;
3241	/** Size of fixed mapping.
3242	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3243	uint32_t cbMappingFixed;
3244	/** Generation ID for the RAM ranges. This member is incremented everytime
3245	* a RAM range is linked or unlinked. */
3246	uint32_t volatile idRamRangesGen;
3247
3248	/** Base address (GC) of fixed mapping.
3249	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3250	RTGCPTR GCPtrMappingFixed;
3251	/** The address of the previous RAM range mapping. */
3252	RTGCPTR GCPtrPrevRamRangeMapping;
3253
3254	/** Physical access handler type for ROM protection. */
3255	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3256	/** Alignment padding. */
3257	uint32_t u32Padding;
3258
3259	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3260	RTGCPHYS GCPhys4MBPSEMask;
3261	/** Mask containing the invalid bits of a guest physical address.
3262	* @remarks this does not stop at bit 52. */
3263	RTGCPHYS GCPhysInvAddrMask;
3264
3265
3266	/** RAM range TLB for R3. */
3267	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3268	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3269	* This is sorted by physical address and contains no overlapping ranges. */
3270	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3271	/** Root of the RAM range search tree for ring-3. */
3272	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3273	/** PGM offset based trees - R3 Ptr. */
3274	R3PTRTYPE(PPGMTREES) pTreesR3;
3275	/** Caching the last physical handler we looked up in R3. */
3276	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3277	/** Shadow Page Pool - R3 Ptr. */
3278	R3PTRTYPE(PPGMPOOL) pPoolR3;
3279	/** Linked list of GC mappings - for HC.
3280	* The list is sorted ascending on address. */
3281	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3282	/** Pointer to the list of ROM ranges - for R3.
3283	* This is sorted by physical address and contains no overlapping ranges. */
3284	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3285	/** Pointer to the list of MMIO2 ranges - for R3.
3286	* Registration order. */
3287	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3288	/** Pointer to SHW+GST mode data (function pointers).
3289	* The index into this table is made up from */
3290	R3PTRTYPE(PPGMMODEDATA) paModeData;
3291	RTR3PTR R3PtrAlignment0;
3292	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3293	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3294
3295	/** RAM range TLB for R0. */
3296	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3297	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3298	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3299	/** Root of the RAM range search tree for ring-0. */
3300	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3301	/** PGM offset based trees - R0 Ptr. */
3302	R0PTRTYPE(PPGMTREES) pTreesR0;
3303	/** Caching the last physical handler we looked up in R0. */
3304	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3305	/** Shadow Page Pool - R0 Ptr. */
3306	R0PTRTYPE(PPGMPOOL) pPoolR0;
3307	/** Linked list of GC mappings - for R0.
3308	* The list is sorted ascending on address. */
3309	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3310	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3311	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3312	RTR0PTR R0PtrAlignment0;
3313	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3314	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3315
3316	/** RAM range TLB for RC. */
3317	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3318	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3319	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3320	/** Root of the RAM range search tree for raw-mode context. */
3321	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3322	/** PGM offset based trees - RC Ptr. */
3323	RCPTRTYPE(PPGMTREES) pTreesRC;
3324	/** Caching the last physical handler we looked up in RC. */
3325	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3326	/** Shadow Page Pool - RC Ptr. */
3327	RCPTRTYPE(PPGMPOOL) pPoolRC;
3328	/** Linked list of GC mappings - for RC.
3329	* The list is sorted ascending on address. */
3330	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3331	/** RC pointer corresponding to PGM::pRomRangesR3. */
3332	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3333	RTRCPTR RCPtrAlignment0;
3334	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3335	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3336	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3337	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3338
3339
3340	/** Pointer to the 5 page CR3 content mapping.
3341	* The first page is always the CR3 (in some form) while the 4 other pages
3342	* are used of the PDs in PAE mode. */
3343	RTGCPTR GCPtrCR3Mapping;
3344
3345	/** @name Intermediate Context
3346	* @{ */
3347	/** Pointer to the intermediate page directory - Normal. */
3348	R3PTRTYPE(PX86PD) pInterPD;
3349	/** Pointer to the intermediate page tables - Normal.
3350	* There are two page tables, one for the identity mapping and one for
3351	* the host context mapping (of the core code). */
3352	R3PTRTYPE(PX86PT) apInterPTs[2];
3353	/** Pointer to the intermediate page tables - PAE. */
3354	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3355	/** Pointer to the intermediate page directory - PAE. */
3356	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3357	/** Pointer to the intermediate page directory - PAE. */
3358	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3359	/** Pointer to the intermediate page-map level 4 - AMD64. */
3360	R3PTRTYPE(PX86PML4) pInterPaePML4;
3361	/** Pointer to the intermediate page directory - AMD64. */
3362	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3363	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3364	RTHCPHYS HCPhysInterPD;
3365	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3366	RTHCPHYS HCPhysInterPaePDPT;
3367	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3368	RTHCPHYS HCPhysInterPaePML4;
3369	/** @} */
3370
3371	/** Base address of the dynamic page mapping area.
3372	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3373	*
3374	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3375	* work out. Some cleaning up of the initialization that would
3376	* remove this memory is yet to be done...
3377	*/
3378	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3379	/** The address of the raw-mode context mapping cache. */
3380	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3381	/** The address of the ring-0 mapping cache if we're making use of it. */
3382	RTR0PTR pvR0DynMapUsed;
3383
3384	/** Hack: Number of deprecated page mapping locks taken by the current lock
3385	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3386	uint32_t cDeprecatedPageLocks;
3387	#if HC_ARCH_BITS == 64
3388	/** Alignment padding. */
3389	uint32_t u32Alignment2;
3390	#endif
3391
3392
3393	/** PGM critical section.
3394	* This protects the physical & virtual access handlers, ram ranges,
3395	* and the page flag updating (some of it anyway).
3396	*/
3397	PDMCRITSECT CritSectX;
3398
3399	/**
3400	* Data associated with managing the ring-3 mappings of the allocation chunks.
3401	*/
3402	struct
3403	{
3404	/** The chunk tree, ordered by chunk id. */
3405	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3406	R3PTRTYPE(PAVLU32NODECORE) pTree;
3407	#else
3408	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3409	#endif
3410	#if HC_ARCH_BITS == 32
3411	uint32_t u32Alignment0;
3412	#endif
3413	/** The chunk mapping TLB. */
3414	PGMCHUNKR3MAPTLB Tlb;
3415	/** The number of mapped chunks. */
3416	uint32_t c;
3417	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3418	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3419	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3420	uint32_t cMax;
3421	/** The current time. This is incremented whenever a chunk is inserted. */
3422	uint32_t iNow;
3423	/** Alignment padding. */
3424	uint32_t u32Alignment1;
3425	} ChunkR3Map;
3426
3427	/**
3428	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3429	*/
3430	PGMPAGER3MAPTLB PhysTlbHC;
3431
3432	/** @name The zero page.
3433	* @{ */
3434	/** The host physical address of the zero page. */
3435	RTHCPHYS HCPhysZeroPg;
3436	/** The ring-3 mapping of the zero page. */
3437	RTR3PTR pvZeroPgR3;
3438	/** The ring-0 mapping of the zero page. */
3439	RTR0PTR pvZeroPgR0;
3440	/** The GC mapping of the zero page. */
3441	RTRCPTR pvZeroPgRC;
3442	RTRCPTR RCPtrAlignment3;
3443	/** @}*/
3444
3445	/** @name The Invalid MMIO page.
3446	* This page is filled with 0xfeedface.
3447	* @{ */
3448	/** The host physical address of the invalid MMIO page. */
3449	RTHCPHYS HCPhysMmioPg;
3450	/** The host pysical address of the invalid MMIO page plus all invalid
3451	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3452	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3453	RTHCPHYS HCPhysInvMmioPg;
3454	/** The ring-3 mapping of the invalid MMIO page. */
3455	RTR3PTR pvMmioPgR3;
3456	#if HC_ARCH_BITS == 32
3457	RTR3PTR R3PtrAlignment4;
3458	#endif
3459	/** @} */
3460
3461
3462	/** The number of handy pages. */
3463	uint32_t cHandyPages;
3464
3465	/** The number of large handy pages. */
3466	uint32_t cLargeHandyPages;
3467
3468	/**
3469	* Array of handy pages.
3470	*
3471	* This array is used in a two way communication between pgmPhysAllocPage
3472	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3473	* an intermediary.
3474	*
3475	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3476	* (The current size of 32 pages, means 128 KB of handy memory.)
3477	*/
3478	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3479
3480	/**
3481	* Array of large handy pages. (currently size 1)
3482	*
3483	* This array is used in a two way communication between pgmPhysAllocLargePage
3484	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3485	* an intermediary.
3486	*/
3487	GMMPAGEDESC aLargeHandyPage[1];
3488
3489	/**
3490	* Live save data.
3491	*/
3492	struct
3493	{
3494	/** Per type statistics. */
3495	struct
3496	{
3497	/** The number of ready pages. */
3498	uint32_t cReadyPages;
3499	/** The number of dirty pages. */
3500	uint32_t cDirtyPages;
3501	/** The number of ready zero pages. */
3502	uint32_t cZeroPages;
3503	/** The number of write monitored pages. */
3504	uint32_t cMonitoredPages;
3505	} Rom,
3506	Mmio2,
3507	Ram;
3508	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3509	uint32_t cIgnoredPages;
3510	/** Indicates that a live save operation is active. */
3511	bool fActive;
3512	/** Padding. */
3513	bool afReserved[2];
3514	/** The next history index. */
3515	uint8_t iDirtyPagesHistory;
3516	/** History of the total amount of dirty pages. */
3517	uint32_t acDirtyPagesHistory[64];
3518	/** Short term dirty page average. */
3519	uint32_t cDirtyPagesShort;
3520	/** Long term dirty page average. */
3521	uint32_t cDirtyPagesLong;
3522	/** The number of saved pages. This is used to get some kind of estimate of the
3523	* link speed so we can decide when we're done. It is reset after the first
3524	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3525	* zero pages. */
3526	uint64_t cSavedPages;
3527	/** The nanosecond timestamp when cSavedPages was 0. */
3528	uint64_t uSaveStartNS;
3529	/** Pages per second (for statistics). */
3530	uint32_t cPagesPerSecond;
3531	uint32_t cAlignment;
3532	} LiveSave;
3533
3534	/** @name Error injection.
3535	* @{ */
3536	/** Inject handy page allocation errors pretending we're completely out of
3537	* memory. */
3538	bool volatile fErrInjHandyPages;
3539	/** Padding. */
3540	bool afReserved[3];
3541	/** @} */
3542
3543	/** @name Release Statistics
3544	* @{ */
3545	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3546	uint32_t cPrivatePages; /*< The number of private pages. /
3547	uint32_t cSharedPages; /*< The number of shared pages. /
3548	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3549	uint32_t cZeroPages; /*< The number of zero backed pages. /
3550	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3551	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3552	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3553	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3554	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3555	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3556	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3557	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3558	uint32_t cLargePages; /*< The number of large pages. /
3559	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3560	/* uint32_t aAlignment4[1]; */
3561
3562	/** The number of times we were forced to change the hypervisor region location. */
3563	STAMCOUNTER cRelocations;
3564
3565	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3566	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3567	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3568
3569	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3570	/** @} */
3571
3572	#ifdef VBOX_WITH_STATISTICS
3573	/** @name Statistics on the heap.
3574	* @{ */
3575	R3PTRTYPE(PGMSTATS *) pStatsR3;
3576	R0PTRTYPE(PGMSTATS *) pStatsR0;
3577	RCPTRTYPE(PGMSTATS *) pStatsRC;
3578	RTRCPTR RCPtrAlignment;
3579	/** @} */
3580	#endif
3581	} PGM;
3582	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3583	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3584	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3585	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3586	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3587	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3588	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3589	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3590	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3591	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3592	#endif /* !IN_TSTVMSTRUCTGC */
3593	/** Pointer to the PGM instance data. */
3594	typedef PGM *PPGM;
3595
3596
3597
3598	typedef struct PGMCPUSTATS
3599	{
3600	/* Common */
3601	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3602	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3603
3604	/* R0 only: */
3605	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3606	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3607
3608	/* RZ only: */
3609	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3610	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3611	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3612	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3613	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3614	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3615	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3616	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3617	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3618	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3619	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3620	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3621	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3622	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3623	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3624	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3625	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3626	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3627	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3628	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3629	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3630	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3631	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3632	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3633	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3634	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3635	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3636	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3637	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3638	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3639	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3640	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3641	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3642	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3643	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3644	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3645	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3646	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3647	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3648	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3649	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3650	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3651	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3652	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3653	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3654	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3655	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3656	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3657	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3658	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3659	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3660	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3661	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3662	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3663	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3664	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3665	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3666	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3667	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3668	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3669	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3670	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3671	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3672	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3673	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3674	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3675	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3676	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3677	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3678	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3679	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3680	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3681	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3682	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3683	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3684	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3685	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3686	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3687
3688	/* HC - R3 and (maybe) R0: */
3689
3690	/* RZ & R3: */
3691	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3692	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3693	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3694	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3695	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3696	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3697	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3698	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3699	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3700	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3701	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3702	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3703	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3704	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3705	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3706	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3707	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3708	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3709	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3710	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3711	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3712	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3713	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3714	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3715	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3716	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3717	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3718	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3719	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3720	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3721	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3722	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3723	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3724	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3725	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3726	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3727	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3728	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3729	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3730	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3731	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3732	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3733	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3734	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3735	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3736	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3737	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3738
3739	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3740	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3741	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3742	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3743	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3744	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3745	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3746	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3747	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3748	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3749	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3750	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3751	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3752	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3753	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3754	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3755	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3756	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3757	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3758	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3759	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3760	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3761	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3762	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3763	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3764	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3765	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3766	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3767	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3768	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3769	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3770	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3771	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3772	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3773	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3774	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3775	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3776	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3777	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3778	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3779	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3780	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3781	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3782	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3783	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3784	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3785	/** @} */
3786	} PGMCPUSTATS;
3787
3788
3789	/**
3790	* Converts a PGMCPU pointer into a VM pointer.
3791	* @returns Pointer to the VM structure the PGM is part of.
3792	* @param pPGM Pointer to PGMCPU instance data.
3793	*/
3794	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3795
3796	/**
3797	* Converts a PGMCPU pointer into a PGM pointer.
3798	* @returns Pointer to the VM structure the PGM is part of.
3799	* @param pPGM Pointer to PGMCPU instance data.
3800	*/
3801	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3802
3803	/**
3804	* PGMCPU Data (part of VMCPU).
3805	*/
3806	typedef struct PGMCPU
3807	{
3808	/** Offset to the VM structure. */
3809	int32_t offVM;
3810	/** Offset to the VMCPU structure. */
3811	int32_t offVCpu;
3812	/** Offset of the PGM structure relative to VMCPU. */
3813	int32_t offPGM;
3814	uint32_t uPadding0; /*< structure size alignment. /
3815
3816	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3817	/** Automatically tracked physical memory mapping set.
3818	* Ring-0 and strict raw-mode builds. */
3819	PGMMAPSET AutoSet;
3820	#endif
3821
3822	/** A20 gate mask.
3823	* Our current approach to A20 emulation is to let REM do it and don't bother
3824	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3825	* But whould need arrise, we'll subject physical addresses to this mask. */
3826	RTGCPHYS GCPhysA20Mask;
3827	/** A20 gate state - boolean! */
3828	bool fA20Enabled;
3829	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3830	bool fNoExecuteEnabled;
3831	/** Unused bits. */
3832	bool afUnused[2];
3833
3834	/** What needs syncing (PGM_SYNC_*).
3835	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3836	* PGMFlushTLB, and PGMR3Load. */
3837	uint32_t fSyncFlags;
3838
3839	/** The shadow paging mode. */
3840	PGMMODE enmShadowMode;
3841	/** The guest paging mode. */
3842	PGMMODE enmGuestMode;
3843
3844	/** The current physical address representing in the guest CR3 register. */
3845	RTGCPHYS GCPhysCR3;
3846
3847	/** @name 32-bit Guest Paging.
3848	* @{ */
3849	/** The guest's page directory, R3 pointer. */
3850	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3851	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3852	/** The guest's page directory, R0 pointer. */
3853	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3854	#endif
3855	/** The guest's page directory, static RC mapping. */
3856	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3857	/** Mask containing the MBZ bits of a big page PDE. */
3858	uint32_t fGst32BitMbzBigPdeMask;
3859	/** Set if the page size extension (PSE) is enabled. */
3860	bool fGst32BitPageSizeExtension;
3861	/** Alignment padding. */
3862	bool afAlignment2[3];
3863	/** @} */
3864
3865	/** @name PAE Guest Paging.
3866	* @{ */
3867	/** The guest's page directory pointer table, static RC mapping. */
3868	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3869	/** The guest's page directory pointer table, R3 pointer. */
3870	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3871	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3872	/** The guest's page directory pointer table, R0 pointer. */
3873	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3874	#endif
3875
3876	/** The guest's page directories, R3 pointers.
3877	* These are individual pointers and don't have to be adjacent.
3878	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3879	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3880	/** The guest's page directories, R0 pointers.
3881	* Same restrictions as apGstPaePDsR3. */
3882	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3883	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3884	#endif
3885	/** The guest's page directories, static GC mapping.
3886	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3887	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3888	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3889	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3890	* @todo Remove this and use aGstPaePdpeRegs instead? */
3891	RTGCPHYS aGCPhysGstPaePDs[4];
3892	/** The values of the 4 PDPE CPU registers (PAE). */
3893	X86PDPE aGstPaePdpeRegs[4];
3894	/** The physical addresses of the monitored guest page directories (PAE). */
3895	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3896	/** Mask containing the MBZ PTE bits. */
3897	uint64_t fGstPaeMbzPteMask;
3898	/** Mask containing the MBZ PDE bits. */
3899	uint64_t fGstPaeMbzPdeMask;
3900	/** Mask containing the MBZ big page PDE bits. */
3901	uint64_t fGstPaeMbzBigPdeMask;
3902	/** Mask containing the MBZ PDPE bits. */
3903	uint64_t fGstPaeMbzPdpeMask;
3904	/** @} */
3905
3906	/** @name AMD64 Guest Paging.
3907	* @{ */
3908	/** The guest's page directory pointer table, R3 pointer. */
3909	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3910	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3911	/** The guest's page directory pointer table, R0 pointer. */
3912	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3913	#else
3914	RTR0PTR alignment6b; /*< alignment equalizer. /
3915	#endif
3916	/** Mask containing the MBZ PTE bits. */
3917	uint64_t fGstAmd64MbzPteMask;
3918	/** Mask containing the MBZ PDE bits. */
3919	uint64_t fGstAmd64MbzPdeMask;
3920	/** Mask containing the MBZ big page PDE bits. */
3921	uint64_t fGstAmd64MbzBigPdeMask;
3922	/** Mask containing the MBZ PDPE bits. */
3923	uint64_t fGstAmd64MbzPdpeMask;
3924	/** Mask containing the MBZ big page PDPE bits. */
3925	uint64_t fGstAmd64MbzBigPdpeMask;
3926	/** Mask containing the MBZ PML4E bits. */
3927	uint64_t fGstAmd64MbzPml4eMask;
3928	/** Mask containing the PDPE bits that we shadow. */
3929	uint64_t fGstAmd64ShadowedPdpeMask;
3930	/** Mask containing the PML4E bits that we shadow. */
3931	uint64_t fGstAmd64ShadowedPml4eMask;
3932	/** @} */
3933
3934	/** @name PAE and AMD64 Guest Paging.
3935	* @{ */
3936	/** Mask containing the PTE bits that we shadow. */
3937	uint64_t fGst64ShadowedPteMask;
3938	/** Mask containing the PDE bits that we shadow. */
3939	uint64_t fGst64ShadowedPdeMask;
3940	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3941	uint64_t fGst64ShadowedBigPdeMask;
3942	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3943	uint64_t fGst64ShadowedBigPde4PteMask;
3944	/** @} */
3945
3946	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3947	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3948	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3949	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3950	/** Pointer to the page of the current active CR3 - RC Ptr. */
3951	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3952	# if HC_ARCH_BITS == 64
3953	RTRCPTR alignment6; /*< structure size alignment. /
3954	# endif
3955	/** @} */
3956
3957	/** @name Function pointers for Shadow paging.
3958	* @{
3959	*/
3960	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3961	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3962	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3963	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3964
3965	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3966	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3967
3968	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3969	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3970
3971	/** @} */
3972
3973	/** @name Function pointers for Guest paging.
3974	* @{
3975	*/
3976	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3977	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3978	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3979	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3980	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3981	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3982	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3983	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3984	#if HC_ARCH_BITS == 64
3985	RTRCPTR alignment3; /*< structure size alignment. /
3986	#endif
3987
3988	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3989	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3990	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3991	/** @} */
3992
3993	/** @name Function pointers for Both Shadow and Guest paging.
3994	* @{
3995	*/
3996	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3997	/* no pfnR3BthTrap0eHandler */
3998	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3999	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4000	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4001	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4002	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4003	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4004	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4005
4006	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4007	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4008	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4009	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4010	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4011	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4012	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4013	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4014
4015	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4016	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4017	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4018	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4019	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4020	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4021	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4022	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4023	#if 0
4024	RTRCPTR alignment2; /*< structure size alignment. /
4025	#endif
4026	/** @} */
4027
4028	/** For saving stack space, the disassembler state is allocated here instead of
4029	* on the stack. */
4030	DISCPUSTATE DisState;
4031
4032	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
4033	uint64_t cNetwareWp0Hacks;
4034
4035	/** Count the number of pgm pool access handler calls. */
4036	uint64_t cPoolAccessHandler;
4037
4038	/** @name Release Statistics
4039	* @{ */
4040	/** The number of times the guest has switched mode since last reset or statistics reset. */
4041	STAMCOUNTER cGuestModeChanges;
4042	/** The number of times the guest has switched mode since last reset or statistics reset. */
4043	STAMCOUNTER cA20Changes;
4044	/** @} */
4045
4046	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4047	/** @name Statistics
4048	* @{ */
4049	/** RC: Pointer to the statistics. */
4050	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4051	/** RC: Which statistic this \#PF should be attributed to. */
4052	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4053	/** R0: Pointer to the statistics. */
4054	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4055	/** R0: Which statistic this \#PF should be attributed to. */
4056	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4057	/** R3: Pointer to the statistics. */
4058	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4059	/** Alignment padding. */
4060	RTR3PTR pPaddingR3;
4061	/** @} */
4062	#endif /* VBOX_WITH_STATISTICS */
4063	} PGMCPU;
4064	/** Pointer to the per-cpu PGM data. */
4065	typedef PGMCPU *PPGMCPU;
4066
4067
4068	/** @name PGM::fSyncFlags Flags
4069	* @{
4070	*/
4071	/** Updates the virtual access handler state bit in PGMPAGE. */
4072	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4073	/** Always sync CR3. */
4074	#define PGM_SYNC_ALWAYS RT_BIT(1)
4075	/** Check monitoring on next CR3 (re)load and invalidate page.
4076	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4077	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4078	/** Check guest mapping in SyncCR3. */
4079	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4080	/** Clear the page pool (a light weight flush). */
4081	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4082	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4083	/** @} */
4084
4085
4086	RT_C_DECLS_BEGIN
4087
4088	#if defined(VBOX_STRICT) && defined(IN_RING3)
4089	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4090	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4091	#else
4092	int pgmLock(PVM pVM);
4093	#endif
4094	void pgmUnlock(PVM pVM);
4095	/**
4096	* Asserts that the caller owns the PDM lock.
4097	* This is the internal variant of PGMIsLockOwner.
4098	* @param a_pVM Pointer to the VM.
4099	*/
4100	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4101	/**
4102	* Asserts that the caller owns the PDM lock.
4103	* This is the internal variant of PGMIsLockOwner.
4104	* @param a_pVM Pointer to the VM.
4105	* @param a_pVCpu The current CPU handle.
4106	*/
4107	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4108
4109	#ifndef PGM_WITHOUT_MAPPINGS
4110	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4111	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4112	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4113	int pgmMapResolveConflicts(PVM pVM);
4114	#endif /* !PGM_WITHOUT_MAPPINGS */
4115	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4116	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4117
4118	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4119	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4120	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4121	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
4122	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4123	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4124	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4125	#else
4126	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4127	#endif
4128	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4129	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4130
4131	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4132	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4133	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4134	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4135	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4136	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4137	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4138	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4139	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4140	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4141	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4142	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4143	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4144	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4145	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4146	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4147	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4148	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4149	#ifndef IN_RING3
4150	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4151	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4152	#endif
4153	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4154	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4155	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4156	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4157	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4158	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4159	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4160	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4161	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4162
4163	#ifdef IN_RING3
4164	void pgmR3PhysRelinkRamRanges(PVM pVM);
4165	int pgmR3PhysRamPreAllocate(PVM pVM);
4166	int pgmR3PhysRamReset(PVM pVM);
4167	int pgmR3PhysRomReset(PVM pVM);
4168	int pgmR3PhysRamZeroAll(PVM pVM);
4169	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4170	int pgmR3PhysRamTerm(PVM pVM);
4171	void pgmR3PhysRomTerm(PVM pVM);
4172	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4173
4174	int pgmR3PoolInit(PVM pVM);
4175	void pgmR3PoolRelocate(PVM pVM);
4176	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4177	void pgmR3PoolReset(PVM pVM);
4178	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4179	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4180	void pgmR3PoolWriteProtectPages(PVM pVM);
4181
4182	#endif /* IN_RING3 */
4183	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4184	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4185	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4186	# ifdef LOG_ENABLED
4187	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4188	# else
4189	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4190	# endif
4191	#endif
4192	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4193	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4194	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4195	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4196	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4197	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4198	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4199	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4200	int pgmPoolSyncCR3(PVMCPU pVCpu);
4201	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4202	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4203	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4204	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4205	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4206	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4207	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4208	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4209	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4210	#ifndef IN_RING3
4211	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
4212	#endif
4213
4214	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4215	void pgmPoolResetDirtyPages(PVM pVM);
4216	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4217
4218	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4219	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4220	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4221
4222	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4223	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4224	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4225	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4226
4227	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4228	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4229	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4230
4231	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4232	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4233	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4234	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4235	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4236
4237	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4238	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4239	FNDBGCCMD pgmR3CmdShowSharedModules;
4240	# endif
4241
4242	RT_C_DECLS_END
4243
4244	/** @} */
4245
4246	#endif
4247

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 55909

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