PGMInternal.h@ 56384

Last change on this file since 56384 was 56384, checked in by vboxsync, 10 years ago
PGM: Disabled the virtual handler code for !VBOX_WITH_RAW_MODE.
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File size: 192.9 KB

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1	/* $Id: PGMInternal.h 56384 2015-06-12 12:34:31Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/list-off32.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings in the shadow tables.
60	*
61	* Note! In ring-3 the macro is also used to exclude the managment of the
62	* intermediate context page tables. On 32-bit systems we use the intermediate
63	* context to support 64-bit guest execution. Thus, we cannot fully make it
64	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
65	*
66	* In raw-mode context there are by design always guest mappings (the code is
67	* executed from one), while in ring-0 there are none at all. Neither context
68	* manages the page tables for intermediate switcher context, that's all done in
69	* ring-3.
70	*
71	* On 32-bit darwin (hybrid kernel) we do 64-bit guest support differently, so
72	* there we can safely work without mappings if we don't compile in raw-mode.
73	*/
74	#if defined(IN_RING0) \
75	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
76	&& ( HC_ARCH_BITS != 32 \
77	\|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# define PGM_WITHOUT_MAPPINGS
82	#endif
83
84	/**
85	* Check and skip global PDEs for non-global flushes
86	*/
87	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
88
89	/**
90	* Optimization for PAE page tables that are modified often
91	*/
92	//#if 0 /* disabled again while debugging */
93	#ifndef IN_RC
94	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	#endif
96	//#endif
97
98	/**
99	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
100	*/
101	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
102	# define PGM_WITH_LARGE_PAGES
103	#endif
104
105	/**
106	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
107	* VMX_EXIT_EPT_MISCONFIG.
108	*/
109	#if 1 /* testing */
110	# define PGM_WITH_MMIO_OPTIMIZATIONS
111	#endif
112
113	/**
114	* Sync N pages instead of a whole page table
115	*/
116	#define PGM_SYNC_N_PAGES
117
118	/**
119	* Number of pages to sync during a page fault
120	*
121	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
122	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
123	*
124	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
125	* world switch overhead, so let's sync more.
126	*/
127	# ifdef IN_RING0
128	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
129	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
130	* but ~5% fewer faults.
131	*/
132	# define PGM_SYNC_NR_PAGES 32
133	#else
134	# define PGM_SYNC_NR_PAGES 8
135	#endif
136
137	/**
138	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
139	*/
140	#define PGM_MAX_PHYSCACHE_ENTRIES 64
141	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
142
143
144	/** @def PGMPOOL_CFG_MAX_GROW
145	* The maximum number of pages to add to the pool in one go.
146	*/
147	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
148
149	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
150	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
151	*/
152	#ifdef VBOX_STRICT
153	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
154	#endif
155
156	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
157	* Enables the experimental lazy page allocation code. */
158	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
159
160	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161	* Enables real write monitoring of pages, i.e. mapping them read-only and
162	* only making them writable when getting a write access #PF. */
163	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165	/** @} */
166
167
168	/** @name PDPT and PML4 flags.
169	* These are placed in the three bits available for system programs in
170	* the PDPT and PML4 entries.
171	* @{ */
172	/** The entry is a permanent one and it's must always be present.
173	* Never free such an entry. */
174	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175	/** Mapping (hypervisor allocated pagetable). */
176	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED 6
213	#define PGM_TYPE_EPT 7
214	#define PGM_TYPE_MAX PGM_TYPE_EPT
215	/** @} */
216
217	/** Macro for checking if the guest is using paging.
218	* @param uGstType PGM_TYPE_*
219	* @param uShwType PGM_TYPE_*
220	* @remark ASSUMES certain order of the PGM_TYPE_* values.
221	*/
222	#define PGM_WITH_PAGING(uGstType, uShwType) \
223	( (uGstType) >= PGM_TYPE_32BIT \
224	&& (uShwType) != PGM_TYPE_NESTED \
225	&& (uShwType) != PGM_TYPE_EPT)
226
227	/** Macro for checking if the guest supports the NX bit.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_NX(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_PAE \
234	&& (uShwType) != PGM_TYPE_NESTED \
235	&& (uShwType) != PGM_TYPE_EPT)
236
237
238	/** @def PGM_HCPHYS_2_PTR
239	* Maps a HC physical page pool address to a virtual address.
240	*
241	* @returns VBox status code.
242	* @param pVM Pointer to the VM.
243	* @param pVCpu The current CPU.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast
246	* this.
247	*
248	* @remark Use with care as we don't have so much dynamic mapping space in
249	* ring-0 on 32-bit darwin and in RC.
250	* @remark There is no need to assert on the result.
251	*/
252	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
253	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
255	#else
256	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
257	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
258	#endif
259
260	/** @def PGM_GCPHYS_2_PTR_V2
261	* Maps a GC physical page address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM Pointer to the VM.
265	* @param pVCpu The current CPU.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark Use with care as we don't have so much dynamic mapping space in
270	* ring-0 on 32-bit darwin and in RC.
271	* @remark There is no need to assert on the result.
272	*/
273	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
274	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
276	#else
277	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
278	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
279	#endif
280
281	/** @def PGM_GCPHYS_2_PTR
282	* Maps a GC physical page address to a virtual address.
283	*
284	* @returns VBox status code.
285	* @param pVM Pointer to the VM.
286	* @param GCPhys The GC physical address to map to a virtual one.
287	* @param ppv Where to store the virtual address. No need to cast this.
288	*
289	* @remark Use with care as we don't have so much dynamic mapping space in
290	* ring-0 on 32-bit darwin and in RC.
291	* @remark There is no need to assert on the result.
292	*/
293	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
294
295	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
296	* Maps a GC physical page address to a virtual address.
297	*
298	* @returns VBox status code.
299	* @param pVCpu The current CPU.
300	* @param GCPhys The GC physical address to map to a virtual one.
301	* @param ppv Where to store the virtual address. No need to cast this.
302	*
303	* @remark Use with care as we don't have so much dynamic mapping space in
304	* ring-0 on 32-bit darwin and in RC.
305	* @remark There is no need to assert on the result.
306	*/
307	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM Pointer to the VM.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark Use with care as we don't have so much dynamic mapping space in
318	* ring-0 on 32-bit darwin and in RC.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327	#endif
328
329	/** @def PGM_DYNMAP_UNUSED_HINT
330	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
331	* is no longer used.
332	*
333	* For best effect only apply this to the page that was mapped most recently.
334	*
335	* @param pVCpu The current CPU.
336	* @param pvPage The pool page.
337	*/
338	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
339	# ifdef LOG_ENABLED
340	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
341	# else
342	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
343	# endif
344	#else
345	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
346	#endif
347
348	/** @def PGM_DYNMAP_UNUSED_HINT_VM
349	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
350	* is no longer used.
351	*
352	* For best effect only apply this to the page that was mapped most recently.
353	*
354	* @param pVM Pointer to the VM.
355	* @param pvPage The pool page.
356	*/
357	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
358
359
360	/** @def PGM_INVL_PG
361	* Invalidates a page.
362	*
363	* @param pVCpu Pointer to the VMCPU.
364	* @param GCVirt The virtual address of the page to invalidate.
365	*/
366	#ifdef IN_RC
367	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
368	#elif defined(IN_RING0)
369	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370	#else
371	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
372	#endif
373
374	/** @def PGM_INVL_PG_ALL_VCPU
375	* Invalidates a page on all VCPUs
376	*
377	* @param pVM Pointer to the VM.
378	* @param GCVirt The virtual address of the page to invalidate.
379	*/
380	#ifdef IN_RC
381	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
382	#elif defined(IN_RING0)
383	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384	#else
385	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
386	#endif
387
388	/** @def PGM_INVL_BIG_PG
389	* Invalidates a 4MB page directory entry.
390	*
391	* @param pVCpu Pointer to the VMCPU.
392	* @param GCVirt The virtual address within the page directory to invalidate.
393	*/
394	#ifdef IN_RC
395	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
396	#elif defined(IN_RING0)
397	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398	#else
399	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
400	#endif
401
402	/** @def PGM_INVL_VCPU_TLBS()
403	* Invalidates the TLBs of the specified VCPU
404	*
405	* @param pVCpu Pointer to the VMCPU.
406	*/
407	#ifdef IN_RC
408	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
409	#elif defined(IN_RING0)
410	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411	#else
412	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
413	#endif
414
415	/** @def PGM_INVL_ALL_VCPU_TLBS()
416	* Invalidates the TLBs of all VCPUs
417	*
418	* @param pVM Pointer to the VM.
419	*/
420	#ifdef IN_RC
421	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
422	#elif defined(IN_RING0)
423	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424	#else
425	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
426	#endif
427
428
429	/** @name Safer Shadow PAE PT/PTE
430	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
431	* present.
432	*
433	* @{
434	*/
435	#if 1
436	/**
437	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
438	* invalid entries for present.
439	* @sa X86PTEPAE.
440	*/
441	typedef union PGMSHWPTEPAE
442	{
443	/** Unsigned integer view */
444	X86PGPAEUINT uCareful;
445	/* Not other views. */
446	} PGMSHWPTEPAE;
447
448	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
449	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
450	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
451	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
452	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
453	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
454	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
455	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
456	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
457	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
458	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
459	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
461	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
462	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
463	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
464
465	/**
466	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
467	* invalid entries for present.
468	* @sa X86PTPAE.
469	*/
470	typedef struct PGMSHWPTPAE
471	{
472	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
473	} PGMSHWPTPAE;
474
475	#else
476	typedef X86PTEPAE PGMSHWPTEPAE;
477	typedef X86PTPAE PGMSHWPTPAE;
478	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
479	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
480	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
481	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
482	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
483	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
484	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
485	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
486	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
487	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
488	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
489	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
491	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
492	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
493	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
494
495	#endif
496
497	/** Pointer to a shadow PAE PTE. */
498	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
499	/** Pointer to a const shadow PAE PTE. */
500	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
501
502	/** Pointer to a shadow PAE page table. */
503	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
504	/** Pointer to a const shadow PAE page table. */
505	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
506	/** @} */
507
508
509	/** Size of the GCPtrConflict array in PGMMAPPING.
510	* @remarks Must be a power of two. */
511	#define PGMMAPPING_CONFLICT_MAX 8
512
513	/**
514	* Structure for tracking GC Mappings.
515	*
516	* This structure is used by linked list in both GC and HC.
517	*/
518	typedef struct PGMMAPPING
519	{
520	/** Pointer to next entry. */
521	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522	/** Pointer to next entry. */
523	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524	/** Pointer to next entry. */
525	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
526	/** Indicate whether this entry is finalized. */
527	bool fFinalized;
528	/** Start Virtual address. */
529	RTGCPTR GCPtr;
530	/** Last Virtual address (inclusive). */
531	RTGCPTR GCPtrLast;
532	/** Range size (bytes). */
533	RTGCPTR cb;
534	/** Pointer to relocation callback function. */
535	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
536	/** User argument to the callback. */
537	R3PTRTYPE(void *) pvUser;
538	/** Mapping description / name. For easing debugging. */
539	R3PTRTYPE(const char *) pszDesc;
540	/** Last 8 addresses that caused conflicts. */
541	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
542	/** Number of conflicts for this hypervisor mapping. */
543	uint32_t cConflicts;
544	/** Number of page tables. */
545	uint32_t cPTs;
546
547	/** Array of page table mapping data. Each entry
548	* describes one page table. The array can be longer
549	* than the declared length.
550	*/
551	struct
552	{
553	/** The HC physical address of the page table. */
554	RTHCPHYS HCPhysPT;
555	/** The HC physical address of the first PAE page table. */
556	RTHCPHYS HCPhysPaePT0;
557	/** The HC physical address of the second PAE page table. */
558	RTHCPHYS HCPhysPaePT1;
559	/** The HC virtual address of the 32-bit page table. */
560	R3PTRTYPE(PX86PT) pPTR3;
561	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
562	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
563	/** The RC virtual address of the 32-bit page table. */
564	RCPTRTYPE(PX86PT) pPTRC;
565	/** The RC virtual address of the two PAE page table. */
566	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
567	/** The R0 virtual address of the 32-bit page table. */
568	R0PTRTYPE(PX86PT) pPTR0;
569	/** The R0 virtual address of the two PAE page table. */
570	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571	} aPTs[1];
572	} PGMMAPPING;
573	/** Pointer to structure for tracking GC Mappings. */
574	typedef struct PGMMAPPING *PPGMMAPPING;
575
576
577	/**
578	* Physical page access handler type registration.
579	*/
580	typedef struct PGMPHYSHANDLERTYPEINT
581	{
582	/** Number of references. */
583	uint32_t volatile cRefs;
584	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
585	uint32_t u32Magic;
586	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
587	RTLISTOFF32NODE ListNode;
588	/** The kind of accesses we're handling. */
589	PGMPHYSHANDLERKIND enmKind;
590	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
591	uint32_t uState;
592	/** Pointer to RC callback function. */
593	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
594	/** Pointer to RC callback function for \#PFs. */
595	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
596	/** Pointer to R3 callback function. */
597	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
598	/** Pointer to R0 callback function. */
599	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
600	/** Pointer to R0 callback function for \#PFs. */
601	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
602	/** Description / Name. For easing debugging. */
603	R3PTRTYPE(const char *) pszDesc;
604	} PGMPHYSHANDLERTYPEINT;
605	/** Pointer to a physical access handler type registration. */
606	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
607	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
609	/** Magic value for the physical handler callbacks. */
610	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
611
612	/**
613	* Converts a handle to a pointer.
614	* @returns PPGMPHYSHANDLERTYPEINT
615	* @param a_pVM Pointer to the cross context VM structure.
616	* @param a_hType Physical access handler type handle.
617	*/
618	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
619
620
621	/**
622	* Physical page access handler structure.
623	*
624	* This is used to keep track of physical address ranges
625	* which are being monitored in some kind of way.
626	*/
627	typedef struct PGMPHYSHANDLER
628	{
629	AVLROGCPHYSNODECORE Core;
630	/** Number of pages to update. */
631	uint32_t cPages;
632	/** Set if we have pages that have been aliased. */
633	uint32_t cAliasedPages;
634	/** Set if we have pages that have temporarily been disabled. */
635	uint32_t cTmpOffPages;
636	/** Registered handler type handle (heap offset). */
637	PGMPHYSHANDLERTYPE hType;
638	/** User argument for RC handlers. */
639	RCPTRTYPE(void *) pvUserRC;
640	#if HC_ARCH_BITS == 64
641	RTRCPTR Padding0; /*< Explicit alignment padding. /
642	#endif
643	/** User argument for R3 handlers. */
644	R3PTRTYPE(void *) pvUserR3;
645	/** User argument for R0 handlers. */
646	R0PTRTYPE(void *) pvUserR0;
647	/** Description / Name. For easing debugging. */
648	R3PTRTYPE(const char *) pszDesc;
649	#ifdef VBOX_WITH_STATISTICS
650	/** Profiling of this handler. */
651	STAMPROFILE Stat;
652	#endif
653	} PGMPHYSHANDLER;
654	/** Pointer to a physical page access handler structure. */
655	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
656
657	/**
658	* Gets the type record for a physical handler (no reference added).
659	* @returns PPGMPHYSHANDLERTYPEINT
660	* @param a_pVM Pointer to the cross context VM structure.
661	* @param a_pPhysHandler Pointer to the physical handler structure
662	* (PGMPHYSHANDLER).
663	*/
664	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
665
666
667	#ifdef VBOX_WITH_RAW_MODE
668
669	/**
670	* Cache node for the physical addresses covered by a virtual handler.
671	*/
672	typedef struct PGMPHYS2VIRTHANDLER
673	{
674	/** Core node for the tree based on physical ranges. */
675	AVLROGCPHYSNODECORE Core;
676	/** Offset from this struct to the PGMVIRTHANDLER structure. */
677	int32_t offVirtHandler;
678	/** Offset of the next alias relative to this one.
679	* Bit 0 is used for indicating whether we're in the tree.
680	* Bit 1 is used for indicating that we're the head node.
681	*/
682	int32_t offNextAlias;
683	} PGMPHYS2VIRTHANDLER;
684	/** Pointer to a phys to virtual handler structure. */
685	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
686
687	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
688	* node is in the tree. */
689	# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
690	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
691	* node is in the head of an alias chain.
692	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
693	# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
694	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
695	# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
696
697
698	/**
699	* Virtual page access handler type registration.
700	*/
701	typedef struct PGMVIRTANDLERTYPEINT
702	{
703	/** Number of references. */
704	uint32_t volatile cRefs;
705	/** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
706	uint32_t u32Magic;
707	/** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
708	RTLISTOFF32NODE ListNode;
709	/** The kind of accesses we're handling. */
710	PGMVIRTHANDLERKIND enmKind;
711	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
712	uint32_t uState;
713	/** Whether the pvUserRC argument should be automatically relocated or not. */
714	bool fRelocUserRC;
715	bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
716	/** Pointer to RC callback function. */
717	RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
718	/** Pointer to RC callback function for \#PFs. */
719	RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
720	/** Pointer to the R3 callback function for invalidation. */
721	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
722	/** Pointer to R3 callback function. */
723	R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
724	/** Description / Name. For easing debugging. */
725	R3PTRTYPE(const char *) pszDesc;
726	} PGMVIRTHANDLERTYPEINT;
727	/** Pointer to a virtual access handler type registration. */
728	typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
729	/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
730	# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
731	/** Magic value for the virtual handler callbacks. */
732	# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
733
734	/**
735	* Converts a handle to a pointer.
736	* @returns PPGMVIRTHANDLERTYPEINT
737	* @param a_pVM Pointer to the cross context VM structure.
738	* @param a_hType Vitual access handler type handle.
739	*/
740	# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
741
742
743	/**
744	* Virtual page access handler structure.
745	*
746	* This is used to keep track of virtual address ranges
747	* which are being monitored in some kind of way.
748	*/
749	typedef struct PGMVIRTHANDLER
750	{
751	/** Core node for the tree based on virtual ranges. */
752	AVLROGCPTRNODECORE Core;
753	/** Size of the range (in bytes). */
754	uint32_t cb;
755	/** Number of cache pages. */
756	uint32_t cPages;
757	/** Registered handler type handle (heap offset). */
758	PGMVIRTHANDLERTYPE hType;
759	/** User argument for RC handlers. */
760	RCPTRTYPE(void *) pvUserRC;
761	/** User argument for R3 handlers. */
762	R3PTRTYPE(void *) pvUserR3;
763	/** Description / Name. For easing debugging. */
764	R3PTRTYPE(const char *) pszDesc;
765	# ifdef VBOX_WITH_STATISTICS
766	/** Profiling of this handler. */
767	STAMPROFILE Stat;
768	# endif
769	/** Array of cached physical addresses for the monitored ranged. */
770	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
771	} PGMVIRTHANDLER;
772	/** Pointer to a virtual page access handler structure. */
773	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
774
775	/**
776	* Gets the type record for a virtual handler (no reference added).
777	* @returns PPGMVIRTHANDLERTYPEINT
778	* @param a_pVM Pointer to the cross context VM structure.
779	* @param a_pVirtHandler Pointer to the virtual handler structure
780	* (PGMVIRTHANDLER).
781	*/
782	# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
783
784	#endif /* VBOX_WITH_RAW_MODE */
785
786
787	/** @name Page type predicates.
788	* @{ */
789	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
790	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
791	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
792	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
793	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
794	/** @} */
795
796
797	/**
798	* A Physical Guest Page tracking structure.
799	*
800	* The format of this structure is complicated because we have to fit a lot
801	* of information into as few bits as possible. The format is also subject
802	* to change (there is one coming up soon). Which means that for we'll be
803	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
804	* accesses to the structure.
805	*/
806	typedef union PGMPAGE
807	{
808	/** Structured view. */
809	struct
810	{
811	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
812	uint64_t u2HandlerPhysStateY : 2;
813	/** 3:2 - Paging structure needed to map the page
814	* (PGM_PAGE_PDE_TYPE_). /
815	uint64_t u2PDETypeY : 2;
816	/** 4 - Indicator of dirty page for fault tolerance tracking. */
817	uint64_t fFTDirtyY : 1;
818	/** 5 - Flag indicating that a write monitored page was written to
819	* when set. */
820	uint64_t fWrittenToY : 1;
821	/** 7:6 - Unused. */
822	uint64_t u2Unused0 : 2;
823	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
824	uint64_t u2HandlerVirtStateY : 2;
825	/** 11:10 - Unused. */
826	uint64_t u2Unused1 : 2;
827	/** 12:48 - The host physical frame number (shift left to get the
828	* address). */
829	uint64_t HCPhysFN : 36;
830	/** 50:48 - The page state. */
831	uint64_t uStateY : 3;
832	/** 51:53 - The page type (PGMPAGETYPE). */
833	uint64_t uTypeY : 3;
834	/** 63:54 - PTE index for usage tracking (page pool). */
835	uint64_t u10PteIdx : 10;
836
837	/** The GMM page ID.
838	* @remarks In the current implementation, MMIO2 and pages aliased to
839	* MMIO2 pages will be exploiting this field to calculate the
840	* ring-3 mapping address corresponding to the page.
841	* Later we may consider including MMIO2 management into GMM. */
842	uint32_t idPage;
843	/** Usage tracking (page pool). */
844	uint16_t u16TrackingY;
845	/** The number of read locks on this page. */
846	uint8_t cReadLocksY;
847	/** The number of write locks on this page. */
848	uint8_t cWriteLocksY;
849	} s;
850
851	/** 64-bit integer view. */
852	uint64_t au64[2];
853	/** 16-bit view. */
854	uint32_t au32[4];
855	/** 16-bit view. */
856	uint16_t au16[8];
857	/** 8-bit view. */
858	uint8_t au8[16];
859	} PGMPAGE;
860	AssertCompileSize(PGMPAGE, 16);
861	/** Pointer to a physical guest page. */
862	typedef PGMPAGE *PPGMPAGE;
863	/** Pointer to a const physical guest page. */
864	typedef const PGMPAGE *PCPGMPAGE;
865	/** Pointer to a physical guest page pointer. */
866	typedef PPGMPAGE *PPPGMPAGE;
867
868
869	/**
870	* Clears the page structure.
871	* @param a_pPage Pointer to the physical guest page tracking structure.
872	*/
873	#define PGM_PAGE_CLEAR(a_pPage) \
874	do { \
875	(a_pPage)->au64[0] = 0; \
876	(a_pPage)->au64[1] = 0; \
877	} while (0)
878
879	/**
880	* Initializes the page structure.
881	* @param a_pPage Pointer to the physical guest page tracking structure.
882	*/
883	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
884	do { \
885	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
886	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
887	(a_pPage)->au64[0] = SetHCPhysTmp; \
888	(a_pPage)->au64[1] = 0; \
889	(a_pPage)->s.idPage = (a_idPage); \
890	(a_pPage)->s.uStateY = (a_uState); \
891	(a_pPage)->s.uTypeY = (a_uType); \
892	} while (0)
893
894	/**
895	* Initializes the page structure of a ZERO page.
896	* @param a_pPage Pointer to the physical guest page tracking structure.
897	* @param a_pVM The VM handle (for getting the zero page address).
898	* @param a_uType The page type (PGMPAGETYPE).
899	*/
900	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
901	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
902
903
904	/** @name The Page state, PGMPAGE::uStateY.
905	* @{ */
906	/** The zero page.
907	* This is a per-VM page that's never ever mapped writable. */
908	#define PGM_PAGE_STATE_ZERO 0
909	/** A allocated page.
910	* This is a per-VM page allocated from the page pool (or wherever
911	* we get MMIO2 pages from if the type is MMIO2).
912	*/
913	#define PGM_PAGE_STATE_ALLOCATED 1
914	/** A allocated page that's being monitored for writes.
915	* The shadow page table mappings are read-only. When a write occurs, the
916	* fWrittenTo member is set, the page remapped as read-write and the state
917	* moved back to allocated. */
918	#define PGM_PAGE_STATE_WRITE_MONITORED 2
919	/** The page is shared, aka. copy-on-write.
920	* This is a page that's shared with other VMs. */
921	#define PGM_PAGE_STATE_SHARED 3
922	/** The page is ballooned, so no longer available for this VM. */
923	#define PGM_PAGE_STATE_BALLOONED 4
924	/** @} */
925
926
927	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
928	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
929	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
930	#else
931	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
932	#endif
933
934	/**
935	* Gets the page state.
936	* @returns page state (PGM_PAGE_STATE_*).
937	* @param a_pPage Pointer to the physical guest page tracking structure.
938	*
939	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
940	* builds.
941	*/
942	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
943	#if defined(__GNUC__) && defined(VBOX_STRICT)
944	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
945	#else
946	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
947	#endif
948
949	/**
950	* Sets the page state.
951	* @param a_pVM The VM handle, only used for lock ownership assertions.
952	* @param a_pPage Pointer to the physical guest page tracking structure.
953	* @param a_uState The new page state.
954	*/
955	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
956	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
957
958
959	/**
960	* Gets the host physical address of the guest page.
961	* @returns host physical address (RTHCPHYS).
962	* @param a_pPage Pointer to the physical guest page tracking structure.
963	*
964	* @remarks In strict builds on gcc platforms, this macro will make some ugly
965	* assumption about a valid pVM variable/parameter being in the
966	* current context. It will use this pVM variable to assert that the
967	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
968	* pVM is not around.
969	*/
970	#if 0
971	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
972	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
973	#else
974	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
975	# if defined(__GNUC__) && defined(VBOX_STRICT)
976	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
977	# else
978	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
979	# endif
980	#endif
981
982	/**
983	* Sets the host physical address of the guest page.
984	*
985	* @param a_pVM The VM handle, only used for lock ownership assertions.
986	* @param a_pPage Pointer to the physical guest page tracking structure.
987	* @param a_HCPhys The new host physical address.
988	*/
989	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
990	do { \
991	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
992	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
993	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
994	PGM_PAGE_ASSERT_LOCK(a_pVM); \
995	} while (0)
996
997	/**
998	* Get the Page ID.
999	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1000	* @param a_pPage Pointer to the physical guest page tracking structure.
1001	*/
1002	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1003
1004	/**
1005	* Sets the Page ID.
1006	* @param a_pVM The VM handle, only used for lock ownership assertions.
1007	* @param a_pPage Pointer to the physical guest page tracking structure.
1008	* @param a_idPage The new page ID.
1009	*/
1010	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1011	do { \
1012	(a_pPage)->s.idPage = (a_idPage); \
1013	PGM_PAGE_ASSERT_LOCK(a_pVM); \
1014	} while (0)
1015
1016	/**
1017	* Get the Chunk ID.
1018	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1019	* @param a_pPage Pointer to the physical guest page tracking structure.
1020	*/
1021	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1022
1023	/**
1024	* Get the index of the page within the allocation chunk.
1025	* @returns The page index.
1026	* @param a_pPage Pointer to the physical guest page tracking structure.
1027	*/
1028	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1029
1030	/**
1031	* Gets the page type.
1032	* @returns The page type.
1033	* @param a_pPage Pointer to the physical guest page tracking structure.
1034	*
1035	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1036	* builds.
1037	*/
1038	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1039	#if defined(__GNUC__) && defined(VBOX_STRICT)
1040	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1041	#else
1042	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1043	#endif
1044
1045	/**
1046	* Sets the page type.
1047	*
1048	* @param a_pVM The VM handle, only used for lock ownership assertions.
1049	* @param a_pPage Pointer to the physical guest page tracking structure.
1050	* @param a_enmType The new page type (PGMPAGETYPE).
1051	*/
1052	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1053	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1054
1055	/**
1056	* Gets the page table index
1057	* @returns The page table index.
1058	* @param a_pPage Pointer to the physical guest page tracking structure.
1059	*/
1060	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1061
1062	/**
1063	* Sets the page table index.
1064	* @param a_pVM The VM handle, only used for lock ownership assertions.
1065	* @param a_pPage Pointer to the physical guest page tracking structure.
1066	* @param a_iPte New page table index.
1067	*/
1068	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1069	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1070
1071	/**
1072	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1073	* @returns true/false.
1074	* @param a_pPage Pointer to the physical guest page tracking structure.
1075	*/
1076	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1077
1078	/**
1079	* Checks if the page is marked for MMIO, including both aliases.
1080	* @returns true/false.
1081	* @param a_pPage Pointer to the physical guest page tracking structure.
1082	*/
1083	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1084	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1085	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1086	)
1087
1088	/**
1089	* Checks if the page is marked for MMIO, including special aliases.
1090	* @returns true/false.
1091	* @param a_pPage Pointer to the physical guest page tracking structure.
1092	*/
1093	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1094	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1095
1096	/**
1097	* Checks if the page is a special aliased MMIO page.
1098	* @returns true/false.
1099	* @param a_pPage Pointer to the physical guest page tracking structure.
1100	*/
1101	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1102
1103	/**
1104	* Checks if the page is backed by the ZERO page.
1105	* @returns true/false.
1106	* @param a_pPage Pointer to the physical guest page tracking structure.
1107	*/
1108	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1109
1110	/**
1111	* Checks if the page is backed by a SHARED page.
1112	* @returns true/false.
1113	* @param a_pPage Pointer to the physical guest page tracking structure.
1114	*/
1115	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1116
1117	/**
1118	* Checks if the page is ballooned.
1119	* @returns true/false.
1120	* @param a_pPage Pointer to the physical guest page tracking structure.
1121	*/
1122	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1123
1124	/**
1125	* Checks if the page is allocated.
1126	* @returns true/false.
1127	* @param a_pPage Pointer to the physical guest page tracking structure.
1128	*/
1129	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1130
1131	/**
1132	* Marks the page as written to (for GMM change monitoring).
1133	* @param a_pVM The VM handle, only used for lock ownership assertions.
1134	* @param a_pPage Pointer to the physical guest page tracking structure.
1135	*/
1136	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1137	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1138
1139	/**
1140	* Clears the written-to indicator.
1141	* @param a_pVM The VM handle, only used for lock ownership assertions.
1142	* @param a_pPage Pointer to the physical guest page tracking structure.
1143	*/
1144	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1145	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1146
1147	/**
1148	* Checks if the page was marked as written-to.
1149	* @returns true/false.
1150	* @param a_pPage Pointer to the physical guest page tracking structure.
1151	*/
1152	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1153
1154	/**
1155	* Marks the page as dirty for FTM
1156	* @param a_pPage Pointer to the physical guest page tracking structure.
1157	*/
1158	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1159
1160	/**
1161	* Clears the FTM dirty indicator
1162	* @param a_pPage Pointer to the physical guest page tracking structure.
1163	*/
1164	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1165
1166	/**
1167	* Checks if the page was marked as dirty for FTM
1168	* @returns true/false.
1169	* @param a_pPage Pointer to the physical guest page tracking structure.
1170	*/
1171	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1172
1173
1174	/** @name PT usage values (PGMPAGE::u2PDEType).
1175	*
1176	* @{ */
1177	/** Either as a PT or PDE. */
1178	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1179	/** Must use a page table to map the range. */
1180	#define PGM_PAGE_PDE_TYPE_PT 1
1181	/** Can use a page directory entry to map the continuous range. */
1182	#define PGM_PAGE_PDE_TYPE_PDE 2
1183	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1184	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1185	/** @} */
1186
1187	/**
1188	* Set the PDE type of the page
1189	* @param a_pVM The VM handle, only used for lock ownership assertions.
1190	* @param a_pPage Pointer to the physical guest page tracking structure.
1191	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1192	*/
1193	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1194	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1195
1196	/**
1197	* Checks if the page was marked being part of a large page
1198	* @returns true/false.
1199	* @param a_pPage Pointer to the physical guest page tracking structure.
1200	*/
1201	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1202
1203	/** Enabled optimized access handler tests.
1204	* These optimizations makes ASSUMPTIONS about the state values and the s1
1205	* layout. When enabled, the compiler should normally generate more compact
1206	* code.
1207	*/
1208	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1209
1210	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1211	*
1212	* @remarks The values are assigned in order of priority, so we can calculate
1213	* the correct state for a page with different handlers installed.
1214	* @{ */
1215	/** No handler installed. */
1216	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1217	/** Monitoring is temporarily disabled. */
1218	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1219	/** Write access is monitored. */
1220	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1221	/** All access is monitored. */
1222	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1223	/** @} */
1224
1225	/**
1226	* Gets the physical access handler state of a page.
1227	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1228	* @param a_pPage Pointer to the physical guest page tracking structure.
1229	*/
1230	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1231
1232	/**
1233	* Sets the physical access handler state of a page.
1234	* @param a_pPage Pointer to the physical guest page tracking structure.
1235	* @param a_uState The new state value.
1236	*/
1237	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1238	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1239
1240	/**
1241	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1242	* @returns true/false
1243	* @param a_pPage Pointer to the physical guest page tracking structure.
1244	*/
1245	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1246	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1247
1248	/**
1249	* Checks if the page has any active physical access handlers.
1250	* @returns true/false
1251	* @param a_pPage Pointer to the physical guest page tracking structure.
1252	*/
1253	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1254	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1255
1256
1257	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1258	*
1259	* @remarks The values are assigned in order of priority, so we can calculate
1260	* the correct state for a page with different handlers installed.
1261	* @{ */
1262	/** No handler installed. */
1263	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1264	/* 1 is reserved so the lineup is identical with the physical ones. */
1265	/** Write access is monitored. */
1266	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1267	/** All access is monitored. */
1268	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1269	/** @} */
1270
1271	/**
1272	* Gets the virtual access handler state of a page.
1273	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1274	* @param a_pPage Pointer to the physical guest page tracking structure.
1275	*/
1276	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1277
1278	/**
1279	* Sets the virtual access handler state of a page.
1280	* @param a_pPage Pointer to the physical guest page tracking structure.
1281	* @param a_uState The new state value.
1282	*/
1283	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1284	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1285
1286	/**
1287	* Checks if the page has any virtual access handlers.
1288	* @returns true/false
1289	* @param a_pPage Pointer to the physical guest page tracking structure.
1290	*/
1291	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1292	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1293
1294	/**
1295	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1296	* virtual handlers.
1297	* @returns true/false
1298	* @param a_pPage Pointer to the physical guest page tracking structure.
1299	*/
1300	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1301	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1302
1303
1304	/**
1305	* Checks if the page has any access handlers, including temporarily disabled ones.
1306	* @returns true/false
1307	* @param a_pPage Pointer to the physical guest page tracking structure.
1308	*/
1309	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1310	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1311	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1312	#else
1313	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1314	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1315	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1316	#endif
1317
1318	/**
1319	* Checks if the page has any active access handlers.
1320	* @returns true/false
1321	* @param a_pPage Pointer to the physical guest page tracking structure.
1322	*/
1323	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1324	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1325	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1326	#else
1327	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1328	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1329	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1330	#endif
1331
1332	/**
1333	* Checks if the page has any active access handlers catching all accesses.
1334	* @returns true/false
1335	* @param a_pPage Pointer to the physical guest page tracking structure.
1336	*/
1337	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1338	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1339	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1340	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1341	#else
1342	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1343	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1344	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1345	#endif
1346
1347
1348	/** @def PGM_PAGE_GET_TRACKING
1349	* Gets the packed shadow page pool tracking data associated with a guest page.
1350	* @returns uint16_t containing the data.
1351	* @param a_pPage Pointer to the physical guest page tracking structure.
1352	*/
1353	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1354	#if defined(__GNUC__) && defined(VBOX_STRICT)
1355	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1356	#else
1357	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1358	#endif
1359
1360	/** @def PGM_PAGE_SET_TRACKING
1361	* Sets the packed shadow page pool tracking data associated with a guest page.
1362	* @param a_pVM The VM handle, only used for lock ownership assertions.
1363	* @param a_pPage Pointer to the physical guest page tracking structure.
1364	* @param a_u16TrackingData The tracking data to store.
1365	*/
1366	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1367	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1368
1369	/** @def PGM_PAGE_GET_TD_CREFS
1370	* Gets the @a cRefs tracking data member.
1371	* @returns cRefs.
1372	* @param a_pPage Pointer to the physical guest page tracking structure.
1373	*/
1374	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1375	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1376	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1377	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1378
1379	/** @def PGM_PAGE_GET_TD_IDX
1380	* Gets the @a idx tracking data member.
1381	* @returns idx.
1382	* @param a_pPage Pointer to the physical guest page tracking structure.
1383	*/
1384	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1385	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1386	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1387	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1388
1389
1390	/** Max number of locks on a page. */
1391	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1392
1393	/** Get the read lock count.
1394	* @returns count.
1395	* @param a_pPage Pointer to the physical guest page tracking structure.
1396	*/
1397	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1398
1399	/** Get the write lock count.
1400	* @returns count.
1401	* @param a_pPage Pointer to the physical guest page tracking structure.
1402	*/
1403	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1404
1405	/** Decrement the read lock counter.
1406	* @param a_pPage Pointer to the physical guest page tracking structure.
1407	*/
1408	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1409
1410	/** Decrement the write lock counter.
1411	* @param a_pPage Pointer to the physical guest page tracking structure.
1412	*/
1413	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1414
1415	/** Increment the read lock counter.
1416	* @param a_pPage Pointer to the physical guest page tracking structure.
1417	*/
1418	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1419
1420	/** Increment the write lock counter.
1421	* @param a_pPage Pointer to the physical guest page tracking structure.
1422	*/
1423	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1424
1425
1426	#if 0
1427	/** Enables sanity checking of write monitoring using CRC-32. */
1428	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1429	#endif
1430
1431	/**
1432	* Per page live save tracking data.
1433	*/
1434	typedef struct PGMLIVESAVERAMPAGE
1435	{
1436	/** Number of times it has been dirtied. */
1437	uint32_t cDirtied : 24;
1438	/** Whether it is currently dirty. */
1439	uint32_t fDirty : 1;
1440	/** Ignore the page.
1441	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1442	* deal with these after pausing the VM and DevPCI have said it bit about
1443	* remappings. */
1444	uint32_t fIgnore : 1;
1445	/** Was a ZERO page last time around. */
1446	uint32_t fZero : 1;
1447	/** Was a SHARED page last time around. */
1448	uint32_t fShared : 1;
1449	/** Whether the page is/was write monitored in a previous pass. */
1450	uint32_t fWriteMonitored : 1;
1451	/** Whether the page is/was write monitored earlier in this pass. */
1452	uint32_t fWriteMonitoredJustNow : 1;
1453	/** Bits reserved for future use. */
1454	uint32_t u2Reserved : 2;
1455	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1456	/** CRC-32 for the page. This is for internal consistency checks. */
1457	uint32_t u32Crc;
1458	#endif
1459	} PGMLIVESAVERAMPAGE;
1460	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1461	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1462	#else
1463	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1464	#endif
1465	/** Pointer to the per page live save tracking data. */
1466	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1467
1468	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1469	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1470
1471
1472	/**
1473	* RAM range for GC Phys to HC Phys conversion.
1474	*
1475	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1476	* conversions too, but we'll let MM handle that for now.
1477	*
1478	* This structure is used by linked lists in both GC and HC.
1479	*/
1480	typedef struct PGMRAMRANGE
1481	{
1482	/** Start of the range. Page aligned. */
1483	RTGCPHYS GCPhys;
1484	/** Size of the range. (Page aligned of course). */
1485	RTGCPHYS cb;
1486	/** Pointer to the next RAM range - for R3. */
1487	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1488	/** Pointer to the next RAM range - for R0. */
1489	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1490	/** Pointer to the next RAM range - for RC. */
1491	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1492	/** PGM_RAM_RANGE_FLAGS_* flags. */
1493	uint32_t fFlags;
1494	/** Last address in the range (inclusive). Page aligned (-1). */
1495	RTGCPHYS GCPhysLast;
1496	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1497	R3PTRTYPE(void *) pvR3;
1498	/** Live save per page tracking data. */
1499	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1500	/** The range description. */
1501	R3PTRTYPE(const char *) pszDesc;
1502	/** Pointer to self - R0 pointer. */
1503	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1504	/** Pointer to self - RC pointer. */
1505	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1506
1507	/** Alignment padding. */
1508	RTRCPTR Alignment0;
1509	/** Pointer to the left search three node - ring-3 context. */
1510	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1511	/** Pointer to the right search three node - ring-3 context. */
1512	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1513	/** Pointer to the left search three node - ring-0 context. */
1514	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1515	/** Pointer to the right search three node - ring-0 context. */
1516	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1517	/** Pointer to the left search three node - raw-mode context. */
1518	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1519	/** Pointer to the right search three node - raw-mode context. */
1520	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1521
1522	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1523	#if HC_ARCH_BITS == 32
1524	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1525	#endif
1526	/** Array of physical guest page tracking structures. */
1527	PGMPAGE aPages[1];
1528	} PGMRAMRANGE;
1529	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1530	typedef PGMRAMRANGE *PPGMRAMRANGE;
1531
1532	/** @name PGMRAMRANGE::fFlags
1533	* @{ */
1534	/** The RAM range is floating around as an independent guest mapping. */
1535	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1536	/** Ad hoc RAM range for an ROM mapping. */
1537	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1538	/** Ad hoc RAM range for an MMIO mapping. */
1539	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1540	/** Ad hoc RAM range for an MMIO2 mapping. */
1541	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1542	/** @} */
1543
1544	/** Tests if a RAM range is an ad hoc one or not.
1545	* @returns true/false.
1546	* @param pRam The RAM range.
1547	*/
1548	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1549	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1550
1551	/** The number of entries in the RAM range TLBs (there is one for each
1552	* context). Must be a power of two. */
1553	#define PGM_RAMRANGE_TLB_ENTRIES 8
1554
1555	/**
1556	* Calculates the RAM range TLB index for the physical address.
1557	*
1558	* @returns RAM range TLB index.
1559	* @param GCPhys The guest physical address.
1560	*/
1561	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1562
1563
1564
1565	/**
1566	* Per page tracking structure for ROM image.
1567	*
1568	* A ROM image may have a shadow page, in which case we may have two pages
1569	* backing it. This structure contains the PGMPAGE for both while
1570	* PGMRAMRANGE have a copy of the active one. It is important that these
1571	* aren't out of sync in any regard other than page pool tracking data.
1572	*/
1573	typedef struct PGMROMPAGE
1574	{
1575	/** The page structure for the virgin ROM page. */
1576	PGMPAGE Virgin;
1577	/** The page structure for the shadow RAM page. */
1578	PGMPAGE Shadow;
1579	/** The current protection setting. */
1580	PGMROMPROT enmProt;
1581	/** Live save status information. Makes use of unused alignment space. */
1582	struct
1583	{
1584	/** The previous protection value. */
1585	uint8_t u8Prot;
1586	/** Written to flag set by the handler. */
1587	bool fWrittenTo;
1588	/** Whether the shadow page is dirty or not. */
1589	bool fDirty;
1590	/** Whether it was dirtied in the recently. */
1591	bool fDirtiedRecently;
1592	} LiveSave;
1593	} PGMROMPAGE;
1594	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1595	/** Pointer to a ROM page tracking structure. */
1596	typedef PGMROMPAGE *PPGMROMPAGE;
1597
1598
1599	/**
1600	* A registered ROM image.
1601	*
1602	* This is needed to keep track of ROM image since they generally intrude
1603	* into a PGMRAMRANGE. It also keeps track of additional info like the
1604	* two page sets (read-only virgin and read-write shadow), the current
1605	* state of each page.
1606	*
1607	* Because access handlers cannot easily be executed in a different
1608	* context, the ROM ranges needs to be accessible and in all contexts.
1609	*/
1610	typedef struct PGMROMRANGE
1611	{
1612	/** Pointer to the next range - R3. */
1613	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1614	/** Pointer to the next range - R0. */
1615	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1616	/** Pointer to the next range - RC. */
1617	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1618	/** Pointer alignment */
1619	RTRCPTR RCPtrAlignment;
1620	/** Address of the range. */
1621	RTGCPHYS GCPhys;
1622	/** Address of the last byte in the range. */
1623	RTGCPHYS GCPhysLast;
1624	/** Size of the range. */
1625	RTGCPHYS cb;
1626	/** The flags (PGMPHYS_ROM_FLAGS_). /
1627	uint32_t fFlags;
1628	/** The saved state range ID. */
1629	uint8_t idSavedState;
1630	/** Alignment padding. */
1631	uint8_t au8Alignment[3];
1632	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1633	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1634	/** The size bits pvOriginal points to. */
1635	uint32_t cbOriginal;
1636	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1637	* This is used for strictness checks. */
1638	R3PTRTYPE(const void *) pvOriginal;
1639	/** The ROM description. */
1640	R3PTRTYPE(const char *) pszDesc;
1641	/** The per page tracking structures. */
1642	PGMROMPAGE aPages[1];
1643	} PGMROMRANGE;
1644	/** Pointer to a ROM range. */
1645	typedef PGMROMRANGE *PPGMROMRANGE;
1646
1647
1648	/**
1649	* Live save per page data for an MMIO2 page.
1650	*
1651	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1652	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1653	* CRC-32 for detecting changes as well as special handling of zero pages. This
1654	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1655	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1656	* because of speed (2.5x and 6x slower).)
1657	*
1658	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1659	* save but normally is disabled. Since we can write monitor guest
1660	* accesses on our own, we only need this for host accesses. Shouldn't be
1661	* too difficult for DevVGA, VMMDev might be doable, the planned
1662	* networking fun will be fun since it involves ring-0.
1663	*/
1664	typedef struct PGMLIVESAVEMMIO2PAGE
1665	{
1666	/** Set if the page is considered dirty. */
1667	bool fDirty;
1668	/** The number of scans this page has remained unchanged for.
1669	* Only updated for dirty pages. */
1670	uint8_t cUnchangedScans;
1671	/** Whether this page was zero at the last scan. */
1672	bool fZero;
1673	/** Alignment padding. */
1674	bool fReserved;
1675	/** CRC-32 for the first half of the page.
1676	* This is used together with u32CrcH2 to quickly detect changes in the page
1677	* during the non-final passes. */
1678	uint32_t u32CrcH1;
1679	/** CRC-32 for the second half of the page. */
1680	uint32_t u32CrcH2;
1681	/** SHA-1 for the saved page.
1682	* This is used in the final pass to skip pages without changes. */
1683	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1684	} PGMLIVESAVEMMIO2PAGE;
1685	/** Pointer to a live save status data for an MMIO2 page. */
1686	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1687
1688	/**
1689	* A registered MMIO2 (= Device RAM) range.
1690	*
1691	* There are a few reason why we need to keep track of these
1692	* registrations. One of them is the deregistration & cleanup stuff,
1693	* while another is that the PGMRAMRANGE associated with such a region may
1694	* have to be removed from the ram range list.
1695	*
1696	* Overlapping with a RAM range has to be 100% or none at all. The pages
1697	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1698	* will be raised if a partial overlap or an overlap of ROM pages is
1699	* encountered. On an overlap we will free all the existing RAM pages and
1700	* put in the ram range pages instead.
1701	*/
1702	typedef struct PGMMMIO2RANGE
1703	{
1704	/** The owner of the range. (a device) */
1705	PPDMDEVINSR3 pDevInsR3;
1706	/** Pointer to the ring-3 mapping of the allocation. */
1707	RTR3PTR pvR3;
1708	/** Pointer to the next range - R3. */
1709	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1710	/** Whether it's mapped or not. */
1711	bool fMapped;
1712	/** Whether it's overlapping or not. */
1713	bool fOverlapping;
1714	/** The PCI region number.
1715	* @remarks This ASSUMES that nobody will ever really need to have multiple
1716	* PCI devices with matching MMIO region numbers on a single device. */
1717	uint8_t iRegion;
1718	/** The saved state range ID. */
1719	uint8_t idSavedState;
1720	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1721	uint8_t idMmio2;
1722	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1723	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1724	/** Live save per page tracking data. */
1725	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1726	/** The associated RAM range. */
1727	PGMRAMRANGE RamRange;
1728	} PGMMMIO2RANGE;
1729	/** Pointer to a MMIO2 range. */
1730	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1731
1732	/** @name Intenal MMIO2 constants.
1733	* @{ */
1734	/** The maximum number of MMIO2 ranges. */
1735	#define PGM_MMIO2_MAX_RANGES 8
1736	/** The maximum number of pages in a MMIO2 range. */
1737	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1738	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1739	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1740	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1741	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1742	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1743	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1744	/** @} */
1745
1746
1747
1748	/**
1749	* PGMPhysRead/Write cache entry
1750	*/
1751	typedef struct PGMPHYSCACHEENTRY
1752	{
1753	/** R3 pointer to physical page. */
1754	R3PTRTYPE(uint8_t *) pbR3;
1755	/** GC Physical address for cache entry */
1756	RTGCPHYS GCPhys;
1757	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1758	RTGCPHYS u32Padding0; /*< alignment padding. /
1759	#endif
1760	} PGMPHYSCACHEENTRY;
1761
1762	/**
1763	* PGMPhysRead/Write cache to reduce REM memory access overhead
1764	*/
1765	typedef struct PGMPHYSCACHE
1766	{
1767	/** Bitmap of valid cache entries */
1768	uint64_t aEntries;
1769	/** Cache entries */
1770	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1771	} PGMPHYSCACHE;
1772
1773
1774	/** Pointer to an allocation chunk ring-3 mapping. */
1775	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1776	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1777	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1778
1779	/**
1780	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1781	*
1782	* The primary tree (Core) uses the chunk id as key.
1783	*/
1784	typedef struct PGMCHUNKR3MAP
1785	{
1786	/** The key is the chunk id. */
1787	AVLU32NODECORE Core;
1788	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1789	* selection. */
1790	uint32_t iLastUsed;
1791	/** The current reference count. */
1792	uint32_t volatile cRefs;
1793	/** The current permanent reference count. */
1794	uint32_t volatile cPermRefs;
1795	/** The mapping address. */
1796	void *pv;
1797	} PGMCHUNKR3MAP;
1798
1799	/**
1800	* Allocation chunk ring-3 mapping TLB entry.
1801	*/
1802	typedef struct PGMCHUNKR3MAPTLBE
1803	{
1804	/** The chunk id. */
1805	uint32_t volatile idChunk;
1806	#if HC_ARCH_BITS == 64
1807	uint32_t u32Padding; /*< alignment padding. /
1808	#endif
1809	/** The chunk map. */
1810	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1811	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1812	#else
1813	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1814	#endif
1815	} PGMCHUNKR3MAPTLBE;
1816	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1817	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1818
1819	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1820	* @remark Must be a power of two value. */
1821	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1822
1823	/**
1824	* Allocation chunk ring-3 mapping TLB.
1825	*
1826	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1827	* At first glance this might look kinda odd since AVL trees are
1828	* supposed to give the most optimal lookup times of all trees
1829	* due to their balancing. However, take a tree with 1023 nodes
1830	* in it, that's 10 levels, meaning that most searches has to go
1831	* down 9 levels before they find what they want. This isn't fast
1832	* compared to a TLB hit. There is the factor of cache misses,
1833	* and of course the problem with trees and branch prediction.
1834	* This is why we use TLBs in front of most of the trees.
1835	*
1836	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1837	* difficult when we switch to the new inlined AVL trees (from kStuff).
1838	*/
1839	typedef struct PGMCHUNKR3MAPTLB
1840	{
1841	/** The TLB entries. */
1842	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1843	} PGMCHUNKR3MAPTLB;
1844
1845	/**
1846	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1847	* @returns Chunk TLB index.
1848	* @param idChunk The Chunk ID.
1849	*/
1850	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1851
1852
1853	/**
1854	* Ring-3 guest page mapping TLB entry.
1855	* @remarks used in ring-0 as well at the moment.
1856	*/
1857	typedef struct PGMPAGER3MAPTLBE
1858	{
1859	/** Address of the page. */
1860	RTGCPHYS volatile GCPhys;
1861	/** The guest page. */
1862	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1863	R3PTRTYPE(PPGMPAGE) volatile pPage;
1864	#else
1865	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1866	#endif
1867	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1868	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1869	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1870	#else
1871	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1872	#endif
1873	/** The address */
1874	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1875	R3PTRTYPE(void *) volatile pv;
1876	#else
1877	R3R0PTRTYPE(void *) volatile pv;
1878	#endif
1879	#if HC_ARCH_BITS == 32
1880	uint32_t u32Padding; /*< alignment padding. /
1881	#endif
1882	} PGMPAGER3MAPTLBE;
1883	/** Pointer to an entry in the HC physical TLB. */
1884	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1885
1886
1887	/** The number of entries in the ring-3 guest page mapping TLB.
1888	* @remarks The value must be a power of two. */
1889	#define PGM_PAGER3MAPTLB_ENTRIES 256
1890
1891	/**
1892	* Ring-3 guest page mapping TLB.
1893	* @remarks used in ring-0 as well at the moment.
1894	*/
1895	typedef struct PGMPAGER3MAPTLB
1896	{
1897	/** The TLB entries. */
1898	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1899	} PGMPAGER3MAPTLB;
1900	/** Pointer to the ring-3 guest page mapping TLB. */
1901	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1902
1903	/**
1904	* Calculates the index of the TLB entry for the specified guest page.
1905	* @returns Physical TLB index.
1906	* @param GCPhys The guest physical address.
1907	*/
1908	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1909
1910
1911	/**
1912	* Raw-mode context dynamic mapping cache entry.
1913	*
1914	* Because of raw-mode context being reloctable and all relocations are applied
1915	* in ring-3, this has to be defined here and be RC specific.
1916	*
1917	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1918	*/
1919	typedef struct PGMRCDYNMAPENTRY
1920	{
1921	/** The physical address of the currently mapped page.
1922	* This is duplicate for three reasons: cache locality, cache policy of the PT
1923	* mappings and sanity checks. */
1924	RTHCPHYS HCPhys;
1925	/** Pointer to the page. */
1926	RTRCPTR pvPage;
1927	/** The number of references. */
1928	int32_t volatile cRefs;
1929	/** PTE pointer union. */
1930	struct PGMRCDYNMAPENTRY_PPTE
1931	{
1932	/** PTE pointer, 32-bit legacy version. */
1933	RCPTRTYPE(PX86PTE) pLegacy;
1934	/** PTE pointer, PAE version. */
1935	RCPTRTYPE(PX86PTEPAE) pPae;
1936	} uPte;
1937	} PGMRCDYNMAPENTRY;
1938	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1939	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1940
1941
1942	/**
1943	* Dynamic mapping cache for the raw-mode context.
1944	*
1945	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1946	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1947	* so that we can perform relocations from PGMR3Relocate. This has the
1948	* consequence that we must have separate ring-0 and raw-mode context versions
1949	* of this struct even if they share the basic elements.
1950	*
1951	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1952	*/
1953	typedef struct PGMRCDYNMAP
1954	{
1955	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1956	uint32_t u32Magic;
1957	/** Array for tracking and managing the pages. */
1958	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1959	/** The cache size given as a number of pages. */
1960	uint32_t cPages;
1961	/** The current load.
1962	* This does not include guard pages. */
1963	uint32_t cLoad;
1964	/** The max load ever.
1965	* This is maintained to get trigger adding of more mapping space. */
1966	uint32_t cMaxLoad;
1967	/** The number of guard pages. */
1968	uint32_t cGuardPages;
1969	/** The number of users (protected by hInitLock). */
1970	uint32_t cUsers;
1971	} PGMRCDYNMAP;
1972	/** Pointer to the dynamic cache for the raw-mode context. */
1973	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1974
1975
1976	/**
1977	* Mapping cache usage set entry.
1978	*
1979	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1980	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1981	* cache. If it's extended to include ring-3, well, then something
1982	* will have be changed here...
1983	*/
1984	typedef struct PGMMAPSETENTRY
1985	{
1986	/** Pointer to the page. */
1987	#ifndef IN_RC
1988	RTR0PTR pvPage;
1989	#else
1990	RTRCPTR pvPage;
1991	# if HC_ARCH_BITS == 64
1992	uint32_t u32Alignment2;
1993	# endif
1994	#endif
1995	/** The mapping cache index. */
1996	uint16_t iPage;
1997	/** The number of references.
1998	* The max is UINT16_MAX - 1. */
1999	uint16_t cRefs;
2000	/** The number inlined references.
2001	* The max is UINT16_MAX - 1. */
2002	uint16_t cInlinedRefs;
2003	/** Unreferences. */
2004	uint16_t cUnrefs;
2005
2006	#if HC_ARCH_BITS == 32
2007	uint32_t u32Alignment1;
2008	#endif
2009	/** The physical address for this entry. */
2010	RTHCPHYS HCPhys;
2011	} PGMMAPSETENTRY;
2012	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2013	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2014	/** Pointer to a mapping cache usage set entry. */
2015	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2016
2017	/**
2018	* Mapping cache usage set.
2019	*
2020	* This is used in ring-0 and the raw-mode context to track dynamic mappings
2021	* done during exits / traps. The set is
2022	*/
2023	typedef struct PGMMAPSET
2024	{
2025	/** The number of occupied entries.
2026	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2027	* dynamic mappings. */
2028	uint32_t cEntries;
2029	/** The start of the current subset.
2030	* This is UINT32_MAX if no subset is currently open. */
2031	uint32_t iSubset;
2032	/** The index of the current CPU, only valid if the set is open. */
2033	int32_t iCpu;
2034	uint32_t alignment;
2035	/** The entries. */
2036	PGMMAPSETENTRY aEntries[64];
2037	/** HCPhys -> iEntry fast lookup table.
2038	* Use PGMMAPSET_HASH for hashing.
2039	* The entries may or may not be valid, check against cEntries. */
2040	uint8_t aiHashTable[128];
2041	} PGMMAPSET;
2042	AssertCompileSizeAlignment(PGMMAPSET, 8);
2043	/** Pointer to the mapping cache set. */
2044	typedef PGMMAPSET *PPGMMAPSET;
2045
2046	/** PGMMAPSET::cEntries value for a closed set. */
2047	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2048
2049	/** Hash function for aiHashTable. */
2050	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2051
2052
2053	/** @name Context neutral page mapper TLB.
2054	*
2055	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2056	* code is writting in a kind of context neutral way. Time will show whether
2057	* this actually makes sense or not...
2058	*
2059	* @todo this needs to be reconsidered and dropped/redone since the ring-0
2060	* context ends up using a global mapping cache on some platforms
2061	* (darwin).
2062	*
2063	* @{ */
2064	/** @typedef PPGMPAGEMAPTLB
2065	* The page mapper TLB pointer type for the current context. */
2066	/** @typedef PPGMPAGEMAPTLB
2067	* The page mapper TLB entry pointer type for the current context. */
2068	/** @typedef PPGMPAGEMAPTLB
2069	* The page mapper TLB entry pointer pointer type for the current context. */
2070	/** @def PGM_PAGEMAPTLB_ENTRIES
2071	* The number of TLB entries in the page mapper TLB for the current context. */
2072	/** @def PGM_PAGEMAPTLB_IDX
2073	* Calculate the TLB index for a guest physical address.
2074	* @returns The TLB index.
2075	* @param GCPhys The guest physical address. */
2076	/** @typedef PPGMPAGEMAP
2077	* Pointer to a page mapper unit for current context. */
2078	/** @typedef PPPGMPAGEMAP
2079	* Pointer to a page mapper unit pointer for current context. */
2080	#ifdef IN_RC
2081	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2082	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2083	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2084	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2085	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2086	typedef void * PPGMPAGEMAP;
2087	typedef void ** PPPGMPAGEMAP;
2088	//#elif IN_RING0
2089	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2090	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2091	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2092	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2093	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2094	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2095	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2096	#else
2097	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2098	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2099	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2100	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2101	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2102	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2103	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2104	#endif
2105	/** @} */
2106
2107
2108	/** @name PGM Pool Indexes.
2109	* Aka. the unique shadow page identifier.
2110	* @{ */
2111	/** NIL page pool IDX. */
2112	#define NIL_PGMPOOL_IDX 0
2113	/** The first normal index. There used to be 5 fictive pages up front, now
2114	* there is only the NIL page. */
2115	#define PGMPOOL_IDX_FIRST 1
2116	/** The last valid index. (inclusive, 14 bits) */
2117	#define PGMPOOL_IDX_LAST 0x3fff
2118	/** @} */
2119
2120	/** The NIL index for the parent chain. */
2121	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2122	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2123
2124	/**
2125	* Node in the chain linking a shadowed page to it's parent (user).
2126	*/
2127	#pragma pack(1)
2128	typedef struct PGMPOOLUSER
2129	{
2130	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2131	uint16_t iNext;
2132	/** The user page index. */
2133	uint16_t iUser;
2134	/** Index into the user table. */
2135	uint32_t iUserTable;
2136	} PGMPOOLUSER, *PPGMPOOLUSER;
2137	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2138	#pragma pack()
2139
2140
2141	/** The NIL index for the phys ext chain. */
2142	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2143	/** The NIL pte index for a phys ext chain slot. */
2144	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2145
2146	/**
2147	* Node in the chain of physical cross reference extents.
2148	* @todo Calling this an 'extent' is not quite right, find a better name.
2149	* @todo find out the optimal size of the aidx array
2150	*/
2151	#pragma pack(1)
2152	typedef struct PGMPOOLPHYSEXT
2153	{
2154	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2155	uint16_t iNext;
2156	/** Alignment. */
2157	uint16_t u16Align;
2158	/** The user page index. */
2159	uint16_t aidx[3];
2160	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2161	uint16_t apte[3];
2162	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2163	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2164	#pragma pack()
2165
2166
2167	/**
2168	* The kind of page that's being shadowed.
2169	*/
2170	typedef enum PGMPOOLKIND
2171	{
2172	/** The virtual invalid 0 entry. */
2173	PGMPOOLKIND_INVALID = 0,
2174	/** The entry is free (=unused). */
2175	PGMPOOLKIND_FREE,
2176
2177	/** Shw: 32-bit page table; Gst: no paging. */
2178	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2179	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2180	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2181	/** Shw: 32-bit page table; Gst: 4MB page. */
2182	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2183	/** Shw: PAE page table; Gst: no paging. */
2184	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2185	/** Shw: PAE page table; Gst: 32-bit page table. */
2186	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2187	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2188	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2189	/** Shw: PAE page table; Gst: PAE page table. */
2190	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2191	/** Shw: PAE page table; Gst: 2MB page. */
2192	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2193
2194	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2195	PGMPOOLKIND_32BIT_PD,
2196	/** Shw: 32-bit page directory. Gst: no paging. */
2197	PGMPOOLKIND_32BIT_PD_PHYS,
2198	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2199	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2200	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2201	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2202	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2203	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2204	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2205	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2206	/** Shw: PAE page directory; Gst: PAE page directory. */
2207	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2208	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2209	PGMPOOLKIND_PAE_PD_PHYS,
2210
2211	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2212	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2213	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2214	PGMPOOLKIND_PAE_PDPT,
2215	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2216	PGMPOOLKIND_PAE_PDPT_PHYS,
2217
2218	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2219	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2220	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2221	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2222	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2223	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2224	/** Shw: 64-bit page directory table; Gst: no paging. */
2225	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2226
2227	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2228	PGMPOOLKIND_64BIT_PML4,
2229
2230	/** Shw: EPT page directory pointer table; Gst: no paging. */
2231	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2232	/** Shw: EPT page directory table; Gst: no paging. */
2233	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2234	/** Shw: EPT page table; Gst: no paging. */
2235	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2236
2237	/** Shw: Root Nested paging table. */
2238	PGMPOOLKIND_ROOT_NESTED,
2239
2240	/** The last valid entry. */
2241	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2242	} PGMPOOLKIND;
2243
2244	/**
2245	* The access attributes of the page; only applies to big pages.
2246	*/
2247	typedef enum
2248	{
2249	PGMPOOLACCESS_DONTCARE = 0,
2250	PGMPOOLACCESS_USER_RW,
2251	PGMPOOLACCESS_USER_R,
2252	PGMPOOLACCESS_USER_RW_NX,
2253	PGMPOOLACCESS_USER_R_NX,
2254	PGMPOOLACCESS_SUPERVISOR_RW,
2255	PGMPOOLACCESS_SUPERVISOR_R,
2256	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2257	PGMPOOLACCESS_SUPERVISOR_R_NX
2258	} PGMPOOLACCESS;
2259
2260	/**
2261	* The tracking data for a page in the pool.
2262	*/
2263	typedef struct PGMPOOLPAGE
2264	{
2265	/** AVL node code with the (HC) physical address of this page. */
2266	AVLOHCPHYSNODECORE Core;
2267	/** Pointer to the R3 mapping of the page. */
2268	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2269	R3PTRTYPE(void *) pvPageR3;
2270	#else
2271	R3R0PTRTYPE(void *) pvPageR3;
2272	#endif
2273	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2274	uint32_t Alignment0;
2275	#endif
2276	/** The guest physical address. */
2277	RTGCPHYS GCPhys;
2278	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2279	uint8_t enmKind;
2280	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2281	uint8_t enmAccess;
2282	/** This supplements enmKind and enmAccess */
2283	bool fA20Enabled : 1;
2284
2285	/** Used to indicate that the page is zeroed. */
2286	bool fZeroed : 1;
2287	/** Used to indicate that a PT has non-global entries. */
2288	bool fSeenNonGlobal : 1;
2289	/** Used to indicate that we're monitoring writes to the guest page. */
2290	bool fMonitored : 1;
2291	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2292	* (All pages are in the age list.) */
2293	bool fCached : 1;
2294	/** This is used by the R3 access handlers when invoked by an async thread.
2295	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2296	bool volatile fReusedFlushPending : 1;
2297	/** Used to mark the page as dirty (write monitoring is temporarily
2298	* off). */
2299	bool fDirty : 1;
2300	bool fPadding1 : 1;
2301	bool fPadding2;
2302
2303	/** The index of this page. */
2304	uint16_t idx;
2305	/** The next entry in the list this page currently resides in.
2306	* It's either in the free list or in the GCPhys hash. */
2307	uint16_t iNext;
2308	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2309	uint16_t iUserHead;
2310	/** The number of present entries. */
2311	uint16_t cPresent;
2312	/** The first entry in the table which is present. */
2313	uint16_t iFirstPresent;
2314	/** The number of modifications to the monitored page. */
2315	uint16_t cModifications;
2316	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2317	uint16_t iModifiedNext;
2318	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2319	uint16_t iModifiedPrev;
2320	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2321	uint16_t iMonitoredNext;
2322	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2323	uint16_t iMonitoredPrev;
2324	/** The next page in the age list. */
2325	uint16_t iAgeNext;
2326	/** The previous page in the age list. */
2327	uint16_t iAgePrev;
2328	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2329	uint8_t idxDirtyEntry;
2330
2331	/** @name Access handler statistics to determine whether the guest is
2332	* (re)initializing a page table.
2333	* @{ */
2334	RTGCPTR GCPtrLastAccessHandlerRip;
2335	RTGCPTR GCPtrLastAccessHandlerFault;
2336	uint64_t cLastAccessHandler;
2337	/** @} */
2338	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2339	uint32_t volatile cLocked;
2340	#if GC_ARCH_BITS == 64
2341	uint32_t u32Alignment3;
2342	#endif
2343	# ifdef VBOX_STRICT
2344	RTGCPTR GCPtrDirtyFault;
2345	# endif
2346	} PGMPOOLPAGE;
2347	/** Pointer to a pool page. */
2348	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2349	/** Pointer to a const pool page. */
2350	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2351	/** Pointer to a pool page pointer. */
2352	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2353
2354
2355	/** The hash table size. */
2356	# define PGMPOOL_HASH_SIZE 0x40
2357	/** The hash function. */
2358	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2359
2360
2361	/**
2362	* The shadow page pool instance data.
2363	*
2364	* It's all one big allocation made at init time, except for the
2365	* pages that is. The user nodes follows immediately after the
2366	* page structures.
2367	*/
2368	typedef struct PGMPOOL
2369	{
2370	/** The VM handle - R3 Ptr. */
2371	PVMR3 pVMR3;
2372	/** The VM handle - R0 Ptr. */
2373	PVMR0 pVMR0;
2374	/** The VM handle - RC Ptr. */
2375	PVMRC pVMRC;
2376	/** The max pool size. This includes the special IDs. */
2377	uint16_t cMaxPages;
2378	/** The current pool size. */
2379	uint16_t cCurPages;
2380	/** The head of the free page list. */
2381	uint16_t iFreeHead;
2382	/* Padding. */
2383	uint16_t u16Padding;
2384	/** Head of the chain of free user nodes. */
2385	uint16_t iUserFreeHead;
2386	/** The number of user nodes we've allocated. */
2387	uint16_t cMaxUsers;
2388	/** The number of present page table entries in the entire pool. */
2389	uint32_t cPresent;
2390	/** Pointer to the array of user nodes - RC pointer. */
2391	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2392	/** Pointer to the array of user nodes - R3 pointer. */
2393	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2394	/** Pointer to the array of user nodes - R0 pointer. */
2395	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2396	/** Head of the chain of free phys ext nodes. */
2397	uint16_t iPhysExtFreeHead;
2398	/** The number of user nodes we've allocated. */
2399	uint16_t cMaxPhysExts;
2400	/** Pointer to the array of physical xref extent - RC pointer. */
2401	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2402	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2403	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2404	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2405	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2406	/** Hash table for GCPhys addresses. */
2407	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2408	/** The head of the age list. */
2409	uint16_t iAgeHead;
2410	/** The tail of the age list. */
2411	uint16_t iAgeTail;
2412	/** Set if the cache is enabled. */
2413	bool fCacheEnabled;
2414	/** Alignment padding. */
2415	bool afPadding1[3];
2416	/** Head of the list of modified pages. */
2417	uint16_t iModifiedHead;
2418	/** The current number of modified pages. */
2419	uint16_t cModifiedPages;
2420	/** Physical access handler type registration handle. */
2421	PGMPHYSHANDLERTYPE hAccessHandlerType;
2422	/** Next available slot (in aDirtyPages). */
2423	uint32_t idxFreeDirtyPage;
2424	/** Number of active dirty pages. */
2425	uint32_t cDirtyPages;
2426	/** Array of current dirty pgm pool page indices. */
2427	struct
2428	{
2429	uint16_t uIdx;
2430	uint16_t Alignment[3];
2431	uint64_t aPage[512];
2432	} aDirtyPages[16];
2433	/** The number of pages currently in use. */
2434	uint16_t cUsedPages;
2435	#ifdef VBOX_WITH_STATISTICS
2436	/** The high water mark for cUsedPages. */
2437	uint16_t cUsedPagesHigh;
2438	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2439	/** Profiling pgmPoolAlloc(). */
2440	STAMPROFILEADV StatAlloc;
2441	/** Profiling pgmR3PoolClearDoIt(). */
2442	STAMPROFILE StatClearAll;
2443	/** Profiling pgmR3PoolReset(). */
2444	STAMPROFILE StatR3Reset;
2445	/** Profiling pgmPoolFlushPage(). */
2446	STAMPROFILE StatFlushPage;
2447	/** Profiling pgmPoolFree(). */
2448	STAMPROFILE StatFree;
2449	/** Counting explicit flushes by PGMPoolFlushPage(). */
2450	STAMCOUNTER StatForceFlushPage;
2451	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2452	STAMCOUNTER StatForceFlushDirtyPage;
2453	/** Counting flushes for reused pages. */
2454	STAMCOUNTER StatForceFlushReused;
2455	/** Profiling time spent zeroing pages. */
2456	STAMPROFILE StatZeroPage;
2457	/** Profiling of pgmPoolTrackDeref. */
2458	STAMPROFILE StatTrackDeref;
2459	/** Profiling pgmTrackFlushGCPhysPT. */
2460	STAMPROFILE StatTrackFlushGCPhysPT;
2461	/** Profiling pgmTrackFlushGCPhysPTs. */
2462	STAMPROFILE StatTrackFlushGCPhysPTs;
2463	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2464	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2465	/** Number of times we've been out of user records. */
2466	STAMCOUNTER StatTrackFreeUpOneUser;
2467	/** Nr of flushed entries. */
2468	STAMCOUNTER StatTrackFlushEntry;
2469	/** Nr of updated entries. */
2470	STAMCOUNTER StatTrackFlushEntryKeep;
2471	/** Profiling deref activity related tracking GC physical pages. */
2472	STAMPROFILE StatTrackDerefGCPhys;
2473	/** Number of linear searches for a HCPhys in the ram ranges. */
2474	STAMCOUNTER StatTrackLinearRamSearches;
2475	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2476	STAMCOUNTER StamTrackPhysExtAllocFailures;
2477	/** Profiling the RC/R0 access handler. */
2478	STAMPROFILE StatMonitorRZ;
2479	/** Times we've failed interpreting the instruction. */
2480	STAMCOUNTER StatMonitorRZEmulateInstr;
2481	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2482	STAMPROFILE StatMonitorRZFlushPage;
2483	/* Times we've detected a page table reinit. */
2484	STAMCOUNTER StatMonitorRZFlushReinit;
2485	/** Counting flushes for pages that are modified too often. */
2486	STAMCOUNTER StatMonitorRZFlushModOverflow;
2487	/** Times we've detected fork(). */
2488	STAMCOUNTER StatMonitorRZFork;
2489	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2490	STAMPROFILE StatMonitorRZHandled;
2491	/** Times we've failed interpreting a patch code instruction. */
2492	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2493	/** Times we've failed interpreting a patch code instruction during flushing. */
2494	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2495	/** The number of times we've seen rep prefixes we can't handle. */
2496	STAMCOUNTER StatMonitorRZRepPrefix;
2497	/** Profiling the REP STOSD cases we've handled. */
2498	STAMPROFILE StatMonitorRZRepStosd;
2499	/** Nr of handled PT faults. */
2500	STAMCOUNTER StatMonitorRZFaultPT;
2501	/** Nr of handled PD faults. */
2502	STAMCOUNTER StatMonitorRZFaultPD;
2503	/** Nr of handled PDPT faults. */
2504	STAMCOUNTER StatMonitorRZFaultPDPT;
2505	/** Nr of handled PML4 faults. */
2506	STAMCOUNTER StatMonitorRZFaultPML4;
2507
2508	/** Profiling the R3 access handler. */
2509	STAMPROFILE StatMonitorR3;
2510	/** Times we've failed interpreting the instruction. */
2511	STAMCOUNTER StatMonitorR3EmulateInstr;
2512	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2513	STAMPROFILE StatMonitorR3FlushPage;
2514	/* Times we've detected a page table reinit. */
2515	STAMCOUNTER StatMonitorR3FlushReinit;
2516	/** Counting flushes for pages that are modified too often. */
2517	STAMCOUNTER StatMonitorR3FlushModOverflow;
2518	/** Times we've detected fork(). */
2519	STAMCOUNTER StatMonitorR3Fork;
2520	/** Profiling the R3 access we've handled (except REP STOSD). */
2521	STAMPROFILE StatMonitorR3Handled;
2522	/** The number of times we've seen rep prefixes we can't handle. */
2523	STAMCOUNTER StatMonitorR3RepPrefix;
2524	/** Profiling the REP STOSD cases we've handled. */
2525	STAMPROFILE StatMonitorR3RepStosd;
2526	/** Nr of handled PT faults. */
2527	STAMCOUNTER StatMonitorR3FaultPT;
2528	/** Nr of handled PD faults. */
2529	STAMCOUNTER StatMonitorR3FaultPD;
2530	/** Nr of handled PDPT faults. */
2531	STAMCOUNTER StatMonitorR3FaultPDPT;
2532	/** Nr of handled PML4 faults. */
2533	STAMCOUNTER StatMonitorR3FaultPML4;
2534	/** The number of times we're called in an async thread an need to flush. */
2535	STAMCOUNTER StatMonitorR3Async;
2536	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2537	STAMCOUNTER StatResetDirtyPages;
2538	/** Times we've called pgmPoolAddDirtyPage. */
2539	STAMCOUNTER StatDirtyPage;
2540	/** Times we've had to flush duplicates for dirty page management. */
2541	STAMCOUNTER StatDirtyPageDupFlush;
2542	/** Times we've had to flush because of overflow. */
2543	STAMCOUNTER StatDirtyPageOverFlowFlush;
2544
2545	/** The high water mark for cModifiedPages. */
2546	uint16_t cModifiedPagesHigh;
2547	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2548
2549	/** The number of cache hits. */
2550	STAMCOUNTER StatCacheHits;
2551	/** The number of cache misses. */
2552	STAMCOUNTER StatCacheMisses;
2553	/** The number of times we've got a conflict of 'kind' in the cache. */
2554	STAMCOUNTER StatCacheKindMismatches;
2555	/** Number of times we've been out of pages. */
2556	STAMCOUNTER StatCacheFreeUpOne;
2557	/** The number of cacheable allocations. */
2558	STAMCOUNTER StatCacheCacheable;
2559	/** The number of uncacheable allocations. */
2560	STAMCOUNTER StatCacheUncacheable;
2561	#else
2562	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2563	#endif
2564	/** The AVL tree for looking up a page by its HC physical address. */
2565	AVLOHCPHYSTREE HCPhysTree;
2566	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2567	/** Array of pages. (cMaxPages in length)
2568	* The Id is the index into thist array.
2569	*/
2570	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2571	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2572	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2573	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2574	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2575	#ifdef VBOX_WITH_STATISTICS
2576	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2577	#endif
2578	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2579
2580
2581	/** @def PGMPOOL_PAGE_2_PTR
2582	* Maps a pool page pool into the current context.
2583	*
2584	* @returns VBox status code.
2585	* @param a_pVM Pointer to the VM.
2586	* @param a_pPage The pool page.
2587	*
2588	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2589	* small page window employeed by that function. Be careful.
2590	* @remark There is no need to assert on the result.
2591	*/
2592	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2593	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2594	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2595	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2596	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2597	{
2598	AssertPtr(a_pPage);
2599	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2600	return a_pPage->pvPageR3;
2601	}
2602	#else
2603	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2604	#endif
2605
2606
2607	/** @def PGMPOOL_PAGE_2_PTR_V2
2608	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2609	*
2610	* @returns VBox status code.
2611	* @param a_pVM Pointer to the VM.
2612	* @param a_pVCpu The current CPU.
2613	* @param a_pPage The pool page.
2614	*
2615	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2616	* small page window employeed by that function. Be careful.
2617	* @remark There is no need to assert on the result.
2618	*/
2619	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2620	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2621	#else
2622	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2623	#endif
2624
2625
2626	/** @name Per guest page tracking data.
2627	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2628	* is to use more bits for it and split it up later on. But for now we'll play
2629	* safe and change as little as possible.
2630	*
2631	* The 16-bit word has two parts:
2632	*
2633	* The first 14-bit forms the @a idx field. It is either the index of a page in
2634	* the shadow page pool, or and index into the extent list.
2635	*
2636	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2637	* shadow page pool references to the page. If cRefs equals
2638	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2639	* (misnomer) table and not the shadow page pool.
2640	*
2641	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2642	* the 16-bit word.
2643	*
2644	* @{ */
2645	/** The shift count for getting to the cRefs part. */
2646	#define PGMPOOL_TD_CREFS_SHIFT 14
2647	/** The mask applied after shifting the tracking data down by
2648	* PGMPOOL_TD_CREFS_SHIFT. */
2649	#define PGMPOOL_TD_CREFS_MASK 0x3
2650	/** The cRefs value used to indicate that the idx is the head of a
2651	* physical cross reference list. */
2652	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2653	/** The shift used to get idx. */
2654	#define PGMPOOL_TD_IDX_SHIFT 0
2655	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2656	#define PGMPOOL_TD_IDX_MASK 0x3fff
2657	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2658	* simply too many mappings of this page. */
2659	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2660
2661	/** @def PGMPOOL_TD_MAKE
2662	* Makes a 16-bit tracking data word.
2663	*
2664	* @returns tracking data.
2665	* @param cRefs The @a cRefs field. Must be within bounds!
2666	* @param idx The @a idx field. Must also be within bounds! */
2667	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2668
2669	/** @def PGMPOOL_TD_GET_CREFS
2670	* Get the @a cRefs field from a tracking data word.
2671	*
2672	* @returns The @a cRefs field
2673	* @param u16 The tracking data word.
2674	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2675	* non-zero @a u16. */
2676	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2677
2678	/** @def PGMPOOL_TD_GET_IDX
2679	* Get the @a idx field from a tracking data word.
2680	*
2681	* @returns The @a idx field
2682	* @param u16 The tracking data word. */
2683	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2684	/** @} */
2685
2686
2687
2688	/** @name A20 gate macros
2689	* @{ */
2690	#define PGM_WITH_A20
2691	#ifdef PGM_WITH_A20
2692	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2693	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2694	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2695	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2696	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2697	#else
2698	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2699	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2700	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2701	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2702	#endif
2703	/** @} */
2704
2705
2706	/**
2707	* Roots and anchors for trees and list employing self relative offsets as
2708	* pointers.
2709	*
2710	* When using self-relative offsets instead of pointers, the offsets needs to be
2711	* the same in all offsets. Thus the roots and anchors needs to live on the
2712	* hyper heap just like the nodes.
2713	*/
2714	typedef struct PGMTREES
2715	{
2716	/** List of physical access handler types (offset pointers) of type
2717	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2718	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2719	/** Physical access handlers (AVL range+offsetptr tree). */
2720	AVLROGCPHYSTREE PhysHandlers;
2721	#ifdef VBOX_WITH_RAW_MODE
2722	/** Virtual access handlers (AVL range + GC ptr tree). */
2723	AVLROGCPTRTREE VirtHandlers;
2724	/** Virtual access handlers (Phys range AVL range + offsetptr tree).
2725	* @remarks Handler of the hypervisor kind are of course not present. */
2726	AVLROGCPHYSTREE PhysToVirtHandlers;
2727	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2728	AVLROGCPTRTREE HyperVirtHandlers;
2729	/** List of virtual access handler types (offset pointers) of type
2730	* PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2731	RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2732	#endif
2733	} PGMTREES;
2734	/** Pointer to PGM trees. */
2735	typedef PGMTREES *PPGMTREES;
2736
2737
2738	/**
2739	* Page fault guest state for the AMD64 paging mode.
2740	*/
2741	typedef struct PGMPTWALKCORE
2742	{
2743	/** The guest virtual address that is being resolved by the walk
2744	* (input). */
2745	RTGCPTR GCPtr;
2746
2747	/** The guest physical address that is the result of the walk.
2748	* @remarks only valid if fSucceeded is set. */
2749	RTGCPHYS GCPhys;
2750
2751	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2752	bool fSucceeded;
2753	/** The level problem arrised at.
2754	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2755	* level 8. This is 0 on success. */
2756	uint8_t uLevel;
2757	/** Set if the page isn't present. */
2758	bool fNotPresent;
2759	/** Encountered a bad physical address. */
2760	bool fBadPhysAddr;
2761	/** Set if there was reserved bit violations. */
2762	bool fRsvdError;
2763	/** Set if it involves a big page (2/4 MB). */
2764	bool fBigPage;
2765	/** Set if it involves a gigantic page (1 GB). */
2766	bool fGigantPage;
2767	/** The effect X86_PTE_US flag for the address. */
2768	bool fEffectiveUS;
2769	/** The effect X86_PTE_RW flag for the address. */
2770	bool fEffectiveRW;
2771	/** The effect X86_PTE_NX flag for the address. */
2772	bool fEffectiveNX;
2773	} PGMPTWALKCORE;
2774
2775
2776	/**
2777	* Guest page table walk for the AMD64 mode.
2778	*/
2779	typedef struct PGMPTWALKGSTAMD64
2780	{
2781	/** The common core. */
2782	PGMPTWALKCORE Core;
2783
2784	PX86PML4 pPml4;
2785	PX86PML4E pPml4e;
2786	X86PML4E Pml4e;
2787
2788	PX86PDPT pPdpt;
2789	PX86PDPE pPdpe;
2790	X86PDPE Pdpe;
2791
2792	PX86PDPAE pPd;
2793	PX86PDEPAE pPde;
2794	X86PDEPAE Pde;
2795
2796	PX86PTPAE pPt;
2797	PX86PTEPAE pPte;
2798	X86PTEPAE Pte;
2799	} PGMPTWALKGSTAMD64;
2800	/** Pointer to a AMD64 guest page table walk. */
2801	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2802	/** Pointer to a const AMD64 guest page table walk. */
2803	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2804
2805	/**
2806	* Guest page table walk for the PAE mode.
2807	*/
2808	typedef struct PGMPTWALKGSTPAE
2809	{
2810	/** The common core. */
2811	PGMPTWALKCORE Core;
2812
2813	PX86PDPT pPdpt;
2814	PX86PDPE pPdpe;
2815	X86PDPE Pdpe;
2816
2817	PX86PDPAE pPd;
2818	PX86PDEPAE pPde;
2819	X86PDEPAE Pde;
2820
2821	PX86PTPAE pPt;
2822	PX86PTEPAE pPte;
2823	X86PTEPAE Pte;
2824	} PGMPTWALKGSTPAE;
2825	/** Pointer to a PAE guest page table walk. */
2826	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2827	/** Pointer to a const AMD64 guest page table walk. */
2828	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2829
2830	/**
2831	* Guest page table walk for the 32-bit mode.
2832	*/
2833	typedef struct PGMPTWALKGST32BIT
2834	{
2835	/** The common core. */
2836	PGMPTWALKCORE Core;
2837
2838	PX86PD pPd;
2839	PX86PDE pPde;
2840	X86PDE Pde;
2841
2842	PX86PT pPt;
2843	PX86PTE pPte;
2844	X86PTE Pte;
2845	} PGMPTWALKGST32BIT;
2846	/** Pointer to a 32-bit guest page table walk. */
2847	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2848	/** Pointer to a const 32-bit guest page table walk. */
2849	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2850
2851	/**
2852	* Which part of PGMPTWALKGST that is valid.
2853	*/
2854	typedef enum PGMPTWALKGSTTYPE
2855	{
2856	/** Customary invalid 0 value. */
2857	PGMPTWALKGSTTYPE_INVALID = 0,
2858	/** PGMPTWALKGST::u.Amd64 is valid. */
2859	PGMPTWALKGSTTYPE_AMD64,
2860	/** PGMPTWALKGST::u.Pae is valid. */
2861	PGMPTWALKGSTTYPE_PAE,
2862	/** PGMPTWALKGST::u.Legacy is valid. */
2863	PGMPTWALKGSTTYPE_32BIT,
2864	/** Customary 32-bit type hack. */
2865	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2866	} PGMPTWALKGSTTYPE;
2867
2868	/**
2869	* Combined guest page table walk result.
2870	*/
2871	typedef struct PGMPTWALKGST
2872	{
2873	union
2874	{
2875	/** The page walker core - always valid. */
2876	PGMPTWALKCORE Core;
2877	/** The page walker for AMD64. */
2878	PGMPTWALKGSTAMD64 Amd64;
2879	/** The page walker for PAE (32-bit). */
2880	PGMPTWALKGSTPAE Pae;
2881	/** The page walker for 32-bit paging (called legacy due to C naming
2882	* convension). */
2883	PGMPTWALKGST32BIT Legacy;
2884	} u;
2885	/** Indicates which part of the union is valid. */
2886	PGMPTWALKGSTTYPE enmType;
2887	} PGMPTWALKGST;
2888	/** Pointer to a combined guest page table walk result. */
2889	typedef PGMPTWALKGST *PPGMPTWALKGST;
2890	/** Pointer to a read-only combined guest page table walk result. */
2891	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2892
2893
2894	/** @name Paging mode macros
2895	* @{
2896	*/
2897	#ifdef IN_RC
2898	# define PGM_CTX(a,b) a##RC##b
2899	# define PGM_CTX_STR(a,b) a "GC" b
2900	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2901	#else
2902	# ifdef IN_RING3
2903	# define PGM_CTX(a,b) a##R3##b
2904	# define PGM_CTX_STR(a,b) a "R3" b
2905	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2906	# else
2907	# define PGM_CTX(a,b) a##R0##b
2908	# define PGM_CTX_STR(a,b) a "R0" b
2909	# define PGM_CTX_DECL(type) VMMDECL(type)
2910	# endif
2911	#endif
2912
2913	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2914	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2915	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2916	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2917	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2918	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2919	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2920	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2921	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2922	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2923	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2924	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2925	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2926	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2927	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2928	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2929	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2930
2931	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2932	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2933	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2934	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2935	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2936	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2937	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2938	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2939	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2940	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2941	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2942	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2943	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2944	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2945	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2946	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2947	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2948
2949	/* Shw_Gst */
2950	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2951	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2952	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2953	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2954	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2955	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2956	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2957	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2958	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2959	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2960	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2961	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2962	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2963	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2964	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2965	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2966	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2967	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2968	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2969
2970	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2971	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2972	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2973	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2974	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2975	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2976	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2977	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2978	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2979	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2980	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2981	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2982	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2983	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2984	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2985	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2986	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2987	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2988	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2989	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2990	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2991	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2992	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2993	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2994	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2995	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2996	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2997	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2998	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2999	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
3000	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
3001	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
3002	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3003	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3004	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3005	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3006	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3007
3008	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3009	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
3010	/** @} */
3011
3012	/**
3013	* Data for each paging mode.
3014	*/
3015	typedef struct PGMMODEDATA
3016	{
3017	/** The guest mode type. */
3018	uint32_t uGstType;
3019	/** The shadow mode type. */
3020	uint32_t uShwType;
3021
3022	/** @name Function pointers for Shadow paging.
3023	* @{
3024	*/
3025	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3026	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3027	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3028	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3029
3030	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3031	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3032
3033	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3034	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3035	/** @} */
3036
3037	/** @name Function pointers for Guest paging.
3038	* @{
3039	*/
3040	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3041	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3042	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3043	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3044	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3045	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3046	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3047	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3048	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3049	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3050	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3051	/** @} */
3052
3053	/** @name Function pointers for Both Shadow and Guest paging.
3054	* @{
3055	*/
3056	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3057	/* no pfnR3BthTrap0eHandler */
3058	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3059	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3060	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3061	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3062	#ifdef VBOX_STRICT
3063	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3064	#endif
3065	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3066	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3067
3068	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3069	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3070	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3071	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3072	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3073	#ifdef VBOX_STRICT
3074	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3075	#endif
3076	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3077	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3078
3079	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3080	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3081	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3082	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3083	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3084	#ifdef VBOX_STRICT
3085	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3086	#endif
3087	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3088	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3089	/** @} */
3090	} PGMMODEDATA, *PPGMMODEDATA;
3091
3092
3093	#ifdef VBOX_WITH_STATISTICS
3094	/**
3095	* PGM statistics.
3096	*
3097	* These lives on the heap when compiled in as they would otherwise waste
3098	* unnecessary space in release builds.
3099	*/
3100	typedef struct PGMSTATS
3101	{
3102	/* R3 only: */
3103	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3104	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3105
3106	/* R3+RZ */
3107	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3108	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3109	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3110	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3111	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3112	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3113	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3114	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3115	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3116	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3117	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3118	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3119	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3120	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3121	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3122	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3123	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3124	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3125	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3126	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3127	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3128	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3129	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3130	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3131	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3132	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3133	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3134	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3135	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3136	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3137	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3138	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3139
3140	/* RC only: */
3141	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3142	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3143
3144	STAMCOUNTER StatRZPhysRead;
3145	STAMCOUNTER StatRZPhysReadBytes;
3146	STAMCOUNTER StatRZPhysWrite;
3147	STAMCOUNTER StatRZPhysWriteBytes;
3148	STAMCOUNTER StatR3PhysRead;
3149	STAMCOUNTER StatR3PhysReadBytes;
3150	STAMCOUNTER StatR3PhysWrite;
3151	STAMCOUNTER StatR3PhysWriteBytes;
3152	STAMCOUNTER StatRCPhysRead;
3153	STAMCOUNTER StatRCPhysReadBytes;
3154	STAMCOUNTER StatRCPhysWrite;
3155	STAMCOUNTER StatRCPhysWriteBytes;
3156
3157	STAMCOUNTER StatRZPhysSimpleRead;
3158	STAMCOUNTER StatRZPhysSimpleReadBytes;
3159	STAMCOUNTER StatRZPhysSimpleWrite;
3160	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3161	STAMCOUNTER StatR3PhysSimpleRead;
3162	STAMCOUNTER StatR3PhysSimpleReadBytes;
3163	STAMCOUNTER StatR3PhysSimpleWrite;
3164	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3165	STAMCOUNTER StatRCPhysSimpleRead;
3166	STAMCOUNTER StatRCPhysSimpleReadBytes;
3167	STAMCOUNTER StatRCPhysSimpleWrite;
3168	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3169
3170	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3171	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3172	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3173	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3174	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3175	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3176	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3177
3178	/** Time spent by the host OS for large page allocation. */
3179	STAMPROFILE StatAllocLargePage;
3180	/** Time spent clearing the newly allocated large pages. */
3181	STAMPROFILE StatClearLargePage;
3182	/** The number of times allocating a large pages takes more than the allowed period. */
3183	STAMCOUNTER StatLargePageOverflow;
3184	/** pgmPhysIsValidLargePage profiling - R3 */
3185	STAMPROFILE StatR3IsValidLargePage;
3186	/** pgmPhysIsValidLargePage profiling - RZ*/
3187	STAMPROFILE StatRZIsValidLargePage;
3188
3189	STAMPROFILE StatChunkAging;
3190	STAMPROFILE StatChunkFindCandidate;
3191	STAMPROFILE StatChunkUnmap;
3192	STAMPROFILE StatChunkMap;
3193	} PGMSTATS;
3194	#endif /* VBOX_WITH_STATISTICS */
3195
3196
3197	/**
3198	* Converts a PGM pointer into a VM pointer.
3199	* @returns Pointer to the VM structure the PGM is part of.
3200	* @param pPGM Pointer to PGM instance data.
3201	*/
3202	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3203
3204	/**
3205	* PGM Data (part of VM)
3206	*/
3207	typedef struct PGM
3208	{
3209	/** Offset to the VM structure. */
3210	int32_t offVM;
3211	/** Offset of the PGMCPU structure relative to VMCPU. */
3212	int32_t offVCpuPGM;
3213
3214	/** @cfgm{/RamPreAlloc, boolean, false}
3215	* Indicates whether the base RAM should all be allocated before starting
3216	* the VM (default), or if it should be allocated when first written to.
3217	*/
3218	bool fRamPreAlloc;
3219	/** Indicates whether write monitoring is currently in use.
3220	* This is used to prevent conflicts between live saving and page sharing
3221	* detection. */
3222	bool fPhysWriteMonitoringEngaged;
3223	/** Set if the CPU has less than 52-bit physical address width.
3224	* This is used */
3225	bool fLessThan52PhysicalAddressBits;
3226	/** Set when nested paging is active.
3227	* This is meant to save calls to HMIsNestedPagingActive and let the
3228	* compilers optimize the code better. Whether we use nested paging or
3229	* not is something we find out during VMM initialization and we won't
3230	* change this later on. */
3231	bool fNestedPaging;
3232	/** The host paging mode. (This is what SUPLib reports.) */
3233	SUPPAGINGMODE enmHostMode;
3234	/** We're not in a state which permits writes to guest memory.
3235	* (Only used in strict builds.) */
3236	bool fNoMorePhysWrites;
3237	/** @cfgm{/PageFusionAllowed, boolean, false}
3238	* Whether page fusion is allowed. */
3239	bool fPageFusionAllowed;
3240	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3241	* Whether PCI passthrough is enabled. */
3242	bool fPciPassthrough;
3243	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3244	uint8_t cMmio2Regions;
3245	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3246	bool afAlignment1[1];
3247
3248	/** Indicates that PGMR3FinalizeMappings has been called and that further
3249	* PGMR3MapIntermediate calls will be rejected. */
3250	bool fFinalizedMappings;
3251	/** If set no conflict checks are required. */
3252	bool fMappingsFixed;
3253	/** If set if restored as fixed but we were unable to re-fixate at the old
3254	* location because of room or address incompatibilities. */
3255	bool fMappingsFixedRestored;
3256	/** Size of fixed mapping.
3257	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3258	uint32_t cbMappingFixed;
3259	/** Generation ID for the RAM ranges. This member is incremented everytime
3260	* a RAM range is linked or unlinked. */
3261	uint32_t volatile idRamRangesGen;
3262
3263	/** Base address (GC) of fixed mapping.
3264	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3265	RTGCPTR GCPtrMappingFixed;
3266	/** The address of the previous RAM range mapping. */
3267	RTGCPTR GCPtrPrevRamRangeMapping;
3268
3269	/** Physical access handler type for ROM protection. */
3270	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3271	/** Alignment padding. */
3272	uint32_t u32Padding;
3273
3274	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3275	RTGCPHYS GCPhys4MBPSEMask;
3276	/** Mask containing the invalid bits of a guest physical address.
3277	* @remarks this does not stop at bit 52. */
3278	RTGCPHYS GCPhysInvAddrMask;
3279
3280
3281	/** RAM range TLB for R3. */
3282	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3283	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3284	* This is sorted by physical address and contains no overlapping ranges. */
3285	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3286	/** Root of the RAM range search tree for ring-3. */
3287	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3288	/** PGM offset based trees - R3 Ptr. */
3289	R3PTRTYPE(PPGMTREES) pTreesR3;
3290	/** Caching the last physical handler we looked up in R3. */
3291	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3292	/** Shadow Page Pool - R3 Ptr. */
3293	R3PTRTYPE(PPGMPOOL) pPoolR3;
3294	/** Linked list of GC mappings - for HC.
3295	* The list is sorted ascending on address. */
3296	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3297	/** Pointer to the list of ROM ranges - for R3.
3298	* This is sorted by physical address and contains no overlapping ranges. */
3299	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3300	/** Pointer to the list of MMIO2 ranges - for R3.
3301	* Registration order. */
3302	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3303	/** Pointer to SHW+GST mode data (function pointers).
3304	* The index into this table is made up from */
3305	R3PTRTYPE(PPGMMODEDATA) paModeData;
3306	RTR3PTR R3PtrAlignment0;
3307	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3308	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3309
3310	/** RAM range TLB for R0. */
3311	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3312	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3313	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3314	/** Root of the RAM range search tree for ring-0. */
3315	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3316	/** PGM offset based trees - R0 Ptr. */
3317	R0PTRTYPE(PPGMTREES) pTreesR0;
3318	/** Caching the last physical handler we looked up in R0. */
3319	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3320	/** Shadow Page Pool - R0 Ptr. */
3321	R0PTRTYPE(PPGMPOOL) pPoolR0;
3322	/** Linked list of GC mappings - for R0.
3323	* The list is sorted ascending on address. */
3324	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3325	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3326	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3327	RTR0PTR R0PtrAlignment0;
3328	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3329	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3330
3331	/** RAM range TLB for RC. */
3332	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3333	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3334	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3335	/** Root of the RAM range search tree for raw-mode context. */
3336	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3337	/** PGM offset based trees - RC Ptr. */
3338	RCPTRTYPE(PPGMTREES) pTreesRC;
3339	/** Caching the last physical handler we looked up in RC. */
3340	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3341	/** Shadow Page Pool - RC Ptr. */
3342	RCPTRTYPE(PPGMPOOL) pPoolRC;
3343	/** Linked list of GC mappings - for RC.
3344	* The list is sorted ascending on address. */
3345	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3346	/** RC pointer corresponding to PGM::pRomRangesR3. */
3347	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3348	RTRCPTR RCPtrAlignment0;
3349	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3350	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3351	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3352	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3353
3354
3355	/** Pointer to the 5 page CR3 content mapping.
3356	* The first page is always the CR3 (in some form) while the 4 other pages
3357	* are used of the PDs in PAE mode. */
3358	RTGCPTR GCPtrCR3Mapping;
3359
3360	/** @name Intermediate Context
3361	* @{ */
3362	/** Pointer to the intermediate page directory - Normal. */
3363	R3PTRTYPE(PX86PD) pInterPD;
3364	/** Pointer to the intermediate page tables - Normal.
3365	* There are two page tables, one for the identity mapping and one for
3366	* the host context mapping (of the core code). */
3367	R3PTRTYPE(PX86PT) apInterPTs[2];
3368	/** Pointer to the intermediate page tables - PAE. */
3369	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3370	/** Pointer to the intermediate page directory - PAE. */
3371	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3372	/** Pointer to the intermediate page directory - PAE. */
3373	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3374	/** Pointer to the intermediate page-map level 4 - AMD64. */
3375	R3PTRTYPE(PX86PML4) pInterPaePML4;
3376	/** Pointer to the intermediate page directory - AMD64. */
3377	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3378	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3379	RTHCPHYS HCPhysInterPD;
3380	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3381	RTHCPHYS HCPhysInterPaePDPT;
3382	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3383	RTHCPHYS HCPhysInterPaePML4;
3384	/** @} */
3385
3386	/** Base address of the dynamic page mapping area.
3387	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3388	*
3389	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3390	* work out. Some cleaning up of the initialization that would
3391	* remove this memory is yet to be done...
3392	*/
3393	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3394	/** The address of the raw-mode context mapping cache. */
3395	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3396	/** The address of the ring-0 mapping cache if we're making use of it. */
3397	RTR0PTR pvR0DynMapUsed;
3398
3399	/** Hack: Number of deprecated page mapping locks taken by the current lock
3400	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3401	uint32_t cDeprecatedPageLocks;
3402	#if HC_ARCH_BITS == 64
3403	/** Alignment padding. */
3404	uint32_t u32Alignment2;
3405	#endif
3406
3407
3408	/** PGM critical section.
3409	* This protects the physical & virtual access handlers, ram ranges,
3410	* and the page flag updating (some of it anyway).
3411	*/
3412	PDMCRITSECT CritSectX;
3413
3414	/**
3415	* Data associated with managing the ring-3 mappings of the allocation chunks.
3416	*/
3417	struct
3418	{
3419	/** The chunk tree, ordered by chunk id. */
3420	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3421	R3PTRTYPE(PAVLU32NODECORE) pTree;
3422	#else
3423	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3424	#endif
3425	#if HC_ARCH_BITS == 32
3426	uint32_t u32Alignment0;
3427	#endif
3428	/** The chunk mapping TLB. */
3429	PGMCHUNKR3MAPTLB Tlb;
3430	/** The number of mapped chunks. */
3431	uint32_t c;
3432	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3433	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3434	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3435	uint32_t cMax;
3436	/** The current time. This is incremented whenever a chunk is inserted. */
3437	uint32_t iNow;
3438	/** Alignment padding. */
3439	uint32_t u32Alignment1;
3440	} ChunkR3Map;
3441
3442	/**
3443	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3444	*/
3445	PGMPAGER3MAPTLB PhysTlbHC;
3446
3447	/** @name The zero page.
3448	* @{ */
3449	/** The host physical address of the zero page. */
3450	RTHCPHYS HCPhysZeroPg;
3451	/** The ring-3 mapping of the zero page. */
3452	RTR3PTR pvZeroPgR3;
3453	/** The ring-0 mapping of the zero page. */
3454	RTR0PTR pvZeroPgR0;
3455	/** The GC mapping of the zero page. */
3456	RTRCPTR pvZeroPgRC;
3457	RTRCPTR RCPtrAlignment3;
3458	/** @}*/
3459
3460	/** @name The Invalid MMIO page.
3461	* This page is filled with 0xfeedface.
3462	* @{ */
3463	/** The host physical address of the invalid MMIO page. */
3464	RTHCPHYS HCPhysMmioPg;
3465	/** The host pysical address of the invalid MMIO page plus all invalid
3466	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3467	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3468	RTHCPHYS HCPhysInvMmioPg;
3469	/** The ring-3 mapping of the invalid MMIO page. */
3470	RTR3PTR pvMmioPgR3;
3471	#if HC_ARCH_BITS == 32
3472	RTR3PTR R3PtrAlignment4;
3473	#endif
3474	/** @} */
3475
3476
3477	/** The number of handy pages. */
3478	uint32_t cHandyPages;
3479
3480	/** The number of large handy pages. */
3481	uint32_t cLargeHandyPages;
3482
3483	/**
3484	* Array of handy pages.
3485	*
3486	* This array is used in a two way communication between pgmPhysAllocPage
3487	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3488	* an intermediary.
3489	*
3490	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3491	* (The current size of 32 pages, means 128 KB of handy memory.)
3492	*/
3493	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3494
3495	/**
3496	* Array of large handy pages. (currently size 1)
3497	*
3498	* This array is used in a two way communication between pgmPhysAllocLargePage
3499	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3500	* an intermediary.
3501	*/
3502	GMMPAGEDESC aLargeHandyPage[1];
3503
3504	/**
3505	* Live save data.
3506	*/
3507	struct
3508	{
3509	/** Per type statistics. */
3510	struct
3511	{
3512	/** The number of ready pages. */
3513	uint32_t cReadyPages;
3514	/** The number of dirty pages. */
3515	uint32_t cDirtyPages;
3516	/** The number of ready zero pages. */
3517	uint32_t cZeroPages;
3518	/** The number of write monitored pages. */
3519	uint32_t cMonitoredPages;
3520	} Rom,
3521	Mmio2,
3522	Ram;
3523	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3524	uint32_t cIgnoredPages;
3525	/** Indicates that a live save operation is active. */
3526	bool fActive;
3527	/** Padding. */
3528	bool afReserved[2];
3529	/** The next history index. */
3530	uint8_t iDirtyPagesHistory;
3531	/** History of the total amount of dirty pages. */
3532	uint32_t acDirtyPagesHistory[64];
3533	/** Short term dirty page average. */
3534	uint32_t cDirtyPagesShort;
3535	/** Long term dirty page average. */
3536	uint32_t cDirtyPagesLong;
3537	/** The number of saved pages. This is used to get some kind of estimate of the
3538	* link speed so we can decide when we're done. It is reset after the first
3539	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3540	* zero pages. */
3541	uint64_t cSavedPages;
3542	/** The nanosecond timestamp when cSavedPages was 0. */
3543	uint64_t uSaveStartNS;
3544	/** Pages per second (for statistics). */
3545	uint32_t cPagesPerSecond;
3546	uint32_t cAlignment;
3547	} LiveSave;
3548
3549	/** @name Error injection.
3550	* @{ */
3551	/** Inject handy page allocation errors pretending we're completely out of
3552	* memory. */
3553	bool volatile fErrInjHandyPages;
3554	/** Padding. */
3555	bool afReserved[3];
3556	/** @} */
3557
3558	/** @name Release Statistics
3559	* @{ */
3560	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3561	uint32_t cPrivatePages; /*< The number of private pages. /
3562	uint32_t cSharedPages; /*< The number of shared pages. /
3563	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3564	uint32_t cZeroPages; /*< The number of zero backed pages. /
3565	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3566	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3567	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3568	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3569	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3570	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3571	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3572	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3573	uint32_t cLargePages; /*< The number of large pages. /
3574	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3575	/* uint32_t aAlignment4[1]; */
3576
3577	/** The number of times we were forced to change the hypervisor region location. */
3578	STAMCOUNTER cRelocations;
3579
3580	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3581	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3582	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3583
3584	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3585	/** @} */
3586
3587	#ifdef VBOX_WITH_STATISTICS
3588	/** @name Statistics on the heap.
3589	* @{ */
3590	R3PTRTYPE(PGMSTATS *) pStatsR3;
3591	R0PTRTYPE(PGMSTATS *) pStatsR0;
3592	RCPTRTYPE(PGMSTATS *) pStatsRC;
3593	RTRCPTR RCPtrAlignment;
3594	/** @} */
3595	#endif
3596	} PGM;
3597	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3598	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3599	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3600	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3601	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3602	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3603	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3604	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3605	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3606	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3607	#endif /* !IN_TSTVMSTRUCTGC */
3608	/** Pointer to the PGM instance data. */
3609	typedef PGM *PPGM;
3610
3611
3612
3613	typedef struct PGMCPUSTATS
3614	{
3615	/* Common */
3616	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3617	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3618
3619	/* R0 only: */
3620	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3621	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3622
3623	/* RZ only: */
3624	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3625	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3626	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3627	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3628	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3629	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3630	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3631	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3632	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3633	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3634	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3635	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3636	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3637	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3638	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3639	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3640	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3641	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3642	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3643	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3644	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3645	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3646	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3647	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3648	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3649	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3650	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3651	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3652	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3653	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3654	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3655	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3656	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3657	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3658	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3659	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3660	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3661	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3662	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3663	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3664	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3665	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3666	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3667	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3668	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3669	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3670	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3671	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3672	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3673	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3674	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3675	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3676	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3677	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3678	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3679	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3680	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3681	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3682	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3683	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3684	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3685	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3686	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3687	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3688	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3689	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3690	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3691	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3692	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3693	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3694	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3695	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3696	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3697	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3698	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3699	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3700	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3701	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3702
3703	/* HC - R3 and (maybe) R0: */
3704
3705	/* RZ & R3: */
3706	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3707	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3708	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3709	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3710	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3711	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3712	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3713	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3714	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3715	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3716	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3717	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3718	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3719	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3720	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3721	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3722	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3723	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3724	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3725	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3726	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3727	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3728	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3729	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3730	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3731	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3732	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3733	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3734	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3735	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3736	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3737	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3738	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3739	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3740	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3741	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3742	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3743	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3744	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3745	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3746	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3747	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3748	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3749	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3750	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3751	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3752	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3753
3754	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3755	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3756	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3757	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3758	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3759	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3760	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3761	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3762	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3763	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3764	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3765	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3766	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3767	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3768	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3769	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3770	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3771	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3772	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3773	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3774	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3775	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3776	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3777	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3778	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3779	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3780	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3781	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3782	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3783	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3784	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3785	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3786	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3787	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3788	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3789	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3790	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3791	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3792	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3793	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3794	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3795	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3796	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3797	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3798	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3799	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3800	/** @} */
3801	} PGMCPUSTATS;
3802
3803
3804	/**
3805	* Converts a PGMCPU pointer into a VM pointer.
3806	* @returns Pointer to the VM structure the PGM is part of.
3807	* @param pPGM Pointer to PGMCPU instance data.
3808	*/
3809	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3810
3811	/**
3812	* Converts a PGMCPU pointer into a PGM pointer.
3813	* @returns Pointer to the VM structure the PGM is part of.
3814	* @param pPGM Pointer to PGMCPU instance data.
3815	*/
3816	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3817
3818	/**
3819	* PGMCPU Data (part of VMCPU).
3820	*/
3821	typedef struct PGMCPU
3822	{
3823	/** Offset to the VM structure. */
3824	int32_t offVM;
3825	/** Offset to the VMCPU structure. */
3826	int32_t offVCpu;
3827	/** Offset of the PGM structure relative to VMCPU. */
3828	int32_t offPGM;
3829	uint32_t uPadding0; /*< structure size alignment. /
3830
3831	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3832	/** Automatically tracked physical memory mapping set.
3833	* Ring-0 and strict raw-mode builds. */
3834	PGMMAPSET AutoSet;
3835	#endif
3836
3837	/** A20 gate mask.
3838	* Our current approach to A20 emulation is to let REM do it and don't bother
3839	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3840	* But whould need arrise, we'll subject physical addresses to this mask. */
3841	RTGCPHYS GCPhysA20Mask;
3842	/** A20 gate state - boolean! */
3843	bool fA20Enabled;
3844	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3845	bool fNoExecuteEnabled;
3846	/** Unused bits. */
3847	bool afUnused[2];
3848
3849	/** What needs syncing (PGM_SYNC_*).
3850	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3851	* PGMFlushTLB, and PGMR3Load. */
3852	uint32_t fSyncFlags;
3853
3854	/** The shadow paging mode. */
3855	PGMMODE enmShadowMode;
3856	/** The guest paging mode. */
3857	PGMMODE enmGuestMode;
3858
3859	/** The current physical address representing in the guest CR3 register. */
3860	RTGCPHYS GCPhysCR3;
3861
3862	/** @name 32-bit Guest Paging.
3863	* @{ */
3864	/** The guest's page directory, R3 pointer. */
3865	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3866	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3867	/** The guest's page directory, R0 pointer. */
3868	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3869	#endif
3870	/** The guest's page directory, static RC mapping. */
3871	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3872	/** Mask containing the MBZ bits of a big page PDE. */
3873	uint32_t fGst32BitMbzBigPdeMask;
3874	/** Set if the page size extension (PSE) is enabled. */
3875	bool fGst32BitPageSizeExtension;
3876	/** Alignment padding. */
3877	bool afAlignment2[3];
3878	/** @} */
3879
3880	/** @name PAE Guest Paging.
3881	* @{ */
3882	/** The guest's page directory pointer table, static RC mapping. */
3883	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3884	/** The guest's page directory pointer table, R3 pointer. */
3885	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3886	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3887	/** The guest's page directory pointer table, R0 pointer. */
3888	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3889	#endif
3890
3891	/** The guest's page directories, R3 pointers.
3892	* These are individual pointers and don't have to be adjacent.
3893	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3894	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3895	/** The guest's page directories, R0 pointers.
3896	* Same restrictions as apGstPaePDsR3. */
3897	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3898	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3899	#endif
3900	/** The guest's page directories, static GC mapping.
3901	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3902	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3903	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3904	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3905	* @todo Remove this and use aGstPaePdpeRegs instead? */
3906	RTGCPHYS aGCPhysGstPaePDs[4];
3907	/** The values of the 4 PDPE CPU registers (PAE). */
3908	X86PDPE aGstPaePdpeRegs[4];
3909	/** The physical addresses of the monitored guest page directories (PAE). */
3910	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3911	/** Mask containing the MBZ PTE bits. */
3912	uint64_t fGstPaeMbzPteMask;
3913	/** Mask containing the MBZ PDE bits. */
3914	uint64_t fGstPaeMbzPdeMask;
3915	/** Mask containing the MBZ big page PDE bits. */
3916	uint64_t fGstPaeMbzBigPdeMask;
3917	/** Mask containing the MBZ PDPE bits. */
3918	uint64_t fGstPaeMbzPdpeMask;
3919	/** @} */
3920
3921	/** @name AMD64 Guest Paging.
3922	* @{ */
3923	/** The guest's page directory pointer table, R3 pointer. */
3924	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3925	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3926	/** The guest's page directory pointer table, R0 pointer. */
3927	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3928	#else
3929	RTR0PTR alignment6b; /*< alignment equalizer. /
3930	#endif
3931	/** Mask containing the MBZ PTE bits. */
3932	uint64_t fGstAmd64MbzPteMask;
3933	/** Mask containing the MBZ PDE bits. */
3934	uint64_t fGstAmd64MbzPdeMask;
3935	/** Mask containing the MBZ big page PDE bits. */
3936	uint64_t fGstAmd64MbzBigPdeMask;
3937	/** Mask containing the MBZ PDPE bits. */
3938	uint64_t fGstAmd64MbzPdpeMask;
3939	/** Mask containing the MBZ big page PDPE bits. */
3940	uint64_t fGstAmd64MbzBigPdpeMask;
3941	/** Mask containing the MBZ PML4E bits. */
3942	uint64_t fGstAmd64MbzPml4eMask;
3943	/** Mask containing the PDPE bits that we shadow. */
3944	uint64_t fGstAmd64ShadowedPdpeMask;
3945	/** Mask containing the PML4E bits that we shadow. */
3946	uint64_t fGstAmd64ShadowedPml4eMask;
3947	/** @} */
3948
3949	/** @name PAE and AMD64 Guest Paging.
3950	* @{ */
3951	/** Mask containing the PTE bits that we shadow. */
3952	uint64_t fGst64ShadowedPteMask;
3953	/** Mask containing the PDE bits that we shadow. */
3954	uint64_t fGst64ShadowedPdeMask;
3955	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3956	uint64_t fGst64ShadowedBigPdeMask;
3957	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3958	uint64_t fGst64ShadowedBigPde4PteMask;
3959	/** @} */
3960
3961	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3962	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3963	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3964	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3965	/** Pointer to the page of the current active CR3 - RC Ptr. */
3966	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3967	# if HC_ARCH_BITS == 64
3968	RTRCPTR alignment6; /*< structure size alignment. /
3969	# endif
3970	/** @} */
3971
3972	/** @name Function pointers for Shadow paging.
3973	* @{
3974	*/
3975	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3976	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3977	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3978	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3979
3980	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3981	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3982
3983	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3984	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3985
3986	/** @} */
3987
3988	/** @name Function pointers for Guest paging.
3989	* @{
3990	*/
3991	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3992	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3993	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3994	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3995	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3996	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3997	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3998	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3999	#if HC_ARCH_BITS == 64
4000	RTRCPTR alignment3; /*< structure size alignment. /
4001	#endif
4002
4003	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4004	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4005	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4006	/** @} */
4007
4008	/** @name Function pointers for Both Shadow and Guest paging.
4009	* @{
4010	*/
4011	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4012	/* no pfnR3BthTrap0eHandler */
4013	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4014	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4015	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4016	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4017	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4018	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4019	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4020
4021	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4022	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4023	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4024	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4025	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4026	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4027	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4028	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4029
4030	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4031	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4032	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4033	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4034	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4035	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4036	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4037	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4038	#if 0
4039	RTRCPTR alignment2; /*< structure size alignment. /
4040	#endif
4041	/** @} */
4042
4043	/** For saving stack space, the disassembler state is allocated here instead of
4044	* on the stack. */
4045	DISCPUSTATE DisState;
4046
4047	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
4048	uint64_t cNetwareWp0Hacks;
4049
4050	/** Count the number of pgm pool access handler calls. */
4051	uint64_t cPoolAccessHandler;
4052
4053	/** @name Release Statistics
4054	* @{ */
4055	/** The number of times the guest has switched mode since last reset or statistics reset. */
4056	STAMCOUNTER cGuestModeChanges;
4057	/** The number of times the guest has switched mode since last reset or statistics reset. */
4058	STAMCOUNTER cA20Changes;
4059	/** @} */
4060
4061	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4062	/** @name Statistics
4063	* @{ */
4064	/** RC: Pointer to the statistics. */
4065	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4066	/** RC: Which statistic this \#PF should be attributed to. */
4067	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4068	/** R0: Pointer to the statistics. */
4069	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4070	/** R0: Which statistic this \#PF should be attributed to. */
4071	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4072	/** R3: Pointer to the statistics. */
4073	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4074	/** Alignment padding. */
4075	RTR3PTR pPaddingR3;
4076	/** @} */
4077	#endif /* VBOX_WITH_STATISTICS */
4078	} PGMCPU;
4079	/** Pointer to the per-cpu PGM data. */
4080	typedef PGMCPU *PPGMCPU;
4081
4082
4083	/** @name PGM::fSyncFlags Flags
4084	* @{
4085	*/
4086	/** Updates the virtual access handler state bit in PGMPAGE. */
4087	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4088	/** Always sync CR3. */
4089	#define PGM_SYNC_ALWAYS RT_BIT(1)
4090	/** Check monitoring on next CR3 (re)load and invalidate page.
4091	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4092	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4093	/** Check guest mapping in SyncCR3. */
4094	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4095	/** Clear the page pool (a light weight flush). */
4096	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4097	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4098	/** @} */
4099
4100
4101	RT_C_DECLS_BEGIN
4102
4103	#if defined(VBOX_STRICT) && defined(IN_RING3)
4104	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4105	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4106	#else
4107	int pgmLock(PVM pVM);
4108	#endif
4109	void pgmUnlock(PVM pVM);
4110	/**
4111	* Asserts that the caller owns the PDM lock.
4112	* This is the internal variant of PGMIsLockOwner.
4113	* @param a_pVM Pointer to the VM.
4114	*/
4115	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4116	/**
4117	* Asserts that the caller owns the PDM lock.
4118	* This is the internal variant of PGMIsLockOwner.
4119	* @param a_pVM Pointer to the VM.
4120	* @param a_pVCpu The current CPU handle.
4121	*/
4122	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4123
4124	#ifndef PGM_WITHOUT_MAPPINGS
4125	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4126	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4127	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4128	int pgmMapResolveConflicts(PVM pVM);
4129	#endif /* !PGM_WITHOUT_MAPPINGS */
4130	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4131	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4132
4133	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4134	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4135	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4136	#ifdef VBOX_WITH_RAW_MODE
4137	PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4138	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4139	# if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4140	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4141	# else
4142	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4143	# endif
4144	#endif /* VBOX_WITH_RAW_MODE */
4145	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4146	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4147
4148	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4149	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4150	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4151	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4152	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4153	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4154	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4155	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4156	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4157	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4158	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4159	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4160	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4161	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4162	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4163	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4164	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4165	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4166	#ifndef IN_RING3
4167	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4168	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4169	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4170	#endif
4171	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4172	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4173	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4174	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4175	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4176	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4177	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4178	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4179	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4180
4181	#ifdef IN_RING3
4182	void pgmR3PhysRelinkRamRanges(PVM pVM);
4183	int pgmR3PhysRamPreAllocate(PVM pVM);
4184	int pgmR3PhysRamReset(PVM pVM);
4185	int pgmR3PhysRomReset(PVM pVM);
4186	int pgmR3PhysRamZeroAll(PVM pVM);
4187	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4188	int pgmR3PhysRamTerm(PVM pVM);
4189	void pgmR3PhysRomTerm(PVM pVM);
4190	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4191
4192	int pgmR3PoolInit(PVM pVM);
4193	void pgmR3PoolRelocate(PVM pVM);
4194	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4195	void pgmR3PoolReset(PVM pVM);
4196	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4197	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4198	void pgmR3PoolWriteProtectPages(PVM pVM);
4199
4200	#endif /* IN_RING3 */
4201	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4202	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4203	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4204	# ifdef LOG_ENABLED
4205	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4206	# else
4207	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4208	# endif
4209	#endif
4210	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4211	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4212	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4213	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4214	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4215	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4216	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4217	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4218	int pgmPoolSyncCR3(PVMCPU pVCpu);
4219	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4220	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4221	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4222	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4223	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4224	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4225	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4226	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4227	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4228	#ifndef IN_RING3
4229	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
4230	#endif
4231
4232	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4233	void pgmPoolResetDirtyPages(PVM pVM);
4234	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4235
4236	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4237	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4238	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4239
4240	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4241	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4242	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4243	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4244
4245	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4246	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4247	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4248
4249	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4250	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4251	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4252	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4253	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4254
4255	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4256	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4257	FNDBGCCMD pgmR3CmdShowSharedModules;
4258	# endif
4259
4260	RT_C_DECLS_END
4261
4262	/** @} */
4263
4264	#endif
4265

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 56384

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