VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 63226

Last change on this file since 63226 was 63226, checked in by vboxsync, 8 years ago

Introducing PGM_ALL_CB2_PROTO.
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1/* $Id: PGMInternal.h 63226 2016-08-09 16:41:16Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hm.h>
36#include <VBox/vmm/hm_vmx.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/avl.h>
40#include <iprt/critsect.h>
41#include <iprt/list-off32.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings in the shadow tables.
59 *
60 * Note! In ring-3 the macro is also used to exclude the managment of the
61 * intermediate context page tables. On 32-bit systems we use the intermediate
62 * context to support 64-bit guest execution. Thus, we cannot fully make it
63 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
64 *
65 * In raw-mode context there are by design always guest mappings (the code is
66 * executed from one), while in ring-0 there are none at all. Neither context
67 * manages the page tables for intermediate switcher context, that's all done in
68 * ring-3.
69 */
70#if defined(IN_RING0) \
71 || ( !defined(VBOX_WITH_RAW_MODE) \
72 && ( HC_ARCH_BITS != 32 \
73 || !defined(VBOX_WITH_64_BITS_GUESTS) \
74 ) \
75 )
76# define PGM_WITHOUT_MAPPINGS
77#endif
78
79/**
80 * Check and skip global PDEs for non-global flushes
81 */
82#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
83
84/**
85 * Optimization for PAE page tables that are modified often
86 */
87//#if 0 /* disabled again while debugging */
88#ifndef IN_RC
89# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
90#endif
91//#endif
92
93/**
94 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
95 */
96#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
97# define PGM_WITH_LARGE_PAGES
98#endif
99
100/**
101 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
102 * VMX_EXIT_EPT_MISCONFIG.
103 */
104#if 1 /* testing */
105# define PGM_WITH_MMIO_OPTIMIZATIONS
106#endif
107
108/**
109 * Sync N pages instead of a whole page table
110 */
111#define PGM_SYNC_N_PAGES
112
113/**
114 * Number of pages to sync during a page fault
115 *
116 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118 *
119 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120 * world switch overhead, so let's sync more.
121 */
122# ifdef IN_RING0
123/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125 * but ~5% fewer faults.
126 */
127# define PGM_SYNC_NR_PAGES 32
128#else
129# define PGM_SYNC_NR_PAGES 8
130#endif
131
132/**
133 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134 */
135#define PGM_MAX_PHYSCACHE_ENTRIES 64
136#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139/** @def PGMPOOL_CFG_MAX_GROW
140 * The maximum number of pages to add to the pool in one go.
141 */
142#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
143
144/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
146 */
147#ifdef VBOX_STRICT
148# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149#endif
150
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153#ifdef DOXYGEN_RUNNING
154# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155#endif
156
157/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158 * Enables real write monitoring of pages, i.e. mapping them read-only and
159 * only making them writable when getting a write access \#PF. */
160#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** Mapping (hypervisor allocated pagetable). */
173#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174/** @} */
175
176/** @name Page directory flags.
177 * These are placed in the three bits available for system programs in
178 * the page directory entries.
179 * @{ */
180/** Mapping (hypervisor allocated pagetable). */
181#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
182/** Made read-only to facilitate dirty bit tracking. */
183#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
184/** @} */
185
186/** @name Page flags.
187 * These are placed in the three bits available for system programs in
188 * the page entries.
189 * @{ */
190/** Made read-only to facilitate dirty bit tracking. */
191#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
192
193#ifndef PGM_PTFLAGS_CSAM_VALIDATED
194/** Scanned and approved by CSAM (tm).
195 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
196 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
197#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
198#endif
199
200/** @} */
201
202/** @name Defines used to indicate the shadow and guest paging in the templates.
203 * @{ */
204#define PGM_TYPE_REAL 1
205#define PGM_TYPE_PROT 2
206#define PGM_TYPE_32BIT 3
207#define PGM_TYPE_PAE 4
208#define PGM_TYPE_AMD64 5
209#define PGM_TYPE_NESTED 6
210#define PGM_TYPE_EPT 7
211#define PGM_TYPE_MAX PGM_TYPE_EPT
212/** @} */
213
214/** Macro for checking if the guest is using paging.
215 * @param uGstType PGM_TYPE_*
216 * @param uShwType PGM_TYPE_*
217 * @remark ASSUMES certain order of the PGM_TYPE_* values.
218 */
219#define PGM_WITH_PAGING(uGstType, uShwType) \
220 ( (uGstType) >= PGM_TYPE_32BIT \
221 && (uShwType) != PGM_TYPE_NESTED \
222 && (uShwType) != PGM_TYPE_EPT)
223
224/** Macro for checking if the guest supports the NX bit.
225 * @param uGstType PGM_TYPE_*
226 * @param uShwType PGM_TYPE_*
227 * @remark ASSUMES certain order of the PGM_TYPE_* values.
228 */
229#define PGM_WITH_NX(uGstType, uShwType) \
230 ( (uGstType) >= PGM_TYPE_PAE \
231 && (uShwType) != PGM_TYPE_NESTED \
232 && (uShwType) != PGM_TYPE_EPT)
233
234
235/** @def PGM_HCPHYS_2_PTR
236 * Maps a HC physical page pool address to a virtual address.
237 *
238 * @returns VBox status code.
239 * @param pVM The cross context VM structure.
240 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
241 * @param HCPhys The HC physical address to map to a virtual one.
242 * @param ppv Where to store the virtual address. No need to cast
243 * this.
244 *
245 * @remark Use with care as we don't have so much dynamic mapping space in
246 * ring-0 on 32-bit darwin and in RC.
247 * @remark There is no need to assert on the result.
248 */
249#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
250# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
251 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
252#else
253# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
255#endif
256
257/** @def PGM_GCPHYS_2_PTR_V2
258 * Maps a GC physical page address to a virtual address.
259 *
260 * @returns VBox status code.
261 * @param pVM The cross context VM structure.
262 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
263 * @param GCPhys The GC physical address to map to a virtual one.
264 * @param ppv Where to store the virtual address. No need to cast this.
265 *
266 * @remark Use with care as we don't have so much dynamic mapping space in
267 * ring-0 on 32-bit darwin and in RC.
268 * @remark There is no need to assert on the result.
269 */
270#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
271# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
272 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
273#else
274# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
276#endif
277
278/** @def PGM_GCPHYS_2_PTR
279 * Maps a GC physical page address to a virtual address.
280 *
281 * @returns VBox status code.
282 * @param pVM The cross context VM structure.
283 * @param GCPhys The GC physical address to map to a virtual one.
284 * @param ppv Where to store the virtual address. No need to cast this.
285 *
286 * @remark Use with care as we don't have so much dynamic mapping space in
287 * ring-0 on 32-bit darwin and in RC.
288 * @remark There is no need to assert on the result.
289 */
290#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
291
292/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
293 * Maps a GC physical page address to a virtual address.
294 *
295 * @returns VBox status code.
296 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
297 * @param GCPhys The GC physical address to map to a virtual one.
298 * @param ppv Where to store the virtual address. No need to cast this.
299 *
300 * @remark Use with care as we don't have so much dynamic mapping space in
301 * ring-0 on 32-bit darwin and in RC.
302 * @remark There is no need to assert on the result.
303 */
304#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
305
306/** @def PGM_GCPHYS_2_PTR_EX
307 * Maps a unaligned GC physical page address to a virtual address.
308 *
309 * @returns VBox status code.
310 * @param pVM The cross context VM structure.
311 * @param GCPhys The GC physical address to map to a virtual one.
312 * @param ppv Where to store the virtual address. No need to cast this.
313 *
314 * @remark Use with care as we don't have so much dynamic mapping space in
315 * ring-0 on 32-bit darwin and in RC.
316 * @remark There is no need to assert on the result.
317 */
318#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
319# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
320 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
321#else
322# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
324#endif
325
326/** @def PGM_DYNMAP_UNUSED_HINT
327 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
328 * is no longer used.
329 *
330 * For best effect only apply this to the page that was mapped most recently.
331 *
332 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
333 * @param pvPage The pool page.
334 */
335#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
336# ifdef LOG_ENABLED
337# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
338# else
339# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
340# endif
341#else
342# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
343#endif
344
345/** @def PGM_DYNMAP_UNUSED_HINT_VM
346 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
347 * is no longer used.
348 *
349 * For best effect only apply this to the page that was mapped most recently.
350 *
351 * @param pVM The cross context VM structure.
352 * @param pvPage The pool page.
353 */
354#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
355
356
357/** @def PGM_INVL_PG
358 * Invalidates a page.
359 *
360 * @param pVCpu The cross context virtual CPU structure.
361 * @param GCVirt The virtual address of the page to invalidate.
362 */
363#ifdef IN_RC
364# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
365#elif defined(IN_RING0)
366# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
367#else
368# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
369#endif
370
371/** @def PGM_INVL_PG_ALL_VCPU
372 * Invalidates a page on all VCPUs
373 *
374 * @param pVM The cross context VM structure.
375 * @param GCVirt The virtual address of the page to invalidate.
376 */
377#ifdef IN_RC
378# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
379#elif defined(IN_RING0)
380# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
381#else
382# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
383#endif
384
385/** @def PGM_INVL_BIG_PG
386 * Invalidates a 4MB page directory entry.
387 *
388 * @param pVCpu The cross context virtual CPU structure.
389 * @param GCVirt The virtual address within the page directory to invalidate.
390 */
391#ifdef IN_RC
392# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
393#elif defined(IN_RING0)
394# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
395#else
396# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
397#endif
398
399/** @def PGM_INVL_VCPU_TLBS()
400 * Invalidates the TLBs of the specified VCPU
401 *
402 * @param pVCpu The cross context virtual CPU structure.
403 */
404#ifdef IN_RC
405# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
406#elif defined(IN_RING0)
407# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
408#else
409# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
410#endif
411
412/** @def PGM_INVL_ALL_VCPU_TLBS()
413 * Invalidates the TLBs of all VCPUs
414 *
415 * @param pVM The cross context VM structure.
416 */
417#ifdef IN_RC
418# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
419#elif defined(IN_RING0)
420# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
421#else
422# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
423#endif
424
425
426/** @name Safer Shadow PAE PT/PTE
427 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
428 * present.
429 *
430 * @{
431 */
432#if 1
433/**
434 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
435 * invalid entries for present.
436 * @sa X86PTEPAE.
437 */
438typedef union PGMSHWPTEPAE
439{
440 /** Unsigned integer view */
441 X86PGPAEUINT uCareful;
442 /* Not other views. */
443} PGMSHWPTEPAE;
444
445# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
446# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
447# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
448# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
449# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
450# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
451# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
452# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
453# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
454# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
455# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
456# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
457# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
458# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
459# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
460# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
461
462/**
463 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
464 * invalid entries for present.
465 * @sa X86PTPAE.
466 */
467typedef struct PGMSHWPTPAE
468{
469 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
470} PGMSHWPTPAE;
471
472#else
473typedef X86PTEPAE PGMSHWPTEPAE;
474typedef X86PTPAE PGMSHWPTPAE;
475# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
476# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
477# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
478# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
479# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
480# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
481# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
482# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
483# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
484# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
485# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
486# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
487# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
488# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
489# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
490# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
491
492#endif
493
494/** Pointer to a shadow PAE PTE. */
495typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
496/** Pointer to a const shadow PAE PTE. */
497typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
498
499/** Pointer to a shadow PAE page table. */
500typedef PGMSHWPTPAE *PPGMSHWPTPAE;
501/** Pointer to a const shadow PAE page table. */
502typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
503/** @} */
504
505
506/** Size of the GCPtrConflict array in PGMMAPPING.
507 * @remarks Must be a power of two. */
508#define PGMMAPPING_CONFLICT_MAX 8
509
510/**
511 * Structure for tracking GC Mappings.
512 *
513 * This structure is used by linked list in both GC and HC.
514 */
515typedef struct PGMMAPPING
516{
517 /** Pointer to next entry. */
518 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
519 /** Pointer to next entry. */
520 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
521 /** Pointer to next entry. */
522 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
523 /** Indicate whether this entry is finalized. */
524 bool fFinalized;
525 /** Start Virtual address. */
526 RTGCPTR GCPtr;
527 /** Last Virtual address (inclusive). */
528 RTGCPTR GCPtrLast;
529 /** Range size (bytes). */
530 RTGCPTR cb;
531 /** Pointer to relocation callback function. */
532 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
533 /** User argument to the callback. */
534 R3PTRTYPE(void *) pvUser;
535 /** Mapping description / name. For easing debugging. */
536 R3PTRTYPE(const char *) pszDesc;
537 /** Last 8 addresses that caused conflicts. */
538 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
539 /** Number of conflicts for this hypervisor mapping. */
540 uint32_t cConflicts;
541 /** Number of page tables. */
542 uint32_t cPTs;
543
544 /** Array of page table mapping data. Each entry
545 * describes one page table. The array can be longer
546 * than the declared length.
547 */
548 struct
549 {
550 /** The HC physical address of the page table. */
551 RTHCPHYS HCPhysPT;
552 /** The HC physical address of the first PAE page table. */
553 RTHCPHYS HCPhysPaePT0;
554 /** The HC physical address of the second PAE page table. */
555 RTHCPHYS HCPhysPaePT1;
556 /** The HC virtual address of the 32-bit page table. */
557 R3PTRTYPE(PX86PT) pPTR3;
558 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
559 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
560 /** The RC virtual address of the 32-bit page table. */
561 RCPTRTYPE(PX86PT) pPTRC;
562 /** The RC virtual address of the two PAE page table. */
563 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
564 /** The R0 virtual address of the 32-bit page table. */
565 R0PTRTYPE(PX86PT) pPTR0;
566 /** The R0 virtual address of the two PAE page table. */
567 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
568 } aPTs[1];
569} PGMMAPPING;
570/** Pointer to structure for tracking GC Mappings. */
571typedef struct PGMMAPPING *PPGMMAPPING;
572
573
574/**
575 * Physical page access handler type registration.
576 */
577typedef struct PGMPHYSHANDLERTYPEINT
578{
579 /** Number of references. */
580 uint32_t volatile cRefs;
581 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
582 uint32_t u32Magic;
583 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
584 RTLISTOFF32NODE ListNode;
585 /** The kind of accesses we're handling. */
586 PGMPHYSHANDLERKIND enmKind;
587 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
588 uint32_t uState;
589 /** Pointer to RC callback function. */
590 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
591 /** Pointer to RC callback function for \#PFs. */
592 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
593 /** Pointer to R3 callback function. */
594 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
595 /** Pointer to R0 callback function. */
596 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
597 /** Pointer to R0 callback function for \#PFs. */
598 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
599 /** Description / Name. For easing debugging. */
600 R3PTRTYPE(const char *) pszDesc;
601} PGMPHYSHANDLERTYPEINT;
602/** Pointer to a physical access handler type registration. */
603typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
604/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
605#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
606/** Magic value for the physical handler callbacks. */
607#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
608
609/**
610 * Converts a handle to a pointer.
611 * @returns PPGMPHYSHANDLERTYPEINT
612 * @param a_pVM The cross context VM structure.
613 * @param a_hType Physical access handler type handle.
614 */
615#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
616
617
618/**
619 * Physical page access handler structure.
620 *
621 * This is used to keep track of physical address ranges
622 * which are being monitored in some kind of way.
623 */
624typedef struct PGMPHYSHANDLER
625{
626 AVLROGCPHYSNODECORE Core;
627 /** Number of pages to update. */
628 uint32_t cPages;
629 /** Set if we have pages that have been aliased. */
630 uint32_t cAliasedPages;
631 /** Set if we have pages that have temporarily been disabled. */
632 uint32_t cTmpOffPages;
633 /** Registered handler type handle (heap offset). */
634 PGMPHYSHANDLERTYPE hType;
635 /** User argument for RC handlers. */
636 RCPTRTYPE(void *) pvUserRC;
637#if HC_ARCH_BITS == 64
638 RTRCPTR Padding0; /**< Explicit alignment padding. */
639#endif
640 /** User argument for R3 handlers. */
641 R3PTRTYPE(void *) pvUserR3;
642 /** User argument for R0 handlers. */
643 R0PTRTYPE(void *) pvUserR0;
644 /** Description / Name. For easing debugging. */
645 R3PTRTYPE(const char *) pszDesc;
646#ifdef VBOX_WITH_STATISTICS
647 /** Profiling of this handler. */
648 STAMPROFILE Stat;
649#endif
650} PGMPHYSHANDLER;
651/** Pointer to a physical page access handler structure. */
652typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
653
654/**
655 * Gets the type record for a physical handler (no reference added).
656 * @returns PPGMPHYSHANDLERTYPEINT
657 * @param a_pVM The cross context VM structure.
658 * @param a_pPhysHandler Pointer to the physical handler structure
659 * (PGMPHYSHANDLER).
660 */
661#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
662
663
664#ifdef VBOX_WITH_RAW_MODE
665
666/**
667 * Cache node for the physical addresses covered by a virtual handler.
668 */
669typedef struct PGMPHYS2VIRTHANDLER
670{
671 /** Core node for the tree based on physical ranges. */
672 AVLROGCPHYSNODECORE Core;
673 /** Offset from this struct to the PGMVIRTHANDLER structure. */
674 int32_t offVirtHandler;
675 /** Offset of the next alias relative to this one.
676 * Bit 0 is used for indicating whether we're in the tree.
677 * Bit 1 is used for indicating that we're the head node.
678 */
679 int32_t offNextAlias;
680} PGMPHYS2VIRTHANDLER;
681/** Pointer to a phys to virtual handler structure. */
682typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
683
684/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
685 * node is in the tree. */
686# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
687/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
688 * node is in the head of an alias chain.
689 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
690# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
691/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
692# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
693
694
695/**
696 * Virtual page access handler type registration.
697 */
698typedef struct PGMVIRTANDLERTYPEINT
699{
700 /** Number of references. */
701 uint32_t volatile cRefs;
702 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
703 uint32_t u32Magic;
704 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
705 RTLISTOFF32NODE ListNode;
706 /** The kind of accesses we're handling. */
707 PGMVIRTHANDLERKIND enmKind;
708 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
709 uint32_t uState;
710 /** Whether the pvUserRC argument should be automatically relocated or not. */
711 bool fRelocUserRC;
712 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
713 /** Pointer to RC callback function. */
714 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
715 /** Pointer to RC callback function for \#PFs. */
716 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
717 /** Pointer to the R3 callback function for invalidation. */
718 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
719 /** Pointer to R3 callback function. */
720 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
721 /** Description / Name. For easing debugging. */
722 R3PTRTYPE(const char *) pszDesc;
723} PGMVIRTHANDLERTYPEINT;
724/** Pointer to a virtual access handler type registration. */
725typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
726/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
727# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
728/** Magic value for the virtual handler callbacks. */
729# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
730
731/**
732 * Converts a handle to a pointer.
733 * @returns PPGMVIRTHANDLERTYPEINT
734 * @param a_pVM The cross context VM structure.
735 * @param a_hType Vitual access handler type handle.
736 */
737# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
738
739
740/**
741 * Virtual page access handler structure.
742 *
743 * This is used to keep track of virtual address ranges
744 * which are being monitored in some kind of way.
745 */
746typedef struct PGMVIRTHANDLER
747{
748 /** Core node for the tree based on virtual ranges. */
749 AVLROGCPTRNODECORE Core;
750 /** Size of the range (in bytes). */
751 uint32_t cb;
752 /** Number of cache pages. */
753 uint32_t cPages;
754 /** Registered handler type handle (heap offset). */
755 PGMVIRTHANDLERTYPE hType;
756 /** User argument for RC handlers. */
757 RCPTRTYPE(void *) pvUserRC;
758 /** User argument for R3 handlers. */
759 R3PTRTYPE(void *) pvUserR3;
760 /** Description / Name. For easing debugging. */
761 R3PTRTYPE(const char *) pszDesc;
762# ifdef VBOX_WITH_STATISTICS
763 /** Profiling of this handler. */
764 STAMPROFILE Stat;
765# endif
766 /** Array of cached physical addresses for the monitored ranged. */
767 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
768} PGMVIRTHANDLER;
769/** Pointer to a virtual page access handler structure. */
770typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
771
772/**
773 * Gets the type record for a virtual handler (no reference added).
774 * @returns PPGMVIRTHANDLERTYPEINT
775 * @param a_pVM The cross context VM structure.
776 * @param a_pVirtHandler Pointer to the virtual handler structure
777 * (PGMVIRTHANDLER).
778 */
779# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
780
781#endif /* VBOX_WITH_RAW_MODE */
782
783
784/** @name Page type predicates.
785 * @{ */
786#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
787#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
788#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
789#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
790#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
791/** @} */
792
793
794/**
795 * A Physical Guest Page tracking structure.
796 *
797 * The format of this structure is complicated because we have to fit a lot
798 * of information into as few bits as possible. The format is also subject
799 * to change (there is one coming up soon). Which means that for we'll be
800 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
801 * accesses to the structure.
802 */
803typedef union PGMPAGE
804{
805 /** Structured view. */
806 struct
807 {
808 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
809 uint64_t u2HandlerPhysStateY : 2;
810 /** 3:2 - Paging structure needed to map the page
811 * (PGM_PAGE_PDE_TYPE_*). */
812 uint64_t u2PDETypeY : 2;
813 /** 4 - Indicator of dirty page for fault tolerance tracking. */
814 uint64_t fFTDirtyY : 1;
815 /** 5 - Flag indicating that a write monitored page was written to
816 * when set. */
817 uint64_t fWrittenToY : 1;
818 /** 7:6 - Unused. */
819 uint64_t u2Unused0 : 2;
820 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
821 uint64_t u2HandlerVirtStateY : 2;
822 /** 11:10 - Unused. */
823 uint64_t u2Unused1 : 2;
824 /** 12:48 - The host physical frame number (shift left to get the
825 * address). */
826 uint64_t HCPhysFN : 36;
827 /** 50:48 - The page state. */
828 uint64_t uStateY : 3;
829 /** 51:53 - The page type (PGMPAGETYPE). */
830 uint64_t uTypeY : 3;
831 /** 63:54 - PTE index for usage tracking (page pool). */
832 uint64_t u10PteIdx : 10;
833
834 /** The GMM page ID.
835 * @remarks In the current implementation, MMIO2 and pages aliased to
836 * MMIO2 pages will be exploiting this field to calculate the
837 * ring-3 mapping address corresponding to the page.
838 * Later we may consider including MMIO2 management into GMM. */
839 uint32_t idPage;
840 /** Usage tracking (page pool). */
841 uint16_t u16TrackingY;
842 /** The number of read locks on this page. */
843 uint8_t cReadLocksY;
844 /** The number of write locks on this page. */
845 uint8_t cWriteLocksY;
846 } s;
847
848 /** 64-bit integer view. */
849 uint64_t au64[2];
850 /** 16-bit view. */
851 uint32_t au32[4];
852 /** 16-bit view. */
853 uint16_t au16[8];
854 /** 8-bit view. */
855 uint8_t au8[16];
856} PGMPAGE;
857AssertCompileSize(PGMPAGE, 16);
858/** Pointer to a physical guest page. */
859typedef PGMPAGE *PPGMPAGE;
860/** Pointer to a const physical guest page. */
861typedef const PGMPAGE *PCPGMPAGE;
862/** Pointer to a physical guest page pointer. */
863typedef PPGMPAGE *PPPGMPAGE;
864
865
866/**
867 * Clears the page structure.
868 * @param a_pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_CLEAR(a_pPage) \
871 do { \
872 (a_pPage)->au64[0] = 0; \
873 (a_pPage)->au64[1] = 0; \
874 } while (0)
875
876/**
877 * Initializes the page structure.
878 * @param a_pPage Pointer to the physical guest page tracking structure.
879 * @param a_HCPhys The host physical address of the page.
880 * @param a_idPage The (GMM) page ID of the page.
881 * @param a_uType The page type (PGMPAGETYPE).
882 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
883 */
884#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
885 do { \
886 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
887 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
888 (a_pPage)->au64[0] = SetHCPhysTmp; \
889 (a_pPage)->au64[1] = 0; \
890 (a_pPage)->s.idPage = (a_idPage); \
891 (a_pPage)->s.uStateY = (a_uState); \
892 (a_pPage)->s.uTypeY = (a_uType); \
893 } while (0)
894
895/**
896 * Initializes the page structure of a ZERO page.
897 * @param a_pPage Pointer to the physical guest page tracking structure.
898 * @param a_pVM The VM handle (for getting the zero page address).
899 * @param a_uType The page type (PGMPAGETYPE).
900 */
901#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
902 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
903
904
905/** @name The Page state, PGMPAGE::uStateY.
906 * @{ */
907/** The zero page.
908 * This is a per-VM page that's never ever mapped writable. */
909#define PGM_PAGE_STATE_ZERO 0
910/** A allocated page.
911 * This is a per-VM page allocated from the page pool (or wherever
912 * we get MMIO2 pages from if the type is MMIO2).
913 */
914#define PGM_PAGE_STATE_ALLOCATED 1
915/** A allocated page that's being monitored for writes.
916 * The shadow page table mappings are read-only. When a write occurs, the
917 * fWrittenTo member is set, the page remapped as read-write and the state
918 * moved back to allocated. */
919#define PGM_PAGE_STATE_WRITE_MONITORED 2
920/** The page is shared, aka. copy-on-write.
921 * This is a page that's shared with other VMs. */
922#define PGM_PAGE_STATE_SHARED 3
923/** The page is ballooned, so no longer available for this VM. */
924#define PGM_PAGE_STATE_BALLOONED 4
925/** @} */
926
927
928/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
929#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
930# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
931#else
932# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
933#endif
934
935/**
936 * Gets the page state.
937 * @returns page state (PGM_PAGE_STATE_*).
938 * @param a_pPage Pointer to the physical guest page tracking structure.
939 *
940 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
941 * builds.
942 */
943#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
944#if defined(__GNUC__) && defined(VBOX_STRICT)
945# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
946#else
947# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
948#endif
949
950/**
951 * Sets the page state.
952 * @param a_pVM The VM handle, only used for lock ownership assertions.
953 * @param a_pPage Pointer to the physical guest page tracking structure.
954 * @param a_uState The new page state.
955 */
956#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
957 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
958
959
960/**
961 * Gets the host physical address of the guest page.
962 * @returns host physical address (RTHCPHYS).
963 * @param a_pPage Pointer to the physical guest page tracking structure.
964 *
965 * @remarks In strict builds on gcc platforms, this macro will make some ugly
966 * assumption about a valid pVM variable/parameter being in the
967 * current context. It will use this pVM variable to assert that the
968 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
969 * pVM is not around.
970 */
971#if 0
972# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
973# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
974#else
975# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
976# if defined(__GNUC__) && defined(VBOX_STRICT)
977# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
978# else
979# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
980# endif
981#endif
982
983/**
984 * Sets the host physical address of the guest page.
985 *
986 * @param a_pVM The VM handle, only used for lock ownership assertions.
987 * @param a_pPage Pointer to the physical guest page tracking structure.
988 * @param a_HCPhys The new host physical address.
989 */
990#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
991 do { \
992 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
993 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
994 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
995 PGM_PAGE_ASSERT_LOCK(a_pVM); \
996 } while (0)
997
998/**
999 * Get the Page ID.
1000 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1001 * @param a_pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1004
1005/**
1006 * Sets the Page ID.
1007 * @param a_pVM The VM handle, only used for lock ownership assertions.
1008 * @param a_pPage Pointer to the physical guest page tracking structure.
1009 * @param a_idPage The new page ID.
1010 */
1011#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1012 do { \
1013 (a_pPage)->s.idPage = (a_idPage); \
1014 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1015 } while (0)
1016
1017/**
1018 * Get the Chunk ID.
1019 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1020 * @param a_pPage Pointer to the physical guest page tracking structure.
1021 */
1022#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1023
1024/**
1025 * Get the index of the page within the allocation chunk.
1026 * @returns The page index.
1027 * @param a_pPage Pointer to the physical guest page tracking structure.
1028 */
1029#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1030
1031/**
1032 * Gets the page type.
1033 * @returns The page type.
1034 * @param a_pPage Pointer to the physical guest page tracking structure.
1035 *
1036 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1037 * builds.
1038 */
1039#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1040#if defined(__GNUC__) && defined(VBOX_STRICT)
1041# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1042#else
1043# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1044#endif
1045
1046/**
1047 * Sets the page type.
1048 *
1049 * @param a_pVM The VM handle, only used for lock ownership assertions.
1050 * @param a_pPage Pointer to the physical guest page tracking structure.
1051 * @param a_enmType The new page type (PGMPAGETYPE).
1052 */
1053#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1054 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1055
1056/**
1057 * Gets the page table index
1058 * @returns The page table index.
1059 * @param a_pPage Pointer to the physical guest page tracking structure.
1060 */
1061#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1062
1063/**
1064 * Sets the page table index.
1065 * @param a_pVM The VM handle, only used for lock ownership assertions.
1066 * @param a_pPage Pointer to the physical guest page tracking structure.
1067 * @param a_iPte New page table index.
1068 */
1069#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1070 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1071
1072/**
1073 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1074 * @returns true/false.
1075 * @param a_pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1078
1079/**
1080 * Checks if the page is marked for MMIO, including both aliases.
1081 * @returns true/false.
1082 * @param a_pPage Pointer to the physical guest page tracking structure.
1083 */
1084#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1085 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1086 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1087 )
1088
1089/**
1090 * Checks if the page is marked for MMIO, including special aliases.
1091 * @returns true/false.
1092 * @param a_pPage Pointer to the physical guest page tracking structure.
1093 */
1094#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1095 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1096
1097/**
1098 * Checks if the page is a special aliased MMIO page.
1099 * @returns true/false.
1100 * @param a_pPage Pointer to the physical guest page tracking structure.
1101 */
1102#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1103
1104/**
1105 * Checks if the page is backed by the ZERO page.
1106 * @returns true/false.
1107 * @param a_pPage Pointer to the physical guest page tracking structure.
1108 */
1109#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1110
1111/**
1112 * Checks if the page is backed by a SHARED page.
1113 * @returns true/false.
1114 * @param a_pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1117
1118/**
1119 * Checks if the page is ballooned.
1120 * @returns true/false.
1121 * @param a_pPage Pointer to the physical guest page tracking structure.
1122 */
1123#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1124
1125/**
1126 * Checks if the page is allocated.
1127 * @returns true/false.
1128 * @param a_pPage Pointer to the physical guest page tracking structure.
1129 */
1130#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1131
1132/**
1133 * Marks the page as written to (for GMM change monitoring).
1134 * @param a_pVM The VM handle, only used for lock ownership assertions.
1135 * @param a_pPage Pointer to the physical guest page tracking structure.
1136 */
1137#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1138 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1139
1140/**
1141 * Clears the written-to indicator.
1142 * @param a_pVM The VM handle, only used for lock ownership assertions.
1143 * @param a_pPage Pointer to the physical guest page tracking structure.
1144 */
1145#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1146 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1147
1148/**
1149 * Checks if the page was marked as written-to.
1150 * @returns true/false.
1151 * @param a_pPage Pointer to the physical guest page tracking structure.
1152 */
1153#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1154
1155/**
1156 * Marks the page as dirty for FTM
1157 * @param a_pPage Pointer to the physical guest page tracking structure.
1158 */
1159#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1160
1161/**
1162 * Clears the FTM dirty indicator
1163 * @param a_pPage Pointer to the physical guest page tracking structure.
1164 */
1165#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1166
1167/**
1168 * Checks if the page was marked as dirty for FTM
1169 * @returns true/false.
1170 * @param a_pPage Pointer to the physical guest page tracking structure.
1171 */
1172#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1173
1174
1175/** @name PT usage values (PGMPAGE::u2PDEType).
1176 *
1177 * @{ */
1178/** Either as a PT or PDE. */
1179#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1180/** Must use a page table to map the range. */
1181#define PGM_PAGE_PDE_TYPE_PT 1
1182/** Can use a page directory entry to map the continuous range. */
1183#define PGM_PAGE_PDE_TYPE_PDE 2
1184/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1185#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1186/** @} */
1187
1188/**
1189 * Set the PDE type of the page
1190 * @param a_pVM The VM handle, only used for lock ownership assertions.
1191 * @param a_pPage Pointer to the physical guest page tracking structure.
1192 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1193 */
1194#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1195 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1196
1197/**
1198 * Checks if the page was marked being part of a large page
1199 * @returns true/false.
1200 * @param a_pPage Pointer to the physical guest page tracking structure.
1201 */
1202#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1203
1204/** Enabled optimized access handler tests.
1205 * These optimizations makes ASSUMPTIONS about the state values and the s1
1206 * layout. When enabled, the compiler should normally generate more compact
1207 * code.
1208 */
1209#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1210
1211/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1212 *
1213 * @remarks The values are assigned in order of priority, so we can calculate
1214 * the correct state for a page with different handlers installed.
1215 * @{ */
1216/** No handler installed. */
1217#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1218/** Monitoring is temporarily disabled. */
1219#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1220/** Write access is monitored. */
1221#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1222/** All access is monitored. */
1223#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1224/** @} */
1225
1226/**
1227 * Gets the physical access handler state of a page.
1228 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1229 * @param a_pPage Pointer to the physical guest page tracking structure.
1230 */
1231#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1232
1233/**
1234 * Sets the physical access handler state of a page.
1235 * @param a_pPage Pointer to the physical guest page tracking structure.
1236 * @param a_uState The new state value.
1237 */
1238#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1239 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1240
1241/**
1242 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1243 * @returns true/false
1244 * @param a_pPage Pointer to the physical guest page tracking structure.
1245 */
1246#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1247 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1248
1249/**
1250 * Checks if the page has any active physical access handlers.
1251 * @returns true/false
1252 * @param a_pPage Pointer to the physical guest page tracking structure.
1253 */
1254#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1255 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1256
1257
1258/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1259 *
1260 * @remarks The values are assigned in order of priority, so we can calculate
1261 * the correct state for a page with different handlers installed.
1262 * @{ */
1263/** No handler installed. */
1264#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1265/* 1 is reserved so the lineup is identical with the physical ones. */
1266/** Write access is monitored. */
1267#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1268/** All access is monitored. */
1269#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1270/** @} */
1271
1272/**
1273 * Gets the virtual access handler state of a page.
1274 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1275 * @param a_pPage Pointer to the physical guest page tracking structure.
1276 */
1277#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1278
1279/**
1280 * Sets the virtual access handler state of a page.
1281 * @param a_pPage Pointer to the physical guest page tracking structure.
1282 * @param a_uState The new state value.
1283 */
1284#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1285 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1286
1287/**
1288 * Checks if the page has any virtual access handlers.
1289 * @returns true/false
1290 * @param a_pPage Pointer to the physical guest page tracking structure.
1291 */
1292#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1293 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1294
1295/**
1296 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1297 * virtual handlers.
1298 * @returns true/false
1299 * @param a_pPage Pointer to the physical guest page tracking structure.
1300 */
1301#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1302 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1303
1304
1305/**
1306 * Checks if the page has any access handlers, including temporarily disabled ones.
1307 * @returns true/false
1308 * @param a_pPage Pointer to the physical guest page tracking structure.
1309 */
1310#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1311# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1312 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1313#else
1314# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1315 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1316 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1317#endif
1318
1319/**
1320 * Checks if the page has any active access handlers.
1321 * @returns true/false
1322 * @param a_pPage Pointer to the physical guest page tracking structure.
1323 */
1324#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1325# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1326 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1327#else
1328# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1329 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1330 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1331#endif
1332
1333/**
1334 * Checks if the page has any active access handlers catching all accesses.
1335 * @returns true/false
1336 * @param a_pPage Pointer to the physical guest page tracking structure.
1337 */
1338#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1339# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1340 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1341 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1342#else
1343# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1344 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1345 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1346#endif
1347
1348
1349/** @def PGM_PAGE_GET_TRACKING
1350 * Gets the packed shadow page pool tracking data associated with a guest page.
1351 * @returns uint16_t containing the data.
1352 * @param a_pPage Pointer to the physical guest page tracking structure.
1353 */
1354#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1355#if defined(__GNUC__) && defined(VBOX_STRICT)
1356# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1357#else
1358# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1359#endif
1360
1361/** @def PGM_PAGE_SET_TRACKING
1362 * Sets the packed shadow page pool tracking data associated with a guest page.
1363 * @param a_pVM The VM handle, only used for lock ownership assertions.
1364 * @param a_pPage Pointer to the physical guest page tracking structure.
1365 * @param a_u16TrackingData The tracking data to store.
1366 */
1367#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1368 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1369
1370/** @def PGM_PAGE_GET_TD_CREFS
1371 * Gets the @a cRefs tracking data member.
1372 * @returns cRefs.
1373 * @param a_pPage Pointer to the physical guest page tracking structure.
1374 */
1375#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1376 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1377#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1378 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1379
1380/** @def PGM_PAGE_GET_TD_IDX
1381 * Gets the @a idx tracking data member.
1382 * @returns idx.
1383 * @param a_pPage Pointer to the physical guest page tracking structure.
1384 */
1385#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1386 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1387#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1388 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1389
1390
1391/** Max number of locks on a page. */
1392#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1393
1394/** Get the read lock count.
1395 * @returns count.
1396 * @param a_pPage Pointer to the physical guest page tracking structure.
1397 */
1398#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1399
1400/** Get the write lock count.
1401 * @returns count.
1402 * @param a_pPage Pointer to the physical guest page tracking structure.
1403 */
1404#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1405
1406/** Decrement the read lock counter.
1407 * @param a_pPage Pointer to the physical guest page tracking structure.
1408 */
1409#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1410
1411/** Decrement the write lock counter.
1412 * @param a_pPage Pointer to the physical guest page tracking structure.
1413 */
1414#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1415
1416/** Increment the read lock counter.
1417 * @param a_pPage Pointer to the physical guest page tracking structure.
1418 */
1419#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1420
1421/** Increment the write lock counter.
1422 * @param a_pPage Pointer to the physical guest page tracking structure.
1423 */
1424#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1425
1426
1427#if 0
1428/** Enables sanity checking of write monitoring using CRC-32. */
1429# define PGMLIVESAVERAMPAGE_WITH_CRC32
1430#endif
1431
1432/**
1433 * Per page live save tracking data.
1434 */
1435typedef struct PGMLIVESAVERAMPAGE
1436{
1437 /** Number of times it has been dirtied. */
1438 uint32_t cDirtied : 24;
1439 /** Whether it is currently dirty. */
1440 uint32_t fDirty : 1;
1441 /** Ignore the page.
1442 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1443 * deal with these after pausing the VM and DevPCI have said it bit about
1444 * remappings. */
1445 uint32_t fIgnore : 1;
1446 /** Was a ZERO page last time around. */
1447 uint32_t fZero : 1;
1448 /** Was a SHARED page last time around. */
1449 uint32_t fShared : 1;
1450 /** Whether the page is/was write monitored in a previous pass. */
1451 uint32_t fWriteMonitored : 1;
1452 /** Whether the page is/was write monitored earlier in this pass. */
1453 uint32_t fWriteMonitoredJustNow : 1;
1454 /** Bits reserved for future use. */
1455 uint32_t u2Reserved : 2;
1456#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1457 /** CRC-32 for the page. This is for internal consistency checks. */
1458 uint32_t u32Crc;
1459#endif
1460} PGMLIVESAVERAMPAGE;
1461#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1462AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1463#else
1464AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1465#endif
1466/** Pointer to the per page live save tracking data. */
1467typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1468
1469/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1470#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1471
1472
1473/**
1474 * RAM range for GC Phys to HC Phys conversion.
1475 *
1476 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1477 * conversions too, but we'll let MM handle that for now.
1478 *
1479 * This structure is used by linked lists in both GC and HC.
1480 */
1481typedef struct PGMRAMRANGE
1482{
1483 /** Start of the range. Page aligned. */
1484 RTGCPHYS GCPhys;
1485 /** Size of the range. (Page aligned of course). */
1486 RTGCPHYS cb;
1487 /** Pointer to the next RAM range - for R3. */
1488 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1489 /** Pointer to the next RAM range - for R0. */
1490 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1491 /** Pointer to the next RAM range - for RC. */
1492 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1493 /** PGM_RAM_RANGE_FLAGS_* flags. */
1494 uint32_t fFlags;
1495 /** Last address in the range (inclusive). Page aligned (-1). */
1496 RTGCPHYS GCPhysLast;
1497 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1498 R3PTRTYPE(void *) pvR3;
1499 /** Live save per page tracking data. */
1500 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1501 /** The range description. */
1502 R3PTRTYPE(const char *) pszDesc;
1503 /** Pointer to self - R0 pointer. */
1504 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1505 /** Pointer to self - RC pointer. */
1506 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1507
1508 /** Alignment padding. */
1509 RTRCPTR Alignment0;
1510 /** Pointer to the left search three node - ring-3 context. */
1511 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1512 /** Pointer to the right search three node - ring-3 context. */
1513 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1514 /** Pointer to the left search three node - ring-0 context. */
1515 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1516 /** Pointer to the right search three node - ring-0 context. */
1517 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1518 /** Pointer to the left search three node - raw-mode context. */
1519 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1520 /** Pointer to the right search three node - raw-mode context. */
1521 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1522
1523 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1524#if HC_ARCH_BITS == 32
1525 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1526#endif
1527 /** Array of physical guest page tracking structures. */
1528 PGMPAGE aPages[1];
1529} PGMRAMRANGE;
1530/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1531typedef PGMRAMRANGE *PPGMRAMRANGE;
1532
1533/** @name PGMRAMRANGE::fFlags
1534 * @{ */
1535/** The RAM range is floating around as an independent guest mapping. */
1536#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1537/** Ad hoc RAM range for an ROM mapping. */
1538#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1539/** Ad hoc RAM range for an MMIO mapping. */
1540#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1541/** Ad hoc RAM range for an MMIO2 mapping. */
1542#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1543/** @} */
1544
1545/** Tests if a RAM range is an ad hoc one or not.
1546 * @returns true/false.
1547 * @param pRam The RAM range.
1548 */
1549#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1550 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1551
1552/** The number of entries in the RAM range TLBs (there is one for each
1553 * context). Must be a power of two. */
1554#define PGM_RAMRANGE_TLB_ENTRIES 8
1555
1556/**
1557 * Calculates the RAM range TLB index for the physical address.
1558 *
1559 * @returns RAM range TLB index.
1560 * @param a_GCPhys The guest physical address.
1561 */
1562#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1563
1564
1565
1566/**
1567 * Per page tracking structure for ROM image.
1568 *
1569 * A ROM image may have a shadow page, in which case we may have two pages
1570 * backing it. This structure contains the PGMPAGE for both while
1571 * PGMRAMRANGE have a copy of the active one. It is important that these
1572 * aren't out of sync in any regard other than page pool tracking data.
1573 */
1574typedef struct PGMROMPAGE
1575{
1576 /** The page structure for the virgin ROM page. */
1577 PGMPAGE Virgin;
1578 /** The page structure for the shadow RAM page. */
1579 PGMPAGE Shadow;
1580 /** The current protection setting. */
1581 PGMROMPROT enmProt;
1582 /** Live save status information. Makes use of unused alignment space. */
1583 struct
1584 {
1585 /** The previous protection value. */
1586 uint8_t u8Prot;
1587 /** Written to flag set by the handler. */
1588 bool fWrittenTo;
1589 /** Whether the shadow page is dirty or not. */
1590 bool fDirty;
1591 /** Whether it was dirtied in the recently. */
1592 bool fDirtiedRecently;
1593 } LiveSave;
1594} PGMROMPAGE;
1595AssertCompileSizeAlignment(PGMROMPAGE, 8);
1596/** Pointer to a ROM page tracking structure. */
1597typedef PGMROMPAGE *PPGMROMPAGE;
1598
1599
1600/**
1601 * A registered ROM image.
1602 *
1603 * This is needed to keep track of ROM image since they generally intrude
1604 * into a PGMRAMRANGE. It also keeps track of additional info like the
1605 * two page sets (read-only virgin and read-write shadow), the current
1606 * state of each page.
1607 *
1608 * Because access handlers cannot easily be executed in a different
1609 * context, the ROM ranges needs to be accessible and in all contexts.
1610 */
1611typedef struct PGMROMRANGE
1612{
1613 /** Pointer to the next range - R3. */
1614 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1615 /** Pointer to the next range - R0. */
1616 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1617 /** Pointer to the next range - RC. */
1618 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1619 /** Pointer alignment */
1620 RTRCPTR RCPtrAlignment;
1621 /** Address of the range. */
1622 RTGCPHYS GCPhys;
1623 /** Address of the last byte in the range. */
1624 RTGCPHYS GCPhysLast;
1625 /** Size of the range. */
1626 RTGCPHYS cb;
1627 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1628 uint32_t fFlags;
1629 /** The saved state range ID. */
1630 uint8_t idSavedState;
1631 /** Alignment padding. */
1632 uint8_t au8Alignment[3];
1633 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1634 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1635 /** The size bits pvOriginal points to. */
1636 uint32_t cbOriginal;
1637 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1638 * This is used for strictness checks. */
1639 R3PTRTYPE(const void *) pvOriginal;
1640 /** The ROM description. */
1641 R3PTRTYPE(const char *) pszDesc;
1642 /** The per page tracking structures. */
1643 PGMROMPAGE aPages[1];
1644} PGMROMRANGE;
1645/** Pointer to a ROM range. */
1646typedef PGMROMRANGE *PPGMROMRANGE;
1647
1648
1649/**
1650 * Live save per page data for an MMIO2 page.
1651 *
1652 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1653 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1654 * CRC-32 for detecting changes as well as special handling of zero pages. This
1655 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1656 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1657 * because of speed (2.5x and 6x slower).)
1658 *
1659 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1660 * save but normally is disabled. Since we can write monitor guest
1661 * accesses on our own, we only need this for host accesses. Shouldn't be
1662 * too difficult for DevVGA, VMMDev might be doable, the planned
1663 * networking fun will be fun since it involves ring-0.
1664 */
1665typedef struct PGMLIVESAVEMMIO2PAGE
1666{
1667 /** Set if the page is considered dirty. */
1668 bool fDirty;
1669 /** The number of scans this page has remained unchanged for.
1670 * Only updated for dirty pages. */
1671 uint8_t cUnchangedScans;
1672 /** Whether this page was zero at the last scan. */
1673 bool fZero;
1674 /** Alignment padding. */
1675 bool fReserved;
1676 /** CRC-32 for the first half of the page.
1677 * This is used together with u32CrcH2 to quickly detect changes in the page
1678 * during the non-final passes. */
1679 uint32_t u32CrcH1;
1680 /** CRC-32 for the second half of the page. */
1681 uint32_t u32CrcH2;
1682 /** SHA-1 for the saved page.
1683 * This is used in the final pass to skip pages without changes. */
1684 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1685} PGMLIVESAVEMMIO2PAGE;
1686/** Pointer to a live save status data for an MMIO2 page. */
1687typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1688
1689/**
1690 * A registered MMIO2 (= Device RAM) range.
1691 *
1692 * There are a few reason why we need to keep track of these
1693 * registrations. One of them is the deregistration & cleanup stuff,
1694 * while another is that the PGMRAMRANGE associated with such a region may
1695 * have to be removed from the ram range list.
1696 *
1697 * Overlapping with a RAM range has to be 100% or none at all. The pages
1698 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1699 * will be raised if a partial overlap or an overlap of ROM pages is
1700 * encountered. On an overlap we will free all the existing RAM pages and
1701 * put in the ram range pages instead.
1702 */
1703typedef struct PGMMMIO2RANGE
1704{
1705 /** The owner of the range. (a device) */
1706 PPDMDEVINSR3 pDevInsR3;
1707 /** Pointer to the ring-3 mapping of the allocation. */
1708 RTR3PTR pvR3;
1709 /** Pointer to the next range - R3. */
1710 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1711 /** Whether it's mapped or not. */
1712 bool fMapped;
1713 /** Whether it's overlapping or not. */
1714 bool fOverlapping;
1715 /** The PCI region number.
1716 * @remarks This ASSUMES that nobody will ever really need to have multiple
1717 * PCI devices with matching MMIO region numbers on a single device. */
1718 uint8_t iRegion;
1719 /** The saved state range ID. */
1720 uint8_t idSavedState;
1721 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1722 uint8_t idMmio2;
1723 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1724 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1725 /** Live save per page tracking data. */
1726 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1727 /** The associated RAM range. */
1728 PGMRAMRANGE RamRange;
1729} PGMMMIO2RANGE;
1730/** Pointer to a MMIO2 range. */
1731typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1732
1733/** @name Intenal MMIO2 constants.
1734 * @{ */
1735/** The maximum number of MMIO2 ranges. */
1736#define PGM_MMIO2_MAX_RANGES 8
1737/** The maximum number of pages in a MMIO2 range. */
1738#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1739/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1740#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1741/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1742#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1743/** Gets the MMIO2 page index from an MMIO2 page ID. */
1744#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1745/** @} */
1746
1747
1748
1749/**
1750 * PGMPhysRead/Write cache entry
1751 */
1752typedef struct PGMPHYSCACHEENTRY
1753{
1754 /** R3 pointer to physical page. */
1755 R3PTRTYPE(uint8_t *) pbR3;
1756 /** GC Physical address for cache entry */
1757 RTGCPHYS GCPhys;
1758#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1759 RTGCPHYS u32Padding0; /**< alignment padding. */
1760#endif
1761} PGMPHYSCACHEENTRY;
1762
1763/**
1764 * PGMPhysRead/Write cache to reduce REM memory access overhead
1765 */
1766typedef struct PGMPHYSCACHE
1767{
1768 /** Bitmap of valid cache entries */
1769 uint64_t aEntries;
1770 /** Cache entries */
1771 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1772} PGMPHYSCACHE;
1773
1774
1775/** Pointer to an allocation chunk ring-3 mapping. */
1776typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1777/** Pointer to an allocation chunk ring-3 mapping pointer. */
1778typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1779
1780/**
1781 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1782 *
1783 * The primary tree (Core) uses the chunk id as key.
1784 */
1785typedef struct PGMCHUNKR3MAP
1786{
1787 /** The key is the chunk id. */
1788 AVLU32NODECORE Core;
1789 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1790 * selection. */
1791 uint32_t iLastUsed;
1792 /** The current reference count. */
1793 uint32_t volatile cRefs;
1794 /** The current permanent reference count. */
1795 uint32_t volatile cPermRefs;
1796 /** The mapping address. */
1797 void *pv;
1798} PGMCHUNKR3MAP;
1799
1800/**
1801 * Allocation chunk ring-3 mapping TLB entry.
1802 */
1803typedef struct PGMCHUNKR3MAPTLBE
1804{
1805 /** The chunk id. */
1806 uint32_t volatile idChunk;
1807#if HC_ARCH_BITS == 64
1808 uint32_t u32Padding; /**< alignment padding. */
1809#endif
1810 /** The chunk map. */
1811#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1812 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1813#else
1814 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1815#endif
1816} PGMCHUNKR3MAPTLBE;
1817/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1818typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1819
1820/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1821 * @remark Must be a power of two value. */
1822#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1823
1824/**
1825 * Allocation chunk ring-3 mapping TLB.
1826 *
1827 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1828 * At first glance this might look kinda odd since AVL trees are
1829 * supposed to give the most optimal lookup times of all trees
1830 * due to their balancing. However, take a tree with 1023 nodes
1831 * in it, that's 10 levels, meaning that most searches has to go
1832 * down 9 levels before they find what they want. This isn't fast
1833 * compared to a TLB hit. There is the factor of cache misses,
1834 * and of course the problem with trees and branch prediction.
1835 * This is why we use TLBs in front of most of the trees.
1836 *
1837 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1838 * difficult when we switch to the new inlined AVL trees (from kStuff).
1839 */
1840typedef struct PGMCHUNKR3MAPTLB
1841{
1842 /** The TLB entries. */
1843 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1844} PGMCHUNKR3MAPTLB;
1845
1846/**
1847 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1848 * @returns Chunk TLB index.
1849 * @param idChunk The Chunk ID.
1850 */
1851#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1852
1853
1854/**
1855 * Ring-3 guest page mapping TLB entry.
1856 * @remarks used in ring-0 as well at the moment.
1857 */
1858typedef struct PGMPAGER3MAPTLBE
1859{
1860 /** Address of the page. */
1861 RTGCPHYS volatile GCPhys;
1862 /** The guest page. */
1863#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1864 R3PTRTYPE(PPGMPAGE) volatile pPage;
1865#else
1866 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1867#endif
1868 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1869#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1870 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1871#else
1872 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1873#endif
1874 /** The address */
1875#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1876 R3PTRTYPE(void *) volatile pv;
1877#else
1878 R3R0PTRTYPE(void *) volatile pv;
1879#endif
1880#if HC_ARCH_BITS == 32
1881 uint32_t u32Padding; /**< alignment padding. */
1882#endif
1883} PGMPAGER3MAPTLBE;
1884/** Pointer to an entry in the HC physical TLB. */
1885typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1886
1887
1888/** The number of entries in the ring-3 guest page mapping TLB.
1889 * @remarks The value must be a power of two. */
1890#define PGM_PAGER3MAPTLB_ENTRIES 256
1891
1892/**
1893 * Ring-3 guest page mapping TLB.
1894 * @remarks used in ring-0 as well at the moment.
1895 */
1896typedef struct PGMPAGER3MAPTLB
1897{
1898 /** The TLB entries. */
1899 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1900} PGMPAGER3MAPTLB;
1901/** Pointer to the ring-3 guest page mapping TLB. */
1902typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1903
1904/**
1905 * Calculates the index of the TLB entry for the specified guest page.
1906 * @returns Physical TLB index.
1907 * @param GCPhys The guest physical address.
1908 */
1909#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1910
1911
1912/**
1913 * Raw-mode context dynamic mapping cache entry.
1914 *
1915 * Because of raw-mode context being reloctable and all relocations are applied
1916 * in ring-3, this has to be defined here and be RC specific.
1917 *
1918 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1919 */
1920typedef struct PGMRCDYNMAPENTRY
1921{
1922 /** The physical address of the currently mapped page.
1923 * This is duplicate for three reasons: cache locality, cache policy of the PT
1924 * mappings and sanity checks. */
1925 RTHCPHYS HCPhys;
1926 /** Pointer to the page. */
1927 RTRCPTR pvPage;
1928 /** The number of references. */
1929 int32_t volatile cRefs;
1930 /** PTE pointer union. */
1931 struct PGMRCDYNMAPENTRY_PPTE
1932 {
1933 /** PTE pointer, 32-bit legacy version. */
1934 RCPTRTYPE(PX86PTE) pLegacy;
1935 /** PTE pointer, PAE version. */
1936 RCPTRTYPE(PX86PTEPAE) pPae;
1937 } uPte;
1938} PGMRCDYNMAPENTRY;
1939/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1940typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1941
1942
1943/**
1944 * Dynamic mapping cache for the raw-mode context.
1945 *
1946 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1947 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1948 * so that we can perform relocations from PGMR3Relocate. This has the
1949 * consequence that we must have separate ring-0 and raw-mode context versions
1950 * of this struct even if they share the basic elements.
1951 *
1952 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1953 */
1954typedef struct PGMRCDYNMAP
1955{
1956 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1957 uint32_t u32Magic;
1958 /** Array for tracking and managing the pages. */
1959 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1960 /** The cache size given as a number of pages. */
1961 uint32_t cPages;
1962 /** The current load.
1963 * This does not include guard pages. */
1964 uint32_t cLoad;
1965 /** The max load ever.
1966 * This is maintained to get trigger adding of more mapping space. */
1967 uint32_t cMaxLoad;
1968 /** The number of guard pages. */
1969 uint32_t cGuardPages;
1970 /** The number of users (protected by hInitLock). */
1971 uint32_t cUsers;
1972} PGMRCDYNMAP;
1973/** Pointer to the dynamic cache for the raw-mode context. */
1974typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1975
1976
1977/**
1978 * Mapping cache usage set entry.
1979 *
1980 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1981 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1982 * cache. If it's extended to include ring-3, well, then something
1983 * will have be changed here...
1984 */
1985typedef struct PGMMAPSETENTRY
1986{
1987 /** Pointer to the page. */
1988#ifndef IN_RC
1989 RTR0PTR pvPage;
1990#else
1991 RTRCPTR pvPage;
1992# if HC_ARCH_BITS == 64
1993 uint32_t u32Alignment2;
1994# endif
1995#endif
1996 /** The mapping cache index. */
1997 uint16_t iPage;
1998 /** The number of references.
1999 * The max is UINT16_MAX - 1. */
2000 uint16_t cRefs;
2001 /** The number inlined references.
2002 * The max is UINT16_MAX - 1. */
2003 uint16_t cInlinedRefs;
2004 /** Unreferences. */
2005 uint16_t cUnrefs;
2006
2007#if HC_ARCH_BITS == 32
2008 uint32_t u32Alignment1;
2009#endif
2010 /** The physical address for this entry. */
2011 RTHCPHYS HCPhys;
2012} PGMMAPSETENTRY;
2013AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2014AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2015/** Pointer to a mapping cache usage set entry. */
2016typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2017
2018/**
2019 * Mapping cache usage set.
2020 *
2021 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2022 * done during exits / traps. The set is
2023 */
2024typedef struct PGMMAPSET
2025{
2026 /** The number of occupied entries.
2027 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2028 * dynamic mappings. */
2029 uint32_t cEntries;
2030 /** The start of the current subset.
2031 * This is UINT32_MAX if no subset is currently open. */
2032 uint32_t iSubset;
2033 /** The index of the current CPU, only valid if the set is open. */
2034 int32_t iCpu;
2035 uint32_t alignment;
2036 /** The entries. */
2037 PGMMAPSETENTRY aEntries[64];
2038 /** HCPhys -> iEntry fast lookup table.
2039 * Use PGMMAPSET_HASH for hashing.
2040 * The entries may or may not be valid, check against cEntries. */
2041 uint8_t aiHashTable[128];
2042} PGMMAPSET;
2043AssertCompileSizeAlignment(PGMMAPSET, 8);
2044/** Pointer to the mapping cache set. */
2045typedef PGMMAPSET *PPGMMAPSET;
2046
2047/** PGMMAPSET::cEntries value for a closed set. */
2048#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2049
2050/** Hash function for aiHashTable. */
2051#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2052
2053
2054/** @name Context neutral page mapper TLB.
2055 *
2056 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2057 * code is writting in a kind of context neutral way. Time will show whether
2058 * this actually makes sense or not...
2059 *
2060 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2061 * context ends up using a global mapping cache on some platforms
2062 * (darwin).
2063 *
2064 * @{ */
2065/** @typedef PPGMPAGEMAPTLB
2066 * The page mapper TLB pointer type for the current context. */
2067/** @typedef PPGMPAGEMAPTLB
2068 * The page mapper TLB entry pointer type for the current context. */
2069/** @typedef PPGMPAGEMAPTLB
2070 * The page mapper TLB entry pointer pointer type for the current context. */
2071/** @def PGM_PAGEMAPTLB_ENTRIES
2072 * The number of TLB entries in the page mapper TLB for the current context. */
2073/** @def PGM_PAGEMAPTLB_IDX
2074 * Calculate the TLB index for a guest physical address.
2075 * @returns The TLB index.
2076 * @param GCPhys The guest physical address. */
2077/** @typedef PPGMPAGEMAP
2078 * Pointer to a page mapper unit for current context. */
2079/** @typedef PPPGMPAGEMAP
2080 * Pointer to a page mapper unit pointer for current context. */
2081#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2082// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2083// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2084// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2085# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2086# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2087 typedef void * PPGMPAGEMAP;
2088 typedef void ** PPPGMPAGEMAP;
2089//#elif IN_RING0
2090// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2091// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2092// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2093//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2094//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2095// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2096// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2097#else
2098 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2099 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2100 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2101# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2102# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2103 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2104 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2105#endif
2106/** @} */
2107
2108
2109/** @name PGM Pool Indexes.
2110 * Aka. the unique shadow page identifier.
2111 * @{ */
2112/** NIL page pool IDX. */
2113#define NIL_PGMPOOL_IDX 0
2114/** The first normal index. There used to be 5 fictive pages up front, now
2115 * there is only the NIL page. */
2116#define PGMPOOL_IDX_FIRST 1
2117/** The last valid index. (inclusive, 14 bits) */
2118#define PGMPOOL_IDX_LAST 0x3fff
2119/** @} */
2120
2121/** The NIL index for the parent chain. */
2122#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2123#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2124
2125/**
2126 * Node in the chain linking a shadowed page to it's parent (user).
2127 */
2128#pragma pack(1)
2129typedef struct PGMPOOLUSER
2130{
2131 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2132 uint16_t iNext;
2133 /** The user page index. */
2134 uint16_t iUser;
2135 /** Index into the user table. */
2136 uint32_t iUserTable;
2137} PGMPOOLUSER, *PPGMPOOLUSER;
2138typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2139#pragma pack()
2140
2141
2142/** The NIL index for the phys ext chain. */
2143#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2144/** The NIL pte index for a phys ext chain slot. */
2145#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2146
2147/**
2148 * Node in the chain of physical cross reference extents.
2149 * @todo Calling this an 'extent' is not quite right, find a better name.
2150 * @todo find out the optimal size of the aidx array
2151 */
2152#pragma pack(1)
2153typedef struct PGMPOOLPHYSEXT
2154{
2155 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2156 uint16_t iNext;
2157 /** Alignment. */
2158 uint16_t u16Align;
2159 /** The user page index. */
2160 uint16_t aidx[3];
2161 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2162 uint16_t apte[3];
2163} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2164typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2165#pragma pack()
2166
2167
2168/**
2169 * The kind of page that's being shadowed.
2170 */
2171typedef enum PGMPOOLKIND
2172{
2173 /** The virtual invalid 0 entry. */
2174 PGMPOOLKIND_INVALID = 0,
2175 /** The entry is free (=unused). */
2176 PGMPOOLKIND_FREE,
2177
2178 /** Shw: 32-bit page table; Gst: no paging. */
2179 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2180 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2181 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2182 /** Shw: 32-bit page table; Gst: 4MB page. */
2183 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2184 /** Shw: PAE page table; Gst: no paging. */
2185 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2186 /** Shw: PAE page table; Gst: 32-bit page table. */
2187 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2188 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2189 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2190 /** Shw: PAE page table; Gst: PAE page table. */
2191 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2192 /** Shw: PAE page table; Gst: 2MB page. */
2193 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2194
2195 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2196 PGMPOOLKIND_32BIT_PD,
2197 /** Shw: 32-bit page directory. Gst: no paging. */
2198 PGMPOOLKIND_32BIT_PD_PHYS,
2199 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2200 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2201 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2202 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2203 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2204 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2205 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2206 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2207 /** Shw: PAE page directory; Gst: PAE page directory. */
2208 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2209 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2210 PGMPOOLKIND_PAE_PD_PHYS,
2211
2212 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2213 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2214 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2215 PGMPOOLKIND_PAE_PDPT,
2216 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2217 PGMPOOLKIND_PAE_PDPT_PHYS,
2218
2219 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2220 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2221 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2222 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2223 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2224 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2225 /** Shw: 64-bit page directory table; Gst: no paging. */
2226 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2227
2228 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2229 PGMPOOLKIND_64BIT_PML4,
2230
2231 /** Shw: EPT page directory pointer table; Gst: no paging. */
2232 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2233 /** Shw: EPT page directory table; Gst: no paging. */
2234 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2235 /** Shw: EPT page table; Gst: no paging. */
2236 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2237
2238 /** Shw: Root Nested paging table. */
2239 PGMPOOLKIND_ROOT_NESTED,
2240
2241 /** The last valid entry. */
2242 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2243} PGMPOOLKIND;
2244
2245/**
2246 * The access attributes of the page; only applies to big pages.
2247 */
2248typedef enum
2249{
2250 PGMPOOLACCESS_DONTCARE = 0,
2251 PGMPOOLACCESS_USER_RW,
2252 PGMPOOLACCESS_USER_R,
2253 PGMPOOLACCESS_USER_RW_NX,
2254 PGMPOOLACCESS_USER_R_NX,
2255 PGMPOOLACCESS_SUPERVISOR_RW,
2256 PGMPOOLACCESS_SUPERVISOR_R,
2257 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2258 PGMPOOLACCESS_SUPERVISOR_R_NX
2259} PGMPOOLACCESS;
2260
2261/**
2262 * The tracking data for a page in the pool.
2263 */
2264typedef struct PGMPOOLPAGE
2265{
2266 /** AVL node code with the (HC) physical address of this page. */
2267 AVLOHCPHYSNODECORE Core;
2268 /** Pointer to the R3 mapping of the page. */
2269#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2270 R3PTRTYPE(void *) pvPageR3;
2271#else
2272 R3R0PTRTYPE(void *) pvPageR3;
2273#endif
2274#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2275 uint32_t Alignment0;
2276#endif
2277 /** The guest physical address. */
2278 RTGCPHYS GCPhys;
2279 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2280 uint8_t enmKind;
2281 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2282 uint8_t enmAccess;
2283 /** This supplements enmKind and enmAccess */
2284 bool fA20Enabled : 1;
2285
2286 /** Used to indicate that the page is zeroed. */
2287 bool fZeroed : 1;
2288 /** Used to indicate that a PT has non-global entries. */
2289 bool fSeenNonGlobal : 1;
2290 /** Used to indicate that we're monitoring writes to the guest page. */
2291 bool fMonitored : 1;
2292 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2293 * (All pages are in the age list.) */
2294 bool fCached : 1;
2295 /** This is used by the R3 access handlers when invoked by an async thread.
2296 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2297 bool volatile fReusedFlushPending : 1;
2298 /** Used to mark the page as dirty (write monitoring is temporarily
2299 * off). */
2300 bool fDirty : 1;
2301 bool fPadding1 : 1;
2302 bool fPadding2;
2303
2304 /** The index of this page. */
2305 uint16_t idx;
2306 /** The next entry in the list this page currently resides in.
2307 * It's either in the free list or in the GCPhys hash. */
2308 uint16_t iNext;
2309 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2310 uint16_t iUserHead;
2311 /** The number of present entries. */
2312 uint16_t cPresent;
2313 /** The first entry in the table which is present. */
2314 uint16_t iFirstPresent;
2315 /** The number of modifications to the monitored page. */
2316 uint16_t cModifications;
2317 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2318 uint16_t iModifiedNext;
2319 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2320 uint16_t iModifiedPrev;
2321 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2322 uint16_t iMonitoredNext;
2323 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2324 uint16_t iMonitoredPrev;
2325 /** The next page in the age list. */
2326 uint16_t iAgeNext;
2327 /** The previous page in the age list. */
2328 uint16_t iAgePrev;
2329 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2330 uint8_t idxDirtyEntry;
2331
2332 /** @name Access handler statistics to determine whether the guest is
2333 * (re)initializing a page table.
2334 * @{ */
2335 RTGCPTR GCPtrLastAccessHandlerRip;
2336 RTGCPTR GCPtrLastAccessHandlerFault;
2337 uint64_t cLastAccessHandler;
2338 /** @} */
2339 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2340 uint32_t volatile cLocked;
2341#if GC_ARCH_BITS == 64
2342 uint32_t u32Alignment3;
2343#endif
2344# ifdef VBOX_STRICT
2345 RTGCPTR GCPtrDirtyFault;
2346# endif
2347} PGMPOOLPAGE;
2348/** Pointer to a pool page. */
2349typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2350/** Pointer to a const pool page. */
2351typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2352/** Pointer to a pool page pointer. */
2353typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2354
2355
2356/** The hash table size. */
2357# define PGMPOOL_HASH_SIZE 0x40
2358/** The hash function. */
2359# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2360
2361
2362/**
2363 * The shadow page pool instance data.
2364 *
2365 * It's all one big allocation made at init time, except for the
2366 * pages that is. The user nodes follows immediately after the
2367 * page structures.
2368 */
2369typedef struct PGMPOOL
2370{
2371 /** The VM handle - R3 Ptr. */
2372 PVMR3 pVMR3;
2373 /** The VM handle - R0 Ptr. */
2374 PVMR0 pVMR0;
2375 /** The VM handle - RC Ptr. */
2376 PVMRC pVMRC;
2377 /** The max pool size. This includes the special IDs. */
2378 uint16_t cMaxPages;
2379 /** The current pool size. */
2380 uint16_t cCurPages;
2381 /** The head of the free page list. */
2382 uint16_t iFreeHead;
2383 /* Padding. */
2384 uint16_t u16Padding;
2385 /** Head of the chain of free user nodes. */
2386 uint16_t iUserFreeHead;
2387 /** The number of user nodes we've allocated. */
2388 uint16_t cMaxUsers;
2389 /** The number of present page table entries in the entire pool. */
2390 uint32_t cPresent;
2391 /** Pointer to the array of user nodes - RC pointer. */
2392 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2393 /** Pointer to the array of user nodes - R3 pointer. */
2394 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2395 /** Pointer to the array of user nodes - R0 pointer. */
2396 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2397 /** Head of the chain of free phys ext nodes. */
2398 uint16_t iPhysExtFreeHead;
2399 /** The number of user nodes we've allocated. */
2400 uint16_t cMaxPhysExts;
2401 /** Pointer to the array of physical xref extent - RC pointer. */
2402 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2403 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2404 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2405 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2406 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2407 /** Hash table for GCPhys addresses. */
2408 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2409 /** The head of the age list. */
2410 uint16_t iAgeHead;
2411 /** The tail of the age list. */
2412 uint16_t iAgeTail;
2413 /** Set if the cache is enabled. */
2414 bool fCacheEnabled;
2415 /** Alignment padding. */
2416 bool afPadding1[3];
2417 /** Head of the list of modified pages. */
2418 uint16_t iModifiedHead;
2419 /** The current number of modified pages. */
2420 uint16_t cModifiedPages;
2421 /** Physical access handler type registration handle. */
2422 PGMPHYSHANDLERTYPE hAccessHandlerType;
2423 /** Next available slot (in aDirtyPages). */
2424 uint32_t idxFreeDirtyPage;
2425 /** Number of active dirty pages. */
2426 uint32_t cDirtyPages;
2427 /** Array of current dirty pgm pool page indices. */
2428 struct
2429 {
2430 uint16_t uIdx;
2431 uint16_t Alignment[3];
2432 uint64_t aPage[512];
2433 } aDirtyPages[16];
2434 /** The number of pages currently in use. */
2435 uint16_t cUsedPages;
2436#ifdef VBOX_WITH_STATISTICS
2437 /** The high water mark for cUsedPages. */
2438 uint16_t cUsedPagesHigh;
2439 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2440 /** Profiling pgmPoolAlloc(). */
2441 STAMPROFILEADV StatAlloc;
2442 /** Profiling pgmR3PoolClearDoIt(). */
2443 STAMPROFILE StatClearAll;
2444 /** Profiling pgmR3PoolReset(). */
2445 STAMPROFILE StatR3Reset;
2446 /** Profiling pgmPoolFlushPage(). */
2447 STAMPROFILE StatFlushPage;
2448 /** Profiling pgmPoolFree(). */
2449 STAMPROFILE StatFree;
2450 /** Counting explicit flushes by PGMPoolFlushPage(). */
2451 STAMCOUNTER StatForceFlushPage;
2452 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2453 STAMCOUNTER StatForceFlushDirtyPage;
2454 /** Counting flushes for reused pages. */
2455 STAMCOUNTER StatForceFlushReused;
2456 /** Profiling time spent zeroing pages. */
2457 STAMPROFILE StatZeroPage;
2458 /** Profiling of pgmPoolTrackDeref. */
2459 STAMPROFILE StatTrackDeref;
2460 /** Profiling pgmTrackFlushGCPhysPT. */
2461 STAMPROFILE StatTrackFlushGCPhysPT;
2462 /** Profiling pgmTrackFlushGCPhysPTs. */
2463 STAMPROFILE StatTrackFlushGCPhysPTs;
2464 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2465 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2466 /** Number of times we've been out of user records. */
2467 STAMCOUNTER StatTrackFreeUpOneUser;
2468 /** Nr of flushed entries. */
2469 STAMCOUNTER StatTrackFlushEntry;
2470 /** Nr of updated entries. */
2471 STAMCOUNTER StatTrackFlushEntryKeep;
2472 /** Profiling deref activity related tracking GC physical pages. */
2473 STAMPROFILE StatTrackDerefGCPhys;
2474 /** Number of linear searches for a HCPhys in the ram ranges. */
2475 STAMCOUNTER StatTrackLinearRamSearches;
2476 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2477 STAMCOUNTER StamTrackPhysExtAllocFailures;
2478 /** Profiling the RC/R0 access handler. */
2479 STAMPROFILE StatMonitorRZ;
2480 /** Times we've failed interpreting the instruction. */
2481 STAMCOUNTER StatMonitorRZEmulateInstr;
2482 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2483 STAMPROFILE StatMonitorRZFlushPage;
2484 /* Times we've detected a page table reinit. */
2485 STAMCOUNTER StatMonitorRZFlushReinit;
2486 /** Counting flushes for pages that are modified too often. */
2487 STAMCOUNTER StatMonitorRZFlushModOverflow;
2488 /** Times we've detected fork(). */
2489 STAMCOUNTER StatMonitorRZFork;
2490 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2491 STAMPROFILE StatMonitorRZHandled;
2492 /** Times we've failed interpreting a patch code instruction. */
2493 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2494 /** Times we've failed interpreting a patch code instruction during flushing. */
2495 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2496 /** The number of times we've seen rep prefixes we can't handle. */
2497 STAMCOUNTER StatMonitorRZRepPrefix;
2498 /** Profiling the REP STOSD cases we've handled. */
2499 STAMPROFILE StatMonitorRZRepStosd;
2500 /** Nr of handled PT faults. */
2501 STAMCOUNTER StatMonitorRZFaultPT;
2502 /** Nr of handled PD faults. */
2503 STAMCOUNTER StatMonitorRZFaultPD;
2504 /** Nr of handled PDPT faults. */
2505 STAMCOUNTER StatMonitorRZFaultPDPT;
2506 /** Nr of handled PML4 faults. */
2507 STAMCOUNTER StatMonitorRZFaultPML4;
2508
2509 /** Profiling the R3 access handler. */
2510 STAMPROFILE StatMonitorR3;
2511 /** Times we've failed interpreting the instruction. */
2512 STAMCOUNTER StatMonitorR3EmulateInstr;
2513 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2514 STAMPROFILE StatMonitorR3FlushPage;
2515 /* Times we've detected a page table reinit. */
2516 STAMCOUNTER StatMonitorR3FlushReinit;
2517 /** Counting flushes for pages that are modified too often. */
2518 STAMCOUNTER StatMonitorR3FlushModOverflow;
2519 /** Times we've detected fork(). */
2520 STAMCOUNTER StatMonitorR3Fork;
2521 /** Profiling the R3 access we've handled (except REP STOSD). */
2522 STAMPROFILE StatMonitorR3Handled;
2523 /** The number of times we've seen rep prefixes we can't handle. */
2524 STAMCOUNTER StatMonitorR3RepPrefix;
2525 /** Profiling the REP STOSD cases we've handled. */
2526 STAMPROFILE StatMonitorR3RepStosd;
2527 /** Nr of handled PT faults. */
2528 STAMCOUNTER StatMonitorR3FaultPT;
2529 /** Nr of handled PD faults. */
2530 STAMCOUNTER StatMonitorR3FaultPD;
2531 /** Nr of handled PDPT faults. */
2532 STAMCOUNTER StatMonitorR3FaultPDPT;
2533 /** Nr of handled PML4 faults. */
2534 STAMCOUNTER StatMonitorR3FaultPML4;
2535 /** The number of times we're called in an async thread an need to flush. */
2536 STAMCOUNTER StatMonitorR3Async;
2537 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2538 STAMCOUNTER StatResetDirtyPages;
2539 /** Times we've called pgmPoolAddDirtyPage. */
2540 STAMCOUNTER StatDirtyPage;
2541 /** Times we've had to flush duplicates for dirty page management. */
2542 STAMCOUNTER StatDirtyPageDupFlush;
2543 /** Times we've had to flush because of overflow. */
2544 STAMCOUNTER StatDirtyPageOverFlowFlush;
2545
2546 /** The high water mark for cModifiedPages. */
2547 uint16_t cModifiedPagesHigh;
2548 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2549
2550 /** The number of cache hits. */
2551 STAMCOUNTER StatCacheHits;
2552 /** The number of cache misses. */
2553 STAMCOUNTER StatCacheMisses;
2554 /** The number of times we've got a conflict of 'kind' in the cache. */
2555 STAMCOUNTER StatCacheKindMismatches;
2556 /** Number of times we've been out of pages. */
2557 STAMCOUNTER StatCacheFreeUpOne;
2558 /** The number of cacheable allocations. */
2559 STAMCOUNTER StatCacheCacheable;
2560 /** The number of uncacheable allocations. */
2561 STAMCOUNTER StatCacheUncacheable;
2562#else
2563 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2564#endif
2565 /** The AVL tree for looking up a page by its HC physical address. */
2566 AVLOHCPHYSTREE HCPhysTree;
2567 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2568 /** Array of pages. (cMaxPages in length)
2569 * The Id is the index into thist array.
2570 */
2571 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2572} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2573AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2574AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2575AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2576#ifdef VBOX_WITH_STATISTICS
2577AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2578#endif
2579AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2580
2581
2582/** @def PGMPOOL_PAGE_2_PTR
2583 * Maps a pool page pool into the current context.
2584 *
2585 * @returns VBox status code.
2586 * @param a_pVM Pointer to the VM.
2587 * @param a_pPage The pool page.
2588 *
2589 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2590 * small page window employeed by that function. Be careful.
2591 * @remark There is no need to assert on the result.
2592 */
2593#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2594# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2595#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2596# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2597DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2598{
2599 AssertPtr(a_pPage);
2600 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2601 return a_pPage->pvPageR3;
2602}
2603#else
2604# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2605#endif
2606
2607
2608/** @def PGMPOOL_PAGE_2_PTR_V2
2609 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2610 *
2611 * @returns VBox status code.
2612 * @param a_pVM Pointer to the VM.
2613 * @param a_pVCpu The current CPU.
2614 * @param a_pPage The pool page.
2615 *
2616 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2617 * small page window employeed by that function. Be careful.
2618 * @remark There is no need to assert on the result.
2619 */
2620#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2621# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2622#else
2623# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2624#endif
2625
2626
2627/** @name Per guest page tracking data.
2628 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2629 * is to use more bits for it and split it up later on. But for now we'll play
2630 * safe and change as little as possible.
2631 *
2632 * The 16-bit word has two parts:
2633 *
2634 * The first 14-bit forms the @a idx field. It is either the index of a page in
2635 * the shadow page pool, or and index into the extent list.
2636 *
2637 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2638 * shadow page pool references to the page. If cRefs equals
2639 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2640 * (misnomer) table and not the shadow page pool.
2641 *
2642 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2643 * the 16-bit word.
2644 *
2645 * @{ */
2646/** The shift count for getting to the cRefs part. */
2647#define PGMPOOL_TD_CREFS_SHIFT 14
2648/** The mask applied after shifting the tracking data down by
2649 * PGMPOOL_TD_CREFS_SHIFT. */
2650#define PGMPOOL_TD_CREFS_MASK 0x3
2651/** The cRefs value used to indicate that the idx is the head of a
2652 * physical cross reference list. */
2653#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2654/** The shift used to get idx. */
2655#define PGMPOOL_TD_IDX_SHIFT 0
2656/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2657#define PGMPOOL_TD_IDX_MASK 0x3fff
2658/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2659 * simply too many mappings of this page. */
2660#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2661
2662/** @def PGMPOOL_TD_MAKE
2663 * Makes a 16-bit tracking data word.
2664 *
2665 * @returns tracking data.
2666 * @param cRefs The @a cRefs field. Must be within bounds!
2667 * @param idx The @a idx field. Must also be within bounds! */
2668#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2669
2670/** @def PGMPOOL_TD_GET_CREFS
2671 * Get the @a cRefs field from a tracking data word.
2672 *
2673 * @returns The @a cRefs field
2674 * @param u16 The tracking data word.
2675 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2676 * non-zero @a u16. */
2677#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2678
2679/** @def PGMPOOL_TD_GET_IDX
2680 * Get the @a idx field from a tracking data word.
2681 *
2682 * @returns The @a idx field
2683 * @param u16 The tracking data word. */
2684#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2685/** @} */
2686
2687
2688
2689/** @name A20 gate macros
2690 * @{ */
2691#define PGM_WITH_A20
2692#ifdef PGM_WITH_A20
2693# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2694# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2695# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2696 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2697# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2698#else
2699# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2700# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2701# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2702# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2703#endif
2704/** @} */
2705
2706
2707/**
2708 * Roots and anchors for trees and list employing self relative offsets as
2709 * pointers.
2710 *
2711 * When using self-relative offsets instead of pointers, the offsets needs to be
2712 * the same in all offsets. Thus the roots and anchors needs to live on the
2713 * hyper heap just like the nodes.
2714 */
2715typedef struct PGMTREES
2716{
2717 /** List of physical access handler types (offset pointers) of type
2718 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2719 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2720 /** Physical access handlers (AVL range+offsetptr tree). */
2721 AVLROGCPHYSTREE PhysHandlers;
2722#ifdef VBOX_WITH_RAW_MODE
2723 /** Virtual access handlers (AVL range + GC ptr tree). */
2724 AVLROGCPTRTREE VirtHandlers;
2725 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2726 * @remarks Handler of the hypervisor kind are of course not present. */
2727 AVLROGCPHYSTREE PhysToVirtHandlers;
2728 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2729 AVLROGCPTRTREE HyperVirtHandlers;
2730 /** List of virtual access handler types (offset pointers) of type
2731 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2732 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2733#endif
2734} PGMTREES;
2735/** Pointer to PGM trees. */
2736typedef PGMTREES *PPGMTREES;
2737
2738
2739/**
2740 * Page fault guest state for the AMD64 paging mode.
2741 */
2742typedef struct PGMPTWALKCORE
2743{
2744 /** The guest virtual address that is being resolved by the walk
2745 * (input). */
2746 RTGCPTR GCPtr;
2747
2748 /** The guest physical address that is the result of the walk.
2749 * @remarks only valid if fSucceeded is set. */
2750 RTGCPHYS GCPhys;
2751
2752 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2753 bool fSucceeded;
2754 /** The level problem arrised at.
2755 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2756 * level 8. This is 0 on success. */
2757 uint8_t uLevel;
2758 /** Set if the page isn't present. */
2759 bool fNotPresent;
2760 /** Encountered a bad physical address. */
2761 bool fBadPhysAddr;
2762 /** Set if there was reserved bit violations. */
2763 bool fRsvdError;
2764 /** Set if it involves a big page (2/4 MB). */
2765 bool fBigPage;
2766 /** Set if it involves a gigantic page (1 GB). */
2767 bool fGigantPage;
2768 /** The effect X86_PTE_US flag for the address. */
2769 bool fEffectiveUS;
2770 /** The effect X86_PTE_RW flag for the address. */
2771 bool fEffectiveRW;
2772 /** The effect X86_PTE_NX flag for the address. */
2773 bool fEffectiveNX;
2774} PGMPTWALKCORE;
2775
2776
2777/**
2778 * Guest page table walk for the AMD64 mode.
2779 */
2780typedef struct PGMPTWALKGSTAMD64
2781{
2782 /** The common core. */
2783 PGMPTWALKCORE Core;
2784
2785 PX86PML4 pPml4;
2786 PX86PML4E pPml4e;
2787 X86PML4E Pml4e;
2788
2789 PX86PDPT pPdpt;
2790 PX86PDPE pPdpe;
2791 X86PDPE Pdpe;
2792
2793 PX86PDPAE pPd;
2794 PX86PDEPAE pPde;
2795 X86PDEPAE Pde;
2796
2797 PX86PTPAE pPt;
2798 PX86PTEPAE pPte;
2799 X86PTEPAE Pte;
2800} PGMPTWALKGSTAMD64;
2801/** Pointer to a AMD64 guest page table walk. */
2802typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2803/** Pointer to a const AMD64 guest page table walk. */
2804typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2805
2806/**
2807 * Guest page table walk for the PAE mode.
2808 */
2809typedef struct PGMPTWALKGSTPAE
2810{
2811 /** The common core. */
2812 PGMPTWALKCORE Core;
2813
2814 PX86PDPT pPdpt;
2815 PX86PDPE pPdpe;
2816 X86PDPE Pdpe;
2817
2818 PX86PDPAE pPd;
2819 PX86PDEPAE pPde;
2820 X86PDEPAE Pde;
2821
2822 PX86PTPAE pPt;
2823 PX86PTEPAE pPte;
2824 X86PTEPAE Pte;
2825} PGMPTWALKGSTPAE;
2826/** Pointer to a PAE guest page table walk. */
2827typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2828/** Pointer to a const AMD64 guest page table walk. */
2829typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2830
2831/**
2832 * Guest page table walk for the 32-bit mode.
2833 */
2834typedef struct PGMPTWALKGST32BIT
2835{
2836 /** The common core. */
2837 PGMPTWALKCORE Core;
2838
2839 PX86PD pPd;
2840 PX86PDE pPde;
2841 X86PDE Pde;
2842
2843 PX86PT pPt;
2844 PX86PTE pPte;
2845 X86PTE Pte;
2846} PGMPTWALKGST32BIT;
2847/** Pointer to a 32-bit guest page table walk. */
2848typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2849/** Pointer to a const 32-bit guest page table walk. */
2850typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2851
2852/**
2853 * Which part of PGMPTWALKGST that is valid.
2854 */
2855typedef enum PGMPTWALKGSTTYPE
2856{
2857 /** Customary invalid 0 value. */
2858 PGMPTWALKGSTTYPE_INVALID = 0,
2859 /** PGMPTWALKGST::u.Amd64 is valid. */
2860 PGMPTWALKGSTTYPE_AMD64,
2861 /** PGMPTWALKGST::u.Pae is valid. */
2862 PGMPTWALKGSTTYPE_PAE,
2863 /** PGMPTWALKGST::u.Legacy is valid. */
2864 PGMPTWALKGSTTYPE_32BIT,
2865 /** Customary 32-bit type hack. */
2866 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2867} PGMPTWALKGSTTYPE;
2868
2869/**
2870 * Combined guest page table walk result.
2871 */
2872typedef struct PGMPTWALKGST
2873{
2874 union
2875 {
2876 /** The page walker core - always valid. */
2877 PGMPTWALKCORE Core;
2878 /** The page walker for AMD64. */
2879 PGMPTWALKGSTAMD64 Amd64;
2880 /** The page walker for PAE (32-bit). */
2881 PGMPTWALKGSTPAE Pae;
2882 /** The page walker for 32-bit paging (called legacy due to C naming
2883 * convension). */
2884 PGMPTWALKGST32BIT Legacy;
2885 } u;
2886 /** Indicates which part of the union is valid. */
2887 PGMPTWALKGSTTYPE enmType;
2888} PGMPTWALKGST;
2889/** Pointer to a combined guest page table walk result. */
2890typedef PGMPTWALKGST *PPGMPTWALKGST;
2891/** Pointer to a read-only combined guest page table walk result. */
2892typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2893
2894
2895/** @name Paging mode macros
2896 * @{
2897 */
2898#ifdef IN_RC
2899# define PGM_CTX(a,b) a##RC##b
2900# define PGM_CTX_STR(a,b) a "GC" b
2901# define PGM_CTX_DECL(type) VMMRCDECL(type)
2902#else
2903# ifdef IN_RING3
2904# define PGM_CTX(a,b) a##R3##b
2905# define PGM_CTX_STR(a,b) a "R3" b
2906# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2907# else
2908# define PGM_CTX(a,b) a##R0##b
2909# define PGM_CTX_STR(a,b) a "R0" b
2910# define PGM_CTX_DECL(type) VMMDECL(type)
2911# endif
2912#endif
2913
2914#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2915#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2916#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2917#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2918#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2919#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2920#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2921#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2922#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2923#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2924#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2925#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2926#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2927#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2928#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2929#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2930#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2931
2932#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2933#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2934#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2935#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2936#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2937#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2938#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2939#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2940#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2941#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2942#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2943#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2944#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2945#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2946#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2947#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2948#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2949
2950/* Shw_Gst */
2951#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2952#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2953#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2954#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2955#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2956#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2957#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2958#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2959#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2960#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2961#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2962#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2963#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2964#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2965#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2966#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2967#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2968#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2969#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2970
2971#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2972#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2973#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2974#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2975#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2976#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2977#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2978#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2979#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2980#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2981#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2982#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2983#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2984#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2985#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2986#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2987#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2988#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2989#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2990#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2991#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2992#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2993#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2994#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2995#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2996#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2997#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2998#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2999#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
3000#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
3001#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
3002#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
3003#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3004#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3005#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3006#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3007#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3008
3009#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3010#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
3011/** @} */
3012
3013/**
3014 * Data for each paging mode.
3015 */
3016typedef struct PGMMODEDATA
3017{
3018 /** The guest mode type. */
3019 uint32_t uGstType;
3020 /** The shadow mode type. */
3021 uint32_t uShwType;
3022
3023 /** @name Function pointers for Shadow paging.
3024 * @{
3025 */
3026 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3027 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3028 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3029 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3030
3031 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3032 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3033
3034 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3035 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3036 /** @} */
3037
3038 /** @name Function pointers for Guest paging.
3039 * @{
3040 */
3041 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3042 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3043 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3044 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3045 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3046 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3047 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3048 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3049 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3050 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3051 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3052 /** @} */
3053
3054 /** @name Function pointers for Both Shadow and Guest paging.
3055 * @{
3056 */
3057 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3058 /* no pfnR3BthTrap0eHandler */
3059 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3060 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3061 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3062 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3063#ifdef VBOX_STRICT
3064 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3065#endif
3066 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3067 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3068
3069 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3070 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3071 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3072 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3073 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3074#ifdef VBOX_STRICT
3075 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3076#endif
3077 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3078 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3079
3080 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3081 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3082 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3083 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3084 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3085#ifdef VBOX_STRICT
3086 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3087#endif
3088 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3089 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3090 /** @} */
3091} PGMMODEDATA, *PPGMMODEDATA;
3092
3093
3094#ifdef VBOX_WITH_STATISTICS
3095/**
3096 * PGM statistics.
3097 *
3098 * These lives on the heap when compiled in as they would otherwise waste
3099 * unnecessary space in release builds.
3100 */
3101typedef struct PGMSTATS
3102{
3103 /* R3 only: */
3104 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3105 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3106
3107 /* R3+RZ */
3108 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3109 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3110 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3111 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3112 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3113 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3114 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3115 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3116 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3117 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3118 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3119 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3120 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3121 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3122 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3123 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3124 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3125 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3126 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3127 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3128 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3129 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3130 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3131 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3132 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3133 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3134 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3135 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3136/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3137 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3138 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3139/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3140
3141 /* RC only: */
3142 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3143 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3144
3145 STAMCOUNTER StatRZPhysRead;
3146 STAMCOUNTER StatRZPhysReadBytes;
3147 STAMCOUNTER StatRZPhysWrite;
3148 STAMCOUNTER StatRZPhysWriteBytes;
3149 STAMCOUNTER StatR3PhysRead;
3150 STAMCOUNTER StatR3PhysReadBytes;
3151 STAMCOUNTER StatR3PhysWrite;
3152 STAMCOUNTER StatR3PhysWriteBytes;
3153 STAMCOUNTER StatRCPhysRead;
3154 STAMCOUNTER StatRCPhysReadBytes;
3155 STAMCOUNTER StatRCPhysWrite;
3156 STAMCOUNTER StatRCPhysWriteBytes;
3157
3158 STAMCOUNTER StatRZPhysSimpleRead;
3159 STAMCOUNTER StatRZPhysSimpleReadBytes;
3160 STAMCOUNTER StatRZPhysSimpleWrite;
3161 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3162 STAMCOUNTER StatR3PhysSimpleRead;
3163 STAMCOUNTER StatR3PhysSimpleReadBytes;
3164 STAMCOUNTER StatR3PhysSimpleWrite;
3165 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3166 STAMCOUNTER StatRCPhysSimpleRead;
3167 STAMCOUNTER StatRCPhysSimpleReadBytes;
3168 STAMCOUNTER StatRCPhysSimpleWrite;
3169 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3170
3171 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3172 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3173 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3174 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3175 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3176 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3177 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3178
3179 /** Time spent by the host OS for large page allocation. */
3180 STAMPROFILE StatAllocLargePage;
3181 /** Time spent clearing the newly allocated large pages. */
3182 STAMPROFILE StatClearLargePage;
3183 /** The number of times allocating a large pages takes more than the allowed period. */
3184 STAMCOUNTER StatLargePageOverflow;
3185 /** pgmPhysIsValidLargePage profiling - R3 */
3186 STAMPROFILE StatR3IsValidLargePage;
3187 /** pgmPhysIsValidLargePage profiling - RZ*/
3188 STAMPROFILE StatRZIsValidLargePage;
3189
3190 STAMPROFILE StatChunkAging;
3191 STAMPROFILE StatChunkFindCandidate;
3192 STAMPROFILE StatChunkUnmap;
3193 STAMPROFILE StatChunkMap;
3194} PGMSTATS;
3195#endif /* VBOX_WITH_STATISTICS */
3196
3197
3198/**
3199 * Converts a PGM pointer into a VM pointer.
3200 * @returns Pointer to the VM structure the PGM is part of.
3201 * @param pPGM Pointer to PGM instance data.
3202 */
3203#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3204
3205/**
3206 * PGM Data (part of VM)
3207 */
3208typedef struct PGM
3209{
3210 /** Offset to the VM structure. */
3211 int32_t offVM;
3212 /** Offset of the PGMCPU structure relative to VMCPU. */
3213 int32_t offVCpuPGM;
3214
3215 /** @cfgm{/RamPreAlloc, boolean, false}
3216 * Indicates whether the base RAM should all be allocated before starting
3217 * the VM (default), or if it should be allocated when first written to.
3218 */
3219 bool fRamPreAlloc;
3220 /** Indicates whether write monitoring is currently in use.
3221 * This is used to prevent conflicts between live saving and page sharing
3222 * detection. */
3223 bool fPhysWriteMonitoringEngaged;
3224 /** Set if the CPU has less than 52-bit physical address width.
3225 * This is used */
3226 bool fLessThan52PhysicalAddressBits;
3227 /** Set when nested paging is active.
3228 * This is meant to save calls to HMIsNestedPagingActive and let the
3229 * compilers optimize the code better. Whether we use nested paging or
3230 * not is something we find out during VMM initialization and we won't
3231 * change this later on. */
3232 bool fNestedPaging;
3233 /** The host paging mode. (This is what SUPLib reports.) */
3234 SUPPAGINGMODE enmHostMode;
3235 /** We're not in a state which permits writes to guest memory.
3236 * (Only used in strict builds.) */
3237 bool fNoMorePhysWrites;
3238 /** @cfgm{/PageFusionAllowed, boolean, false}
3239 * Whether page fusion is allowed. */
3240 bool fPageFusionAllowed;
3241 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3242 * Whether PCI passthrough is enabled. */
3243 bool fPciPassthrough;
3244 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3245 uint8_t cMmio2Regions;
3246 /** Restore original ROM page content when resetting after loading state.
3247 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3248 * enables the VM to start using an updated ROM without requiring powering
3249 * down the VM, just rebooting or resetting it. */
3250 bool fRestoreRomPagesOnReset;
3251 /** Whether to automatically clear all RAM pages on reset. */
3252 bool fZeroRamPagesOnReset;
3253 /** Alignment padding. */
3254 bool afAlignment3[7];
3255
3256 /** Indicates that PGMR3FinalizeMappings has been called and that further
3257 * PGMR3MapIntermediate calls will be rejected. */
3258 bool fFinalizedMappings;
3259 /** If set no conflict checks are required. */
3260 bool fMappingsFixed;
3261 /** If set if restored as fixed but we were unable to re-fixate at the old
3262 * location because of room or address incompatibilities. */
3263 bool fMappingsFixedRestored;
3264 /** Size of fixed mapping.
3265 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3266 uint32_t cbMappingFixed;
3267 /** Generation ID for the RAM ranges. This member is incremented everytime
3268 * a RAM range is linked or unlinked. */
3269 uint32_t volatile idRamRangesGen;
3270
3271 /** Base address (GC) of fixed mapping.
3272 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3273 RTGCPTR GCPtrMappingFixed;
3274 /** The address of the previous RAM range mapping. */
3275 RTGCPTR GCPtrPrevRamRangeMapping;
3276
3277 /** Physical access handler type for ROM protection. */
3278 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3279 /** Alignment padding. */
3280 uint32_t u32Padding;
3281
3282 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3283 RTGCPHYS GCPhys4MBPSEMask;
3284 /** Mask containing the invalid bits of a guest physical address.
3285 * @remarks this does not stop at bit 52. */
3286 RTGCPHYS GCPhysInvAddrMask;
3287
3288
3289 /** RAM range TLB for R3. */
3290 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3291 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3292 * This is sorted by physical address and contains no overlapping ranges. */
3293 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3294 /** Root of the RAM range search tree for ring-3. */
3295 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3296 /** PGM offset based trees - R3 Ptr. */
3297 R3PTRTYPE(PPGMTREES) pTreesR3;
3298 /** Caching the last physical handler we looked up in R3. */
3299 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3300 /** Shadow Page Pool - R3 Ptr. */
3301 R3PTRTYPE(PPGMPOOL) pPoolR3;
3302 /** Linked list of GC mappings - for HC.
3303 * The list is sorted ascending on address. */
3304 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3305 /** Pointer to the list of ROM ranges - for R3.
3306 * This is sorted by physical address and contains no overlapping ranges. */
3307 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3308 /** Pointer to the list of MMIO2 ranges - for R3.
3309 * Registration order. */
3310 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3311 /** Pointer to SHW+GST mode data (function pointers).
3312 * The index into this table is made up from */
3313 R3PTRTYPE(PPGMMODEDATA) paModeData;
3314 RTR3PTR R3PtrAlignment0;
3315 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3316 R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3317
3318 /** RAM range TLB for R0. */
3319 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3320 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3321 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3322 /** Root of the RAM range search tree for ring-0. */
3323 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3324 /** PGM offset based trees - R0 Ptr. */
3325 R0PTRTYPE(PPGMTREES) pTreesR0;
3326 /** Caching the last physical handler we looked up in R0. */
3327 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3328 /** Shadow Page Pool - R0 Ptr. */
3329 R0PTRTYPE(PPGMPOOL) pPoolR0;
3330 /** Linked list of GC mappings - for R0.
3331 * The list is sorted ascending on address. */
3332 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3333 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3334 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3335 RTR0PTR R0PtrAlignment0;
3336 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3337 R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3338
3339 /** RAM range TLB for RC. */
3340 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3341 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3342 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3343 /** Root of the RAM range search tree for raw-mode context. */
3344 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3345 /** PGM offset based trees - RC Ptr. */
3346 RCPTRTYPE(PPGMTREES) pTreesRC;
3347 /** Caching the last physical handler we looked up in RC. */
3348 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3349 /** Shadow Page Pool - RC Ptr. */
3350 RCPTRTYPE(PPGMPOOL) pPoolRC;
3351 /** Linked list of GC mappings - for RC.
3352 * The list is sorted ascending on address. */
3353 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3354 /** RC pointer corresponding to PGM::pRomRangesR3. */
3355 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3356 RTRCPTR RCPtrAlignment0;
3357 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3358 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3359 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3360 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3361
3362
3363 /** Pointer to the 5 page CR3 content mapping.
3364 * The first page is always the CR3 (in some form) while the 4 other pages
3365 * are used of the PDs in PAE mode. */
3366 RTGCPTR GCPtrCR3Mapping;
3367
3368 /** @name Intermediate Context
3369 * @{ */
3370 /** Pointer to the intermediate page directory - Normal. */
3371 R3PTRTYPE(PX86PD) pInterPD;
3372 /** Pointer to the intermediate page tables - Normal.
3373 * There are two page tables, one for the identity mapping and one for
3374 * the host context mapping (of the core code). */
3375 R3PTRTYPE(PX86PT) apInterPTs[2];
3376 /** Pointer to the intermediate page tables - PAE. */
3377 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3378 /** Pointer to the intermediate page directory - PAE. */
3379 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3380 /** Pointer to the intermediate page directory - PAE. */
3381 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3382 /** Pointer to the intermediate page-map level 4 - AMD64. */
3383 R3PTRTYPE(PX86PML4) pInterPaePML4;
3384 /** Pointer to the intermediate page directory - AMD64. */
3385 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3386 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3387 RTHCPHYS HCPhysInterPD;
3388 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3389 RTHCPHYS HCPhysInterPaePDPT;
3390 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3391 RTHCPHYS HCPhysInterPaePML4;
3392 /** @} */
3393
3394 /** Base address of the dynamic page mapping area.
3395 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3396 *
3397 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3398 * work out. Some cleaning up of the initialization that would
3399 * remove this memory is yet to be done...
3400 */
3401 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3402 /** The address of the raw-mode context mapping cache. */
3403 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3404 /** The address of the ring-0 mapping cache if we're making use of it. */
3405 RTR0PTR pvR0DynMapUsed;
3406
3407 /** Hack: Number of deprecated page mapping locks taken by the current lock
3408 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3409 uint32_t cDeprecatedPageLocks;
3410#if HC_ARCH_BITS == 64
3411 /** Alignment padding. */
3412 uint32_t u32Alignment2;
3413#endif
3414
3415
3416 /** PGM critical section.
3417 * This protects the physical & virtual access handlers, ram ranges,
3418 * and the page flag updating (some of it anyway).
3419 */
3420 PDMCRITSECT CritSectX;
3421
3422 /**
3423 * Data associated with managing the ring-3 mappings of the allocation chunks.
3424 */
3425 struct
3426 {
3427 /** The chunk tree, ordered by chunk id. */
3428#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3429 R3PTRTYPE(PAVLU32NODECORE) pTree;
3430#else
3431 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3432#endif
3433#if HC_ARCH_BITS == 32
3434 uint32_t u32Alignment0;
3435#endif
3436 /** The chunk mapping TLB. */
3437 PGMCHUNKR3MAPTLB Tlb;
3438 /** The number of mapped chunks. */
3439 uint32_t c;
3440 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3441 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3442 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3443 uint32_t cMax;
3444 /** The current time. This is incremented whenever a chunk is inserted. */
3445 uint32_t iNow;
3446 /** Alignment padding. */
3447 uint32_t u32Alignment1;
3448 } ChunkR3Map;
3449
3450 /**
3451 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3452 */
3453 PGMPAGER3MAPTLB PhysTlbHC;
3454
3455 /** @name The zero page.
3456 * @{ */
3457 /** The host physical address of the zero page. */
3458 RTHCPHYS HCPhysZeroPg;
3459 /** The ring-3 mapping of the zero page. */
3460 RTR3PTR pvZeroPgR3;
3461 /** The ring-0 mapping of the zero page. */
3462 RTR0PTR pvZeroPgR0;
3463 /** The GC mapping of the zero page. */
3464 RTRCPTR pvZeroPgRC;
3465 RTRCPTR RCPtrAlignment3;
3466 /** @}*/
3467
3468 /** @name The Invalid MMIO page.
3469 * This page is filled with 0xfeedface.
3470 * @{ */
3471 /** The host physical address of the invalid MMIO page. */
3472 RTHCPHYS HCPhysMmioPg;
3473 /** The host pysical address of the invalid MMIO page plus all invalid
3474 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3475 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3476 RTHCPHYS HCPhysInvMmioPg;
3477 /** The ring-3 mapping of the invalid MMIO page. */
3478 RTR3PTR pvMmioPgR3;
3479#if HC_ARCH_BITS == 32
3480 RTR3PTR R3PtrAlignment4;
3481#endif
3482 /** @} */
3483
3484
3485 /** The number of handy pages. */
3486 uint32_t cHandyPages;
3487
3488 /** The number of large handy pages. */
3489 uint32_t cLargeHandyPages;
3490
3491 /**
3492 * Array of handy pages.
3493 *
3494 * This array is used in a two way communication between pgmPhysAllocPage
3495 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3496 * an intermediary.
3497 *
3498 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3499 * (The current size of 32 pages, means 128 KB of handy memory.)
3500 */
3501 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3502
3503 /**
3504 * Array of large handy pages. (currently size 1)
3505 *
3506 * This array is used in a two way communication between pgmPhysAllocLargePage
3507 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3508 * an intermediary.
3509 */
3510 GMMPAGEDESC aLargeHandyPage[1];
3511
3512 /**
3513 * Live save data.
3514 */
3515 struct
3516 {
3517 /** Per type statistics. */
3518 struct
3519 {
3520 /** The number of ready pages. */
3521 uint32_t cReadyPages;
3522 /** The number of dirty pages. */
3523 uint32_t cDirtyPages;
3524 /** The number of ready zero pages. */
3525 uint32_t cZeroPages;
3526 /** The number of write monitored pages. */
3527 uint32_t cMonitoredPages;
3528 } Rom,
3529 Mmio2,
3530 Ram;
3531 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3532 uint32_t cIgnoredPages;
3533 /** Indicates that a live save operation is active. */
3534 bool fActive;
3535 /** Padding. */
3536 bool afReserved[2];
3537 /** The next history index. */
3538 uint8_t iDirtyPagesHistory;
3539 /** History of the total amount of dirty pages. */
3540 uint32_t acDirtyPagesHistory[64];
3541 /** Short term dirty page average. */
3542 uint32_t cDirtyPagesShort;
3543 /** Long term dirty page average. */
3544 uint32_t cDirtyPagesLong;
3545 /** The number of saved pages. This is used to get some kind of estimate of the
3546 * link speed so we can decide when we're done. It is reset after the first
3547 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3548 * zero pages. */
3549 uint64_t cSavedPages;
3550 /** The nanosecond timestamp when cSavedPages was 0. */
3551 uint64_t uSaveStartNS;
3552 /** Pages per second (for statistics). */
3553 uint32_t cPagesPerSecond;
3554 uint32_t cAlignment;
3555 } LiveSave;
3556
3557 /** @name Error injection.
3558 * @{ */
3559 /** Inject handy page allocation errors pretending we're completely out of
3560 * memory. */
3561 bool volatile fErrInjHandyPages;
3562 /** Padding. */
3563 bool afReserved[3];
3564 /** @} */
3565
3566 /** @name Release Statistics
3567 * @{ */
3568 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3569 uint32_t cPrivatePages; /**< The number of private pages. */
3570 uint32_t cSharedPages; /**< The number of shared pages. */
3571 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3572 uint32_t cZeroPages; /**< The number of zero backed pages. */
3573 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3574 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3575 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3576 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3577 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3578 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3579 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3580 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3581 uint32_t cLargePages; /**< The number of large pages. */
3582 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3583/* uint32_t aAlignment4[1]; */
3584
3585 /** The number of times we were forced to change the hypervisor region location. */
3586 STAMCOUNTER cRelocations;
3587
3588 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3589 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3590 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3591
3592 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3593 /** @} */
3594
3595#ifdef VBOX_WITH_STATISTICS
3596 /** @name Statistics on the heap.
3597 * @{ */
3598 R3PTRTYPE(PGMSTATS *) pStatsR3;
3599 R0PTRTYPE(PGMSTATS *) pStatsR0;
3600 RCPTRTYPE(PGMSTATS *) pStatsRC;
3601 RTRCPTR RCPtrAlignment;
3602 /** @} */
3603#endif
3604} PGM;
3605#ifndef IN_TSTVMSTRUCTGC /* HACK */
3606AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3607AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3608AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3609AssertCompileMemberAlignment(PGM, CritSectX, 8);
3610AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3611AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3612AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3613AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3614AssertCompileMemberAlignment(PGM, cRelocations, 8);
3615#endif /* !IN_TSTVMSTRUCTGC */
3616/** Pointer to the PGM instance data. */
3617typedef PGM *PPGM;
3618
3619
3620
3621typedef struct PGMCPUSTATS
3622{
3623 /* Common */
3624 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3625 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3626
3627 /* R0 only: */
3628 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3629 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3630
3631 /* RZ only: */
3632 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3633 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3634 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3635 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3636 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3637 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3638 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3639 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3640 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3641 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3642 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3643 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3644 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3645 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3646 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3647 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3648 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3649 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3650 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3651 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3652 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3653 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3654 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3655 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3656 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3657 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3658 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3659 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3660 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3661 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3662 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3663 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3664 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3665 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3666 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3667 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3668 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3669 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3670 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3671 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3672 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3673 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3674 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3675 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3676 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3677 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3678 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3679 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3680 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3681 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3682 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3683 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3684 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3685 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3686 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3687 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3688 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3689 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3690 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3691 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3692 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3693 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3694 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3695 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3696 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3697 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3698 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3699 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3700 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3701 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3702 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3703 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3704 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3705 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3706 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3707 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3708 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3709 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3710
3711 /* HC - R3 and (maybe) R0: */
3712
3713 /* RZ & R3: */
3714 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3715 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3716 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3717 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3718 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3719 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3720 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3721 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3722 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3723 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3724 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3725 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3726 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3727 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3728 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3729 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3730 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3731 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3732 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3733 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3734 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3735 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3736 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3737 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3738 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3739 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3740 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3741 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3742 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3743 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3744 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3745 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3746 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3747 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3748 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3749 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3750 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3751 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3752 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3753 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3754 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3755 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3756 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3757 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3758 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3759 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3760 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3761
3762 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3763 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3764 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3765 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3766 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3767 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3768 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3769 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3770 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3771 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3772 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3773 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3774 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3775 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3776 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3777 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3778 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3779 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3780 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3781 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3782 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3783 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3784 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3785 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3786 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3787 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3788 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3789 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3790 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3791 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3792 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3793 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3794 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3795 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3796 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3797 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3798 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3799 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3800 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3801 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3802 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3803 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3804 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3805 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3806 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3807 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3808 /** @} */
3809} PGMCPUSTATS;
3810
3811
3812/**
3813 * Converts a PGMCPU pointer into a VM pointer.
3814 * @returns Pointer to the VM structure the PGM is part of.
3815 * @param pPGM Pointer to PGMCPU instance data.
3816 */
3817#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3818
3819/**
3820 * Converts a PGMCPU pointer into a PGM pointer.
3821 * @returns Pointer to the VM structure the PGM is part of.
3822 * @param pPGMCpu Pointer to PGMCPU instance data.
3823 */
3824#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3825
3826/**
3827 * PGMCPU Data (part of VMCPU).
3828 */
3829typedef struct PGMCPU
3830{
3831 /** Offset to the VM structure. */
3832 int32_t offVM;
3833 /** Offset to the VMCPU structure. */
3834 int32_t offVCpu;
3835 /** Offset of the PGM structure relative to VMCPU. */
3836 int32_t offPGM;
3837 uint32_t uPadding0; /**< structure size alignment. */
3838
3839#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3840 /** Automatically tracked physical memory mapping set.
3841 * Ring-0 and strict raw-mode builds. */
3842 PGMMAPSET AutoSet;
3843#endif
3844
3845 /** A20 gate mask.
3846 * Our current approach to A20 emulation is to let REM do it and don't bother
3847 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3848 * But whould need arrise, we'll subject physical addresses to this mask. */
3849 RTGCPHYS GCPhysA20Mask;
3850 /** A20 gate state - boolean! */
3851 bool fA20Enabled;
3852 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3853 bool fNoExecuteEnabled;
3854 /** Unused bits. */
3855 bool afUnused[2];
3856
3857 /** What needs syncing (PGM_SYNC_*).
3858 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3859 * PGMFlushTLB, and PGMR3Load. */
3860 uint32_t fSyncFlags;
3861
3862 /** The shadow paging mode. */
3863 PGMMODE enmShadowMode;
3864 /** The guest paging mode. */
3865 PGMMODE enmGuestMode;
3866
3867 /** The current physical address representing in the guest CR3 register. */
3868 RTGCPHYS GCPhysCR3;
3869
3870 /** @name 32-bit Guest Paging.
3871 * @{ */
3872 /** The guest's page directory, R3 pointer. */
3873 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3874#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3875 /** The guest's page directory, R0 pointer. */
3876 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3877#endif
3878 /** The guest's page directory, static RC mapping. */
3879 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3880 /** Mask containing the MBZ bits of a big page PDE. */
3881 uint32_t fGst32BitMbzBigPdeMask;
3882 /** Set if the page size extension (PSE) is enabled. */
3883 bool fGst32BitPageSizeExtension;
3884 /** Alignment padding. */
3885 bool afAlignment2[3];
3886 /** @} */
3887
3888 /** @name PAE Guest Paging.
3889 * @{ */
3890 /** The guest's page directory pointer table, static RC mapping. */
3891 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3892 /** The guest's page directory pointer table, R3 pointer. */
3893 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3894#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3895 /** The guest's page directory pointer table, R0 pointer. */
3896 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3897#endif
3898
3899 /** The guest's page directories, R3 pointers.
3900 * These are individual pointers and don't have to be adjacent.
3901 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3902 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3903 /** The guest's page directories, R0 pointers.
3904 * Same restrictions as apGstPaePDsR3. */
3905#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3906 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3907#endif
3908 /** The guest's page directories, static GC mapping.
3909 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3910 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3911 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3912 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3913 * @todo Remove this and use aGstPaePdpeRegs instead? */
3914 RTGCPHYS aGCPhysGstPaePDs[4];
3915 /** The values of the 4 PDPE CPU registers (PAE). */
3916 X86PDPE aGstPaePdpeRegs[4];
3917 /** The physical addresses of the monitored guest page directories (PAE). */
3918 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3919 /** Mask containing the MBZ PTE bits. */
3920 uint64_t fGstPaeMbzPteMask;
3921 /** Mask containing the MBZ PDE bits. */
3922 uint64_t fGstPaeMbzPdeMask;
3923 /** Mask containing the MBZ big page PDE bits. */
3924 uint64_t fGstPaeMbzBigPdeMask;
3925 /** Mask containing the MBZ PDPE bits. */
3926 uint64_t fGstPaeMbzPdpeMask;
3927 /** @} */
3928
3929 /** @name AMD64 Guest Paging.
3930 * @{ */
3931 /** The guest's page directory pointer table, R3 pointer. */
3932 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3933#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3934 /** The guest's page directory pointer table, R0 pointer. */
3935 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3936#else
3937 RTR0PTR alignment6b; /**< alignment equalizer. */
3938#endif
3939 /** Mask containing the MBZ PTE bits. */
3940 uint64_t fGstAmd64MbzPteMask;
3941 /** Mask containing the MBZ PDE bits. */
3942 uint64_t fGstAmd64MbzPdeMask;
3943 /** Mask containing the MBZ big page PDE bits. */
3944 uint64_t fGstAmd64MbzBigPdeMask;
3945 /** Mask containing the MBZ PDPE bits. */
3946 uint64_t fGstAmd64MbzPdpeMask;
3947 /** Mask containing the MBZ big page PDPE bits. */
3948 uint64_t fGstAmd64MbzBigPdpeMask;
3949 /** Mask containing the MBZ PML4E bits. */
3950 uint64_t fGstAmd64MbzPml4eMask;
3951 /** Mask containing the PDPE bits that we shadow. */
3952 uint64_t fGstAmd64ShadowedPdpeMask;
3953 /** Mask containing the PML4E bits that we shadow. */
3954 uint64_t fGstAmd64ShadowedPml4eMask;
3955 /** @} */
3956
3957 /** @name PAE and AMD64 Guest Paging.
3958 * @{ */
3959 /** Mask containing the PTE bits that we shadow. */
3960 uint64_t fGst64ShadowedPteMask;
3961 /** Mask containing the PDE bits that we shadow. */
3962 uint64_t fGst64ShadowedPdeMask;
3963 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3964 uint64_t fGst64ShadowedBigPdeMask;
3965 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3966 uint64_t fGst64ShadowedBigPde4PteMask;
3967 /** @} */
3968
3969 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3970 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3971 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3972 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3973 /** Pointer to the page of the current active CR3 - RC Ptr. */
3974 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3975# if HC_ARCH_BITS == 64
3976 RTRCPTR alignment6; /**< structure size alignment. */
3977# endif
3978 /** @} */
3979
3980 /** @name Function pointers for Shadow paging.
3981 * @{
3982 */
3983 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3984 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3985 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3986 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3987
3988 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3989 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3990
3991 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3992 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3993
3994 /** @} */
3995
3996 /** @name Function pointers for Guest paging.
3997 * @{
3998 */
3999 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4000 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
4001 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4002 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4003 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4004 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4005 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4006 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4007#if HC_ARCH_BITS == 64
4008 RTRCPTR alignment3; /**< structure size alignment. */
4009#endif
4010
4011 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4012 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4013 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4014 /** @} */
4015
4016 /** @name Function pointers for Both Shadow and Guest paging.
4017 * @{
4018 */
4019 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4020 /* no pfnR3BthTrap0eHandler */
4021 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4022 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4023 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4024 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4025 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4026 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4027 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4028
4029 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4030 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4031 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4032 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4033 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4034 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4035 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4036 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4037
4038 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4039 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4040 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4041 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4042 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4043 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4044 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4045 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4046#if 0
4047 RTRCPTR alignment2; /**< structure size alignment. */
4048#endif
4049 /** @} */
4050
4051 /** For saving stack space, the disassembler state is allocated here instead of
4052 * on the stack. */
4053 DISCPUSTATE DisState;
4054
4055 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4056 uint64_t cNetwareWp0Hacks;
4057
4058 /** Count the number of pgm pool access handler calls. */
4059 uint64_t cPoolAccessHandler;
4060
4061 /** @name Release Statistics
4062 * @{ */
4063 /** The number of times the guest has switched mode since last reset or statistics reset. */
4064 STAMCOUNTER cGuestModeChanges;
4065 /** The number of times the guest has switched mode since last reset or statistics reset. */
4066 STAMCOUNTER cA20Changes;
4067 /** @} */
4068
4069#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4070 /** @name Statistics
4071 * @{ */
4072 /** RC: Pointer to the statistics. */
4073 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4074 /** RC: Which statistic this \#PF should be attributed to. */
4075 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4076 /** R0: Pointer to the statistics. */
4077 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4078 /** R0: Which statistic this \#PF should be attributed to. */
4079 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4080 /** R3: Pointer to the statistics. */
4081 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4082 /** Alignment padding. */
4083 RTR3PTR pPaddingR3;
4084 /** @} */
4085#endif /* VBOX_WITH_STATISTICS */
4086} PGMCPU;
4087/** Pointer to the per-cpu PGM data. */
4088typedef PGMCPU *PPGMCPU;
4089
4090
4091/** @name PGM::fSyncFlags Flags
4092 * @{
4093 */
4094/** Updates the virtual access handler state bit in PGMPAGE. */
4095#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4096/** Always sync CR3. */
4097#define PGM_SYNC_ALWAYS RT_BIT(1)
4098/** Check monitoring on next CR3 (re)load and invalidate page.
4099 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4100#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4101/** Check guest mapping in SyncCR3. */
4102#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4103/** Clear the page pool (a light weight flush). */
4104#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4105#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4106/** @} */
4107
4108
4109RT_C_DECLS_BEGIN
4110
4111#if defined(VBOX_STRICT) && defined(IN_RING3)
4112int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4113# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4114#else
4115int pgmLock(PVM pVM);
4116#endif
4117void pgmUnlock(PVM pVM);
4118/**
4119 * Asserts that the caller owns the PDM lock.
4120 * This is the internal variant of PGMIsLockOwner.
4121 * @param a_pVM Pointer to the VM.
4122 */
4123#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4124/**
4125 * Asserts that the caller owns the PDM lock.
4126 * This is the internal variant of PGMIsLockOwner.
4127 * @param a_pVM Pointer to the VM.
4128 * @param a_pVCpu The current CPU handle.
4129 */
4130#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4131
4132#ifndef PGM_WITHOUT_MAPPINGS
4133int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4134int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4135int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4136int pgmMapResolveConflicts(PVM pVM);
4137#endif /* !PGM_WITHOUT_MAPPINGS */
4138PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4139DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4140
4141void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4142bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4143void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4144#ifdef VBOX_WITH_RAW_MODE
4145PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4146DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4147# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4148void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4149# else
4150# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4151# endif
4152#endif /* VBOX_WITH_RAW_MODE */
4153DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4154int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4155
4156int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4157int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4158int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4159int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4160int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4161void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4162int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4163int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4164int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4165int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4166int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4167int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4168int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4169int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4170int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4171int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4172void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4173PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4174#ifndef IN_RING3
4175DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4176DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4177DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4178#endif
4179int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4180void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4181void pgmPhysInvalidatePageMapTLB(PVM pVM);
4182void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4183PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4184PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4185PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4186int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4187int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4188
4189#ifdef IN_RING3
4190void pgmR3PhysRelinkRamRanges(PVM pVM);
4191int pgmR3PhysRamPreAllocate(PVM pVM);
4192int pgmR3PhysRamReset(PVM pVM);
4193int pgmR3PhysRomReset(PVM pVM);
4194int pgmR3PhysRamZeroAll(PVM pVM);
4195int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4196int pgmR3PhysRamTerm(PVM pVM);
4197void pgmR3PhysRomTerm(PVM pVM);
4198void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4199
4200int pgmR3PoolInit(PVM pVM);
4201void pgmR3PoolRelocate(PVM pVM);
4202void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4203void pgmR3PoolReset(PVM pVM);
4204void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4205DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4206void pgmR3PoolWriteProtectPages(PVM pVM);
4207
4208#endif /* IN_RING3 */
4209#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4210int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4211int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4212# ifdef LOG_ENABLED
4213void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4214# else
4215void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4216# endif
4217#endif
4218int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4219 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4220void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4221void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4222int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4223void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4224PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4225PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4226int pgmPoolSyncCR3(PVMCPU pVCpu);
4227bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4228void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4229int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4230void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4231uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4232void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4233int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4234void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4235PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4236#ifndef IN_RING3
4237DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
4238#endif
4239
4240void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4241void pgmPoolResetDirtyPages(PVM pVM);
4242void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4243
4244int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4245int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4246void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4247
4248void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4249void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4250int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4251int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4252
4253int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4254int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4255int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4256
4257int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4258int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4259int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4260int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4261int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4262
4263# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4264FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4265FNDBGCCMD pgmR3CmdShowSharedModules;
4266# endif
4267
4268RT_C_DECLS_END
4269
4270/** @} */
4271
4272#endif
4273
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