VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 72064

Last change on this file since 72064 was 70977, checked in by vboxsync, 7 years ago

NEM: Working on PGM notifications. bugref:9044
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1/* $Id: PGMInternal.h 70977 2018-02-12 20:45:31Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hm.h>
36#include <VBox/vmm/hm_vmx.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/avl.h>
40#include <iprt/critsect.h>
41#include <iprt/list-off32.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings in the shadow tables.
59 *
60 * Note! In ring-3 the macro is also used to exclude the managment of the
61 * intermediate context page tables. On 32-bit systems we use the intermediate
62 * context to support 64-bit guest execution. Thus, we cannot fully make it
63 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
64 *
65 * In raw-mode context there are by design always guest mappings (the code is
66 * executed from one), while in ring-0 there are none at all. Neither context
67 * manages the page tables for intermediate switcher context, that's all done in
68 * ring-3.
69 */
70#if defined(IN_RING0) \
71 || ( !defined(VBOX_WITH_RAW_MODE) \
72 && ( HC_ARCH_BITS != 32 \
73 || !defined(VBOX_WITH_64_BITS_GUESTS) \
74 ) \
75 )
76# define PGM_WITHOUT_MAPPINGS
77#endif
78
79/**
80 * Check and skip global PDEs for non-global flushes
81 */
82#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
83
84/**
85 * Optimization for PAE page tables that are modified often
86 */
87//#if 0 /* disabled again while debugging */
88#ifndef IN_RC
89# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
90#endif
91//#endif
92
93/**
94 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
95 */
96#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
97# define PGM_WITH_LARGE_PAGES
98#endif
99
100/**
101 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
102 * VMX_EXIT_EPT_MISCONFIG.
103 */
104#if 1 /* testing */
105# define PGM_WITH_MMIO_OPTIMIZATIONS
106#endif
107
108/**
109 * Sync N pages instead of a whole page table
110 */
111#define PGM_SYNC_N_PAGES
112
113/**
114 * Number of pages to sync during a page fault
115 *
116 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118 *
119 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120 * world switch overhead, so let's sync more.
121 */
122# ifdef IN_RING0
123/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125 * but ~5% fewer faults.
126 */
127# define PGM_SYNC_NR_PAGES 32
128#else
129# define PGM_SYNC_NR_PAGES 8
130#endif
131
132/**
133 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134 */
135#define PGM_MAX_PHYSCACHE_ENTRIES 64
136#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139/** @def PGMPOOL_CFG_MAX_GROW
140 * The maximum number of pages to add to the pool in one go.
141 */
142#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
143
144/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
146 */
147#ifdef VBOX_STRICT
148# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149#endif
150
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153#ifdef DOXYGEN_RUNNING
154# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155#endif
156
157/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158 * Enables real write monitoring of pages, i.e. mapping them read-only and
159 * only making them writable when getting a write access \#PF. */
160#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** Mapping (hypervisor allocated pagetable). */
173#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174/** @} */
175
176/** @name Page directory flags.
177 * These are placed in the three bits available for system programs in
178 * the page directory entries.
179 * @{ */
180/** Indicates the original entry was a big page.
181 * @remarks This is currently only used for statistics and can be recycled. */
182#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED 6
213#define PGM_TYPE_EPT 7
214#define PGM_TYPE_MAX PGM_TYPE_EPT
215/** @} */
216
217/** Macro for checking if the guest is using paging.
218 * @param uGstType PGM_TYPE_*
219 * @param uShwType PGM_TYPE_*
220 * @remark ASSUMES certain order of the PGM_TYPE_* values.
221 */
222#define PGM_WITH_PAGING(uGstType, uShwType) \
223 ( (uGstType) >= PGM_TYPE_32BIT \
224 && (uShwType) != PGM_TYPE_NESTED \
225 && (uShwType) != PGM_TYPE_EPT)
226
227/** Macro for checking if the guest supports the NX bit.
228 * @param uGstType PGM_TYPE_*
229 * @param uShwType PGM_TYPE_*
230 * @remark ASSUMES certain order of the PGM_TYPE_* values.
231 */
232#define PGM_WITH_NX(uGstType, uShwType) \
233 ( (uGstType) >= PGM_TYPE_PAE \
234 && (uShwType) != PGM_TYPE_NESTED \
235 && (uShwType) != PGM_TYPE_EPT)
236
237
238/** @def PGM_HCPHYS_2_PTR
239 * Maps a HC physical page pool address to a virtual address.
240 *
241 * @returns VBox status code.
242 * @param pVM The cross context VM structure.
243 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
244 * @param HCPhys The HC physical address to map to a virtual one.
245 * @param ppv Where to store the virtual address. No need to cast
246 * this.
247 *
248 * @remark Use with care as we don't have so much dynamic mapping space in
249 * ring-0 on 32-bit darwin and in RC.
250 * @remark There is no need to assert on the result.
251 */
252#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
253# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
255#else
256# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
257 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
258#endif
259
260/** @def PGM_GCPHYS_2_PTR_V2
261 * Maps a GC physical page address to a virtual address.
262 *
263 * @returns VBox status code.
264 * @param pVM The cross context VM structure.
265 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
266 * @param GCPhys The GC physical address to map to a virtual one.
267 * @param ppv Where to store the virtual address. No need to cast this.
268 *
269 * @remark Use with care as we don't have so much dynamic mapping space in
270 * ring-0 on 32-bit darwin and in RC.
271 * @remark There is no need to assert on the result.
272 */
273#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
274# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
276#else
277# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
278 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
279#endif
280
281/** @def PGM_GCPHYS_2_PTR
282 * Maps a GC physical page address to a virtual address.
283 *
284 * @returns VBox status code.
285 * @param pVM The cross context VM structure.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark Use with care as we don't have so much dynamic mapping space in
290 * ring-0 on 32-bit darwin and in RC.
291 * @remark There is no need to assert on the result.
292 */
293#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
294
295/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
296 * Maps a GC physical page address to a virtual address.
297 *
298 * @returns VBox status code.
299 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
300 * @param GCPhys The GC physical address to map to a virtual one.
301 * @param ppv Where to store the virtual address. No need to cast this.
302 *
303 * @remark Use with care as we don't have so much dynamic mapping space in
304 * ring-0 on 32-bit darwin and in RC.
305 * @remark There is no need to assert on the result.
306 */
307#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
308
309/** @def PGM_GCPHYS_2_PTR_EX
310 * Maps a unaligned GC physical page address to a virtual address.
311 *
312 * @returns VBox status code.
313 * @param pVM The cross context VM structure.
314 * @param GCPhys The GC physical address to map to a virtual one.
315 * @param ppv Where to store the virtual address. No need to cast this.
316 *
317 * @remark Use with care as we don't have so much dynamic mapping space in
318 * ring-0 on 32-bit darwin and in RC.
319 * @remark There is no need to assert on the result.
320 */
321#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
324#else
325# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327#endif
328
329/** @def PGM_DYNMAP_UNUSED_HINT
330 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
331 * is no longer used.
332 *
333 * For best effect only apply this to the page that was mapped most recently.
334 *
335 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
336 * @param pvPage The pool page.
337 */
338#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
339# ifdef LOG_ENABLED
340# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
341# else
342# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
343# endif
344#else
345# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
346#endif
347
348/** @def PGM_DYNMAP_UNUSED_HINT_VM
349 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
350 * is no longer used.
351 *
352 * For best effect only apply this to the page that was mapped most recently.
353 *
354 * @param pVM The cross context VM structure.
355 * @param pvPage The pool page.
356 */
357#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
358
359
360/** @def PGM_INVL_PG
361 * Invalidates a page.
362 *
363 * @param pVCpu The cross context virtual CPU structure.
364 * @param GCVirt The virtual address of the page to invalidate.
365 */
366#ifdef IN_RC
367# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
368#elif defined(IN_RING0)
369# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370#else
371# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
372#endif
373
374/** @def PGM_INVL_PG_ALL_VCPU
375 * Invalidates a page on all VCPUs
376 *
377 * @param pVM The cross context VM structure.
378 * @param GCVirt The virtual address of the page to invalidate.
379 */
380#ifdef IN_RC
381# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
382#elif defined(IN_RING0)
383# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384#else
385# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
386#endif
387
388/** @def PGM_INVL_BIG_PG
389 * Invalidates a 4MB page directory entry.
390 *
391 * @param pVCpu The cross context virtual CPU structure.
392 * @param GCVirt The virtual address within the page directory to invalidate.
393 */
394#ifdef IN_RC
395# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
396#elif defined(IN_RING0)
397# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398#else
399# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
400#endif
401
402/** @def PGM_INVL_VCPU_TLBS()
403 * Invalidates the TLBs of the specified VCPU
404 *
405 * @param pVCpu The cross context virtual CPU structure.
406 */
407#ifdef IN_RC
408# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
409#elif defined(IN_RING0)
410# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411#else
412# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
413#endif
414
415/** @def PGM_INVL_ALL_VCPU_TLBS()
416 * Invalidates the TLBs of all VCPUs
417 *
418 * @param pVM The cross context VM structure.
419 */
420#ifdef IN_RC
421# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
422#elif defined(IN_RING0)
423# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424#else
425# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
426#endif
427
428
429/** @name Safer Shadow PAE PT/PTE
430 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
431 * present.
432 *
433 * @{
434 */
435#if 1
436/**
437 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
438 * invalid entries for present.
439 * @sa X86PTEPAE.
440 */
441typedef union PGMSHWPTEPAE
442{
443 /** Unsigned integer view */
444 X86PGPAEUINT uCareful;
445 /* Not other views. */
446} PGMSHWPTEPAE;
447
448# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
449# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
450# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
451# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
452# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
453# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
454# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
455# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
456# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
457# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
458# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
459# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
460# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
461# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
462# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
463# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
464
465/**
466 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
467 * invalid entries for present.
468 * @sa X86PTPAE.
469 */
470typedef struct PGMSHWPTPAE
471{
472 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
473} PGMSHWPTPAE;
474
475#else
476typedef X86PTEPAE PGMSHWPTEPAE;
477typedef X86PTPAE PGMSHWPTPAE;
478# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
479# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
480# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
481# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
482# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
483# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
484# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
485# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
486# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
487# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
488# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
489# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
490# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
491# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
492# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
493# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
494
495#endif
496
497/** Pointer to a shadow PAE PTE. */
498typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
499/** Pointer to a const shadow PAE PTE. */
500typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
501
502/** Pointer to a shadow PAE page table. */
503typedef PGMSHWPTPAE *PPGMSHWPTPAE;
504/** Pointer to a const shadow PAE page table. */
505typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
506/** @} */
507
508
509/** Size of the GCPtrConflict array in PGMMAPPING.
510 * @remarks Must be a power of two. */
511#define PGMMAPPING_CONFLICT_MAX 8
512
513/**
514 * Structure for tracking GC Mappings.
515 *
516 * This structure is used by linked list in both GC and HC.
517 */
518typedef struct PGMMAPPING
519{
520 /** Pointer to next entry. */
521 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522 /** Pointer to next entry. */
523 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524 /** Pointer to next entry. */
525 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
526 /** Indicate whether this entry is finalized. */
527 bool fFinalized;
528 /** Start Virtual address. */
529 RTGCPTR GCPtr;
530 /** Last Virtual address (inclusive). */
531 RTGCPTR GCPtrLast;
532 /** Range size (bytes). */
533 RTGCPTR cb;
534 /** Pointer to relocation callback function. */
535 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
536 /** User argument to the callback. */
537 R3PTRTYPE(void *) pvUser;
538 /** Mapping description / name. For easing debugging. */
539 R3PTRTYPE(const char *) pszDesc;
540 /** Last 8 addresses that caused conflicts. */
541 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
542 /** Number of conflicts for this hypervisor mapping. */
543 uint32_t cConflicts;
544 /** Number of page tables. */
545 uint32_t cPTs;
546
547 /** Array of page table mapping data. Each entry
548 * describes one page table. The array can be longer
549 * than the declared length.
550 */
551 struct
552 {
553 /** The HC physical address of the page table. */
554 RTHCPHYS HCPhysPT;
555 /** The HC physical address of the first PAE page table. */
556 RTHCPHYS HCPhysPaePT0;
557 /** The HC physical address of the second PAE page table. */
558 RTHCPHYS HCPhysPaePT1;
559 /** The HC virtual address of the 32-bit page table. */
560 R3PTRTYPE(PX86PT) pPTR3;
561 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
562 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
563 /** The RC virtual address of the 32-bit page table. */
564 RCPTRTYPE(PX86PT) pPTRC;
565 /** The RC virtual address of the two PAE page table. */
566 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
567 /** The R0 virtual address of the 32-bit page table. */
568 R0PTRTYPE(PX86PT) pPTR0;
569 /** The R0 virtual address of the two PAE page table. */
570 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571 } aPTs[1];
572} PGMMAPPING;
573/** Pointer to structure for tracking GC Mappings. */
574typedef struct PGMMAPPING *PPGMMAPPING;
575
576
577/**
578 * Physical page access handler type registration.
579 */
580typedef struct PGMPHYSHANDLERTYPEINT
581{
582 /** Number of references. */
583 uint32_t volatile cRefs;
584 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
585 uint32_t u32Magic;
586 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
587 RTLISTOFF32NODE ListNode;
588 /** The kind of accesses we're handling. */
589 PGMPHYSHANDLERKIND enmKind;
590 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
591 uint32_t uState;
592 /** Pointer to RC callback function. */
593 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
594 /** Pointer to RC callback function for \#PFs. */
595 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
596 /** Pointer to R3 callback function. */
597 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
598 /** Pointer to R0 callback function. */
599 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
600 /** Pointer to R0 callback function for \#PFs. */
601 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
602 /** Description / Name. For easing debugging. */
603 R3PTRTYPE(const char *) pszDesc;
604} PGMPHYSHANDLERTYPEINT;
605/** Pointer to a physical access handler type registration. */
606typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
607/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
608#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
609/** Magic value for the physical handler callbacks. */
610#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
611
612/**
613 * Converts a handle to a pointer.
614 * @returns PPGMPHYSHANDLERTYPEINT
615 * @param a_pVM The cross context VM structure.
616 * @param a_hType Physical access handler type handle.
617 */
618#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
619
620
621/**
622 * Physical page access handler structure.
623 *
624 * This is used to keep track of physical address ranges
625 * which are being monitored in some kind of way.
626 */
627typedef struct PGMPHYSHANDLER
628{
629 AVLROGCPHYSNODECORE Core;
630 /** Number of pages to update. */
631 uint32_t cPages;
632 /** Set if we have pages that have been aliased. */
633 uint32_t cAliasedPages;
634 /** Set if we have pages that have temporarily been disabled. */
635 uint32_t cTmpOffPages;
636 /** Registered handler type handle (heap offset). */
637 PGMPHYSHANDLERTYPE hType;
638 /** User argument for RC handlers. */
639 RCPTRTYPE(void *) pvUserRC;
640#if HC_ARCH_BITS == 64
641 RTRCPTR Padding0; /**< Explicit alignment padding. */
642#endif
643 /** User argument for R3 handlers. */
644 R3PTRTYPE(void *) pvUserR3;
645 /** User argument for R0 handlers. */
646 R0PTRTYPE(void *) pvUserR0;
647 /** Description / Name. For easing debugging. */
648 R3PTRTYPE(const char *) pszDesc;
649#ifdef VBOX_WITH_STATISTICS
650 /** Profiling of this handler. */
651 STAMPROFILE Stat;
652#endif
653} PGMPHYSHANDLER;
654/** Pointer to a physical page access handler structure. */
655typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
656
657/**
658 * Gets the type record for a physical handler (no reference added).
659 * @returns PPGMPHYSHANDLERTYPEINT
660 * @param a_pVM The cross context VM structure.
661 * @param a_pPhysHandler Pointer to the physical handler structure
662 * (PGMPHYSHANDLER).
663 */
664#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
665
666
667#ifdef VBOX_WITH_RAW_MODE
668
669/**
670 * Cache node for the physical addresses covered by a virtual handler.
671 */
672typedef struct PGMPHYS2VIRTHANDLER
673{
674 /** Core node for the tree based on physical ranges. */
675 AVLROGCPHYSNODECORE Core;
676 /** Offset from this struct to the PGMVIRTHANDLER structure. */
677 int32_t offVirtHandler;
678 /** Offset of the next alias relative to this one.
679 * Bit 0 is used for indicating whether we're in the tree.
680 * Bit 1 is used for indicating that we're the head node.
681 */
682 int32_t offNextAlias;
683} PGMPHYS2VIRTHANDLER;
684/** Pointer to a phys to virtual handler structure. */
685typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
686
687/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
688 * node is in the tree. */
689# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
690/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
691 * node is in the head of an alias chain.
692 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
693# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
694/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
695# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
696
697
698/**
699 * Virtual page access handler type registration.
700 */
701typedef struct PGMVIRTANDLERTYPEINT
702{
703 /** Number of references. */
704 uint32_t volatile cRefs;
705 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
706 uint32_t u32Magic;
707 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
708 RTLISTOFF32NODE ListNode;
709 /** The kind of accesses we're handling. */
710 PGMVIRTHANDLERKIND enmKind;
711 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
712 uint32_t uState;
713 /** Whether the pvUserRC argument should be automatically relocated or not. */
714 bool fRelocUserRC;
715 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
716 /** Pointer to RC callback function. */
717 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
718 /** Pointer to RC callback function for \#PFs. */
719 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
720 /** Pointer to the R3 callback function for invalidation. */
721 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
722 /** Pointer to R3 callback function. */
723 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
724 /** Description / Name. For easing debugging. */
725 R3PTRTYPE(const char *) pszDesc;
726} PGMVIRTHANDLERTYPEINT;
727/** Pointer to a virtual access handler type registration. */
728typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
729/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
730# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
731/** Magic value for the virtual handler callbacks. */
732# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
733
734/**
735 * Converts a handle to a pointer.
736 * @returns PPGMVIRTHANDLERTYPEINT
737 * @param a_pVM The cross context VM structure.
738 * @param a_hType Vitual access handler type handle.
739 */
740# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
741
742
743/**
744 * Virtual page access handler structure.
745 *
746 * This is used to keep track of virtual address ranges
747 * which are being monitored in some kind of way.
748 */
749typedef struct PGMVIRTHANDLER
750{
751 /** Core node for the tree based on virtual ranges. */
752 AVLROGCPTRNODECORE Core;
753 /** Size of the range (in bytes). */
754 uint32_t cb;
755 /** Number of cache pages. */
756 uint32_t cPages;
757 /** Registered handler type handle (heap offset). */
758 PGMVIRTHANDLERTYPE hType;
759 /** User argument for RC handlers. */
760 RCPTRTYPE(void *) pvUserRC;
761 /** User argument for R3 handlers. */
762 R3PTRTYPE(void *) pvUserR3;
763 /** Description / Name. For easing debugging. */
764 R3PTRTYPE(const char *) pszDesc;
765# ifdef VBOX_WITH_STATISTICS
766 /** Profiling of this handler. */
767 STAMPROFILE Stat;
768# endif
769 /** Array of cached physical addresses for the monitored ranged. */
770 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
771} PGMVIRTHANDLER;
772/** Pointer to a virtual page access handler structure. */
773typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
774
775/**
776 * Gets the type record for a virtual handler (no reference added).
777 * @returns PPGMVIRTHANDLERTYPEINT
778 * @param a_pVM The cross context VM structure.
779 * @param a_pVirtHandler Pointer to the virtual handler structure
780 * (PGMVIRTHANDLER).
781 */
782# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
783
784#endif /* VBOX_WITH_RAW_MODE */
785
786
787/**
788 * A Physical Guest Page tracking structure.
789 *
790 * The format of this structure is complicated because we have to fit a lot
791 * of information into as few bits as possible. The format is also subject
792 * to change (there is one coming up soon). Which means that for we'll be
793 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
794 * accesses to the structure.
795 */
796typedef union PGMPAGE
797{
798 /** Structured view. */
799 struct
800 {
801 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
802 uint64_t u2HandlerPhysStateY : 2;
803 /** 3:2 - Paging structure needed to map the page
804 * (PGM_PAGE_PDE_TYPE_*). */
805 uint64_t u2PDETypeY : 2;
806 /** 4 - Indicator of dirty page for fault tolerance tracking. */
807 uint64_t fFTDirtyY : 1;
808 /** 5 - Flag indicating that a write monitored page was written to
809 * when set. */
810 uint64_t fWrittenToY : 1;
811 /** 7:6 - Unused. */
812 uint64_t u2Unused0 : 2;
813 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
814 uint64_t u2HandlerVirtStateY : 2;
815 /** 11:10 - NEM state bits. */
816 uint64_t u2NemStateY : 2;
817 /** 12:48 - The host physical frame number (shift left to get the
818 * address). */
819 uint64_t HCPhysFN : 36;
820 /** 50:48 - The page state. */
821 uint64_t uStateY : 3;
822 /** 51:53 - The page type (PGMPAGETYPE). */
823 uint64_t uTypeY : 3;
824 /** 63:54 - PTE index for usage tracking (page pool). */
825 uint64_t u10PteIdx : 10;
826
827 /** The GMM page ID.
828 * @remarks In the current implementation, MMIO2 and pages aliased to
829 * MMIO2 pages will be exploiting this field to calculate the
830 * ring-3 mapping address corresponding to the page.
831 * Later we may consider including MMIO2 management into GMM. */
832 uint32_t idPage;
833 /** Usage tracking (page pool). */
834 uint16_t u16TrackingY;
835 /** The number of read locks on this page. */
836 uint8_t cReadLocksY;
837 /** The number of write locks on this page. */
838 uint8_t cWriteLocksY;
839 } s;
840
841 /** 64-bit integer view. */
842 uint64_t au64[2];
843 /** 16-bit view. */
844 uint32_t au32[4];
845 /** 16-bit view. */
846 uint16_t au16[8];
847 /** 8-bit view. */
848 uint8_t au8[16];
849} PGMPAGE;
850AssertCompileSize(PGMPAGE, 16);
851/** Pointer to a physical guest page. */
852typedef PGMPAGE *PPGMPAGE;
853/** Pointer to a const physical guest page. */
854typedef const PGMPAGE *PCPGMPAGE;
855/** Pointer to a physical guest page pointer. */
856typedef PPGMPAGE *PPPGMPAGE;
857
858
859/**
860 * Clears the page structure.
861 * @param a_pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_CLEAR(a_pPage) \
864 do { \
865 (a_pPage)->au64[0] = 0; \
866 (a_pPage)->au64[1] = 0; \
867 } while (0)
868
869/**
870 * Initializes the page structure.
871 * @param a_pPage Pointer to the physical guest page tracking structure.
872 * @param a_HCPhys The host physical address of the page.
873 * @param a_idPage The (GMM) page ID of the page.
874 * @param a_uType The page type (PGMPAGETYPE).
875 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
876 */
877#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
878 do { \
879 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
880 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
881 (a_pPage)->au64[0] = SetHCPhysTmp; \
882 (a_pPage)->au64[1] = 0; \
883 (a_pPage)->s.idPage = (a_idPage); \
884 (a_pPage)->s.uStateY = (a_uState); \
885 (a_pPage)->s.uTypeY = (a_uType); \
886 } while (0)
887
888/**
889 * Initializes the page structure of a ZERO page.
890 * @param a_pPage Pointer to the physical guest page tracking structure.
891 * @param a_pVM The VM handle (for getting the zero page address).
892 * @param a_uType The page type (PGMPAGETYPE).
893 */
894#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
895 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
896
897
898/** @name The Page state, PGMPAGE::uStateY.
899 * @{ */
900/** The zero page.
901 * This is a per-VM page that's never ever mapped writable. */
902#define PGM_PAGE_STATE_ZERO 0U
903/** A allocated page.
904 * This is a per-VM page allocated from the page pool (or wherever
905 * we get MMIO2 pages from if the type is MMIO2).
906 */
907#define PGM_PAGE_STATE_ALLOCATED 1U
908/** A allocated page that's being monitored for writes.
909 * The shadow page table mappings are read-only. When a write occurs, the
910 * fWrittenTo member is set, the page remapped as read-write and the state
911 * moved back to allocated. */
912#define PGM_PAGE_STATE_WRITE_MONITORED 2U
913/** The page is shared, aka. copy-on-write.
914 * This is a page that's shared with other VMs. */
915#define PGM_PAGE_STATE_SHARED 3U
916/** The page is ballooned, so no longer available for this VM. */
917#define PGM_PAGE_STATE_BALLOONED 4U
918/** @} */
919
920
921/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
922#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
923# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
924#else
925# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
926#endif
927
928/**
929 * Gets the page state.
930 * @returns page state (PGM_PAGE_STATE_*).
931 * @param a_pPage Pointer to the physical guest page tracking structure.
932 *
933 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
934 * builds.
935 */
936#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
937#if defined(__GNUC__) && defined(VBOX_STRICT)
938# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
939#else
940# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
941#endif
942
943/**
944 * Sets the page state.
945 * @param a_pVM The VM handle, only used for lock ownership assertions.
946 * @param a_pPage Pointer to the physical guest page tracking structure.
947 * @param a_uState The new page state.
948 */
949#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
950 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
951
952
953/**
954 * Gets the host physical address of the guest page.
955 * @returns host physical address (RTHCPHYS).
956 * @param a_pPage Pointer to the physical guest page tracking structure.
957 *
958 * @remarks In strict builds on gcc platforms, this macro will make some ugly
959 * assumption about a valid pVM variable/parameter being in the
960 * current context. It will use this pVM variable to assert that the
961 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
962 * pVM is not around.
963 */
964#if 0
965# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
966# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
967#else
968# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
969# if defined(__GNUC__) && defined(VBOX_STRICT)
970# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
971# else
972# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
973# endif
974#endif
975
976/**
977 * Sets the host physical address of the guest page.
978 *
979 * @param a_pVM The VM handle, only used for lock ownership assertions.
980 * @param a_pPage Pointer to the physical guest page tracking structure.
981 * @param a_HCPhys The new host physical address.
982 */
983#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
984 do { \
985 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
986 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
987 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
988 PGM_PAGE_ASSERT_LOCK(a_pVM); \
989 } while (0)
990
991/**
992 * Get the Page ID.
993 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
994 * @param a_pPage Pointer to the physical guest page tracking structure.
995 */
996#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
997
998/**
999 * Sets the Page ID.
1000 * @param a_pVM The VM handle, only used for lock ownership assertions.
1001 * @param a_pPage Pointer to the physical guest page tracking structure.
1002 * @param a_idPage The new page ID.
1003 */
1004#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1005 do { \
1006 (a_pPage)->s.idPage = (a_idPage); \
1007 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1008 } while (0)
1009
1010/**
1011 * Get the Chunk ID.
1012 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1013 * @param a_pPage Pointer to the physical guest page tracking structure.
1014 */
1015#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1016
1017/**
1018 * Get the index of the page within the allocation chunk.
1019 * @returns The page index.
1020 * @param a_pPage Pointer to the physical guest page tracking structure.
1021 */
1022#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1023
1024/**
1025 * Gets the page type.
1026 * @returns The page type.
1027 * @param a_pPage Pointer to the physical guest page tracking structure.
1028 *
1029 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1030 * builds.
1031 */
1032#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1033#if defined(__GNUC__) && defined(VBOX_STRICT)
1034# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1035#else
1036# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1037#endif
1038
1039/**
1040 * Sets the page type.
1041 *
1042 * @param a_pVM The VM handle, only used for lock ownership assertions.
1043 * @param a_pPage Pointer to the physical guest page tracking structure.
1044 * @param a_enmType The new page type (PGMPAGETYPE).
1045 */
1046#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1047 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1048
1049/**
1050 * Gets the page table index
1051 * @returns The page table index.
1052 * @param a_pPage Pointer to the physical guest page tracking structure.
1053 */
1054#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1055
1056/**
1057 * Sets the page table index.
1058 * @param a_pVM The VM handle, only used for lock ownership assertions.
1059 * @param a_pPage Pointer to the physical guest page tracking structure.
1060 * @param a_iPte New page table index.
1061 */
1062#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1063 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1064
1065/**
1066 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1067 * @returns true/false.
1068 * @param a_pPage Pointer to the physical guest page tracking structure.
1069 */
1070#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1071
1072/**
1073 * Checks if the page is marked for MMIO, including both aliases.
1074 * @returns true/false.
1075 * @param a_pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1078 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1079 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1080 )
1081
1082/**
1083 * Checks if the page is marked for MMIO, including special aliases.
1084 * @returns true/false.
1085 * @param a_pPage Pointer to the physical guest page tracking structure.
1086 */
1087#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1088 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1089
1090/**
1091 * Checks if the page is a special aliased MMIO page.
1092 * @returns true/false.
1093 * @param a_pPage Pointer to the physical guest page tracking structure.
1094 */
1095#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1096
1097/**
1098 * Checks if the page is backed by the ZERO page.
1099 * @returns true/false.
1100 * @param a_pPage Pointer to the physical guest page tracking structure.
1101 */
1102#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1103
1104/**
1105 * Checks if the page is backed by a SHARED page.
1106 * @returns true/false.
1107 * @param a_pPage Pointer to the physical guest page tracking structure.
1108 */
1109#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1110
1111/**
1112 * Checks if the page is ballooned.
1113 * @returns true/false.
1114 * @param a_pPage Pointer to the physical guest page tracking structure.
1115 */
1116#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1117
1118/**
1119 * Checks if the page is allocated.
1120 * @returns true/false.
1121 * @param a_pPage Pointer to the physical guest page tracking structure.
1122 */
1123#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1124
1125/**
1126 * Marks the page as written to (for GMM change monitoring).
1127 * @param a_pVM The VM handle, only used for lock ownership assertions.
1128 * @param a_pPage Pointer to the physical guest page tracking structure.
1129 */
1130#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1131 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1132
1133/**
1134 * Clears the written-to indicator.
1135 * @param a_pVM The VM handle, only used for lock ownership assertions.
1136 * @param a_pPage Pointer to the physical guest page tracking structure.
1137 */
1138#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1139 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1140
1141/**
1142 * Checks if the page was marked as written-to.
1143 * @returns true/false.
1144 * @param a_pPage Pointer to the physical guest page tracking structure.
1145 */
1146#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1147
1148/**
1149 * Marks the page as dirty for FTM
1150 * @param a_pPage Pointer to the physical guest page tracking structure.
1151 */
1152#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1153
1154/**
1155 * Clears the FTM dirty indicator
1156 * @param a_pPage Pointer to the physical guest page tracking structure.
1157 */
1158#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1159
1160/**
1161 * Checks if the page was marked as dirty for FTM
1162 * @returns true/false.
1163 * @param a_pPage Pointer to the physical guest page tracking structure.
1164 */
1165#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1166
1167
1168/** @name PT usage values (PGMPAGE::u2PDEType).
1169 *
1170 * @{ */
1171/** Either as a PT or PDE. */
1172#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1173/** Must use a page table to map the range. */
1174#define PGM_PAGE_PDE_TYPE_PT 1
1175/** Can use a page directory entry to map the continuous range. */
1176#define PGM_PAGE_PDE_TYPE_PDE 2
1177/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1178#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1179/** @} */
1180
1181/**
1182 * Set the PDE type of the page
1183 * @param a_pVM The VM handle, only used for lock ownership assertions.
1184 * @param a_pPage Pointer to the physical guest page tracking structure.
1185 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1186 */
1187#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1188 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1189
1190/**
1191 * Checks if the page was marked being part of a large page
1192 * @returns true/false.
1193 * @param a_pPage Pointer to the physical guest page tracking structure.
1194 */
1195#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1196
1197/** Enabled optimized access handler tests.
1198 * These optimizations makes ASSUMPTIONS about the state values and the s1
1199 * layout. When enabled, the compiler should normally generate more compact
1200 * code.
1201 */
1202#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1203
1204/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1205 *
1206 * @remarks The values are assigned in order of priority, so we can calculate
1207 * the correct state for a page with different handlers installed.
1208 * @{ */
1209/** No handler installed. */
1210#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1211/** Monitoring is temporarily disabled. */
1212#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1213/** Write access is monitored. */
1214#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1215/** All access is monitored. */
1216#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1217/** @} */
1218
1219/**
1220 * Gets the physical access handler state of a page.
1221 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1222 * @param a_pPage Pointer to the physical guest page tracking structure.
1223 */
1224#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1225
1226/**
1227 * Sets the physical access handler state of a page.
1228 * @param a_pPage Pointer to the physical guest page tracking structure.
1229 * @param a_uState The new state value.
1230 */
1231#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1232 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1233
1234/**
1235 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1236 * @returns true/false
1237 * @param a_pPage Pointer to the physical guest page tracking structure.
1238 */
1239#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1240 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1241
1242/**
1243 * Checks if the page has any active physical access handlers.
1244 * @returns true/false
1245 * @param a_pPage Pointer to the physical guest page tracking structure.
1246 */
1247#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1248 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1249
1250
1251/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1252 *
1253 * @remarks The values are assigned in order of priority, so we can calculate
1254 * the correct state for a page with different handlers installed.
1255 * @{ */
1256/** No handler installed. */
1257#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1258/* 1 is reserved so the lineup is identical with the physical ones. */
1259/** Write access is monitored. */
1260#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1261/** All access is monitored. */
1262#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1263/** @} */
1264
1265/**
1266 * Gets the virtual access handler state of a page.
1267 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1268 * @param a_pPage Pointer to the physical guest page tracking structure.
1269 */
1270#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1271
1272/**
1273 * Sets the virtual access handler state of a page.
1274 * @param a_pPage Pointer to the physical guest page tracking structure.
1275 * @param a_uState The new state value.
1276 */
1277#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1278 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1279
1280/**
1281 * Checks if the page has any virtual access handlers.
1282 * @returns true/false
1283 * @param a_pPage Pointer to the physical guest page tracking structure.
1284 */
1285#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1286 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1287
1288/**
1289 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1290 * virtual handlers.
1291 * @returns true/false
1292 * @param a_pPage Pointer to the physical guest page tracking structure.
1293 */
1294#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1295 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1296
1297
1298/**
1299 * Checks if the page has any access handlers, including temporarily disabled ones.
1300 * @returns true/false
1301 * @param a_pPage Pointer to the physical guest page tracking structure.
1302 */
1303#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1304# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1305 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1306#else
1307# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1308 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1309 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1310#endif
1311
1312/**
1313 * Checks if the page has any active access handlers.
1314 * @returns true/false
1315 * @param a_pPage Pointer to the physical guest page tracking structure.
1316 */
1317#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1318# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1319 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1320#else
1321# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1322 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1323 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1324#endif
1325
1326/**
1327 * Checks if the page has any active access handlers catching all accesses.
1328 * @returns true/false
1329 * @param a_pPage Pointer to the physical guest page tracking structure.
1330 */
1331#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1332# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1333 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1334 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1335#else
1336# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1337 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1338 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1339#endif
1340
1341
1342/** @def PGM_PAGE_GET_TRACKING
1343 * Gets the packed shadow page pool tracking data associated with a guest page.
1344 * @returns uint16_t containing the data.
1345 * @param a_pPage Pointer to the physical guest page tracking structure.
1346 */
1347#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1348#if defined(__GNUC__) && defined(VBOX_STRICT)
1349# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1350#else
1351# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1352#endif
1353
1354/** @def PGM_PAGE_SET_TRACKING
1355 * Sets the packed shadow page pool tracking data associated with a guest page.
1356 * @param a_pVM The VM handle, only used for lock ownership assertions.
1357 * @param a_pPage Pointer to the physical guest page tracking structure.
1358 * @param a_u16TrackingData The tracking data to store.
1359 */
1360#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1361 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1362
1363/** @def PGM_PAGE_GET_TD_CREFS
1364 * Gets the @a cRefs tracking data member.
1365 * @returns cRefs.
1366 * @param a_pPage Pointer to the physical guest page tracking structure.
1367 */
1368#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1369 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1370#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1371 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1372
1373/** @def PGM_PAGE_GET_TD_IDX
1374 * Gets the @a idx tracking data member.
1375 * @returns idx.
1376 * @param a_pPage Pointer to the physical guest page tracking structure.
1377 */
1378#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1379 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1380#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1381 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1382
1383
1384/** Max number of locks on a page. */
1385#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1386
1387/** Get the read lock count.
1388 * @returns count.
1389 * @param a_pPage Pointer to the physical guest page tracking structure.
1390 */
1391#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1392
1393/** Get the write lock count.
1394 * @returns count.
1395 * @param a_pPage Pointer to the physical guest page tracking structure.
1396 */
1397#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1398
1399/** Decrement the read lock counter.
1400 * @param a_pPage Pointer to the physical guest page tracking structure.
1401 */
1402#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1403
1404/** Decrement the write lock counter.
1405 * @param a_pPage Pointer to the physical guest page tracking structure.
1406 */
1407#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1408
1409/** Increment the read lock counter.
1410 * @param a_pPage Pointer to the physical guest page tracking structure.
1411 */
1412#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1413
1414/** Increment the write lock counter.
1415 * @param a_pPage Pointer to the physical guest page tracking structure.
1416 */
1417#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1418
1419
1420/** Gets the NEM state.
1421 * @returns NEM state value (two bits).
1422 * @param a_pPage Pointer to the physical guest page tracking structure.
1423 */
1424#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1425
1426/** Sets the NEM state.
1427 * @param a_pPage Pointer to the physical guest page tracking structure.
1428 * @param a_u2State The NEM state value (specific to NEM impl.).
1429 */
1430#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1431 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1432
1433
1434#if 0
1435/** Enables sanity checking of write monitoring using CRC-32. */
1436# define PGMLIVESAVERAMPAGE_WITH_CRC32
1437#endif
1438
1439/**
1440 * Per page live save tracking data.
1441 */
1442typedef struct PGMLIVESAVERAMPAGE
1443{
1444 /** Number of times it has been dirtied. */
1445 uint32_t cDirtied : 24;
1446 /** Whether it is currently dirty. */
1447 uint32_t fDirty : 1;
1448 /** Ignore the page.
1449 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1450 * deal with these after pausing the VM and DevPCI have said it bit about
1451 * remappings. */
1452 uint32_t fIgnore : 1;
1453 /** Was a ZERO page last time around. */
1454 uint32_t fZero : 1;
1455 /** Was a SHARED page last time around. */
1456 uint32_t fShared : 1;
1457 /** Whether the page is/was write monitored in a previous pass. */
1458 uint32_t fWriteMonitored : 1;
1459 /** Whether the page is/was write monitored earlier in this pass. */
1460 uint32_t fWriteMonitoredJustNow : 1;
1461 /** Bits reserved for future use. */
1462 uint32_t u2Reserved : 2;
1463#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1464 /** CRC-32 for the page. This is for internal consistency checks. */
1465 uint32_t u32Crc;
1466#endif
1467} PGMLIVESAVERAMPAGE;
1468#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1469AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1470#else
1471AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1472#endif
1473/** Pointer to the per page live save tracking data. */
1474typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1475
1476/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1477#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1478
1479
1480/**
1481 * RAM range for GC Phys to HC Phys conversion.
1482 *
1483 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1484 * conversions too, but we'll let MM handle that for now.
1485 *
1486 * This structure is used by linked lists in both GC and HC.
1487 */
1488typedef struct PGMRAMRANGE
1489{
1490 /** Start of the range. Page aligned. */
1491 RTGCPHYS GCPhys;
1492 /** Size of the range. (Page aligned of course). */
1493 RTGCPHYS cb;
1494 /** Pointer to the next RAM range - for R3. */
1495 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1496 /** Pointer to the next RAM range - for R0. */
1497 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1498 /** Pointer to the next RAM range - for RC. */
1499 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1500 /** PGM_RAM_RANGE_FLAGS_* flags. */
1501 uint32_t fFlags;
1502 /** Last address in the range (inclusive). Page aligned (-1). */
1503 RTGCPHYS GCPhysLast;
1504 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1505 R3PTRTYPE(void *) pvR3;
1506 /** Live save per page tracking data. */
1507 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1508 /** The range description. */
1509 R3PTRTYPE(const char *) pszDesc;
1510 /** Pointer to self - R0 pointer. */
1511 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1512 /** Pointer to self - RC pointer. */
1513 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1514
1515 /** Alignment padding. */
1516 RTRCPTR Alignment0;
1517 /** Pointer to the left search three node - ring-3 context. */
1518 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1519 /** Pointer to the right search three node - ring-3 context. */
1520 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1521 /** Pointer to the left search three node - ring-0 context. */
1522 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1523 /** Pointer to the right search three node - ring-0 context. */
1524 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1525 /** Pointer to the left search three node - raw-mode context. */
1526 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1527 /** Pointer to the right search three node - raw-mode context. */
1528 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1529
1530 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1531#if HC_ARCH_BITS == 32
1532 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1533#endif
1534 /** Array of physical guest page tracking structures. */
1535 PGMPAGE aPages[1];
1536} PGMRAMRANGE;
1537/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1538typedef PGMRAMRANGE *PPGMRAMRANGE;
1539
1540/** @name PGMRAMRANGE::fFlags
1541 * @{ */
1542/** The RAM range is floating around as an independent guest mapping. */
1543#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1544/** Ad hoc RAM range for an ROM mapping. */
1545#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1546/** Ad hoc RAM range for an MMIO mapping. */
1547#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1548/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1549#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1550/** @} */
1551
1552/** Tests if a RAM range is an ad hoc one or not.
1553 * @returns true/false.
1554 * @param pRam The RAM range.
1555 */
1556#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1557 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1558
1559/** The number of entries in the RAM range TLBs (there is one for each
1560 * context). Must be a power of two. */
1561#define PGM_RAMRANGE_TLB_ENTRIES 8
1562
1563/**
1564 * Calculates the RAM range TLB index for the physical address.
1565 *
1566 * @returns RAM range TLB index.
1567 * @param a_GCPhys The guest physical address.
1568 */
1569#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1570
1571
1572
1573/**
1574 * Per page tracking structure for ROM image.
1575 *
1576 * A ROM image may have a shadow page, in which case we may have two pages
1577 * backing it. This structure contains the PGMPAGE for both while
1578 * PGMRAMRANGE have a copy of the active one. It is important that these
1579 * aren't out of sync in any regard other than page pool tracking data.
1580 */
1581typedef struct PGMROMPAGE
1582{
1583 /** The page structure for the virgin ROM page. */
1584 PGMPAGE Virgin;
1585 /** The page structure for the shadow RAM page. */
1586 PGMPAGE Shadow;
1587 /** The current protection setting. */
1588 PGMROMPROT enmProt;
1589 /** Live save status information. Makes use of unused alignment space. */
1590 struct
1591 {
1592 /** The previous protection value. */
1593 uint8_t u8Prot;
1594 /** Written to flag set by the handler. */
1595 bool fWrittenTo;
1596 /** Whether the shadow page is dirty or not. */
1597 bool fDirty;
1598 /** Whether it was dirtied in the recently. */
1599 bool fDirtiedRecently;
1600 } LiveSave;
1601} PGMROMPAGE;
1602AssertCompileSizeAlignment(PGMROMPAGE, 8);
1603/** Pointer to a ROM page tracking structure. */
1604typedef PGMROMPAGE *PPGMROMPAGE;
1605
1606
1607/**
1608 * A registered ROM image.
1609 *
1610 * This is needed to keep track of ROM image since they generally intrude
1611 * into a PGMRAMRANGE. It also keeps track of additional info like the
1612 * two page sets (read-only virgin and read-write shadow), the current
1613 * state of each page.
1614 *
1615 * Because access handlers cannot easily be executed in a different
1616 * context, the ROM ranges needs to be accessible and in all contexts.
1617 */
1618typedef struct PGMROMRANGE
1619{
1620 /** Pointer to the next range - R3. */
1621 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1622 /** Pointer to the next range - R0. */
1623 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1624 /** Pointer to the next range - RC. */
1625 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1626 /** Pointer alignment */
1627 RTRCPTR RCPtrAlignment;
1628 /** Address of the range. */
1629 RTGCPHYS GCPhys;
1630 /** Address of the last byte in the range. */
1631 RTGCPHYS GCPhysLast;
1632 /** Size of the range. */
1633 RTGCPHYS cb;
1634 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1635 uint32_t fFlags;
1636 /** The saved state range ID. */
1637 uint8_t idSavedState;
1638 /** Alignment padding. */
1639 uint8_t au8Alignment[3];
1640 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1641 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1642 /** The size bits pvOriginal points to. */
1643 uint32_t cbOriginal;
1644 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1645 * This is used for strictness checks. */
1646 R3PTRTYPE(const void *) pvOriginal;
1647 /** The ROM description. */
1648 R3PTRTYPE(const char *) pszDesc;
1649 /** The per page tracking structures. */
1650 PGMROMPAGE aPages[1];
1651} PGMROMRANGE;
1652/** Pointer to a ROM range. */
1653typedef PGMROMRANGE *PPGMROMRANGE;
1654
1655
1656/**
1657 * Live save per page data for an MMIO2 page.
1658 *
1659 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1660 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1661 * CRC-32 for detecting changes as well as special handling of zero pages. This
1662 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1663 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1664 * because of speed (2.5x and 6x slower).)
1665 *
1666 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1667 * save but normally is disabled. Since we can write monitor guest
1668 * accesses on our own, we only need this for host accesses. Shouldn't be
1669 * too difficult for DevVGA, VMMDev might be doable, the planned
1670 * networking fun will be fun since it involves ring-0.
1671 */
1672typedef struct PGMLIVESAVEMMIO2PAGE
1673{
1674 /** Set if the page is considered dirty. */
1675 bool fDirty;
1676 /** The number of scans this page has remained unchanged for.
1677 * Only updated for dirty pages. */
1678 uint8_t cUnchangedScans;
1679 /** Whether this page was zero at the last scan. */
1680 bool fZero;
1681 /** Alignment padding. */
1682 bool fReserved;
1683 /** CRC-32 for the first half of the page.
1684 * This is used together with u32CrcH2 to quickly detect changes in the page
1685 * during the non-final passes. */
1686 uint32_t u32CrcH1;
1687 /** CRC-32 for the second half of the page. */
1688 uint32_t u32CrcH2;
1689 /** SHA-1 for the saved page.
1690 * This is used in the final pass to skip pages without changes. */
1691 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1692} PGMLIVESAVEMMIO2PAGE;
1693/** Pointer to a live save status data for an MMIO2 page. */
1694typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1695
1696/**
1697 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1698 *
1699 * There are a few reason why we need to keep track of these registrations. One
1700 * of them is the deregistration & cleanup stuff, while another is that the
1701 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1702 * range list.
1703 *
1704 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1705 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1706 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1707 * overlap we will free all the existing RAM pages and put in the ram range
1708 * pages instead.
1709 */
1710typedef struct PGMREGMMIORANGE
1711{
1712 /** The owner of the range. (a device) */
1713 PPDMDEVINSR3 pDevInsR3;
1714 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1715 RTR3PTR pvR3;
1716 /** Pointer to the next range - R3. */
1717 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1718 /** Flags (PGMREGMMIORANGE_F_XXX). */
1719 uint16_t fFlags;
1720 /** The sub device number (internal PCI config (CFGM) number). */
1721 uint8_t iSubDev;
1722 /** The PCI region number. */
1723 uint8_t iRegion;
1724 /** The saved state range ID. */
1725 uint8_t idSavedState;
1726 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1727 uint8_t idMmio2;
1728 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1729 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1730 /** The real size.
1731 * This may be larger than indicated by RamRange.cb if the range has been
1732 * reduced during saved state loading. */
1733 RTGCPHYS cbReal;
1734 /** Pointer to the physical handler for MMIO. */
1735 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1736 /** Live save per page tracking data for MMIO2. */
1737 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1738 /** The associated RAM range. */
1739 PGMRAMRANGE RamRange;
1740} PGMREGMMIORANGE;
1741AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1742/** Pointer to a MMIO2 or pre-registered MMIO range. */
1743typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1744
1745/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1746 * @{ */
1747/** Set if it's an MMIO2 range. */
1748#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1749/** Set if this is the first chunk in the MMIO2 range. */
1750#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1751/** Set if this is the last chunk in the MMIO2 range. */
1752#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1753/** Set if the whole range is mapped. */
1754#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1755/** Set if it's overlapping, clear if not. */
1756#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1757/** @} */
1758
1759
1760/** @name Internal MMIO2 constants.
1761 * @{ */
1762/** The maximum number of MMIO2 ranges. */
1763#define PGM_MMIO2_MAX_RANGES 8
1764/** The maximum number of pages in a MMIO2 range. */
1765#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1766/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1767#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1768/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1769#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1770/** Gets the MMIO2 page index from an MMIO2 page ID. */
1771#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1772/** @} */
1773
1774
1775
1776/**
1777 * PGMPhysRead/Write cache entry
1778 */
1779typedef struct PGMPHYSCACHEENTRY
1780{
1781 /** R3 pointer to physical page. */
1782 R3PTRTYPE(uint8_t *) pbR3;
1783 /** GC Physical address for cache entry */
1784 RTGCPHYS GCPhys;
1785#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1786 RTGCPHYS u32Padding0; /**< alignment padding. */
1787#endif
1788} PGMPHYSCACHEENTRY;
1789
1790/**
1791 * PGMPhysRead/Write cache to reduce REM memory access overhead
1792 */
1793typedef struct PGMPHYSCACHE
1794{
1795 /** Bitmap of valid cache entries */
1796 uint64_t aEntries;
1797 /** Cache entries */
1798 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1799} PGMPHYSCACHE;
1800
1801
1802/** Pointer to an allocation chunk ring-3 mapping. */
1803typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1804/** Pointer to an allocation chunk ring-3 mapping pointer. */
1805typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1806
1807/**
1808 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1809 *
1810 * The primary tree (Core) uses the chunk id as key.
1811 */
1812typedef struct PGMCHUNKR3MAP
1813{
1814 /** The key is the chunk id. */
1815 AVLU32NODECORE Core;
1816 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1817 * selection. */
1818 uint32_t iLastUsed;
1819 /** The current reference count. */
1820 uint32_t volatile cRefs;
1821 /** The current permanent reference count. */
1822 uint32_t volatile cPermRefs;
1823 /** The mapping address. */
1824 void *pv;
1825} PGMCHUNKR3MAP;
1826
1827/**
1828 * Allocation chunk ring-3 mapping TLB entry.
1829 */
1830typedef struct PGMCHUNKR3MAPTLBE
1831{
1832 /** The chunk id. */
1833 uint32_t volatile idChunk;
1834#if HC_ARCH_BITS == 64
1835 uint32_t u32Padding; /**< alignment padding. */
1836#endif
1837 /** The chunk map. */
1838#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1839 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1840#else
1841 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1842#endif
1843} PGMCHUNKR3MAPTLBE;
1844/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1845typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1846
1847/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1848 * @remark Must be a power of two value. */
1849#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1850
1851/**
1852 * Allocation chunk ring-3 mapping TLB.
1853 *
1854 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1855 * At first glance this might look kinda odd since AVL trees are
1856 * supposed to give the most optimal lookup times of all trees
1857 * due to their balancing. However, take a tree with 1023 nodes
1858 * in it, that's 10 levels, meaning that most searches has to go
1859 * down 9 levels before they find what they want. This isn't fast
1860 * compared to a TLB hit. There is the factor of cache misses,
1861 * and of course the problem with trees and branch prediction.
1862 * This is why we use TLBs in front of most of the trees.
1863 *
1864 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1865 * difficult when we switch to the new inlined AVL trees (from kStuff).
1866 */
1867typedef struct PGMCHUNKR3MAPTLB
1868{
1869 /** The TLB entries. */
1870 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1871} PGMCHUNKR3MAPTLB;
1872
1873/**
1874 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1875 * @returns Chunk TLB index.
1876 * @param idChunk The Chunk ID.
1877 */
1878#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1879
1880
1881/**
1882 * Ring-3 guest page mapping TLB entry.
1883 * @remarks used in ring-0 as well at the moment.
1884 */
1885typedef struct PGMPAGER3MAPTLBE
1886{
1887 /** Address of the page. */
1888 RTGCPHYS volatile GCPhys;
1889 /** The guest page. */
1890#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1891 R3PTRTYPE(PPGMPAGE) volatile pPage;
1892#else
1893 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1894#endif
1895 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1896#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1897 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1898#else
1899 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1900#endif
1901 /** The address */
1902#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1903 R3PTRTYPE(void *) volatile pv;
1904#else
1905 R3R0PTRTYPE(void *) volatile pv;
1906#endif
1907#if HC_ARCH_BITS == 32
1908 uint32_t u32Padding; /**< alignment padding. */
1909#endif
1910} PGMPAGER3MAPTLBE;
1911/** Pointer to an entry in the HC physical TLB. */
1912typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1913
1914
1915/** The number of entries in the ring-3 guest page mapping TLB.
1916 * @remarks The value must be a power of two. */
1917#define PGM_PAGER3MAPTLB_ENTRIES 256
1918
1919/**
1920 * Ring-3 guest page mapping TLB.
1921 * @remarks used in ring-0 as well at the moment.
1922 */
1923typedef struct PGMPAGER3MAPTLB
1924{
1925 /** The TLB entries. */
1926 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1927} PGMPAGER3MAPTLB;
1928/** Pointer to the ring-3 guest page mapping TLB. */
1929typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1930
1931/**
1932 * Calculates the index of the TLB entry for the specified guest page.
1933 * @returns Physical TLB index.
1934 * @param GCPhys The guest physical address.
1935 */
1936#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1937
1938
1939/**
1940 * Raw-mode context dynamic mapping cache entry.
1941 *
1942 * Because of raw-mode context being reloctable and all relocations are applied
1943 * in ring-3, this has to be defined here and be RC specific.
1944 *
1945 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1946 */
1947typedef struct PGMRCDYNMAPENTRY
1948{
1949 /** The physical address of the currently mapped page.
1950 * This is duplicate for three reasons: cache locality, cache policy of the PT
1951 * mappings and sanity checks. */
1952 RTHCPHYS HCPhys;
1953 /** Pointer to the page. */
1954 RTRCPTR pvPage;
1955 /** The number of references. */
1956 int32_t volatile cRefs;
1957 /** PTE pointer union. */
1958 struct PGMRCDYNMAPENTRY_PPTE
1959 {
1960 /** PTE pointer, 32-bit legacy version. */
1961 RCPTRTYPE(PX86PTE) pLegacy;
1962 /** PTE pointer, PAE version. */
1963 RCPTRTYPE(PX86PTEPAE) pPae;
1964 } uPte;
1965} PGMRCDYNMAPENTRY;
1966/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1967typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1968
1969
1970/**
1971 * Dynamic mapping cache for the raw-mode context.
1972 *
1973 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1974 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1975 * so that we can perform relocations from PGMR3Relocate. This has the
1976 * consequence that we must have separate ring-0 and raw-mode context versions
1977 * of this struct even if they share the basic elements.
1978 *
1979 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1980 */
1981typedef struct PGMRCDYNMAP
1982{
1983 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1984 uint32_t u32Magic;
1985 /** Array for tracking and managing the pages. */
1986 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1987 /** The cache size given as a number of pages. */
1988 uint32_t cPages;
1989 /** The current load.
1990 * This does not include guard pages. */
1991 uint32_t cLoad;
1992 /** The max load ever.
1993 * This is maintained to get trigger adding of more mapping space. */
1994 uint32_t cMaxLoad;
1995 /** The number of guard pages. */
1996 uint32_t cGuardPages;
1997 /** The number of users (protected by hInitLock). */
1998 uint32_t cUsers;
1999} PGMRCDYNMAP;
2000/** Pointer to the dynamic cache for the raw-mode context. */
2001typedef PGMRCDYNMAP *PPGMRCDYNMAP;
2002
2003
2004/**
2005 * Mapping cache usage set entry.
2006 *
2007 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
2008 * the dynamic ring-0 and (to some extent) raw-mode context mapping
2009 * cache. If it's extended to include ring-3, well, then something
2010 * will have be changed here...
2011 */
2012typedef struct PGMMAPSETENTRY
2013{
2014 /** Pointer to the page. */
2015#ifndef IN_RC
2016 RTR0PTR pvPage;
2017#else
2018 RTRCPTR pvPage;
2019# if HC_ARCH_BITS == 64
2020 uint32_t u32Alignment2;
2021# endif
2022#endif
2023 /** The mapping cache index. */
2024 uint16_t iPage;
2025 /** The number of references.
2026 * The max is UINT16_MAX - 1. */
2027 uint16_t cRefs;
2028 /** The number inlined references.
2029 * The max is UINT16_MAX - 1. */
2030 uint16_t cInlinedRefs;
2031 /** Unreferences. */
2032 uint16_t cUnrefs;
2033
2034#if HC_ARCH_BITS == 32
2035 uint32_t u32Alignment1;
2036#endif
2037 /** The physical address for this entry. */
2038 RTHCPHYS HCPhys;
2039} PGMMAPSETENTRY;
2040AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2041AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2042/** Pointer to a mapping cache usage set entry. */
2043typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2044
2045/**
2046 * Mapping cache usage set.
2047 *
2048 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2049 * done during exits / traps. The set is
2050 */
2051typedef struct PGMMAPSET
2052{
2053 /** The number of occupied entries.
2054 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2055 * dynamic mappings. */
2056 uint32_t cEntries;
2057 /** The start of the current subset.
2058 * This is UINT32_MAX if no subset is currently open. */
2059 uint32_t iSubset;
2060 /** The index of the current CPU, only valid if the set is open. */
2061 int32_t iCpu;
2062 uint32_t alignment;
2063 /** The entries. */
2064 PGMMAPSETENTRY aEntries[64];
2065 /** HCPhys -> iEntry fast lookup table.
2066 * Use PGMMAPSET_HASH for hashing.
2067 * The entries may or may not be valid, check against cEntries. */
2068 uint8_t aiHashTable[128];
2069} PGMMAPSET;
2070AssertCompileSizeAlignment(PGMMAPSET, 8);
2071/** Pointer to the mapping cache set. */
2072typedef PGMMAPSET *PPGMMAPSET;
2073
2074/** PGMMAPSET::cEntries value for a closed set. */
2075#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2076
2077/** Hash function for aiHashTable. */
2078#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2079
2080
2081/** @name Context neutral page mapper TLB.
2082 *
2083 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2084 * code is writting in a kind of context neutral way. Time will show whether
2085 * this actually makes sense or not...
2086 *
2087 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2088 * context ends up using a global mapping cache on some platforms
2089 * (darwin).
2090 *
2091 * @{ */
2092/** @typedef PPGMPAGEMAPTLB
2093 * The page mapper TLB pointer type for the current context. */
2094/** @typedef PPGMPAGEMAPTLB
2095 * The page mapper TLB entry pointer type for the current context. */
2096/** @typedef PPGMPAGEMAPTLB
2097 * The page mapper TLB entry pointer pointer type for the current context. */
2098/** @def PGM_PAGEMAPTLB_ENTRIES
2099 * The number of TLB entries in the page mapper TLB for the current context. */
2100/** @def PGM_PAGEMAPTLB_IDX
2101 * Calculate the TLB index for a guest physical address.
2102 * @returns The TLB index.
2103 * @param GCPhys The guest physical address. */
2104/** @typedef PPGMPAGEMAP
2105 * Pointer to a page mapper unit for current context. */
2106/** @typedef PPPGMPAGEMAP
2107 * Pointer to a page mapper unit pointer for current context. */
2108#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2109// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2110// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2111// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2112# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2113# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2114 typedef void * PPGMPAGEMAP;
2115 typedef void ** PPPGMPAGEMAP;
2116//#elif IN_RING0
2117// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2118// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2119// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2120//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2121//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2122// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2123// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2124#else
2125 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2126 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2127 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2128# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2129# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2130 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2131 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2132#endif
2133/** @} */
2134
2135
2136/** @name PGM Pool Indexes.
2137 * Aka. the unique shadow page identifier.
2138 * @{ */
2139/** NIL page pool IDX. */
2140#define NIL_PGMPOOL_IDX 0
2141/** The first normal index. There used to be 5 fictive pages up front, now
2142 * there is only the NIL page. */
2143#define PGMPOOL_IDX_FIRST 1
2144/** The last valid index. (inclusive, 14 bits) */
2145#define PGMPOOL_IDX_LAST 0x3fff
2146/** @} */
2147
2148/** The NIL index for the parent chain. */
2149#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2150#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2151
2152/**
2153 * Node in the chain linking a shadowed page to it's parent (user).
2154 */
2155#pragma pack(1)
2156typedef struct PGMPOOLUSER
2157{
2158 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2159 uint16_t iNext;
2160 /** The user page index. */
2161 uint16_t iUser;
2162 /** Index into the user table. */
2163 uint32_t iUserTable;
2164} PGMPOOLUSER, *PPGMPOOLUSER;
2165typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2166#pragma pack()
2167
2168
2169/** The NIL index for the phys ext chain. */
2170#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2171/** The NIL pte index for a phys ext chain slot. */
2172#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2173
2174/**
2175 * Node in the chain of physical cross reference extents.
2176 * @todo Calling this an 'extent' is not quite right, find a better name.
2177 * @todo find out the optimal size of the aidx array
2178 */
2179#pragma pack(1)
2180typedef struct PGMPOOLPHYSEXT
2181{
2182 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2183 uint16_t iNext;
2184 /** Alignment. */
2185 uint16_t u16Align;
2186 /** The user page index. */
2187 uint16_t aidx[3];
2188 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2189 uint16_t apte[3];
2190} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2191typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2192#pragma pack()
2193
2194
2195/**
2196 * The kind of page that's being shadowed.
2197 */
2198typedef enum PGMPOOLKIND
2199{
2200 /** The virtual invalid 0 entry. */
2201 PGMPOOLKIND_INVALID = 0,
2202 /** The entry is free (=unused). */
2203 PGMPOOLKIND_FREE,
2204
2205 /** Shw: 32-bit page table; Gst: no paging. */
2206 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2207 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2208 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2209 /** Shw: 32-bit page table; Gst: 4MB page. */
2210 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2211 /** Shw: PAE page table; Gst: no paging. */
2212 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2213 /** Shw: PAE page table; Gst: 32-bit page table. */
2214 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2215 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2216 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2217 /** Shw: PAE page table; Gst: PAE page table. */
2218 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2219 /** Shw: PAE page table; Gst: 2MB page. */
2220 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2221
2222 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2223 PGMPOOLKIND_32BIT_PD,
2224 /** Shw: 32-bit page directory. Gst: no paging. */
2225 PGMPOOLKIND_32BIT_PD_PHYS,
2226 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2227 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2228 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2229 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2230 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2231 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2232 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2233 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2234 /** Shw: PAE page directory; Gst: PAE page directory. */
2235 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2236 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2237 PGMPOOLKIND_PAE_PD_PHYS,
2238
2239 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2240 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2241 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2242 PGMPOOLKIND_PAE_PDPT,
2243 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2244 PGMPOOLKIND_PAE_PDPT_PHYS,
2245
2246 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2247 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2248 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2249 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2250 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2251 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2252 /** Shw: 64-bit page directory table; Gst: no paging. */
2253 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2254
2255 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2256 PGMPOOLKIND_64BIT_PML4,
2257
2258 /** Shw: EPT page directory pointer table; Gst: no paging. */
2259 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2260 /** Shw: EPT page directory table; Gst: no paging. */
2261 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2262 /** Shw: EPT page table; Gst: no paging. */
2263 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2264
2265 /** Shw: Root Nested paging table. */
2266 PGMPOOLKIND_ROOT_NESTED,
2267
2268 /** The last valid entry. */
2269 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2270} PGMPOOLKIND;
2271
2272/**
2273 * The access attributes of the page; only applies to big pages.
2274 */
2275typedef enum
2276{
2277 PGMPOOLACCESS_DONTCARE = 0,
2278 PGMPOOLACCESS_USER_RW,
2279 PGMPOOLACCESS_USER_R,
2280 PGMPOOLACCESS_USER_RW_NX,
2281 PGMPOOLACCESS_USER_R_NX,
2282 PGMPOOLACCESS_SUPERVISOR_RW,
2283 PGMPOOLACCESS_SUPERVISOR_R,
2284 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2285 PGMPOOLACCESS_SUPERVISOR_R_NX
2286} PGMPOOLACCESS;
2287
2288/**
2289 * The tracking data for a page in the pool.
2290 */
2291typedef struct PGMPOOLPAGE
2292{
2293 /** AVL node code with the (HC) physical address of this page. */
2294 AVLOHCPHYSNODECORE Core;
2295 /** Pointer to the R3 mapping of the page. */
2296#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2297 R3PTRTYPE(void *) pvPageR3;
2298#else
2299 R3R0PTRTYPE(void *) pvPageR3;
2300#endif
2301#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2302 uint32_t Alignment0;
2303#endif
2304 /** The guest physical address. */
2305 RTGCPHYS GCPhys;
2306 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2307 uint8_t enmKind;
2308 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2309 uint8_t enmAccess;
2310 /** This supplements enmKind and enmAccess */
2311 bool fA20Enabled : 1;
2312
2313 /** Used to indicate that the page is zeroed. */
2314 bool fZeroed : 1;
2315 /** Used to indicate that a PT has non-global entries. */
2316 bool fSeenNonGlobal : 1;
2317 /** Used to indicate that we're monitoring writes to the guest page. */
2318 bool fMonitored : 1;
2319 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2320 * (All pages are in the age list.) */
2321 bool fCached : 1;
2322 /** This is used by the R3 access handlers when invoked by an async thread.
2323 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2324 bool volatile fReusedFlushPending : 1;
2325 /** Used to mark the page as dirty (write monitoring is temporarily
2326 * off). */
2327 bool fDirty : 1;
2328 bool fPadding1 : 1;
2329 bool fPadding2;
2330
2331 /** The index of this page. */
2332 uint16_t idx;
2333 /** The next entry in the list this page currently resides in.
2334 * It's either in the free list or in the GCPhys hash. */
2335 uint16_t iNext;
2336 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2337 uint16_t iUserHead;
2338 /** The number of present entries. */
2339 uint16_t cPresent;
2340 /** The first entry in the table which is present. */
2341 uint16_t iFirstPresent;
2342 /** The number of modifications to the monitored page. */
2343 uint16_t cModifications;
2344 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2345 uint16_t iModifiedNext;
2346 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2347 uint16_t iModifiedPrev;
2348 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2349 uint16_t iMonitoredNext;
2350 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2351 uint16_t iMonitoredPrev;
2352 /** The next page in the age list. */
2353 uint16_t iAgeNext;
2354 /** The previous page in the age list. */
2355 uint16_t iAgePrev;
2356 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2357 uint8_t idxDirtyEntry;
2358
2359 /** @name Access handler statistics to determine whether the guest is
2360 * (re)initializing a page table.
2361 * @{ */
2362 RTGCPTR GCPtrLastAccessHandlerRip;
2363 RTGCPTR GCPtrLastAccessHandlerFault;
2364 uint64_t cLastAccessHandler;
2365 /** @} */
2366 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2367 uint32_t volatile cLocked;
2368#if GC_ARCH_BITS == 64
2369 uint32_t u32Alignment3;
2370#endif
2371# ifdef VBOX_STRICT
2372 RTGCPTR GCPtrDirtyFault;
2373# endif
2374} PGMPOOLPAGE;
2375/** Pointer to a pool page. */
2376typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2377/** Pointer to a const pool page. */
2378typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2379/** Pointer to a pool page pointer. */
2380typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2381
2382
2383/** The hash table size. */
2384# define PGMPOOL_HASH_SIZE 0x40
2385/** The hash function. */
2386# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2387
2388
2389/**
2390 * The shadow page pool instance data.
2391 *
2392 * It's all one big allocation made at init time, except for the
2393 * pages that is. The user nodes follows immediately after the
2394 * page structures.
2395 */
2396typedef struct PGMPOOL
2397{
2398 /** The VM handle - R3 Ptr. */
2399 PVMR3 pVMR3;
2400 /** The VM handle - R0 Ptr. */
2401 PVMR0 pVMR0;
2402 /** The VM handle - RC Ptr. */
2403 PVMRC pVMRC;
2404 /** The max pool size. This includes the special IDs. */
2405 uint16_t cMaxPages;
2406 /** The current pool size. */
2407 uint16_t cCurPages;
2408 /** The head of the free page list. */
2409 uint16_t iFreeHead;
2410 /* Padding. */
2411 uint16_t u16Padding;
2412 /** Head of the chain of free user nodes. */
2413 uint16_t iUserFreeHead;
2414 /** The number of user nodes we've allocated. */
2415 uint16_t cMaxUsers;
2416 /** The number of present page table entries in the entire pool. */
2417 uint32_t cPresent;
2418 /** Pointer to the array of user nodes - RC pointer. */
2419 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2420 /** Pointer to the array of user nodes - R3 pointer. */
2421 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2422 /** Pointer to the array of user nodes - R0 pointer. */
2423 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2424 /** Head of the chain of free phys ext nodes. */
2425 uint16_t iPhysExtFreeHead;
2426 /** The number of user nodes we've allocated. */
2427 uint16_t cMaxPhysExts;
2428 /** Pointer to the array of physical xref extent - RC pointer. */
2429 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2430 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2431 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2432 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2433 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2434 /** Hash table for GCPhys addresses. */
2435 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2436 /** The head of the age list. */
2437 uint16_t iAgeHead;
2438 /** The tail of the age list. */
2439 uint16_t iAgeTail;
2440 /** Set if the cache is enabled. */
2441 bool fCacheEnabled;
2442 /** Alignment padding. */
2443 bool afPadding1[3];
2444 /** Head of the list of modified pages. */
2445 uint16_t iModifiedHead;
2446 /** The current number of modified pages. */
2447 uint16_t cModifiedPages;
2448 /** Physical access handler type registration handle. */
2449 PGMPHYSHANDLERTYPE hAccessHandlerType;
2450 /** Next available slot (in aDirtyPages). */
2451 uint32_t idxFreeDirtyPage;
2452 /** Number of active dirty pages. */
2453 uint32_t cDirtyPages;
2454 /** Array of current dirty pgm pool page indices. */
2455 struct
2456 {
2457 uint16_t uIdx;
2458 uint16_t Alignment[3];
2459 uint64_t aPage[512];
2460 } aDirtyPages[16];
2461 /** The number of pages currently in use. */
2462 uint16_t cUsedPages;
2463#ifdef VBOX_WITH_STATISTICS
2464 /** The high water mark for cUsedPages. */
2465 uint16_t cUsedPagesHigh;
2466 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2467 /** Profiling pgmPoolAlloc(). */
2468 STAMPROFILEADV StatAlloc;
2469 /** Profiling pgmR3PoolClearDoIt(). */
2470 STAMPROFILE StatClearAll;
2471 /** Profiling pgmR3PoolReset(). */
2472 STAMPROFILE StatR3Reset;
2473 /** Profiling pgmPoolFlushPage(). */
2474 STAMPROFILE StatFlushPage;
2475 /** Profiling pgmPoolFree(). */
2476 STAMPROFILE StatFree;
2477 /** Counting explicit flushes by PGMPoolFlushPage(). */
2478 STAMCOUNTER StatForceFlushPage;
2479 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2480 STAMCOUNTER StatForceFlushDirtyPage;
2481 /** Counting flushes for reused pages. */
2482 STAMCOUNTER StatForceFlushReused;
2483 /** Profiling time spent zeroing pages. */
2484 STAMPROFILE StatZeroPage;
2485 /** Profiling of pgmPoolTrackDeref. */
2486 STAMPROFILE StatTrackDeref;
2487 /** Profiling pgmTrackFlushGCPhysPT. */
2488 STAMPROFILE StatTrackFlushGCPhysPT;
2489 /** Profiling pgmTrackFlushGCPhysPTs. */
2490 STAMPROFILE StatTrackFlushGCPhysPTs;
2491 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2492 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2493 /** Number of times we've been out of user records. */
2494 STAMCOUNTER StatTrackFreeUpOneUser;
2495 /** Nr of flushed entries. */
2496 STAMCOUNTER StatTrackFlushEntry;
2497 /** Nr of updated entries. */
2498 STAMCOUNTER StatTrackFlushEntryKeep;
2499 /** Profiling deref activity related tracking GC physical pages. */
2500 STAMPROFILE StatTrackDerefGCPhys;
2501 /** Number of linear searches for a HCPhys in the ram ranges. */
2502 STAMCOUNTER StatTrackLinearRamSearches;
2503 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2504 STAMCOUNTER StamTrackPhysExtAllocFailures;
2505
2506 /** Profiling the RC/R0 \#PF access handler. */
2507 STAMPROFILE StatMonitorPfRZ;
2508 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2509 STAMPROFILE StatMonitorPfRZHandled;
2510 /** Times we've failed interpreting the instruction. */
2511 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2512 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2513 STAMPROFILE StatMonitorPfRZFlushPage;
2514 /* Times we've detected a page table reinit. */
2515 STAMCOUNTER StatMonitorPfRZFlushReinit;
2516 /** Counting flushes for pages that are modified too often. */
2517 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2518 /** Times we've detected fork(). */
2519 STAMCOUNTER StatMonitorPfRZFork;
2520 /** Times we've failed interpreting a patch code instruction. */
2521 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2522 /** Times we've failed interpreting a patch code instruction during flushing. */
2523 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2524 /** The number of times we've seen rep prefixes we can't handle. */
2525 STAMCOUNTER StatMonitorPfRZRepPrefix;
2526 /** Profiling the REP STOSD cases we've handled. */
2527 STAMPROFILE StatMonitorPfRZRepStosd;
2528
2529 /** Profiling the R0/RC regular access handler. */
2530 STAMPROFILE StatMonitorRZ;
2531 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2532 STAMPROFILE StatMonitorRZFlushPage;
2533 /** Per access size counts indexed by size minus 1, last for larger. */
2534 STAMCOUNTER aStatMonitorRZSizes[16+3];
2535 /** Missaligned access counts indexed by offset - 1. */
2536 STAMCOUNTER aStatMonitorRZMisaligned[7];
2537
2538 /** Nr of handled PT faults. */
2539 STAMCOUNTER StatMonitorRZFaultPT;
2540 /** Nr of handled PD faults. */
2541 STAMCOUNTER StatMonitorRZFaultPD;
2542 /** Nr of handled PDPT faults. */
2543 STAMCOUNTER StatMonitorRZFaultPDPT;
2544 /** Nr of handled PML4 faults. */
2545 STAMCOUNTER StatMonitorRZFaultPML4;
2546
2547 /** Profiling the R3 access handler. */
2548 STAMPROFILE StatMonitorR3;
2549 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2550 STAMPROFILE StatMonitorR3FlushPage;
2551 /** Per access size counts indexed by size minus 1, last for larger. */
2552 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2553 /** Missaligned access counts indexed by offset - 1. */
2554 STAMCOUNTER aStatMonitorR3Misaligned[7];
2555 /** Nr of handled PT faults. */
2556 STAMCOUNTER StatMonitorR3FaultPT;
2557 /** Nr of handled PD faults. */
2558 STAMCOUNTER StatMonitorR3FaultPD;
2559 /** Nr of handled PDPT faults. */
2560 STAMCOUNTER StatMonitorR3FaultPDPT;
2561 /** Nr of handled PML4 faults. */
2562 STAMCOUNTER StatMonitorR3FaultPML4;
2563
2564 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2565 STAMCOUNTER StatResetDirtyPages;
2566 /** Times we've called pgmPoolAddDirtyPage. */
2567 STAMCOUNTER StatDirtyPage;
2568 /** Times we've had to flush duplicates for dirty page management. */
2569 STAMCOUNTER StatDirtyPageDupFlush;
2570 /** Times we've had to flush because of overflow. */
2571 STAMCOUNTER StatDirtyPageOverFlowFlush;
2572
2573 /** The high water mark for cModifiedPages. */
2574 uint16_t cModifiedPagesHigh;
2575 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2576
2577 /** The number of cache hits. */
2578 STAMCOUNTER StatCacheHits;
2579 /** The number of cache misses. */
2580 STAMCOUNTER StatCacheMisses;
2581 /** The number of times we've got a conflict of 'kind' in the cache. */
2582 STAMCOUNTER StatCacheKindMismatches;
2583 /** Number of times we've been out of pages. */
2584 STAMCOUNTER StatCacheFreeUpOne;
2585 /** The number of cacheable allocations. */
2586 STAMCOUNTER StatCacheCacheable;
2587 /** The number of uncacheable allocations. */
2588 STAMCOUNTER StatCacheUncacheable;
2589#else
2590 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2591#endif
2592 /** The AVL tree for looking up a page by its HC physical address. */
2593 AVLOHCPHYSTREE HCPhysTree;
2594 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2595 /** Array of pages. (cMaxPages in length)
2596 * The Id is the index into thist array.
2597 */
2598 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2599} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2600AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2601AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2602AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2603#ifdef VBOX_WITH_STATISTICS
2604AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2605#endif
2606AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2607
2608
2609/** @def PGMPOOL_PAGE_2_PTR
2610 * Maps a pool page pool into the current context.
2611 *
2612 * @returns VBox status code.
2613 * @param a_pVM Pointer to the VM.
2614 * @param a_pPage The pool page.
2615 *
2616 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2617 * small page window employeed by that function. Be careful.
2618 * @remark There is no need to assert on the result.
2619 */
2620#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2621# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2622#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2623# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2624DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2625{
2626 AssertPtr(a_pPage);
2627 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2628 return a_pPage->pvPageR3;
2629}
2630#else
2631# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2632#endif
2633
2634
2635/** @def PGMPOOL_PAGE_2_PTR_V2
2636 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2637 *
2638 * @returns VBox status code.
2639 * @param a_pVM Pointer to the VM.
2640 * @param a_pVCpu The current CPU.
2641 * @param a_pPage The pool page.
2642 *
2643 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2644 * small page window employeed by that function. Be careful.
2645 * @remark There is no need to assert on the result.
2646 */
2647#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2648# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2649#else
2650# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2651#endif
2652
2653
2654/** @name Per guest page tracking data.
2655 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2656 * is to use more bits for it and split it up later on. But for now we'll play
2657 * safe and change as little as possible.
2658 *
2659 * The 16-bit word has two parts:
2660 *
2661 * The first 14-bit forms the @a idx field. It is either the index of a page in
2662 * the shadow page pool, or and index into the extent list.
2663 *
2664 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2665 * shadow page pool references to the page. If cRefs equals
2666 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2667 * (misnomer) table and not the shadow page pool.
2668 *
2669 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2670 * the 16-bit word.
2671 *
2672 * @{ */
2673/** The shift count for getting to the cRefs part. */
2674#define PGMPOOL_TD_CREFS_SHIFT 14
2675/** The mask applied after shifting the tracking data down by
2676 * PGMPOOL_TD_CREFS_SHIFT. */
2677#define PGMPOOL_TD_CREFS_MASK 0x3
2678/** The cRefs value used to indicate that the idx is the head of a
2679 * physical cross reference list. */
2680#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2681/** The shift used to get idx. */
2682#define PGMPOOL_TD_IDX_SHIFT 0
2683/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2684#define PGMPOOL_TD_IDX_MASK 0x3fff
2685/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2686 * simply too many mappings of this page. */
2687#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2688
2689/** @def PGMPOOL_TD_MAKE
2690 * Makes a 16-bit tracking data word.
2691 *
2692 * @returns tracking data.
2693 * @param cRefs The @a cRefs field. Must be within bounds!
2694 * @param idx The @a idx field. Must also be within bounds! */
2695#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2696
2697/** @def PGMPOOL_TD_GET_CREFS
2698 * Get the @a cRefs field from a tracking data word.
2699 *
2700 * @returns The @a cRefs field
2701 * @param u16 The tracking data word.
2702 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2703 * non-zero @a u16. */
2704#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2705
2706/** @def PGMPOOL_TD_GET_IDX
2707 * Get the @a idx field from a tracking data word.
2708 *
2709 * @returns The @a idx field
2710 * @param u16 The tracking data word. */
2711#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2712/** @} */
2713
2714
2715
2716/** @name A20 gate macros
2717 * @{ */
2718#define PGM_WITH_A20
2719#ifdef PGM_WITH_A20
2720# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2721# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2722# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2723 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2724# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2725#else
2726# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2727# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2728# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2729# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2730#endif
2731/** @} */
2732
2733
2734/**
2735 * Roots and anchors for trees and list employing self relative offsets as
2736 * pointers.
2737 *
2738 * When using self-relative offsets instead of pointers, the offsets needs to be
2739 * the same in all offsets. Thus the roots and anchors needs to live on the
2740 * hyper heap just like the nodes.
2741 */
2742typedef struct PGMTREES
2743{
2744 /** List of physical access handler types (offset pointers) of type
2745 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2746 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2747 /** Physical access handlers (AVL range+offsetptr tree). */
2748 AVLROGCPHYSTREE PhysHandlers;
2749#ifdef VBOX_WITH_RAW_MODE
2750 /** Virtual access handlers (AVL range + GC ptr tree). */
2751 AVLROGCPTRTREE VirtHandlers;
2752 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2753 * @remarks Handler of the hypervisor kind are of course not present. */
2754 AVLROGCPHYSTREE PhysToVirtHandlers;
2755 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2756 AVLROGCPTRTREE HyperVirtHandlers;
2757 /** List of virtual access handler types (offset pointers) of type
2758 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2759 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2760#endif
2761} PGMTREES;
2762/** Pointer to PGM trees. */
2763typedef PGMTREES *PPGMTREES;
2764
2765
2766/**
2767 * Page fault guest state for the AMD64 paging mode.
2768 */
2769typedef struct PGMPTWALKCORE
2770{
2771 /** The guest virtual address that is being resolved by the walk
2772 * (input). */
2773 RTGCPTR GCPtr;
2774
2775 /** The guest physical address that is the result of the walk.
2776 * @remarks only valid if fSucceeded is set. */
2777 RTGCPHYS GCPhys;
2778
2779 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2780 bool fSucceeded;
2781 /** The level problem arrised at.
2782 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2783 * level 8. This is 0 on success. */
2784 uint8_t uLevel;
2785 /** Set if the page isn't present. */
2786 bool fNotPresent;
2787 /** Encountered a bad physical address. */
2788 bool fBadPhysAddr;
2789 /** Set if there was reserved bit violations. */
2790 bool fRsvdError;
2791 /** Set if it involves a big page (2/4 MB). */
2792 bool fBigPage;
2793 /** Set if it involves a gigantic page (1 GB). */
2794 bool fGigantPage;
2795 /** The effective X86_PTE_US flag for the address. */
2796 bool fEffectiveUS;
2797 /** The effective X86_PTE_RW flag for the address. */
2798 bool fEffectiveRW;
2799 /** The effective X86_PTE_NX flag for the address. */
2800 bool fEffectiveNX;
2801 bool afPadding1[2];
2802 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2803 * The NX bit is inverted and shifted down 63 places to bit 0. */
2804 uint32_t fEffective;
2805} PGMPTWALKCORE;
2806
2807/** @name PGMPTWALKCORE::fEffective bits.
2808 * @{ */
2809/** Effective execute bit (!NX). */
2810#define PGMPTWALK_EFF_X UINT32_C(1)
2811/** Effective write access bit. */
2812#define PGMPTWALK_EFF_RW X86_PTE_RW
2813/** Effective user-mode access bit. */
2814#define PGMPTWALK_EFF_US X86_PTE_US
2815/** Effective write through cache bit. */
2816#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2817/** Effective cache disabled bit. */
2818#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2819/** Effective accessed bit. */
2820#define PGMPTWALK_EFF_A X86_PTE_A
2821/** The dirty bit of the final entry. */
2822#define PGMPTWALK_EFF_D X86_PTE_D
2823/** The PAT bit of the final entry. */
2824#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2825/** The global bit of the final entry. */
2826#define PGMPTWALK_EFF_G X86_PTE_G
2827/** @} */
2828
2829
2830/**
2831 * Guest page table walk for the AMD64 mode.
2832 */
2833typedef struct PGMPTWALKGSTAMD64
2834{
2835 /** The common core. */
2836 PGMPTWALKCORE Core;
2837
2838 PX86PML4 pPml4;
2839 PX86PML4E pPml4e;
2840 X86PML4E Pml4e;
2841
2842 PX86PDPT pPdpt;
2843 PX86PDPE pPdpe;
2844 X86PDPE Pdpe;
2845
2846 PX86PDPAE pPd;
2847 PX86PDEPAE pPde;
2848 X86PDEPAE Pde;
2849
2850 PX86PTPAE pPt;
2851 PX86PTEPAE pPte;
2852 X86PTEPAE Pte;
2853} PGMPTWALKGSTAMD64;
2854/** Pointer to a AMD64 guest page table walk. */
2855typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2856/** Pointer to a const AMD64 guest page table walk. */
2857typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2858
2859/**
2860 * Guest page table walk for the PAE mode.
2861 */
2862typedef struct PGMPTWALKGSTPAE
2863{
2864 /** The common core. */
2865 PGMPTWALKCORE Core;
2866
2867 PX86PDPT pPdpt;
2868 PX86PDPE pPdpe;
2869 X86PDPE Pdpe;
2870
2871 PX86PDPAE pPd;
2872 PX86PDEPAE pPde;
2873 X86PDEPAE Pde;
2874
2875 PX86PTPAE pPt;
2876 PX86PTEPAE pPte;
2877 X86PTEPAE Pte;
2878} PGMPTWALKGSTPAE;
2879/** Pointer to a PAE guest page table walk. */
2880typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2881/** Pointer to a const AMD64 guest page table walk. */
2882typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2883
2884/**
2885 * Guest page table walk for the 32-bit mode.
2886 */
2887typedef struct PGMPTWALKGST32BIT
2888{
2889 /** The common core. */
2890 PGMPTWALKCORE Core;
2891
2892 PX86PD pPd;
2893 PX86PDE pPde;
2894 X86PDE Pde;
2895
2896 PX86PT pPt;
2897 PX86PTE pPte;
2898 X86PTE Pte;
2899} PGMPTWALKGST32BIT;
2900/** Pointer to a 32-bit guest page table walk. */
2901typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2902/** Pointer to a const 32-bit guest page table walk. */
2903typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2904
2905/**
2906 * Which part of PGMPTWALKGST that is valid.
2907 */
2908typedef enum PGMPTWALKGSTTYPE
2909{
2910 /** Customary invalid 0 value. */
2911 PGMPTWALKGSTTYPE_INVALID = 0,
2912 /** PGMPTWALKGST::u.Amd64 is valid. */
2913 PGMPTWALKGSTTYPE_AMD64,
2914 /** PGMPTWALKGST::u.Pae is valid. */
2915 PGMPTWALKGSTTYPE_PAE,
2916 /** PGMPTWALKGST::u.Legacy is valid. */
2917 PGMPTWALKGSTTYPE_32BIT,
2918 /** Customary 32-bit type hack. */
2919 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2920} PGMPTWALKGSTTYPE;
2921
2922/**
2923 * Combined guest page table walk result.
2924 */
2925typedef struct PGMPTWALKGST
2926{
2927 union
2928 {
2929 /** The page walker core - always valid. */
2930 PGMPTWALKCORE Core;
2931 /** The page walker for AMD64. */
2932 PGMPTWALKGSTAMD64 Amd64;
2933 /** The page walker for PAE (32-bit). */
2934 PGMPTWALKGSTPAE Pae;
2935 /** The page walker for 32-bit paging (called legacy due to C naming
2936 * convension). */
2937 PGMPTWALKGST32BIT Legacy;
2938 } u;
2939 /** Indicates which part of the union is valid. */
2940 PGMPTWALKGSTTYPE enmType;
2941} PGMPTWALKGST;
2942/** Pointer to a combined guest page table walk result. */
2943typedef PGMPTWALKGST *PPGMPTWALKGST;
2944/** Pointer to a read-only combined guest page table walk result. */
2945typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2946
2947
2948/** @name Paging mode macros
2949 * @{
2950 */
2951#ifdef IN_RC
2952# define PGM_CTX(a,b) a##RC##b
2953# define PGM_CTX_STR(a,b) a "GC" b
2954# define PGM_CTX_DECL(type) VMMRCDECL(type)
2955#else
2956# ifdef IN_RING3
2957# define PGM_CTX(a,b) a##R3##b
2958# define PGM_CTX_STR(a,b) a "R3" b
2959# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2960# else
2961# define PGM_CTX(a,b) a##R0##b
2962# define PGM_CTX_STR(a,b) a "R0" b
2963# define PGM_CTX_DECL(type) VMMDECL(type)
2964# endif
2965#endif
2966
2967#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2968#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2969#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2970#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2971#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2972#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2973#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2974#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2975#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2976#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2977#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2978#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2979#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2980#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2981#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2982#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2983#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2984
2985#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2986#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2987#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2988#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2989#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2990#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2991#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2992#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2993#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2994#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2995#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2996#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2997#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2998#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2999#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
3000#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
3001#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
3002
3003/* Shw_Gst */
3004#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
3005#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
3006#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
3007#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
3008#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
3009#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
3010#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
3011#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
3012#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
3013#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
3014#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
3015#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
3016#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
3017#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
3018#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
3019#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
3020#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
3021#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
3022#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
3023
3024#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
3025#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
3026#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
3027#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
3028#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
3029#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
3030#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
3031#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
3032#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
3033#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
3034#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
3035#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
3036#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
3037#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
3038#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
3039#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
3040#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
3041#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
3042#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
3043#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
3044#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
3045#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
3046#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
3047#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
3048#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
3049#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
3050#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
3051#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
3052#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
3053#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
3054#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
3055#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
3056#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3057#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3058#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3059#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3060#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3061
3062#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3063#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
3064/** @} */
3065
3066/**
3067 * Data for each paging mode.
3068 */
3069typedef struct PGMMODEDATA
3070{
3071 /** The guest mode type. */
3072 uint32_t uGstType;
3073 /** The shadow mode type. */
3074 uint32_t uShwType;
3075
3076 /** @name Function pointers for Shadow paging.
3077 * @{
3078 */
3079 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3080 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3081 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3082 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3083
3084 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3085 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3086
3087 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3088 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3089 /** @} */
3090
3091 /** @name Function pointers for Guest paging.
3092 * @{
3093 */
3094 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3095 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3096 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3097 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3098 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3099 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3100 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3101 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3102 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3103 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3104 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3105 /** @} */
3106
3107 /** @name Function pointers for Both Shadow and Guest paging.
3108 * @{
3109 */
3110 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3111 /* no pfnR3BthTrap0eHandler */
3112 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3113 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3114 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3115 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3116#ifdef VBOX_STRICT
3117 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3118#endif
3119 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3120 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3121
3122 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3123 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3124 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3125 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3126 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3127#ifdef VBOX_STRICT
3128 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3129#endif
3130 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3131 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3132
3133 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3134 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3135 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3136 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3137 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3138#ifdef VBOX_STRICT
3139 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3140#endif
3141 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3142 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3143 /** @} */
3144} PGMMODEDATA, *PPGMMODEDATA;
3145
3146
3147#ifdef VBOX_WITH_STATISTICS
3148/**
3149 * PGM statistics.
3150 *
3151 * These lives on the heap when compiled in as they would otherwise waste
3152 * unnecessary space in release builds.
3153 */
3154typedef struct PGMSTATS
3155{
3156 /* R3 only: */
3157 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3158 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3159
3160 /* R3+RZ */
3161 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3162 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3163 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3164 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3165 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3166 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3167 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3168 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3169 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3170 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3171 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3172 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3173 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3174 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3175 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3176 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3177 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3178 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3179 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3180 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3181 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3182 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3183 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3184 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3185 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3186 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3187 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3188 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3189/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3190 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3191 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3192/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3193
3194 /* RC only: */
3195 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3196 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3197
3198 STAMCOUNTER StatRZPhysRead;
3199 STAMCOUNTER StatRZPhysReadBytes;
3200 STAMCOUNTER StatRZPhysWrite;
3201 STAMCOUNTER StatRZPhysWriteBytes;
3202 STAMCOUNTER StatR3PhysRead;
3203 STAMCOUNTER StatR3PhysReadBytes;
3204 STAMCOUNTER StatR3PhysWrite;
3205 STAMCOUNTER StatR3PhysWriteBytes;
3206 STAMCOUNTER StatRCPhysRead;
3207 STAMCOUNTER StatRCPhysReadBytes;
3208 STAMCOUNTER StatRCPhysWrite;
3209 STAMCOUNTER StatRCPhysWriteBytes;
3210
3211 STAMCOUNTER StatRZPhysSimpleRead;
3212 STAMCOUNTER StatRZPhysSimpleReadBytes;
3213 STAMCOUNTER StatRZPhysSimpleWrite;
3214 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3215 STAMCOUNTER StatR3PhysSimpleRead;
3216 STAMCOUNTER StatR3PhysSimpleReadBytes;
3217 STAMCOUNTER StatR3PhysSimpleWrite;
3218 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3219 STAMCOUNTER StatRCPhysSimpleRead;
3220 STAMCOUNTER StatRCPhysSimpleReadBytes;
3221 STAMCOUNTER StatRCPhysSimpleWrite;
3222 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3223
3224 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3225 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3226 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3227 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3228 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3229 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3230 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3231
3232 /** Time spent by the host OS for large page allocation. */
3233 STAMPROFILE StatAllocLargePage;
3234 /** Time spent clearing the newly allocated large pages. */
3235 STAMPROFILE StatClearLargePage;
3236 /** The number of times allocating a large pages takes more than the allowed period. */
3237 STAMCOUNTER StatLargePageOverflow;
3238 /** pgmPhysIsValidLargePage profiling - R3 */
3239 STAMPROFILE StatR3IsValidLargePage;
3240 /** pgmPhysIsValidLargePage profiling - RZ*/
3241 STAMPROFILE StatRZIsValidLargePage;
3242
3243 STAMPROFILE StatChunkAging;
3244 STAMPROFILE StatChunkFindCandidate;
3245 STAMPROFILE StatChunkUnmap;
3246 STAMPROFILE StatChunkMap;
3247} PGMSTATS;
3248#endif /* VBOX_WITH_STATISTICS */
3249
3250
3251/**
3252 * Converts a PGM pointer into a VM pointer.
3253 * @returns Pointer to the VM structure the PGM is part of.
3254 * @param pPGM Pointer to PGM instance data.
3255 */
3256#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3257
3258/**
3259 * PGM Data (part of VM)
3260 */
3261typedef struct PGM
3262{
3263 /** Offset to the VM structure. */
3264 int32_t offVM;
3265 /** Offset of the PGMCPU structure relative to VMCPU. */
3266 int32_t offVCpuPGM;
3267
3268 /** @cfgm{/RamPreAlloc, boolean, false}
3269 * Indicates whether the base RAM should all be allocated before starting
3270 * the VM (default), or if it should be allocated when first written to.
3271 */
3272 bool fRamPreAlloc;
3273 /** Indicates whether write monitoring is currently in use.
3274 * This is used to prevent conflicts between live saving and page sharing
3275 * detection. */
3276 bool fPhysWriteMonitoringEngaged;
3277 /** Set if the CPU has less than 52-bit physical address width.
3278 * This is used */
3279 bool fLessThan52PhysicalAddressBits;
3280 /** Set when nested paging is active.
3281 * This is meant to save calls to HMIsNestedPagingActive and let the
3282 * compilers optimize the code better. Whether we use nested paging or
3283 * not is something we find out during VMM initialization and we won't
3284 * change this later on. */
3285 bool fNestedPaging;
3286 /** The host paging mode. (This is what SUPLib reports.) */
3287 SUPPAGINGMODE enmHostMode;
3288 /** We're not in a state which permits writes to guest memory.
3289 * (Only used in strict builds.) */
3290 bool fNoMorePhysWrites;
3291 /** @cfgm{/PageFusionAllowed, boolean, false}
3292 * Whether page fusion is allowed. */
3293 bool fPageFusionAllowed;
3294 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3295 * Whether PCI passthrough is enabled. */
3296 bool fPciPassthrough;
3297 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3298 uint8_t cMmio2Regions;
3299 /** Restore original ROM page content when resetting after loading state.
3300 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3301 * enables the VM to start using an updated ROM without requiring powering
3302 * down the VM, just rebooting or resetting it. */
3303 bool fRestoreRomPagesOnReset;
3304 /** Whether to automatically clear all RAM pages on reset. */
3305 bool fZeroRamPagesOnReset;
3306 /** Alignment padding. */
3307 bool afAlignment3[7];
3308
3309 /** Indicates that PGMR3FinalizeMappings has been called and that further
3310 * PGMR3MapIntermediate calls will be rejected. */
3311 bool fFinalizedMappings;
3312 /** If set no conflict checks are required. */
3313 bool fMappingsFixed;
3314 /** If set if restored as fixed but we were unable to re-fixate at the old
3315 * location because of room or address incompatibilities. */
3316 bool fMappingsFixedRestored;
3317 /** Size of fixed mapping.
3318 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3319 uint32_t cbMappingFixed;
3320 /** Generation ID for the RAM ranges. This member is incremented everytime
3321 * a RAM range is linked or unlinked. */
3322 uint32_t volatile idRamRangesGen;
3323
3324 /** Base address (GC) of fixed mapping.
3325 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3326 RTGCPTR GCPtrMappingFixed;
3327 /** The address of the previous RAM range mapping. */
3328 RTGCPTR GCPtrPrevRamRangeMapping;
3329
3330 /** Physical access handler type for ROM protection. */
3331 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3332 /** Alignment padding. */
3333 uint32_t u32Padding;
3334
3335 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3336 RTGCPHYS GCPhys4MBPSEMask;
3337 /** Mask containing the invalid bits of a guest physical address.
3338 * @remarks this does not stop at bit 52. */
3339 RTGCPHYS GCPhysInvAddrMask;
3340
3341
3342 /** RAM range TLB for R3. */
3343 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3344 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3345 * This is sorted by physical address and contains no overlapping ranges. */
3346 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3347 /** Root of the RAM range search tree for ring-3. */
3348 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3349 /** PGM offset based trees - R3 Ptr. */
3350 R3PTRTYPE(PPGMTREES) pTreesR3;
3351 /** Caching the last physical handler we looked up in R3. */
3352 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3353 /** Shadow Page Pool - R3 Ptr. */
3354 R3PTRTYPE(PPGMPOOL) pPoolR3;
3355 /** Linked list of GC mappings - for HC.
3356 * The list is sorted ascending on address. */
3357 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3358 /** Pointer to the list of ROM ranges - for R3.
3359 * This is sorted by physical address and contains no overlapping ranges. */
3360 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3361 /** Pointer to the list of MMIO2 ranges - for R3.
3362 * Registration order. */
3363 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3364 /** Pointer to SHW+GST mode data (function pointers).
3365 * The index into this table is made up from */
3366 R3PTRTYPE(PPGMMODEDATA) paModeData;
3367 RTR3PTR R3PtrAlignment0;
3368 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3369 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3370
3371 /** RAM range TLB for R0. */
3372 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3373 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3374 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3375 /** Root of the RAM range search tree for ring-0. */
3376 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3377 /** PGM offset based trees - R0 Ptr. */
3378 R0PTRTYPE(PPGMTREES) pTreesR0;
3379 /** Caching the last physical handler we looked up in R0. */
3380 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3381 /** Shadow Page Pool - R0 Ptr. */
3382 R0PTRTYPE(PPGMPOOL) pPoolR0;
3383 /** Linked list of GC mappings - for R0.
3384 * The list is sorted ascending on address. */
3385 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3386 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3387 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3388 RTR0PTR R0PtrAlignment0;
3389 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3390 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3391
3392 /** RAM range TLB for RC. */
3393 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3394 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3395 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3396 /** Root of the RAM range search tree for raw-mode context. */
3397 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3398 /** PGM offset based trees - RC Ptr. */
3399 RCPTRTYPE(PPGMTREES) pTreesRC;
3400 /** Caching the last physical handler we looked up in RC. */
3401 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3402 /** Shadow Page Pool - RC Ptr. */
3403 RCPTRTYPE(PPGMPOOL) pPoolRC;
3404 /** Linked list of GC mappings - for RC.
3405 * The list is sorted ascending on address. */
3406 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3407 /** RC pointer corresponding to PGM::pRomRangesR3. */
3408 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3409 RTRCPTR RCPtrAlignment0;
3410 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3411 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3412 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3413 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3414
3415
3416 /** Pointer to the 5 page CR3 content mapping.
3417 * The first page is always the CR3 (in some form) while the 4 other pages
3418 * are used of the PDs in PAE mode. */
3419 RTGCPTR GCPtrCR3Mapping;
3420
3421 /** @name Intermediate Context
3422 * @{ */
3423 /** Pointer to the intermediate page directory - Normal. */
3424 R3PTRTYPE(PX86PD) pInterPD;
3425 /** Pointer to the intermediate page tables - Normal.
3426 * There are two page tables, one for the identity mapping and one for
3427 * the host context mapping (of the core code). */
3428 R3PTRTYPE(PX86PT) apInterPTs[2];
3429 /** Pointer to the intermediate page tables - PAE. */
3430 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3431 /** Pointer to the intermediate page directory - PAE. */
3432 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3433 /** Pointer to the intermediate page directory - PAE. */
3434 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3435 /** Pointer to the intermediate page-map level 4 - AMD64. */
3436 R3PTRTYPE(PX86PML4) pInterPaePML4;
3437 /** Pointer to the intermediate page directory - AMD64. */
3438 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3439 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3440 RTHCPHYS HCPhysInterPD;
3441 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3442 RTHCPHYS HCPhysInterPaePDPT;
3443 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3444 RTHCPHYS HCPhysInterPaePML4;
3445 /** @} */
3446
3447 /** Base address of the dynamic page mapping area.
3448 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3449 *
3450 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3451 * work out. Some cleaning up of the initialization that would
3452 * remove this memory is yet to be done...
3453 */
3454 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3455 /** The address of the raw-mode context mapping cache. */
3456 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3457 /** The address of the ring-0 mapping cache if we're making use of it. */
3458 RTR0PTR pvR0DynMapUsed;
3459
3460 /** Hack: Number of deprecated page mapping locks taken by the current lock
3461 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3462 uint32_t cDeprecatedPageLocks;
3463#if HC_ARCH_BITS == 64
3464 /** Alignment padding. */
3465 uint32_t u32Alignment2;
3466#endif
3467
3468
3469 /** PGM critical section.
3470 * This protects the physical & virtual access handlers, ram ranges,
3471 * and the page flag updating (some of it anyway).
3472 */
3473 PDMCRITSECT CritSectX;
3474
3475 /**
3476 * Data associated with managing the ring-3 mappings of the allocation chunks.
3477 */
3478 struct
3479 {
3480 /** The chunk tree, ordered by chunk id. */
3481#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3482 R3PTRTYPE(PAVLU32NODECORE) pTree;
3483#else
3484 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3485#endif
3486#if HC_ARCH_BITS == 32
3487 uint32_t u32Alignment0;
3488#endif
3489 /** The chunk mapping TLB. */
3490 PGMCHUNKR3MAPTLB Tlb;
3491 /** The number of mapped chunks. */
3492 uint32_t c;
3493 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3494 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3495 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3496 uint32_t cMax;
3497 /** The current time. This is incremented whenever a chunk is inserted. */
3498 uint32_t iNow;
3499 /** Alignment padding. */
3500 uint32_t u32Alignment1;
3501 } ChunkR3Map;
3502
3503 /**
3504 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3505 */
3506 PGMPAGER3MAPTLB PhysTlbHC;
3507
3508 /** @name The zero page.
3509 * @{ */
3510 /** The host physical address of the zero page. */
3511 RTHCPHYS HCPhysZeroPg;
3512 /** The ring-3 mapping of the zero page. */
3513 RTR3PTR pvZeroPgR3;
3514 /** The ring-0 mapping of the zero page. */
3515 RTR0PTR pvZeroPgR0;
3516 /** The GC mapping of the zero page. */
3517 RTRCPTR pvZeroPgRC;
3518 RTRCPTR RCPtrAlignment3;
3519 /** @}*/
3520
3521 /** @name The Invalid MMIO page.
3522 * This page is filled with 0xfeedface.
3523 * @{ */
3524 /** The host physical address of the invalid MMIO page. */
3525 RTHCPHYS HCPhysMmioPg;
3526 /** The host pysical address of the invalid MMIO page plus all invalid
3527 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3528 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3529 RTHCPHYS HCPhysInvMmioPg;
3530 /** The ring-3 mapping of the invalid MMIO page. */
3531 RTR3PTR pvMmioPgR3;
3532#if HC_ARCH_BITS == 32
3533 RTR3PTR R3PtrAlignment4;
3534#endif
3535 /** @} */
3536
3537
3538 /** The number of handy pages. */
3539 uint32_t cHandyPages;
3540
3541 /** The number of large handy pages. */
3542 uint32_t cLargeHandyPages;
3543
3544 /**
3545 * Array of handy pages.
3546 *
3547 * This array is used in a two way communication between pgmPhysAllocPage
3548 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3549 * an intermediary.
3550 *
3551 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3552 * (The current size of 32 pages, means 128 KB of handy memory.)
3553 */
3554 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3555
3556 /**
3557 * Array of large handy pages. (currently size 1)
3558 *
3559 * This array is used in a two way communication between pgmPhysAllocLargePage
3560 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3561 * an intermediary.
3562 */
3563 GMMPAGEDESC aLargeHandyPage[1];
3564
3565 /**
3566 * Live save data.
3567 */
3568 struct
3569 {
3570 /** Per type statistics. */
3571 struct
3572 {
3573 /** The number of ready pages. */
3574 uint32_t cReadyPages;
3575 /** The number of dirty pages. */
3576 uint32_t cDirtyPages;
3577 /** The number of ready zero pages. */
3578 uint32_t cZeroPages;
3579 /** The number of write monitored pages. */
3580 uint32_t cMonitoredPages;
3581 } Rom,
3582 Mmio2,
3583 Ram;
3584 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3585 uint32_t cIgnoredPages;
3586 /** Indicates that a live save operation is active. */
3587 bool fActive;
3588 /** Padding. */
3589 bool afReserved[2];
3590 /** The next history index. */
3591 uint8_t iDirtyPagesHistory;
3592 /** History of the total amount of dirty pages. */
3593 uint32_t acDirtyPagesHistory[64];
3594 /** Short term dirty page average. */
3595 uint32_t cDirtyPagesShort;
3596 /** Long term dirty page average. */
3597 uint32_t cDirtyPagesLong;
3598 /** The number of saved pages. This is used to get some kind of estimate of the
3599 * link speed so we can decide when we're done. It is reset after the first
3600 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3601 * zero pages. */
3602 uint64_t cSavedPages;
3603 /** The nanosecond timestamp when cSavedPages was 0. */
3604 uint64_t uSaveStartNS;
3605 /** Pages per second (for statistics). */
3606 uint32_t cPagesPerSecond;
3607 uint32_t cAlignment;
3608 } LiveSave;
3609
3610 /** @name Error injection.
3611 * @{ */
3612 /** Inject handy page allocation errors pretending we're completely out of
3613 * memory. */
3614 bool volatile fErrInjHandyPages;
3615 /** Padding. */
3616 bool afReserved[3];
3617 /** @} */
3618
3619 /** @name Release Statistics
3620 * @{ */
3621 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3622 uint32_t cPrivatePages; /**< The number of private pages. */
3623 uint32_t cSharedPages; /**< The number of shared pages. */
3624 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3625 uint32_t cZeroPages; /**< The number of zero backed pages. */
3626 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3627 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3628 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3629 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3630 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3631 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3632 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3633 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3634 uint32_t cLargePages; /**< The number of large pages. */
3635 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3636/* uint32_t aAlignment4[1]; */
3637
3638 /** The number of times we were forced to change the hypervisor region location. */
3639 STAMCOUNTER cRelocations;
3640
3641 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3642 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3643 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3644
3645 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3646 /** @} */
3647
3648#ifdef VBOX_WITH_STATISTICS
3649 /** @name Statistics on the heap.
3650 * @{ */
3651 R3PTRTYPE(PGMSTATS *) pStatsR3;
3652 R0PTRTYPE(PGMSTATS *) pStatsR0;
3653 RCPTRTYPE(PGMSTATS *) pStatsRC;
3654 RTRCPTR RCPtrAlignment;
3655 /** @} */
3656#endif
3657} PGM;
3658#ifndef IN_TSTVMSTRUCTGC /* HACK */
3659AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3660AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3661AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3662AssertCompileMemberAlignment(PGM, CritSectX, 8);
3663AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3664AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3665AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3666AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3667AssertCompileMemberAlignment(PGM, cRelocations, 8);
3668#endif /* !IN_TSTVMSTRUCTGC */
3669/** Pointer to the PGM instance data. */
3670typedef PGM *PPGM;
3671
3672
3673
3674typedef struct PGMCPUSTATS
3675{
3676 /* Common */
3677 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3678 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3679
3680 /* R0 only: */
3681 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3682 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3683
3684 /* RZ only: */
3685 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3686 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3687 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3688 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3689 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3690 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3691 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3692 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3693 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3694 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3695 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3696 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3697 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3698 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3699 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3700 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3701 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3702 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3703 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3704 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3705 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3706 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3707 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3708 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3709 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3710 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3711 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3712 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3713 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3714 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3715 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3716 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3717 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3718 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3719 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3720 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3721 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3722 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3723 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3724 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3725 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3726 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3727 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3728 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3729 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3730 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3731 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3732 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3733 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3734 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3735 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3736 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3737 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3738 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3739 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3740 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3741 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3742 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3743 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3744 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3745 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3746 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3747 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3748 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3749 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3750 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3751 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3752 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3753 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3754 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3755 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3756 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3757 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3758 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3759 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3760 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3761 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3762 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3763
3764 /* HC - R3 and (maybe) R0: */
3765
3766 /* RZ & R3: */
3767 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3768 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3769 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3770 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3771 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3772 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3773 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3774 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3775 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3776 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3777 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3778 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3779 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3780 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3781 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3782 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3783 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3784 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3785 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3786 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3787 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3788 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3789 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3790 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3791 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3792 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3793 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3794 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3795 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3796 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3797 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3798 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3799 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3800 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3801 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3802 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3803 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3804 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3805 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3806 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3807 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3808 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3809 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3810 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3811 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3812 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3813 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3814 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3815
3816 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3817 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3818 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3819 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3820 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3821 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3822 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3823 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3824 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3825 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3826 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3827 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3828 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3829 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3830 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3831 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3832 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3833 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3834 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3835 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3836 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3837 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3838 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3839 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3840 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3841 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3842 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3843 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3844 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3845 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3846 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3847 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3848 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3849 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3850 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3851 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3852 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3853 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3854 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3855 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3856 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3857 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3858 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3859 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3860 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3861 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3862 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3863 /** @} */
3864} PGMCPUSTATS;
3865
3866
3867/**
3868 * Converts a PGMCPU pointer into a VM pointer.
3869 * @returns Pointer to the VM structure the PGM is part of.
3870 * @param pPGM Pointer to PGMCPU instance data.
3871 */
3872#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3873
3874/**
3875 * Converts a PGMCPU pointer into a PGM pointer.
3876 * @returns Pointer to the VM structure the PGM is part of.
3877 * @param pPGMCpu Pointer to PGMCPU instance data.
3878 */
3879#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3880
3881/**
3882 * PGMCPU Data (part of VMCPU).
3883 */
3884typedef struct PGMCPU
3885{
3886 /** Offset to the VM structure. */
3887 int32_t offVM;
3888 /** Offset to the VMCPU structure. */
3889 int32_t offVCpu;
3890 /** Offset of the PGM structure relative to VMCPU. */
3891 int32_t offPGM;
3892 uint32_t uPadding0; /**< structure size alignment. */
3893
3894#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3895 /** Automatically tracked physical memory mapping set.
3896 * Ring-0 and strict raw-mode builds. */
3897 PGMMAPSET AutoSet;
3898#endif
3899
3900 /** A20 gate mask.
3901 * Our current approach to A20 emulation is to let REM do it and don't bother
3902 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3903 * But whould need arrise, we'll subject physical addresses to this mask. */
3904 RTGCPHYS GCPhysA20Mask;
3905 /** A20 gate state - boolean! */
3906 bool fA20Enabled;
3907 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3908 bool fNoExecuteEnabled;
3909 /** Unused bits. */
3910 bool afUnused[2];
3911
3912 /** What needs syncing (PGM_SYNC_*).
3913 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3914 * PGMFlushTLB, and PGMR3Load. */
3915 uint32_t fSyncFlags;
3916
3917 /** The shadow paging mode. */
3918 PGMMODE enmShadowMode;
3919 /** The guest paging mode. */
3920 PGMMODE enmGuestMode;
3921
3922 /** The current physical address represented in the guest CR3 register. */
3923 RTGCPHYS GCPhysCR3;
3924
3925 /** @name 32-bit Guest Paging.
3926 * @{ */
3927 /** The guest's page directory, R3 pointer. */
3928 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3929#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3930 /** The guest's page directory, R0 pointer. */
3931 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3932#endif
3933 /** The guest's page directory, static RC mapping. */
3934 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3935 /** Mask containing the MBZ bits of a big page PDE. */
3936 uint32_t fGst32BitMbzBigPdeMask;
3937 /** Set if the page size extension (PSE) is enabled. */
3938 bool fGst32BitPageSizeExtension;
3939 /** Alignment padding. */
3940 bool afAlignment2[3];
3941 /** @} */
3942
3943 /** @name PAE Guest Paging.
3944 * @{ */
3945 /** The guest's page directory pointer table, static RC mapping. */
3946 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3947 /** The guest's page directory pointer table, R3 pointer. */
3948 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3949#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3950 /** The guest's page directory pointer table, R0 pointer. */
3951 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3952#endif
3953
3954 /** The guest's page directories, R3 pointers.
3955 * These are individual pointers and don't have to be adjacent.
3956 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3957 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3958 /** The guest's page directories, R0 pointers.
3959 * Same restrictions as apGstPaePDsR3. */
3960#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3961 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3962#endif
3963 /** The guest's page directories, static GC mapping.
3964 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3965 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3966 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3967 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3968 * @todo Remove this and use aGstPaePdpeRegs instead? */
3969 RTGCPHYS aGCPhysGstPaePDs[4];
3970 /** The values of the 4 PDPE CPU registers (PAE). */
3971 X86PDPE aGstPaePdpeRegs[4];
3972 /** The physical addresses of the monitored guest page directories (PAE). */
3973 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3974 /** Mask containing the MBZ PTE bits. */
3975 uint64_t fGstPaeMbzPteMask;
3976 /** Mask containing the MBZ PDE bits. */
3977 uint64_t fGstPaeMbzPdeMask;
3978 /** Mask containing the MBZ big page PDE bits. */
3979 uint64_t fGstPaeMbzBigPdeMask;
3980 /** Mask containing the MBZ PDPE bits. */
3981 uint64_t fGstPaeMbzPdpeMask;
3982 /** @} */
3983
3984 /** @name AMD64 Guest Paging.
3985 * @{ */
3986 /** The guest's page directory pointer table, R3 pointer. */
3987 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3988#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3989 /** The guest's page directory pointer table, R0 pointer. */
3990 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3991#else
3992 RTR0PTR alignment6b; /**< alignment equalizer. */
3993#endif
3994 /** Mask containing the MBZ PTE bits. */
3995 uint64_t fGstAmd64MbzPteMask;
3996 /** Mask containing the MBZ PDE bits. */
3997 uint64_t fGstAmd64MbzPdeMask;
3998 /** Mask containing the MBZ big page PDE bits. */
3999 uint64_t fGstAmd64MbzBigPdeMask;
4000 /** Mask containing the MBZ PDPE bits. */
4001 uint64_t fGstAmd64MbzPdpeMask;
4002 /** Mask containing the MBZ big page PDPE bits. */
4003 uint64_t fGstAmd64MbzBigPdpeMask;
4004 /** Mask containing the MBZ PML4E bits. */
4005 uint64_t fGstAmd64MbzPml4eMask;
4006 /** Mask containing the PDPE bits that we shadow. */
4007 uint64_t fGstAmd64ShadowedPdpeMask;
4008 /** Mask containing the PML4E bits that we shadow. */
4009 uint64_t fGstAmd64ShadowedPml4eMask;
4010 /** @} */
4011
4012 /** @name PAE and AMD64 Guest Paging.
4013 * @{ */
4014 /** Mask containing the PTE bits that we shadow. */
4015 uint64_t fGst64ShadowedPteMask;
4016 /** Mask containing the PDE bits that we shadow. */
4017 uint64_t fGst64ShadowedPdeMask;
4018 /** Mask containing the big page PDE bits that we shadow in the PDE. */
4019 uint64_t fGst64ShadowedBigPdeMask;
4020 /** Mask containing the big page PDE bits that we shadow in the PTE. */
4021 uint64_t fGst64ShadowedBigPde4PteMask;
4022 /** @} */
4023
4024 /** Pointer to the page of the current active CR3 - R3 Ptr. */
4025 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
4026 /** Pointer to the page of the current active CR3 - R0 Ptr. */
4027 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
4028 /** Pointer to the page of the current active CR3 - RC Ptr. */
4029 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
4030# if HC_ARCH_BITS == 64
4031 RTRCPTR alignment6; /**< structure size alignment. */
4032# endif
4033 /** @} */
4034
4035 /** @name Function pointers for Shadow paging.
4036 * @{
4037 */
4038 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4039 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
4040 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
4041 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
4042
4043 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
4044 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
4045
4046 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
4047 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
4048
4049 /** @} */
4050
4051 /** @name Function pointers for Guest paging.
4052 * @{
4053 */
4054 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4055 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
4056 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4057 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4058 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4059 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4060 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4061 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4062#if HC_ARCH_BITS == 64
4063 RTRCPTR alignment3; /**< structure size alignment. */
4064#endif
4065
4066 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4067 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4068 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4069 /** @} */
4070
4071 /** @name Function pointers for Both Shadow and Guest paging.
4072 * @{
4073 */
4074 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4075 /* no pfnR3BthTrap0eHandler */
4076 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4077 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4078 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4079 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4080 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4081 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4082 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4083
4084 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4085 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4086 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4087 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4088 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4089 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4090 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4091 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4092
4093 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4094 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4095 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4096 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4097 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4098 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4099 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4100 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4101#if 0
4102 RTRCPTR alignment2; /**< structure size alignment. */
4103#endif
4104 /** @} */
4105
4106 /** For saving stack space, the disassembler state is allocated here instead of
4107 * on the stack. */
4108 DISCPUSTATE DisState;
4109
4110 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4111 uint64_t cNetwareWp0Hacks;
4112
4113 /** Count the number of pgm pool access handler calls. */
4114 uint64_t cPoolAccessHandler;
4115
4116 /** @name Release Statistics
4117 * @{ */
4118 /** The number of times the guest has switched mode since last reset or statistics reset. */
4119 STAMCOUNTER cGuestModeChanges;
4120 /** The number of times the guest has switched mode since last reset or statistics reset. */
4121 STAMCOUNTER cA20Changes;
4122 /** @} */
4123
4124#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4125 /** @name Statistics
4126 * @{ */
4127 /** RC: Pointer to the statistics. */
4128 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4129 /** RC: Which statistic this \#PF should be attributed to. */
4130 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4131 /** R0: Pointer to the statistics. */
4132 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4133 /** R0: Which statistic this \#PF should be attributed to. */
4134 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4135 /** R3: Pointer to the statistics. */
4136 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4137 /** Alignment padding. */
4138 RTR3PTR pPaddingR3;
4139 /** @} */
4140#endif /* VBOX_WITH_STATISTICS */
4141} PGMCPU;
4142/** Pointer to the per-cpu PGM data. */
4143typedef PGMCPU *PPGMCPU;
4144
4145
4146/** @name PGM::fSyncFlags Flags
4147 * @note Was part of saved state a long time ago.
4148 * @{
4149 */
4150/** Updates the virtual access handler state bit in PGMPAGE. */
4151#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4152/** Always sync CR3. */
4153#define PGM_SYNC_ALWAYS RT_BIT(1)
4154/** Check monitoring on next CR3 (re)load and invalidate page.
4155 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4156#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4157/** Check guest mapping in SyncCR3. */
4158#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4159/** Clear the page pool (a light weight flush). */
4160#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4161#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4162/** @} */
4163
4164
4165RT_C_DECLS_BEGIN
4166
4167#if defined(VBOX_STRICT) && defined(IN_RING3)
4168int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4169# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4170#else
4171int pgmLock(PVM pVM);
4172#endif
4173void pgmUnlock(PVM pVM);
4174/**
4175 * Asserts that the caller owns the PDM lock.
4176 * This is the internal variant of PGMIsLockOwner.
4177 * @param a_pVM Pointer to the VM.
4178 */
4179#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4180/**
4181 * Asserts that the caller owns the PDM lock.
4182 * This is the internal variant of PGMIsLockOwner.
4183 * @param a_pVM Pointer to the VM.
4184 * @param a_pVCpu The current CPU handle.
4185 */
4186#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4187
4188#ifndef PGM_WITHOUT_MAPPINGS
4189int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4190int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4191int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4192int pgmMapResolveConflicts(PVM pVM);
4193#endif /* !PGM_WITHOUT_MAPPINGS */
4194PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4195DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4196
4197int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4198 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
4199int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4200int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4201int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4202int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4203void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4204bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4205void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4206#ifdef VBOX_WITH_RAW_MODE
4207PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4208DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4209# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4210void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4211# else
4212# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4213# endif
4214#endif /* VBOX_WITH_RAW_MODE */
4215DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4216int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4217
4218int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4219int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4220int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4221int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4222int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4223void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4224int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4225int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4226int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4227int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4228int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4229int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4230int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4231int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4232int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4233int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4234void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4235PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4236#ifndef IN_RING3
4237DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4238DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4239DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4240#endif
4241int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4242 PGMPAGETYPE enmNewType);
4243void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4244void pgmPhysInvalidatePageMapTLB(PVM pVM);
4245void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4246PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4247PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4248PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4249int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4250int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4251
4252#ifdef IN_RING3
4253void pgmR3PhysRelinkRamRanges(PVM pVM);
4254int pgmR3PhysRamPreAllocate(PVM pVM);
4255int pgmR3PhysRamReset(PVM pVM);
4256int pgmR3PhysRomReset(PVM pVM);
4257int pgmR3PhysRamZeroAll(PVM pVM);
4258int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4259int pgmR3PhysRamTerm(PVM pVM);
4260void pgmR3PhysRomTerm(PVM pVM);
4261void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4262
4263int pgmR3PoolInit(PVM pVM);
4264void pgmR3PoolRelocate(PVM pVM);
4265void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4266void pgmR3PoolReset(PVM pVM);
4267void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4268DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4269void pgmR3PoolWriteProtectPages(PVM pVM);
4270
4271#endif /* IN_RING3 */
4272#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4273int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4274int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4275# ifdef LOG_ENABLED
4276void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4277# else
4278void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4279# endif
4280#endif
4281int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4282 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4283void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4284void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4285int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4286void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4287PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4288PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4289int pgmPoolSyncCR3(PVMCPU pVCpu);
4290bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4291void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4292int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4293void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4294uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4295void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4296int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4297void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4298PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4299#ifndef IN_RING3
4300DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4301#endif
4302
4303void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4304void pgmPoolResetDirtyPages(PVM pVM);
4305void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4306
4307int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4308int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4309void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4310
4311void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4312void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4313int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4314int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4315
4316int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4317int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4318int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4319
4320int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4321int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4322int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4323int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4324int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4325
4326# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4327FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4328FNDBGCCMD pgmR3CmdShowSharedModules;
4329# endif
4330
4331void pgmLogState(PVM pVM);
4332
4333RT_C_DECLS_END
4334
4335/** @} */
4336
4337#endif
4338
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