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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 76553

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1/* $Id: PGMInternal.h 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Indicates that there are no guest mappings in the shadow tables.
62 *
63 * Note! In ring-3 the macro is also used to exclude the managment of the
64 * intermediate context page tables. On 32-bit systems we use the intermediate
65 * context to support 64-bit guest execution. Thus, we cannot fully make it
66 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67 *
68 * In raw-mode context there are by design always guest mappings (the code is
69 * executed from one), while in ring-0 there are none at all. Neither context
70 * manages the page tables for intermediate switcher context, that's all done in
71 * ring-3.
72 */
73#if defined(IN_RING0) \
74 || ( !defined(VBOX_WITH_RAW_MODE) \
75 && ( HC_ARCH_BITS != 32 \
76 || !defined(VBOX_WITH_64_BITS_GUESTS) \
77 ) \
78 )
79# define PGM_WITHOUT_MAPPINGS
80#endif
81
82/**
83 * Check and skip global PDEs for non-global flushes
84 */
85#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
86
87/**
88 * Optimization for PAE page tables that are modified often
89 */
90//#if 0 /* disabled again while debugging */
91#ifndef IN_RC
92# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
93#endif
94//#endif
95
96/**
97 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
98 */
99#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
100# define PGM_WITH_LARGE_PAGES
101#endif
102
103/**
104 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
105 * VMX_EXIT_EPT_MISCONFIG.
106 */
107#if 1 /* testing */
108# define PGM_WITH_MMIO_OPTIMIZATIONS
109#endif
110
111/**
112 * Sync N pages instead of a whole page table
113 */
114#define PGM_SYNC_N_PAGES
115
116/**
117 * Number of pages to sync during a page fault
118 *
119 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
120 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
121 *
122 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
123 * world switch overhead, so let's sync more.
124 */
125# ifdef IN_RING0
126/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
127 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
128 * but ~5% fewer faults.
129 */
130# define PGM_SYNC_NR_PAGES 32
131#else
132# define PGM_SYNC_NR_PAGES 8
133#endif
134
135/**
136 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
137 */
138#define PGM_MAX_PHYSCACHE_ENTRIES 64
139#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
140
141
142/** @def PGMPOOL_CFG_MAX_GROW
143 * The maximum number of pages to add to the pool in one go.
144 */
145#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
146
147/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
148 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
149 */
150#ifdef VBOX_STRICT
151# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
152#endif
153
154/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155 * Enables the experimental lazy page allocation code. */
156#ifdef DOXYGEN_RUNNING
157# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
158#endif
159
160/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161 * Enables real write monitoring of pages, i.e. mapping them read-only and
162 * only making them writable when getting a write access \#PF. */
163#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Indicates the original entry was a big page.
184 * @remarks This is currently only used for statistics and can be recycled. */
185#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
186/** Mapping (hypervisor allocated pagetable). */
187#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
188/** Made read-only to facilitate dirty bit tracking. */
189#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
190/** @} */
191
192/** @name Page flags.
193 * These are placed in the three bits available for system programs in
194 * the page entries.
195 * @{ */
196/** Made read-only to facilitate dirty bit tracking. */
197#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
198
199#ifndef PGM_PTFLAGS_CSAM_VALIDATED
200/** Scanned and approved by CSAM (tm).
201 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
202 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
203#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
204#endif
205
206/** @} */
207
208/** @name Defines used to indicate the shadow and guest paging in the templates.
209 * @{ */
210#define PGM_TYPE_REAL 1
211#define PGM_TYPE_PROT 2
212#define PGM_TYPE_32BIT 3
213#define PGM_TYPE_PAE 4
214#define PGM_TYPE_AMD64 5
215#define PGM_TYPE_NESTED_32BIT 6
216#define PGM_TYPE_NESTED_PAE 7
217#define PGM_TYPE_NESTED_AMD64 8
218#define PGM_TYPE_EPT 9
219#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
220#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
221#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
222/** @} */
223
224/** Macro for checking if the guest is using paging.
225 * @param uGstType PGM_TYPE_*
226 * @param uShwType PGM_TYPE_*
227 * @remark ASSUMES certain order of the PGM_TYPE_* values.
228 */
229#define PGM_WITH_PAGING(uGstType, uShwType) \
230 ( (uGstType) >= PGM_TYPE_32BIT \
231 && (uShwType) < PGM_TYPE_NESTED_32BIT)
232
233/** Macro for checking if the guest supports the NX bit.
234 * @param uGstType PGM_TYPE_*
235 * @param uShwType PGM_TYPE_*
236 * @remark ASSUMES certain order of the PGM_TYPE_* values.
237 */
238#define PGM_WITH_NX(uGstType, uShwType) \
239 ( (uGstType) >= PGM_TYPE_PAE \
240 && (uShwType) < PGM_TYPE_NESTED_32BIT)
241
242/** Macro for checking for nested or EPT.
243 * @param uType PGM_TYPE_*
244 */
245#define PGM_TYPE_IS_NESTED(uType) \
246 ( (uType) == PGM_TYPE_NESTED_32BIT \
247 || (uType) == PGM_TYPE_NESTED_PAE \
248 || (uType) == PGM_TYPE_NESTED_AMD64)
249
250/** Macro for checking for nested or EPT.
251 * @param uType PGM_TYPE_*
252 */
253#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
254 ( (uType) == PGM_TYPE_NESTED_32BIT \
255 || (uType) == PGM_TYPE_NESTED_PAE \
256 || (uType) == PGM_TYPE_NESTED_AMD64 \
257 || (uType) == PGM_TYPE_EPT)
258
259
260
261/** @def PGM_HCPHYS_2_PTR
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pVM The cross context VM structure.
266 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
267 * @param HCPhys The HC physical address to map to a virtual one.
268 * @param ppv Where to store the virtual address. No need to cast
269 * this.
270 *
271 * @remark Use with care as we don't have so much dynamic mapping space in
272 * ring-0 on 32-bit darwin and in RC.
273 * @remark There is no need to assert on the result.
274 */
275#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
276# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
277 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
278#else
279# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
280 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
281#endif
282
283/** @def PGM_GCPHYS_2_PTR_V2
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVM The cross context VM structure.
288 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark Use with care as we don't have so much dynamic mapping space in
293 * ring-0 on 32-bit darwin and in RC.
294 * @remark There is no need to assert on the result.
295 */
296#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
297# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
298 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
299#else
300# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
301 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pVM The cross context VM structure.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark Use with care as we don't have so much dynamic mapping space in
313 * ring-0 on 32-bit darwin and in RC.
314 * @remark There is no need to assert on the result.
315 */
316#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
317
318/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
319 * Maps a GC physical page address to a virtual address.
320 *
321 * @returns VBox status code.
322 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
323 * @param GCPhys The GC physical address to map to a virtual one.
324 * @param ppv Where to store the virtual address. No need to cast this.
325 *
326 * @remark Use with care as we don't have so much dynamic mapping space in
327 * ring-0 on 32-bit darwin and in RC.
328 * @remark There is no need to assert on the result.
329 */
330#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
331
332/** @def PGM_GCPHYS_2_PTR_EX
333 * Maps a unaligned GC physical page address to a virtual address.
334 *
335 * @returns VBox status code.
336 * @param pVM The cross context VM structure.
337 * @param GCPhys The GC physical address to map to a virtual one.
338 * @param ppv Where to store the virtual address. No need to cast this.
339 *
340 * @remark Use with care as we don't have so much dynamic mapping space in
341 * ring-0 on 32-bit darwin and in RC.
342 * @remark There is no need to assert on the result.
343 */
344#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
345# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
346 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
347#else
348# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
349 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
350#endif
351
352/** @def PGM_DYNMAP_UNUSED_HINT
353 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
354 * is no longer used.
355 *
356 * For best effect only apply this to the page that was mapped most recently.
357 *
358 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
359 * @param pvPage The pool page.
360 */
361#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
362# ifdef LOG_ENABLED
363# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
364# else
365# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
366# endif
367#else
368# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
369#endif
370
371/** @def PGM_DYNMAP_UNUSED_HINT_VM
372 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
373 * is no longer used.
374 *
375 * For best effect only apply this to the page that was mapped most recently.
376 *
377 * @param pVM The cross context VM structure.
378 * @param pvPage The pool page.
379 */
380#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
381
382
383/** @def PGM_INVL_PG
384 * Invalidates a page.
385 *
386 * @param pVCpu The cross context virtual CPU structure.
387 * @param GCVirt The virtual address of the page to invalidate.
388 */
389#ifdef IN_RC
390# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
391#elif defined(IN_RING0)
392# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
393#else
394# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
395#endif
396
397/** @def PGM_INVL_PG_ALL_VCPU
398 * Invalidates a page on all VCPUs
399 *
400 * @param pVM The cross context VM structure.
401 * @param GCVirt The virtual address of the page to invalidate.
402 */
403#ifdef IN_RC
404# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
405#elif defined(IN_RING0)
406# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
407#else
408# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
409#endif
410
411/** @def PGM_INVL_BIG_PG
412 * Invalidates a 4MB page directory entry.
413 *
414 * @param pVCpu The cross context virtual CPU structure.
415 * @param GCVirt The virtual address within the page directory to invalidate.
416 */
417#ifdef IN_RC
418# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
419#elif defined(IN_RING0)
420# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
421#else
422# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
423#endif
424
425/** @def PGM_INVL_VCPU_TLBS()
426 * Invalidates the TLBs of the specified VCPU
427 *
428 * @param pVCpu The cross context virtual CPU structure.
429 */
430#ifdef IN_RC
431# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
432#elif defined(IN_RING0)
433# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
434#else
435# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
436#endif
437
438/** @def PGM_INVL_ALL_VCPU_TLBS()
439 * Invalidates the TLBs of all VCPUs
440 *
441 * @param pVM The cross context VM structure.
442 */
443#ifdef IN_RC
444# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
445#elif defined(IN_RING0)
446# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
447#else
448# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
449#endif
450
451
452/** @name Safer Shadow PAE PT/PTE
453 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
454 * present.
455 *
456 * @{
457 */
458#if 1
459/**
460 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
461 * invalid entries for present.
462 * @sa X86PTEPAE.
463 */
464typedef union PGMSHWPTEPAE
465{
466 /** Unsigned integer view */
467 X86PGPAEUINT uCareful;
468 /* Not other views. */
469} PGMSHWPTEPAE;
470
471# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
472# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
473# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
474# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
475# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
476# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
477# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
478# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
479# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
480# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
481# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
482# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
483# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
484# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
485# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
486# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
487
488/**
489 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
490 * invalid entries for present.
491 * @sa X86PTPAE.
492 */
493typedef struct PGMSHWPTPAE
494{
495 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
496} PGMSHWPTPAE;
497
498#else
499typedef X86PTEPAE PGMSHWPTEPAE;
500typedef X86PTPAE PGMSHWPTPAE;
501# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
502# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
503# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
504# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
505# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
506# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
507# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
508# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
509# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
510# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
511# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
512# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
513# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
514# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
515# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
516# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
517
518#endif
519
520/** Pointer to a shadow PAE PTE. */
521typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
522/** Pointer to a const shadow PAE PTE. */
523typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
524
525/** Pointer to a shadow PAE page table. */
526typedef PGMSHWPTPAE *PPGMSHWPTPAE;
527/** Pointer to a const shadow PAE page table. */
528typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
529/** @} */
530
531
532/** Size of the GCPtrConflict array in PGMMAPPING.
533 * @remarks Must be a power of two. */
534#define PGMMAPPING_CONFLICT_MAX 8
535
536/**
537 * Structure for tracking GC Mappings.
538 *
539 * This structure is used by linked list in both GC and HC.
540 */
541typedef struct PGMMAPPING
542{
543 /** Pointer to next entry. */
544 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
545 /** Pointer to next entry. */
546 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
547 /** Pointer to next entry. */
548 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
549 /** Indicate whether this entry is finalized. */
550 bool fFinalized;
551 /** Start Virtual address. */
552 RTGCPTR GCPtr;
553 /** Last Virtual address (inclusive). */
554 RTGCPTR GCPtrLast;
555 /** Range size (bytes). */
556 RTGCPTR cb;
557 /** Pointer to relocation callback function. */
558 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
559 /** User argument to the callback. */
560 R3PTRTYPE(void *) pvUser;
561 /** Mapping description / name. For easing debugging. */
562 R3PTRTYPE(const char *) pszDesc;
563 /** Last 8 addresses that caused conflicts. */
564 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
565 /** Number of conflicts for this hypervisor mapping. */
566 uint32_t cConflicts;
567 /** Number of page tables. */
568 uint32_t cPTs;
569
570 /** Array of page table mapping data. Each entry
571 * describes one page table. The array can be longer
572 * than the declared length.
573 */
574 struct
575 {
576 /** The HC physical address of the page table. */
577 RTHCPHYS HCPhysPT;
578 /** The HC physical address of the first PAE page table. */
579 RTHCPHYS HCPhysPaePT0;
580 /** The HC physical address of the second PAE page table. */
581 RTHCPHYS HCPhysPaePT1;
582 /** The HC virtual address of the 32-bit page table. */
583 R3PTRTYPE(PX86PT) pPTR3;
584 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
585 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
586 /** The RC virtual address of the 32-bit page table. */
587 RCPTRTYPE(PX86PT) pPTRC;
588 /** The RC virtual address of the two PAE page table. */
589 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
590 /** The R0 virtual address of the 32-bit page table. */
591 R0PTRTYPE(PX86PT) pPTR0;
592 /** The R0 virtual address of the two PAE page table. */
593 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
594 } aPTs[1];
595} PGMMAPPING;
596/** Pointer to structure for tracking GC Mappings. */
597typedef struct PGMMAPPING *PPGMMAPPING;
598
599
600/**
601 * Physical page access handler type registration.
602 */
603typedef struct PGMPHYSHANDLERTYPEINT
604{
605 /** Number of references. */
606 uint32_t volatile cRefs;
607 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
608 uint32_t u32Magic;
609 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
610 RTLISTOFF32NODE ListNode;
611 /** The kind of accesses we're handling. */
612 PGMPHYSHANDLERKIND enmKind;
613 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
614 uint32_t uState;
615 /** Pointer to RC callback function. */
616 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
617 /** Pointer to RC callback function for \#PFs. */
618 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
619 /** Pointer to R3 callback function. */
620 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
621 /** Pointer to R0 callback function. */
622 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
623 /** Pointer to R0 callback function for \#PFs. */
624 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
625 /** Description / Name. For easing debugging. */
626 R3PTRTYPE(const char *) pszDesc;
627} PGMPHYSHANDLERTYPEINT;
628/** Pointer to a physical access handler type registration. */
629typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
630/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
631#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
632/** Magic value for the physical handler callbacks. */
633#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
634
635/**
636 * Converts a handle to a pointer.
637 * @returns PPGMPHYSHANDLERTYPEINT
638 * @param a_pVM The cross context VM structure.
639 * @param a_hType Physical access handler type handle.
640 */
641#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
642
643
644/**
645 * Physical page access handler structure.
646 *
647 * This is used to keep track of physical address ranges
648 * which are being monitored in some kind of way.
649 */
650typedef struct PGMPHYSHANDLER
651{
652 AVLROGCPHYSNODECORE Core;
653 /** Number of pages to update. */
654 uint32_t cPages;
655 /** Set if we have pages that have been aliased. */
656 uint32_t cAliasedPages;
657 /** Set if we have pages that have temporarily been disabled. */
658 uint32_t cTmpOffPages;
659 /** Registered handler type handle (heap offset). */
660 PGMPHYSHANDLERTYPE hType;
661 /** User argument for RC handlers. */
662 RCPTRTYPE(void *) pvUserRC;
663#if HC_ARCH_BITS == 64
664 RTRCPTR Padding0; /**< Explicit alignment padding. */
665#endif
666 /** User argument for R3 handlers. */
667 R3PTRTYPE(void *) pvUserR3;
668 /** User argument for R0 handlers. */
669 R0PTRTYPE(void *) pvUserR0;
670 /** Description / Name. For easing debugging. */
671 R3PTRTYPE(const char *) pszDesc;
672#ifdef VBOX_WITH_STATISTICS
673 /** Profiling of this handler. */
674 STAMPROFILE Stat;
675#endif
676} PGMPHYSHANDLER;
677/** Pointer to a physical page access handler structure. */
678typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
679
680/**
681 * Gets the type record for a physical handler (no reference added).
682 * @returns PPGMPHYSHANDLERTYPEINT
683 * @param a_pVM The cross context VM structure.
684 * @param a_pPhysHandler Pointer to the physical handler structure
685 * (PGMPHYSHANDLER).
686 */
687#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
688
689
690#ifdef VBOX_WITH_RAW_MODE
691
692/**
693 * Cache node for the physical addresses covered by a virtual handler.
694 */
695typedef struct PGMPHYS2VIRTHANDLER
696{
697 /** Core node for the tree based on physical ranges. */
698 AVLROGCPHYSNODECORE Core;
699 /** Offset from this struct to the PGMVIRTHANDLER structure. */
700 int32_t offVirtHandler;
701 /** Offset of the next alias relative to this one.
702 * Bit 0 is used for indicating whether we're in the tree.
703 * Bit 1 is used for indicating that we're the head node.
704 */
705 int32_t offNextAlias;
706} PGMPHYS2VIRTHANDLER;
707/** Pointer to a phys to virtual handler structure. */
708typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
709
710/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
711 * node is in the tree. */
712# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
713/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
714 * node is in the head of an alias chain.
715 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
716# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
717/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
718# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
719
720
721/**
722 * Virtual page access handler type registration.
723 */
724typedef struct PGMVIRTANDLERTYPEINT
725{
726 /** Number of references. */
727 uint32_t volatile cRefs;
728 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
729 uint32_t u32Magic;
730 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
731 RTLISTOFF32NODE ListNode;
732 /** The kind of accesses we're handling. */
733 PGMVIRTHANDLERKIND enmKind;
734 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
735 uint32_t uState;
736 /** Whether the pvUserRC argument should be automatically relocated or not. */
737 bool fRelocUserRC;
738 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
739 /** Pointer to RC callback function. */
740 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
741 /** Pointer to RC callback function for \#PFs. */
742 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
743 /** Pointer to the R3 callback function for invalidation. */
744 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
745 /** Pointer to R3 callback function. */
746 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
747 /** Description / Name. For easing debugging. */
748 R3PTRTYPE(const char *) pszDesc;
749} PGMVIRTHANDLERTYPEINT;
750/** Pointer to a virtual access handler type registration. */
751typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
752/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
753# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
754/** Magic value for the virtual handler callbacks. */
755# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
756
757/**
758 * Converts a handle to a pointer.
759 * @returns PPGMVIRTHANDLERTYPEINT
760 * @param a_pVM The cross context VM structure.
761 * @param a_hType Vitual access handler type handle.
762 */
763# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
764
765
766/**
767 * Virtual page access handler structure.
768 *
769 * This is used to keep track of virtual address ranges
770 * which are being monitored in some kind of way.
771 */
772typedef struct PGMVIRTHANDLER
773{
774 /** Core node for the tree based on virtual ranges. */
775 AVLROGCPTRNODECORE Core;
776 /** Size of the range (in bytes). */
777 uint32_t cb;
778 /** Number of cache pages. */
779 uint32_t cPages;
780 /** Registered handler type handle (heap offset). */
781 PGMVIRTHANDLERTYPE hType;
782 /** User argument for RC handlers. */
783 RCPTRTYPE(void *) pvUserRC;
784 /** User argument for R3 handlers. */
785 R3PTRTYPE(void *) pvUserR3;
786 /** Description / Name. For easing debugging. */
787 R3PTRTYPE(const char *) pszDesc;
788# ifdef VBOX_WITH_STATISTICS
789 /** Profiling of this handler. */
790 STAMPROFILE Stat;
791# endif
792 /** Array of cached physical addresses for the monitored ranged. */
793 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
794} PGMVIRTHANDLER;
795/** Pointer to a virtual page access handler structure. */
796typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
797
798/**
799 * Gets the type record for a virtual handler (no reference added).
800 * @returns PPGMVIRTHANDLERTYPEINT
801 * @param a_pVM The cross context VM structure.
802 * @param a_pVirtHandler Pointer to the virtual handler structure
803 * (PGMVIRTHANDLER).
804 */
805# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
806
807#endif /* VBOX_WITH_RAW_MODE */
808
809
810/**
811 * A Physical Guest Page tracking structure.
812 *
813 * The format of this structure is complicated because we have to fit a lot
814 * of information into as few bits as possible. The format is also subject
815 * to change (there is one coming up soon). Which means that for we'll be
816 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
817 * accesses to the structure.
818 */
819typedef union PGMPAGE
820{
821 /** Structured view. */
822 struct
823 {
824 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
825 uint64_t u2HandlerPhysStateY : 2;
826 /** 3:2 - Paging structure needed to map the page
827 * (PGM_PAGE_PDE_TYPE_*). */
828 uint64_t u2PDETypeY : 2;
829 /** 4 - Indicator of dirty page for fault tolerance tracking. */
830 uint64_t fFTDirtyY : 1;
831 /** 5 - Flag indicating that a write monitored page was written to
832 * when set. */
833 uint64_t fWrittenToY : 1;
834 /** 7:6 - Unused. */
835 uint64_t u2Unused0 : 2;
836 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
837 uint64_t u2HandlerVirtStateY : 2;
838 /** 11:10 - NEM state bits. */
839 uint64_t u2NemStateY : 2;
840 /** 12:48 - The host physical frame number (shift left to get the
841 * address). */
842 uint64_t HCPhysFN : 36;
843 /** 50:48 - The page state. */
844 uint64_t uStateY : 3;
845 /** 51:53 - The page type (PGMPAGETYPE). */
846 uint64_t uTypeY : 3;
847 /** 63:54 - PTE index for usage tracking (page pool). */
848 uint64_t u10PteIdx : 10;
849
850 /** The GMM page ID.
851 * @remarks In the current implementation, MMIO2 and pages aliased to
852 * MMIO2 pages will be exploiting this field to calculate the
853 * ring-3 mapping address corresponding to the page.
854 * Later we may consider including MMIO2 management into GMM. */
855 uint32_t idPage;
856 /** Usage tracking (page pool). */
857 uint16_t u16TrackingY;
858 /** The number of read locks on this page. */
859 uint8_t cReadLocksY;
860 /** The number of write locks on this page. */
861 uint8_t cWriteLocksY;
862 } s;
863
864 /** 64-bit integer view. */
865 uint64_t au64[2];
866 /** 16-bit view. */
867 uint32_t au32[4];
868 /** 16-bit view. */
869 uint16_t au16[8];
870 /** 8-bit view. */
871 uint8_t au8[16];
872} PGMPAGE;
873AssertCompileSize(PGMPAGE, 16);
874/** Pointer to a physical guest page. */
875typedef PGMPAGE *PPGMPAGE;
876/** Pointer to a const physical guest page. */
877typedef const PGMPAGE *PCPGMPAGE;
878/** Pointer to a physical guest page pointer. */
879typedef PPGMPAGE *PPPGMPAGE;
880
881
882/**
883 * Clears the page structure.
884 * @param a_pPage Pointer to the physical guest page tracking structure.
885 */
886#define PGM_PAGE_CLEAR(a_pPage) \
887 do { \
888 (a_pPage)->au64[0] = 0; \
889 (a_pPage)->au64[1] = 0; \
890 } while (0)
891
892/**
893 * Initializes the page structure.
894 * @param a_pPage Pointer to the physical guest page tracking structure.
895 * @param a_HCPhys The host physical address of the page.
896 * @param a_idPage The (GMM) page ID of the page.
897 * @param a_uType The page type (PGMPAGETYPE).
898 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
899 */
900#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
901 do { \
902 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
903 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
904 (a_pPage)->au64[0] = SetHCPhysTmp; \
905 (a_pPage)->au64[1] = 0; \
906 (a_pPage)->s.idPage = (a_idPage); \
907 (a_pPage)->s.uStateY = (a_uState); \
908 (a_pPage)->s.uTypeY = (a_uType); \
909 } while (0)
910
911/**
912 * Initializes the page structure of a ZERO page.
913 * @param a_pPage Pointer to the physical guest page tracking structure.
914 * @param a_pVM The VM handle (for getting the zero page address).
915 * @param a_uType The page type (PGMPAGETYPE).
916 */
917#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
918 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
919
920
921/** @name The Page state, PGMPAGE::uStateY.
922 * @{ */
923/** The zero page.
924 * This is a per-VM page that's never ever mapped writable. */
925#define PGM_PAGE_STATE_ZERO 0U
926/** A allocated page.
927 * This is a per-VM page allocated from the page pool (or wherever
928 * we get MMIO2 pages from if the type is MMIO2).
929 */
930#define PGM_PAGE_STATE_ALLOCATED 1U
931/** A allocated page that's being monitored for writes.
932 * The shadow page table mappings are read-only. When a write occurs, the
933 * fWrittenTo member is set, the page remapped as read-write and the state
934 * moved back to allocated. */
935#define PGM_PAGE_STATE_WRITE_MONITORED 2U
936/** The page is shared, aka. copy-on-write.
937 * This is a page that's shared with other VMs. */
938#define PGM_PAGE_STATE_SHARED 3U
939/** The page is ballooned, so no longer available for this VM. */
940#define PGM_PAGE_STATE_BALLOONED 4U
941/** @} */
942
943
944/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
945#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
946# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
947#else
948# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
949#endif
950
951/**
952 * Gets the page state.
953 * @returns page state (PGM_PAGE_STATE_*).
954 * @param a_pPage Pointer to the physical guest page tracking structure.
955 *
956 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
957 * builds.
958 */
959#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
960#if defined(__GNUC__) && defined(VBOX_STRICT)
961# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
962#else
963# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
964#endif
965
966/**
967 * Sets the page state.
968 * @param a_pVM The VM handle, only used for lock ownership assertions.
969 * @param a_pPage Pointer to the physical guest page tracking structure.
970 * @param a_uState The new page state.
971 */
972#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
973 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
974
975
976/**
977 * Gets the host physical address of the guest page.
978 * @returns host physical address (RTHCPHYS).
979 * @param a_pPage Pointer to the physical guest page tracking structure.
980 *
981 * @remarks In strict builds on gcc platforms, this macro will make some ugly
982 * assumption about a valid pVM variable/parameter being in the
983 * current context. It will use this pVM variable to assert that the
984 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
985 * pVM is not around.
986 */
987#if 0
988# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
989# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
990#else
991# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
992# if defined(__GNUC__) && defined(VBOX_STRICT)
993# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
994# else
995# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
996# endif
997#endif
998
999/**
1000 * Sets the host physical address of the guest page.
1001 *
1002 * @param a_pVM The VM handle, only used for lock ownership assertions.
1003 * @param a_pPage Pointer to the physical guest page tracking structure.
1004 * @param a_HCPhys The new host physical address.
1005 */
1006#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
1007 do { \
1008 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
1009 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
1010 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
1011 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1012 } while (0)
1013
1014/**
1015 * Get the Page ID.
1016 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1020
1021/**
1022 * Sets the Page ID.
1023 * @param a_pVM The VM handle, only used for lock ownership assertions.
1024 * @param a_pPage Pointer to the physical guest page tracking structure.
1025 * @param a_idPage The new page ID.
1026 */
1027#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1028 do { \
1029 (a_pPage)->s.idPage = (a_idPage); \
1030 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1031 } while (0)
1032
1033/**
1034 * Get the Chunk ID.
1035 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1036 * @param a_pPage Pointer to the physical guest page tracking structure.
1037 */
1038#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1039
1040/**
1041 * Get the index of the page within the allocation chunk.
1042 * @returns The page index.
1043 * @param a_pPage Pointer to the physical guest page tracking structure.
1044 */
1045#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1046
1047/**
1048 * Gets the page type.
1049 * @returns The page type.
1050 * @param a_pPage Pointer to the physical guest page tracking structure.
1051 *
1052 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1053 * builds.
1054 */
1055#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1056#if defined(__GNUC__) && defined(VBOX_STRICT)
1057# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1058#else
1059# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1060#endif
1061
1062/**
1063 * Sets the page type.
1064 *
1065 * @param a_pVM The VM handle, only used for lock ownership assertions.
1066 * @param a_pPage Pointer to the physical guest page tracking structure.
1067 * @param a_enmType The new page type (PGMPAGETYPE).
1068 */
1069#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1070 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1071
1072/**
1073 * Gets the page table index
1074 * @returns The page table index.
1075 * @param a_pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1078
1079/**
1080 * Sets the page table index.
1081 * @param a_pVM The VM handle, only used for lock ownership assertions.
1082 * @param a_pPage Pointer to the physical guest page tracking structure.
1083 * @param a_iPte New page table index.
1084 */
1085#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1086 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1087
1088/**
1089 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1090 * @returns true/false.
1091 * @param a_pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1094
1095/**
1096 * Checks if the page is marked for MMIO, including both aliases.
1097 * @returns true/false.
1098 * @param a_pPage Pointer to the physical guest page tracking structure.
1099 */
1100#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1101 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1102 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1103 )
1104
1105/**
1106 * Checks if the page is marked for MMIO, including special aliases.
1107 * @returns true/false.
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 */
1110#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1111 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1112
1113/**
1114 * Checks if the page is a special aliased MMIO page.
1115 * @returns true/false.
1116 * @param a_pPage Pointer to the physical guest page tracking structure.
1117 */
1118#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1119
1120/**
1121 * Checks if the page is backed by the ZERO page.
1122 * @returns true/false.
1123 * @param a_pPage Pointer to the physical guest page tracking structure.
1124 */
1125#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1126
1127/**
1128 * Checks if the page is backed by a SHARED page.
1129 * @returns true/false.
1130 * @param a_pPage Pointer to the physical guest page tracking structure.
1131 */
1132#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1133
1134/**
1135 * Checks if the page is ballooned.
1136 * @returns true/false.
1137 * @param a_pPage Pointer to the physical guest page tracking structure.
1138 */
1139#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1140
1141/**
1142 * Checks if the page is allocated.
1143 * @returns true/false.
1144 * @param a_pPage Pointer to the physical guest page tracking structure.
1145 */
1146#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1147
1148/**
1149 * Marks the page as written to (for GMM change monitoring).
1150 * @param a_pVM The VM handle, only used for lock ownership assertions.
1151 * @param a_pPage Pointer to the physical guest page tracking structure.
1152 */
1153#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1154 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1155
1156/**
1157 * Clears the written-to indicator.
1158 * @param a_pVM The VM handle, only used for lock ownership assertions.
1159 * @param a_pPage Pointer to the physical guest page tracking structure.
1160 */
1161#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1162 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1163
1164/**
1165 * Checks if the page was marked as written-to.
1166 * @returns true/false.
1167 * @param a_pPage Pointer to the physical guest page tracking structure.
1168 */
1169#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1170
1171/**
1172 * Marks the page as dirty for FTM
1173 * @param a_pPage Pointer to the physical guest page tracking structure.
1174 */
1175#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1176
1177/**
1178 * Clears the FTM dirty indicator
1179 * @param a_pPage Pointer to the physical guest page tracking structure.
1180 */
1181#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1182
1183/**
1184 * Checks if the page was marked as dirty for FTM
1185 * @returns true/false.
1186 * @param a_pPage Pointer to the physical guest page tracking structure.
1187 */
1188#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1189
1190
1191/** @name PT usage values (PGMPAGE::u2PDEType).
1192 *
1193 * @{ */
1194/** Either as a PT or PDE. */
1195#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1196/** Must use a page table to map the range. */
1197#define PGM_PAGE_PDE_TYPE_PT 1
1198/** Can use a page directory entry to map the continuous range. */
1199#define PGM_PAGE_PDE_TYPE_PDE 2
1200/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1201#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1202/** @} */
1203
1204/**
1205 * Set the PDE type of the page
1206 * @param a_pVM The VM handle, only used for lock ownership assertions.
1207 * @param a_pPage Pointer to the physical guest page tracking structure.
1208 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1209 */
1210#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1211 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1212
1213/**
1214 * Checks if the page was marked being part of a large page
1215 * @returns true/false.
1216 * @param a_pPage Pointer to the physical guest page tracking structure.
1217 */
1218#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1219
1220/** Enabled optimized access handler tests.
1221 * These optimizations makes ASSUMPTIONS about the state values and the s1
1222 * layout. When enabled, the compiler should normally generate more compact
1223 * code.
1224 */
1225#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1226
1227/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1228 *
1229 * @remarks The values are assigned in order of priority, so we can calculate
1230 * the correct state for a page with different handlers installed.
1231 * @{ */
1232/** No handler installed. */
1233#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1234/** Monitoring is temporarily disabled. */
1235#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1236/** Write access is monitored. */
1237#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1238/** All access is monitored. */
1239#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1240/** @} */
1241
1242/**
1243 * Gets the physical access handler state of a page.
1244 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1245 * @param a_pPage Pointer to the physical guest page tracking structure.
1246 */
1247#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1248
1249/**
1250 * Sets the physical access handler state of a page.
1251 * @param a_pPage Pointer to the physical guest page tracking structure.
1252 * @param a_uState The new state value.
1253 */
1254#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1255 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1256
1257/**
1258 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1259 * @returns true/false
1260 * @param a_pPage Pointer to the physical guest page tracking structure.
1261 */
1262#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1263 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1264
1265/**
1266 * Checks if the page has any active physical access handlers.
1267 * @returns true/false
1268 * @param a_pPage Pointer to the physical guest page tracking structure.
1269 */
1270#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1271 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1272
1273
1274/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1275 *
1276 * @remarks The values are assigned in order of priority, so we can calculate
1277 * the correct state for a page with different handlers installed.
1278 * @{ */
1279/** No handler installed. */
1280#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1281/* 1 is reserved so the lineup is identical with the physical ones. */
1282/** Write access is monitored. */
1283#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1284/** All access is monitored. */
1285#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1286/** @} */
1287
1288/**
1289 * Gets the virtual access handler state of a page.
1290 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1291 * @param a_pPage Pointer to the physical guest page tracking structure.
1292 */
1293#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1294
1295/**
1296 * Sets the virtual access handler state of a page.
1297 * @param a_pPage Pointer to the physical guest page tracking structure.
1298 * @param a_uState The new state value.
1299 */
1300#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1301 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1302
1303/**
1304 * Checks if the page has any virtual access handlers.
1305 * @returns true/false
1306 * @param a_pPage Pointer to the physical guest page tracking structure.
1307 */
1308#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1309 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1310
1311/**
1312 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1313 * virtual handlers.
1314 * @returns true/false
1315 * @param a_pPage Pointer to the physical guest page tracking structure.
1316 */
1317#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1318 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1319
1320
1321/**
1322 * Checks if the page has any access handlers, including temporarily disabled ones.
1323 * @returns true/false
1324 * @param a_pPage Pointer to the physical guest page tracking structure.
1325 */
1326#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1327# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1328 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1329#else
1330# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1331 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1332 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1333#endif
1334
1335/**
1336 * Checks if the page has any active access handlers.
1337 * @returns true/false
1338 * @param a_pPage Pointer to the physical guest page tracking structure.
1339 */
1340#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1341# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1342 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1343#else
1344# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1345 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1346 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1347#endif
1348
1349/**
1350 * Checks if the page has any active access handlers catching all accesses.
1351 * @returns true/false
1352 * @param a_pPage Pointer to the physical guest page tracking structure.
1353 */
1354#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1355# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1356 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1357 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1358#else
1359# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1360 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1361 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1362#endif
1363
1364
1365/** @def PGM_PAGE_GET_TRACKING
1366 * Gets the packed shadow page pool tracking data associated with a guest page.
1367 * @returns uint16_t containing the data.
1368 * @param a_pPage Pointer to the physical guest page tracking structure.
1369 */
1370#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1371#if defined(__GNUC__) && defined(VBOX_STRICT)
1372# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1373#else
1374# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1375#endif
1376
1377/** @def PGM_PAGE_SET_TRACKING
1378 * Sets the packed shadow page pool tracking data associated with a guest page.
1379 * @param a_pVM The VM handle, only used for lock ownership assertions.
1380 * @param a_pPage Pointer to the physical guest page tracking structure.
1381 * @param a_u16TrackingData The tracking data to store.
1382 */
1383#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1384 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1385
1386/** @def PGM_PAGE_GET_TD_CREFS
1387 * Gets the @a cRefs tracking data member.
1388 * @returns cRefs.
1389 * @param a_pPage Pointer to the physical guest page tracking structure.
1390 */
1391#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1392 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1393#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1394 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1395
1396/** @def PGM_PAGE_GET_TD_IDX
1397 * Gets the @a idx tracking data member.
1398 * @returns idx.
1399 * @param a_pPage Pointer to the physical guest page tracking structure.
1400 */
1401#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1402 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1403#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1404 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1405
1406
1407/** Max number of locks on a page. */
1408#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1409
1410/** Get the read lock count.
1411 * @returns count.
1412 * @param a_pPage Pointer to the physical guest page tracking structure.
1413 */
1414#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1415
1416/** Get the write lock count.
1417 * @returns count.
1418 * @param a_pPage Pointer to the physical guest page tracking structure.
1419 */
1420#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1421
1422/** Decrement the read lock counter.
1423 * @param a_pPage Pointer to the physical guest page tracking structure.
1424 */
1425#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1426
1427/** Decrement the write lock counter.
1428 * @param a_pPage Pointer to the physical guest page tracking structure.
1429 */
1430#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1431
1432/** Increment the read lock counter.
1433 * @param a_pPage Pointer to the physical guest page tracking structure.
1434 */
1435#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1436
1437/** Increment the write lock counter.
1438 * @param a_pPage Pointer to the physical guest page tracking structure.
1439 */
1440#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1441
1442
1443/** Gets the NEM state.
1444 * @returns NEM state value (two bits).
1445 * @param a_pPage Pointer to the physical guest page tracking structure.
1446 */
1447#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1448
1449/** Sets the NEM state.
1450 * @param a_pPage Pointer to the physical guest page tracking structure.
1451 * @param a_u2State The NEM state value (specific to NEM impl.).
1452 */
1453#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1454 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1455
1456
1457#if 0
1458/** Enables sanity checking of write monitoring using CRC-32. */
1459# define PGMLIVESAVERAMPAGE_WITH_CRC32
1460#endif
1461
1462/**
1463 * Per page live save tracking data.
1464 */
1465typedef struct PGMLIVESAVERAMPAGE
1466{
1467 /** Number of times it has been dirtied. */
1468 uint32_t cDirtied : 24;
1469 /** Whether it is currently dirty. */
1470 uint32_t fDirty : 1;
1471 /** Ignore the page.
1472 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1473 * deal with these after pausing the VM and DevPCI have said it bit about
1474 * remappings. */
1475 uint32_t fIgnore : 1;
1476 /** Was a ZERO page last time around. */
1477 uint32_t fZero : 1;
1478 /** Was a SHARED page last time around. */
1479 uint32_t fShared : 1;
1480 /** Whether the page is/was write monitored in a previous pass. */
1481 uint32_t fWriteMonitored : 1;
1482 /** Whether the page is/was write monitored earlier in this pass. */
1483 uint32_t fWriteMonitoredJustNow : 1;
1484 /** Bits reserved for future use. */
1485 uint32_t u2Reserved : 2;
1486#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1487 /** CRC-32 for the page. This is for internal consistency checks. */
1488 uint32_t u32Crc;
1489#endif
1490} PGMLIVESAVERAMPAGE;
1491#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1492AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1493#else
1494AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1495#endif
1496/** Pointer to the per page live save tracking data. */
1497typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1498
1499/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1500#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1501
1502
1503/**
1504 * RAM range for GC Phys to HC Phys conversion.
1505 *
1506 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1507 * conversions too, but we'll let MM handle that for now.
1508 *
1509 * This structure is used by linked lists in both GC and HC.
1510 */
1511typedef struct PGMRAMRANGE
1512{
1513 /** Start of the range. Page aligned. */
1514 RTGCPHYS GCPhys;
1515 /** Size of the range. (Page aligned of course). */
1516 RTGCPHYS cb;
1517 /** Pointer to the next RAM range - for R3. */
1518 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1519 /** Pointer to the next RAM range - for R0. */
1520 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1521 /** Pointer to the next RAM range - for RC. */
1522 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1523 /** PGM_RAM_RANGE_FLAGS_* flags. */
1524 uint32_t fFlags;
1525 /** Last address in the range (inclusive). Page aligned (-1). */
1526 RTGCPHYS GCPhysLast;
1527 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1528 R3PTRTYPE(void *) pvR3;
1529 /** Live save per page tracking data. */
1530 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1531 /** The range description. */
1532 R3PTRTYPE(const char *) pszDesc;
1533 /** Pointer to self - R0 pointer. */
1534 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1535 /** Pointer to self - RC pointer. */
1536 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1537
1538 /** Alignment padding. */
1539 RTRCPTR Alignment0;
1540 /** Pointer to the left search three node - ring-3 context. */
1541 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1542 /** Pointer to the right search three node - ring-3 context. */
1543 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1544 /** Pointer to the left search three node - ring-0 context. */
1545 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1546 /** Pointer to the right search three node - ring-0 context. */
1547 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1548 /** Pointer to the left search three node - raw-mode context. */
1549 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1550 /** Pointer to the right search three node - raw-mode context. */
1551 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1552
1553 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1554#if HC_ARCH_BITS == 32
1555 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1556#endif
1557 /** Array of physical guest page tracking structures. */
1558 PGMPAGE aPages[1];
1559} PGMRAMRANGE;
1560/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1561typedef PGMRAMRANGE *PPGMRAMRANGE;
1562
1563/** @name PGMRAMRANGE::fFlags
1564 * @{ */
1565/** The RAM range is floating around as an independent guest mapping. */
1566#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1567/** Ad hoc RAM range for an ROM mapping. */
1568#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1569/** Ad hoc RAM range for an MMIO mapping. */
1570#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1571/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1572#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1573/** @} */
1574
1575/** Tests if a RAM range is an ad hoc one or not.
1576 * @returns true/false.
1577 * @param pRam The RAM range.
1578 */
1579#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1580 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1581
1582/** The number of entries in the RAM range TLBs (there is one for each
1583 * context). Must be a power of two. */
1584#define PGM_RAMRANGE_TLB_ENTRIES 8
1585
1586/**
1587 * Calculates the RAM range TLB index for the physical address.
1588 *
1589 * @returns RAM range TLB index.
1590 * @param a_GCPhys The guest physical address.
1591 */
1592#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1593
1594
1595
1596/**
1597 * Per page tracking structure for ROM image.
1598 *
1599 * A ROM image may have a shadow page, in which case we may have two pages
1600 * backing it. This structure contains the PGMPAGE for both while
1601 * PGMRAMRANGE have a copy of the active one. It is important that these
1602 * aren't out of sync in any regard other than page pool tracking data.
1603 */
1604typedef struct PGMROMPAGE
1605{
1606 /** The page structure for the virgin ROM page. */
1607 PGMPAGE Virgin;
1608 /** The page structure for the shadow RAM page. */
1609 PGMPAGE Shadow;
1610 /** The current protection setting. */
1611 PGMROMPROT enmProt;
1612 /** Live save status information. Makes use of unused alignment space. */
1613 struct
1614 {
1615 /** The previous protection value. */
1616 uint8_t u8Prot;
1617 /** Written to flag set by the handler. */
1618 bool fWrittenTo;
1619 /** Whether the shadow page is dirty or not. */
1620 bool fDirty;
1621 /** Whether it was dirtied in the recently. */
1622 bool fDirtiedRecently;
1623 } LiveSave;
1624} PGMROMPAGE;
1625AssertCompileSizeAlignment(PGMROMPAGE, 8);
1626/** Pointer to a ROM page tracking structure. */
1627typedef PGMROMPAGE *PPGMROMPAGE;
1628
1629
1630/**
1631 * A registered ROM image.
1632 *
1633 * This is needed to keep track of ROM image since they generally intrude
1634 * into a PGMRAMRANGE. It also keeps track of additional info like the
1635 * two page sets (read-only virgin and read-write shadow), the current
1636 * state of each page.
1637 *
1638 * Because access handlers cannot easily be executed in a different
1639 * context, the ROM ranges needs to be accessible and in all contexts.
1640 */
1641typedef struct PGMROMRANGE
1642{
1643 /** Pointer to the next range - R3. */
1644 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1645 /** Pointer to the next range - R0. */
1646 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1647 /** Pointer to the next range - RC. */
1648 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1649 /** Pointer alignment */
1650 RTRCPTR RCPtrAlignment;
1651 /** Address of the range. */
1652 RTGCPHYS GCPhys;
1653 /** Address of the last byte in the range. */
1654 RTGCPHYS GCPhysLast;
1655 /** Size of the range. */
1656 RTGCPHYS cb;
1657 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1658 uint32_t fFlags;
1659 /** The saved state range ID. */
1660 uint8_t idSavedState;
1661 /** Alignment padding. */
1662 uint8_t au8Alignment[3];
1663 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1664 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1665 /** The size bits pvOriginal points to. */
1666 uint32_t cbOriginal;
1667 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1668 * This is used for strictness checks. */
1669 R3PTRTYPE(const void *) pvOriginal;
1670 /** The ROM description. */
1671 R3PTRTYPE(const char *) pszDesc;
1672 /** The per page tracking structures. */
1673 PGMROMPAGE aPages[1];
1674} PGMROMRANGE;
1675/** Pointer to a ROM range. */
1676typedef PGMROMRANGE *PPGMROMRANGE;
1677
1678
1679/**
1680 * Live save per page data for an MMIO2 page.
1681 *
1682 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1683 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1684 * CRC-32 for detecting changes as well as special handling of zero pages. This
1685 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1686 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1687 * because of speed (2.5x and 6x slower).)
1688 *
1689 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1690 * save but normally is disabled. Since we can write monitor guest
1691 * accesses on our own, we only need this for host accesses. Shouldn't be
1692 * too difficult for DevVGA, VMMDev might be doable, the planned
1693 * networking fun will be fun since it involves ring-0.
1694 */
1695typedef struct PGMLIVESAVEMMIO2PAGE
1696{
1697 /** Set if the page is considered dirty. */
1698 bool fDirty;
1699 /** The number of scans this page has remained unchanged for.
1700 * Only updated for dirty pages. */
1701 uint8_t cUnchangedScans;
1702 /** Whether this page was zero at the last scan. */
1703 bool fZero;
1704 /** Alignment padding. */
1705 bool fReserved;
1706 /** CRC-32 for the first half of the page.
1707 * This is used together with u32CrcH2 to quickly detect changes in the page
1708 * during the non-final passes. */
1709 uint32_t u32CrcH1;
1710 /** CRC-32 for the second half of the page. */
1711 uint32_t u32CrcH2;
1712 /** SHA-1 for the saved page.
1713 * This is used in the final pass to skip pages without changes. */
1714 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1715} PGMLIVESAVEMMIO2PAGE;
1716/** Pointer to a live save status data for an MMIO2 page. */
1717typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1718
1719/**
1720 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1721 *
1722 * There are a few reason why we need to keep track of these registrations. One
1723 * of them is the deregistration & cleanup stuff, while another is that the
1724 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1725 * range list.
1726 *
1727 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1728 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1729 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1730 * overlap we will free all the existing RAM pages and put in the ram range
1731 * pages instead.
1732 */
1733typedef struct PGMREGMMIORANGE
1734{
1735 /** The owner of the range. (a device) */
1736 PPDMDEVINSR3 pDevInsR3;
1737 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1738 RTR3PTR pvR3;
1739 /** Pointer to the next range - R3. */
1740 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1741 /** Flags (PGMREGMMIORANGE_F_XXX). */
1742 uint16_t fFlags;
1743 /** The sub device number (internal PCI config (CFGM) number). */
1744 uint8_t iSubDev;
1745 /** The PCI region number. */
1746 uint8_t iRegion;
1747 /** The saved state range ID. */
1748 uint8_t idSavedState;
1749 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1750 uint8_t idMmio2;
1751 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1752 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1753 /** The real size.
1754 * This may be larger than indicated by RamRange.cb if the range has been
1755 * reduced during saved state loading. */
1756 RTGCPHYS cbReal;
1757 /** Pointer to the physical handler for MMIO. */
1758 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1759 /** Live save per page tracking data for MMIO2. */
1760 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1761 /** The associated RAM range. */
1762 PGMRAMRANGE RamRange;
1763} PGMREGMMIORANGE;
1764AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1765/** Pointer to a MMIO2 or pre-registered MMIO range. */
1766typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1767
1768/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1769 * @{ */
1770/** Set if it's an MMIO2 range. */
1771#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1772/** Set if this is the first chunk in the MMIO2 range. */
1773#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1774/** Set if this is the last chunk in the MMIO2 range. */
1775#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1776/** Set if the whole range is mapped. */
1777#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1778/** Set if it's overlapping, clear if not. */
1779#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1780/** @} */
1781
1782
1783/** @name Internal MMIO2 constants.
1784 * @{ */
1785/** The maximum number of MMIO2 ranges. */
1786#define PGM_MMIO2_MAX_RANGES 8
1787/** The maximum number of pages in a MMIO2 range. */
1788#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1789/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1790#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1791/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1792#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1793/** Gets the MMIO2 page index from an MMIO2 page ID. */
1794#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1795/** @} */
1796
1797
1798
1799/**
1800 * PGMPhysRead/Write cache entry
1801 */
1802typedef struct PGMPHYSCACHEENTRY
1803{
1804 /** R3 pointer to physical page. */
1805 R3PTRTYPE(uint8_t *) pbR3;
1806 /** GC Physical address for cache entry */
1807 RTGCPHYS GCPhys;
1808#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1809 RTGCPHYS u32Padding0; /**< alignment padding. */
1810#endif
1811} PGMPHYSCACHEENTRY;
1812
1813/**
1814 * PGMPhysRead/Write cache to reduce REM memory access overhead
1815 */
1816typedef struct PGMPHYSCACHE
1817{
1818 /** Bitmap of valid cache entries */
1819 uint64_t aEntries;
1820 /** Cache entries */
1821 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1822} PGMPHYSCACHE;
1823
1824
1825/** Pointer to an allocation chunk ring-3 mapping. */
1826typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1827/** Pointer to an allocation chunk ring-3 mapping pointer. */
1828typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1829
1830/**
1831 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1832 *
1833 * The primary tree (Core) uses the chunk id as key.
1834 */
1835typedef struct PGMCHUNKR3MAP
1836{
1837 /** The key is the chunk id. */
1838 AVLU32NODECORE Core;
1839 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1840 * selection. */
1841 uint32_t iLastUsed;
1842 /** The current reference count. */
1843 uint32_t volatile cRefs;
1844 /** The current permanent reference count. */
1845 uint32_t volatile cPermRefs;
1846 /** The mapping address. */
1847 void *pv;
1848} PGMCHUNKR3MAP;
1849
1850/**
1851 * Allocation chunk ring-3 mapping TLB entry.
1852 */
1853typedef struct PGMCHUNKR3MAPTLBE
1854{
1855 /** The chunk id. */
1856 uint32_t volatile idChunk;
1857#if HC_ARCH_BITS == 64
1858 uint32_t u32Padding; /**< alignment padding. */
1859#endif
1860 /** The chunk map. */
1861#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1862 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1863#else
1864 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1865#endif
1866} PGMCHUNKR3MAPTLBE;
1867/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1868typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1869
1870/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1871 * @remark Must be a power of two value. */
1872#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1873
1874/**
1875 * Allocation chunk ring-3 mapping TLB.
1876 *
1877 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1878 * At first glance this might look kinda odd since AVL trees are
1879 * supposed to give the most optimal lookup times of all trees
1880 * due to their balancing. However, take a tree with 1023 nodes
1881 * in it, that's 10 levels, meaning that most searches has to go
1882 * down 9 levels before they find what they want. This isn't fast
1883 * compared to a TLB hit. There is the factor of cache misses,
1884 * and of course the problem with trees and branch prediction.
1885 * This is why we use TLBs in front of most of the trees.
1886 *
1887 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1888 * difficult when we switch to the new inlined AVL trees (from kStuff).
1889 */
1890typedef struct PGMCHUNKR3MAPTLB
1891{
1892 /** The TLB entries. */
1893 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1894} PGMCHUNKR3MAPTLB;
1895
1896/**
1897 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1898 * @returns Chunk TLB index.
1899 * @param idChunk The Chunk ID.
1900 */
1901#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1902
1903
1904/**
1905 * Ring-3 guest page mapping TLB entry.
1906 * @remarks used in ring-0 as well at the moment.
1907 */
1908typedef struct PGMPAGER3MAPTLBE
1909{
1910 /** Address of the page. */
1911 RTGCPHYS volatile GCPhys;
1912 /** The guest page. */
1913#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1914 R3PTRTYPE(PPGMPAGE) volatile pPage;
1915#else
1916 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1917#endif
1918 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1919#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1920 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1921#else
1922 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1923#endif
1924 /** The address */
1925#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1926 R3PTRTYPE(void *) volatile pv;
1927#else
1928 R3R0PTRTYPE(void *) volatile pv;
1929#endif
1930#if HC_ARCH_BITS == 32
1931 uint32_t u32Padding; /**< alignment padding. */
1932#endif
1933} PGMPAGER3MAPTLBE;
1934/** Pointer to an entry in the HC physical TLB. */
1935typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1936
1937
1938/** The number of entries in the ring-3 guest page mapping TLB.
1939 * @remarks The value must be a power of two. */
1940#define PGM_PAGER3MAPTLB_ENTRIES 256
1941
1942/**
1943 * Ring-3 guest page mapping TLB.
1944 * @remarks used in ring-0 as well at the moment.
1945 */
1946typedef struct PGMPAGER3MAPTLB
1947{
1948 /** The TLB entries. */
1949 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1950} PGMPAGER3MAPTLB;
1951/** Pointer to the ring-3 guest page mapping TLB. */
1952typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1953
1954/**
1955 * Calculates the index of the TLB entry for the specified guest page.
1956 * @returns Physical TLB index.
1957 * @param GCPhys The guest physical address.
1958 */
1959#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1960
1961
1962/**
1963 * Raw-mode context dynamic mapping cache entry.
1964 *
1965 * Because of raw-mode context being reloctable and all relocations are applied
1966 * in ring-3, this has to be defined here and be RC specific.
1967 *
1968 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1969 */
1970typedef struct PGMRCDYNMAPENTRY
1971{
1972 /** The physical address of the currently mapped page.
1973 * This is duplicate for three reasons: cache locality, cache policy of the PT
1974 * mappings and sanity checks. */
1975 RTHCPHYS HCPhys;
1976 /** Pointer to the page. */
1977 RTRCPTR pvPage;
1978 /** The number of references. */
1979 int32_t volatile cRefs;
1980 /** PTE pointer union. */
1981 struct PGMRCDYNMAPENTRY_PPTE
1982 {
1983 /** PTE pointer, 32-bit legacy version. */
1984 RCPTRTYPE(PX86PTE) pLegacy;
1985 /** PTE pointer, PAE version. */
1986 RCPTRTYPE(PX86PTEPAE) pPae;
1987 } uPte;
1988} PGMRCDYNMAPENTRY;
1989/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1990typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1991
1992
1993/**
1994 * Dynamic mapping cache for the raw-mode context.
1995 *
1996 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1997 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1998 * so that we can perform relocations from PGMR3Relocate. This has the
1999 * consequence that we must have separate ring-0 and raw-mode context versions
2000 * of this struct even if they share the basic elements.
2001 *
2002 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
2003 */
2004typedef struct PGMRCDYNMAP
2005{
2006 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
2007 uint32_t u32Magic;
2008 /** Array for tracking and managing the pages. */
2009 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
2010 /** The cache size given as a number of pages. */
2011 uint32_t cPages;
2012 /** The current load.
2013 * This does not include guard pages. */
2014 uint32_t cLoad;
2015 /** The max load ever.
2016 * This is maintained to get trigger adding of more mapping space. */
2017 uint32_t cMaxLoad;
2018 /** The number of guard pages. */
2019 uint32_t cGuardPages;
2020 /** The number of users (protected by hInitLock). */
2021 uint32_t cUsers;
2022} PGMRCDYNMAP;
2023/** Pointer to the dynamic cache for the raw-mode context. */
2024typedef PGMRCDYNMAP *PPGMRCDYNMAP;
2025
2026
2027/**
2028 * Mapping cache usage set entry.
2029 *
2030 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
2031 * the dynamic ring-0 and (to some extent) raw-mode context mapping
2032 * cache. If it's extended to include ring-3, well, then something
2033 * will have be changed here...
2034 */
2035typedef struct PGMMAPSETENTRY
2036{
2037 /** Pointer to the page. */
2038#ifndef IN_RC
2039 RTR0PTR pvPage;
2040#else
2041 RTRCPTR pvPage;
2042# if HC_ARCH_BITS == 64
2043 uint32_t u32Alignment2;
2044# endif
2045#endif
2046 /** The mapping cache index. */
2047 uint16_t iPage;
2048 /** The number of references.
2049 * The max is UINT16_MAX - 1. */
2050 uint16_t cRefs;
2051 /** The number inlined references.
2052 * The max is UINT16_MAX - 1. */
2053 uint16_t cInlinedRefs;
2054 /** Unreferences. */
2055 uint16_t cUnrefs;
2056
2057#if HC_ARCH_BITS == 32
2058 uint32_t u32Alignment1;
2059#endif
2060 /** The physical address for this entry. */
2061 RTHCPHYS HCPhys;
2062} PGMMAPSETENTRY;
2063AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2064AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2065/** Pointer to a mapping cache usage set entry. */
2066typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2067
2068/**
2069 * Mapping cache usage set.
2070 *
2071 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2072 * done during exits / traps. The set is
2073 */
2074typedef struct PGMMAPSET
2075{
2076 /** The number of occupied entries.
2077 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2078 * dynamic mappings. */
2079 uint32_t cEntries;
2080 /** The start of the current subset.
2081 * This is UINT32_MAX if no subset is currently open. */
2082 uint32_t iSubset;
2083 /** The index of the current CPU, only valid if the set is open. */
2084 int32_t iCpu;
2085 uint32_t alignment;
2086 /** The entries. */
2087 PGMMAPSETENTRY aEntries[64];
2088 /** HCPhys -> iEntry fast lookup table.
2089 * Use PGMMAPSET_HASH for hashing.
2090 * The entries may or may not be valid, check against cEntries. */
2091 uint8_t aiHashTable[128];
2092} PGMMAPSET;
2093AssertCompileSizeAlignment(PGMMAPSET, 8);
2094/** Pointer to the mapping cache set. */
2095typedef PGMMAPSET *PPGMMAPSET;
2096
2097/** PGMMAPSET::cEntries value for a closed set. */
2098#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2099
2100/** Hash function for aiHashTable. */
2101#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2102
2103
2104/** @name Context neutral page mapper TLB.
2105 *
2106 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2107 * code is writting in a kind of context neutral way. Time will show whether
2108 * this actually makes sense or not...
2109 *
2110 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2111 * context ends up using a global mapping cache on some platforms
2112 * (darwin).
2113 *
2114 * @{ */
2115/** @typedef PPGMPAGEMAPTLB
2116 * The page mapper TLB pointer type for the current context. */
2117/** @typedef PPGMPAGEMAPTLB
2118 * The page mapper TLB entry pointer type for the current context. */
2119/** @typedef PPGMPAGEMAPTLB
2120 * The page mapper TLB entry pointer pointer type for the current context. */
2121/** @def PGM_PAGEMAPTLB_ENTRIES
2122 * The number of TLB entries in the page mapper TLB for the current context. */
2123/** @def PGM_PAGEMAPTLB_IDX
2124 * Calculate the TLB index for a guest physical address.
2125 * @returns The TLB index.
2126 * @param GCPhys The guest physical address. */
2127/** @typedef PPGMPAGEMAP
2128 * Pointer to a page mapper unit for current context. */
2129/** @typedef PPPGMPAGEMAP
2130 * Pointer to a page mapper unit pointer for current context. */
2131#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2132// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2133// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2134// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2135# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2136# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2137 typedef void * PPGMPAGEMAP;
2138 typedef void ** PPPGMPAGEMAP;
2139//#elif IN_RING0
2140// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2141// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2142// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2143//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2144//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2145// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2146// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2147#else
2148 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2149 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2150 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2151# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2152# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2153 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2154 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2155#endif
2156/** @} */
2157
2158
2159/** @name PGM Pool Indexes.
2160 * Aka. the unique shadow page identifier.
2161 * @{ */
2162/** NIL page pool IDX. */
2163#define NIL_PGMPOOL_IDX 0
2164/** The first normal index. There used to be 5 fictive pages up front, now
2165 * there is only the NIL page. */
2166#define PGMPOOL_IDX_FIRST 1
2167/** The last valid index. (inclusive, 14 bits) */
2168#define PGMPOOL_IDX_LAST 0x3fff
2169/** @} */
2170
2171/** The NIL index for the parent chain. */
2172#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2173#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2174
2175/**
2176 * Node in the chain linking a shadowed page to it's parent (user).
2177 */
2178#pragma pack(1)
2179typedef struct PGMPOOLUSER
2180{
2181 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2182 uint16_t iNext;
2183 /** The user page index. */
2184 uint16_t iUser;
2185 /** Index into the user table. */
2186 uint32_t iUserTable;
2187} PGMPOOLUSER, *PPGMPOOLUSER;
2188typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2189#pragma pack()
2190
2191
2192/** The NIL index for the phys ext chain. */
2193#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2194/** The NIL pte index for a phys ext chain slot. */
2195#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2196
2197/**
2198 * Node in the chain of physical cross reference extents.
2199 * @todo Calling this an 'extent' is not quite right, find a better name.
2200 * @todo find out the optimal size of the aidx array
2201 */
2202#pragma pack(1)
2203typedef struct PGMPOOLPHYSEXT
2204{
2205 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2206 uint16_t iNext;
2207 /** Alignment. */
2208 uint16_t u16Align;
2209 /** The user page index. */
2210 uint16_t aidx[3];
2211 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2212 uint16_t apte[3];
2213} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2214typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2215#pragma pack()
2216
2217
2218/**
2219 * The kind of page that's being shadowed.
2220 */
2221typedef enum PGMPOOLKIND
2222{
2223 /** The virtual invalid 0 entry. */
2224 PGMPOOLKIND_INVALID = 0,
2225 /** The entry is free (=unused). */
2226 PGMPOOLKIND_FREE,
2227
2228 /** Shw: 32-bit page table; Gst: no paging. */
2229 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2230 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2231 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2232 /** Shw: 32-bit page table; Gst: 4MB page. */
2233 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2234 /** Shw: PAE page table; Gst: no paging. */
2235 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2236 /** Shw: PAE page table; Gst: 32-bit page table. */
2237 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2238 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2239 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2240 /** Shw: PAE page table; Gst: PAE page table. */
2241 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2242 /** Shw: PAE page table; Gst: 2MB page. */
2243 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2244
2245 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2246 PGMPOOLKIND_32BIT_PD,
2247 /** Shw: 32-bit page directory. Gst: no paging. */
2248 PGMPOOLKIND_32BIT_PD_PHYS,
2249 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2250 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2251 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2252 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2253 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2254 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2255 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2256 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2257 /** Shw: PAE page directory; Gst: PAE page directory. */
2258 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2259 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2260 PGMPOOLKIND_PAE_PD_PHYS,
2261
2262 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2263 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2264 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2265 PGMPOOLKIND_PAE_PDPT,
2266 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2267 PGMPOOLKIND_PAE_PDPT_PHYS,
2268
2269 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2270 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2271 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2272 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2273 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2274 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2275 /** Shw: 64-bit page directory table; Gst: no paging. */
2276 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2277
2278 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2279 PGMPOOLKIND_64BIT_PML4,
2280
2281 /** Shw: EPT page directory pointer table; Gst: no paging. */
2282 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2283 /** Shw: EPT page directory table; Gst: no paging. */
2284 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2285 /** Shw: EPT page table; Gst: no paging. */
2286 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2287
2288 /** Shw: Root Nested paging table. */
2289 PGMPOOLKIND_ROOT_NESTED,
2290
2291 /** The last valid entry. */
2292 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2293} PGMPOOLKIND;
2294
2295/**
2296 * The access attributes of the page; only applies to big pages.
2297 */
2298typedef enum
2299{
2300 PGMPOOLACCESS_DONTCARE = 0,
2301 PGMPOOLACCESS_USER_RW,
2302 PGMPOOLACCESS_USER_R,
2303 PGMPOOLACCESS_USER_RW_NX,
2304 PGMPOOLACCESS_USER_R_NX,
2305 PGMPOOLACCESS_SUPERVISOR_RW,
2306 PGMPOOLACCESS_SUPERVISOR_R,
2307 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2308 PGMPOOLACCESS_SUPERVISOR_R_NX
2309} PGMPOOLACCESS;
2310
2311/**
2312 * The tracking data for a page in the pool.
2313 */
2314typedef struct PGMPOOLPAGE
2315{
2316 /** AVL node code with the (HC) physical address of this page. */
2317 AVLOHCPHYSNODECORE Core;
2318 /** Pointer to the R3 mapping of the page. */
2319#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2320 R3PTRTYPE(void *) pvPageR3;
2321#else
2322 R3R0PTRTYPE(void *) pvPageR3;
2323#endif
2324#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2325 uint32_t Alignment0;
2326#endif
2327 /** The guest physical address. */
2328 RTGCPHYS GCPhys;
2329 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2330 uint8_t enmKind;
2331 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2332 uint8_t enmAccess;
2333 /** This supplements enmKind and enmAccess */
2334 bool fA20Enabled : 1;
2335
2336 /** Used to indicate that the page is zeroed. */
2337 bool fZeroed : 1;
2338 /** Used to indicate that a PT has non-global entries. */
2339 bool fSeenNonGlobal : 1;
2340 /** Used to indicate that we're monitoring writes to the guest page. */
2341 bool fMonitored : 1;
2342 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2343 * (All pages are in the age list.) */
2344 bool fCached : 1;
2345 /** This is used by the R3 access handlers when invoked by an async thread.
2346 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2347 bool volatile fReusedFlushPending : 1;
2348 /** Used to mark the page as dirty (write monitoring is temporarily
2349 * off). */
2350 bool fDirty : 1;
2351 bool fPadding1 : 1;
2352 bool fPadding2;
2353
2354 /** The index of this page. */
2355 uint16_t idx;
2356 /** The next entry in the list this page currently resides in.
2357 * It's either in the free list or in the GCPhys hash. */
2358 uint16_t iNext;
2359 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2360 uint16_t iUserHead;
2361 /** The number of present entries. */
2362 uint16_t cPresent;
2363 /** The first entry in the table which is present. */
2364 uint16_t iFirstPresent;
2365 /** The number of modifications to the monitored page. */
2366 uint16_t cModifications;
2367 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2368 uint16_t iModifiedNext;
2369 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2370 uint16_t iModifiedPrev;
2371 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2372 uint16_t iMonitoredNext;
2373 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2374 uint16_t iMonitoredPrev;
2375 /** The next page in the age list. */
2376 uint16_t iAgeNext;
2377 /** The previous page in the age list. */
2378 uint16_t iAgePrev;
2379 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2380 uint8_t idxDirtyEntry;
2381
2382 /** @name Access handler statistics to determine whether the guest is
2383 * (re)initializing a page table.
2384 * @{ */
2385 RTGCPTR GCPtrLastAccessHandlerRip;
2386 RTGCPTR GCPtrLastAccessHandlerFault;
2387 uint64_t cLastAccessHandler;
2388 /** @} */
2389 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2390 uint32_t volatile cLocked;
2391#if GC_ARCH_BITS == 64
2392 uint32_t u32Alignment3;
2393#endif
2394# ifdef VBOX_STRICT
2395 RTGCPTR GCPtrDirtyFault;
2396# endif
2397} PGMPOOLPAGE;
2398/** Pointer to a pool page. */
2399typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2400/** Pointer to a const pool page. */
2401typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2402/** Pointer to a pool page pointer. */
2403typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2404
2405
2406/** The hash table size. */
2407# define PGMPOOL_HASH_SIZE 0x40
2408/** The hash function. */
2409# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2410
2411
2412/**
2413 * The shadow page pool instance data.
2414 *
2415 * It's all one big allocation made at init time, except for the
2416 * pages that is. The user nodes follows immediately after the
2417 * page structures.
2418 */
2419typedef struct PGMPOOL
2420{
2421 /** The VM handle - R3 Ptr. */
2422 PVMR3 pVMR3;
2423 /** The VM handle - R0 Ptr. */
2424 PVMR0 pVMR0;
2425 /** The VM handle - RC Ptr. */
2426 PVMRC pVMRC;
2427 /** The max pool size. This includes the special IDs. */
2428 uint16_t cMaxPages;
2429 /** The current pool size. */
2430 uint16_t cCurPages;
2431 /** The head of the free page list. */
2432 uint16_t iFreeHead;
2433 /* Padding. */
2434 uint16_t u16Padding;
2435 /** Head of the chain of free user nodes. */
2436 uint16_t iUserFreeHead;
2437 /** The number of user nodes we've allocated. */
2438 uint16_t cMaxUsers;
2439 /** The number of present page table entries in the entire pool. */
2440 uint32_t cPresent;
2441 /** Pointer to the array of user nodes - RC pointer. */
2442 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2443 /** Pointer to the array of user nodes - R3 pointer. */
2444 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2445 /** Pointer to the array of user nodes - R0 pointer. */
2446 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2447 /** Head of the chain of free phys ext nodes. */
2448 uint16_t iPhysExtFreeHead;
2449 /** The number of user nodes we've allocated. */
2450 uint16_t cMaxPhysExts;
2451 /** Pointer to the array of physical xref extent - RC pointer. */
2452 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2453 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2454 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2455 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2456 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2457 /** Hash table for GCPhys addresses. */
2458 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2459 /** The head of the age list. */
2460 uint16_t iAgeHead;
2461 /** The tail of the age list. */
2462 uint16_t iAgeTail;
2463 /** Set if the cache is enabled. */
2464 bool fCacheEnabled;
2465 /** Alignment padding. */
2466 bool afPadding1[3];
2467 /** Head of the list of modified pages. */
2468 uint16_t iModifiedHead;
2469 /** The current number of modified pages. */
2470 uint16_t cModifiedPages;
2471 /** Physical access handler type registration handle. */
2472 PGMPHYSHANDLERTYPE hAccessHandlerType;
2473 /** Next available slot (in aDirtyPages). */
2474 uint32_t idxFreeDirtyPage;
2475 /** Number of active dirty pages. */
2476 uint32_t cDirtyPages;
2477 /** Array of current dirty pgm pool page indices. */
2478 struct
2479 {
2480 uint16_t uIdx;
2481 uint16_t Alignment[3];
2482 uint64_t aPage[512];
2483 } aDirtyPages[16];
2484 /** The number of pages currently in use. */
2485 uint16_t cUsedPages;
2486#ifdef VBOX_WITH_STATISTICS
2487 /** The high water mark for cUsedPages. */
2488 uint16_t cUsedPagesHigh;
2489 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2490 /** Profiling pgmPoolAlloc(). */
2491 STAMPROFILEADV StatAlloc;
2492 /** Profiling pgmR3PoolClearDoIt(). */
2493 STAMPROFILE StatClearAll;
2494 /** Profiling pgmR3PoolReset(). */
2495 STAMPROFILE StatR3Reset;
2496 /** Profiling pgmPoolFlushPage(). */
2497 STAMPROFILE StatFlushPage;
2498 /** Profiling pgmPoolFree(). */
2499 STAMPROFILE StatFree;
2500 /** Counting explicit flushes by PGMPoolFlushPage(). */
2501 STAMCOUNTER StatForceFlushPage;
2502 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2503 STAMCOUNTER StatForceFlushDirtyPage;
2504 /** Counting flushes for reused pages. */
2505 STAMCOUNTER StatForceFlushReused;
2506 /** Profiling time spent zeroing pages. */
2507 STAMPROFILE StatZeroPage;
2508 /** Profiling of pgmPoolTrackDeref. */
2509 STAMPROFILE StatTrackDeref;
2510 /** Profiling pgmTrackFlushGCPhysPT. */
2511 STAMPROFILE StatTrackFlushGCPhysPT;
2512 /** Profiling pgmTrackFlushGCPhysPTs. */
2513 STAMPROFILE StatTrackFlushGCPhysPTs;
2514 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2515 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2516 /** Number of times we've been out of user records. */
2517 STAMCOUNTER StatTrackFreeUpOneUser;
2518 /** Nr of flushed entries. */
2519 STAMCOUNTER StatTrackFlushEntry;
2520 /** Nr of updated entries. */
2521 STAMCOUNTER StatTrackFlushEntryKeep;
2522 /** Profiling deref activity related tracking GC physical pages. */
2523 STAMPROFILE StatTrackDerefGCPhys;
2524 /** Number of linear searches for a HCPhys in the ram ranges. */
2525 STAMCOUNTER StatTrackLinearRamSearches;
2526 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2527 STAMCOUNTER StamTrackPhysExtAllocFailures;
2528
2529 /** Profiling the RC/R0 \#PF access handler. */
2530 STAMPROFILE StatMonitorPfRZ;
2531 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2532 STAMPROFILE StatMonitorPfRZHandled;
2533 /** Times we've failed interpreting the instruction. */
2534 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2535 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2536 STAMPROFILE StatMonitorPfRZFlushPage;
2537 /* Times we've detected a page table reinit. */
2538 STAMCOUNTER StatMonitorPfRZFlushReinit;
2539 /** Counting flushes for pages that are modified too often. */
2540 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2541 /** Times we've detected fork(). */
2542 STAMCOUNTER StatMonitorPfRZFork;
2543 /** Times we've failed interpreting a patch code instruction. */
2544 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2545 /** Times we've failed interpreting a patch code instruction during flushing. */
2546 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2547 /** The number of times we've seen rep prefixes we can't handle. */
2548 STAMCOUNTER StatMonitorPfRZRepPrefix;
2549 /** Profiling the REP STOSD cases we've handled. */
2550 STAMPROFILE StatMonitorPfRZRepStosd;
2551
2552 /** Profiling the R0/RC regular access handler. */
2553 STAMPROFILE StatMonitorRZ;
2554 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2555 STAMPROFILE StatMonitorRZFlushPage;
2556 /** Per access size counts indexed by size minus 1, last for larger. */
2557 STAMCOUNTER aStatMonitorRZSizes[16+3];
2558 /** Missaligned access counts indexed by offset - 1. */
2559 STAMCOUNTER aStatMonitorRZMisaligned[7];
2560
2561 /** Nr of handled PT faults. */
2562 STAMCOUNTER StatMonitorRZFaultPT;
2563 /** Nr of handled PD faults. */
2564 STAMCOUNTER StatMonitorRZFaultPD;
2565 /** Nr of handled PDPT faults. */
2566 STAMCOUNTER StatMonitorRZFaultPDPT;
2567 /** Nr of handled PML4 faults. */
2568 STAMCOUNTER StatMonitorRZFaultPML4;
2569
2570 /** Profiling the R3 access handler. */
2571 STAMPROFILE StatMonitorR3;
2572 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2573 STAMPROFILE StatMonitorR3FlushPage;
2574 /** Per access size counts indexed by size minus 1, last for larger. */
2575 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2576 /** Missaligned access counts indexed by offset - 1. */
2577 STAMCOUNTER aStatMonitorR3Misaligned[7];
2578 /** Nr of handled PT faults. */
2579 STAMCOUNTER StatMonitorR3FaultPT;
2580 /** Nr of handled PD faults. */
2581 STAMCOUNTER StatMonitorR3FaultPD;
2582 /** Nr of handled PDPT faults. */
2583 STAMCOUNTER StatMonitorR3FaultPDPT;
2584 /** Nr of handled PML4 faults. */
2585 STAMCOUNTER StatMonitorR3FaultPML4;
2586
2587 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2588 STAMCOUNTER StatResetDirtyPages;
2589 /** Times we've called pgmPoolAddDirtyPage. */
2590 STAMCOUNTER StatDirtyPage;
2591 /** Times we've had to flush duplicates for dirty page management. */
2592 STAMCOUNTER StatDirtyPageDupFlush;
2593 /** Times we've had to flush because of overflow. */
2594 STAMCOUNTER StatDirtyPageOverFlowFlush;
2595
2596 /** The high water mark for cModifiedPages. */
2597 uint16_t cModifiedPagesHigh;
2598 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2599
2600 /** The number of cache hits. */
2601 STAMCOUNTER StatCacheHits;
2602 /** The number of cache misses. */
2603 STAMCOUNTER StatCacheMisses;
2604 /** The number of times we've got a conflict of 'kind' in the cache. */
2605 STAMCOUNTER StatCacheKindMismatches;
2606 /** Number of times we've been out of pages. */
2607 STAMCOUNTER StatCacheFreeUpOne;
2608 /** The number of cacheable allocations. */
2609 STAMCOUNTER StatCacheCacheable;
2610 /** The number of uncacheable allocations. */
2611 STAMCOUNTER StatCacheUncacheable;
2612#else
2613 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2614#endif
2615 /** The AVL tree for looking up a page by its HC physical address. */
2616 AVLOHCPHYSTREE HCPhysTree;
2617 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2618 /** Array of pages. (cMaxPages in length)
2619 * The Id is the index into thist array.
2620 */
2621 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2622} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2623AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2624AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2625AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2626#ifdef VBOX_WITH_STATISTICS
2627AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2628#endif
2629AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2630
2631
2632/** @def PGMPOOL_PAGE_2_PTR
2633 * Maps a pool page pool into the current context.
2634 *
2635 * @returns VBox status code.
2636 * @param a_pVM Pointer to the VM.
2637 * @param a_pPage The pool page.
2638 *
2639 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2640 * small page window employeed by that function. Be careful.
2641 * @remark There is no need to assert on the result.
2642 */
2643#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2644# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2645#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2646# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2647DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2648{
2649 AssertPtr(a_pPage);
2650 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2651 return a_pPage->pvPageR3;
2652}
2653#else
2654# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2655#endif
2656
2657
2658/** @def PGMPOOL_PAGE_2_PTR_V2
2659 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2660 *
2661 * @returns VBox status code.
2662 * @param a_pVM Pointer to the VM.
2663 * @param a_pVCpu The current CPU.
2664 * @param a_pPage The pool page.
2665 *
2666 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2667 * small page window employeed by that function. Be careful.
2668 * @remark There is no need to assert on the result.
2669 */
2670#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2671# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2672#else
2673# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2674#endif
2675
2676
2677/** @name Per guest page tracking data.
2678 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2679 * is to use more bits for it and split it up later on. But for now we'll play
2680 * safe and change as little as possible.
2681 *
2682 * The 16-bit word has two parts:
2683 *
2684 * The first 14-bit forms the @a idx field. It is either the index of a page in
2685 * the shadow page pool, or and index into the extent list.
2686 *
2687 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2688 * shadow page pool references to the page. If cRefs equals
2689 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2690 * (misnomer) table and not the shadow page pool.
2691 *
2692 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2693 * the 16-bit word.
2694 *
2695 * @{ */
2696/** The shift count for getting to the cRefs part. */
2697#define PGMPOOL_TD_CREFS_SHIFT 14
2698/** The mask applied after shifting the tracking data down by
2699 * PGMPOOL_TD_CREFS_SHIFT. */
2700#define PGMPOOL_TD_CREFS_MASK 0x3
2701/** The cRefs value used to indicate that the idx is the head of a
2702 * physical cross reference list. */
2703#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2704/** The shift used to get idx. */
2705#define PGMPOOL_TD_IDX_SHIFT 0
2706/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2707#define PGMPOOL_TD_IDX_MASK 0x3fff
2708/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2709 * simply too many mappings of this page. */
2710#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2711
2712/** @def PGMPOOL_TD_MAKE
2713 * Makes a 16-bit tracking data word.
2714 *
2715 * @returns tracking data.
2716 * @param cRefs The @a cRefs field. Must be within bounds!
2717 * @param idx The @a idx field. Must also be within bounds! */
2718#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2719
2720/** @def PGMPOOL_TD_GET_CREFS
2721 * Get the @a cRefs field from a tracking data word.
2722 *
2723 * @returns The @a cRefs field
2724 * @param u16 The tracking data word.
2725 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2726 * non-zero @a u16. */
2727#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2728
2729/** @def PGMPOOL_TD_GET_IDX
2730 * Get the @a idx field from a tracking data word.
2731 *
2732 * @returns The @a idx field
2733 * @param u16 The tracking data word. */
2734#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2735/** @} */
2736
2737
2738
2739/** @name A20 gate macros
2740 * @{ */
2741#define PGM_WITH_A20
2742#ifdef PGM_WITH_A20
2743# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2744# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2745# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2746 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2747# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2748#else
2749# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2750# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2751# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2752# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2753#endif
2754/** @} */
2755
2756
2757/**
2758 * Roots and anchors for trees and list employing self relative offsets as
2759 * pointers.
2760 *
2761 * When using self-relative offsets instead of pointers, the offsets needs to be
2762 * the same in all offsets. Thus the roots and anchors needs to live on the
2763 * hyper heap just like the nodes.
2764 */
2765typedef struct PGMTREES
2766{
2767 /** List of physical access handler types (offset pointers) of type
2768 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2769 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2770 /** Physical access handlers (AVL range+offsetptr tree). */
2771 AVLROGCPHYSTREE PhysHandlers;
2772#ifdef VBOX_WITH_RAW_MODE
2773 /** Virtual access handlers (AVL range + GC ptr tree). */
2774 AVLROGCPTRTREE VirtHandlers;
2775 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2776 * @remarks Handler of the hypervisor kind are of course not present. */
2777 AVLROGCPHYSTREE PhysToVirtHandlers;
2778 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2779 AVLROGCPTRTREE HyperVirtHandlers;
2780 /** List of virtual access handler types (offset pointers) of type
2781 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2782 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2783#endif
2784} PGMTREES;
2785/** Pointer to PGM trees. */
2786typedef PGMTREES *PPGMTREES;
2787
2788
2789/**
2790 * Page fault guest state for the AMD64 paging mode.
2791 */
2792typedef struct PGMPTWALKCORE
2793{
2794 /** The guest virtual address that is being resolved by the walk
2795 * (input). */
2796 RTGCPTR GCPtr;
2797
2798 /** The guest physical address that is the result of the walk.
2799 * @remarks only valid if fSucceeded is set. */
2800 RTGCPHYS GCPhys;
2801
2802 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2803 bool fSucceeded;
2804 /** The level problem arrised at.
2805 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2806 * level 8. This is 0 on success. */
2807 uint8_t uLevel;
2808 /** Set if the page isn't present. */
2809 bool fNotPresent;
2810 /** Encountered a bad physical address. */
2811 bool fBadPhysAddr;
2812 /** Set if there was reserved bit violations. */
2813 bool fRsvdError;
2814 /** Set if it involves a big page (2/4 MB). */
2815 bool fBigPage;
2816 /** Set if it involves a gigantic page (1 GB). */
2817 bool fGigantPage;
2818 /** The effective X86_PTE_US flag for the address. */
2819 bool fEffectiveUS;
2820 /** The effective X86_PTE_RW flag for the address. */
2821 bool fEffectiveRW;
2822 /** The effective X86_PTE_NX flag for the address. */
2823 bool fEffectiveNX;
2824 bool afPadding1[2];
2825 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2826 * The NX bit is inverted and shifted down 63 places to bit 0. */
2827 uint32_t fEffective;
2828} PGMPTWALKCORE;
2829
2830/** @name PGMPTWALKCORE::fEffective bits.
2831 * @{ */
2832/** Effective execute bit (!NX). */
2833#define PGMPTWALK_EFF_X UINT32_C(1)
2834/** Effective write access bit. */
2835#define PGMPTWALK_EFF_RW X86_PTE_RW
2836/** Effective user-mode access bit. */
2837#define PGMPTWALK_EFF_US X86_PTE_US
2838/** Effective write through cache bit. */
2839#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2840/** Effective cache disabled bit. */
2841#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2842/** Effective accessed bit. */
2843#define PGMPTWALK_EFF_A X86_PTE_A
2844/** The dirty bit of the final entry. */
2845#define PGMPTWALK_EFF_D X86_PTE_D
2846/** The PAT bit of the final entry. */
2847#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2848/** The global bit of the final entry. */
2849#define PGMPTWALK_EFF_G X86_PTE_G
2850/** @} */
2851
2852
2853/**
2854 * Guest page table walk for the AMD64 mode.
2855 */
2856typedef struct PGMPTWALKGSTAMD64
2857{
2858 /** The common core. */
2859 PGMPTWALKCORE Core;
2860
2861 PX86PML4 pPml4;
2862 PX86PML4E pPml4e;
2863 X86PML4E Pml4e;
2864
2865 PX86PDPT pPdpt;
2866 PX86PDPE pPdpe;
2867 X86PDPE Pdpe;
2868
2869 PX86PDPAE pPd;
2870 PX86PDEPAE pPde;
2871 X86PDEPAE Pde;
2872
2873 PX86PTPAE pPt;
2874 PX86PTEPAE pPte;
2875 X86PTEPAE Pte;
2876} PGMPTWALKGSTAMD64;
2877/** Pointer to a AMD64 guest page table walk. */
2878typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2879/** Pointer to a const AMD64 guest page table walk. */
2880typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2881
2882/**
2883 * Guest page table walk for the PAE mode.
2884 */
2885typedef struct PGMPTWALKGSTPAE
2886{
2887 /** The common core. */
2888 PGMPTWALKCORE Core;
2889
2890 PX86PDPT pPdpt;
2891 PX86PDPE pPdpe;
2892 X86PDPE Pdpe;
2893
2894 PX86PDPAE pPd;
2895 PX86PDEPAE pPde;
2896 X86PDEPAE Pde;
2897
2898 PX86PTPAE pPt;
2899 PX86PTEPAE pPte;
2900 X86PTEPAE Pte;
2901} PGMPTWALKGSTPAE;
2902/** Pointer to a PAE guest page table walk. */
2903typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2904/** Pointer to a const AMD64 guest page table walk. */
2905typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2906
2907/**
2908 * Guest page table walk for the 32-bit mode.
2909 */
2910typedef struct PGMPTWALKGST32BIT
2911{
2912 /** The common core. */
2913 PGMPTWALKCORE Core;
2914
2915 PX86PD pPd;
2916 PX86PDE pPde;
2917 X86PDE Pde;
2918
2919 PX86PT pPt;
2920 PX86PTE pPte;
2921 X86PTE Pte;
2922} PGMPTWALKGST32BIT;
2923/** Pointer to a 32-bit guest page table walk. */
2924typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2925/** Pointer to a const 32-bit guest page table walk. */
2926typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2927
2928/**
2929 * Which part of PGMPTWALKGST that is valid.
2930 */
2931typedef enum PGMPTWALKGSTTYPE
2932{
2933 /** Customary invalid 0 value. */
2934 PGMPTWALKGSTTYPE_INVALID = 0,
2935 /** PGMPTWALKGST::u.Amd64 is valid. */
2936 PGMPTWALKGSTTYPE_AMD64,
2937 /** PGMPTWALKGST::u.Pae is valid. */
2938 PGMPTWALKGSTTYPE_PAE,
2939 /** PGMPTWALKGST::u.Legacy is valid. */
2940 PGMPTWALKGSTTYPE_32BIT,
2941 /** Customary 32-bit type hack. */
2942 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2943} PGMPTWALKGSTTYPE;
2944
2945/**
2946 * Combined guest page table walk result.
2947 */
2948typedef struct PGMPTWALKGST
2949{
2950 union
2951 {
2952 /** The page walker core - always valid. */
2953 PGMPTWALKCORE Core;
2954 /** The page walker for AMD64. */
2955 PGMPTWALKGSTAMD64 Amd64;
2956 /** The page walker for PAE (32-bit). */
2957 PGMPTWALKGSTPAE Pae;
2958 /** The page walker for 32-bit paging (called legacy due to C naming
2959 * convension). */
2960 PGMPTWALKGST32BIT Legacy;
2961 } u;
2962 /** Indicates which part of the union is valid. */
2963 PGMPTWALKGSTTYPE enmType;
2964} PGMPTWALKGST;
2965/** Pointer to a combined guest page table walk result. */
2966typedef PGMPTWALKGST *PPGMPTWALKGST;
2967/** Pointer to a read-only combined guest page table walk result. */
2968typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2969
2970
2971/** @name Paging mode macros
2972 * @{
2973 */
2974#ifdef IN_RC
2975# define PGM_CTX(a,b) a##RC##b
2976# define PGM_CTX_STR(a,b) a "GC" b
2977# define PGM_CTX_DECL(type) VMMRCDECL(type)
2978#else
2979# ifdef IN_RING3
2980# define PGM_CTX(a,b) a##R3##b
2981# define PGM_CTX_STR(a,b) a "R3" b
2982# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2983# else
2984# define PGM_CTX(a,b) a##R0##b
2985# define PGM_CTX_STR(a,b) a "R0" b
2986# define PGM_CTX_DECL(type) VMMDECL(type)
2987# endif
2988#endif
2989
2990#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2991#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2992#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2993#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2994#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2995#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2996#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2997#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2998#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2999#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
3000#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
3001#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
3002#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
3003#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
3004#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
3005#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
3006
3007#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
3008#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
3009#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
3010#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
3011#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
3012#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
3013#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
3014#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
3015#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
3016#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
3017#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
3018#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
3019#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
3020#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
3021#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
3022#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
3023#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
3024#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
3025#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
3026#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
3027#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
3028#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
3029#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
3030#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
3031#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
3032
3033/* Shw_Gst */
3034#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
3035#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
3036#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
3037#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
3038#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
3039#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
3040#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
3041#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
3042#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
3043#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
3044#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
3045#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
3046#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
3047#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
3048#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
3049#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
3050#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
3051#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
3052#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
3053#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
3054#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
3055#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
3056#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
3057#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
3058#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
3059#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
3060#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
3061#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
3062#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
3063#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
3064#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
3065#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
3066#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
3067#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
3068
3069#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
3070#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
3071#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
3072#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
3073#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
3074#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
3075#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
3076#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
3077#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
3078#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
3079#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
3080#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
3081#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
3082#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
3083#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
3084#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
3085#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
3086#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
3087#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
3088#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
3089#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
3090#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
3091#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
3092#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
3093#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
3094#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
3095#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
3096#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
3097
3098#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
3099#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
3100#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
3101#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
3102#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
3103#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
3104#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
3105#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
3106#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
3107#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
3108#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
3109#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
3110#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
3111#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
3112#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
3113#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
3114#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
3115#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
3116#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
3117#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
3118#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
3119#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
3120#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
3121#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
3122#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3123#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3124#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3125#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3126#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3127
3128#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3129/** @} */
3130
3131
3132/**
3133 * Function pointers for guest paging.
3134 */
3135typedef struct PGMMODEDATAGST
3136{
3137 /** The guest mode type. */
3138 uint32_t uType;
3139 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
3140 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
3141 DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
3142 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3143 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3144#ifdef IN_RING3
3145 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3146#endif
3147} PGMMODEDATAGST;
3148
3149/** The length of g_aPgmGuestModeData. */
3150#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
3151# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
3152#else
3153# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3154#endif
3155/** The guest mode data array. */
3156extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
3157
3158
3159/**
3160 * Function pointers for shadow paging.
3161 */
3162typedef struct PGMMODEDATASHW
3163{
3164 /** The shadow mode type. */
3165 uint32_t uType;
3166 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
3167 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
3168 uint64_t fMask, uint32_t fOpFlags);
3169 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
3170 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3171#ifdef IN_RING3
3172 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3173#endif
3174} PGMMODEDATASHW;
3175
3176/** The length of g_aPgmShadowModeData. */
3177#ifndef IN_RC
3178# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
3179#else
3180# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3181#endif
3182/** The shadow mode data array. */
3183extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
3184
3185
3186/**
3187 * Function pointers for guest+shadow paging.
3188 */
3189typedef struct PGMMODEDATABTH
3190{
3191 /** The shadow mode type. */
3192 uint32_t uShwType;
3193 /** The guest mode type. */
3194 uint32_t uGstType;
3195
3196 DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3197 DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
3198 DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3199 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
3200 DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3201 DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPU pVCpu);
3202 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3203#ifndef IN_RING3
3204 DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
3205#endif
3206#ifdef VBOX_STRICT
3207 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
3208#endif
3209} PGMMODEDATABTH;
3210
3211/** The length of g_aPgmBothModeData. */
3212#ifndef IN_RC
3213# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3214#else
3215# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_PAE + 1 - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3216#endif
3217/** The guest+shadow mode data array. */
3218extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
3219
3220
3221#ifdef VBOX_WITH_STATISTICS
3222/**
3223 * PGM statistics.
3224 *
3225 * These lives on the heap when compiled in as they would otherwise waste
3226 * unnecessary space in release builds.
3227 */
3228typedef struct PGMSTATS
3229{
3230 /* R3 only: */
3231 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3232 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3233
3234 /* R3+RZ */
3235 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3236 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3237 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3238 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3239 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3240 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3241 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3242 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3243 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3244 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3245 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3246 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3247 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3248 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3249 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3250 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3251 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3252 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3253 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3254 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3255 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3256 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3257 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3258 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3259 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3260 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3261 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3262 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3263/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3264 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3265 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3266/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3267
3268 /* RC only: */
3269 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3270 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3271
3272 STAMCOUNTER StatRZPhysRead;
3273 STAMCOUNTER StatRZPhysReadBytes;
3274 STAMCOUNTER StatRZPhysWrite;
3275 STAMCOUNTER StatRZPhysWriteBytes;
3276 STAMCOUNTER StatR3PhysRead;
3277 STAMCOUNTER StatR3PhysReadBytes;
3278 STAMCOUNTER StatR3PhysWrite;
3279 STAMCOUNTER StatR3PhysWriteBytes;
3280 STAMCOUNTER StatRCPhysRead;
3281 STAMCOUNTER StatRCPhysReadBytes;
3282 STAMCOUNTER StatRCPhysWrite;
3283 STAMCOUNTER StatRCPhysWriteBytes;
3284
3285 STAMCOUNTER StatRZPhysSimpleRead;
3286 STAMCOUNTER StatRZPhysSimpleReadBytes;
3287 STAMCOUNTER StatRZPhysSimpleWrite;
3288 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3289 STAMCOUNTER StatR3PhysSimpleRead;
3290 STAMCOUNTER StatR3PhysSimpleReadBytes;
3291 STAMCOUNTER StatR3PhysSimpleWrite;
3292 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3293 STAMCOUNTER StatRCPhysSimpleRead;
3294 STAMCOUNTER StatRCPhysSimpleReadBytes;
3295 STAMCOUNTER StatRCPhysSimpleWrite;
3296 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3297
3298 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3299 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3300 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3301 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3302 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3303 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3304 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3305
3306 /** Time spent by the host OS for large page allocation. */
3307 STAMPROFILE StatAllocLargePage;
3308 /** Time spent clearing the newly allocated large pages. */
3309 STAMPROFILE StatClearLargePage;
3310 /** The number of times allocating a large pages takes more than the allowed period. */
3311 STAMCOUNTER StatLargePageOverflow;
3312 /** pgmPhysIsValidLargePage profiling - R3 */
3313 STAMPROFILE StatR3IsValidLargePage;
3314 /** pgmPhysIsValidLargePage profiling - RZ*/
3315 STAMPROFILE StatRZIsValidLargePage;
3316
3317 STAMPROFILE StatChunkAging;
3318 STAMPROFILE StatChunkFindCandidate;
3319 STAMPROFILE StatChunkUnmap;
3320 STAMPROFILE StatChunkMap;
3321} PGMSTATS;
3322#endif /* VBOX_WITH_STATISTICS */
3323
3324
3325/**
3326 * Converts a PGM pointer into a VM pointer.
3327 * @returns Pointer to the VM structure the PGM is part of.
3328 * @param pPGM Pointer to PGM instance data.
3329 */
3330#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3331
3332/**
3333 * PGM Data (part of VM)
3334 */
3335typedef struct PGM
3336{
3337 /** Offset to the VM structure. */
3338 int32_t offVM;
3339 /** Offset of the PGMCPU structure relative to VMCPU. */
3340 int32_t offVCpuPGM;
3341
3342 /** @cfgm{/RamPreAlloc, boolean, false}
3343 * Indicates whether the base RAM should all be allocated before starting
3344 * the VM (default), or if it should be allocated when first written to.
3345 */
3346 bool fRamPreAlloc;
3347 /** Indicates whether write monitoring is currently in use.
3348 * This is used to prevent conflicts between live saving and page sharing
3349 * detection. */
3350 bool fPhysWriteMonitoringEngaged;
3351 /** Set if the CPU has less than 52-bit physical address width.
3352 * This is used */
3353 bool fLessThan52PhysicalAddressBits;
3354 /** Set when nested paging is active.
3355 * This is meant to save calls to HMIsNestedPagingActive and let the
3356 * compilers optimize the code better. Whether we use nested paging or
3357 * not is something we find out during VMM initialization and we won't
3358 * change this later on. */
3359 bool fNestedPaging;
3360 /** The host paging mode. (This is what SUPLib reports.) */
3361 SUPPAGINGMODE enmHostMode;
3362 /** We're not in a state which permits writes to guest memory.
3363 * (Only used in strict builds.) */
3364 bool fNoMorePhysWrites;
3365 /** @cfgm{/PageFusionAllowed, boolean, false}
3366 * Whether page fusion is allowed. */
3367 bool fPageFusionAllowed;
3368 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3369 * Whether PCI passthrough is enabled. */
3370 bool fPciPassthrough;
3371 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3372 uint8_t cMmio2Regions;
3373 /** Restore original ROM page content when resetting after loading state.
3374 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3375 * enables the VM to start using an updated ROM without requiring powering
3376 * down the VM, just rebooting or resetting it. */
3377 bool fRestoreRomPagesOnReset;
3378 /** Whether to automatically clear all RAM pages on reset. */
3379 bool fZeroRamPagesOnReset;
3380 /** Alignment padding. */
3381 bool afAlignment3[7];
3382
3383 /** Indicates that PGMR3FinalizeMappings has been called and that further
3384 * PGMR3MapIntermediate calls will be rejected. */
3385 bool fFinalizedMappings;
3386 /** If set no conflict checks are required. */
3387 bool fMappingsFixed;
3388 /** If set if restored as fixed but we were unable to re-fixate at the old
3389 * location because of room or address incompatibilities. */
3390 bool fMappingsFixedRestored;
3391 /** Size of fixed mapping.
3392 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3393 uint32_t cbMappingFixed;
3394 /** Generation ID for the RAM ranges. This member is incremented everytime
3395 * a RAM range is linked or unlinked. */
3396 uint32_t volatile idRamRangesGen;
3397
3398 /** Base address (GC) of fixed mapping.
3399 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3400 RTGCPTR GCPtrMappingFixed;
3401 /** The address of the previous RAM range mapping. */
3402 RTGCPTR GCPtrPrevRamRangeMapping;
3403
3404 /** Physical access handler type for ROM protection. */
3405 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3406 /** Alignment padding. */
3407 uint32_t u32Padding;
3408
3409 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3410 RTGCPHYS GCPhys4MBPSEMask;
3411 /** Mask containing the invalid bits of a guest physical address.
3412 * @remarks this does not stop at bit 52. */
3413 RTGCPHYS GCPhysInvAddrMask;
3414
3415
3416 /** RAM range TLB for R3. */
3417 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3418 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3419 * This is sorted by physical address and contains no overlapping ranges. */
3420 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3421 /** Root of the RAM range search tree for ring-3. */
3422 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3423 /** PGM offset based trees - R3 Ptr. */
3424 R3PTRTYPE(PPGMTREES) pTreesR3;
3425 /** Caching the last physical handler we looked up in R3. */
3426 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3427 /** Shadow Page Pool - R3 Ptr. */
3428 R3PTRTYPE(PPGMPOOL) pPoolR3;
3429 /** Linked list of GC mappings - for HC.
3430 * The list is sorted ascending on address. */
3431 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3432 /** Pointer to the list of ROM ranges - for R3.
3433 * This is sorted by physical address and contains no overlapping ranges. */
3434 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3435 /** Pointer to the list of MMIO2 ranges - for R3.
3436 * Registration order. */
3437 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3438 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3439 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3440
3441 /** RAM range TLB for R0. */
3442 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3443 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3444 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3445 /** Root of the RAM range search tree for ring-0. */
3446 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3447 /** PGM offset based trees - R0 Ptr. */
3448 R0PTRTYPE(PPGMTREES) pTreesR0;
3449 /** Caching the last physical handler we looked up in R0. */
3450 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3451 /** Shadow Page Pool - R0 Ptr. */
3452 R0PTRTYPE(PPGMPOOL) pPoolR0;
3453 /** Linked list of GC mappings - for R0.
3454 * The list is sorted ascending on address. */
3455 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3456 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3457 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3458 RTR0PTR R0PtrAlignment0;
3459 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3460 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3461
3462 /** RAM range TLB for RC. */
3463 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3464 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3465 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3466 /** Root of the RAM range search tree for raw-mode context. */
3467 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3468 /** PGM offset based trees - RC Ptr. */
3469 RCPTRTYPE(PPGMTREES) pTreesRC;
3470 /** Caching the last physical handler we looked up in RC. */
3471 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3472 /** Shadow Page Pool - RC Ptr. */
3473 RCPTRTYPE(PPGMPOOL) pPoolRC;
3474 /** Linked list of GC mappings - for RC.
3475 * The list is sorted ascending on address. */
3476 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3477 /** RC pointer corresponding to PGM::pRomRangesR3. */
3478 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3479 RTRCPTR RCPtrAlignment0;
3480 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3481 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3482 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3483 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3484
3485
3486 /** Pointer to the 5 page CR3 content mapping.
3487 * The first page is always the CR3 (in some form) while the 4 other pages
3488 * are used for the PDs in PAE mode. */
3489 RTGCPTR GCPtrCR3Mapping;
3490
3491 /** @name Intermediate Context
3492 * @{ */
3493 /** Pointer to the intermediate page directory - Normal. */
3494 R3PTRTYPE(PX86PD) pInterPD;
3495 /** Pointer to the intermediate page tables - Normal.
3496 * There are two page tables, one for the identity mapping and one for
3497 * the host context mapping (of the core code). */
3498 R3PTRTYPE(PX86PT) apInterPTs[2];
3499 /** Pointer to the intermediate page tables - PAE. */
3500 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3501 /** Pointer to the intermediate page directory - PAE. */
3502 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3503 /** Pointer to the intermediate page directory - PAE. */
3504 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3505 /** Pointer to the intermediate page-map level 4 - AMD64. */
3506 R3PTRTYPE(PX86PML4) pInterPaePML4;
3507 /** Pointer to the intermediate page directory - AMD64. */
3508 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3509 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3510 RTHCPHYS HCPhysInterPD;
3511 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3512 RTHCPHYS HCPhysInterPaePDPT;
3513 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3514 RTHCPHYS HCPhysInterPaePML4;
3515 /** @} */
3516
3517 /** Base address of the dynamic page mapping area.
3518 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3519 *
3520 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3521 * work out. Some cleaning up of the initialization that would
3522 * remove this memory is yet to be done...
3523 */
3524 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3525 /** The address of the raw-mode context mapping cache. */
3526 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3527 /** The address of the ring-0 mapping cache if we're making use of it. */
3528 RTR0PTR pvR0DynMapUsed;
3529
3530 /** Hack: Number of deprecated page mapping locks taken by the current lock
3531 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3532 uint32_t cDeprecatedPageLocks;
3533#if HC_ARCH_BITS == 64
3534 /** Alignment padding. */
3535 uint32_t u32Alignment2;
3536#endif
3537
3538
3539 /** PGM critical section.
3540 * This protects the physical & virtual access handlers, ram ranges,
3541 * and the page flag updating (some of it anyway).
3542 */
3543 PDMCRITSECT CritSectX;
3544
3545 /**
3546 * Data associated with managing the ring-3 mappings of the allocation chunks.
3547 */
3548 struct
3549 {
3550 /** The chunk tree, ordered by chunk id. */
3551#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3552 R3PTRTYPE(PAVLU32NODECORE) pTree;
3553#else
3554 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3555#endif
3556#if HC_ARCH_BITS == 32
3557 uint32_t u32Alignment0;
3558#endif
3559 /** The chunk mapping TLB. */
3560 PGMCHUNKR3MAPTLB Tlb;
3561 /** The number of mapped chunks. */
3562 uint32_t c;
3563 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3564 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3565 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3566 uint32_t cMax;
3567 /** The current time. This is incremented whenever a chunk is inserted. */
3568 uint32_t iNow;
3569 /** Alignment padding. */
3570 uint32_t u32Alignment1;
3571 } ChunkR3Map;
3572
3573 /**
3574 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3575 */
3576 PGMPAGER3MAPTLB PhysTlbHC;
3577
3578 /** @name The zero page.
3579 * @{ */
3580 /** The host physical address of the zero page. */
3581 RTHCPHYS HCPhysZeroPg;
3582 /** The ring-3 mapping of the zero page. */
3583 RTR3PTR pvZeroPgR3;
3584 /** The ring-0 mapping of the zero page. */
3585 RTR0PTR pvZeroPgR0;
3586 /** The GC mapping of the zero page. */
3587 RTRCPTR pvZeroPgRC;
3588 RTRCPTR RCPtrAlignment3;
3589 /** @}*/
3590
3591 /** @name The Invalid MMIO page.
3592 * This page is filled with 0xfeedface.
3593 * @{ */
3594 /** The host physical address of the invalid MMIO page. */
3595 RTHCPHYS HCPhysMmioPg;
3596 /** The host pysical address of the invalid MMIO page plus all invalid
3597 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3598 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3599 RTHCPHYS HCPhysInvMmioPg;
3600 /** The ring-3 mapping of the invalid MMIO page. */
3601 RTR3PTR pvMmioPgR3;
3602#if HC_ARCH_BITS == 32
3603 RTR3PTR R3PtrAlignment4;
3604#endif
3605 /** @} */
3606
3607
3608 /** The number of handy pages. */
3609 uint32_t cHandyPages;
3610
3611 /** The number of large handy pages. */
3612 uint32_t cLargeHandyPages;
3613
3614 /**
3615 * Array of handy pages.
3616 *
3617 * This array is used in a two way communication between pgmPhysAllocPage
3618 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3619 * an intermediary.
3620 *
3621 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3622 * (The current size of 32 pages, means 128 KB of handy memory.)
3623 */
3624 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3625
3626 /**
3627 * Array of large handy pages. (currently size 1)
3628 *
3629 * This array is used in a two way communication between pgmPhysAllocLargePage
3630 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3631 * an intermediary.
3632 */
3633 GMMPAGEDESC aLargeHandyPage[1];
3634
3635 /**
3636 * Live save data.
3637 */
3638 struct
3639 {
3640 /** Per type statistics. */
3641 struct
3642 {
3643 /** The number of ready pages. */
3644 uint32_t cReadyPages;
3645 /** The number of dirty pages. */
3646 uint32_t cDirtyPages;
3647 /** The number of ready zero pages. */
3648 uint32_t cZeroPages;
3649 /** The number of write monitored pages. */
3650 uint32_t cMonitoredPages;
3651 } Rom,
3652 Mmio2,
3653 Ram;
3654 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3655 uint32_t cIgnoredPages;
3656 /** Indicates that a live save operation is active. */
3657 bool fActive;
3658 /** Padding. */
3659 bool afReserved[2];
3660 /** The next history index. */
3661 uint8_t iDirtyPagesHistory;
3662 /** History of the total amount of dirty pages. */
3663 uint32_t acDirtyPagesHistory[64];
3664 /** Short term dirty page average. */
3665 uint32_t cDirtyPagesShort;
3666 /** Long term dirty page average. */
3667 uint32_t cDirtyPagesLong;
3668 /** The number of saved pages. This is used to get some kind of estimate of the
3669 * link speed so we can decide when we're done. It is reset after the first
3670 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3671 * zero pages. */
3672 uint64_t cSavedPages;
3673 /** The nanosecond timestamp when cSavedPages was 0. */
3674 uint64_t uSaveStartNS;
3675 /** Pages per second (for statistics). */
3676 uint32_t cPagesPerSecond;
3677 uint32_t cAlignment;
3678 } LiveSave;
3679
3680 /** @name Error injection.
3681 * @{ */
3682 /** Inject handy page allocation errors pretending we're completely out of
3683 * memory. */
3684 bool volatile fErrInjHandyPages;
3685 /** Padding. */
3686 bool afReserved[3];
3687 /** @} */
3688
3689 /** @name Release Statistics
3690 * @{ */
3691 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3692 uint32_t cPrivatePages; /**< The number of private pages. */
3693 uint32_t cSharedPages; /**< The number of shared pages. */
3694 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3695 uint32_t cZeroPages; /**< The number of zero backed pages. */
3696 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3697 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3698 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3699 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3700 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3701 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3702 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3703 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3704 uint32_t cLargePages; /**< The number of large pages. */
3705 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3706/* uint32_t aAlignment4[1]; */
3707
3708 /** The number of times we were forced to change the hypervisor region location. */
3709 STAMCOUNTER cRelocations;
3710
3711 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3712 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3713 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3714
3715 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3716 /** @} */
3717
3718#ifdef VBOX_WITH_STATISTICS
3719 /** @name Statistics on the heap.
3720 * @{ */
3721 R3PTRTYPE(PGMSTATS *) pStatsR3;
3722 R0PTRTYPE(PGMSTATS *) pStatsR0;
3723 RCPTRTYPE(PGMSTATS *) pStatsRC;
3724 RTRCPTR RCPtrAlignment;
3725 /** @} */
3726#endif
3727} PGM;
3728#ifndef IN_TSTVMSTRUCTGC /* HACK */
3729AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3730AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3731AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3732AssertCompileMemberAlignment(PGM, CritSectX, 8);
3733AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3734AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3735AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3736AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3737AssertCompileMemberAlignment(PGM, cRelocations, 8);
3738#endif /* !IN_TSTVMSTRUCTGC */
3739/** Pointer to the PGM instance data. */
3740typedef PGM *PPGM;
3741
3742
3743
3744typedef struct PGMCPUSTATS
3745{
3746 /* Common */
3747 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3748 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3749
3750 /* R0 only: */
3751 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3752 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3753
3754 /* RZ only: */
3755 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3756 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3757 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3758 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3759 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3760 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3761 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3762 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3763 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3764 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3765 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3766 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3767 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3768 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3769 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3770 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3771 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3772 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3773 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3774 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3775 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3776 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3777 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3778 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3779 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3780 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3781 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3782 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3783 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3784 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3785 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3786 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3787 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3788 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3789 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3790 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3791 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3792 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3793 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3794 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3795 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3796 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3797 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3798 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3799 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3800 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3801 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3802 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3803 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3804 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3805 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3806 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3807 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3808 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3809 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3810 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3811 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3812 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3813 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3814 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3815 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3816 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3817 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3818 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3819 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3820 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3821 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3822 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3823 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3824 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3825 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3826 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3827 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3828 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3829 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3830 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3831 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3832 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3833
3834 /* HC - R3 and (maybe) R0: */
3835
3836 /* RZ & R3: */
3837 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3838 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3839 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3840 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3841 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3842 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3843 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3844 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3845 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3846 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3847 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3848 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3849 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3850 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3851 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3852 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3853 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3854 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3855 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3856 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3857 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3858 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3859 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3860 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3861 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3862 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3863 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3864 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3865 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3866 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3867 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3868 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3869 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3870 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3871 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3872 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3873 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3874 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3875 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3876 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3877 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3878 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3879 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3880 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3881 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3882 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3883 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3884 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3885
3886 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3887 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3888 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3889 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3890 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3891 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3892 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3893 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3894 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3895 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3896 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3897 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3898 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3899 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3900 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3901 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3902 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3903 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3904 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3905 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3906 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3907 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3908 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3909 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3910 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3911 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3912 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3913 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3914 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3915 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3916 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3917 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3918 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3919 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3920 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3921 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3922 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3923 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3924 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3925 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3926 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3927 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3928 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3929 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3930 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3931 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3932 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3933 /** @} */
3934} PGMCPUSTATS;
3935
3936
3937/**
3938 * Converts a PGMCPU pointer into a VM pointer.
3939 * @returns Pointer to the VM structure the PGM is part of.
3940 * @param pPGM Pointer to PGMCPU instance data.
3941 */
3942#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3943
3944/**
3945 * Converts a PGMCPU pointer into a PGM pointer.
3946 * @returns Pointer to the VM structure the PGM is part of.
3947 * @param pPGMCpu Pointer to PGMCPU instance data.
3948 */
3949#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3950
3951/**
3952 * PGMCPU Data (part of VMCPU).
3953 */
3954typedef struct PGMCPU
3955{
3956 /** Offset to the VM structure. */
3957 int32_t offVM;
3958 /** Offset to the VMCPU structure. */
3959 int32_t offVCpu;
3960 /** Offset of the PGM structure relative to VMCPU. */
3961 int32_t offPGM;
3962 uint32_t uPadding0; /**< structure size alignment. */
3963
3964#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3965 /** Automatically tracked physical memory mapping set.
3966 * Ring-0 and strict raw-mode builds. */
3967 PGMMAPSET AutoSet;
3968#endif
3969
3970 /** A20 gate mask.
3971 * Our current approach to A20 emulation is to let REM do it and don't bother
3972 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3973 * But whould need arrise, we'll subject physical addresses to this mask. */
3974 RTGCPHYS GCPhysA20Mask;
3975 /** A20 gate state - boolean! */
3976 bool fA20Enabled;
3977 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3978 bool fNoExecuteEnabled;
3979 /** Unused bits. */
3980 bool afUnused[2];
3981
3982 /** What needs syncing (PGM_SYNC_*).
3983 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3984 * PGMFlushTLB, and PGMR3Load. */
3985 uint32_t fSyncFlags;
3986
3987 /** The shadow paging mode. */
3988 PGMMODE enmShadowMode;
3989 /** The guest paging mode. */
3990 PGMMODE enmGuestMode;
3991 /** Guest mode data table index (PGM_TYPE_XXX). */
3992 uint8_t volatile idxGuestModeData;
3993 /** Shadow mode data table index (PGM_TYPE_XXX). */
3994 uint8_t volatile idxShadowModeData;
3995 /** Both mode data table index (complicated). */
3996 uint8_t volatile idxBothModeData;
3997 /** Alignment padding. */
3998 uint8_t abPadding[5];
3999
4000 /** The current physical address represented in the guest CR3 register. */
4001 RTGCPHYS GCPhysCR3;
4002
4003 /** @name 32-bit Guest Paging.
4004 * @{ */
4005 /** The guest's page directory, R3 pointer. */
4006 R3PTRTYPE(PX86PD) pGst32BitPdR3;
4007#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4008 /** The guest's page directory, R0 pointer. */
4009 R0PTRTYPE(PX86PD) pGst32BitPdR0;
4010#endif
4011 /** The guest's page directory, static RC mapping. */
4012 RCPTRTYPE(PX86PD) pGst32BitPdRC;
4013 /** Mask containing the MBZ bits of a big page PDE. */
4014 uint32_t fGst32BitMbzBigPdeMask;
4015 /** Set if the page size extension (PSE) is enabled. */
4016 bool fGst32BitPageSizeExtension;
4017 /** Alignment padding. */
4018 bool afAlignment2[3];
4019 /** @} */
4020
4021 /** @name PAE Guest Paging.
4022 * @{ */
4023 /** The guest's page directory pointer table, static RC mapping. */
4024 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
4025 /** The guest's page directory pointer table, R3 pointer. */
4026 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
4027#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4028 /** The guest's page directory pointer table, R0 pointer. */
4029 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
4030#endif
4031
4032 /** The guest's page directories, R3 pointers.
4033 * These are individual pointers and don't have to be adjacent.
4034 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4035 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
4036 /** The guest's page directories, R0 pointers.
4037 * Same restrictions as apGstPaePDsR3. */
4038#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4039 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
4040#endif
4041 /** The guest's page directories, static GC mapping.
4042 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
4043 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4044 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
4045 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
4046 * @todo Remove this and use aGstPaePdpeRegs instead? */
4047 RTGCPHYS aGCPhysGstPaePDs[4];
4048 /** The values of the 4 PDPE CPU registers (PAE). */
4049 X86PDPE aGstPaePdpeRegs[4];
4050 /** The physical addresses of the monitored guest page directories (PAE). */
4051 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
4052 /** Mask containing the MBZ PTE bits. */
4053 uint64_t fGstPaeMbzPteMask;
4054 /** Mask containing the MBZ PDE bits. */
4055 uint64_t fGstPaeMbzPdeMask;
4056 /** Mask containing the MBZ big page PDE bits. */
4057 uint64_t fGstPaeMbzBigPdeMask;
4058 /** Mask containing the MBZ PDPE bits. */
4059 uint64_t fGstPaeMbzPdpeMask;
4060 /** @} */
4061
4062 /** @name AMD64 Guest Paging.
4063 * @{ */
4064 /** The guest's page directory pointer table, R3 pointer. */
4065 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
4066#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4067 /** The guest's page directory pointer table, R0 pointer. */
4068 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
4069#else
4070 RTR0PTR alignment6b; /**< alignment equalizer. */
4071#endif
4072 /** Mask containing the MBZ PTE bits. */
4073 uint64_t fGstAmd64MbzPteMask;
4074 /** Mask containing the MBZ PDE bits. */
4075 uint64_t fGstAmd64MbzPdeMask;
4076 /** Mask containing the MBZ big page PDE bits. */
4077 uint64_t fGstAmd64MbzBigPdeMask;
4078 /** Mask containing the MBZ PDPE bits. */
4079 uint64_t fGstAmd64MbzPdpeMask;
4080 /** Mask containing the MBZ big page PDPE bits. */
4081 uint64_t fGstAmd64MbzBigPdpeMask;
4082 /** Mask containing the MBZ PML4E bits. */
4083 uint64_t fGstAmd64MbzPml4eMask;
4084 /** Mask containing the PDPE bits that we shadow. */
4085 uint64_t fGstAmd64ShadowedPdpeMask;
4086 /** Mask containing the PML4E bits that we shadow. */
4087 uint64_t fGstAmd64ShadowedPml4eMask;
4088 /** @} */
4089
4090 /** @name PAE and AMD64 Guest Paging.
4091 * @{ */
4092 /** Mask containing the PTE bits that we shadow. */
4093 uint64_t fGst64ShadowedPteMask;
4094 /** Mask containing the PDE bits that we shadow. */
4095 uint64_t fGst64ShadowedPdeMask;
4096 /** Mask containing the big page PDE bits that we shadow in the PDE. */
4097 uint64_t fGst64ShadowedBigPdeMask;
4098 /** Mask containing the big page PDE bits that we shadow in the PTE. */
4099 uint64_t fGst64ShadowedBigPde4PteMask;
4100 /** @} */
4101
4102 /** Pointer to the page of the current active CR3 - R3 Ptr. */
4103 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
4104 /** Pointer to the page of the current active CR3 - R0 Ptr. */
4105 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
4106 /** Pointer to the page of the current active CR3 - RC Ptr. */
4107 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
4108 /** Explicit alignment. */
4109 RTRCPTR alignment6;
4110 /** @} */
4111
4112 /** For saving stack space, the disassembler state is allocated here instead of
4113 * on the stack. */
4114 DISCPUSTATE DisState;
4115
4116 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4117 uint64_t cNetwareWp0Hacks;
4118
4119 /** Count the number of pgm pool access handler calls. */
4120 uint64_t cPoolAccessHandler;
4121
4122 /** @name Release Statistics
4123 * @{ */
4124 /** The number of times the guest has switched mode since last reset or statistics reset. */
4125 STAMCOUNTER cGuestModeChanges;
4126 /** The number of times the guest has switched mode since last reset or statistics reset. */
4127 STAMCOUNTER cA20Changes;
4128 /** @} */
4129
4130#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4131 /** @name Statistics
4132 * @{ */
4133 /** RC: Pointer to the statistics. */
4134 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4135 /** RC: Which statistic this \#PF should be attributed to. */
4136 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4137 /** R0: Pointer to the statistics. */
4138 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4139 /** R0: Which statistic this \#PF should be attributed to. */
4140 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4141 /** R3: Pointer to the statistics. */
4142 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4143 /** Alignment padding. */
4144 RTR3PTR pPaddingR3;
4145 /** @} */
4146#endif /* VBOX_WITH_STATISTICS */
4147} PGMCPU;
4148/** Pointer to the per-cpu PGM data. */
4149typedef PGMCPU *PPGMCPU;
4150
4151
4152/** @name PGM::fSyncFlags Flags
4153 * @note Was part of saved state a long time ago.
4154 * @{
4155 */
4156/** Updates the virtual access handler state bit in PGMPAGE. */
4157#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4158/** Always sync CR3. */
4159#define PGM_SYNC_ALWAYS RT_BIT(1)
4160/** Check monitoring on next CR3 (re)load and invalidate page.
4161 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4162#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4163/** Check guest mapping in SyncCR3. */
4164#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4165/** Clear the page pool (a light weight flush). */
4166#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4167#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4168/** @} */
4169
4170
4171RT_C_DECLS_BEGIN
4172
4173#if defined(VBOX_STRICT) && defined(IN_RING3)
4174int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4175# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4176#else
4177int pgmLock(PVM pVM);
4178#endif
4179void pgmUnlock(PVM pVM);
4180/**
4181 * Asserts that the caller owns the PDM lock.
4182 * This is the internal variant of PGMIsLockOwner.
4183 * @param a_pVM Pointer to the VM.
4184 */
4185#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4186/**
4187 * Asserts that the caller owns the PDM lock.
4188 * This is the internal variant of PGMIsLockOwner.
4189 * @param a_pVM Pointer to the VM.
4190 * @param a_pVCpu The current CPU handle.
4191 */
4192#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4193
4194#ifndef PGM_WITHOUT_MAPPINGS
4195int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4196int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4197int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4198int pgmMapResolveConflicts(PVM pVM);
4199#endif /* !PGM_WITHOUT_MAPPINGS */
4200PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4201DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4202
4203int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4204 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
4205int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4206int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4207int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4208int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4209void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4210bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4211void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4212#ifdef VBOX_WITH_RAW_MODE
4213PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4214DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4215# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4216void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4217# else
4218# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4219# endif
4220#endif /* VBOX_WITH_RAW_MODE */
4221DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4222int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4223
4224int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4225int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4226int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4227int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4228int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4229void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4230int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4231int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4232int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4233int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4234int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4235int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4236int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4237int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4238int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4239int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4240void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4241PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4242#ifndef IN_RING3
4243DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4244DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4245DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4246#endif
4247int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4248 PGMPAGETYPE enmNewType);
4249void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4250void pgmPhysInvalidatePageMapTLB(PVM pVM);
4251void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4252PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4253PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4254PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4255int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4256int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4257
4258#ifdef IN_RING3
4259void pgmR3PhysRelinkRamRanges(PVM pVM);
4260int pgmR3PhysRamPreAllocate(PVM pVM);
4261int pgmR3PhysRamReset(PVM pVM);
4262int pgmR3PhysRomReset(PVM pVM);
4263int pgmR3PhysRamZeroAll(PVM pVM);
4264int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4265int pgmR3PhysRamTerm(PVM pVM);
4266void pgmR3PhysRomTerm(PVM pVM);
4267void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4268
4269int pgmR3PoolInit(PVM pVM);
4270void pgmR3PoolRelocate(PVM pVM);
4271void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4272void pgmR3PoolReset(PVM pVM);
4273void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4274DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4275void pgmR3PoolWriteProtectPages(PVM pVM);
4276
4277#endif /* IN_RING3 */
4278#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4279int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4280int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4281# ifdef LOG_ENABLED
4282void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4283# else
4284void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4285# endif
4286#endif
4287int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4288 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4289void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4290void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4291int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4292void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4293PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4294PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4295int pgmPoolSyncCR3(PVMCPU pVCpu);
4296bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4297void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4298int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4299void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4300uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4301void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4302void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4303void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4304PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4305#ifndef IN_RING3
4306DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4307#endif
4308
4309void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4310void pgmPoolResetDirtyPages(PVM pVM);
4311void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4312
4313int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4314int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4315void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4316
4317void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4318void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4319int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4320int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4321
4322int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4323int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4324int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4325
4326int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4327int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4328int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4329int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4330int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4331int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4332
4333# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4334FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4335FNDBGCCMD pgmR3CmdShowSharedModules;
4336# endif
4337
4338void pgmLogState(PVM pVM);
4339
4340RT_C_DECLS_END
4341
4342/** @} */
4343
4344#endif
4345
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