VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 80074

Last change on this file since 80074 was 80074, checked in by vboxsync, 5 years ago

VMM,Main,++: Retired the unfinished FTM component.
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1/* $Id: PGMInternal.h 80074 2019-07-31 14:18:34Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Indicates that there are no guest mappings in the shadow tables.
62 *
63 * Note! In ring-3 the macro is also used to exclude the managment of the
64 * intermediate context page tables. On 32-bit systems we use the intermediate
65 * context to support 64-bit guest execution. Thus, we cannot fully make it
66 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67 *
68 * In raw-mode context there are by design always guest mappings (the code is
69 * executed from one), while in ring-0 there are none at all. Neither context
70 * manages the page tables for intermediate switcher context, that's all done in
71 * ring-3.
72 */
73#if defined(IN_RING0) \
74 || ( !defined(VBOX_WITH_RAW_MODE) \
75 && ( HC_ARCH_BITS != 32 \
76 || !defined(VBOX_WITH_64_BITS_GUESTS) \
77 ) \
78 )
79# define PGM_WITHOUT_MAPPINGS
80#endif
81
82/**
83 * Check and skip global PDEs for non-global flushes
84 */
85#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
86
87/**
88 * Optimization for PAE page tables that are modified often
89 */
90//#if 0 /* disabled again while debugging */
91#ifndef IN_RC
92# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
93#endif
94//#endif
95
96/**
97 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
98 */
99#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
100# define PGM_WITH_LARGE_PAGES
101#endif
102
103/**
104 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
105 * VMX_EXIT_EPT_MISCONFIG.
106 */
107#if 1 /* testing */
108# define PGM_WITH_MMIO_OPTIMIZATIONS
109#endif
110
111/**
112 * Sync N pages instead of a whole page table
113 */
114#define PGM_SYNC_N_PAGES
115
116/**
117 * Number of pages to sync during a page fault
118 *
119 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
120 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
121 *
122 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
123 * world switch overhead, so let's sync more.
124 */
125# ifdef IN_RING0
126/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
127 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
128 * but ~5% fewer faults.
129 */
130# define PGM_SYNC_NR_PAGES 32
131#else
132# define PGM_SYNC_NR_PAGES 8
133#endif
134
135/**
136 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
137 */
138#define PGM_MAX_PHYSCACHE_ENTRIES 64
139#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
140
141
142/** @def PGMPOOL_CFG_MAX_GROW
143 * The maximum number of pages to add to the pool in one go.
144 */
145#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
146
147/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
148 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
149 */
150#ifdef VBOX_STRICT
151# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
152#endif
153
154/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155 * Enables the experimental lazy page allocation code. */
156#ifdef DOXYGEN_RUNNING
157# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
158#endif
159
160/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161 * Enables real write monitoring of pages, i.e. mapping them read-only and
162 * only making them writable when getting a write access \#PF. */
163#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165/** @} */
166
167
168/** @name PDPT and PML4 flags.
169 * These are placed in the three bits available for system programs in
170 * the PDPT and PML4 entries.
171 * @{ */
172/** The entry is a permanent one and it's must always be present.
173 * Never free such an entry. */
174#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175/** Mapping (hypervisor allocated pagetable). */
176#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177/** @} */
178
179/** @name Page directory flags.
180 * These are placed in the three bits available for system programs in
181 * the page directory entries.
182 * @{ */
183/** Indicates the original entry was a big page.
184 * @remarks This is currently only used for statistics and can be recycled. */
185#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
186/** Mapping (hypervisor allocated pagetable). */
187#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
188/** Made read-only to facilitate dirty bit tracking. */
189#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
190/** @} */
191
192/** @name Page flags.
193 * These are placed in the three bits available for system programs in
194 * the page entries.
195 * @{ */
196/** Made read-only to facilitate dirty bit tracking. */
197#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
198
199#ifndef PGM_PTFLAGS_CSAM_VALIDATED
200/** Scanned and approved by CSAM (tm).
201 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
202 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
203#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
204#endif
205
206/** @} */
207
208/** @name Defines used to indicate the shadow and guest paging in the templates.
209 * @{ */
210#define PGM_TYPE_REAL 1
211#define PGM_TYPE_PROT 2
212#define PGM_TYPE_32BIT 3
213#define PGM_TYPE_PAE 4
214#define PGM_TYPE_AMD64 5
215#define PGM_TYPE_NESTED_32BIT 6
216#define PGM_TYPE_NESTED_PAE 7
217#define PGM_TYPE_NESTED_AMD64 8
218#define PGM_TYPE_EPT 9
219#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
220#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
221#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
222/** @} */
223
224/** Macro for checking if the guest is using paging.
225 * @param uGstType PGM_TYPE_*
226 * @param uShwType PGM_TYPE_*
227 * @remark ASSUMES certain order of the PGM_TYPE_* values.
228 */
229#define PGM_WITH_PAGING(uGstType, uShwType) \
230 ( (uGstType) >= PGM_TYPE_32BIT \
231 && (uShwType) < PGM_TYPE_NESTED_32BIT)
232
233/** Macro for checking if the guest supports the NX bit.
234 * @param uGstType PGM_TYPE_*
235 * @param uShwType PGM_TYPE_*
236 * @remark ASSUMES certain order of the PGM_TYPE_* values.
237 */
238#define PGM_WITH_NX(uGstType, uShwType) \
239 ( (uGstType) >= PGM_TYPE_PAE \
240 && (uShwType) < PGM_TYPE_NESTED_32BIT)
241
242/** Macro for checking for nested or EPT.
243 * @param uType PGM_TYPE_*
244 */
245#define PGM_TYPE_IS_NESTED(uType) \
246 ( (uType) == PGM_TYPE_NESTED_32BIT \
247 || (uType) == PGM_TYPE_NESTED_PAE \
248 || (uType) == PGM_TYPE_NESTED_AMD64)
249
250/** Macro for checking for nested or EPT.
251 * @param uType PGM_TYPE_*
252 */
253#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
254 ( (uType) == PGM_TYPE_NESTED_32BIT \
255 || (uType) == PGM_TYPE_NESTED_PAE \
256 || (uType) == PGM_TYPE_NESTED_AMD64 \
257 || (uType) == PGM_TYPE_EPT)
258
259
260
261/** @def PGM_HCPHYS_2_PTR
262 * Maps a HC physical page pool address to a virtual address.
263 *
264 * @returns VBox status code.
265 * @param pVM The cross context VM structure.
266 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
267 * @param HCPhys The HC physical address to map to a virtual one.
268 * @param ppv Where to store the virtual address. No need to cast
269 * this.
270 *
271 * @remark Use with care as we don't have so much dynamic mapping space in
272 * ring-0 on 32-bit darwin and in RC.
273 * @remark There is no need to assert on the result.
274 */
275#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
276# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
277 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
278#else
279# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
280 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
281#endif
282
283/** @def PGM_GCPHYS_2_PTR_V2
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVM The cross context VM structure.
288 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark Use with care as we don't have so much dynamic mapping space in
293 * ring-0 on 32-bit darwin and in RC.
294 * @remark There is no need to assert on the result.
295 */
296#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
297# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
298 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
299#else
300# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
301 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
302#endif
303
304/** @def PGM_GCPHYS_2_PTR
305 * Maps a GC physical page address to a virtual address.
306 *
307 * @returns VBox status code.
308 * @param pVM The cross context VM structure.
309 * @param GCPhys The GC physical address to map to a virtual one.
310 * @param ppv Where to store the virtual address. No need to cast this.
311 *
312 * @remark Use with care as we don't have so much dynamic mapping space in
313 * ring-0 on 32-bit darwin and in RC.
314 * @remark There is no need to assert on the result.
315 */
316#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
317
318/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
319 * Maps a GC physical page address to a virtual address.
320 *
321 * @returns VBox status code.
322 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
323 * @param GCPhys The GC physical address to map to a virtual one.
324 * @param ppv Where to store the virtual address. No need to cast this.
325 *
326 * @remark Use with care as we don't have so much dynamic mapping space in
327 * ring-0 on 32-bit darwin and in RC.
328 * @remark There is no need to assert on the result.
329 */
330#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
331
332/** @def PGM_GCPHYS_2_PTR_EX
333 * Maps a unaligned GC physical page address to a virtual address.
334 *
335 * @returns VBox status code.
336 * @param pVM The cross context VM structure.
337 * @param GCPhys The GC physical address to map to a virtual one.
338 * @param ppv Where to store the virtual address. No need to cast this.
339 *
340 * @remark Use with care as we don't have so much dynamic mapping space in
341 * ring-0 on 32-bit darwin and in RC.
342 * @remark There is no need to assert on the result.
343 */
344#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
345# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
346 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
347#else
348# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
349 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
350#endif
351
352/** @def PGM_DYNMAP_UNUSED_HINT
353 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
354 * is no longer used.
355 *
356 * For best effect only apply this to the page that was mapped most recently.
357 *
358 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
359 * @param pvPage The pool page.
360 */
361#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
362# ifdef LOG_ENABLED
363# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
364# else
365# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
366# endif
367#else
368# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
369#endif
370
371/** @def PGM_DYNMAP_UNUSED_HINT_VM
372 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
373 * is no longer used.
374 *
375 * For best effect only apply this to the page that was mapped most recently.
376 *
377 * @param pVM The cross context VM structure.
378 * @param pvPage The pool page.
379 */
380#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
381
382
383/** @def PGM_INVL_PG
384 * Invalidates a page.
385 *
386 * @param pVCpu The cross context virtual CPU structure.
387 * @param GCVirt The virtual address of the page to invalidate.
388 */
389#ifdef IN_RC
390# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
391#elif defined(IN_RING0)
392# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
393#else
394# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
395#endif
396
397/** @def PGM_INVL_PG_ALL_VCPU
398 * Invalidates a page on all VCPUs
399 *
400 * @param pVM The cross context VM structure.
401 * @param GCVirt The virtual address of the page to invalidate.
402 */
403#ifdef IN_RC
404# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
405#elif defined(IN_RING0)
406# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
407#else
408# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
409#endif
410
411/** @def PGM_INVL_BIG_PG
412 * Invalidates a 4MB page directory entry.
413 *
414 * @param pVCpu The cross context virtual CPU structure.
415 * @param GCVirt The virtual address within the page directory to invalidate.
416 */
417#ifdef IN_RC
418# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
419#elif defined(IN_RING0)
420# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
421#else
422# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
423#endif
424
425/** @def PGM_INVL_VCPU_TLBS()
426 * Invalidates the TLBs of the specified VCPU
427 *
428 * @param pVCpu The cross context virtual CPU structure.
429 */
430#ifdef IN_RC
431# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
432#elif defined(IN_RING0)
433# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
434#else
435# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
436#endif
437
438/** @def PGM_INVL_ALL_VCPU_TLBS()
439 * Invalidates the TLBs of all VCPUs
440 *
441 * @param pVM The cross context VM structure.
442 */
443#ifdef IN_RC
444# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
445#elif defined(IN_RING0)
446# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
447#else
448# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
449#endif
450
451
452/** @name Safer Shadow PAE PT/PTE
453 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
454 * present.
455 *
456 * @{
457 */
458#if 1
459/**
460 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
461 * invalid entries for present.
462 * @sa X86PTEPAE.
463 */
464typedef union PGMSHWPTEPAE
465{
466 /** Unsigned integer view */
467 X86PGPAEUINT uCareful;
468 /* Not other views. */
469} PGMSHWPTEPAE;
470
471# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
472# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
473# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
474# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
475# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
476# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
477# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
478# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
479# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
480# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
481# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
482# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
483# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
484# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
485# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
486# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
487
488/**
489 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
490 * invalid entries for present.
491 * @sa X86PTPAE.
492 */
493typedef struct PGMSHWPTPAE
494{
495 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
496} PGMSHWPTPAE;
497
498#else
499typedef X86PTEPAE PGMSHWPTEPAE;
500typedef X86PTPAE PGMSHWPTPAE;
501# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
502# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
503# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
504# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
505# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
506# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
507# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
508# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
509# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
510# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
511# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
512# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
513# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
514# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
515# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
516# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
517
518#endif
519
520/** Pointer to a shadow PAE PTE. */
521typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
522/** Pointer to a const shadow PAE PTE. */
523typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
524
525/** Pointer to a shadow PAE page table. */
526typedef PGMSHWPTPAE *PPGMSHWPTPAE;
527/** Pointer to a const shadow PAE page table. */
528typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
529/** @} */
530
531
532/** Size of the GCPtrConflict array in PGMMAPPING.
533 * @remarks Must be a power of two. */
534#define PGMMAPPING_CONFLICT_MAX 8
535
536/**
537 * Structure for tracking GC Mappings.
538 *
539 * This structure is used by linked list in both GC and HC.
540 */
541typedef struct PGMMAPPING
542{
543 /** Pointer to next entry. */
544 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
545 /** Pointer to next entry. */
546 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
547 /** Pointer to next entry. */
548 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
549 /** Indicate whether this entry is finalized. */
550 bool fFinalized;
551 /** Start Virtual address. */
552 RTGCPTR GCPtr;
553 /** Last Virtual address (inclusive). */
554 RTGCPTR GCPtrLast;
555 /** Range size (bytes). */
556 RTGCPTR cb;
557 /** Pointer to relocation callback function. */
558 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
559 /** User argument to the callback. */
560 R3PTRTYPE(void *) pvUser;
561 /** Mapping description / name. For easing debugging. */
562 R3PTRTYPE(const char *) pszDesc;
563 /** Last 8 addresses that caused conflicts. */
564 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
565 /** Number of conflicts for this hypervisor mapping. */
566 uint32_t cConflicts;
567 /** Number of page tables. */
568 uint32_t cPTs;
569
570 /** Array of page table mapping data. Each entry
571 * describes one page table. The array can be longer
572 * than the declared length.
573 */
574 struct
575 {
576 /** The HC physical address of the page table. */
577 RTHCPHYS HCPhysPT;
578 /** The HC physical address of the first PAE page table. */
579 RTHCPHYS HCPhysPaePT0;
580 /** The HC physical address of the second PAE page table. */
581 RTHCPHYS HCPhysPaePT1;
582 /** The HC virtual address of the 32-bit page table. */
583 R3PTRTYPE(PX86PT) pPTR3;
584 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
585 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
586 /** The RC virtual address of the 32-bit page table. */
587 RCPTRTYPE(PX86PT) pPTRC;
588 /** The RC virtual address of the two PAE page table. */
589 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
590 /** The R0 virtual address of the 32-bit page table. */
591 R0PTRTYPE(PX86PT) pPTR0;
592 /** The R0 virtual address of the two PAE page table. */
593 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
594 } aPTs[1];
595} PGMMAPPING;
596/** Pointer to structure for tracking GC Mappings. */
597typedef struct PGMMAPPING *PPGMMAPPING;
598
599
600/**
601 * Physical page access handler type registration.
602 */
603typedef struct PGMPHYSHANDLERTYPEINT
604{
605 /** Number of references. */
606 uint32_t volatile cRefs;
607 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
608 uint32_t u32Magic;
609 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
610 RTLISTOFF32NODE ListNode;
611 /** The kind of accesses we're handling. */
612 PGMPHYSHANDLERKIND enmKind;
613 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
614 uint32_t uState;
615 /** Pointer to RC callback function. */
616 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
617 /** Pointer to RC callback function for \#PFs. */
618 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
619 /** Pointer to R3 callback function. */
620 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
621 /** Pointer to R0 callback function. */
622 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
623 /** Pointer to R0 callback function for \#PFs. */
624 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
625 /** Description / Name. For easing debugging. */
626 R3PTRTYPE(const char *) pszDesc;
627} PGMPHYSHANDLERTYPEINT;
628/** Pointer to a physical access handler type registration. */
629typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
630/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
631#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
632/** Magic value for the physical handler callbacks. */
633#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
634
635/**
636 * Converts a handle to a pointer.
637 * @returns PPGMPHYSHANDLERTYPEINT
638 * @param a_pVM The cross context VM structure.
639 * @param a_hType Physical access handler type handle.
640 */
641#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
642
643
644/**
645 * Physical page access handler structure.
646 *
647 * This is used to keep track of physical address ranges
648 * which are being monitored in some kind of way.
649 */
650typedef struct PGMPHYSHANDLER
651{
652 AVLROGCPHYSNODECORE Core;
653 /** Number of pages to update. */
654 uint32_t cPages;
655 /** Set if we have pages that have been aliased. */
656 uint32_t cAliasedPages;
657 /** Set if we have pages that have temporarily been disabled. */
658 uint32_t cTmpOffPages;
659 /** Registered handler type handle (heap offset). */
660 PGMPHYSHANDLERTYPE hType;
661 /** User argument for RC handlers. */
662 RCPTRTYPE(void *) pvUserRC;
663#if HC_ARCH_BITS == 64
664 RTRCPTR Padding0; /**< Explicit alignment padding. */
665#endif
666 /** User argument for R3 handlers. */
667 R3PTRTYPE(void *) pvUserR3;
668 /** User argument for R0 handlers. */
669 R0PTRTYPE(void *) pvUserR0;
670 /** Description / Name. For easing debugging. */
671 R3PTRTYPE(const char *) pszDesc;
672#ifdef VBOX_WITH_STATISTICS
673 /** Profiling of this handler. */
674 STAMPROFILE Stat;
675#endif
676} PGMPHYSHANDLER;
677/** Pointer to a physical page access handler structure. */
678typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
679
680/**
681 * Gets the type record for a physical handler (no reference added).
682 * @returns PPGMPHYSHANDLERTYPEINT
683 * @param a_pVM The cross context VM structure.
684 * @param a_pPhysHandler Pointer to the physical handler structure
685 * (PGMPHYSHANDLER).
686 */
687#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
688
689
690#ifdef VBOX_WITH_RAW_MODE
691
692/**
693 * Cache node for the physical addresses covered by a virtual handler.
694 */
695typedef struct PGMPHYS2VIRTHANDLER
696{
697 /** Core node for the tree based on physical ranges. */
698 AVLROGCPHYSNODECORE Core;
699 /** Offset from this struct to the PGMVIRTHANDLER structure. */
700 int32_t offVirtHandler;
701 /** Offset of the next alias relative to this one.
702 * Bit 0 is used for indicating whether we're in the tree.
703 * Bit 1 is used for indicating that we're the head node.
704 */
705 int32_t offNextAlias;
706} PGMPHYS2VIRTHANDLER;
707/** Pointer to a phys to virtual handler structure. */
708typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
709
710/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
711 * node is in the tree. */
712# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
713/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
714 * node is in the head of an alias chain.
715 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
716# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
717/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
718# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
719
720
721/**
722 * Virtual page access handler type registration.
723 */
724typedef struct PGMVIRTANDLERTYPEINT
725{
726 /** Number of references. */
727 uint32_t volatile cRefs;
728 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
729 uint32_t u32Magic;
730 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
731 RTLISTOFF32NODE ListNode;
732 /** The kind of accesses we're handling. */
733 PGMVIRTHANDLERKIND enmKind;
734 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
735 uint32_t uState;
736 /** Whether the pvUserRC argument should be automatically relocated or not. */
737 bool fRelocUserRC;
738 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
739 /** Pointer to RC callback function. */
740 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
741 /** Pointer to RC callback function for \#PFs. */
742 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
743 /** Pointer to the R3 callback function for invalidation. */
744 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
745 /** Pointer to R3 callback function. */
746 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
747 /** Description / Name. For easing debugging. */
748 R3PTRTYPE(const char *) pszDesc;
749} PGMVIRTHANDLERTYPEINT;
750/** Pointer to a virtual access handler type registration. */
751typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
752/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
753# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
754/** Magic value for the virtual handler callbacks. */
755# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
756
757/**
758 * Converts a handle to a pointer.
759 * @returns PPGMVIRTHANDLERTYPEINT
760 * @param a_pVM The cross context VM structure.
761 * @param a_hType Vitual access handler type handle.
762 */
763# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
764
765
766/**
767 * Virtual page access handler structure.
768 *
769 * This is used to keep track of virtual address ranges
770 * which are being monitored in some kind of way.
771 */
772typedef struct PGMVIRTHANDLER
773{
774 /** Core node for the tree based on virtual ranges. */
775 AVLROGCPTRNODECORE Core;
776 /** Size of the range (in bytes). */
777 uint32_t cb;
778 /** Number of cache pages. */
779 uint32_t cPages;
780 /** Registered handler type handle (heap offset). */
781 PGMVIRTHANDLERTYPE hType;
782 /** User argument for RC handlers. */
783 RCPTRTYPE(void *) pvUserRC;
784 /** User argument for R3 handlers. */
785 R3PTRTYPE(void *) pvUserR3;
786 /** Description / Name. For easing debugging. */
787 R3PTRTYPE(const char *) pszDesc;
788# ifdef VBOX_WITH_STATISTICS
789 /** Profiling of this handler. */
790 STAMPROFILE Stat;
791# endif
792 /** Array of cached physical addresses for the monitored ranged. */
793 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
794} PGMVIRTHANDLER;
795/** Pointer to a virtual page access handler structure. */
796typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
797
798/**
799 * Gets the type record for a virtual handler (no reference added).
800 * @returns PPGMVIRTHANDLERTYPEINT
801 * @param a_pVM The cross context VM structure.
802 * @param a_pVirtHandler Pointer to the virtual handler structure
803 * (PGMVIRTHANDLER).
804 */
805# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
806
807#endif /* VBOX_WITH_RAW_MODE */
808
809
810/**
811 * A Physical Guest Page tracking structure.
812 *
813 * The format of this structure is complicated because we have to fit a lot
814 * of information into as few bits as possible. The format is also subject
815 * to change (there is one coming up soon). Which means that for we'll be
816 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
817 * accesses to the structure.
818 */
819typedef union PGMPAGE
820{
821 /** Structured view. */
822 struct
823 {
824 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
825 uint64_t u2HandlerPhysStateY : 2;
826 /** 3:2 - Paging structure needed to map the page
827 * (PGM_PAGE_PDE_TYPE_*). */
828 uint64_t u2PDETypeY : 2;
829 /** 4 - Unused (was used by FTE for dirty tracking). */
830 uint64_t fUnused1 : 1;
831 /** 5 - Flag indicating that a write monitored page was written to
832 * when set. */
833 uint64_t fWrittenToY : 1;
834 /** 7:6 - Unused. */
835 uint64_t u2Unused0 : 2;
836 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
837 uint64_t u2HandlerVirtStateY : 2;
838 /** 11:10 - NEM state bits. */
839 uint64_t u2NemStateY : 2;
840 /** 12:48 - The host physical frame number (shift left to get the
841 * address). */
842 uint64_t HCPhysFN : 36;
843 /** 50:48 - The page state. */
844 uint64_t uStateY : 3;
845 /** 51:53 - The page type (PGMPAGETYPE). */
846 uint64_t uTypeY : 3;
847 /** 63:54 - PTE index for usage tracking (page pool). */
848 uint64_t u10PteIdx : 10;
849
850 /** The GMM page ID.
851 * @remarks In the current implementation, MMIO2 and pages aliased to
852 * MMIO2 pages will be exploiting this field to calculate the
853 * ring-3 mapping address corresponding to the page.
854 * Later we may consider including MMIO2 management into GMM. */
855 uint32_t idPage;
856 /** Usage tracking (page pool). */
857 uint16_t u16TrackingY;
858 /** The number of read locks on this page. */
859 uint8_t cReadLocksY;
860 /** The number of write locks on this page. */
861 uint8_t cWriteLocksY;
862 } s;
863
864 /** 64-bit integer view. */
865 uint64_t au64[2];
866 /** 16-bit view. */
867 uint32_t au32[4];
868 /** 16-bit view. */
869 uint16_t au16[8];
870 /** 8-bit view. */
871 uint8_t au8[16];
872} PGMPAGE;
873AssertCompileSize(PGMPAGE, 16);
874/** Pointer to a physical guest page. */
875typedef PGMPAGE *PPGMPAGE;
876/** Pointer to a const physical guest page. */
877typedef const PGMPAGE *PCPGMPAGE;
878/** Pointer to a physical guest page pointer. */
879typedef PPGMPAGE *PPPGMPAGE;
880
881
882/**
883 * Clears the page structure.
884 * @param a_pPage Pointer to the physical guest page tracking structure.
885 */
886#define PGM_PAGE_CLEAR(a_pPage) \
887 do { \
888 (a_pPage)->au64[0] = 0; \
889 (a_pPage)->au64[1] = 0; \
890 } while (0)
891
892/**
893 * Initializes the page structure.
894 * @param a_pPage Pointer to the physical guest page tracking structure.
895 * @param a_HCPhys The host physical address of the page.
896 * @param a_idPage The (GMM) page ID of the page.
897 * @param a_uType The page type (PGMPAGETYPE).
898 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
899 */
900#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
901 do { \
902 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
903 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
904 (a_pPage)->au64[0] = SetHCPhysTmp; \
905 (a_pPage)->au64[1] = 0; \
906 (a_pPage)->s.idPage = (a_idPage); \
907 (a_pPage)->s.uStateY = (a_uState); \
908 (a_pPage)->s.uTypeY = (a_uType); \
909 } while (0)
910
911/**
912 * Initializes the page structure of a ZERO page.
913 * @param a_pPage Pointer to the physical guest page tracking structure.
914 * @param a_pVM The VM handle (for getting the zero page address).
915 * @param a_uType The page type (PGMPAGETYPE).
916 */
917#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
918 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
919
920
921/** @name The Page state, PGMPAGE::uStateY.
922 * @{ */
923/** The zero page.
924 * This is a per-VM page that's never ever mapped writable. */
925#define PGM_PAGE_STATE_ZERO 0U
926/** A allocated page.
927 * This is a per-VM page allocated from the page pool (or wherever
928 * we get MMIO2 pages from if the type is MMIO2).
929 */
930#define PGM_PAGE_STATE_ALLOCATED 1U
931/** A allocated page that's being monitored for writes.
932 * The shadow page table mappings are read-only. When a write occurs, the
933 * fWrittenTo member is set, the page remapped as read-write and the state
934 * moved back to allocated. */
935#define PGM_PAGE_STATE_WRITE_MONITORED 2U
936/** The page is shared, aka. copy-on-write.
937 * This is a page that's shared with other VMs. */
938#define PGM_PAGE_STATE_SHARED 3U
939/** The page is ballooned, so no longer available for this VM. */
940#define PGM_PAGE_STATE_BALLOONED 4U
941/** @} */
942
943
944/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
945#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
946# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
947#else
948# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
949#endif
950
951/**
952 * Gets the page state.
953 * @returns page state (PGM_PAGE_STATE_*).
954 * @param a_pPage Pointer to the physical guest page tracking structure.
955 *
956 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
957 * builds.
958 */
959#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
960#if defined(__GNUC__) && defined(VBOX_STRICT)
961# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
962#else
963# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
964#endif
965
966/**
967 * Sets the page state.
968 * @param a_pVM The VM handle, only used for lock ownership assertions.
969 * @param a_pPage Pointer to the physical guest page tracking structure.
970 * @param a_uState The new page state.
971 */
972#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
973 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
974
975
976/**
977 * Gets the host physical address of the guest page.
978 * @returns host physical address (RTHCPHYS).
979 * @param a_pPage Pointer to the physical guest page tracking structure.
980 *
981 * @remarks In strict builds on gcc platforms, this macro will make some ugly
982 * assumption about a valid pVM variable/parameter being in the
983 * current context. It will use this pVM variable to assert that the
984 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
985 * pVM is not around.
986 */
987#if 0
988# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
989# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
990#else
991# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
992# if defined(__GNUC__) && defined(VBOX_STRICT)
993# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
994# else
995# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
996# endif
997#endif
998
999/**
1000 * Sets the host physical address of the guest page.
1001 *
1002 * @param a_pVM The VM handle, only used for lock ownership assertions.
1003 * @param a_pPage Pointer to the physical guest page tracking structure.
1004 * @param a_HCPhys The new host physical address.
1005 */
1006#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
1007 do { \
1008 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
1009 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
1010 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
1011 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1012 } while (0)
1013
1014/**
1015 * Get the Page ID.
1016 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1020
1021/**
1022 * Sets the Page ID.
1023 * @param a_pVM The VM handle, only used for lock ownership assertions.
1024 * @param a_pPage Pointer to the physical guest page tracking structure.
1025 * @param a_idPage The new page ID.
1026 */
1027#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1028 do { \
1029 (a_pPage)->s.idPage = (a_idPage); \
1030 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1031 } while (0)
1032
1033/**
1034 * Get the Chunk ID.
1035 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1036 * @param a_pPage Pointer to the physical guest page tracking structure.
1037 */
1038#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1039
1040/**
1041 * Get the index of the page within the allocation chunk.
1042 * @returns The page index.
1043 * @param a_pPage Pointer to the physical guest page tracking structure.
1044 */
1045#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1046
1047/**
1048 * Gets the page type.
1049 * @returns The page type.
1050 * @param a_pPage Pointer to the physical guest page tracking structure.
1051 *
1052 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1053 * builds.
1054 */
1055#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1056#if defined(__GNUC__) && defined(VBOX_STRICT)
1057# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1058#else
1059# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1060#endif
1061
1062/**
1063 * Sets the page type.
1064 *
1065 * @param a_pVM The VM handle, only used for lock ownership assertions.
1066 * @param a_pPage Pointer to the physical guest page tracking structure.
1067 * @param a_enmType The new page type (PGMPAGETYPE).
1068 */
1069#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1070 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1071
1072/**
1073 * Gets the page table index
1074 * @returns The page table index.
1075 * @param a_pPage Pointer to the physical guest page tracking structure.
1076 */
1077#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1078
1079/**
1080 * Sets the page table index.
1081 * @param a_pVM The VM handle, only used for lock ownership assertions.
1082 * @param a_pPage Pointer to the physical guest page tracking structure.
1083 * @param a_iPte New page table index.
1084 */
1085#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1086 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1087
1088/**
1089 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1090 * @returns true/false.
1091 * @param a_pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1094
1095/**
1096 * Checks if the page is marked for MMIO, including both aliases.
1097 * @returns true/false.
1098 * @param a_pPage Pointer to the physical guest page tracking structure.
1099 */
1100#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1101 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1102 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1103 )
1104
1105/**
1106 * Checks if the page is marked for MMIO, including special aliases.
1107 * @returns true/false.
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 */
1110#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1111 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1112
1113/**
1114 * Checks if the page is a special aliased MMIO page.
1115 * @returns true/false.
1116 * @param a_pPage Pointer to the physical guest page tracking structure.
1117 */
1118#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1119
1120/**
1121 * Checks if the page is backed by the ZERO page.
1122 * @returns true/false.
1123 * @param a_pPage Pointer to the physical guest page tracking structure.
1124 */
1125#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1126
1127/**
1128 * Checks if the page is backed by a SHARED page.
1129 * @returns true/false.
1130 * @param a_pPage Pointer to the physical guest page tracking structure.
1131 */
1132#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1133
1134/**
1135 * Checks if the page is ballooned.
1136 * @returns true/false.
1137 * @param a_pPage Pointer to the physical guest page tracking structure.
1138 */
1139#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1140
1141/**
1142 * Checks if the page is allocated.
1143 * @returns true/false.
1144 * @param a_pPage Pointer to the physical guest page tracking structure.
1145 */
1146#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1147
1148/**
1149 * Marks the page as written to (for GMM change monitoring).
1150 * @param a_pVM The VM handle, only used for lock ownership assertions.
1151 * @param a_pPage Pointer to the physical guest page tracking structure.
1152 */
1153#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1154 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1155
1156/**
1157 * Clears the written-to indicator.
1158 * @param a_pVM The VM handle, only used for lock ownership assertions.
1159 * @param a_pPage Pointer to the physical guest page tracking structure.
1160 */
1161#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1162 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1163
1164/**
1165 * Checks if the page was marked as written-to.
1166 * @returns true/false.
1167 * @param a_pPage Pointer to the physical guest page tracking structure.
1168 */
1169#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1170
1171
1172/** @name PT usage values (PGMPAGE::u2PDEType).
1173 *
1174 * @{ */
1175/** Either as a PT or PDE. */
1176#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1177/** Must use a page table to map the range. */
1178#define PGM_PAGE_PDE_TYPE_PT 1
1179/** Can use a page directory entry to map the continuous range. */
1180#define PGM_PAGE_PDE_TYPE_PDE 2
1181/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1182#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1183/** @} */
1184
1185/**
1186 * Set the PDE type of the page
1187 * @param a_pVM The VM handle, only used for lock ownership assertions.
1188 * @param a_pPage Pointer to the physical guest page tracking structure.
1189 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1190 */
1191#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1192 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1193
1194/**
1195 * Checks if the page was marked being part of a large page
1196 * @returns true/false.
1197 * @param a_pPage Pointer to the physical guest page tracking structure.
1198 */
1199#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1200
1201/** Enabled optimized access handler tests.
1202 * These optimizations makes ASSUMPTIONS about the state values and the s1
1203 * layout. When enabled, the compiler should normally generate more compact
1204 * code.
1205 */
1206#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1207
1208/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1209 *
1210 * @remarks The values are assigned in order of priority, so we can calculate
1211 * the correct state for a page with different handlers installed.
1212 * @{ */
1213/** No handler installed. */
1214#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1215/** Monitoring is temporarily disabled. */
1216#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1217/** Write access is monitored. */
1218#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1219/** All access is monitored. */
1220#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1221/** @} */
1222
1223/**
1224 * Gets the physical access handler state of a page.
1225 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1226 * @param a_pPage Pointer to the physical guest page tracking structure.
1227 */
1228#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1229
1230/**
1231 * Sets the physical access handler state of a page.
1232 * @param a_pPage Pointer to the physical guest page tracking structure.
1233 * @param a_uState The new state value.
1234 */
1235#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1236 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1237
1238/**
1239 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1240 * @returns true/false
1241 * @param a_pPage Pointer to the physical guest page tracking structure.
1242 */
1243#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1244 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1245
1246/**
1247 * Checks if the page has any active physical access handlers.
1248 * @returns true/false
1249 * @param a_pPage Pointer to the physical guest page tracking structure.
1250 */
1251#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1252 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1253
1254
1255/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1256 *
1257 * @remarks The values are assigned in order of priority, so we can calculate
1258 * the correct state for a page with different handlers installed.
1259 * @{ */
1260/** No handler installed. */
1261#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1262/* 1 is reserved so the lineup is identical with the physical ones. */
1263/** Write access is monitored. */
1264#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1265/** All access is monitored. */
1266#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1267/** @} */
1268
1269/**
1270 * Gets the virtual access handler state of a page.
1271 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1272 * @param a_pPage Pointer to the physical guest page tracking structure.
1273 */
1274#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1275
1276/**
1277 * Sets the virtual access handler state of a page.
1278 * @param a_pPage Pointer to the physical guest page tracking structure.
1279 * @param a_uState The new state value.
1280 */
1281#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1282 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1283
1284/**
1285 * Checks if the page has any virtual access handlers.
1286 * @returns true/false
1287 * @param a_pPage Pointer to the physical guest page tracking structure.
1288 */
1289#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1290 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1291
1292/**
1293 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1294 * virtual handlers.
1295 * @returns true/false
1296 * @param a_pPage Pointer to the physical guest page tracking structure.
1297 */
1298#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1299 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1300
1301
1302/**
1303 * Checks if the page has any access handlers, including temporarily disabled ones.
1304 * @returns true/false
1305 * @param a_pPage Pointer to the physical guest page tracking structure.
1306 */
1307#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1308# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1309 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1310#else
1311# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1312 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1313 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1314#endif
1315
1316/**
1317 * Checks if the page has any active access handlers.
1318 * @returns true/false
1319 * @param a_pPage Pointer to the physical guest page tracking structure.
1320 */
1321#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1322# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1323 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1324#else
1325# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1326 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1327 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1328#endif
1329
1330/**
1331 * Checks if the page has any active access handlers catching all accesses.
1332 * @returns true/false
1333 * @param a_pPage Pointer to the physical guest page tracking structure.
1334 */
1335#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1336# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1337 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1338 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1339#else
1340# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1341 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1342 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1343#endif
1344
1345
1346/** @def PGM_PAGE_GET_TRACKING
1347 * Gets the packed shadow page pool tracking data associated with a guest page.
1348 * @returns uint16_t containing the data.
1349 * @param a_pPage Pointer to the physical guest page tracking structure.
1350 */
1351#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1352#if defined(__GNUC__) && defined(VBOX_STRICT)
1353# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1354#else
1355# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1356#endif
1357
1358/** @def PGM_PAGE_SET_TRACKING
1359 * Sets the packed shadow page pool tracking data associated with a guest page.
1360 * @param a_pVM The VM handle, only used for lock ownership assertions.
1361 * @param a_pPage Pointer to the physical guest page tracking structure.
1362 * @param a_u16TrackingData The tracking data to store.
1363 */
1364#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1365 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1366
1367/** @def PGM_PAGE_GET_TD_CREFS
1368 * Gets the @a cRefs tracking data member.
1369 * @returns cRefs.
1370 * @param a_pPage Pointer to the physical guest page tracking structure.
1371 */
1372#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1373 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1374#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1375 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1376
1377/** @def PGM_PAGE_GET_TD_IDX
1378 * Gets the @a idx tracking data member.
1379 * @returns idx.
1380 * @param a_pPage Pointer to the physical guest page tracking structure.
1381 */
1382#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1383 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1384#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1385 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1386
1387
1388/** Max number of locks on a page. */
1389#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1390
1391/** Get the read lock count.
1392 * @returns count.
1393 * @param a_pPage Pointer to the physical guest page tracking structure.
1394 */
1395#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1396
1397/** Get the write lock count.
1398 * @returns count.
1399 * @param a_pPage Pointer to the physical guest page tracking structure.
1400 */
1401#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1402
1403/** Decrement the read lock counter.
1404 * @param a_pPage Pointer to the physical guest page tracking structure.
1405 */
1406#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1407
1408/** Decrement the write lock counter.
1409 * @param a_pPage Pointer to the physical guest page tracking structure.
1410 */
1411#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1412
1413/** Increment the read lock counter.
1414 * @param a_pPage Pointer to the physical guest page tracking structure.
1415 */
1416#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1417
1418/** Increment the write lock counter.
1419 * @param a_pPage Pointer to the physical guest page tracking structure.
1420 */
1421#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1422
1423
1424/** Gets the NEM state.
1425 * @returns NEM state value (two bits).
1426 * @param a_pPage Pointer to the physical guest page tracking structure.
1427 */
1428#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1429
1430/** Sets the NEM state.
1431 * @param a_pPage Pointer to the physical guest page tracking structure.
1432 * @param a_u2State The NEM state value (specific to NEM impl.).
1433 */
1434#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1435 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1436
1437
1438#if 0
1439/** Enables sanity checking of write monitoring using CRC-32. */
1440# define PGMLIVESAVERAMPAGE_WITH_CRC32
1441#endif
1442
1443/**
1444 * Per page live save tracking data.
1445 */
1446typedef struct PGMLIVESAVERAMPAGE
1447{
1448 /** Number of times it has been dirtied. */
1449 uint32_t cDirtied : 24;
1450 /** Whether it is currently dirty. */
1451 uint32_t fDirty : 1;
1452 /** Ignore the page.
1453 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1454 * deal with these after pausing the VM and DevPCI have said it bit about
1455 * remappings. */
1456 uint32_t fIgnore : 1;
1457 /** Was a ZERO page last time around. */
1458 uint32_t fZero : 1;
1459 /** Was a SHARED page last time around. */
1460 uint32_t fShared : 1;
1461 /** Whether the page is/was write monitored in a previous pass. */
1462 uint32_t fWriteMonitored : 1;
1463 /** Whether the page is/was write monitored earlier in this pass. */
1464 uint32_t fWriteMonitoredJustNow : 1;
1465 /** Bits reserved for future use. */
1466 uint32_t u2Reserved : 2;
1467#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1468 /** CRC-32 for the page. This is for internal consistency checks. */
1469 uint32_t u32Crc;
1470#endif
1471} PGMLIVESAVERAMPAGE;
1472#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1473AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1474#else
1475AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1476#endif
1477/** Pointer to the per page live save tracking data. */
1478typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1479
1480/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1481#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1482
1483
1484/**
1485 * RAM range for GC Phys to HC Phys conversion.
1486 *
1487 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1488 * conversions too, but we'll let MM handle that for now.
1489 *
1490 * This structure is used by linked lists in both GC and HC.
1491 */
1492typedef struct PGMRAMRANGE
1493{
1494 /** Start of the range. Page aligned. */
1495 RTGCPHYS GCPhys;
1496 /** Size of the range. (Page aligned of course). */
1497 RTGCPHYS cb;
1498 /** Pointer to the next RAM range - for R3. */
1499 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1500 /** Pointer to the next RAM range - for R0. */
1501 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1502 /** Pointer to the next RAM range - for RC. */
1503 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1504 /** PGM_RAM_RANGE_FLAGS_* flags. */
1505 uint32_t fFlags;
1506 /** Last address in the range (inclusive). Page aligned (-1). */
1507 RTGCPHYS GCPhysLast;
1508 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1509 R3PTRTYPE(void *) pvR3;
1510 /** Live save per page tracking data. */
1511 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1512 /** The range description. */
1513 R3PTRTYPE(const char *) pszDesc;
1514 /** Pointer to self - R0 pointer. */
1515 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1516 /** Pointer to self - RC pointer. */
1517 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1518
1519 /** Alignment padding. */
1520 RTRCPTR Alignment0;
1521 /** Pointer to the left search three node - ring-3 context. */
1522 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1523 /** Pointer to the right search three node - ring-3 context. */
1524 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1525 /** Pointer to the left search three node - ring-0 context. */
1526 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1527 /** Pointer to the right search three node - ring-0 context. */
1528 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1529 /** Pointer to the left search three node - raw-mode context. */
1530 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1531 /** Pointer to the right search three node - raw-mode context. */
1532 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1533
1534 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1535#if HC_ARCH_BITS == 32
1536 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1537#endif
1538 /** Array of physical guest page tracking structures. */
1539 PGMPAGE aPages[1];
1540} PGMRAMRANGE;
1541/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1542typedef PGMRAMRANGE *PPGMRAMRANGE;
1543
1544/** @name PGMRAMRANGE::fFlags
1545 * @{ */
1546/** The RAM range is floating around as an independent guest mapping. */
1547#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1548/** Ad hoc RAM range for an ROM mapping. */
1549#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1550/** Ad hoc RAM range for an MMIO mapping. */
1551#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1552/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1553#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1554/** @} */
1555
1556/** Tests if a RAM range is an ad hoc one or not.
1557 * @returns true/false.
1558 * @param pRam The RAM range.
1559 */
1560#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1561 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1562
1563/** The number of entries in the RAM range TLBs (there is one for each
1564 * context). Must be a power of two. */
1565#define PGM_RAMRANGE_TLB_ENTRIES 8
1566
1567/**
1568 * Calculates the RAM range TLB index for the physical address.
1569 *
1570 * @returns RAM range TLB index.
1571 * @param a_GCPhys The guest physical address.
1572 */
1573#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1574
1575
1576
1577/**
1578 * Per page tracking structure for ROM image.
1579 *
1580 * A ROM image may have a shadow page, in which case we may have two pages
1581 * backing it. This structure contains the PGMPAGE for both while
1582 * PGMRAMRANGE have a copy of the active one. It is important that these
1583 * aren't out of sync in any regard other than page pool tracking data.
1584 */
1585typedef struct PGMROMPAGE
1586{
1587 /** The page structure for the virgin ROM page. */
1588 PGMPAGE Virgin;
1589 /** The page structure for the shadow RAM page. */
1590 PGMPAGE Shadow;
1591 /** The current protection setting. */
1592 PGMROMPROT enmProt;
1593 /** Live save status information. Makes use of unused alignment space. */
1594 struct
1595 {
1596 /** The previous protection value. */
1597 uint8_t u8Prot;
1598 /** Written to flag set by the handler. */
1599 bool fWrittenTo;
1600 /** Whether the shadow page is dirty or not. */
1601 bool fDirty;
1602 /** Whether it was dirtied in the recently. */
1603 bool fDirtiedRecently;
1604 } LiveSave;
1605} PGMROMPAGE;
1606AssertCompileSizeAlignment(PGMROMPAGE, 8);
1607/** Pointer to a ROM page tracking structure. */
1608typedef PGMROMPAGE *PPGMROMPAGE;
1609
1610
1611/**
1612 * A registered ROM image.
1613 *
1614 * This is needed to keep track of ROM image since they generally intrude
1615 * into a PGMRAMRANGE. It also keeps track of additional info like the
1616 * two page sets (read-only virgin and read-write shadow), the current
1617 * state of each page.
1618 *
1619 * Because access handlers cannot easily be executed in a different
1620 * context, the ROM ranges needs to be accessible and in all contexts.
1621 */
1622typedef struct PGMROMRANGE
1623{
1624 /** Pointer to the next range - R3. */
1625 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1626 /** Pointer to the next range - R0. */
1627 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1628 /** Pointer to the next range - RC. */
1629 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1630 /** Pointer alignment */
1631 RTRCPTR RCPtrAlignment;
1632 /** Address of the range. */
1633 RTGCPHYS GCPhys;
1634 /** Address of the last byte in the range. */
1635 RTGCPHYS GCPhysLast;
1636 /** Size of the range. */
1637 RTGCPHYS cb;
1638 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1639 uint32_t fFlags;
1640 /** The saved state range ID. */
1641 uint8_t idSavedState;
1642 /** Alignment padding. */
1643 uint8_t au8Alignment[3];
1644 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1645 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1646 /** The size bits pvOriginal points to. */
1647 uint32_t cbOriginal;
1648 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1649 * This is used for strictness checks. */
1650 R3PTRTYPE(const void *) pvOriginal;
1651 /** The ROM description. */
1652 R3PTRTYPE(const char *) pszDesc;
1653 /** The per page tracking structures. */
1654 PGMROMPAGE aPages[1];
1655} PGMROMRANGE;
1656/** Pointer to a ROM range. */
1657typedef PGMROMRANGE *PPGMROMRANGE;
1658
1659
1660/**
1661 * Live save per page data for an MMIO2 page.
1662 *
1663 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1664 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1665 * CRC-32 for detecting changes as well as special handling of zero pages. This
1666 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1667 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1668 * because of speed (2.5x and 6x slower).)
1669 *
1670 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1671 * save but normally is disabled. Since we can write monitor guest
1672 * accesses on our own, we only need this for host accesses. Shouldn't be
1673 * too difficult for DevVGA, VMMDev might be doable, the planned
1674 * networking fun will be fun since it involves ring-0.
1675 */
1676typedef struct PGMLIVESAVEMMIO2PAGE
1677{
1678 /** Set if the page is considered dirty. */
1679 bool fDirty;
1680 /** The number of scans this page has remained unchanged for.
1681 * Only updated for dirty pages. */
1682 uint8_t cUnchangedScans;
1683 /** Whether this page was zero at the last scan. */
1684 bool fZero;
1685 /** Alignment padding. */
1686 bool fReserved;
1687 /** CRC-32 for the first half of the page.
1688 * This is used together with u32CrcH2 to quickly detect changes in the page
1689 * during the non-final passes. */
1690 uint32_t u32CrcH1;
1691 /** CRC-32 for the second half of the page. */
1692 uint32_t u32CrcH2;
1693 /** SHA-1 for the saved page.
1694 * This is used in the final pass to skip pages without changes. */
1695 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1696} PGMLIVESAVEMMIO2PAGE;
1697/** Pointer to a live save status data for an MMIO2 page. */
1698typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1699
1700/**
1701 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1702 *
1703 * There are a few reason why we need to keep track of these registrations. One
1704 * of them is the deregistration & cleanup stuff, while another is that the
1705 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1706 * range list.
1707 *
1708 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1709 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1710 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1711 * overlap we will free all the existing RAM pages and put in the ram range
1712 * pages instead.
1713 */
1714typedef struct PGMREGMMIORANGE
1715{
1716 /** The owner of the range. (a device) */
1717 PPDMDEVINSR3 pDevInsR3;
1718 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1719 RTR3PTR pvR3;
1720 /** Pointer to the next range - R3. */
1721 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1722 /** Flags (PGMREGMMIORANGE_F_XXX). */
1723 uint16_t fFlags;
1724 /** The sub device number (internal PCI config (CFGM) number). */
1725 uint8_t iSubDev;
1726 /** The PCI region number. */
1727 uint8_t iRegion;
1728 /** The saved state range ID. */
1729 uint8_t idSavedState;
1730 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1731 uint8_t idMmio2;
1732 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1733 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1734 /** The real size.
1735 * This may be larger than indicated by RamRange.cb if the range has been
1736 * reduced during saved state loading. */
1737 RTGCPHYS cbReal;
1738 /** Pointer to the physical handler for MMIO. */
1739 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1740 /** Live save per page tracking data for MMIO2. */
1741 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1742 /** The associated RAM range. */
1743 PGMRAMRANGE RamRange;
1744} PGMREGMMIORANGE;
1745AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1746/** Pointer to a MMIO2 or pre-registered MMIO range. */
1747typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1748
1749/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1750 * @{ */
1751/** Set if it's an MMIO2 range. */
1752#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1753/** Set if this is the first chunk in the MMIO2 range. */
1754#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1755/** Set if this is the last chunk in the MMIO2 range. */
1756#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1757/** Set if the whole range is mapped. */
1758#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1759/** Set if it's overlapping, clear if not. */
1760#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1761/** @} */
1762
1763
1764/** @name Internal MMIO2 constants.
1765 * @{ */
1766/** The maximum number of MMIO2 ranges. */
1767#define PGM_MMIO2_MAX_RANGES 8
1768/** The maximum number of pages in a MMIO2 range. */
1769#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1770/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1771#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1772/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1773#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1774/** Gets the MMIO2 page index from an MMIO2 page ID. */
1775#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1776/** @} */
1777
1778
1779
1780/**
1781 * PGMPhysRead/Write cache entry
1782 */
1783typedef struct PGMPHYSCACHEENTRY
1784{
1785 /** R3 pointer to physical page. */
1786 R3PTRTYPE(uint8_t *) pbR3;
1787 /** GC Physical address for cache entry */
1788 RTGCPHYS GCPhys;
1789#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1790 RTGCPHYS u32Padding0; /**< alignment padding. */
1791#endif
1792} PGMPHYSCACHEENTRY;
1793
1794/**
1795 * PGMPhysRead/Write cache to reduce REM memory access overhead
1796 */
1797typedef struct PGMPHYSCACHE
1798{
1799 /** Bitmap of valid cache entries */
1800 uint64_t aEntries;
1801 /** Cache entries */
1802 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1803} PGMPHYSCACHE;
1804
1805
1806/** Pointer to an allocation chunk ring-3 mapping. */
1807typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1808/** Pointer to an allocation chunk ring-3 mapping pointer. */
1809typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1810
1811/**
1812 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1813 *
1814 * The primary tree (Core) uses the chunk id as key.
1815 */
1816typedef struct PGMCHUNKR3MAP
1817{
1818 /** The key is the chunk id. */
1819 AVLU32NODECORE Core;
1820 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1821 * selection. */
1822 uint32_t iLastUsed;
1823 /** The current reference count. */
1824 uint32_t volatile cRefs;
1825 /** The current permanent reference count. */
1826 uint32_t volatile cPermRefs;
1827 /** The mapping address. */
1828 void *pv;
1829} PGMCHUNKR3MAP;
1830
1831/**
1832 * Allocation chunk ring-3 mapping TLB entry.
1833 */
1834typedef struct PGMCHUNKR3MAPTLBE
1835{
1836 /** The chunk id. */
1837 uint32_t volatile idChunk;
1838#if HC_ARCH_BITS == 64
1839 uint32_t u32Padding; /**< alignment padding. */
1840#endif
1841 /** The chunk map. */
1842#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1843 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1844#else
1845 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1846#endif
1847} PGMCHUNKR3MAPTLBE;
1848/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1849typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1850
1851/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1852 * @remark Must be a power of two value. */
1853#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1854
1855/**
1856 * Allocation chunk ring-3 mapping TLB.
1857 *
1858 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1859 * At first glance this might look kinda odd since AVL trees are
1860 * supposed to give the most optimal lookup times of all trees
1861 * due to their balancing. However, take a tree with 1023 nodes
1862 * in it, that's 10 levels, meaning that most searches has to go
1863 * down 9 levels before they find what they want. This isn't fast
1864 * compared to a TLB hit. There is the factor of cache misses,
1865 * and of course the problem with trees and branch prediction.
1866 * This is why we use TLBs in front of most of the trees.
1867 *
1868 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1869 * difficult when we switch to the new inlined AVL trees (from kStuff).
1870 */
1871typedef struct PGMCHUNKR3MAPTLB
1872{
1873 /** The TLB entries. */
1874 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1875} PGMCHUNKR3MAPTLB;
1876
1877/**
1878 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1879 * @returns Chunk TLB index.
1880 * @param idChunk The Chunk ID.
1881 */
1882#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1883
1884
1885/**
1886 * Ring-3 guest page mapping TLB entry.
1887 * @remarks used in ring-0 as well at the moment.
1888 */
1889typedef struct PGMPAGER3MAPTLBE
1890{
1891 /** Address of the page. */
1892 RTGCPHYS volatile GCPhys;
1893 /** The guest page. */
1894#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1895 R3PTRTYPE(PPGMPAGE) volatile pPage;
1896#else
1897 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1898#endif
1899 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1900#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1901 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1902#else
1903 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1904#endif
1905 /** The address */
1906#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1907 R3PTRTYPE(void *) volatile pv;
1908#else
1909 R3R0PTRTYPE(void *) volatile pv;
1910#endif
1911#if HC_ARCH_BITS == 32
1912 uint32_t u32Padding; /**< alignment padding. */
1913#endif
1914} PGMPAGER3MAPTLBE;
1915/** Pointer to an entry in the HC physical TLB. */
1916typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1917
1918
1919/** The number of entries in the ring-3 guest page mapping TLB.
1920 * @remarks The value must be a power of two. */
1921#define PGM_PAGER3MAPTLB_ENTRIES 256
1922
1923/**
1924 * Ring-3 guest page mapping TLB.
1925 * @remarks used in ring-0 as well at the moment.
1926 */
1927typedef struct PGMPAGER3MAPTLB
1928{
1929 /** The TLB entries. */
1930 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1931} PGMPAGER3MAPTLB;
1932/** Pointer to the ring-3 guest page mapping TLB. */
1933typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1934
1935/**
1936 * Calculates the index of the TLB entry for the specified guest page.
1937 * @returns Physical TLB index.
1938 * @param GCPhys The guest physical address.
1939 */
1940#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1941
1942
1943/**
1944 * Raw-mode context dynamic mapping cache entry.
1945 *
1946 * Because of raw-mode context being reloctable and all relocations are applied
1947 * in ring-3, this has to be defined here and be RC specific.
1948 *
1949 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1950 */
1951typedef struct PGMRCDYNMAPENTRY
1952{
1953 /** The physical address of the currently mapped page.
1954 * This is duplicate for three reasons: cache locality, cache policy of the PT
1955 * mappings and sanity checks. */
1956 RTHCPHYS HCPhys;
1957 /** Pointer to the page. */
1958 RTRCPTR pvPage;
1959 /** The number of references. */
1960 int32_t volatile cRefs;
1961 /** PTE pointer union. */
1962 struct PGMRCDYNMAPENTRY_PPTE
1963 {
1964 /** PTE pointer, 32-bit legacy version. */
1965 RCPTRTYPE(PX86PTE) pLegacy;
1966 /** PTE pointer, PAE version. */
1967 RCPTRTYPE(PX86PTEPAE) pPae;
1968 } uPte;
1969} PGMRCDYNMAPENTRY;
1970/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1971typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1972
1973
1974/**
1975 * Dynamic mapping cache for the raw-mode context.
1976 *
1977 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1978 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1979 * so that we can perform relocations from PGMR3Relocate. This has the
1980 * consequence that we must have separate ring-0 and raw-mode context versions
1981 * of this struct even if they share the basic elements.
1982 *
1983 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1984 */
1985typedef struct PGMRCDYNMAP
1986{
1987 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1988 uint32_t u32Magic;
1989 /** Array for tracking and managing the pages. */
1990 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1991 /** The cache size given as a number of pages. */
1992 uint32_t cPages;
1993 /** The current load.
1994 * This does not include guard pages. */
1995 uint32_t cLoad;
1996 /** The max load ever.
1997 * This is maintained to get trigger adding of more mapping space. */
1998 uint32_t cMaxLoad;
1999 /** The number of guard pages. */
2000 uint32_t cGuardPages;
2001 /** The number of users (protected by hInitLock). */
2002 uint32_t cUsers;
2003} PGMRCDYNMAP;
2004/** Pointer to the dynamic cache for the raw-mode context. */
2005typedef PGMRCDYNMAP *PPGMRCDYNMAP;
2006
2007
2008/**
2009 * Mapping cache usage set entry.
2010 *
2011 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
2012 * the dynamic ring-0 and (to some extent) raw-mode context mapping
2013 * cache. If it's extended to include ring-3, well, then something
2014 * will have be changed here...
2015 */
2016typedef struct PGMMAPSETENTRY
2017{
2018 /** Pointer to the page. */
2019#ifndef IN_RC
2020 RTR0PTR pvPage;
2021#else
2022 RTRCPTR pvPage;
2023# if HC_ARCH_BITS == 64
2024 uint32_t u32Alignment2;
2025# endif
2026#endif
2027 /** The mapping cache index. */
2028 uint16_t iPage;
2029 /** The number of references.
2030 * The max is UINT16_MAX - 1. */
2031 uint16_t cRefs;
2032 /** The number inlined references.
2033 * The max is UINT16_MAX - 1. */
2034 uint16_t cInlinedRefs;
2035 /** Unreferences. */
2036 uint16_t cUnrefs;
2037
2038#if HC_ARCH_BITS == 32
2039 uint32_t u32Alignment1;
2040#endif
2041 /** The physical address for this entry. */
2042 RTHCPHYS HCPhys;
2043} PGMMAPSETENTRY;
2044AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2045AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2046/** Pointer to a mapping cache usage set entry. */
2047typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2048
2049/**
2050 * Mapping cache usage set.
2051 *
2052 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2053 * done during exits / traps. The set is
2054 */
2055typedef struct PGMMAPSET
2056{
2057 /** The number of occupied entries.
2058 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2059 * dynamic mappings. */
2060 uint32_t cEntries;
2061 /** The start of the current subset.
2062 * This is UINT32_MAX if no subset is currently open. */
2063 uint32_t iSubset;
2064 /** The index of the current CPU, only valid if the set is open. */
2065 int32_t iCpu;
2066 uint32_t alignment;
2067 /** The entries. */
2068 PGMMAPSETENTRY aEntries[64];
2069 /** HCPhys -> iEntry fast lookup table.
2070 * Use PGMMAPSET_HASH for hashing.
2071 * The entries may or may not be valid, check against cEntries. */
2072 uint8_t aiHashTable[128];
2073} PGMMAPSET;
2074AssertCompileSizeAlignment(PGMMAPSET, 8);
2075/** Pointer to the mapping cache set. */
2076typedef PGMMAPSET *PPGMMAPSET;
2077
2078/** PGMMAPSET::cEntries value for a closed set. */
2079#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2080
2081/** Hash function for aiHashTable. */
2082#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2083
2084
2085/** @name Context neutral page mapper TLB.
2086 *
2087 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2088 * code is writting in a kind of context neutral way. Time will show whether
2089 * this actually makes sense or not...
2090 *
2091 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2092 * context ends up using a global mapping cache on some platforms
2093 * (darwin).
2094 *
2095 * @{ */
2096/** @typedef PPGMPAGEMAPTLB
2097 * The page mapper TLB pointer type for the current context. */
2098/** @typedef PPGMPAGEMAPTLB
2099 * The page mapper TLB entry pointer type for the current context. */
2100/** @typedef PPGMPAGEMAPTLB
2101 * The page mapper TLB entry pointer pointer type for the current context. */
2102/** @def PGM_PAGEMAPTLB_ENTRIES
2103 * The number of TLB entries in the page mapper TLB for the current context. */
2104/** @def PGM_PAGEMAPTLB_IDX
2105 * Calculate the TLB index for a guest physical address.
2106 * @returns The TLB index.
2107 * @param GCPhys The guest physical address. */
2108/** @typedef PPGMPAGEMAP
2109 * Pointer to a page mapper unit for current context. */
2110/** @typedef PPPGMPAGEMAP
2111 * Pointer to a page mapper unit pointer for current context. */
2112#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2113// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2114// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2115// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2116# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2117# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2118 typedef void * PPGMPAGEMAP;
2119 typedef void ** PPPGMPAGEMAP;
2120//#elif IN_RING0
2121// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2122// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2123// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2124//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2125//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2126// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2127// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2128#else
2129 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2130 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2131 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2132# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2133# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2134 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2135 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2136#endif
2137/** @} */
2138
2139
2140/** @name PGM Pool Indexes.
2141 * Aka. the unique shadow page identifier.
2142 * @{ */
2143/** NIL page pool IDX. */
2144#define NIL_PGMPOOL_IDX 0
2145/** The first normal index. There used to be 5 fictive pages up front, now
2146 * there is only the NIL page. */
2147#define PGMPOOL_IDX_FIRST 1
2148/** The last valid index. (inclusive, 14 bits) */
2149#define PGMPOOL_IDX_LAST 0x3fff
2150/** @} */
2151
2152/** The NIL index for the parent chain. */
2153#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2154#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2155
2156/**
2157 * Node in the chain linking a shadowed page to it's parent (user).
2158 */
2159#pragma pack(1)
2160typedef struct PGMPOOLUSER
2161{
2162 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2163 uint16_t iNext;
2164 /** The user page index. */
2165 uint16_t iUser;
2166 /** Index into the user table. */
2167 uint32_t iUserTable;
2168} PGMPOOLUSER, *PPGMPOOLUSER;
2169typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2170#pragma pack()
2171
2172
2173/** The NIL index for the phys ext chain. */
2174#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2175/** The NIL pte index for a phys ext chain slot. */
2176#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2177
2178/**
2179 * Node in the chain of physical cross reference extents.
2180 * @todo Calling this an 'extent' is not quite right, find a better name.
2181 * @todo find out the optimal size of the aidx array
2182 */
2183#pragma pack(1)
2184typedef struct PGMPOOLPHYSEXT
2185{
2186 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2187 uint16_t iNext;
2188 /** Alignment. */
2189 uint16_t u16Align;
2190 /** The user page index. */
2191 uint16_t aidx[3];
2192 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2193 uint16_t apte[3];
2194} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2195typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2196#pragma pack()
2197
2198
2199/**
2200 * The kind of page that's being shadowed.
2201 */
2202typedef enum PGMPOOLKIND
2203{
2204 /** The virtual invalid 0 entry. */
2205 PGMPOOLKIND_INVALID = 0,
2206 /** The entry is free (=unused). */
2207 PGMPOOLKIND_FREE,
2208
2209 /** Shw: 32-bit page table; Gst: no paging. */
2210 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2211 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2212 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2213 /** Shw: 32-bit page table; Gst: 4MB page. */
2214 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2215 /** Shw: PAE page table; Gst: no paging. */
2216 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2217 /** Shw: PAE page table; Gst: 32-bit page table. */
2218 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2219 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2220 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2221 /** Shw: PAE page table; Gst: PAE page table. */
2222 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2223 /** Shw: PAE page table; Gst: 2MB page. */
2224 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2225
2226 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2227 PGMPOOLKIND_32BIT_PD,
2228 /** Shw: 32-bit page directory. Gst: no paging. */
2229 PGMPOOLKIND_32BIT_PD_PHYS,
2230 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2231 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2232 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2233 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2234 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2235 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2236 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2237 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2238 /** Shw: PAE page directory; Gst: PAE page directory. */
2239 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2240 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2241 PGMPOOLKIND_PAE_PD_PHYS,
2242
2243 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2244 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2245 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2246 PGMPOOLKIND_PAE_PDPT,
2247 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2248 PGMPOOLKIND_PAE_PDPT_PHYS,
2249
2250 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2251 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2252 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2253 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2254 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2255 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2256 /** Shw: 64-bit page directory table; Gst: no paging. */
2257 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2258
2259 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2260 PGMPOOLKIND_64BIT_PML4,
2261
2262 /** Shw: EPT page directory pointer table; Gst: no paging. */
2263 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2264 /** Shw: EPT page directory table; Gst: no paging. */
2265 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2266 /** Shw: EPT page table; Gst: no paging. */
2267 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2268
2269 /** Shw: Root Nested paging table. */
2270 PGMPOOLKIND_ROOT_NESTED,
2271
2272 /** The last valid entry. */
2273 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2274} PGMPOOLKIND;
2275
2276/**
2277 * The access attributes of the page; only applies to big pages.
2278 */
2279typedef enum
2280{
2281 PGMPOOLACCESS_DONTCARE = 0,
2282 PGMPOOLACCESS_USER_RW,
2283 PGMPOOLACCESS_USER_R,
2284 PGMPOOLACCESS_USER_RW_NX,
2285 PGMPOOLACCESS_USER_R_NX,
2286 PGMPOOLACCESS_SUPERVISOR_RW,
2287 PGMPOOLACCESS_SUPERVISOR_R,
2288 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2289 PGMPOOLACCESS_SUPERVISOR_R_NX
2290} PGMPOOLACCESS;
2291
2292/**
2293 * The tracking data for a page in the pool.
2294 */
2295typedef struct PGMPOOLPAGE
2296{
2297 /** AVL node code with the (HC) physical address of this page. */
2298 AVLOHCPHYSNODECORE Core;
2299 /** Pointer to the R3 mapping of the page. */
2300#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2301 R3PTRTYPE(void *) pvPageR3;
2302#else
2303 R3R0PTRTYPE(void *) pvPageR3;
2304#endif
2305#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2306 uint32_t Alignment0;
2307#endif
2308 /** The guest physical address. */
2309 RTGCPHYS GCPhys;
2310 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2311 uint8_t enmKind;
2312 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2313 uint8_t enmAccess;
2314 /** This supplements enmKind and enmAccess */
2315 bool fA20Enabled : 1;
2316
2317 /** Used to indicate that the page is zeroed. */
2318 bool fZeroed : 1;
2319 /** Used to indicate that a PT has non-global entries. */
2320 bool fSeenNonGlobal : 1;
2321 /** Used to indicate that we're monitoring writes to the guest page. */
2322 bool fMonitored : 1;
2323 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2324 * (All pages are in the age list.) */
2325 bool fCached : 1;
2326 /** This is used by the R3 access handlers when invoked by an async thread.
2327 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2328 bool volatile fReusedFlushPending : 1;
2329 /** Used to mark the page as dirty (write monitoring is temporarily
2330 * off). */
2331 bool fDirty : 1;
2332 bool fPadding1 : 1;
2333 bool fPadding2;
2334
2335 /** The index of this page. */
2336 uint16_t idx;
2337 /** The next entry in the list this page currently resides in.
2338 * It's either in the free list or in the GCPhys hash. */
2339 uint16_t iNext;
2340 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2341 uint16_t iUserHead;
2342 /** The number of present entries. */
2343 uint16_t cPresent;
2344 /** The first entry in the table which is present. */
2345 uint16_t iFirstPresent;
2346 /** The number of modifications to the monitored page. */
2347 uint16_t cModifications;
2348 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2349 uint16_t iModifiedNext;
2350 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2351 uint16_t iModifiedPrev;
2352 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2353 uint16_t iMonitoredNext;
2354 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2355 uint16_t iMonitoredPrev;
2356 /** The next page in the age list. */
2357 uint16_t iAgeNext;
2358 /** The previous page in the age list. */
2359 uint16_t iAgePrev;
2360 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2361 uint8_t idxDirtyEntry;
2362
2363 /** @name Access handler statistics to determine whether the guest is
2364 * (re)initializing a page table.
2365 * @{ */
2366 RTGCPTR GCPtrLastAccessHandlerRip;
2367 RTGCPTR GCPtrLastAccessHandlerFault;
2368 uint64_t cLastAccessHandler;
2369 /** @} */
2370 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2371 uint32_t volatile cLocked;
2372#if GC_ARCH_BITS == 64
2373 uint32_t u32Alignment3;
2374#endif
2375# ifdef VBOX_STRICT
2376 RTGCPTR GCPtrDirtyFault;
2377# endif
2378} PGMPOOLPAGE;
2379/** Pointer to a pool page. */
2380typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2381/** Pointer to a const pool page. */
2382typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2383/** Pointer to a pool page pointer. */
2384typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2385
2386
2387/** The hash table size. */
2388# define PGMPOOL_HASH_SIZE 0x40
2389/** The hash function. */
2390# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2391
2392
2393/**
2394 * The shadow page pool instance data.
2395 *
2396 * It's all one big allocation made at init time, except for the
2397 * pages that is. The user nodes follows immediately after the
2398 * page structures.
2399 */
2400typedef struct PGMPOOL
2401{
2402 /** The VM handle - R3 Ptr. */
2403 PVMR3 pVMR3;
2404 /** The VM handle - R0 Ptr. */
2405 PVMR0 pVMR0;
2406 /** The VM handle - RC Ptr. */
2407 PVMRC pVMRC;
2408 /** The max pool size. This includes the special IDs. */
2409 uint16_t cMaxPages;
2410 /** The current pool size. */
2411 uint16_t cCurPages;
2412 /** The head of the free page list. */
2413 uint16_t iFreeHead;
2414 /* Padding. */
2415 uint16_t u16Padding;
2416 /** Head of the chain of free user nodes. */
2417 uint16_t iUserFreeHead;
2418 /** The number of user nodes we've allocated. */
2419 uint16_t cMaxUsers;
2420 /** The number of present page table entries in the entire pool. */
2421 uint32_t cPresent;
2422 /** Pointer to the array of user nodes - RC pointer. */
2423 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2424 /** Pointer to the array of user nodes - R3 pointer. */
2425 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2426 /** Pointer to the array of user nodes - R0 pointer. */
2427 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2428 /** Head of the chain of free phys ext nodes. */
2429 uint16_t iPhysExtFreeHead;
2430 /** The number of user nodes we've allocated. */
2431 uint16_t cMaxPhysExts;
2432 /** Pointer to the array of physical xref extent - RC pointer. */
2433 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2434 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2435 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2436 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2437 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2438 /** Hash table for GCPhys addresses. */
2439 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2440 /** The head of the age list. */
2441 uint16_t iAgeHead;
2442 /** The tail of the age list. */
2443 uint16_t iAgeTail;
2444 /** Set if the cache is enabled. */
2445 bool fCacheEnabled;
2446 /** Alignment padding. */
2447 bool afPadding1[3];
2448 /** Head of the list of modified pages. */
2449 uint16_t iModifiedHead;
2450 /** The current number of modified pages. */
2451 uint16_t cModifiedPages;
2452 /** Physical access handler type registration handle. */
2453 PGMPHYSHANDLERTYPE hAccessHandlerType;
2454 /** Next available slot (in aDirtyPages). */
2455 uint32_t idxFreeDirtyPage;
2456 /** Number of active dirty pages. */
2457 uint32_t cDirtyPages;
2458 /** Array of current dirty pgm pool page indices. */
2459 uint16_t aidxDirtyPages[16];
2460 /** Array running in parallel to aidxDirtyPages with the page data. */
2461 struct
2462 {
2463 uint64_t aPage[512];
2464 } aDirtyPages[16];
2465
2466 /** The number of pages currently in use. */
2467 uint16_t cUsedPages;
2468#ifdef VBOX_WITH_STATISTICS
2469 /** The high water mark for cUsedPages. */
2470 uint16_t cUsedPagesHigh;
2471 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2472 /** Profiling pgmPoolAlloc(). */
2473 STAMPROFILEADV StatAlloc;
2474 /** Profiling pgmR3PoolClearDoIt(). */
2475 STAMPROFILE StatClearAll;
2476 /** Profiling pgmR3PoolReset(). */
2477 STAMPROFILE StatR3Reset;
2478 /** Profiling pgmPoolFlushPage(). */
2479 STAMPROFILE StatFlushPage;
2480 /** Profiling pgmPoolFree(). */
2481 STAMPROFILE StatFree;
2482 /** Counting explicit flushes by PGMPoolFlushPage(). */
2483 STAMCOUNTER StatForceFlushPage;
2484 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2485 STAMCOUNTER StatForceFlushDirtyPage;
2486 /** Counting flushes for reused pages. */
2487 STAMCOUNTER StatForceFlushReused;
2488 /** Profiling time spent zeroing pages. */
2489 STAMPROFILE StatZeroPage;
2490 /** Profiling of pgmPoolTrackDeref. */
2491 STAMPROFILE StatTrackDeref;
2492 /** Profiling pgmTrackFlushGCPhysPT. */
2493 STAMPROFILE StatTrackFlushGCPhysPT;
2494 /** Profiling pgmTrackFlushGCPhysPTs. */
2495 STAMPROFILE StatTrackFlushGCPhysPTs;
2496 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2497 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2498 /** Number of times we've been out of user records. */
2499 STAMCOUNTER StatTrackFreeUpOneUser;
2500 /** Nr of flushed entries. */
2501 STAMCOUNTER StatTrackFlushEntry;
2502 /** Nr of updated entries. */
2503 STAMCOUNTER StatTrackFlushEntryKeep;
2504 /** Profiling deref activity related tracking GC physical pages. */
2505 STAMPROFILE StatTrackDerefGCPhys;
2506 /** Number of linear searches for a HCPhys in the ram ranges. */
2507 STAMCOUNTER StatTrackLinearRamSearches;
2508 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2509 STAMCOUNTER StamTrackPhysExtAllocFailures;
2510
2511 /** Profiling the RC/R0 \#PF access handler. */
2512 STAMPROFILE StatMonitorPfRZ;
2513 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2514 STAMPROFILE StatMonitorPfRZHandled;
2515 /** Times we've failed interpreting the instruction. */
2516 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2517 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2518 STAMPROFILE StatMonitorPfRZFlushPage;
2519 /* Times we've detected a page table reinit. */
2520 STAMCOUNTER StatMonitorPfRZFlushReinit;
2521 /** Counting flushes for pages that are modified too often. */
2522 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2523 /** Times we've detected fork(). */
2524 STAMCOUNTER StatMonitorPfRZFork;
2525 /** Times we've failed interpreting a patch code instruction. */
2526 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2527 /** Times we've failed interpreting a patch code instruction during flushing. */
2528 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2529 /** The number of times we've seen rep prefixes we can't handle. */
2530 STAMCOUNTER StatMonitorPfRZRepPrefix;
2531 /** Profiling the REP STOSD cases we've handled. */
2532 STAMPROFILE StatMonitorPfRZRepStosd;
2533
2534 /** Profiling the R0/RC regular access handler. */
2535 STAMPROFILE StatMonitorRZ;
2536 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2537 STAMPROFILE StatMonitorRZFlushPage;
2538 /** Per access size counts indexed by size minus 1, last for larger. */
2539 STAMCOUNTER aStatMonitorRZSizes[16+3];
2540 /** Missaligned access counts indexed by offset - 1. */
2541 STAMCOUNTER aStatMonitorRZMisaligned[7];
2542
2543 /** Nr of handled PT faults. */
2544 STAMCOUNTER StatMonitorRZFaultPT;
2545 /** Nr of handled PD faults. */
2546 STAMCOUNTER StatMonitorRZFaultPD;
2547 /** Nr of handled PDPT faults. */
2548 STAMCOUNTER StatMonitorRZFaultPDPT;
2549 /** Nr of handled PML4 faults. */
2550 STAMCOUNTER StatMonitorRZFaultPML4;
2551
2552 /** Profiling the R3 access handler. */
2553 STAMPROFILE StatMonitorR3;
2554 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2555 STAMPROFILE StatMonitorR3FlushPage;
2556 /** Per access size counts indexed by size minus 1, last for larger. */
2557 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2558 /** Missaligned access counts indexed by offset - 1. */
2559 STAMCOUNTER aStatMonitorR3Misaligned[7];
2560 /** Nr of handled PT faults. */
2561 STAMCOUNTER StatMonitorR3FaultPT;
2562 /** Nr of handled PD faults. */
2563 STAMCOUNTER StatMonitorR3FaultPD;
2564 /** Nr of handled PDPT faults. */
2565 STAMCOUNTER StatMonitorR3FaultPDPT;
2566 /** Nr of handled PML4 faults. */
2567 STAMCOUNTER StatMonitorR3FaultPML4;
2568
2569 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2570 STAMCOUNTER StatResetDirtyPages;
2571 /** Times we've called pgmPoolAddDirtyPage. */
2572 STAMCOUNTER StatDirtyPage;
2573 /** Times we've had to flush duplicates for dirty page management. */
2574 STAMCOUNTER StatDirtyPageDupFlush;
2575 /** Times we've had to flush because of overflow. */
2576 STAMCOUNTER StatDirtyPageOverFlowFlush;
2577
2578 /** The high water mark for cModifiedPages. */
2579 uint16_t cModifiedPagesHigh;
2580 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2581
2582 /** The number of cache hits. */
2583 STAMCOUNTER StatCacheHits;
2584 /** The number of cache misses. */
2585 STAMCOUNTER StatCacheMisses;
2586 /** The number of times we've got a conflict of 'kind' in the cache. */
2587 STAMCOUNTER StatCacheKindMismatches;
2588 /** Number of times we've been out of pages. */
2589 STAMCOUNTER StatCacheFreeUpOne;
2590 /** The number of cacheable allocations. */
2591 STAMCOUNTER StatCacheCacheable;
2592 /** The number of uncacheable allocations. */
2593 STAMCOUNTER StatCacheUncacheable;
2594#else
2595 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2596#endif
2597 /** The AVL tree for looking up a page by its HC physical address. */
2598 AVLOHCPHYSTREE HCPhysTree;
2599 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2600 /** Array of pages. (cMaxPages in length)
2601 * The Id is the index into thist array.
2602 */
2603 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2604} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2605AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2606AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2607AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2608#ifdef VBOX_WITH_STATISTICS
2609AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2610#endif
2611AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2612
2613
2614/** @def PGMPOOL_PAGE_2_PTR
2615 * Maps a pool page pool into the current context.
2616 *
2617 * @returns VBox status code.
2618 * @param a_pVM Pointer to the VM.
2619 * @param a_pPage The pool page.
2620 *
2621 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2622 * small page window employeed by that function. Be careful.
2623 * @remark There is no need to assert on the result.
2624 */
2625#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2626# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2627#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2628# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2629DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2630{
2631 AssertPtr(a_pPage);
2632 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2633 return a_pPage->pvPageR3;
2634}
2635#else
2636# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2637#endif
2638
2639
2640/** @def PGMPOOL_PAGE_2_PTR_V2
2641 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2642 *
2643 * @returns VBox status code.
2644 * @param a_pVM Pointer to the VM.
2645 * @param a_pVCpu The current CPU.
2646 * @param a_pPage The pool page.
2647 *
2648 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2649 * small page window employeed by that function. Be careful.
2650 * @remark There is no need to assert on the result.
2651 */
2652#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2653# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2654#else
2655# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2656#endif
2657
2658
2659/** @name Per guest page tracking data.
2660 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2661 * is to use more bits for it and split it up later on. But for now we'll play
2662 * safe and change as little as possible.
2663 *
2664 * The 16-bit word has two parts:
2665 *
2666 * The first 14-bit forms the @a idx field. It is either the index of a page in
2667 * the shadow page pool, or and index into the extent list.
2668 *
2669 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2670 * shadow page pool references to the page. If cRefs equals
2671 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2672 * (misnomer) table and not the shadow page pool.
2673 *
2674 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2675 * the 16-bit word.
2676 *
2677 * @{ */
2678/** The shift count for getting to the cRefs part. */
2679#define PGMPOOL_TD_CREFS_SHIFT 14
2680/** The mask applied after shifting the tracking data down by
2681 * PGMPOOL_TD_CREFS_SHIFT. */
2682#define PGMPOOL_TD_CREFS_MASK 0x3
2683/** The cRefs value used to indicate that the idx is the head of a
2684 * physical cross reference list. */
2685#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2686/** The shift used to get idx. */
2687#define PGMPOOL_TD_IDX_SHIFT 0
2688/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2689#define PGMPOOL_TD_IDX_MASK 0x3fff
2690/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2691 * simply too many mappings of this page. */
2692#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2693
2694/** @def PGMPOOL_TD_MAKE
2695 * Makes a 16-bit tracking data word.
2696 *
2697 * @returns tracking data.
2698 * @param cRefs The @a cRefs field. Must be within bounds!
2699 * @param idx The @a idx field. Must also be within bounds! */
2700#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2701
2702/** @def PGMPOOL_TD_GET_CREFS
2703 * Get the @a cRefs field from a tracking data word.
2704 *
2705 * @returns The @a cRefs field
2706 * @param u16 The tracking data word.
2707 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2708 * non-zero @a u16. */
2709#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2710
2711/** @def PGMPOOL_TD_GET_IDX
2712 * Get the @a idx field from a tracking data word.
2713 *
2714 * @returns The @a idx field
2715 * @param u16 The tracking data word. */
2716#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2717/** @} */
2718
2719
2720
2721/** @name A20 gate macros
2722 * @{ */
2723#define PGM_WITH_A20
2724#ifdef PGM_WITH_A20
2725# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2726# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2727# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2728 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2729# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2730#else
2731# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2732# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2733# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2734# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2735#endif
2736/** @} */
2737
2738
2739/**
2740 * Roots and anchors for trees and list employing self relative offsets as
2741 * pointers.
2742 *
2743 * When using self-relative offsets instead of pointers, the offsets needs to be
2744 * the same in all offsets. Thus the roots and anchors needs to live on the
2745 * hyper heap just like the nodes.
2746 */
2747typedef struct PGMTREES
2748{
2749 /** List of physical access handler types (offset pointers) of type
2750 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2751 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2752 /** Physical access handlers (AVL range+offsetptr tree). */
2753 AVLROGCPHYSTREE PhysHandlers;
2754#ifdef VBOX_WITH_RAW_MODE
2755 /** Virtual access handlers (AVL range + GC ptr tree). */
2756 AVLROGCPTRTREE VirtHandlers;
2757 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2758 * @remarks Handler of the hypervisor kind are of course not present. */
2759 AVLROGCPHYSTREE PhysToVirtHandlers;
2760 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2761 AVLROGCPTRTREE HyperVirtHandlers;
2762 /** List of virtual access handler types (offset pointers) of type
2763 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2764 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2765#endif
2766} PGMTREES;
2767/** Pointer to PGM trees. */
2768typedef PGMTREES *PPGMTREES;
2769
2770
2771/**
2772 * Page fault guest state for the AMD64 paging mode.
2773 */
2774typedef struct PGMPTWALKCORE
2775{
2776 /** The guest virtual address that is being resolved by the walk
2777 * (input). */
2778 RTGCPTR GCPtr;
2779
2780 /** The guest physical address that is the result of the walk.
2781 * @remarks only valid if fSucceeded is set. */
2782 RTGCPHYS GCPhys;
2783
2784 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2785 bool fSucceeded;
2786 /** The level problem arrised at.
2787 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2788 * level 8. This is 0 on success. */
2789 uint8_t uLevel;
2790 /** Set if the page isn't present. */
2791 bool fNotPresent;
2792 /** Encountered a bad physical address. */
2793 bool fBadPhysAddr;
2794 /** Set if there was reserved bit violations. */
2795 bool fRsvdError;
2796 /** Set if it involves a big page (2/4 MB). */
2797 bool fBigPage;
2798 /** Set if it involves a gigantic page (1 GB). */
2799 bool fGigantPage;
2800 /** The effective X86_PTE_US flag for the address. */
2801 bool fEffectiveUS;
2802 /** The effective X86_PTE_RW flag for the address. */
2803 bool fEffectiveRW;
2804 /** The effective X86_PTE_NX flag for the address. */
2805 bool fEffectiveNX;
2806 bool afPadding1[2];
2807 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2808 * The NX bit is inverted and shifted down 63 places to bit 0. */
2809 uint32_t fEffective;
2810} PGMPTWALKCORE;
2811
2812/** @name PGMPTWALKCORE::fEffective bits.
2813 * @{ */
2814/** Effective execute bit (!NX). */
2815#define PGMPTWALK_EFF_X UINT32_C(1)
2816/** Effective write access bit. */
2817#define PGMPTWALK_EFF_RW X86_PTE_RW
2818/** Effective user-mode access bit. */
2819#define PGMPTWALK_EFF_US X86_PTE_US
2820/** Effective write through cache bit. */
2821#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2822/** Effective cache disabled bit. */
2823#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2824/** Effective accessed bit. */
2825#define PGMPTWALK_EFF_A X86_PTE_A
2826/** The dirty bit of the final entry. */
2827#define PGMPTWALK_EFF_D X86_PTE_D
2828/** The PAT bit of the final entry. */
2829#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2830/** The global bit of the final entry. */
2831#define PGMPTWALK_EFF_G X86_PTE_G
2832/** @} */
2833
2834
2835/**
2836 * Guest page table walk for the AMD64 mode.
2837 */
2838typedef struct PGMPTWALKGSTAMD64
2839{
2840 /** The common core. */
2841 PGMPTWALKCORE Core;
2842
2843 PX86PML4 pPml4;
2844 PX86PML4E pPml4e;
2845 X86PML4E Pml4e;
2846
2847 PX86PDPT pPdpt;
2848 PX86PDPE pPdpe;
2849 X86PDPE Pdpe;
2850
2851 PX86PDPAE pPd;
2852 PX86PDEPAE pPde;
2853 X86PDEPAE Pde;
2854
2855 PX86PTPAE pPt;
2856 PX86PTEPAE pPte;
2857 X86PTEPAE Pte;
2858} PGMPTWALKGSTAMD64;
2859/** Pointer to a AMD64 guest page table walk. */
2860typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2861/** Pointer to a const AMD64 guest page table walk. */
2862typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2863
2864/**
2865 * Guest page table walk for the PAE mode.
2866 */
2867typedef struct PGMPTWALKGSTPAE
2868{
2869 /** The common core. */
2870 PGMPTWALKCORE Core;
2871
2872 PX86PDPT pPdpt;
2873 PX86PDPE pPdpe;
2874 X86PDPE Pdpe;
2875
2876 PX86PDPAE pPd;
2877 PX86PDEPAE pPde;
2878 X86PDEPAE Pde;
2879
2880 PX86PTPAE pPt;
2881 PX86PTEPAE pPte;
2882 X86PTEPAE Pte;
2883} PGMPTWALKGSTPAE;
2884/** Pointer to a PAE guest page table walk. */
2885typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2886/** Pointer to a const AMD64 guest page table walk. */
2887typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2888
2889/**
2890 * Guest page table walk for the 32-bit mode.
2891 */
2892typedef struct PGMPTWALKGST32BIT
2893{
2894 /** The common core. */
2895 PGMPTWALKCORE Core;
2896
2897 PX86PD pPd;
2898 PX86PDE pPde;
2899 X86PDE Pde;
2900
2901 PX86PT pPt;
2902 PX86PTE pPte;
2903 X86PTE Pte;
2904} PGMPTWALKGST32BIT;
2905/** Pointer to a 32-bit guest page table walk. */
2906typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2907/** Pointer to a const 32-bit guest page table walk. */
2908typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2909
2910/**
2911 * Which part of PGMPTWALKGST that is valid.
2912 */
2913typedef enum PGMPTWALKGSTTYPE
2914{
2915 /** Customary invalid 0 value. */
2916 PGMPTWALKGSTTYPE_INVALID = 0,
2917 /** PGMPTWALKGST::u.Amd64 is valid. */
2918 PGMPTWALKGSTTYPE_AMD64,
2919 /** PGMPTWALKGST::u.Pae is valid. */
2920 PGMPTWALKGSTTYPE_PAE,
2921 /** PGMPTWALKGST::u.Legacy is valid. */
2922 PGMPTWALKGSTTYPE_32BIT,
2923 /** Customary 32-bit type hack. */
2924 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2925} PGMPTWALKGSTTYPE;
2926
2927/**
2928 * Combined guest page table walk result.
2929 */
2930typedef struct PGMPTWALKGST
2931{
2932 union
2933 {
2934 /** The page walker core - always valid. */
2935 PGMPTWALKCORE Core;
2936 /** The page walker for AMD64. */
2937 PGMPTWALKGSTAMD64 Amd64;
2938 /** The page walker for PAE (32-bit). */
2939 PGMPTWALKGSTPAE Pae;
2940 /** The page walker for 32-bit paging (called legacy due to C naming
2941 * convension). */
2942 PGMPTWALKGST32BIT Legacy;
2943 } u;
2944 /** Indicates which part of the union is valid. */
2945 PGMPTWALKGSTTYPE enmType;
2946} PGMPTWALKGST;
2947/** Pointer to a combined guest page table walk result. */
2948typedef PGMPTWALKGST *PPGMPTWALKGST;
2949/** Pointer to a read-only combined guest page table walk result. */
2950typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2951
2952
2953/** @name Paging mode macros
2954 * @{
2955 */
2956#ifdef IN_RC
2957# define PGM_CTX(a,b) a##RC##b
2958# define PGM_CTX_STR(a,b) a "GC" b
2959# define PGM_CTX_DECL(type) VMMRCDECL(type)
2960#else
2961# ifdef IN_RING3
2962# define PGM_CTX(a,b) a##R3##b
2963# define PGM_CTX_STR(a,b) a "R3" b
2964# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2965# else
2966# define PGM_CTX(a,b) a##R0##b
2967# define PGM_CTX_STR(a,b) a "R0" b
2968# define PGM_CTX_DECL(type) VMMDECL(type)
2969# endif
2970#endif
2971
2972#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2973#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2974#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2975#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2976#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2977#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2978#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2979#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2980#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2981#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2982#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2983#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2984#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2985#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2986#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2987#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2988
2989#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2990#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2991#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2992#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2993#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2994#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2995#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2996#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2997#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2998#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2999#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
3000#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
3001#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
3002#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
3003#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
3004#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
3005#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
3006#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
3007#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
3008#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
3009#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
3010#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
3011#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
3012#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
3013#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
3014
3015/* Shw_Gst */
3016#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
3017#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
3018#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
3019#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
3020#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
3021#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
3022#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
3023#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
3024#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
3025#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
3026#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
3027#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
3028#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
3029#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
3030#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
3031#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
3032#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
3033#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
3034#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
3035#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
3036#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
3037#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
3038#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
3039#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
3040#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
3041#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
3042#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
3043#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
3044#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
3045#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
3046#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
3047#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
3048#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
3049#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
3050
3051#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
3052#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
3053#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
3054#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
3055#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
3056#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
3057#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
3058#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
3059#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
3060#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
3061#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
3062#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
3063#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
3064#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
3065#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
3066#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
3067#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
3068#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
3069#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
3070#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
3071#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
3072#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
3073#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
3074#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
3075#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
3076#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
3077#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
3078#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
3079
3080#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
3081#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
3082#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
3083#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
3084#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
3085#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
3086#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
3087#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
3088#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
3089#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
3090#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
3091#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
3092#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
3093#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
3094#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
3095#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
3096#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
3097#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
3098#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
3099#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
3100#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
3101#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
3102#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
3103#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
3104#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3105#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3106#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3107#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3108#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3109
3110#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3111/** @} */
3112
3113
3114/**
3115 * Function pointers for guest paging.
3116 */
3117typedef struct PGMMODEDATAGST
3118{
3119 /** The guest mode type. */
3120 uint32_t uType;
3121 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
3122 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
3123 DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
3124 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3125 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3126#ifdef IN_RING3
3127 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3128#endif
3129} PGMMODEDATAGST;
3130
3131/** The length of g_aPgmGuestModeData. */
3132#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
3133# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
3134#else
3135# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3136#endif
3137/** The guest mode data array. */
3138extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
3139
3140
3141/**
3142 * Function pointers for shadow paging.
3143 */
3144typedef struct PGMMODEDATASHW
3145{
3146 /** The shadow mode type. */
3147 uint32_t uType;
3148 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
3149 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
3150 uint64_t fMask, uint32_t fOpFlags);
3151 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
3152 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3153#ifdef IN_RING3
3154 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3155#endif
3156} PGMMODEDATASHW;
3157
3158/** The length of g_aPgmShadowModeData. */
3159#ifndef IN_RC
3160# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
3161#else
3162# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3163#endif
3164/** The shadow mode data array. */
3165extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
3166
3167
3168/**
3169 * Function pointers for guest+shadow paging.
3170 */
3171typedef struct PGMMODEDATABTH
3172{
3173 /** The shadow mode type. */
3174 uint32_t uShwType;
3175 /** The guest mode type. */
3176 uint32_t uGstType;
3177
3178 DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3179 DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
3180 DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3181 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
3182 DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3183 DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPU pVCpu);
3184 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3185#ifndef IN_RING3
3186 DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
3187#endif
3188#ifdef VBOX_STRICT
3189 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
3190#endif
3191} PGMMODEDATABTH;
3192
3193/** The length of g_aPgmBothModeData. */
3194#ifndef IN_RC
3195# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3196#else
3197# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_PAE + 1 - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3198#endif
3199/** The guest+shadow mode data array. */
3200extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
3201
3202
3203#ifdef VBOX_WITH_STATISTICS
3204/**
3205 * PGM statistics.
3206 *
3207 * These lives on the heap when compiled in as they would otherwise waste
3208 * unnecessary space in release builds.
3209 */
3210typedef struct PGMSTATS
3211{
3212 /* R3 only: */
3213 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3214 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3215
3216 /* R3+RZ */
3217 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3218 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3219 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3220 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3221 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3222 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3223 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3224 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3225 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3226 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3227 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3228 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3229 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3230 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3231 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3232 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3233 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3234 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3235 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3236 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3237 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3238 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3239 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3240 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3241 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3242 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3243 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3244 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3245/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3246 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3247 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3248/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3249
3250 /* RC only: */
3251 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3252 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3253
3254 STAMCOUNTER StatRZPhysRead;
3255 STAMCOUNTER StatRZPhysReadBytes;
3256 STAMCOUNTER StatRZPhysWrite;
3257 STAMCOUNTER StatRZPhysWriteBytes;
3258 STAMCOUNTER StatR3PhysRead;
3259 STAMCOUNTER StatR3PhysReadBytes;
3260 STAMCOUNTER StatR3PhysWrite;
3261 STAMCOUNTER StatR3PhysWriteBytes;
3262 STAMCOUNTER StatRCPhysRead;
3263 STAMCOUNTER StatRCPhysReadBytes;
3264 STAMCOUNTER StatRCPhysWrite;
3265 STAMCOUNTER StatRCPhysWriteBytes;
3266
3267 STAMCOUNTER StatRZPhysSimpleRead;
3268 STAMCOUNTER StatRZPhysSimpleReadBytes;
3269 STAMCOUNTER StatRZPhysSimpleWrite;
3270 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3271 STAMCOUNTER StatR3PhysSimpleRead;
3272 STAMCOUNTER StatR3PhysSimpleReadBytes;
3273 STAMCOUNTER StatR3PhysSimpleWrite;
3274 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3275 STAMCOUNTER StatRCPhysSimpleRead;
3276 STAMCOUNTER StatRCPhysSimpleReadBytes;
3277 STAMCOUNTER StatRCPhysSimpleWrite;
3278 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3279
3280 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3281 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3282 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3283 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3284 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3285 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3286 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3287
3288 /** Time spent by the host OS for large page allocation. */
3289 STAMPROFILE StatAllocLargePage;
3290 /** Time spent clearing the newly allocated large pages. */
3291 STAMPROFILE StatClearLargePage;
3292 /** The number of times allocating a large pages takes more than the allowed period. */
3293 STAMCOUNTER StatLargePageOverflow;
3294 /** pgmPhysIsValidLargePage profiling - R3 */
3295 STAMPROFILE StatR3IsValidLargePage;
3296 /** pgmPhysIsValidLargePage profiling - RZ*/
3297 STAMPROFILE StatRZIsValidLargePage;
3298
3299 STAMPROFILE StatChunkAging;
3300 STAMPROFILE StatChunkFindCandidate;
3301 STAMPROFILE StatChunkUnmap;
3302 STAMPROFILE StatChunkMap;
3303} PGMSTATS;
3304#endif /* VBOX_WITH_STATISTICS */
3305
3306
3307/**
3308 * Converts a PGM pointer into a VM pointer.
3309 * @returns Pointer to the VM structure the PGM is part of.
3310 * @param pPGM Pointer to PGM instance data.
3311 */
3312#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3313
3314/**
3315 * PGM Data (part of VM)
3316 */
3317typedef struct PGM
3318{
3319 /** Offset to the VM structure. */
3320 int32_t offVM;
3321 /** Offset of the PGMCPU structure relative to VMCPU. */
3322 int32_t offVCpuPGM;
3323
3324 /** @cfgm{/RamPreAlloc, boolean, false}
3325 * Indicates whether the base RAM should all be allocated before starting
3326 * the VM (default), or if it should be allocated when first written to.
3327 */
3328 bool fRamPreAlloc;
3329 /** Indicates whether write monitoring is currently in use.
3330 * This is used to prevent conflicts between live saving and page sharing
3331 * detection. */
3332 bool fPhysWriteMonitoringEngaged;
3333 /** Set if the CPU has less than 52-bit physical address width.
3334 * This is used */
3335 bool fLessThan52PhysicalAddressBits;
3336 /** Set when nested paging is active.
3337 * This is meant to save calls to HMIsNestedPagingActive and let the
3338 * compilers optimize the code better. Whether we use nested paging or
3339 * not is something we find out during VMM initialization and we won't
3340 * change this later on. */
3341 bool fNestedPaging;
3342 /** The host paging mode. (This is what SUPLib reports.) */
3343 SUPPAGINGMODE enmHostMode;
3344 /** We're not in a state which permits writes to guest memory.
3345 * (Only used in strict builds.) */
3346 bool fNoMorePhysWrites;
3347 /** @cfgm{/PageFusionAllowed, boolean, false}
3348 * Whether page fusion is allowed. */
3349 bool fPageFusionAllowed;
3350 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3351 * Whether PCI passthrough is enabled. */
3352 bool fPciPassthrough;
3353 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3354 uint8_t cMmio2Regions;
3355 /** Restore original ROM page content when resetting after loading state.
3356 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3357 * enables the VM to start using an updated ROM without requiring powering
3358 * down the VM, just rebooting or resetting it. */
3359 bool fRestoreRomPagesOnReset;
3360 /** Whether to automatically clear all RAM pages on reset. */
3361 bool fZeroRamPagesOnReset;
3362 /** Alignment padding. */
3363 bool afAlignment3[7];
3364
3365 /** Indicates that PGMR3FinalizeMappings has been called and that further
3366 * PGMR3MapIntermediate calls will be rejected. */
3367 bool fFinalizedMappings;
3368 /** If set no conflict checks are required. */
3369 bool fMappingsFixed;
3370 /** If set if restored as fixed but we were unable to re-fixate at the old
3371 * location because of room or address incompatibilities. */
3372 bool fMappingsFixedRestored;
3373 /** Size of fixed mapping.
3374 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3375 uint32_t cbMappingFixed;
3376 /** Generation ID for the RAM ranges. This member is incremented everytime
3377 * a RAM range is linked or unlinked. */
3378 uint32_t volatile idRamRangesGen;
3379
3380 /** Base address (GC) of fixed mapping.
3381 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3382 RTGCPTR GCPtrMappingFixed;
3383 /** The address of the previous RAM range mapping. */
3384 RTGCPTR GCPtrPrevRamRangeMapping;
3385
3386 /** Physical access handler type for ROM protection. */
3387 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3388 /** Alignment padding. */
3389 uint32_t u32Padding;
3390
3391 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3392 RTGCPHYS GCPhys4MBPSEMask;
3393 /** Mask containing the invalid bits of a guest physical address.
3394 * @remarks this does not stop at bit 52. */
3395 RTGCPHYS GCPhysInvAddrMask;
3396
3397
3398 /** RAM range TLB for R3. */
3399 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3400 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3401 * This is sorted by physical address and contains no overlapping ranges. */
3402 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3403 /** Root of the RAM range search tree for ring-3. */
3404 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3405 /** PGM offset based trees - R3 Ptr. */
3406 R3PTRTYPE(PPGMTREES) pTreesR3;
3407 /** Caching the last physical handler we looked up in R3. */
3408 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3409 /** Shadow Page Pool - R3 Ptr. */
3410 R3PTRTYPE(PPGMPOOL) pPoolR3;
3411 /** Linked list of GC mappings - for HC.
3412 * The list is sorted ascending on address. */
3413 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3414 /** Pointer to the list of ROM ranges - for R3.
3415 * This is sorted by physical address and contains no overlapping ranges. */
3416 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3417 /** Pointer to the list of MMIO2 ranges - for R3.
3418 * Registration order. */
3419 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3420 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3421 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3422
3423 /** RAM range TLB for R0. */
3424 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3425 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3426 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3427 /** Root of the RAM range search tree for ring-0. */
3428 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3429 /** PGM offset based trees - R0 Ptr. */
3430 R0PTRTYPE(PPGMTREES) pTreesR0;
3431 /** Caching the last physical handler we looked up in R0. */
3432 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3433 /** Shadow Page Pool - R0 Ptr. */
3434 R0PTRTYPE(PPGMPOOL) pPoolR0;
3435 /** Linked list of GC mappings - for R0.
3436 * The list is sorted ascending on address. */
3437 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3438 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3439 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3440 RTR0PTR R0PtrAlignment0;
3441 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3442 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3443
3444 /** RAM range TLB for RC. */
3445 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3446 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3447 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3448 /** Root of the RAM range search tree for raw-mode context. */
3449 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3450 /** PGM offset based trees - RC Ptr. */
3451 RCPTRTYPE(PPGMTREES) pTreesRC;
3452 /** Caching the last physical handler we looked up in RC. */
3453 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3454 /** Shadow Page Pool - RC Ptr. */
3455 RCPTRTYPE(PPGMPOOL) pPoolRC;
3456 /** Linked list of GC mappings - for RC.
3457 * The list is sorted ascending on address. */
3458 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3459 /** RC pointer corresponding to PGM::pRomRangesR3. */
3460 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3461 RTRCPTR RCPtrAlignment0;
3462 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3463 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3464 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3465 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3466
3467
3468 /** Pointer to the 5 page CR3 content mapping.
3469 * The first page is always the CR3 (in some form) while the 4 other pages
3470 * are used for the PDs in PAE mode. */
3471 RTGCPTR GCPtrCR3Mapping;
3472
3473 /** @name Intermediate Context
3474 * @{ */
3475 /** Pointer to the intermediate page directory - Normal. */
3476 R3PTRTYPE(PX86PD) pInterPD;
3477 /** Pointer to the intermediate page tables - Normal.
3478 * There are two page tables, one for the identity mapping and one for
3479 * the host context mapping (of the core code). */
3480 R3PTRTYPE(PX86PT) apInterPTs[2];
3481 /** Pointer to the intermediate page tables - PAE. */
3482 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3483 /** Pointer to the intermediate page directory - PAE. */
3484 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3485 /** Pointer to the intermediate page directory - PAE. */
3486 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3487 /** Pointer to the intermediate page-map level 4 - AMD64. */
3488 R3PTRTYPE(PX86PML4) pInterPaePML4;
3489 /** Pointer to the intermediate page directory - AMD64. */
3490 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3491 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3492 RTHCPHYS HCPhysInterPD;
3493 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3494 RTHCPHYS HCPhysInterPaePDPT;
3495 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3496 RTHCPHYS HCPhysInterPaePML4;
3497 /** @} */
3498
3499 /** Base address of the dynamic page mapping area.
3500 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3501 *
3502 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3503 * work out. Some cleaning up of the initialization that would
3504 * remove this memory is yet to be done...
3505 */
3506 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3507 /** The address of the raw-mode context mapping cache. */
3508 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3509 /** The address of the ring-0 mapping cache if we're making use of it. */
3510 RTR0PTR pvR0DynMapUsed;
3511
3512 /** Hack: Number of deprecated page mapping locks taken by the current lock
3513 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3514 uint32_t cDeprecatedPageLocks;
3515#if HC_ARCH_BITS == 64
3516 /** Alignment padding. */
3517 uint32_t u32Alignment2;
3518#endif
3519
3520
3521 /** PGM critical section.
3522 * This protects the physical & virtual access handlers, ram ranges,
3523 * and the page flag updating (some of it anyway).
3524 */
3525 PDMCRITSECT CritSectX;
3526
3527 /**
3528 * Data associated with managing the ring-3 mappings of the allocation chunks.
3529 */
3530 struct
3531 {
3532 /** The chunk tree, ordered by chunk id. */
3533#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3534 R3PTRTYPE(PAVLU32NODECORE) pTree;
3535#else
3536 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3537#endif
3538#if HC_ARCH_BITS == 32
3539 uint32_t u32Alignment0;
3540#endif
3541 /** The chunk mapping TLB. */
3542 PGMCHUNKR3MAPTLB Tlb;
3543 /** The number of mapped chunks. */
3544 uint32_t c;
3545 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3546 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3547 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3548 uint32_t cMax;
3549 /** The current time. This is incremented whenever a chunk is inserted. */
3550 uint32_t iNow;
3551 /** Alignment padding. */
3552 uint32_t u32Alignment1;
3553 } ChunkR3Map;
3554
3555 /**
3556 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3557 */
3558 PGMPAGER3MAPTLB PhysTlbHC;
3559
3560 /** @name The zero page.
3561 * @{ */
3562 /** The host physical address of the zero page. */
3563 RTHCPHYS HCPhysZeroPg;
3564 /** The ring-3 mapping of the zero page. */
3565 RTR3PTR pvZeroPgR3;
3566 /** The ring-0 mapping of the zero page. */
3567 RTR0PTR pvZeroPgR0;
3568 /** The GC mapping of the zero page. */
3569 RTRCPTR pvZeroPgRC;
3570 RTRCPTR RCPtrAlignment3;
3571 /** @}*/
3572
3573 /** @name The Invalid MMIO page.
3574 * This page is filled with 0xfeedface.
3575 * @{ */
3576 /** The host physical address of the invalid MMIO page. */
3577 RTHCPHYS HCPhysMmioPg;
3578 /** The host pysical address of the invalid MMIO page plus all invalid
3579 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3580 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3581 RTHCPHYS HCPhysInvMmioPg;
3582 /** The ring-3 mapping of the invalid MMIO page. */
3583 RTR3PTR pvMmioPgR3;
3584#if HC_ARCH_BITS == 32
3585 RTR3PTR R3PtrAlignment4;
3586#endif
3587 /** @} */
3588
3589
3590 /** The number of handy pages. */
3591 uint32_t cHandyPages;
3592
3593 /** The number of large handy pages. */
3594 uint32_t cLargeHandyPages;
3595
3596 /**
3597 * Array of handy pages.
3598 *
3599 * This array is used in a two way communication between pgmPhysAllocPage
3600 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3601 * an intermediary.
3602 *
3603 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3604 * (The current size of 32 pages, means 128 KB of handy memory.)
3605 */
3606 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3607
3608 /**
3609 * Array of large handy pages. (currently size 1)
3610 *
3611 * This array is used in a two way communication between pgmPhysAllocLargePage
3612 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3613 * an intermediary.
3614 */
3615 GMMPAGEDESC aLargeHandyPage[1];
3616
3617 /**
3618 * Live save data.
3619 */
3620 struct
3621 {
3622 /** Per type statistics. */
3623 struct
3624 {
3625 /** The number of ready pages. */
3626 uint32_t cReadyPages;
3627 /** The number of dirty pages. */
3628 uint32_t cDirtyPages;
3629 /** The number of ready zero pages. */
3630 uint32_t cZeroPages;
3631 /** The number of write monitored pages. */
3632 uint32_t cMonitoredPages;
3633 } Rom,
3634 Mmio2,
3635 Ram;
3636 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3637 uint32_t cIgnoredPages;
3638 /** Indicates that a live save operation is active. */
3639 bool fActive;
3640 /** Padding. */
3641 bool afReserved[2];
3642 /** The next history index. */
3643 uint8_t iDirtyPagesHistory;
3644 /** History of the total amount of dirty pages. */
3645 uint32_t acDirtyPagesHistory[64];
3646 /** Short term dirty page average. */
3647 uint32_t cDirtyPagesShort;
3648 /** Long term dirty page average. */
3649 uint32_t cDirtyPagesLong;
3650 /** The number of saved pages. This is used to get some kind of estimate of the
3651 * link speed so we can decide when we're done. It is reset after the first
3652 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3653 * zero pages. */
3654 uint64_t cSavedPages;
3655 /** The nanosecond timestamp when cSavedPages was 0. */
3656 uint64_t uSaveStartNS;
3657 /** Pages per second (for statistics). */
3658 uint32_t cPagesPerSecond;
3659 uint32_t cAlignment;
3660 } LiveSave;
3661
3662 /** @name Error injection.
3663 * @{ */
3664 /** Inject handy page allocation errors pretending we're completely out of
3665 * memory. */
3666 bool volatile fErrInjHandyPages;
3667 /** Padding. */
3668 bool afReserved[3];
3669 /** @} */
3670
3671 /** @name Release Statistics
3672 * @{ */
3673 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3674 uint32_t cPrivatePages; /**< The number of private pages. */
3675 uint32_t cSharedPages; /**< The number of shared pages. */
3676 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3677 uint32_t cZeroPages; /**< The number of zero backed pages. */
3678 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3679 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3680 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3681 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3682 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3683 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3684 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3685 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3686 uint32_t cLargePages; /**< The number of large pages. */
3687 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3688/* uint32_t aAlignment4[1]; */
3689
3690 /** The number of times we were forced to change the hypervisor region location. */
3691 STAMCOUNTER cRelocations;
3692
3693 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3694 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3695 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3696
3697 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3698 /** @} */
3699
3700#ifdef VBOX_WITH_STATISTICS
3701 /** @name Statistics on the heap.
3702 * @{ */
3703 R3PTRTYPE(PGMSTATS *) pStatsR3;
3704 R0PTRTYPE(PGMSTATS *) pStatsR0;
3705 RCPTRTYPE(PGMSTATS *) pStatsRC;
3706 RTRCPTR RCPtrAlignment;
3707 /** @} */
3708#endif
3709} PGM;
3710#ifndef IN_TSTVMSTRUCTGC /* HACK */
3711AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3712AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3713AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3714AssertCompileMemberAlignment(PGM, CritSectX, 8);
3715AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3716AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3717AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3718AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3719AssertCompileMemberAlignment(PGM, cRelocations, 8);
3720#endif /* !IN_TSTVMSTRUCTGC */
3721/** Pointer to the PGM instance data. */
3722typedef PGM *PPGM;
3723
3724
3725
3726typedef struct PGMCPUSTATS
3727{
3728 /* Common */
3729 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3730 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3731
3732 /* R0 only: */
3733 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3734 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3735
3736 /* RZ only: */
3737 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3738 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3739 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3740 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3741 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3742 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3743 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3744 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3745 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3746 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3747 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3748 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3749 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3750 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3751 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3752 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3753 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3754 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3755 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3756 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3757 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3758 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3759 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3760 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3761 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3762 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3763 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3764 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3765 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3766 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3767 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3768 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3769 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3770 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3771 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3772 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3773 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3774 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3775 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3776 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3777 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3778 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3779 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3780 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3781 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3782 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3783 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3784 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3785 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3786 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3787 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3788 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3789 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3790 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3791 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3792 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3793 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3794 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3795 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3796 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3797 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3798 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3799 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3800 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3801 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3802 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3803 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3804 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3805 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3806 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3807 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3808 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3809 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3810 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3811 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3812 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3813 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3814 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3815
3816 /* HC - R3 and (maybe) R0: */
3817
3818 /* RZ & R3: */
3819 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3820 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3821 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3822 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3823 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3824 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3825 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3826 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3827 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3828 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3829 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3830 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3831 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3832 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3833 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3834 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3835 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3836 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3837 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3838 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3839 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3840 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3841 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3842 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3843 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3844 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3845 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3846 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3847 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3848 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3849 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3850 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3851 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3852 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3853 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3854 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3855 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3856 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3857 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3858 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3859 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3860 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3861 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3862 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3863 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3864 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3865 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3866 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3867
3868 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3869 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3870 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3871 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3872 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3873 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3874 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3875 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3876 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3877 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3878 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3879 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3880 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3881 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3882 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3883 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3884 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3885 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3886 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3887 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3888 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3889 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3890 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3891 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3892 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3893 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3894 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3895 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3896 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3897 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3898 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3899 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3900 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3901 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3902 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3903 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3904 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3905 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3906 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3907 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3908 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3909 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3910 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3911 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3912 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3913 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3914 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3915 /** @} */
3916} PGMCPUSTATS;
3917
3918
3919/**
3920 * Converts a PGMCPU pointer into a VM pointer.
3921 * @returns Pointer to the VM structure the PGM is part of.
3922 * @param pPGM Pointer to PGMCPU instance data.
3923 */
3924#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3925
3926/**
3927 * Converts a PGMCPU pointer into a PGM pointer.
3928 * @returns Pointer to the VM structure the PGM is part of.
3929 * @param pPGMCpu Pointer to PGMCPU instance data.
3930 */
3931#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3932
3933/**
3934 * PGMCPU Data (part of VMCPU).
3935 */
3936typedef struct PGMCPU
3937{
3938 /** Offset to the VM structure. */
3939 int32_t offVM;
3940 /** Offset to the VMCPU structure. */
3941 int32_t offVCpu;
3942 /** Offset of the PGM structure relative to VMCPU. */
3943 int32_t offPGM;
3944 uint32_t uPadding0; /**< structure size alignment. */
3945
3946#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3947 /** Automatically tracked physical memory mapping set.
3948 * Ring-0 and strict raw-mode builds. */
3949 PGMMAPSET AutoSet;
3950#endif
3951
3952 /** A20 gate mask.
3953 * Our current approach to A20 emulation is to let REM do it and don't bother
3954 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3955 * But whould need arrise, we'll subject physical addresses to this mask. */
3956 RTGCPHYS GCPhysA20Mask;
3957 /** A20 gate state - boolean! */
3958 bool fA20Enabled;
3959 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3960 bool fNoExecuteEnabled;
3961 /** Unused bits. */
3962 bool afUnused[2];
3963
3964 /** What needs syncing (PGM_SYNC_*).
3965 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3966 * PGMFlushTLB, and PGMR3Load. */
3967 uint32_t fSyncFlags;
3968
3969 /** The shadow paging mode. */
3970 PGMMODE enmShadowMode;
3971 /** The guest paging mode. */
3972 PGMMODE enmGuestMode;
3973 /** Guest mode data table index (PGM_TYPE_XXX). */
3974 uint8_t volatile idxGuestModeData;
3975 /** Shadow mode data table index (PGM_TYPE_XXX). */
3976 uint8_t volatile idxShadowModeData;
3977 /** Both mode data table index (complicated). */
3978 uint8_t volatile idxBothModeData;
3979 /** Alignment padding. */
3980 uint8_t abPadding[5];
3981
3982 /** The current physical address represented in the guest CR3 register. */
3983 RTGCPHYS GCPhysCR3;
3984
3985 /** @name 32-bit Guest Paging.
3986 * @{ */
3987 /** The guest's page directory, R3 pointer. */
3988 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3989#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3990 /** The guest's page directory, R0 pointer. */
3991 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3992#endif
3993 /** The guest's page directory, static RC mapping. */
3994 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3995 /** Mask containing the MBZ bits of a big page PDE. */
3996 uint32_t fGst32BitMbzBigPdeMask;
3997 /** Set if the page size extension (PSE) is enabled. */
3998 bool fGst32BitPageSizeExtension;
3999 /** Alignment padding. */
4000 bool afAlignment2[3];
4001 /** @} */
4002
4003 /** @name PAE Guest Paging.
4004 * @{ */
4005 /** The guest's page directory pointer table, static RC mapping. */
4006 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
4007 /** The guest's page directory pointer table, R3 pointer. */
4008 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
4009#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4010 /** The guest's page directory pointer table, R0 pointer. */
4011 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
4012#endif
4013
4014 /** The guest's page directories, R3 pointers.
4015 * These are individual pointers and don't have to be adjacent.
4016 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4017 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
4018 /** The guest's page directories, R0 pointers.
4019 * Same restrictions as apGstPaePDsR3. */
4020#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4021 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
4022#endif
4023 /** The guest's page directories, static GC mapping.
4024 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
4025 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4026 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
4027 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
4028 * @todo Remove this and use aGstPaePdpeRegs instead? */
4029 RTGCPHYS aGCPhysGstPaePDs[4];
4030 /** The values of the 4 PDPE CPU registers (PAE). */
4031 X86PDPE aGstPaePdpeRegs[4];
4032 /** The physical addresses of the monitored guest page directories (PAE). */
4033 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
4034 /** Mask containing the MBZ PTE bits. */
4035 uint64_t fGstPaeMbzPteMask;
4036 /** Mask containing the MBZ PDE bits. */
4037 uint64_t fGstPaeMbzPdeMask;
4038 /** Mask containing the MBZ big page PDE bits. */
4039 uint64_t fGstPaeMbzBigPdeMask;
4040 /** Mask containing the MBZ PDPE bits. */
4041 uint64_t fGstPaeMbzPdpeMask;
4042 /** @} */
4043
4044 /** @name AMD64 Guest Paging.
4045 * @{ */
4046 /** The guest's page directory pointer table, R3 pointer. */
4047 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
4048#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4049 /** The guest's page directory pointer table, R0 pointer. */
4050 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
4051#else
4052 RTR0PTR alignment6b; /**< alignment equalizer. */
4053#endif
4054 /** Mask containing the MBZ PTE bits. */
4055 uint64_t fGstAmd64MbzPteMask;
4056 /** Mask containing the MBZ PDE bits. */
4057 uint64_t fGstAmd64MbzPdeMask;
4058 /** Mask containing the MBZ big page PDE bits. */
4059 uint64_t fGstAmd64MbzBigPdeMask;
4060 /** Mask containing the MBZ PDPE bits. */
4061 uint64_t fGstAmd64MbzPdpeMask;
4062 /** Mask containing the MBZ big page PDPE bits. */
4063 uint64_t fGstAmd64MbzBigPdpeMask;
4064 /** Mask containing the MBZ PML4E bits. */
4065 uint64_t fGstAmd64MbzPml4eMask;
4066 /** Mask containing the PDPE bits that we shadow. */
4067 uint64_t fGstAmd64ShadowedPdpeMask;
4068 /** Mask containing the PML4E bits that we shadow. */
4069 uint64_t fGstAmd64ShadowedPml4eMask;
4070 /** @} */
4071
4072 /** @name PAE and AMD64 Guest Paging.
4073 * @{ */
4074 /** Mask containing the PTE bits that we shadow. */
4075 uint64_t fGst64ShadowedPteMask;
4076 /** Mask containing the PDE bits that we shadow. */
4077 uint64_t fGst64ShadowedPdeMask;
4078 /** Mask containing the big page PDE bits that we shadow in the PDE. */
4079 uint64_t fGst64ShadowedBigPdeMask;
4080 /** Mask containing the big page PDE bits that we shadow in the PTE. */
4081 uint64_t fGst64ShadowedBigPde4PteMask;
4082 /** @} */
4083
4084 /** Pointer to the page of the current active CR3 - R3 Ptr. */
4085 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
4086 /** Pointer to the page of the current active CR3 - R0 Ptr. */
4087 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
4088 /** Pointer to the page of the current active CR3 - RC Ptr. */
4089 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
4090 /** Explicit alignment. */
4091 RTRCPTR alignment6;
4092 /** @} */
4093
4094 /** For saving stack space, the disassembler state is allocated here instead of
4095 * on the stack. */
4096 DISCPUSTATE DisState;
4097
4098 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4099 uint64_t cNetwareWp0Hacks;
4100
4101 /** Count the number of pgm pool access handler calls. */
4102 uint64_t cPoolAccessHandler;
4103
4104 /** @name Release Statistics
4105 * @{ */
4106 /** The number of times the guest has switched mode since last reset or statistics reset. */
4107 STAMCOUNTER cGuestModeChanges;
4108 /** The number of times the guest has switched mode since last reset or statistics reset. */
4109 STAMCOUNTER cA20Changes;
4110 /** @} */
4111
4112#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4113 /** @name Statistics
4114 * @{ */
4115 /** RC: Pointer to the statistics. */
4116 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4117 /** RC: Which statistic this \#PF should be attributed to. */
4118 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4119 /** R0: Pointer to the statistics. */
4120 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4121 /** R0: Which statistic this \#PF should be attributed to. */
4122 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4123 /** R3: Pointer to the statistics. */
4124 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4125 /** Alignment padding. */
4126 RTR3PTR pPaddingR3;
4127 /** @} */
4128#endif /* VBOX_WITH_STATISTICS */
4129} PGMCPU;
4130/** Pointer to the per-cpu PGM data. */
4131typedef PGMCPU *PPGMCPU;
4132
4133
4134/** @name PGM::fSyncFlags Flags
4135 * @note Was part of saved state a long time ago.
4136 * @{
4137 */
4138/** Updates the virtual access handler state bit in PGMPAGE. */
4139#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4140/** Always sync CR3. */
4141#define PGM_SYNC_ALWAYS RT_BIT(1)
4142/** Check monitoring on next CR3 (re)load and invalidate page.
4143 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4144#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4145/** Check guest mapping in SyncCR3. */
4146#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4147/** Clear the page pool (a light weight flush). */
4148#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4149#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4150/** @} */
4151
4152
4153RT_C_DECLS_BEGIN
4154
4155#if defined(VBOX_STRICT) && defined(IN_RING3)
4156int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4157# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4158#else
4159int pgmLock(PVM pVM);
4160#endif
4161void pgmUnlock(PVM pVM);
4162/**
4163 * Asserts that the caller owns the PDM lock.
4164 * This is the internal variant of PGMIsLockOwner.
4165 * @param a_pVM Pointer to the VM.
4166 */
4167#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4168/**
4169 * Asserts that the caller owns the PDM lock.
4170 * This is the internal variant of PGMIsLockOwner.
4171 * @param a_pVM Pointer to the VM.
4172 * @param a_pVCpu The current CPU handle.
4173 */
4174#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4175
4176#ifndef PGM_WITHOUT_MAPPINGS
4177int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4178int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4179int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4180int pgmMapResolveConflicts(PVM pVM);
4181#endif /* !PGM_WITHOUT_MAPPINGS */
4182PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4183DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4184
4185int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4186 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
4187int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4188int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4189int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4190int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4191void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4192bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4193void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4194#ifdef VBOX_WITH_RAW_MODE
4195PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4196DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4197# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4198void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4199# else
4200# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4201# endif
4202#endif /* VBOX_WITH_RAW_MODE */
4203DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4204int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4205
4206int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4207int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4208int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4209int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4210int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4211void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4212int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4213int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4214int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4215int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4216int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4217int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4218int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4219int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4220int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4221int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4222void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4223PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4224#ifndef IN_RING3
4225DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4226DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4227DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4228#endif
4229int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4230 PGMPAGETYPE enmNewType);
4231void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4232void pgmPhysInvalidatePageMapTLB(PVM pVM);
4233void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4234PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4235PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4236PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4237int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4238int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4239
4240#ifdef IN_RING3
4241void pgmR3PhysRelinkRamRanges(PVM pVM);
4242int pgmR3PhysRamPreAllocate(PVM pVM);
4243int pgmR3PhysRamReset(PVM pVM);
4244int pgmR3PhysRomReset(PVM pVM);
4245int pgmR3PhysRamZeroAll(PVM pVM);
4246int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4247int pgmR3PhysRamTerm(PVM pVM);
4248void pgmR3PhysRomTerm(PVM pVM);
4249void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4250
4251int pgmR3PoolInit(PVM pVM);
4252void pgmR3PoolRelocate(PVM pVM);
4253void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4254void pgmR3PoolReset(PVM pVM);
4255void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4256DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4257void pgmR3PoolWriteProtectPages(PVM pVM);
4258
4259#endif /* IN_RING3 */
4260#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4261int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4262int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4263# ifdef LOG_ENABLED
4264void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4265# else
4266void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4267# endif
4268#endif
4269int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4270 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4271void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4272void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4273int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4274void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4275PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4276PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4277int pgmPoolSyncCR3(PVMCPU pVCpu);
4278bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4279void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4280int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4281void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4282uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4283void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4284void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4285void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4286PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4287#ifndef IN_RING3
4288DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4289#endif
4290
4291void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4292void pgmPoolResetDirtyPages(PVM pVM);
4293void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4294
4295int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4296int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4297void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4298
4299void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4300void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4301int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4302int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4303
4304int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4305int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4306int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4307
4308int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4309int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4310int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4311int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4312int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4313int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4314
4315# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4316FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4317FNDBGCCMD pgmR3CmdShowSharedModules;
4318# endif
4319
4320void pgmLogState(PVM pVM);
4321
4322RT_C_DECLS_END
4323
4324/** @} */
4325
4326#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4327
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