PGMInternal.h@ 80163

Last change on this file since 80163 was 80163, checked in by vboxsync, 5 years ago
VMM: Kicking out raw-mode - PGM Virt Handlers, ++. bugref:9517
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1	/* $Id: PGMInternal.h 80163 2019-08-06 20:28:12Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/hm_vmx.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/avl.h>
43	#include <iprt/critsect.h>
44	#include <iprt/list-off32.h>
45	#include <iprt/sha.h>
46
47
48
49	/** @defgroup grp_pgm_int Internals
50	* @ingroup grp_pgm
51	* @internal
52	* @{
53	*/
54
55
56	/** @name PGM Compile Time Config
57	* @{
58	*/
59
60	/**
61	* Indicates that there are no guest mappings in the shadow tables.
62	*
63	* Note! In ring-3 the macro is also used to exclude the managment of the
64	* intermediate context page tables. On 32-bit systems we use the intermediate
65	* context to support 64-bit guest execution. Thus, we cannot fully make it
66	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67	*
68	* In raw-mode context there are by design always guest mappings (the code is
69	* executed from one), while in ring-0 there are none at all. Neither context
70	* manages the page tables for intermediate switcher context, that's all done in
71	* ring-3.
72	*
73	* Update 6.1: It is always defined now, in pgm.h
74	*/
75	#if defined(IN_RING0) \
76	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
77	&& ( HC_ARCH_BITS != 32 \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# undef PGM_WITHOUT_MAPPINGS
82	# define PGM_WITHOUT_MAPPINGS
83	#endif
84
85	/**
86	* Check and skip global PDEs for non-global flushes
87	*/
88	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90	/**
91	* Optimization for PAE page tables that are modified often
92	*/
93	//#if 0 /* disabled again while debugging */
94	#ifndef IN_RC
95	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
96	#endif
97	//#endif
98
99	/**
100	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
101	*/
102	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
103	# define PGM_WITH_LARGE_PAGES
104	#endif
105
106	/**
107	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
108	* VMX_EXIT_EPT_MISCONFIG.
109	*/
110	#if 1 /* testing */
111	# define PGM_WITH_MMIO_OPTIMIZATIONS
112	#endif
113
114	/**
115	* Sync N pages instead of a whole page table
116	*/
117	#define PGM_SYNC_N_PAGES
118
119	/**
120	* Number of pages to sync during a page fault
121	*
122	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
123	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
124	*
125	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
126	* world switch overhead, so let's sync more.
127	*/
128	# ifdef IN_RING0
129	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
130	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
131	* but ~5% fewer faults.
132	*/
133	# define PGM_SYNC_NR_PAGES 32
134	#else
135	# define PGM_SYNC_NR_PAGES 8
136	#endif
137
138	/**
139	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
140	*/
141	#define PGM_MAX_PHYSCACHE_ENTRIES 64
142	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
143
144
145	/** @def PGMPOOL_CFG_MAX_GROW
146	* The maximum number of pages to add to the pool in one go.
147	*/
148	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
149
150	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
151	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
152	*/
153	#ifdef VBOX_STRICT
154	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
155	#endif
156
157	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
158	* Enables the experimental lazy page allocation code. */
159	#ifdef DOXYGEN_RUNNING
160	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
161	#endif
162
163	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164	* Enables real write monitoring of pages, i.e. mapping them read-only and
165	* only making them writable when getting a write access \#PF. */
166	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
167
168	/** @} */
169
170
171	/** @name PDPT and PML4 flags.
172	* These are placed in the three bits available for system programs in
173	* the PDPT and PML4 entries.
174	* @{ */
175	/** The entry is a permanent one and it's must always be present.
176	* Never free such an entry. */
177	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
178	/** Mapping (hypervisor allocated pagetable). */
179	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
180	/** @} */
181
182	/** @name Page directory flags.
183	* These are placed in the three bits available for system programs in
184	* the page directory entries.
185	* @{ */
186	/** Indicates the original entry was a big page.
187	* @remarks This is currently only used for statistics and can be recycled. */
188	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
189	/** Mapping (hypervisor allocated pagetable). */
190	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
191	/** Made read-only to facilitate dirty bit tracking. */
192	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
193	/** @} */
194
195	/** @name Page flags.
196	* These are placed in the three bits available for system programs in
197	* the page entries.
198	* @{ */
199	/** Made read-only to facilitate dirty bit tracking. */
200	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
201
202	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
203	/** Scanned and approved by CSAM (tm).
204	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
205	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
206	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
207	#endif
208
209	/** @} */
210
211	/** @name Defines used to indicate the shadow and guest paging in the templates.
212	* @{ */
213	#define PGM_TYPE_REAL 1
214	#define PGM_TYPE_PROT 2
215	#define PGM_TYPE_32BIT 3
216	#define PGM_TYPE_PAE 4
217	#define PGM_TYPE_AMD64 5
218	#define PGM_TYPE_NESTED_32BIT 6
219	#define PGM_TYPE_NESTED_PAE 7
220	#define PGM_TYPE_NESTED_AMD64 8
221	#define PGM_TYPE_EPT 9
222	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
223	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
224	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
225	/** @} */
226
227	/** Macro for checking if the guest is using paging.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_PAGING(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_32BIT \
234	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
235
236	/** Macro for checking if the guest supports the NX bit.
237	* @param uGstType PGM_TYPE_*
238	* @param uShwType PGM_TYPE_*
239	* @remark ASSUMES certain order of the PGM_TYPE_* values.
240	*/
241	#define PGM_WITH_NX(uGstType, uShwType) \
242	( (uGstType) >= PGM_TYPE_PAE \
243	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
244
245	/** Macro for checking for nested or EPT.
246	* @param uType PGM_TYPE_*
247	*/
248	#define PGM_TYPE_IS_NESTED(uType) \
249	( (uType) == PGM_TYPE_NESTED_32BIT \
250	\|\| (uType) == PGM_TYPE_NESTED_PAE \
251	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
252
253	/** Macro for checking for nested or EPT.
254	* @param uType PGM_TYPE_*
255	*/
256	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
257	( (uType) == PGM_TYPE_NESTED_32BIT \
258	\|\| (uType) == PGM_TYPE_NESTED_PAE \
259	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
260	\|\| (uType) == PGM_TYPE_EPT)
261
262
263
264	/** @def PGM_HCPHYS_2_PTR
265	* Maps a HC physical page pool address to a virtual address.
266	*
267	* @returns VBox status code.
268	* @param pVM The cross context VM structure.
269	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
270	* @param HCPhys The HC physical address to map to a virtual one.
271	* @param ppv Where to store the virtual address. No need to cast
272	* this.
273	*
274	* @remark Use with care as we don't have so much dynamic mapping space in
275	* ring-0 on 32-bit darwin and in RC.
276	* @remark There is no need to assert on the result.
277	*/
278	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
279	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
280	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
281	#else
282	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
283	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
284	#endif
285
286	/** @def PGM_GCPHYS_2_PTR_V2
287	* Maps a GC physical page address to a virtual address.
288	*
289	* @returns VBox status code.
290	* @param pVM The cross context VM structure.
291	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
292	* @param GCPhys The GC physical address to map to a virtual one.
293	* @param ppv Where to store the virtual address. No need to cast this.
294	*
295	* @remark Use with care as we don't have so much dynamic mapping space in
296	* ring-0 on 32-bit darwin and in RC.
297	* @remark There is no need to assert on the result.
298	*/
299	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
300	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
301	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
302	#else
303	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
304	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
305	#endif
306
307	/** @def PGM_GCPHYS_2_PTR
308	* Maps a GC physical page address to a virtual address.
309	*
310	* @returns VBox status code.
311	* @param pVM The cross context VM structure.
312	* @param GCPhys The GC physical address to map to a virtual one.
313	* @param ppv Where to store the virtual address. No need to cast this.
314	*
315	* @remark Use with care as we don't have so much dynamic mapping space in
316	* ring-0 on 32-bit darwin and in RC.
317	* @remark There is no need to assert on the result.
318	*/
319	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
320
321	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
322	* Maps a GC physical page address to a virtual address.
323	*
324	* @returns VBox status code.
325	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
326	* @param GCPhys The GC physical address to map to a virtual one.
327	* @param ppv Where to store the virtual address. No need to cast this.
328	*
329	* @remark Use with care as we don't have so much dynamic mapping space in
330	* ring-0 on 32-bit darwin and in RC.
331	* @remark There is no need to assert on the result.
332	*/
333	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
334
335	/** @def PGM_GCPHYS_2_PTR_EX
336	* Maps a unaligned GC physical page address to a virtual address.
337	*
338	* @returns VBox status code.
339	* @param pVM The cross context VM structure.
340	* @param GCPhys The GC physical address to map to a virtual one.
341	* @param ppv Where to store the virtual address. No need to cast this.
342	*
343	* @remark Use with care as we don't have so much dynamic mapping space in
344	* ring-0 on 32-bit darwin and in RC.
345	* @remark There is no need to assert on the result.
346	*/
347	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
348	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
349	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
350	#else
351	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
352	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
353	#endif
354
355	/** @def PGM_DYNMAP_UNUSED_HINT
356	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
357	* is no longer used.
358	*
359	* For best effect only apply this to the page that was mapped most recently.
360	*
361	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
362	* @param pvPage The pool page.
363	*/
364	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
365	# ifdef LOG_ENABLED
366	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
367	# else
368	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
369	# endif
370	#else
371	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
372	#endif
373
374	/** @def PGM_DYNMAP_UNUSED_HINT_VM
375	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
376	* is no longer used.
377	*
378	* For best effect only apply this to the page that was mapped most recently.
379	*
380	* @param pVM The cross context VM structure.
381	* @param pvPage The pool page.
382	*/
383	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
384
385
386	/** @def PGM_INVL_PG
387	* Invalidates a page.
388	*
389	* @param pVCpu The cross context virtual CPU structure.
390	* @param GCVirt The virtual address of the page to invalidate.
391	*/
392	#ifdef IN_RC
393	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
394	#elif defined(IN_RING0)
395	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
396	#else
397	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
398	#endif
399
400	/** @def PGM_INVL_PG_ALL_VCPU
401	* Invalidates a page on all VCPUs
402	*
403	* @param pVM The cross context VM structure.
404	* @param GCVirt The virtual address of the page to invalidate.
405	*/
406	#ifdef IN_RC
407	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
408	#elif defined(IN_RING0)
409	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
410	#else
411	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
412	#endif
413
414	/** @def PGM_INVL_BIG_PG
415	* Invalidates a 4MB page directory entry.
416	*
417	* @param pVCpu The cross context virtual CPU structure.
418	* @param GCVirt The virtual address within the page directory to invalidate.
419	*/
420	#ifdef IN_RC
421	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
422	#elif defined(IN_RING0)
423	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
424	#else
425	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
426	#endif
427
428	/** @def PGM_INVL_VCPU_TLBS()
429	* Invalidates the TLBs of the specified VCPU
430	*
431	* @param pVCpu The cross context virtual CPU structure.
432	*/
433	#ifdef IN_RC
434	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
435	#elif defined(IN_RING0)
436	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
437	#else
438	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
439	#endif
440
441	/** @def PGM_INVL_ALL_VCPU_TLBS()
442	* Invalidates the TLBs of all VCPUs
443	*
444	* @param pVM The cross context VM structure.
445	*/
446	#ifdef IN_RC
447	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
448	#elif defined(IN_RING0)
449	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
450	#else
451	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
452	#endif
453
454
455	/** @name Safer Shadow PAE PT/PTE
456	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
457	* present.
458	*
459	* @{
460	*/
461	#if 1
462	/**
463	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
464	* invalid entries for present.
465	* @sa X86PTEPAE.
466	*/
467	typedef union PGMSHWPTEPAE
468	{
469	/** Unsigned integer view */
470	X86PGPAEUINT uCareful;
471	/* Not other views. */
472	} PGMSHWPTEPAE;
473
474	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
475	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
476	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
477	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
478	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
479	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
480	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
481	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
482	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
483	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
484	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
485	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
486	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
487	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
488	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
489	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
490
491	/**
492	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
493	* invalid entries for present.
494	* @sa X86PTPAE.
495	*/
496	typedef struct PGMSHWPTPAE
497	{
498	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
499	} PGMSHWPTPAE;
500
501	#else
502	typedef X86PTEPAE PGMSHWPTEPAE;
503	typedef X86PTPAE PGMSHWPTPAE;
504	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
505	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
506	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
507	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
508	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
509	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
510	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
511	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
512	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
513	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
514	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
515	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
516	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
517	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
518	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
519	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
520
521	#endif
522
523	/** Pointer to a shadow PAE PTE. */
524	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
525	/** Pointer to a const shadow PAE PTE. */
526	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
527
528	/** Pointer to a shadow PAE page table. */
529	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
530	/** Pointer to a const shadow PAE page table. */
531	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
532	/** @} */
533
534	#ifndef PGM_WITHOUT_MAPPINGS
535
536	/** Size of the GCPtrConflict array in PGMMAPPING.
537	* @remarks Must be a power of two. */
538	# define PGMMAPPING_CONFLICT_MAX 8
539
540	/**
541	* Structure for tracking GC Mappings.
542	*
543	* This structure is used by linked list in both GC and HC.
544	*/
545	typedef struct PGMMAPPING
546	{
547	/** Pointer to next entry. */
548	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
549	/** Pointer to next entry. */
550	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
551	/** Pointer to next entry. */
552	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
553	/** Indicate whether this entry is finalized. */
554	bool fFinalized;
555	/** Start Virtual address. */
556	RTGCPTR GCPtr;
557	/** Last Virtual address (inclusive). */
558	RTGCPTR GCPtrLast;
559	/** Range size (bytes). */
560	RTGCPTR cb;
561	/** Pointer to relocation callback function. */
562	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
563	/** User argument to the callback. */
564	R3PTRTYPE(void *) pvUser;
565	/** Mapping description / name. For easing debugging. */
566	R3PTRTYPE(const char *) pszDesc;
567	/** Last 8 addresses that caused conflicts. */
568	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
569	/** Number of conflicts for this hypervisor mapping. */
570	uint32_t cConflicts;
571	/** Number of page tables. */
572	uint32_t cPTs;
573
574	/** Array of page table mapping data. Each entry
575	* describes one page table. The array can be longer
576	* than the declared length.
577	*/
578	struct
579	{
580	/** The HC physical address of the page table. */
581	RTHCPHYS HCPhysPT;
582	/** The HC physical address of the first PAE page table. */
583	RTHCPHYS HCPhysPaePT0;
584	/** The HC physical address of the second PAE page table. */
585	RTHCPHYS HCPhysPaePT1;
586	/** The HC virtual address of the 32-bit page table. */
587	R3PTRTYPE(PX86PT) pPTR3;
588	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
589	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
590	/** The RC virtual address of the 32-bit page table. */
591	RCPTRTYPE(PX86PT) pPTRC;
592	/** The RC virtual address of the two PAE page table. */
593	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
594	/** The R0 virtual address of the 32-bit page table. */
595	R0PTRTYPE(PX86PT) pPTR0;
596	/** The R0 virtual address of the two PAE page table. */
597	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
598	} aPTs[1];
599	} PGMMAPPING;
600	/** Pointer to structure for tracking GC Mappings. */
601	typedef struct PGMMAPPING *PPGMMAPPING;
602
603	#endif /* !PGM_WITHOUT_MAPPINGS */
604
605
606	/**
607	* Physical page access handler type registration.
608	*/
609	typedef struct PGMPHYSHANDLERTYPEINT
610	{
611	/** Number of references. */
612	uint32_t volatile cRefs;
613	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
614	uint32_t u32Magic;
615	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
616	RTLISTOFF32NODE ListNode;
617	/** The kind of accesses we're handling. */
618	PGMPHYSHANDLERKIND enmKind;
619	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
620	uint32_t uState;
621	/** Pointer to RC callback function. */
622	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
623	/** Pointer to RC callback function for \#PFs. */
624	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
625	/** Pointer to R3 callback function. */
626	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
627	/** Pointer to R0 callback function. */
628	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
629	/** Pointer to R0 callback function for \#PFs. */
630	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
631	/** Description / Name. For easing debugging. */
632	R3PTRTYPE(const char *) pszDesc;
633	} PGMPHYSHANDLERTYPEINT;
634	/** Pointer to a physical access handler type registration. */
635	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
636	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
637	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
638	/** Magic value for the physical handler callbacks. */
639	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
640
641	/**
642	* Converts a handle to a pointer.
643	* @returns PPGMPHYSHANDLERTYPEINT
644	* @param a_pVM The cross context VM structure.
645	* @param a_hType Physical access handler type handle.
646	*/
647	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
648
649
650	/**
651	* Physical page access handler structure.
652	*
653	* This is used to keep track of physical address ranges
654	* which are being monitored in some kind of way.
655	*/
656	typedef struct PGMPHYSHANDLER
657	{
658	AVLROGCPHYSNODECORE Core;
659	/** Number of pages to update. */
660	uint32_t cPages;
661	/** Set if we have pages that have been aliased. */
662	uint32_t cAliasedPages;
663	/** Set if we have pages that have temporarily been disabled. */
664	uint32_t cTmpOffPages;
665	/** Registered handler type handle (heap offset). */
666	PGMPHYSHANDLERTYPE hType;
667	/** User argument for RC handlers. */
668	RCPTRTYPE(void *) pvUserRC;
669	#if HC_ARCH_BITS == 64
670	RTRCPTR Padding0; /*< Explicit alignment padding. /
671	#endif
672	/** User argument for R3 handlers. */
673	R3PTRTYPE(void *) pvUserR3;
674	/** User argument for R0 handlers. */
675	R0PTRTYPE(void *) pvUserR0;
676	/** Description / Name. For easing debugging. */
677	R3PTRTYPE(const char *) pszDesc;
678	#ifdef VBOX_WITH_STATISTICS
679	/** Profiling of this handler. */
680	STAMPROFILE Stat;
681	#endif
682	} PGMPHYSHANDLER;
683	/** Pointer to a physical page access handler structure. */
684	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
685
686	/**
687	* Gets the type record for a physical handler (no reference added).
688	* @returns PPGMPHYSHANDLERTYPEINT
689	* @param a_pVM The cross context VM structure.
690	* @param a_pPhysHandler Pointer to the physical handler structure
691	* (PGMPHYSHANDLER).
692	*/
693	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
694
695
696	/**
697	* A Physical Guest Page tracking structure.
698	*
699	* The format of this structure is complicated because we have to fit a lot
700	* of information into as few bits as possible. The format is also subject
701	* to change (there is one coming up soon). Which means that for we'll be
702	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
703	* accesses to the structure.
704	*/
705	typedef union PGMPAGE
706	{
707	/** Structured view. */
708	struct
709	{
710	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
711	uint64_t u2HandlerPhysStateY : 2;
712	/** 3:2 - Paging structure needed to map the page
713	* (PGM_PAGE_PDE_TYPE_). /
714	uint64_t u2PDETypeY : 2;
715	/** 4 - Unused (was used by FTE for dirty tracking). */
716	uint64_t fUnused1 : 1;
717	/** 5 - Flag indicating that a write monitored page was written to
718	* when set. */
719	uint64_t fWrittenToY : 1;
720	/** 7:6 - Unused. */
721	uint64_t u2Unused0 : 2;
722	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
723	uint64_t u2Unused1 : 2;
724	/** 11:10 - NEM state bits. */
725	uint64_t u2NemStateY : 2;
726	/** 12:48 - The host physical frame number (shift left to get the
727	* address). */
728	uint64_t HCPhysFN : 36;
729	/** 50:48 - The page state. */
730	uint64_t uStateY : 3;
731	/** 51:53 - The page type (PGMPAGETYPE). */
732	uint64_t uTypeY : 3;
733	/** 63:54 - PTE index for usage tracking (page pool). */
734	uint64_t u10PteIdx : 10;
735
736	/** The GMM page ID.
737	* @remarks In the current implementation, MMIO2 and pages aliased to
738	* MMIO2 pages will be exploiting this field to calculate the
739	* ring-3 mapping address corresponding to the page.
740	* Later we may consider including MMIO2 management into GMM. */
741	uint32_t idPage;
742	/** Usage tracking (page pool). */
743	uint16_t u16TrackingY;
744	/** The number of read locks on this page. */
745	uint8_t cReadLocksY;
746	/** The number of write locks on this page. */
747	uint8_t cWriteLocksY;
748	} s;
749
750	/** 64-bit integer view. */
751	uint64_t au64[2];
752	/** 16-bit view. */
753	uint32_t au32[4];
754	/** 16-bit view. */
755	uint16_t au16[8];
756	/** 8-bit view. */
757	uint8_t au8[16];
758	} PGMPAGE;
759	AssertCompileSize(PGMPAGE, 16);
760	/** Pointer to a physical guest page. */
761	typedef PGMPAGE *PPGMPAGE;
762	/** Pointer to a const physical guest page. */
763	typedef const PGMPAGE *PCPGMPAGE;
764	/** Pointer to a physical guest page pointer. */
765	typedef PPGMPAGE *PPPGMPAGE;
766
767
768	/**
769	* Clears the page structure.
770	* @param a_pPage Pointer to the physical guest page tracking structure.
771	*/
772	#define PGM_PAGE_CLEAR(a_pPage) \
773	do { \
774	(a_pPage)->au64[0] = 0; \
775	(a_pPage)->au64[1] = 0; \
776	} while (0)
777
778	/**
779	* Initializes the page structure.
780	* @param a_pPage Pointer to the physical guest page tracking structure.
781	* @param a_HCPhys The host physical address of the page.
782	* @param a_idPage The (GMM) page ID of the page.
783	* @param a_uType The page type (PGMPAGETYPE).
784	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
785	*/
786	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
787	do { \
788	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
789	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
790	(a_pPage)->au64[0] = SetHCPhysTmp; \
791	(a_pPage)->au64[1] = 0; \
792	(a_pPage)->s.idPage = (a_idPage); \
793	(a_pPage)->s.uStateY = (a_uState); \
794	(a_pPage)->s.uTypeY = (a_uType); \
795	} while (0)
796
797	/**
798	* Initializes the page structure of a ZERO page.
799	* @param a_pPage Pointer to the physical guest page tracking structure.
800	* @param a_pVM The VM handle (for getting the zero page address).
801	* @param a_uType The page type (PGMPAGETYPE).
802	*/
803	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
804	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
805
806
807	/** @name The Page state, PGMPAGE::uStateY.
808	* @{ */
809	/** The zero page.
810	* This is a per-VM page that's never ever mapped writable. */
811	#define PGM_PAGE_STATE_ZERO 0U
812	/** A allocated page.
813	* This is a per-VM page allocated from the page pool (or wherever
814	* we get MMIO2 pages from if the type is MMIO2).
815	*/
816	#define PGM_PAGE_STATE_ALLOCATED 1U
817	/** A allocated page that's being monitored for writes.
818	* The shadow page table mappings are read-only. When a write occurs, the
819	* fWrittenTo member is set, the page remapped as read-write and the state
820	* moved back to allocated. */
821	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
822	/** The page is shared, aka. copy-on-write.
823	* This is a page that's shared with other VMs. */
824	#define PGM_PAGE_STATE_SHARED 3U
825	/** The page is ballooned, so no longer available for this VM. */
826	#define PGM_PAGE_STATE_BALLOONED 4U
827	/** @} */
828
829
830	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
831	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
832	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
833	#else
834	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
835	#endif
836
837	/**
838	* Gets the page state.
839	* @returns page state (PGM_PAGE_STATE_*).
840	* @param a_pPage Pointer to the physical guest page tracking structure.
841	*
842	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
843	* builds.
844	*/
845	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
846	#if defined(__GNUC__) && defined(VBOX_STRICT)
847	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
848	#else
849	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
850	#endif
851
852	/**
853	* Sets the page state.
854	* @param a_pVM The VM handle, only used for lock ownership assertions.
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	* @param a_uState The new page state.
857	*/
858	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
859	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
860
861
862	/**
863	* Gets the host physical address of the guest page.
864	* @returns host physical address (RTHCPHYS).
865	* @param a_pPage Pointer to the physical guest page tracking structure.
866	*
867	* @remarks In strict builds on gcc platforms, this macro will make some ugly
868	* assumption about a valid pVM variable/parameter being in the
869	* current context. It will use this pVM variable to assert that the
870	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
871	* pVM is not around.
872	*/
873	#if 0
874	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
875	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
876	#else
877	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
878	# if defined(__GNUC__) && defined(VBOX_STRICT)
879	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
880	# else
881	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
882	# endif
883	#endif
884
885	/**
886	* Sets the host physical address of the guest page.
887	*
888	* @param a_pVM The VM handle, only used for lock ownership assertions.
889	* @param a_pPage Pointer to the physical guest page tracking structure.
890	* @param a_HCPhys The new host physical address.
891	*/
892	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
893	do { \
894	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
895	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
896	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
897	PGM_PAGE_ASSERT_LOCK(a_pVM); \
898	} while (0)
899
900	/**
901	* Get the Page ID.
902	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
903	* @param a_pPage Pointer to the physical guest page tracking structure.
904	*/
905	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
906
907	/**
908	* Sets the Page ID.
909	* @param a_pVM The VM handle, only used for lock ownership assertions.
910	* @param a_pPage Pointer to the physical guest page tracking structure.
911	* @param a_idPage The new page ID.
912	*/
913	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
914	do { \
915	(a_pPage)->s.idPage = (a_idPage); \
916	PGM_PAGE_ASSERT_LOCK(a_pVM); \
917	} while (0)
918
919	/**
920	* Get the Chunk ID.
921	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
922	* @param a_pPage Pointer to the physical guest page tracking structure.
923	*/
924	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
925
926	/**
927	* Get the index of the page within the allocation chunk.
928	* @returns The page index.
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*/
931	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
932
933	/**
934	* Gets the page type.
935	* @returns The page type.
936	* @param a_pPage Pointer to the physical guest page tracking structure.
937	*
938	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
939	* builds.
940	*/
941	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
942	#if defined(__GNUC__) && defined(VBOX_STRICT)
943	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
944	#else
945	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
946	#endif
947
948	/**
949	* Sets the page type.
950	*
951	* @param a_pVM The VM handle, only used for lock ownership assertions.
952	* @param a_pPage Pointer to the physical guest page tracking structure.
953	* @param a_enmType The new page type (PGMPAGETYPE).
954	*/
955	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
956	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
957
958	/**
959	* Gets the page table index
960	* @returns The page table index.
961	* @param a_pPage Pointer to the physical guest page tracking structure.
962	*/
963	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
964
965	/**
966	* Sets the page table index.
967	* @param a_pVM The VM handle, only used for lock ownership assertions.
968	* @param a_pPage Pointer to the physical guest page tracking structure.
969	* @param a_iPte New page table index.
970	*/
971	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
972	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
973
974	/**
975	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
976	* @returns true/false.
977	* @param a_pPage Pointer to the physical guest page tracking structure.
978	*/
979	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
980
981	/**
982	* Checks if the page is marked for MMIO, including both aliases.
983	* @returns true/false.
984	* @param a_pPage Pointer to the physical guest page tracking structure.
985	*/
986	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
987	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
988	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
989	)
990
991	/**
992	* Checks if the page is marked for MMIO, including special aliases.
993	* @returns true/false.
994	* @param a_pPage Pointer to the physical guest page tracking structure.
995	*/
996	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
997	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
998
999	/**
1000	* Checks if the page is a special aliased MMIO page.
1001	* @returns true/false.
1002	* @param a_pPage Pointer to the physical guest page tracking structure.
1003	*/
1004	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1005
1006	/**
1007	* Checks if the page is backed by the ZERO page.
1008	* @returns true/false.
1009	* @param a_pPage Pointer to the physical guest page tracking structure.
1010	*/
1011	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1012
1013	/**
1014	* Checks if the page is backed by a SHARED page.
1015	* @returns true/false.
1016	* @param a_pPage Pointer to the physical guest page tracking structure.
1017	*/
1018	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1019
1020	/**
1021	* Checks if the page is ballooned.
1022	* @returns true/false.
1023	* @param a_pPage Pointer to the physical guest page tracking structure.
1024	*/
1025	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1026
1027	/**
1028	* Checks if the page is allocated.
1029	* @returns true/false.
1030	* @param a_pPage Pointer to the physical guest page tracking structure.
1031	*/
1032	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1033
1034	/**
1035	* Marks the page as written to (for GMM change monitoring).
1036	* @param a_pVM The VM handle, only used for lock ownership assertions.
1037	* @param a_pPage Pointer to the physical guest page tracking structure.
1038	*/
1039	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1040	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1041
1042	/**
1043	* Clears the written-to indicator.
1044	* @param a_pVM The VM handle, only used for lock ownership assertions.
1045	* @param a_pPage Pointer to the physical guest page tracking structure.
1046	*/
1047	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1048	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1049
1050	/**
1051	* Checks if the page was marked as written-to.
1052	* @returns true/false.
1053	* @param a_pPage Pointer to the physical guest page tracking structure.
1054	*/
1055	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1056
1057
1058	/** @name PT usage values (PGMPAGE::u2PDEType).
1059	*
1060	* @{ */
1061	/** Either as a PT or PDE. */
1062	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1063	/** Must use a page table to map the range. */
1064	#define PGM_PAGE_PDE_TYPE_PT 1
1065	/** Can use a page directory entry to map the continuous range. */
1066	#define PGM_PAGE_PDE_TYPE_PDE 2
1067	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1068	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1069	/** @} */
1070
1071	/**
1072	* Set the PDE type of the page
1073	* @param a_pVM The VM handle, only used for lock ownership assertions.
1074	* @param a_pPage Pointer to the physical guest page tracking structure.
1075	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1076	*/
1077	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1078	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1079
1080	/**
1081	* Checks if the page was marked being part of a large page
1082	* @returns true/false.
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1086
1087	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1088	*
1089	* @remarks The values are assigned in order of priority, so we can calculate
1090	* the correct state for a page with different handlers installed.
1091	* @{ */
1092	/** No handler installed. */
1093	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1094	/** Monitoring is temporarily disabled. */
1095	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1096	/** Write access is monitored. */
1097	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1098	/** All access is monitored. */
1099	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1100	/** @} */
1101
1102	/**
1103	* Gets the physical access handler state of a page.
1104	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1105	* @param a_pPage Pointer to the physical guest page tracking structure.
1106	*/
1107	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1108
1109	/**
1110	* Sets the physical access handler state of a page.
1111	* @param a_pPage Pointer to the physical guest page tracking structure.
1112	* @param a_uState The new state value.
1113	*/
1114	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1115	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1116
1117	/**
1118	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1119	* @returns true/false
1120	* @param a_pPage Pointer to the physical guest page tracking structure.
1121	*/
1122	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1123	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1124
1125	/**
1126	* Checks if the page has any active physical access handlers.
1127	* @returns true/false
1128	* @param a_pPage Pointer to the physical guest page tracking structure.
1129	*/
1130	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1131	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1132
1133
1134	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1135	*
1136	* @remarks The values are assigned in order of priority, so we can calculate
1137	* the correct state for a page with different handlers installed.
1138	* @{ */
1139	/** No handler installed. */
1140	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1141	/* 1 is reserved so the lineup is identical with the physical ones. */
1142	/** Write access is monitored. */
1143	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1144	/** All access is monitored. */
1145	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1146	/** @} */
1147
1148	/**
1149	* Gets the virtual access handler state of a page.
1150	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1151	* @param a_pPage Pointer to the physical guest page tracking structure.
1152	*/
1153	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1154
1155	/**
1156	* Sets the virtual access handler state of a page.
1157	* @param a_pPage Pointer to the physical guest page tracking structure.
1158	* @param a_uState The new state value.
1159	*/
1160	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1161	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1162
1163	/**
1164	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1165	* virtual handlers.
1166	* @returns true/false
1167	* @param a_pPage Pointer to the physical guest page tracking structure.
1168	*/
1169	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1170	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1171
1172
1173	/**
1174	* Checks if the page has any access handlers, including temporarily disabled ones.
1175	* @returns true/false
1176	* @param a_pPage Pointer to the physical guest page tracking structure.
1177	*/
1178	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1179	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1180
1181	/**
1182	* Checks if the page has any active access handlers.
1183	* @returns true/false
1184	* @param a_pPage Pointer to the physical guest page tracking structure.
1185	*/
1186	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1187	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1188
1189	/**
1190	* Checks if the page has any active access handlers catching all accesses.
1191	* @returns true/false
1192	* @param a_pPage Pointer to the physical guest page tracking structure.
1193	*/
1194	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1195	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1196
1197
1198	/** @def PGM_PAGE_GET_TRACKING
1199	* Gets the packed shadow page pool tracking data associated with a guest page.
1200	* @returns uint16_t containing the data.
1201	* @param a_pPage Pointer to the physical guest page tracking structure.
1202	*/
1203	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1204	#if defined(__GNUC__) && defined(VBOX_STRICT)
1205	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1206	#else
1207	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1208	#endif
1209
1210	/** @def PGM_PAGE_SET_TRACKING
1211	* Sets the packed shadow page pool tracking data associated with a guest page.
1212	* @param a_pVM The VM handle, only used for lock ownership assertions.
1213	* @param a_pPage Pointer to the physical guest page tracking structure.
1214	* @param a_u16TrackingData The tracking data to store.
1215	*/
1216	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1217	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1218
1219	/** @def PGM_PAGE_GET_TD_CREFS
1220	* Gets the @a cRefs tracking data member.
1221	* @returns cRefs.
1222	* @param a_pPage Pointer to the physical guest page tracking structure.
1223	*/
1224	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1225	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1226	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1227	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1228
1229	/** @def PGM_PAGE_GET_TD_IDX
1230	* Gets the @a idx tracking data member.
1231	* @returns idx.
1232	* @param a_pPage Pointer to the physical guest page tracking structure.
1233	*/
1234	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1235	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1236	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1237	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1238
1239
1240	/** Max number of locks on a page. */
1241	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1242
1243	/** Get the read lock count.
1244	* @returns count.
1245	* @param a_pPage Pointer to the physical guest page tracking structure.
1246	*/
1247	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1248
1249	/** Get the write lock count.
1250	* @returns count.
1251	* @param a_pPage Pointer to the physical guest page tracking structure.
1252	*/
1253	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1254
1255	/** Decrement the read lock counter.
1256	* @param a_pPage Pointer to the physical guest page tracking structure.
1257	*/
1258	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1259
1260	/** Decrement the write lock counter.
1261	* @param a_pPage Pointer to the physical guest page tracking structure.
1262	*/
1263	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1264
1265	/** Increment the read lock counter.
1266	* @param a_pPage Pointer to the physical guest page tracking structure.
1267	*/
1268	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1269
1270	/** Increment the write lock counter.
1271	* @param a_pPage Pointer to the physical guest page tracking structure.
1272	*/
1273	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1274
1275
1276	/** Gets the NEM state.
1277	* @returns NEM state value (two bits).
1278	* @param a_pPage Pointer to the physical guest page tracking structure.
1279	*/
1280	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1281
1282	/** Sets the NEM state.
1283	* @param a_pPage Pointer to the physical guest page tracking structure.
1284	* @param a_u2State The NEM state value (specific to NEM impl.).
1285	*/
1286	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1287	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1288
1289
1290	#if 0
1291	/** Enables sanity checking of write monitoring using CRC-32. */
1292	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1293	#endif
1294
1295	/**
1296	* Per page live save tracking data.
1297	*/
1298	typedef struct PGMLIVESAVERAMPAGE
1299	{
1300	/** Number of times it has been dirtied. */
1301	uint32_t cDirtied : 24;
1302	/** Whether it is currently dirty. */
1303	uint32_t fDirty : 1;
1304	/** Ignore the page.
1305	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1306	* deal with these after pausing the VM and DevPCI have said it bit about
1307	* remappings. */
1308	uint32_t fIgnore : 1;
1309	/** Was a ZERO page last time around. */
1310	uint32_t fZero : 1;
1311	/** Was a SHARED page last time around. */
1312	uint32_t fShared : 1;
1313	/** Whether the page is/was write monitored in a previous pass. */
1314	uint32_t fWriteMonitored : 1;
1315	/** Whether the page is/was write monitored earlier in this pass. */
1316	uint32_t fWriteMonitoredJustNow : 1;
1317	/** Bits reserved for future use. */
1318	uint32_t u2Reserved : 2;
1319	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1320	/** CRC-32 for the page. This is for internal consistency checks. */
1321	uint32_t u32Crc;
1322	#endif
1323	} PGMLIVESAVERAMPAGE;
1324	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1325	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1326	#else
1327	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1328	#endif
1329	/** Pointer to the per page live save tracking data. */
1330	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1331
1332	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1333	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1334
1335
1336	/**
1337	* RAM range for GC Phys to HC Phys conversion.
1338	*
1339	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1340	* conversions too, but we'll let MM handle that for now.
1341	*
1342	* This structure is used by linked lists in both GC and HC.
1343	*/
1344	typedef struct PGMRAMRANGE
1345	{
1346	/** Start of the range. Page aligned. */
1347	RTGCPHYS GCPhys;
1348	/** Size of the range. (Page aligned of course). */
1349	RTGCPHYS cb;
1350	/** Pointer to the next RAM range - for R3. */
1351	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1352	/** Pointer to the next RAM range - for R0. */
1353	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1354	/** Pointer to the next RAM range - for RC. */
1355	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1356	/** PGM_RAM_RANGE_FLAGS_* flags. */
1357	uint32_t fFlags;
1358	/** Last address in the range (inclusive). Page aligned (-1). */
1359	RTGCPHYS GCPhysLast;
1360	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1361	R3PTRTYPE(void *) pvR3;
1362	/** Live save per page tracking data. */
1363	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1364	/** The range description. */
1365	R3PTRTYPE(const char *) pszDesc;
1366	/** Pointer to self - R0 pointer. */
1367	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1368	/** Pointer to self - RC pointer. */
1369	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1370
1371	/** Alignment padding. */
1372	RTRCPTR Alignment0;
1373	/** Pointer to the left search three node - ring-3 context. */
1374	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1375	/** Pointer to the right search three node - ring-3 context. */
1376	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1377	/** Pointer to the left search three node - ring-0 context. */
1378	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1379	/** Pointer to the right search three node - ring-0 context. */
1380	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1381	/** Pointer to the left search three node - raw-mode context. */
1382	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1383	/** Pointer to the right search three node - raw-mode context. */
1384	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1385
1386	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1387	#if HC_ARCH_BITS == 32
1388	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1389	#endif
1390	/** Array of physical guest page tracking structures. */
1391	PGMPAGE aPages[1];
1392	} PGMRAMRANGE;
1393	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1394	typedef PGMRAMRANGE *PPGMRAMRANGE;
1395
1396	/** @name PGMRAMRANGE::fFlags
1397	* @{ */
1398	/** The RAM range is floating around as an independent guest mapping. */
1399	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1400	/** Ad hoc RAM range for an ROM mapping. */
1401	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1402	/** Ad hoc RAM range for an MMIO mapping. */
1403	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1404	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1405	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1406	/** @} */
1407
1408	/** Tests if a RAM range is an ad hoc one or not.
1409	* @returns true/false.
1410	* @param pRam The RAM range.
1411	*/
1412	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1413	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1414
1415	/** The number of entries in the RAM range TLBs (there is one for each
1416	* context). Must be a power of two. */
1417	#define PGM_RAMRANGE_TLB_ENTRIES 8
1418
1419	/**
1420	* Calculates the RAM range TLB index for the physical address.
1421	*
1422	* @returns RAM range TLB index.
1423	* @param a_GCPhys The guest physical address.
1424	*/
1425	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1426
1427
1428
1429	/**
1430	* Per page tracking structure for ROM image.
1431	*
1432	* A ROM image may have a shadow page, in which case we may have two pages
1433	* backing it. This structure contains the PGMPAGE for both while
1434	* PGMRAMRANGE have a copy of the active one. It is important that these
1435	* aren't out of sync in any regard other than page pool tracking data.
1436	*/
1437	typedef struct PGMROMPAGE
1438	{
1439	/** The page structure for the virgin ROM page. */
1440	PGMPAGE Virgin;
1441	/** The page structure for the shadow RAM page. */
1442	PGMPAGE Shadow;
1443	/** The current protection setting. */
1444	PGMROMPROT enmProt;
1445	/** Live save status information. Makes use of unused alignment space. */
1446	struct
1447	{
1448	/** The previous protection value. */
1449	uint8_t u8Prot;
1450	/** Written to flag set by the handler. */
1451	bool fWrittenTo;
1452	/** Whether the shadow page is dirty or not. */
1453	bool fDirty;
1454	/** Whether it was dirtied in the recently. */
1455	bool fDirtiedRecently;
1456	} LiveSave;
1457	} PGMROMPAGE;
1458	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1459	/** Pointer to a ROM page tracking structure. */
1460	typedef PGMROMPAGE *PPGMROMPAGE;
1461
1462
1463	/**
1464	* A registered ROM image.
1465	*
1466	* This is needed to keep track of ROM image since they generally intrude
1467	* into a PGMRAMRANGE. It also keeps track of additional info like the
1468	* two page sets (read-only virgin and read-write shadow), the current
1469	* state of each page.
1470	*
1471	* Because access handlers cannot easily be executed in a different
1472	* context, the ROM ranges needs to be accessible and in all contexts.
1473	*/
1474	typedef struct PGMROMRANGE
1475	{
1476	/** Pointer to the next range - R3. */
1477	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1478	/** Pointer to the next range - R0. */
1479	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1480	/** Pointer to the next range - RC. */
1481	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1482	/** Pointer alignment */
1483	RTRCPTR RCPtrAlignment;
1484	/** Address of the range. */
1485	RTGCPHYS GCPhys;
1486	/** Address of the last byte in the range. */
1487	RTGCPHYS GCPhysLast;
1488	/** Size of the range. */
1489	RTGCPHYS cb;
1490	/** The flags (PGMPHYS_ROM_FLAGS_). /
1491	uint32_t fFlags;
1492	/** The saved state range ID. */
1493	uint8_t idSavedState;
1494	/** Alignment padding. */
1495	uint8_t au8Alignment[3];
1496	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1497	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1498	/** The size bits pvOriginal points to. */
1499	uint32_t cbOriginal;
1500	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1501	* This is used for strictness checks. */
1502	R3PTRTYPE(const void *) pvOriginal;
1503	/** The ROM description. */
1504	R3PTRTYPE(const char *) pszDesc;
1505	/** The per page tracking structures. */
1506	PGMROMPAGE aPages[1];
1507	} PGMROMRANGE;
1508	/** Pointer to a ROM range. */
1509	typedef PGMROMRANGE *PPGMROMRANGE;
1510
1511
1512	/**
1513	* Live save per page data for an MMIO2 page.
1514	*
1515	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1516	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1517	* CRC-32 for detecting changes as well as special handling of zero pages. This
1518	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1519	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1520	* because of speed (2.5x and 6x slower).)
1521	*
1522	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1523	* save but normally is disabled. Since we can write monitor guest
1524	* accesses on our own, we only need this for host accesses. Shouldn't be
1525	* too difficult for DevVGA, VMMDev might be doable, the planned
1526	* networking fun will be fun since it involves ring-0.
1527	*/
1528	typedef struct PGMLIVESAVEMMIO2PAGE
1529	{
1530	/** Set if the page is considered dirty. */
1531	bool fDirty;
1532	/** The number of scans this page has remained unchanged for.
1533	* Only updated for dirty pages. */
1534	uint8_t cUnchangedScans;
1535	/** Whether this page was zero at the last scan. */
1536	bool fZero;
1537	/** Alignment padding. */
1538	bool fReserved;
1539	/** CRC-32 for the first half of the page.
1540	* This is used together with u32CrcH2 to quickly detect changes in the page
1541	* during the non-final passes. */
1542	uint32_t u32CrcH1;
1543	/** CRC-32 for the second half of the page. */
1544	uint32_t u32CrcH2;
1545	/** SHA-1 for the saved page.
1546	* This is used in the final pass to skip pages without changes. */
1547	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1548	} PGMLIVESAVEMMIO2PAGE;
1549	/** Pointer to a live save status data for an MMIO2 page. */
1550	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1551
1552	/**
1553	* A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1554	*
1555	* There are a few reason why we need to keep track of these registrations. One
1556	* of them is the deregistration & cleanup stuff, while another is that the
1557	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1558	* range list.
1559	*
1560	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1561	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1562	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1563	* overlap we will free all the existing RAM pages and put in the ram range
1564	* pages instead.
1565	*/
1566	typedef struct PGMREGMMIORANGE
1567	{
1568	/** The owner of the range. (a device) */
1569	PPDMDEVINSR3 pDevInsR3;
1570	/** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1571	RTR3PTR pvR3;
1572	/** Pointer to the next range - R3. */
1573	R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1574	/** Flags (PGMREGMMIORANGE_F_XXX). */
1575	uint16_t fFlags;
1576	/** The sub device number (internal PCI config (CFGM) number). */
1577	uint8_t iSubDev;
1578	/** The PCI region number. */
1579	uint8_t iRegion;
1580	/** The saved state range ID. */
1581	uint8_t idSavedState;
1582	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1583	uint8_t idMmio2;
1584	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1585	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1586	/** The real size.
1587	* This may be larger than indicated by RamRange.cb if the range has been
1588	* reduced during saved state loading. */
1589	RTGCPHYS cbReal;
1590	/** Pointer to the physical handler for MMIO. */
1591	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1592	/** Live save per page tracking data for MMIO2. */
1593	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1594	/** The associated RAM range. */
1595	PGMRAMRANGE RamRange;
1596	} PGMREGMMIORANGE;
1597	AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1598	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1599	typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1600
1601	/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1602	* @{ */
1603	/** Set if it's an MMIO2 range. */
1604	#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1605	/** Set if this is the first chunk in the MMIO2 range. */
1606	#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1607	/** Set if this is the last chunk in the MMIO2 range. */
1608	#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1609	/** Set if the whole range is mapped. */
1610	#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1611	/** Set if it's overlapping, clear if not. */
1612	#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1613	/** @} */
1614
1615
1616	/** @name Internal MMIO2 constants.
1617	* @{ */
1618	/** The maximum number of MMIO2 ranges. */
1619	#define PGM_MMIO2_MAX_RANGES 8
1620	/** The maximum number of pages in a MMIO2 range. */
1621	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1622	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1623	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1624	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1625	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1626	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1627	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1628	/** @} */
1629
1630
1631
1632	/**
1633	* PGMPhysRead/Write cache entry
1634	*/
1635	typedef struct PGMPHYSCACHEENTRY
1636	{
1637	/** R3 pointer to physical page. */
1638	R3PTRTYPE(uint8_t *) pbR3;
1639	/** GC Physical address for cache entry */
1640	RTGCPHYS GCPhys;
1641	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1642	RTGCPHYS u32Padding0; /*< alignment padding. /
1643	#endif
1644	} PGMPHYSCACHEENTRY;
1645
1646	/**
1647	* PGMPhysRead/Write cache to reduce REM memory access overhead
1648	*/
1649	typedef struct PGMPHYSCACHE
1650	{
1651	/** Bitmap of valid cache entries */
1652	uint64_t aEntries;
1653	/** Cache entries */
1654	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1655	} PGMPHYSCACHE;
1656
1657
1658	/** Pointer to an allocation chunk ring-3 mapping. */
1659	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1660	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1661	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1662
1663	/**
1664	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1665	*
1666	* The primary tree (Core) uses the chunk id as key.
1667	*/
1668	typedef struct PGMCHUNKR3MAP
1669	{
1670	/** The key is the chunk id. */
1671	AVLU32NODECORE Core;
1672	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1673	* selection. */
1674	uint32_t iLastUsed;
1675	/** The current reference count. */
1676	uint32_t volatile cRefs;
1677	/** The current permanent reference count. */
1678	uint32_t volatile cPermRefs;
1679	/** The mapping address. */
1680	void *pv;
1681	} PGMCHUNKR3MAP;
1682
1683	/**
1684	* Allocation chunk ring-3 mapping TLB entry.
1685	*/
1686	typedef struct PGMCHUNKR3MAPTLBE
1687	{
1688	/** The chunk id. */
1689	uint32_t volatile idChunk;
1690	#if HC_ARCH_BITS == 64
1691	uint32_t u32Padding; /*< alignment padding. /
1692	#endif
1693	/** The chunk map. */
1694	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1695	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1696	#else
1697	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1698	#endif
1699	} PGMCHUNKR3MAPTLBE;
1700	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1701	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1702
1703	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1704	* @remark Must be a power of two value. */
1705	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1706
1707	/**
1708	* Allocation chunk ring-3 mapping TLB.
1709	*
1710	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1711	* At first glance this might look kinda odd since AVL trees are
1712	* supposed to give the most optimal lookup times of all trees
1713	* due to their balancing. However, take a tree with 1023 nodes
1714	* in it, that's 10 levels, meaning that most searches has to go
1715	* down 9 levels before they find what they want. This isn't fast
1716	* compared to a TLB hit. There is the factor of cache misses,
1717	* and of course the problem with trees and branch prediction.
1718	* This is why we use TLBs in front of most of the trees.
1719	*
1720	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1721	* difficult when we switch to the new inlined AVL trees (from kStuff).
1722	*/
1723	typedef struct PGMCHUNKR3MAPTLB
1724	{
1725	/** The TLB entries. */
1726	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1727	} PGMCHUNKR3MAPTLB;
1728
1729	/**
1730	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1731	* @returns Chunk TLB index.
1732	* @param idChunk The Chunk ID.
1733	*/
1734	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1735
1736
1737	/**
1738	* Ring-3 guest page mapping TLB entry.
1739	* @remarks used in ring-0 as well at the moment.
1740	*/
1741	typedef struct PGMPAGER3MAPTLBE
1742	{
1743	/** Address of the page. */
1744	RTGCPHYS volatile GCPhys;
1745	/** The guest page. */
1746	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1747	R3PTRTYPE(PPGMPAGE) volatile pPage;
1748	#else
1749	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1750	#endif
1751	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1752	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1753	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1754	#else
1755	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1756	#endif
1757	/** The address */
1758	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1759	R3PTRTYPE(void *) volatile pv;
1760	#else
1761	R3R0PTRTYPE(void *) volatile pv;
1762	#endif
1763	#if HC_ARCH_BITS == 32
1764	uint32_t u32Padding; /*< alignment padding. /
1765	#endif
1766	} PGMPAGER3MAPTLBE;
1767	/** Pointer to an entry in the HC physical TLB. */
1768	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1769
1770
1771	/** The number of entries in the ring-3 guest page mapping TLB.
1772	* @remarks The value must be a power of two. */
1773	#define PGM_PAGER3MAPTLB_ENTRIES 256
1774
1775	/**
1776	* Ring-3 guest page mapping TLB.
1777	* @remarks used in ring-0 as well at the moment.
1778	*/
1779	typedef struct PGMPAGER3MAPTLB
1780	{
1781	/** The TLB entries. */
1782	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1783	} PGMPAGER3MAPTLB;
1784	/** Pointer to the ring-3 guest page mapping TLB. */
1785	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1786
1787	/**
1788	* Calculates the index of the TLB entry for the specified guest page.
1789	* @returns Physical TLB index.
1790	* @param GCPhys The guest physical address.
1791	*/
1792	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1793
1794
1795	/**
1796	* Raw-mode context dynamic mapping cache entry.
1797	*
1798	* Because of raw-mode context being reloctable and all relocations are applied
1799	* in ring-3, this has to be defined here and be RC specific.
1800	*
1801	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1802	*/
1803	typedef struct PGMRCDYNMAPENTRY
1804	{
1805	/** The physical address of the currently mapped page.
1806	* This is duplicate for three reasons: cache locality, cache policy of the PT
1807	* mappings and sanity checks. */
1808	RTHCPHYS HCPhys;
1809	/** Pointer to the page. */
1810	RTRCPTR pvPage;
1811	/** The number of references. */
1812	int32_t volatile cRefs;
1813	/** PTE pointer union. */
1814	struct PGMRCDYNMAPENTRY_PPTE
1815	{
1816	/** PTE pointer, 32-bit legacy version. */
1817	RCPTRTYPE(PX86PTE) pLegacy;
1818	/** PTE pointer, PAE version. */
1819	RCPTRTYPE(PX86PTEPAE) pPae;
1820	} uPte;
1821	} PGMRCDYNMAPENTRY;
1822	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1823	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1824
1825
1826	/**
1827	* Dynamic mapping cache for the raw-mode context.
1828	*
1829	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1830	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1831	* so that we can perform relocations from PGMR3Relocate. This has the
1832	* consequence that we must have separate ring-0 and raw-mode context versions
1833	* of this struct even if they share the basic elements.
1834	*
1835	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1836	*/
1837	typedef struct PGMRCDYNMAP
1838	{
1839	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1840	uint32_t u32Magic;
1841	/** Array for tracking and managing the pages. */
1842	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1843	/** The cache size given as a number of pages. */
1844	uint32_t cPages;
1845	/** The current load.
1846	* This does not include guard pages. */
1847	uint32_t cLoad;
1848	/** The max load ever.
1849	* This is maintained to get trigger adding of more mapping space. */
1850	uint32_t cMaxLoad;
1851	/** The number of guard pages. */
1852	uint32_t cGuardPages;
1853	/** The number of users (protected by hInitLock). */
1854	uint32_t cUsers;
1855	} PGMRCDYNMAP;
1856	/** Pointer to the dynamic cache for the raw-mode context. */
1857	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1858
1859
1860	/**
1861	* Mapping cache usage set entry.
1862	*
1863	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1864	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1865	* cache. If it's extended to include ring-3, well, then something
1866	* will have be changed here...
1867	*/
1868	typedef struct PGMMAPSETENTRY
1869	{
1870	/** Pointer to the page. */
1871	#ifndef IN_RC
1872	RTR0PTR pvPage;
1873	#else
1874	RTRCPTR pvPage;
1875	# if HC_ARCH_BITS == 64
1876	uint32_t u32Alignment2;
1877	# endif
1878	#endif
1879	/** The mapping cache index. */
1880	uint16_t iPage;
1881	/** The number of references.
1882	* The max is UINT16_MAX - 1. */
1883	uint16_t cRefs;
1884	/** The number inlined references.
1885	* The max is UINT16_MAX - 1. */
1886	uint16_t cInlinedRefs;
1887	/** Unreferences. */
1888	uint16_t cUnrefs;
1889
1890	#if HC_ARCH_BITS == 32
1891	uint32_t u32Alignment1;
1892	#endif
1893	/** The physical address for this entry. */
1894	RTHCPHYS HCPhys;
1895	} PGMMAPSETENTRY;
1896	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1897	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1898	/** Pointer to a mapping cache usage set entry. */
1899	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1900
1901	/**
1902	* Mapping cache usage set.
1903	*
1904	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1905	* done during exits / traps. The set is
1906	*/
1907	typedef struct PGMMAPSET
1908	{
1909	/** The number of occupied entries.
1910	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1911	* dynamic mappings. */
1912	uint32_t cEntries;
1913	/** The start of the current subset.
1914	* This is UINT32_MAX if no subset is currently open. */
1915	uint32_t iSubset;
1916	/** The index of the current CPU, only valid if the set is open. */
1917	int32_t iCpu;
1918	uint32_t alignment;
1919	/** The entries. */
1920	PGMMAPSETENTRY aEntries[64];
1921	/** HCPhys -> iEntry fast lookup table.
1922	* Use PGMMAPSET_HASH for hashing.
1923	* The entries may or may not be valid, check against cEntries. */
1924	uint8_t aiHashTable[128];
1925	} PGMMAPSET;
1926	AssertCompileSizeAlignment(PGMMAPSET, 8);
1927	/** Pointer to the mapping cache set. */
1928	typedef PGMMAPSET *PPGMMAPSET;
1929
1930	/** PGMMAPSET::cEntries value for a closed set. */
1931	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1932
1933	/** Hash function for aiHashTable. */
1934	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1935
1936
1937	/** @name Context neutral page mapper TLB.
1938	*
1939	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1940	* code is writting in a kind of context neutral way. Time will show whether
1941	* this actually makes sense or not...
1942	*
1943	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1944	* context ends up using a global mapping cache on some platforms
1945	* (darwin).
1946	*
1947	* @{ */
1948	/** @typedef PPGMPAGEMAPTLB
1949	* The page mapper TLB pointer type for the current context. */
1950	/** @typedef PPGMPAGEMAPTLB
1951	* The page mapper TLB entry pointer type for the current context. */
1952	/** @typedef PPGMPAGEMAPTLB
1953	* The page mapper TLB entry pointer pointer type for the current context. */
1954	/** @def PGM_PAGEMAPTLB_ENTRIES
1955	* The number of TLB entries in the page mapper TLB for the current context. */
1956	/** @def PGM_PAGEMAPTLB_IDX
1957	* Calculate the TLB index for a guest physical address.
1958	* @returns The TLB index.
1959	* @param GCPhys The guest physical address. */
1960	/** @typedef PPGMPAGEMAP
1961	* Pointer to a page mapper unit for current context. */
1962	/** @typedef PPPGMPAGEMAP
1963	* Pointer to a page mapper unit pointer for current context. */
1964	#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
1965	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1966	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1967	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1968	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1969	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1970	typedef void * PPGMPAGEMAP;
1971	typedef void ** PPPGMPAGEMAP;
1972	//#elif IN_RING0
1973	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1974	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1975	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1976	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1977	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1978	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1979	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1980	#else
1981	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1982	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1983	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1984	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1985	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1986	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1987	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1988	#endif
1989	/** @} */
1990
1991
1992	/** @name PGM Pool Indexes.
1993	* Aka. the unique shadow page identifier.
1994	* @{ */
1995	/** NIL page pool IDX. */
1996	#define NIL_PGMPOOL_IDX 0
1997	/** The first normal index. There used to be 5 fictive pages up front, now
1998	* there is only the NIL page. */
1999	#define PGMPOOL_IDX_FIRST 1
2000	/** The last valid index. (inclusive, 14 bits) */
2001	#define PGMPOOL_IDX_LAST 0x3fff
2002	/** @} */
2003
2004	/** The NIL index for the parent chain. */
2005	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2006	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2007
2008	/**
2009	* Node in the chain linking a shadowed page to it's parent (user).
2010	*/
2011	#pragma pack(1)
2012	typedef struct PGMPOOLUSER
2013	{
2014	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2015	uint16_t iNext;
2016	/** The user page index. */
2017	uint16_t iUser;
2018	/** Index into the user table. */
2019	uint32_t iUserTable;
2020	} PGMPOOLUSER, *PPGMPOOLUSER;
2021	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2022	#pragma pack()
2023
2024
2025	/** The NIL index for the phys ext chain. */
2026	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2027	/** The NIL pte index for a phys ext chain slot. */
2028	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2029
2030	/**
2031	* Node in the chain of physical cross reference extents.
2032	* @todo Calling this an 'extent' is not quite right, find a better name.
2033	* @todo find out the optimal size of the aidx array
2034	*/
2035	#pragma pack(1)
2036	typedef struct PGMPOOLPHYSEXT
2037	{
2038	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2039	uint16_t iNext;
2040	/** Alignment. */
2041	uint16_t u16Align;
2042	/** The user page index. */
2043	uint16_t aidx[3];
2044	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2045	uint16_t apte[3];
2046	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2047	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2048	#pragma pack()
2049
2050
2051	/**
2052	* The kind of page that's being shadowed.
2053	*/
2054	typedef enum PGMPOOLKIND
2055	{
2056	/** The virtual invalid 0 entry. */
2057	PGMPOOLKIND_INVALID = 0,
2058	/** The entry is free (=unused). */
2059	PGMPOOLKIND_FREE,
2060
2061	/** Shw: 32-bit page table; Gst: no paging. */
2062	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2063	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2064	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2065	/** Shw: 32-bit page table; Gst: 4MB page. */
2066	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2067	/** Shw: PAE page table; Gst: no paging. */
2068	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2069	/** Shw: PAE page table; Gst: 32-bit page table. */
2070	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2071	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2072	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2073	/** Shw: PAE page table; Gst: PAE page table. */
2074	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2075	/** Shw: PAE page table; Gst: 2MB page. */
2076	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2077
2078	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2079	PGMPOOLKIND_32BIT_PD,
2080	/** Shw: 32-bit page directory. Gst: no paging. */
2081	PGMPOOLKIND_32BIT_PD_PHYS,
2082	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2083	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2084	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2085	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2086	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2087	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2088	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2089	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2090	/** Shw: PAE page directory; Gst: PAE page directory. */
2091	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2092	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2093	PGMPOOLKIND_PAE_PD_PHYS,
2094
2095	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2096	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2097	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2098	PGMPOOLKIND_PAE_PDPT,
2099	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2100	PGMPOOLKIND_PAE_PDPT_PHYS,
2101
2102	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2103	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2104	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2105	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2106	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2107	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2108	/** Shw: 64-bit page directory table; Gst: no paging. */
2109	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2110
2111	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2112	PGMPOOLKIND_64BIT_PML4,
2113
2114	/** Shw: EPT page directory pointer table; Gst: no paging. */
2115	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2116	/** Shw: EPT page directory table; Gst: no paging. */
2117	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2118	/** Shw: EPT page table; Gst: no paging. */
2119	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2120
2121	/** Shw: Root Nested paging table. */
2122	PGMPOOLKIND_ROOT_NESTED,
2123
2124	/** The last valid entry. */
2125	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2126	} PGMPOOLKIND;
2127
2128	/**
2129	* The access attributes of the page; only applies to big pages.
2130	*/
2131	typedef enum
2132	{
2133	PGMPOOLACCESS_DONTCARE = 0,
2134	PGMPOOLACCESS_USER_RW,
2135	PGMPOOLACCESS_USER_R,
2136	PGMPOOLACCESS_USER_RW_NX,
2137	PGMPOOLACCESS_USER_R_NX,
2138	PGMPOOLACCESS_SUPERVISOR_RW,
2139	PGMPOOLACCESS_SUPERVISOR_R,
2140	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2141	PGMPOOLACCESS_SUPERVISOR_R_NX
2142	} PGMPOOLACCESS;
2143
2144	/**
2145	* The tracking data for a page in the pool.
2146	*/
2147	typedef struct PGMPOOLPAGE
2148	{
2149	/** AVL node code with the (HC) physical address of this page. */
2150	AVLOHCPHYSNODECORE Core;
2151	/** Pointer to the R3 mapping of the page. */
2152	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2153	R3PTRTYPE(void *) pvPageR3;
2154	#else
2155	R3R0PTRTYPE(void *) pvPageR3;
2156	#endif
2157	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2158	uint32_t Alignment0;
2159	#endif
2160	/** The guest physical address. */
2161	RTGCPHYS GCPhys;
2162	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2163	uint8_t enmKind;
2164	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2165	uint8_t enmAccess;
2166	/** This supplements enmKind and enmAccess */
2167	bool fA20Enabled : 1;
2168
2169	/** Used to indicate that the page is zeroed. */
2170	bool fZeroed : 1;
2171	/** Used to indicate that a PT has non-global entries. */
2172	bool fSeenNonGlobal : 1;
2173	/** Used to indicate that we're monitoring writes to the guest page. */
2174	bool fMonitored : 1;
2175	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2176	* (All pages are in the age list.) */
2177	bool fCached : 1;
2178	/** This is used by the R3 access handlers when invoked by an async thread.
2179	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2180	bool volatile fReusedFlushPending : 1;
2181	/** Used to mark the page as dirty (write monitoring is temporarily
2182	* off). */
2183	bool fDirty : 1;
2184	bool fPadding1 : 1;
2185	bool fPadding2;
2186
2187	/** The index of this page. */
2188	uint16_t idx;
2189	/** The next entry in the list this page currently resides in.
2190	* It's either in the free list or in the GCPhys hash. */
2191	uint16_t iNext;
2192	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2193	uint16_t iUserHead;
2194	/** The number of present entries. */
2195	uint16_t cPresent;
2196	/** The first entry in the table which is present. */
2197	uint16_t iFirstPresent;
2198	/** The number of modifications to the monitored page. */
2199	uint16_t cModifications;
2200	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2201	uint16_t iModifiedNext;
2202	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2203	uint16_t iModifiedPrev;
2204	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2205	uint16_t iMonitoredNext;
2206	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2207	uint16_t iMonitoredPrev;
2208	/** The next page in the age list. */
2209	uint16_t iAgeNext;
2210	/** The previous page in the age list. */
2211	uint16_t iAgePrev;
2212	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2213	uint8_t idxDirtyEntry;
2214
2215	/** @name Access handler statistics to determine whether the guest is
2216	* (re)initializing a page table.
2217	* @{ */
2218	RTGCPTR GCPtrLastAccessHandlerRip;
2219	RTGCPTR GCPtrLastAccessHandlerFault;
2220	uint64_t cLastAccessHandler;
2221	/** @} */
2222	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2223	uint32_t volatile cLocked;
2224	#if GC_ARCH_BITS == 64
2225	uint32_t u32Alignment3;
2226	#endif
2227	# ifdef VBOX_STRICT
2228	RTGCPTR GCPtrDirtyFault;
2229	# endif
2230	} PGMPOOLPAGE;
2231	/** Pointer to a pool page. */
2232	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2233	/** Pointer to a const pool page. */
2234	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2235	/** Pointer to a pool page pointer. */
2236	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2237
2238
2239	/** The hash table size. */
2240	# define PGMPOOL_HASH_SIZE 0x40
2241	/** The hash function. */
2242	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2243
2244
2245	/**
2246	* The shadow page pool instance data.
2247	*
2248	* It's all one big allocation made at init time, except for the
2249	* pages that is. The user nodes follows immediately after the
2250	* page structures.
2251	*/
2252	typedef struct PGMPOOL
2253	{
2254	/** The VM handle - R3 Ptr. */
2255	PVMR3 pVMR3;
2256	/** The VM handle - R0 Ptr. */
2257	PVMR0 pVMR0;
2258	/** The VM handle - RC Ptr. */
2259	PVMRC pVMRC;
2260	/** The max pool size. This includes the special IDs. */
2261	uint16_t cMaxPages;
2262	/** The current pool size. */
2263	uint16_t cCurPages;
2264	/** The head of the free page list. */
2265	uint16_t iFreeHead;
2266	/* Padding. */
2267	uint16_t u16Padding;
2268	/** Head of the chain of free user nodes. */
2269	uint16_t iUserFreeHead;
2270	/** The number of user nodes we've allocated. */
2271	uint16_t cMaxUsers;
2272	/** The number of present page table entries in the entire pool. */
2273	uint32_t cPresent;
2274	/** Pointer to the array of user nodes - RC pointer. */
2275	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2276	/** Pointer to the array of user nodes - R3 pointer. */
2277	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2278	/** Pointer to the array of user nodes - R0 pointer. */
2279	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2280	/** Head of the chain of free phys ext nodes. */
2281	uint16_t iPhysExtFreeHead;
2282	/** The number of user nodes we've allocated. */
2283	uint16_t cMaxPhysExts;
2284	/** Pointer to the array of physical xref extent - RC pointer. */
2285	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2286	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2287	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2288	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2289	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2290	/** Hash table for GCPhys addresses. */
2291	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2292	/** The head of the age list. */
2293	uint16_t iAgeHead;
2294	/** The tail of the age list. */
2295	uint16_t iAgeTail;
2296	/** Set if the cache is enabled. */
2297	bool fCacheEnabled;
2298	/** Alignment padding. */
2299	bool afPadding1[3];
2300	/** Head of the list of modified pages. */
2301	uint16_t iModifiedHead;
2302	/** The current number of modified pages. */
2303	uint16_t cModifiedPages;
2304	/** Physical access handler type registration handle. */
2305	PGMPHYSHANDLERTYPE hAccessHandlerType;
2306	/** Next available slot (in aDirtyPages). */
2307	uint32_t idxFreeDirtyPage;
2308	/** Number of active dirty pages. */
2309	uint32_t cDirtyPages;
2310	/** Array of current dirty pgm pool page indices. */
2311	uint16_t aidxDirtyPages[16];
2312	/** Array running in parallel to aidxDirtyPages with the page data. */
2313	struct
2314	{
2315	uint64_t aPage[512];
2316	} aDirtyPages[16];
2317
2318	/** The number of pages currently in use. */
2319	uint16_t cUsedPages;
2320	#ifdef VBOX_WITH_STATISTICS
2321	/** The high water mark for cUsedPages. */
2322	uint16_t cUsedPagesHigh;
2323	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2324	/** Profiling pgmPoolAlloc(). */
2325	STAMPROFILEADV StatAlloc;
2326	/** Profiling pgmR3PoolClearDoIt(). */
2327	STAMPROFILE StatClearAll;
2328	/** Profiling pgmR3PoolReset(). */
2329	STAMPROFILE StatR3Reset;
2330	/** Profiling pgmPoolFlushPage(). */
2331	STAMPROFILE StatFlushPage;
2332	/** Profiling pgmPoolFree(). */
2333	STAMPROFILE StatFree;
2334	/** Counting explicit flushes by PGMPoolFlushPage(). */
2335	STAMCOUNTER StatForceFlushPage;
2336	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2337	STAMCOUNTER StatForceFlushDirtyPage;
2338	/** Counting flushes for reused pages. */
2339	STAMCOUNTER StatForceFlushReused;
2340	/** Profiling time spent zeroing pages. */
2341	STAMPROFILE StatZeroPage;
2342	/** Profiling of pgmPoolTrackDeref. */
2343	STAMPROFILE StatTrackDeref;
2344	/** Profiling pgmTrackFlushGCPhysPT. */
2345	STAMPROFILE StatTrackFlushGCPhysPT;
2346	/** Profiling pgmTrackFlushGCPhysPTs. */
2347	STAMPROFILE StatTrackFlushGCPhysPTs;
2348	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2349	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2350	/** Number of times we've been out of user records. */
2351	STAMCOUNTER StatTrackFreeUpOneUser;
2352	/** Nr of flushed entries. */
2353	STAMCOUNTER StatTrackFlushEntry;
2354	/** Nr of updated entries. */
2355	STAMCOUNTER StatTrackFlushEntryKeep;
2356	/** Profiling deref activity related tracking GC physical pages. */
2357	STAMPROFILE StatTrackDerefGCPhys;
2358	/** Number of linear searches for a HCPhys in the ram ranges. */
2359	STAMCOUNTER StatTrackLinearRamSearches;
2360	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2361	STAMCOUNTER StamTrackPhysExtAllocFailures;
2362
2363	/** Profiling the RC/R0 \#PF access handler. */
2364	STAMPROFILE StatMonitorPfRZ;
2365	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2366	STAMPROFILE StatMonitorPfRZHandled;
2367	/** Times we've failed interpreting the instruction. */
2368	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2369	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2370	STAMPROFILE StatMonitorPfRZFlushPage;
2371	/* Times we've detected a page table reinit. */
2372	STAMCOUNTER StatMonitorPfRZFlushReinit;
2373	/** Counting flushes for pages that are modified too often. */
2374	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2375	/** Times we've detected fork(). */
2376	STAMCOUNTER StatMonitorPfRZFork;
2377	/** Times we've failed interpreting a patch code instruction. */
2378	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2379	/** Times we've failed interpreting a patch code instruction during flushing. */
2380	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2381	/** The number of times we've seen rep prefixes we can't handle. */
2382	STAMCOUNTER StatMonitorPfRZRepPrefix;
2383	/** Profiling the REP STOSD cases we've handled. */
2384	STAMPROFILE StatMonitorPfRZRepStosd;
2385
2386	/** Profiling the R0/RC regular access handler. */
2387	STAMPROFILE StatMonitorRZ;
2388	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2389	STAMPROFILE StatMonitorRZFlushPage;
2390	/** Per access size counts indexed by size minus 1, last for larger. */
2391	STAMCOUNTER aStatMonitorRZSizes[16+3];
2392	/** Missaligned access counts indexed by offset - 1. */
2393	STAMCOUNTER aStatMonitorRZMisaligned[7];
2394
2395	/** Nr of handled PT faults. */
2396	STAMCOUNTER StatMonitorRZFaultPT;
2397	/** Nr of handled PD faults. */
2398	STAMCOUNTER StatMonitorRZFaultPD;
2399	/** Nr of handled PDPT faults. */
2400	STAMCOUNTER StatMonitorRZFaultPDPT;
2401	/** Nr of handled PML4 faults. */
2402	STAMCOUNTER StatMonitorRZFaultPML4;
2403
2404	/** Profiling the R3 access handler. */
2405	STAMPROFILE StatMonitorR3;
2406	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2407	STAMPROFILE StatMonitorR3FlushPage;
2408	/** Per access size counts indexed by size minus 1, last for larger. */
2409	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2410	/** Missaligned access counts indexed by offset - 1. */
2411	STAMCOUNTER aStatMonitorR3Misaligned[7];
2412	/** Nr of handled PT faults. */
2413	STAMCOUNTER StatMonitorR3FaultPT;
2414	/** Nr of handled PD faults. */
2415	STAMCOUNTER StatMonitorR3FaultPD;
2416	/** Nr of handled PDPT faults. */
2417	STAMCOUNTER StatMonitorR3FaultPDPT;
2418	/** Nr of handled PML4 faults. */
2419	STAMCOUNTER StatMonitorR3FaultPML4;
2420
2421	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2422	STAMCOUNTER StatResetDirtyPages;
2423	/** Times we've called pgmPoolAddDirtyPage. */
2424	STAMCOUNTER StatDirtyPage;
2425	/** Times we've had to flush duplicates for dirty page management. */
2426	STAMCOUNTER StatDirtyPageDupFlush;
2427	/** Times we've had to flush because of overflow. */
2428	STAMCOUNTER StatDirtyPageOverFlowFlush;
2429
2430	/** The high water mark for cModifiedPages. */
2431	uint16_t cModifiedPagesHigh;
2432	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2433
2434	/** The number of cache hits. */
2435	STAMCOUNTER StatCacheHits;
2436	/** The number of cache misses. */
2437	STAMCOUNTER StatCacheMisses;
2438	/** The number of times we've got a conflict of 'kind' in the cache. */
2439	STAMCOUNTER StatCacheKindMismatches;
2440	/** Number of times we've been out of pages. */
2441	STAMCOUNTER StatCacheFreeUpOne;
2442	/** The number of cacheable allocations. */
2443	STAMCOUNTER StatCacheCacheable;
2444	/** The number of uncacheable allocations. */
2445	STAMCOUNTER StatCacheUncacheable;
2446	#else
2447	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2448	#endif
2449	/** The AVL tree for looking up a page by its HC physical address. */
2450	AVLOHCPHYSTREE HCPhysTree;
2451	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2452	/** Array of pages. (cMaxPages in length)
2453	* The Id is the index into thist array.
2454	*/
2455	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2456	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2457	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2458	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2459	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2460	#ifdef VBOX_WITH_STATISTICS
2461	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2462	#endif
2463	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2464
2465
2466	/** @def PGMPOOL_PAGE_2_PTR
2467	* Maps a pool page pool into the current context.
2468	*
2469	* @returns VBox status code.
2470	* @param a_pVM Pointer to the VM.
2471	* @param a_pPage The pool page.
2472	*
2473	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2474	* small page window employeed by that function. Be careful.
2475	* @remark There is no need to assert on the result.
2476	*/
2477	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2478	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2479	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2480	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2481	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2482	{
2483	AssertPtr(a_pPage);
2484	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2485	return a_pPage->pvPageR3;
2486	}
2487	#else
2488	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2489	#endif
2490
2491
2492	/** @def PGMPOOL_PAGE_2_PTR_V2
2493	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2494	*
2495	* @returns VBox status code.
2496	* @param a_pVM Pointer to the VM.
2497	* @param a_pVCpu The current CPU.
2498	* @param a_pPage The pool page.
2499	*
2500	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2501	* small page window employeed by that function. Be careful.
2502	* @remark There is no need to assert on the result.
2503	*/
2504	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2505	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2506	#else
2507	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2508	#endif
2509
2510
2511	/** @name Per guest page tracking data.
2512	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2513	* is to use more bits for it and split it up later on. But for now we'll play
2514	* safe and change as little as possible.
2515	*
2516	* The 16-bit word has two parts:
2517	*
2518	* The first 14-bit forms the @a idx field. It is either the index of a page in
2519	* the shadow page pool, or and index into the extent list.
2520	*
2521	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2522	* shadow page pool references to the page. If cRefs equals
2523	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2524	* (misnomer) table and not the shadow page pool.
2525	*
2526	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2527	* the 16-bit word.
2528	*
2529	* @{ */
2530	/** The shift count for getting to the cRefs part. */
2531	#define PGMPOOL_TD_CREFS_SHIFT 14
2532	/** The mask applied after shifting the tracking data down by
2533	* PGMPOOL_TD_CREFS_SHIFT. */
2534	#define PGMPOOL_TD_CREFS_MASK 0x3
2535	/** The cRefs value used to indicate that the idx is the head of a
2536	* physical cross reference list. */
2537	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2538	/** The shift used to get idx. */
2539	#define PGMPOOL_TD_IDX_SHIFT 0
2540	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2541	#define PGMPOOL_TD_IDX_MASK 0x3fff
2542	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2543	* simply too many mappings of this page. */
2544	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2545
2546	/** @def PGMPOOL_TD_MAKE
2547	* Makes a 16-bit tracking data word.
2548	*
2549	* @returns tracking data.
2550	* @param cRefs The @a cRefs field. Must be within bounds!
2551	* @param idx The @a idx field. Must also be within bounds! */
2552	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2553
2554	/** @def PGMPOOL_TD_GET_CREFS
2555	* Get the @a cRefs field from a tracking data word.
2556	*
2557	* @returns The @a cRefs field
2558	* @param u16 The tracking data word.
2559	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2560	* non-zero @a u16. */
2561	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2562
2563	/** @def PGMPOOL_TD_GET_IDX
2564	* Get the @a idx field from a tracking data word.
2565	*
2566	* @returns The @a idx field
2567	* @param u16 The tracking data word. */
2568	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2569	/** @} */
2570
2571
2572
2573	/** @name A20 gate macros
2574	* @{ */
2575	#define PGM_WITH_A20
2576	#ifdef PGM_WITH_A20
2577	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2578	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2579	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2580	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2581	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2582	#else
2583	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2584	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2585	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2586	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2587	#endif
2588	/** @} */
2589
2590
2591	/**
2592	* Roots and anchors for trees and list employing self relative offsets as
2593	* pointers.
2594	*
2595	* When using self-relative offsets instead of pointers, the offsets needs to be
2596	* the same in all offsets. Thus the roots and anchors needs to live on the
2597	* hyper heap just like the nodes.
2598	*/
2599	typedef struct PGMTREES
2600	{
2601	/** List of physical access handler types (offset pointers) of type
2602	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2603	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2604	/** Physical access handlers (AVL range+offsetptr tree). */
2605	AVLROGCPHYSTREE PhysHandlers;
2606	#ifdef VBOX_WITH_RAW_MODE
2607	/** Virtual access handlers (AVL range + GC ptr tree). */
2608	AVLROGCPTRTREE VirtHandlers;
2609	/** Virtual access handlers (Phys range AVL range + offsetptr tree).
2610	* @remarks Handler of the hypervisor kind are of course not present. */
2611	AVLROGCPHYSTREE PhysToVirtHandlers;
2612	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2613	AVLROGCPTRTREE HyperVirtHandlers;
2614	/** List of virtual access handler types (offset pointers) of type
2615	* PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2616	RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2617	#endif
2618	} PGMTREES;
2619	/** Pointer to PGM trees. */
2620	typedef PGMTREES *PPGMTREES;
2621
2622
2623	/**
2624	* Page fault guest state for the AMD64 paging mode.
2625	*/
2626	typedef struct PGMPTWALKCORE
2627	{
2628	/** The guest virtual address that is being resolved by the walk
2629	* (input). */
2630	RTGCPTR GCPtr;
2631
2632	/** The guest physical address that is the result of the walk.
2633	* @remarks only valid if fSucceeded is set. */
2634	RTGCPHYS GCPhys;
2635
2636	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2637	bool fSucceeded;
2638	/** The level problem arrised at.
2639	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2640	* level 8. This is 0 on success. */
2641	uint8_t uLevel;
2642	/** Set if the page isn't present. */
2643	bool fNotPresent;
2644	/** Encountered a bad physical address. */
2645	bool fBadPhysAddr;
2646	/** Set if there was reserved bit violations. */
2647	bool fRsvdError;
2648	/** Set if it involves a big page (2/4 MB). */
2649	bool fBigPage;
2650	/** Set if it involves a gigantic page (1 GB). */
2651	bool fGigantPage;
2652	/** The effective X86_PTE_US flag for the address. */
2653	bool fEffectiveUS;
2654	/** The effective X86_PTE_RW flag for the address. */
2655	bool fEffectiveRW;
2656	/** The effective X86_PTE_NX flag for the address. */
2657	bool fEffectiveNX;
2658	bool afPadding1[2];
2659	/** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2660	* The NX bit is inverted and shifted down 63 places to bit 0. */
2661	uint32_t fEffective;
2662	} PGMPTWALKCORE;
2663
2664	/** @name PGMPTWALKCORE::fEffective bits.
2665	* @{ */
2666	/** Effective execute bit (!NX). */
2667	#define PGMPTWALK_EFF_X UINT32_C(1)
2668	/** Effective write access bit. */
2669	#define PGMPTWALK_EFF_RW X86_PTE_RW
2670	/** Effective user-mode access bit. */
2671	#define PGMPTWALK_EFF_US X86_PTE_US
2672	/** Effective write through cache bit. */
2673	#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2674	/** Effective cache disabled bit. */
2675	#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2676	/** Effective accessed bit. */
2677	#define PGMPTWALK_EFF_A X86_PTE_A
2678	/** The dirty bit of the final entry. */
2679	#define PGMPTWALK_EFF_D X86_PTE_D
2680	/** The PAT bit of the final entry. */
2681	#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2682	/** The global bit of the final entry. */
2683	#define PGMPTWALK_EFF_G X86_PTE_G
2684	/** @} */
2685
2686
2687	/**
2688	* Guest page table walk for the AMD64 mode.
2689	*/
2690	typedef struct PGMPTWALKGSTAMD64
2691	{
2692	/** The common core. */
2693	PGMPTWALKCORE Core;
2694
2695	PX86PML4 pPml4;
2696	PX86PML4E pPml4e;
2697	X86PML4E Pml4e;
2698
2699	PX86PDPT pPdpt;
2700	PX86PDPE pPdpe;
2701	X86PDPE Pdpe;
2702
2703	PX86PDPAE pPd;
2704	PX86PDEPAE pPde;
2705	X86PDEPAE Pde;
2706
2707	PX86PTPAE pPt;
2708	PX86PTEPAE pPte;
2709	X86PTEPAE Pte;
2710	} PGMPTWALKGSTAMD64;
2711	/** Pointer to a AMD64 guest page table walk. */
2712	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2713	/** Pointer to a const AMD64 guest page table walk. */
2714	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2715
2716	/**
2717	* Guest page table walk for the PAE mode.
2718	*/
2719	typedef struct PGMPTWALKGSTPAE
2720	{
2721	/** The common core. */
2722	PGMPTWALKCORE Core;
2723
2724	PX86PDPT pPdpt;
2725	PX86PDPE pPdpe;
2726	X86PDPE Pdpe;
2727
2728	PX86PDPAE pPd;
2729	PX86PDEPAE pPde;
2730	X86PDEPAE Pde;
2731
2732	PX86PTPAE pPt;
2733	PX86PTEPAE pPte;
2734	X86PTEPAE Pte;
2735	} PGMPTWALKGSTPAE;
2736	/** Pointer to a PAE guest page table walk. */
2737	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2738	/** Pointer to a const AMD64 guest page table walk. */
2739	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2740
2741	/**
2742	* Guest page table walk for the 32-bit mode.
2743	*/
2744	typedef struct PGMPTWALKGST32BIT
2745	{
2746	/** The common core. */
2747	PGMPTWALKCORE Core;
2748
2749	PX86PD pPd;
2750	PX86PDE pPde;
2751	X86PDE Pde;
2752
2753	PX86PT pPt;
2754	PX86PTE pPte;
2755	X86PTE Pte;
2756	} PGMPTWALKGST32BIT;
2757	/** Pointer to a 32-bit guest page table walk. */
2758	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2759	/** Pointer to a const 32-bit guest page table walk. */
2760	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2761
2762	/**
2763	* Which part of PGMPTWALKGST that is valid.
2764	*/
2765	typedef enum PGMPTWALKGSTTYPE
2766	{
2767	/** Customary invalid 0 value. */
2768	PGMPTWALKGSTTYPE_INVALID = 0,
2769	/** PGMPTWALKGST::u.Amd64 is valid. */
2770	PGMPTWALKGSTTYPE_AMD64,
2771	/** PGMPTWALKGST::u.Pae is valid. */
2772	PGMPTWALKGSTTYPE_PAE,
2773	/** PGMPTWALKGST::u.Legacy is valid. */
2774	PGMPTWALKGSTTYPE_32BIT,
2775	/** Customary 32-bit type hack. */
2776	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2777	} PGMPTWALKGSTTYPE;
2778
2779	/**
2780	* Combined guest page table walk result.
2781	*/
2782	typedef struct PGMPTWALKGST
2783	{
2784	union
2785	{
2786	/** The page walker core - always valid. */
2787	PGMPTWALKCORE Core;
2788	/** The page walker for AMD64. */
2789	PGMPTWALKGSTAMD64 Amd64;
2790	/** The page walker for PAE (32-bit). */
2791	PGMPTWALKGSTPAE Pae;
2792	/** The page walker for 32-bit paging (called legacy due to C naming
2793	* convension). */
2794	PGMPTWALKGST32BIT Legacy;
2795	} u;
2796	/** Indicates which part of the union is valid. */
2797	PGMPTWALKGSTTYPE enmType;
2798	} PGMPTWALKGST;
2799	/** Pointer to a combined guest page table walk result. */
2800	typedef PGMPTWALKGST *PPGMPTWALKGST;
2801	/** Pointer to a read-only combined guest page table walk result. */
2802	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2803
2804
2805	/** @name Paging mode macros
2806	* @{
2807	*/
2808	#ifdef IN_RC
2809	# define PGM_CTX(a,b) a##RC##b
2810	# define PGM_CTX_STR(a,b) a "GC" b
2811	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2812	#else
2813	# ifdef IN_RING3
2814	# define PGM_CTX(a,b) a##R3##b
2815	# define PGM_CTX_STR(a,b) a "R3" b
2816	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2817	# else
2818	# define PGM_CTX(a,b) a##R0##b
2819	# define PGM_CTX_STR(a,b) a "R0" b
2820	# define PGM_CTX_DECL(type) VMMDECL(type)
2821	# endif
2822	#endif
2823
2824	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2825	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2826	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2827	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2828	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2829	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2830	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2831	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2832	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2833	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2834	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2835	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2836	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2837	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2838	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2839	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2840
2841	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2842	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2843	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2844	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2845	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2846	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2847	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2848	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2849	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2850	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2851	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2852	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2853	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2854	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2855	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2856	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2857	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2858	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2859	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2860	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2861	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2862	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2863	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2864	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2865	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2866
2867	/* Shw_Gst */
2868	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2869	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2870	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2871	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2872	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2873	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2874	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2875	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2876	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2877	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2878	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2879	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2880	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2881	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2882	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2883	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2884	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2885	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2886	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2887	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2888	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2889	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2890	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2891	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2892	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2893	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2894	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2895	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2896	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2897	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2898	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2899	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2900	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2901	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2902
2903	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2904	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2905	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2906	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2907	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2908	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2909	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2910	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2911	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2912	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2913	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2914	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2915	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2916	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2917	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2918	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2919	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2920	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2921	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2922	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2923	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2924	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2925	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2926	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2927	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2928	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2929	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2930	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2931
2932	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2933	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2934	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2935	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2936	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2937	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2938	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2939	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2940	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2941	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2942	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2943	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2944	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2945	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2946	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2947	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2948	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2949	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2950	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2951	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2952	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2953	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2954	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2955	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2956	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2957	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2958	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2959	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2960	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2961
2962	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2963	/** @} */
2964
2965
2966	/**
2967	* Function pointers for guest paging.
2968	*/
2969	typedef struct PGMMODEDATAGST
2970	{
2971	/** The guest mode type. */
2972	uint32_t uType;
2973	DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
2974	DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
2975	DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
2976	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
2977	DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
2978	#ifdef IN_RING3
2979	DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /*< Only in ring-3. /
2980	#endif
2981	} PGMMODEDATAGST;
2982
2983	/** The length of g_aPgmGuestModeData. */
2984	#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
2985	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2986	#else
2987	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2988	#endif
2989	/** The guest mode data array. */
2990	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2991
2992
2993	/**
2994	* Function pointers for shadow paging.
2995	*/
2996	typedef struct PGMMODEDATASHW
2997	{
2998	/** The shadow mode type. */
2999	uint32_t uType;
3000	DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
3001	DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
3002	uint64_t fMask, uint32_t fOpFlags);
3003	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
3004	DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3005	#ifdef IN_RING3
3006	DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /*< Only in ring-3. /
3007	#endif
3008	} PGMMODEDATASHW;
3009
3010	/** The length of g_aPgmShadowModeData. */
3011	#ifndef IN_RC
3012	# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
3013	#else
3014	# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3015	#endif
3016	/** The shadow mode data array. */
3017	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
3018
3019
3020	/**
3021	* Function pointers for guest+shadow paging.
3022	*/
3023	typedef struct PGMMODEDATABTH
3024	{
3025	/** The shadow mode type. */
3026	uint32_t uShwType;
3027	/** The guest mode type. */
3028	uint32_t uGstType;
3029
3030	DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3031	DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
3032	DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3033	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
3034	DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3035	DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPU pVCpu);
3036	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3037	#ifndef IN_RING3
3038	DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
3039	#endif
3040	#ifdef VBOX_STRICT
3041	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
3042	#endif
3043	} PGMMODEDATABTH;
3044
3045	/** The length of g_aPgmBothModeData. */
3046	#ifndef IN_RC
3047	# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3048	#else
3049	# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_PAE + 1 - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3050	#endif
3051	/** The guest+shadow mode data array. */
3052	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
3053
3054
3055	#ifdef VBOX_WITH_STATISTICS
3056	/**
3057	* PGM statistics.
3058	*
3059	* These lives on the heap when compiled in as they would otherwise waste
3060	* unnecessary space in release builds.
3061	*/
3062	typedef struct PGMSTATS
3063	{
3064	/* R3 only: */
3065	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3066	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3067
3068	/* R3+RZ */
3069	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3070	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3071	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3072	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3073	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3074	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3075	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3076	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3077	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3078	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3079	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3080	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3081	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3082	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3083	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3084	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3085	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3086	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3087	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3088	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3089	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3090	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3091	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3092	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3093	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3094	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3095
3096	/* RC only: */
3097	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3098	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3099
3100	STAMCOUNTER StatRZPhysRead;
3101	STAMCOUNTER StatRZPhysReadBytes;
3102	STAMCOUNTER StatRZPhysWrite;
3103	STAMCOUNTER StatRZPhysWriteBytes;
3104	STAMCOUNTER StatR3PhysRead;
3105	STAMCOUNTER StatR3PhysReadBytes;
3106	STAMCOUNTER StatR3PhysWrite;
3107	STAMCOUNTER StatR3PhysWriteBytes;
3108	STAMCOUNTER StatRCPhysRead;
3109	STAMCOUNTER StatRCPhysReadBytes;
3110	STAMCOUNTER StatRCPhysWrite;
3111	STAMCOUNTER StatRCPhysWriteBytes;
3112
3113	STAMCOUNTER StatRZPhysSimpleRead;
3114	STAMCOUNTER StatRZPhysSimpleReadBytes;
3115	STAMCOUNTER StatRZPhysSimpleWrite;
3116	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3117	STAMCOUNTER StatR3PhysSimpleRead;
3118	STAMCOUNTER StatR3PhysSimpleReadBytes;
3119	STAMCOUNTER StatR3PhysSimpleWrite;
3120	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3121	STAMCOUNTER StatRCPhysSimpleRead;
3122	STAMCOUNTER StatRCPhysSimpleReadBytes;
3123	STAMCOUNTER StatRCPhysSimpleWrite;
3124	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3125
3126	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3127	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3128	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3129	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3130	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3131	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3132	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3133
3134	/** Time spent by the host OS for large page allocation. */
3135	STAMPROFILE StatAllocLargePage;
3136	/** Time spent clearing the newly allocated large pages. */
3137	STAMPROFILE StatClearLargePage;
3138	/** The number of times allocating a large pages takes more than the allowed period. */
3139	STAMCOUNTER StatLargePageOverflow;
3140	/** pgmPhysIsValidLargePage profiling - R3 */
3141	STAMPROFILE StatR3IsValidLargePage;
3142	/** pgmPhysIsValidLargePage profiling - RZ*/
3143	STAMPROFILE StatRZIsValidLargePage;
3144
3145	STAMPROFILE StatChunkAging;
3146	STAMPROFILE StatChunkFindCandidate;
3147	STAMPROFILE StatChunkUnmap;
3148	STAMPROFILE StatChunkMap;
3149	} PGMSTATS;
3150	#endif /* VBOX_WITH_STATISTICS */
3151
3152
3153	/**
3154	* Converts a PGM pointer into a VM pointer.
3155	* @returns Pointer to the VM structure the PGM is part of.
3156	* @param pPGM Pointer to PGM instance data.
3157	*/
3158	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3159
3160	/**
3161	* PGM Data (part of VM)
3162	*/
3163	typedef struct PGM
3164	{
3165	/** Offset to the VM structure. */
3166	int32_t offVM;
3167	/** Offset of the PGMCPU structure relative to VMCPU. */
3168	int32_t offVCpuPGM;
3169
3170	/** @cfgm{/RamPreAlloc, boolean, false}
3171	* Indicates whether the base RAM should all be allocated before starting
3172	* the VM (default), or if it should be allocated when first written to.
3173	*/
3174	bool fRamPreAlloc;
3175	/** Indicates whether write monitoring is currently in use.
3176	* This is used to prevent conflicts between live saving and page sharing
3177	* detection. */
3178	bool fPhysWriteMonitoringEngaged;
3179	/** Set if the CPU has less than 52-bit physical address width.
3180	* This is used */
3181	bool fLessThan52PhysicalAddressBits;
3182	/** Set when nested paging is active.
3183	* This is meant to save calls to HMIsNestedPagingActive and let the
3184	* compilers optimize the code better. Whether we use nested paging or
3185	* not is something we find out during VMM initialization and we won't
3186	* change this later on. */
3187	bool fNestedPaging;
3188	/** The host paging mode. (This is what SUPLib reports.) */
3189	SUPPAGINGMODE enmHostMode;
3190	/** We're not in a state which permits writes to guest memory.
3191	* (Only used in strict builds.) */
3192	bool fNoMorePhysWrites;
3193	/** @cfgm{/PageFusionAllowed, boolean, false}
3194	* Whether page fusion is allowed. */
3195	bool fPageFusionAllowed;
3196	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3197	* Whether PCI passthrough is enabled. */
3198	bool fPciPassthrough;
3199	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3200	uint8_t cMmio2Regions;
3201	/** Restore original ROM page content when resetting after loading state.
3202	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3203	* enables the VM to start using an updated ROM without requiring powering
3204	* down the VM, just rebooting or resetting it. */
3205	bool fRestoreRomPagesOnReset;
3206	/** Whether to automatically clear all RAM pages on reset. */
3207	bool fZeroRamPagesOnReset;
3208	/** Alignment padding. */
3209	bool afAlignment3[7];
3210
3211	/** Indicates that PGMR3FinalizeMappings has been called and that further
3212	* PGMR3MapIntermediate calls will be rejected. */
3213	bool fFinalizedMappings;
3214	/** If set no conflict checks are required. */
3215	bool fMappingsFixed;
3216	/** If set if restored as fixed but we were unable to re-fixate at the old
3217	* location because of room or address incompatibilities. */
3218	bool fMappingsFixedRestored;
3219	/** Size of fixed mapping.
3220	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3221	uint32_t cbMappingFixed;
3222	/** Generation ID for the RAM ranges. This member is incremented everytime
3223	* a RAM range is linked or unlinked. */
3224	uint32_t volatile idRamRangesGen;
3225
3226	/** Base address (GC) of fixed mapping.
3227	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3228	RTGCPTR GCPtrMappingFixed;
3229	/** The address of the previous RAM range mapping. */
3230	RTGCPTR GCPtrPrevRamRangeMapping;
3231
3232	/** Physical access handler type for ROM protection. */
3233	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3234	/** Alignment padding. */
3235	uint32_t u32Padding;
3236
3237	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3238	RTGCPHYS GCPhys4MBPSEMask;
3239	/** Mask containing the invalid bits of a guest physical address.
3240	* @remarks this does not stop at bit 52. */
3241	RTGCPHYS GCPhysInvAddrMask;
3242
3243
3244	/** RAM range TLB for R3. */
3245	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3246	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3247	* This is sorted by physical address and contains no overlapping ranges. */
3248	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3249	/** Root of the RAM range search tree for ring-3. */
3250	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3251	/** PGM offset based trees - R3 Ptr. */
3252	R3PTRTYPE(PPGMTREES) pTreesR3;
3253	/** Caching the last physical handler we looked up in R3. */
3254	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3255	/** Shadow Page Pool - R3 Ptr. */
3256	R3PTRTYPE(PPGMPOOL) pPoolR3;
3257	#ifndef PGM_WITHOUT_MAPPINGS
3258	/** Linked list of GC mappings - for HC.
3259	* The list is sorted ascending on address. */
3260	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3261	#endif
3262	/** Pointer to the list of ROM ranges - for R3.
3263	* This is sorted by physical address and contains no overlapping ranges. */
3264	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3265	/** Pointer to the list of MMIO2 ranges - for R3.
3266	* Registration order. */
3267	R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3268	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3269	R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3270
3271	/** RAM range TLB for R0. */
3272	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3273	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3274	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3275	/** Root of the RAM range search tree for ring-0. */
3276	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3277	/** PGM offset based trees - R0 Ptr. */
3278	R0PTRTYPE(PPGMTREES) pTreesR0;
3279	/** Caching the last physical handler we looked up in R0. */
3280	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3281	/** Shadow Page Pool - R0 Ptr. */
3282	R0PTRTYPE(PPGMPOOL) pPoolR0;
3283	#ifndef PGM_WITHOUT_MAPPINGS
3284	/** Linked list of GC mappings - for R0.
3285	* The list is sorted ascending on address. */
3286	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3287	RTR0PTR R0PtrAlignment0;
3288	#endif
3289	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3290	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3291	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3292	R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3293
3294	/** RAM range TLB for RC. */
3295	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3296	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3297	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3298	/** Root of the RAM range search tree for raw-mode context. */
3299	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3300	/** PGM offset based trees - RC Ptr. */
3301	RCPTRTYPE(PPGMTREES) pTreesRC;
3302	/** Caching the last physical handler we looked up in RC. */
3303	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3304	/** Shadow Page Pool - RC Ptr. */
3305	RCPTRTYPE(PPGMPOOL) pPoolRC;
3306	#ifndef PGM_WITHOUT_MAPPINGS
3307	/** Linked list of GC mappings - for RC.
3308	* The list is sorted ascending on address. */
3309	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3310	RTRCPTR RCPtrAlignment0;
3311	#endif
3312	/** RC pointer corresponding to PGM::pRomRangesR3. */
3313	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3314	#ifndef PGM_WITHOUT_MAPPINGS
3315	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3316	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3317	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3318	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3319	#endif
3320
3321
3322	#ifndef PGM_WITHOUT_MAPPINGS
3323	/** Pointer to the 5 page CR3 content mapping.
3324	* The first page is always the CR3 (in some form) while the 4 other pages
3325	* are used for the PDs in PAE mode. */
3326	RTGCPTR GCPtrCR3Mapping;
3327
3328	/** @name Intermediate Context
3329	* @{ */
3330	/** Pointer to the intermediate page directory - Normal. */
3331	R3PTRTYPE(PX86PD) pInterPD;
3332	/** Pointer to the intermediate page tables - Normal.
3333	* There are two page tables, one for the identity mapping and one for
3334	* the host context mapping (of the core code). */
3335	R3PTRTYPE(PX86PT) apInterPTs[2];
3336	/** Pointer to the intermediate page tables - PAE. */
3337	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3338	/** Pointer to the intermediate page directory - PAE. */
3339	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3340	/** Pointer to the intermediate page directory - PAE. */
3341	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3342	/** Pointer to the intermediate page-map level 4 - AMD64. */
3343	R3PTRTYPE(PX86PML4) pInterPaePML4;
3344	/** Pointer to the intermediate page directory - AMD64. */
3345	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3346	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3347	RTHCPHYS HCPhysInterPD;
3348	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3349	RTHCPHYS HCPhysInterPaePDPT;
3350	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3351	RTHCPHYS HCPhysInterPaePML4;
3352	/** @} */
3353	#endif
3354
3355	#ifndef PGM_WITHOUT_MAPPINGS
3356	/** Base address of the dynamic page mapping area.
3357	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3358	*
3359	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3360	* work out. Some cleaning up of the initialization that would
3361	* remove this memory is yet to be done...
3362	*/
3363	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3364	/** The address of the raw-mode context mapping cache. */
3365	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3366	/** The address of the ring-0 mapping cache if we're making use of it. */
3367	RTR0PTR pvR0DynMapUsed;
3368	#endif
3369
3370	/** Hack: Number of deprecated page mapping locks taken by the current lock
3371	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3372	uint32_t cDeprecatedPageLocks;
3373	/** Alignment padding. */
3374	uint32_t au32Alignment2[3];
3375
3376
3377	/** PGM critical section.
3378	* This protects the physical & virtual access handlers, ram ranges,
3379	* and the page flag updating (some of it anyway).
3380	*/
3381	PDMCRITSECT CritSectX;
3382
3383	/**
3384	* Data associated with managing the ring-3 mappings of the allocation chunks.
3385	*/
3386	struct
3387	{
3388	/** The chunk mapping TLB. */
3389	PGMCHUNKR3MAPTLB Tlb;
3390	/** The chunk tree, ordered by chunk id. */
3391	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3392	R3PTRTYPE(PAVLU32NODECORE) pTree;
3393	#else
3394	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3395	#endif
3396	#if HC_ARCH_BITS == 32
3397	uint32_t u32Alignment0;
3398	#endif
3399	/** The number of mapped chunks. */
3400	uint32_t c;
3401	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3402	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3403	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3404	uint32_t cMax;
3405	/** The current time. This is incremented whenever a chunk is inserted. */
3406	uint32_t iNow;
3407	/** Alignment padding. */
3408	uint32_t au32Alignment1[3];
3409	} ChunkR3Map;
3410
3411	/** The page mapping TLB for ring-3. */
3412	PGMPAGER3MAPTLB PhysTlbR3;
3413	/** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3414	PGMPAGER3MAPTLB PhysTlbR0;
3415
3416	/** @name The zero page.
3417	* @{ */
3418	/** The host physical address of the zero page. */
3419	RTHCPHYS HCPhysZeroPg;
3420	/** The ring-3 mapping of the zero page. */
3421	RTR3PTR pvZeroPgR3;
3422	/** The ring-0 mapping of the zero page. */
3423	RTR0PTR pvZeroPgR0;
3424	/** The GC mapping of the zero page. */
3425	RTRCPTR pvZeroPgRC;
3426	RTRCPTR RCPtrAlignment3;
3427	/** @}*/
3428
3429	/** @name The Invalid MMIO page.
3430	* This page is filled with 0xfeedface.
3431	* @{ */
3432	/** The host physical address of the invalid MMIO page. */
3433	RTHCPHYS HCPhysMmioPg;
3434	/** The host pysical address of the invalid MMIO page plus all invalid
3435	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3436	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3437	RTHCPHYS HCPhysInvMmioPg;
3438	/** The ring-3 mapping of the invalid MMIO page. */
3439	RTR3PTR pvMmioPgR3;
3440	#if HC_ARCH_BITS == 32
3441	RTR3PTR R3PtrAlignment4;
3442	#endif
3443	/** @} */
3444
3445
3446	/** The number of handy pages. */
3447	uint32_t cHandyPages;
3448
3449	/** The number of large handy pages. */
3450	uint32_t cLargeHandyPages;
3451
3452	/**
3453	* Array of handy pages.
3454	*
3455	* This array is used in a two way communication between pgmPhysAllocPage
3456	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3457	* an intermediary.
3458	*
3459	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3460	* (The current size of 32 pages, means 128 KB of handy memory.)
3461	*/
3462	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3463
3464	/**
3465	* Array of large handy pages. (currently size 1)
3466	*
3467	* This array is used in a two way communication between pgmPhysAllocLargePage
3468	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3469	* an intermediary.
3470	*/
3471	GMMPAGEDESC aLargeHandyPage[1];
3472
3473	/**
3474	* Live save data.
3475	*/
3476	struct
3477	{
3478	/** Per type statistics. */
3479	struct
3480	{
3481	/** The number of ready pages. */
3482	uint32_t cReadyPages;
3483	/** The number of dirty pages. */
3484	uint32_t cDirtyPages;
3485	/** The number of ready zero pages. */
3486	uint32_t cZeroPages;
3487	/** The number of write monitored pages. */
3488	uint32_t cMonitoredPages;
3489	} Rom,
3490	Mmio2,
3491	Ram;
3492	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3493	uint32_t cIgnoredPages;
3494	/** Indicates that a live save operation is active. */
3495	bool fActive;
3496	/** Padding. */
3497	bool afReserved[2];
3498	/** The next history index. */
3499	uint8_t iDirtyPagesHistory;
3500	/** History of the total amount of dirty pages. */
3501	uint32_t acDirtyPagesHistory[64];
3502	/** Short term dirty page average. */
3503	uint32_t cDirtyPagesShort;
3504	/** Long term dirty page average. */
3505	uint32_t cDirtyPagesLong;
3506	/** The number of saved pages. This is used to get some kind of estimate of the
3507	* link speed so we can decide when we're done. It is reset after the first
3508	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3509	* zero pages. */
3510	uint64_t cSavedPages;
3511	/** The nanosecond timestamp when cSavedPages was 0. */
3512	uint64_t uSaveStartNS;
3513	/** Pages per second (for statistics). */
3514	uint32_t cPagesPerSecond;
3515	uint32_t cAlignment;
3516	} LiveSave;
3517
3518	/** @name Error injection.
3519	* @{ */
3520	/** Inject handy page allocation errors pretending we're completely out of
3521	* memory. */
3522	bool volatile fErrInjHandyPages;
3523	/** Padding. */
3524	bool afReserved[3];
3525	/** @} */
3526
3527	/** @name Release Statistics
3528	* @{ */
3529	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3530	uint32_t cPrivatePages; /*< The number of private pages. /
3531	uint32_t cSharedPages; /*< The number of shared pages. /
3532	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3533	uint32_t cZeroPages; /*< The number of zero backed pages. /
3534	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3535	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3536	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3537	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3538	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3539	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3540	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3541	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3542	uint32_t cLargePages; /*< The number of large pages. /
3543	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3544	/* uint32_t aAlignment4[1]; */
3545
3546	/** The number of times we were forced to change the hypervisor region location. */
3547	STAMCOUNTER cRelocations;
3548
3549	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3550	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3551	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3552
3553	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3554	/** @} */
3555
3556	#ifdef VBOX_WITH_STATISTICS
3557	/** @name Statistics on the heap.
3558	* @{ */
3559	R3PTRTYPE(PGMSTATS *) pStatsR3;
3560	R0PTRTYPE(PGMSTATS *) pStatsR0;
3561	RCPTRTYPE(PGMSTATS *) pStatsRC;
3562	RTRCPTR RCPtrAlignment;
3563	/** @} */
3564	#endif
3565	} PGM;
3566	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3567	# ifndef PGM_WITHOUT_MAPPINGS
3568	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3569	# endif
3570	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3571	# ifndef PGM_WITHOUT_MAPPINGS
3572	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3573	# endif
3574	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3575	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3576	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3577	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3578	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3579	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3580	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3581	#endif /* !IN_TSTVMSTRUCTGC */
3582	/** Pointer to the PGM instance data. */
3583	typedef PGM *PPGM;
3584
3585
3586
3587	typedef struct PGMCPUSTATS
3588	{
3589	/* Common */
3590	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3591	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3592
3593	/* R0 only: */
3594	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3595	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3596
3597	/* RZ only: */
3598	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3599	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3600	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3601	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3602	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3603	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3604	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3605	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3606	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3607	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3608	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3609	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3610	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3611	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3612	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3613	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3614	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3615	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3616	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3617	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3618	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3619	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3620	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3621	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3622	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3623	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3624	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3625	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3626	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3627	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3628	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3629	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3630	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3631	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3632	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3633	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3634	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3635	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3636	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3637	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3638	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3639	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3640	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3641	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3642	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3643	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3644	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3645	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3646	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3647	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3648	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3649	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3650	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3651	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3652	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3653	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3654	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3655	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3656	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3657	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3658	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3659	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3660	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3661	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3662	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3663	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3664	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3665	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3666	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3667	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3668	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3669	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3670	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3671
3672	/* HC - R3 and (maybe) R0: */
3673
3674	/* RZ & R3: */
3675	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3676	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3677	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3678	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3679	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3680	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3681	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3682	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3683	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3684	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3685	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3686	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3687	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3688	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3689	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3690	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3691	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3692	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3693	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3694	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3695	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3696	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3697	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3698	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3699	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3700	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3701	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3702	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3703	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3704	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3705	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3706	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3707	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3708	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3709	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3710	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3711	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3712	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3713	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3714	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3715	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3716	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3717	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3718	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3719	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3720	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3721	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3722	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3723
3724	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3725	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3726	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3727	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3728	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3729	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3730	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3731	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3732	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3733	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3734	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3735	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3736	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3737	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3738	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3739	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3740	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3741	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3742	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3743	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3744	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3745	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3746	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3747	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3748	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3749	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3750	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3751	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3752	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3753	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3754	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3755	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3756	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3757	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3758	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3759	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3760	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3761	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3762	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3763	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3764	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3765	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3766	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3767	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3768	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3769	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3770	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3771	/** @} */
3772	} PGMCPUSTATS;
3773
3774
3775	/**
3776	* Converts a PGMCPU pointer into a VM pointer.
3777	* @returns Pointer to the VM structure the PGM is part of.
3778	* @param pPGM Pointer to PGMCPU instance data.
3779	*/
3780	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3781
3782	/**
3783	* Converts a PGMCPU pointer into a PGM pointer.
3784	* @returns Pointer to the VM structure the PGM is part of.
3785	* @param pPGMCpu Pointer to PGMCPU instance data.
3786	*/
3787	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3788
3789	/**
3790	* PGMCPU Data (part of VMCPU).
3791	*/
3792	typedef struct PGMCPU
3793	{
3794	/** Offset to the VM structure. */
3795	int32_t offVM;
3796	/** Offset to the VMCPU structure. */
3797	int32_t offVCpu;
3798	/** Offset of the PGM structure relative to VMCPU. */
3799	int32_t offPGM;
3800	uint32_t uPadding0; /*< structure size alignment. /
3801
3802	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3803	/** Automatically tracked physical memory mapping set.
3804	* Ring-0 and strict raw-mode builds. */
3805	PGMMAPSET AutoSet;
3806	#endif
3807
3808	/** A20 gate mask.
3809	* Our current approach to A20 emulation is to let REM do it and don't bother
3810	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3811	* But whould need arrise, we'll subject physical addresses to this mask. */
3812	RTGCPHYS GCPhysA20Mask;
3813	/** A20 gate state - boolean! */
3814	bool fA20Enabled;
3815	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3816	bool fNoExecuteEnabled;
3817	/** Unused bits. */
3818	bool afUnused[2];
3819
3820	/** What needs syncing (PGM_SYNC_*).
3821	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3822	* PGMFlushTLB, and PGMR3Load. */
3823	uint32_t fSyncFlags;
3824
3825	/** The shadow paging mode. */
3826	PGMMODE enmShadowMode;
3827	/** The guest paging mode. */
3828	PGMMODE enmGuestMode;
3829	/** Guest mode data table index (PGM_TYPE_XXX). */
3830	uint8_t volatile idxGuestModeData;
3831	/** Shadow mode data table index (PGM_TYPE_XXX). */
3832	uint8_t volatile idxShadowModeData;
3833	/** Both mode data table index (complicated). */
3834	uint8_t volatile idxBothModeData;
3835	/** Alignment padding. */
3836	uint8_t abPadding[5];
3837
3838	/** The current physical address represented in the guest CR3 register. */
3839	RTGCPHYS GCPhysCR3;
3840
3841	/** @name 32-bit Guest Paging.
3842	* @{ */
3843	/** The guest's page directory, R3 pointer. */
3844	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3845	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3846	/** The guest's page directory, R0 pointer. */
3847	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3848	#endif
3849	/** The guest's page directory, static RC mapping. */
3850	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3851	/** Mask containing the MBZ bits of a big page PDE. */
3852	uint32_t fGst32BitMbzBigPdeMask;
3853	/** Set if the page size extension (PSE) is enabled. */
3854	bool fGst32BitPageSizeExtension;
3855	/** Alignment padding. */
3856	bool afAlignment2[3];
3857	/** @} */
3858
3859	/** @name PAE Guest Paging.
3860	* @{ */
3861	/** The guest's page directory pointer table, static RC mapping. */
3862	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3863	/** The guest's page directory pointer table, R3 pointer. */
3864	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3865	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3866	/** The guest's page directory pointer table, R0 pointer. */
3867	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3868	#endif
3869
3870	/** The guest's page directories, R3 pointers.
3871	* These are individual pointers and don't have to be adjacent.
3872	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3873	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3874	/** The guest's page directories, R0 pointers.
3875	* Same restrictions as apGstPaePDsR3. */
3876	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3877	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3878	#endif
3879	/** The guest's page directories, static GC mapping.
3880	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3881	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3882	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3883	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3884	* @todo Remove this and use aGstPaePdpeRegs instead? */
3885	RTGCPHYS aGCPhysGstPaePDs[4];
3886	/** The values of the 4 PDPE CPU registers (PAE). */
3887	X86PDPE aGstPaePdpeRegs[4];
3888	/** The physical addresses of the monitored guest page directories (PAE). */
3889	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3890	/** Mask containing the MBZ PTE bits. */
3891	uint64_t fGstPaeMbzPteMask;
3892	/** Mask containing the MBZ PDE bits. */
3893	uint64_t fGstPaeMbzPdeMask;
3894	/** Mask containing the MBZ big page PDE bits. */
3895	uint64_t fGstPaeMbzBigPdeMask;
3896	/** Mask containing the MBZ PDPE bits. */
3897	uint64_t fGstPaeMbzPdpeMask;
3898	/** @} */
3899
3900	/** @name AMD64 Guest Paging.
3901	* @{ */
3902	/** The guest's page directory pointer table, R3 pointer. */
3903	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3904	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3905	/** The guest's page directory pointer table, R0 pointer. */
3906	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3907	#else
3908	RTR0PTR alignment6b; /*< alignment equalizer. /
3909	#endif
3910	/** Mask containing the MBZ PTE bits. */
3911	uint64_t fGstAmd64MbzPteMask;
3912	/** Mask containing the MBZ PDE bits. */
3913	uint64_t fGstAmd64MbzPdeMask;
3914	/** Mask containing the MBZ big page PDE bits. */
3915	uint64_t fGstAmd64MbzBigPdeMask;
3916	/** Mask containing the MBZ PDPE bits. */
3917	uint64_t fGstAmd64MbzPdpeMask;
3918	/** Mask containing the MBZ big page PDPE bits. */
3919	uint64_t fGstAmd64MbzBigPdpeMask;
3920	/** Mask containing the MBZ PML4E bits. */
3921	uint64_t fGstAmd64MbzPml4eMask;
3922	/** Mask containing the PDPE bits that we shadow. */
3923	uint64_t fGstAmd64ShadowedPdpeMask;
3924	/** Mask containing the PML4E bits that we shadow. */
3925	uint64_t fGstAmd64ShadowedPml4eMask;
3926	/** @} */
3927
3928	/** @name PAE and AMD64 Guest Paging.
3929	* @{ */
3930	/** Mask containing the PTE bits that we shadow. */
3931	uint64_t fGst64ShadowedPteMask;
3932	/** Mask containing the PDE bits that we shadow. */
3933	uint64_t fGst64ShadowedPdeMask;
3934	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3935	uint64_t fGst64ShadowedBigPdeMask;
3936	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3937	uint64_t fGst64ShadowedBigPde4PteMask;
3938	/** @} */
3939
3940	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3941	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3942	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3943	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3944	/** Pointer to the page of the current active CR3 - RC Ptr. */
3945	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3946	/** Explicit alignment. */
3947	RTRCPTR alignment6;
3948	/** @} */
3949
3950	/** For saving stack space, the disassembler state is allocated here instead of
3951	* on the stack. */
3952	DISCPUSTATE DisState;
3953
3954	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3955	uint64_t cNetwareWp0Hacks;
3956
3957	/** Count the number of pgm pool access handler calls. */
3958	uint64_t cPoolAccessHandler;
3959
3960	/** @name Release Statistics
3961	* @{ */
3962	/** The number of times the guest has switched mode since last reset or statistics reset. */
3963	STAMCOUNTER cGuestModeChanges;
3964	/** The number of times the guest has switched mode since last reset or statistics reset. */
3965	STAMCOUNTER cA20Changes;
3966	/** @} */
3967
3968	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3969	/** @name Statistics
3970	* @{ */
3971	/** RC: Pointer to the statistics. */
3972	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3973	/** RC: Which statistic this \#PF should be attributed to. */
3974	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3975	/** R0: Pointer to the statistics. */
3976	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3977	/** R0: Which statistic this \#PF should be attributed to. */
3978	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3979	/** R3: Pointer to the statistics. */
3980	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3981	/** Alignment padding. */
3982	RTR3PTR pPaddingR3;
3983	/** @} */
3984	#endif /* VBOX_WITH_STATISTICS */
3985	} PGMCPU;
3986	/** Pointer to the per-cpu PGM data. */
3987	typedef PGMCPU *PPGMCPU;
3988
3989
3990	/** @name PGM::fSyncFlags Flags
3991	* @note Was part of saved state a long time ago.
3992	* @{
3993	*/
3994	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3995	/** Always sync CR3. */
3996	#define PGM_SYNC_ALWAYS RT_BIT(1)
3997	/** Check monitoring on next CR3 (re)load and invalidate page.
3998	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3999	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4000	/** Check guest mapping in SyncCR3. */
4001	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4002	/** Clear the page pool (a light weight flush). */
4003	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4004	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4005	/** @} */
4006
4007
4008	RT_C_DECLS_BEGIN
4009
4010	#if defined(VBOX_STRICT) && defined(IN_RING3)
4011	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4012	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4013	#else
4014	int pgmLock(PVM pVM);
4015	#endif
4016	void pgmUnlock(PVM pVM);
4017	/**
4018	* Asserts that the caller owns the PDM lock.
4019	* This is the internal variant of PGMIsLockOwner.
4020	* @param a_pVM Pointer to the VM.
4021	*/
4022	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4023	/**
4024	* Asserts that the caller owns the PDM lock.
4025	* This is the internal variant of PGMIsLockOwner.
4026	* @param a_pVM Pointer to the VM.
4027	* @param a_pVCpu The current CPU handle.
4028	*/
4029	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4030
4031	#ifndef PGM_WITHOUT_MAPPINGS
4032	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4033	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4034	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4035	int pgmMapResolveConflicts(PVM pVM);
4036	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4037	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4038	#endif /* !PGM_WITHOUT_MAPPINGS */
4039
4040	int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4041	RTRCPTR pvUserRC, R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
4042	int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4043	int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4044	int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4045	int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4046	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4047	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4048	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4049	#ifdef VBOX_WITH_RAW_MODE
4050	PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4051	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4052	# if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4053	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4054	# else
4055	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4056	# endif
4057	#endif /* VBOX_WITH_RAW_MODE */
4058	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4059	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4060
4061	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4062	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4063	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4064	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4065	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4066	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4067	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4068	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4069	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4070	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4071	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4072	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4073	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4074	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4075	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4076	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4077	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4078	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4079	#ifndef IN_RING3
4080	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4081	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4082	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4083	#endif
4084	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4085	PGMPAGETYPE enmNewType);
4086	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4087	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4088	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4089	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4090	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4091	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4092	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4093	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4094
4095	#ifdef IN_RING3
4096	void pgmR3PhysRelinkRamRanges(PVM pVM);
4097	int pgmR3PhysRamPreAllocate(PVM pVM);
4098	int pgmR3PhysRamReset(PVM pVM);
4099	int pgmR3PhysRomReset(PVM pVM);
4100	int pgmR3PhysRamZeroAll(PVM pVM);
4101	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4102	int pgmR3PhysRamTerm(PVM pVM);
4103	void pgmR3PhysRomTerm(PVM pVM);
4104	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4105
4106	int pgmR3PoolInit(PVM pVM);
4107	void pgmR3PoolRelocate(PVM pVM);
4108	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4109	void pgmR3PoolReset(PVM pVM);
4110	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4111	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4112	void pgmR3PoolWriteProtectPages(PVM pVM);
4113
4114	#endif /* IN_RING3 */
4115	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4116	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4117	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4118	# ifdef LOG_ENABLED
4119	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4120	# else
4121	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4122	# endif
4123	#endif
4124	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4125	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4126	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4127	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4128	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4129	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4130	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4131	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4132	int pgmPoolSyncCR3(PVMCPU pVCpu);
4133	bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4134	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4135	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4136	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4137	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4138	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4139	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4140	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4141	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4142	#ifndef IN_RING3
4143	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4144	#endif
4145
4146	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4147	void pgmPoolResetDirtyPages(PVM pVM);
4148	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4149
4150	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4151	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4152	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4153
4154	#ifndef PGM_WITHOUT_MAPPINGS
4155	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4156	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4157	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4158	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4159	#endif
4160
4161	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4162	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4163	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4164
4165	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4166	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4167	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4168	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4169	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4170	int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4171
4172	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4173	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4174	FNDBGCCMD pgmR3CmdShowSharedModules;
4175	# endif
4176
4177	void pgmLogState(PVM pVM);
4178
4179	RT_C_DECLS_END
4180
4181	/** @} */
4182
4183	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4184

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 80163

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