VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 80507

Last change on this file since 80507 was 80281, checked in by vboxsync, 5 years ago

VMM,++: Refactoring code to use VMMC & VMMCPUCC. bugref:9217
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1/* $Id: PGMInternal.h 80281 2019-08-15 07:29:37Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Indicates that there are no guest mappings in the shadow tables.
62 *
63 * Note! In ring-3 the macro is also used to exclude the managment of the
64 * intermediate context page tables. On 32-bit systems we use the intermediate
65 * context to support 64-bit guest execution. Thus, we cannot fully make it
66 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67 *
68 * In raw-mode context there are by design always guest mappings (the code is
69 * executed from one), while in ring-0 there are none at all. Neither context
70 * manages the page tables for intermediate switcher context, that's all done in
71 * ring-3.
72 *
73 * Update 6.1: It is always defined now, in pgm.h
74 */
75#if defined(IN_RING0) \
76 || ( !defined(VBOX_WITH_RAW_MODE) \
77 && ( HC_ARCH_BITS != 32 \
78 || !defined(VBOX_WITH_64_BITS_GUESTS) \
79 ) \
80 )
81# undef PGM_WITHOUT_MAPPINGS
82# define PGM_WITHOUT_MAPPINGS
83#endif
84
85/**
86 * Check and skip global PDEs for non-global flushes
87 */
88#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90/**
91 * Optimization for PAE page tables that are modified often
92 */
93//#if 0 /* disabled again while debugging */
94#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95//#endif
96
97/**
98 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
99 */
100#define PGM_WITH_LARGE_PAGES
101
102/**
103 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
104 * VMX_EXIT_EPT_MISCONFIG.
105 */
106#define PGM_WITH_MMIO_OPTIMIZATIONS
107
108/**
109 * Sync N pages instead of a whole page table
110 */
111#define PGM_SYNC_N_PAGES
112
113/**
114 * Number of pages to sync during a page fault
115 *
116 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118 *
119 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120 * world switch overhead, so let's sync more.
121 */
122# ifdef IN_RING0
123/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125 * but ~5% fewer faults.
126 */
127# define PGM_SYNC_NR_PAGES 32
128#else
129# define PGM_SYNC_NR_PAGES 8
130#endif
131
132/**
133 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134 */
135#define PGM_MAX_PHYSCACHE_ENTRIES 64
136#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139/** @def PGMPOOL_CFG_MAX_GROW
140 * The maximum number of pages to add to the pool in one go.
141 */
142#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
143
144/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
146 */
147#ifdef VBOX_STRICT
148# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149#endif
150
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153#ifdef DOXYGEN_RUNNING
154# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155#endif
156
157/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158 * Enables real write monitoring of pages, i.e. mapping them read-only and
159 * only making them writable when getting a write access \#PF. */
160#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** Mapping (hypervisor allocated pagetable). */
173#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174/** @} */
175
176/** @name Page directory flags.
177 * These are placed in the three bits available for system programs in
178 * the page directory entries.
179 * @{ */
180/** Indicates the original entry was a big page.
181 * @remarks This is currently only used for statistics and can be recycled. */
182#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED_32BIT 6
213#define PGM_TYPE_NESTED_PAE 7
214#define PGM_TYPE_NESTED_AMD64 8
215#define PGM_TYPE_EPT 9
216#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
217#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
218#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
219/** @} */
220
221/** Macro for checking if the guest is using paging.
222 * @param uGstType PGM_TYPE_*
223 * @param uShwType PGM_TYPE_*
224 * @remark ASSUMES certain order of the PGM_TYPE_* values.
225 */
226#define PGM_WITH_PAGING(uGstType, uShwType) \
227 ( (uGstType) >= PGM_TYPE_32BIT \
228 && (uShwType) < PGM_TYPE_NESTED_32BIT)
229
230/** Macro for checking if the guest supports the NX bit.
231 * @param uGstType PGM_TYPE_*
232 * @param uShwType PGM_TYPE_*
233 * @remark ASSUMES certain order of the PGM_TYPE_* values.
234 */
235#define PGM_WITH_NX(uGstType, uShwType) \
236 ( (uGstType) >= PGM_TYPE_PAE \
237 && (uShwType) < PGM_TYPE_NESTED_32BIT)
238
239/** Macro for checking for nested or EPT.
240 * @param uType PGM_TYPE_*
241 */
242#define PGM_TYPE_IS_NESTED(uType) \
243 ( (uType) == PGM_TYPE_NESTED_32BIT \
244 || (uType) == PGM_TYPE_NESTED_PAE \
245 || (uType) == PGM_TYPE_NESTED_AMD64)
246
247/** Macro for checking for nested or EPT.
248 * @param uType PGM_TYPE_*
249 */
250#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
251 ( (uType) == PGM_TYPE_NESTED_32BIT \
252 || (uType) == PGM_TYPE_NESTED_PAE \
253 || (uType) == PGM_TYPE_NESTED_AMD64 \
254 || (uType) == PGM_TYPE_EPT)
255
256
257
258/** @def PGM_HCPHYS_2_PTR
259 * Maps a HC physical page pool address to a virtual address.
260 *
261 * @returns VBox status code.
262 * @param pVM The cross context VM structure.
263 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
264 * @param HCPhys The HC physical address to map to a virtual one.
265 * @param ppv Where to store the virtual address. No need to cast
266 * this.
267 *
268 * @remark Use with care as we don't have so much dynamic mapping space in
269 * ring-0 on 32-bit darwin and in RC.
270 * @remark There is no need to assert on the result.
271 */
272#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
273# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
274 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
275#else
276# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
277 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
278#endif
279
280/** @def PGM_GCPHYS_2_PTR_V2
281 * Maps a GC physical page address to a virtual address.
282 *
283 * @returns VBox status code.
284 * @param pVM The cross context VM structure.
285 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark Use with care as we don't have so much dynamic mapping space in
290 * ring-0 on 32-bit darwin and in RC.
291 * @remark There is no need to assert on the result.
292 */
293#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
294# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
295 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
296#else
297# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
298 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
299#endif
300
301/** @def PGM_GCPHYS_2_PTR
302 * Maps a GC physical page address to a virtual address.
303 *
304 * @returns VBox status code.
305 * @param pVM The cross context VM structure.
306 * @param GCPhys The GC physical address to map to a virtual one.
307 * @param ppv Where to store the virtual address. No need to cast this.
308 *
309 * @remark Use with care as we don't have so much dynamic mapping space in
310 * ring-0 on 32-bit darwin and in RC.
311 * @remark There is no need to assert on the result.
312 */
313#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
314
315/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
316 * Maps a GC physical page address to a virtual address.
317 *
318 * @returns VBox status code.
319 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
320 * @param GCPhys The GC physical address to map to a virtual one.
321 * @param ppv Where to store the virtual address. No need to cast this.
322 *
323 * @remark Use with care as we don't have so much dynamic mapping space in
324 * ring-0 on 32-bit darwin and in RC.
325 * @remark There is no need to assert on the result.
326 */
327#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
328
329/** @def PGM_GCPHYS_2_PTR_EX
330 * Maps a unaligned GC physical page address to a virtual address.
331 *
332 * @returns VBox status code.
333 * @param pVM The cross context VM structure.
334 * @param GCPhys The GC physical address to map to a virtual one.
335 * @param ppv Where to store the virtual address. No need to cast this.
336 *
337 * @remark Use with care as we don't have so much dynamic mapping space in
338 * ring-0 on 32-bit darwin and in RC.
339 * @remark There is no need to assert on the result.
340 */
341#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
342# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
343 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
344#else
345# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
346 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
347#endif
348
349/** @def PGM_DYNMAP_UNUSED_HINT
350 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
351 * is no longer used.
352 *
353 * For best effect only apply this to the page that was mapped most recently.
354 *
355 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
356 * @param pvPage The pool page.
357 */
358#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
359# ifdef LOG_ENABLED
360# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
361# else
362# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
363# endif
364#else
365# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
366#endif
367
368/** @def PGM_DYNMAP_UNUSED_HINT_VM
369 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
370 * is no longer used.
371 *
372 * For best effect only apply this to the page that was mapped most recently.
373 *
374 * @param pVM The cross context VM structure.
375 * @param pvPage The pool page.
376 */
377#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
378
379
380/** @def PGM_INVL_PG
381 * Invalidates a page.
382 *
383 * @param pVCpu The cross context virtual CPU structure.
384 * @param GCVirt The virtual address of the page to invalidate.
385 */
386#ifdef IN_RING0
387# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
388#elif defined(IN_RING3)
389# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
390#else
391# error "Not IN_RING0 or IN_RING3!"
392#endif
393
394/** @def PGM_INVL_PG_ALL_VCPU
395 * Invalidates a page on all VCPUs
396 *
397 * @param pVM The cross context VM structure.
398 * @param GCVirt The virtual address of the page to invalidate.
399 */
400#ifdef IN_RING0
401# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
402#else
403# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
404#endif
405
406/** @def PGM_INVL_BIG_PG
407 * Invalidates a 4MB page directory entry.
408 *
409 * @param pVCpu The cross context virtual CPU structure.
410 * @param GCVirt The virtual address within the page directory to invalidate.
411 */
412#ifdef IN_RING0
413# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
414#else
415# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
416#endif
417
418/** @def PGM_INVL_VCPU_TLBS()
419 * Invalidates the TLBs of the specified VCPU
420 *
421 * @param pVCpu The cross context virtual CPU structure.
422 */
423#ifdef IN_RING0
424# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
425#else
426# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
427#endif
428
429/** @def PGM_INVL_ALL_VCPU_TLBS()
430 * Invalidates the TLBs of all VCPUs
431 *
432 * @param pVM The cross context VM structure.
433 */
434#ifdef IN_RING0
435# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
436#else
437# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
438#endif
439
440
441/** @name Safer Shadow PAE PT/PTE
442 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
443 * present.
444 *
445 * @{
446 */
447#if 1
448/**
449 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
450 * invalid entries for present.
451 * @sa X86PTEPAE.
452 */
453typedef union PGMSHWPTEPAE
454{
455 /** Unsigned integer view */
456 X86PGPAEUINT uCareful;
457 /* Not other views. */
458} PGMSHWPTEPAE;
459
460# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
461# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
462# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
463# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
464# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
465# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
466# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
467# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
468# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
469# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
470# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
471# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
472# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
473# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
474# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
475# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
476
477/**
478 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
479 * invalid entries for present.
480 * @sa X86PTPAE.
481 */
482typedef struct PGMSHWPTPAE
483{
484 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
485} PGMSHWPTPAE;
486
487#else
488typedef X86PTEPAE PGMSHWPTEPAE;
489typedef X86PTPAE PGMSHWPTPAE;
490# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
491# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
492# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
493# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
494# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
495# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
496# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
497# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
498# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
499# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
500# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
501# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
502# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
503# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
504# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
505# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
506
507#endif
508
509/** Pointer to a shadow PAE PTE. */
510typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
511/** Pointer to a const shadow PAE PTE. */
512typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
513
514/** Pointer to a shadow PAE page table. */
515typedef PGMSHWPTPAE *PPGMSHWPTPAE;
516/** Pointer to a const shadow PAE page table. */
517typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
518/** @} */
519
520#ifndef PGM_WITHOUT_MAPPINGS
521
522/** Size of the GCPtrConflict array in PGMMAPPING.
523 * @remarks Must be a power of two. */
524# define PGMMAPPING_CONFLICT_MAX 8
525
526/**
527 * Structure for tracking GC Mappings.
528 *
529 * This structure is used by linked list in both GC and HC.
530 */
531typedef struct PGMMAPPING
532{
533 /** Pointer to next entry. */
534 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
535 /** Pointer to next entry. */
536 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
537 /** Indicate whether this entry is finalized. */
538 bool fFinalized;
539 bool afPadding[7];
540 /** Start Virtual address. */
541 RTGCPTR GCPtr;
542 /** Last Virtual address (inclusive). */
543 RTGCPTR GCPtrLast;
544 /** Range size (bytes). */
545 RTGCPTR cb;
546 /** Pointer to relocation callback function. */
547 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
548 /** User argument to the callback. */
549 R3PTRTYPE(void *) pvUser;
550 /** Mapping description / name. For easing debugging. */
551 R3PTRTYPE(const char *) pszDesc;
552 /** Last 8 addresses that caused conflicts. */
553 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
554 /** Number of conflicts for this hypervisor mapping. */
555 uint32_t cConflicts;
556 /** Number of page tables. */
557 uint32_t cPTs;
558
559 /** Array of page table mapping data. Each entry
560 * describes one page table. The array can be longer
561 * than the declared length.
562 */
563 struct
564 {
565 /** The HC physical address of the page table. */
566 RTHCPHYS HCPhysPT;
567 /** The HC physical address of the first PAE page table. */
568 RTHCPHYS HCPhysPaePT0;
569 /** The HC physical address of the second PAE page table. */
570 RTHCPHYS HCPhysPaePT1;
571 /** The HC virtual address of the 32-bit page table. */
572 R3PTRTYPE(PX86PT) pPTR3;
573 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
574 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
575 /** The R0 virtual address of the 32-bit page table. */
576 R0PTRTYPE(PX86PT) pPTR0;
577 /** The R0 virtual address of the two PAE page table. */
578 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
579 } aPTs[1];
580} PGMMAPPING;
581/** Pointer to structure for tracking GC Mappings. */
582typedef struct PGMMAPPING *PPGMMAPPING;
583
584#endif /* !PGM_WITHOUT_MAPPINGS */
585
586
587/**
588 * Physical page access handler type registration.
589 */
590typedef struct PGMPHYSHANDLERTYPEINT
591{
592 /** Number of references. */
593 uint32_t volatile cRefs;
594 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
595 uint32_t u32Magic;
596 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
597 RTLISTOFF32NODE ListNode;
598 /** The kind of accesses we're handling. */
599 PGMPHYSHANDLERKIND enmKind;
600 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
601 uint32_t uState;
602 /** Pointer to R3 callback function. */
603 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
604 /** Pointer to R0 callback function. */
605 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
606 /** Pointer to R0 callback function for \#PFs. */
607 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
608 /** Description / Name. For easing debugging. */
609 R3PTRTYPE(const char *) pszDesc;
610} PGMPHYSHANDLERTYPEINT;
611/** Pointer to a physical access handler type registration. */
612typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
613/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
614#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
615/** Magic value for the physical handler callbacks. */
616#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
617
618/**
619 * Converts a handle to a pointer.
620 * @returns PPGMPHYSHANDLERTYPEINT
621 * @param a_pVM The cross context VM structure.
622 * @param a_hType Physical access handler type handle.
623 */
624#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
625
626
627/**
628 * Physical page access handler structure.
629 *
630 * This is used to keep track of physical address ranges
631 * which are being monitored in some kind of way.
632 */
633typedef struct PGMPHYSHANDLER
634{
635 AVLROGCPHYSNODECORE Core;
636 /** Number of pages to update. */
637 uint32_t cPages;
638 /** Set if we have pages that have been aliased. */
639 uint32_t cAliasedPages;
640 /** Set if we have pages that have temporarily been disabled. */
641 uint32_t cTmpOffPages;
642 /** Registered handler type handle (heap offset). */
643 PGMPHYSHANDLERTYPE hType;
644 /** User argument for R3 handlers. */
645 R3PTRTYPE(void *) pvUserR3;
646 /** User argument for R0 handlers. */
647 R0PTRTYPE(void *) pvUserR0;
648 /** Description / Name. For easing debugging. */
649 R3PTRTYPE(const char *) pszDesc;
650#ifdef VBOX_WITH_STATISTICS
651 /** Profiling of this handler. */
652 STAMPROFILE Stat;
653#endif
654} PGMPHYSHANDLER;
655/** Pointer to a physical page access handler structure. */
656typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
657
658/**
659 * Gets the type record for a physical handler (no reference added).
660 * @returns PPGMPHYSHANDLERTYPEINT
661 * @param a_pVM The cross context VM structure.
662 * @param a_pPhysHandler Pointer to the physical handler structure
663 * (PGMPHYSHANDLER).
664 */
665#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
666
667
668/**
669 * A Physical Guest Page tracking structure.
670 *
671 * The format of this structure is complicated because we have to fit a lot
672 * of information into as few bits as possible. The format is also subject
673 * to change (there is one coming up soon). Which means that for we'll be
674 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
675 * accesses to the structure.
676 */
677typedef union PGMPAGE
678{
679 /** Structured view. */
680 struct
681 {
682 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
683 uint64_t u2HandlerPhysStateY : 2;
684 /** 3:2 - Paging structure needed to map the page
685 * (PGM_PAGE_PDE_TYPE_*). */
686 uint64_t u2PDETypeY : 2;
687 /** 4 - Unused (was used by FTE for dirty tracking). */
688 uint64_t fUnused1 : 1;
689 /** 5 - Flag indicating that a write monitored page was written to
690 * when set. */
691 uint64_t fWrittenToY : 1;
692 /** 7:6 - Unused. */
693 uint64_t u2Unused0 : 2;
694 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
695 uint64_t u2Unused1 : 2;
696 /** 11:10 - NEM state bits. */
697 uint64_t u2NemStateY : 2;
698 /** 12:48 - The host physical frame number (shift left to get the
699 * address). */
700 uint64_t HCPhysFN : 36;
701 /** 50:48 - The page state. */
702 uint64_t uStateY : 3;
703 /** 51:53 - The page type (PGMPAGETYPE). */
704 uint64_t uTypeY : 3;
705 /** 63:54 - PTE index for usage tracking (page pool). */
706 uint64_t u10PteIdx : 10;
707
708 /** The GMM page ID.
709 * @remarks In the current implementation, MMIO2 and pages aliased to
710 * MMIO2 pages will be exploiting this field to calculate the
711 * ring-3 mapping address corresponding to the page.
712 * Later we may consider including MMIO2 management into GMM. */
713 uint32_t idPage;
714 /** Usage tracking (page pool). */
715 uint16_t u16TrackingY;
716 /** The number of read locks on this page. */
717 uint8_t cReadLocksY;
718 /** The number of write locks on this page. */
719 uint8_t cWriteLocksY;
720 } s;
721
722 /** 64-bit integer view. */
723 uint64_t au64[2];
724 /** 16-bit view. */
725 uint32_t au32[4];
726 /** 16-bit view. */
727 uint16_t au16[8];
728 /** 8-bit view. */
729 uint8_t au8[16];
730} PGMPAGE;
731AssertCompileSize(PGMPAGE, 16);
732/** Pointer to a physical guest page. */
733typedef PGMPAGE *PPGMPAGE;
734/** Pointer to a const physical guest page. */
735typedef const PGMPAGE *PCPGMPAGE;
736/** Pointer to a physical guest page pointer. */
737typedef PPGMPAGE *PPPGMPAGE;
738
739
740/**
741 * Clears the page structure.
742 * @param a_pPage Pointer to the physical guest page tracking structure.
743 */
744#define PGM_PAGE_CLEAR(a_pPage) \
745 do { \
746 (a_pPage)->au64[0] = 0; \
747 (a_pPage)->au64[1] = 0; \
748 } while (0)
749
750/**
751 * Initializes the page structure.
752 * @param a_pPage Pointer to the physical guest page tracking structure.
753 * @param a_HCPhys The host physical address of the page.
754 * @param a_idPage The (GMM) page ID of the page.
755 * @param a_uType The page type (PGMPAGETYPE).
756 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
757 */
758#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
759 do { \
760 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
761 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
762 (a_pPage)->au64[0] = SetHCPhysTmp; \
763 (a_pPage)->au64[1] = 0; \
764 (a_pPage)->s.idPage = (a_idPage); \
765 (a_pPage)->s.uStateY = (a_uState); \
766 (a_pPage)->s.uTypeY = (a_uType); \
767 } while (0)
768
769/**
770 * Initializes the page structure of a ZERO page.
771 * @param a_pPage Pointer to the physical guest page tracking structure.
772 * @param a_pVM The VM handle (for getting the zero page address).
773 * @param a_uType The page type (PGMPAGETYPE).
774 */
775#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
776 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
777
778
779/** @name The Page state, PGMPAGE::uStateY.
780 * @{ */
781/** The zero page.
782 * This is a per-VM page that's never ever mapped writable. */
783#define PGM_PAGE_STATE_ZERO 0U
784/** A allocated page.
785 * This is a per-VM page allocated from the page pool (or wherever
786 * we get MMIO2 pages from if the type is MMIO2).
787 */
788#define PGM_PAGE_STATE_ALLOCATED 1U
789/** A allocated page that's being monitored for writes.
790 * The shadow page table mappings are read-only. When a write occurs, the
791 * fWrittenTo member is set, the page remapped as read-write and the state
792 * moved back to allocated. */
793#define PGM_PAGE_STATE_WRITE_MONITORED 2U
794/** The page is shared, aka. copy-on-write.
795 * This is a page that's shared with other VMs. */
796#define PGM_PAGE_STATE_SHARED 3U
797/** The page is ballooned, so no longer available for this VM. */
798#define PGM_PAGE_STATE_BALLOONED 4U
799/** @} */
800
801
802/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
803#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
804# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
805#else
806# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
807#endif
808
809/**
810 * Gets the page state.
811 * @returns page state (PGM_PAGE_STATE_*).
812 * @param a_pPage Pointer to the physical guest page tracking structure.
813 *
814 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
815 * builds.
816 */
817#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
818#if defined(__GNUC__) && defined(VBOX_STRICT)
819# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
820#else
821# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
822#endif
823
824/**
825 * Sets the page state.
826 * @param a_pVM The VM handle, only used for lock ownership assertions.
827 * @param a_pPage Pointer to the physical guest page tracking structure.
828 * @param a_uState The new page state.
829 */
830#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
831 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
832
833
834/**
835 * Gets the host physical address of the guest page.
836 * @returns host physical address (RTHCPHYS).
837 * @param a_pPage Pointer to the physical guest page tracking structure.
838 *
839 * @remarks In strict builds on gcc platforms, this macro will make some ugly
840 * assumption about a valid pVM variable/parameter being in the
841 * current context. It will use this pVM variable to assert that the
842 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
843 * pVM is not around.
844 */
845#if 0
846# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
847# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
848#else
849# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
850# if defined(__GNUC__) && defined(VBOX_STRICT)
851# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
852# else
853# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
854# endif
855#endif
856
857/**
858 * Sets the host physical address of the guest page.
859 *
860 * @param a_pVM The VM handle, only used for lock ownership assertions.
861 * @param a_pPage Pointer to the physical guest page tracking structure.
862 * @param a_HCPhys The new host physical address.
863 */
864#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
865 do { \
866 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
867 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
868 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
869 PGM_PAGE_ASSERT_LOCK(a_pVM); \
870 } while (0)
871
872/**
873 * Get the Page ID.
874 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
875 * @param a_pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
878
879/**
880 * Sets the Page ID.
881 * @param a_pVM The VM handle, only used for lock ownership assertions.
882 * @param a_pPage Pointer to the physical guest page tracking structure.
883 * @param a_idPage The new page ID.
884 */
885#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
886 do { \
887 (a_pPage)->s.idPage = (a_idPage); \
888 PGM_PAGE_ASSERT_LOCK(a_pVM); \
889 } while (0)
890
891/**
892 * Get the Chunk ID.
893 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
894 * @param a_pPage Pointer to the physical guest page tracking structure.
895 */
896#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
897
898/**
899 * Get the index of the page within the allocation chunk.
900 * @returns The page index.
901 * @param a_pPage Pointer to the physical guest page tracking structure.
902 */
903#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
904
905/**
906 * Gets the page type.
907 * @returns The page type.
908 * @param a_pPage Pointer to the physical guest page tracking structure.
909 *
910 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
911 * builds.
912 */
913#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
914#if defined(__GNUC__) && defined(VBOX_STRICT)
915# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
916#else
917# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
918#endif
919
920/**
921 * Sets the page type.
922 *
923 * @param a_pVM The VM handle, only used for lock ownership assertions.
924 * @param a_pPage Pointer to the physical guest page tracking structure.
925 * @param a_enmType The new page type (PGMPAGETYPE).
926 */
927#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
928 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
929
930/**
931 * Gets the page table index
932 * @returns The page table index.
933 * @param a_pPage Pointer to the physical guest page tracking structure.
934 */
935#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
936
937/**
938 * Sets the page table index.
939 * @param a_pVM The VM handle, only used for lock ownership assertions.
940 * @param a_pPage Pointer to the physical guest page tracking structure.
941 * @param a_iPte New page table index.
942 */
943#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
944 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
945
946/**
947 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
948 * @returns true/false.
949 * @param a_pPage Pointer to the physical guest page tracking structure.
950 */
951#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
952
953/**
954 * Checks if the page is marked for MMIO, including both aliases.
955 * @returns true/false.
956 * @param a_pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
959 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
960 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
961 )
962
963/**
964 * Checks if the page is marked for MMIO, including special aliases.
965 * @returns true/false.
966 * @param a_pPage Pointer to the physical guest page tracking structure.
967 */
968#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
969 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
970
971/**
972 * Checks if the page is a special aliased MMIO page.
973 * @returns true/false.
974 * @param a_pPage Pointer to the physical guest page tracking structure.
975 */
976#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
977
978/**
979 * Checks if the page is backed by the ZERO page.
980 * @returns true/false.
981 * @param a_pPage Pointer to the physical guest page tracking structure.
982 */
983#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
984
985/**
986 * Checks if the page is backed by a SHARED page.
987 * @returns true/false.
988 * @param a_pPage Pointer to the physical guest page tracking structure.
989 */
990#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
991
992/**
993 * Checks if the page is ballooned.
994 * @returns true/false.
995 * @param a_pPage Pointer to the physical guest page tracking structure.
996 */
997#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
998
999/**
1000 * Checks if the page is allocated.
1001 * @returns true/false.
1002 * @param a_pPage Pointer to the physical guest page tracking structure.
1003 */
1004#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1005
1006/**
1007 * Marks the page as written to (for GMM change monitoring).
1008 * @param a_pVM The VM handle, only used for lock ownership assertions.
1009 * @param a_pPage Pointer to the physical guest page tracking structure.
1010 */
1011#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1012 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1013
1014/**
1015 * Clears the written-to indicator.
1016 * @param a_pVM The VM handle, only used for lock ownership assertions.
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1020 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1021
1022/**
1023 * Checks if the page was marked as written-to.
1024 * @returns true/false.
1025 * @param a_pPage Pointer to the physical guest page tracking structure.
1026 */
1027#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1028
1029
1030/** @name PT usage values (PGMPAGE::u2PDEType).
1031 *
1032 * @{ */
1033/** Either as a PT or PDE. */
1034#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1035/** Must use a page table to map the range. */
1036#define PGM_PAGE_PDE_TYPE_PT 1
1037/** Can use a page directory entry to map the continuous range. */
1038#define PGM_PAGE_PDE_TYPE_PDE 2
1039/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1040#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1041/** @} */
1042
1043/**
1044 * Set the PDE type of the page
1045 * @param a_pVM The VM handle, only used for lock ownership assertions.
1046 * @param a_pPage Pointer to the physical guest page tracking structure.
1047 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1048 */
1049#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1050 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1051
1052/**
1053 * Checks if the page was marked being part of a large page
1054 * @returns true/false.
1055 * @param a_pPage Pointer to the physical guest page tracking structure.
1056 */
1057#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1058
1059/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1060 *
1061 * @remarks The values are assigned in order of priority, so we can calculate
1062 * the correct state for a page with different handlers installed.
1063 * @{ */
1064/** No handler installed. */
1065#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1066/** Monitoring is temporarily disabled. */
1067#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1068/** Write access is monitored. */
1069#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1070/** All access is monitored. */
1071#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1072/** @} */
1073
1074/**
1075 * Gets the physical access handler state of a page.
1076 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1077 * @param a_pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1080
1081/**
1082 * Sets the physical access handler state of a page.
1083 * @param a_pPage Pointer to the physical guest page tracking structure.
1084 * @param a_uState The new state value.
1085 */
1086#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1087 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1088
1089/**
1090 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1091 * @returns true/false
1092 * @param a_pPage Pointer to the physical guest page tracking structure.
1093 */
1094#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1095 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1096
1097/**
1098 * Checks if the page has any active physical access handlers.
1099 * @returns true/false
1100 * @param a_pPage Pointer to the physical guest page tracking structure.
1101 */
1102#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1103 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1104
1105/**
1106 * Checks if the page has any access handlers, including temporarily disabled ones.
1107 * @returns true/false
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 */
1110#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1111 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1112
1113/**
1114 * Checks if the page has any active access handlers.
1115 * @returns true/false
1116 * @param a_pPage Pointer to the physical guest page tracking structure.
1117 */
1118#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1119 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1120
1121/**
1122 * Checks if the page has any active access handlers catching all accesses.
1123 * @returns true/false
1124 * @param a_pPage Pointer to the physical guest page tracking structure.
1125 */
1126#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1127 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1128
1129
1130/** @def PGM_PAGE_GET_TRACKING
1131 * Gets the packed shadow page pool tracking data associated with a guest page.
1132 * @returns uint16_t containing the data.
1133 * @param a_pPage Pointer to the physical guest page tracking structure.
1134 */
1135#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1136#if defined(__GNUC__) && defined(VBOX_STRICT)
1137# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1138#else
1139# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1140#endif
1141
1142/** @def PGM_PAGE_SET_TRACKING
1143 * Sets the packed shadow page pool tracking data associated with a guest page.
1144 * @param a_pVM The VM handle, only used for lock ownership assertions.
1145 * @param a_pPage Pointer to the physical guest page tracking structure.
1146 * @param a_u16TrackingData The tracking data to store.
1147 */
1148#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1149 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1150
1151/** @def PGM_PAGE_GET_TD_CREFS
1152 * Gets the @a cRefs tracking data member.
1153 * @returns cRefs.
1154 * @param a_pPage Pointer to the physical guest page tracking structure.
1155 */
1156#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1157 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1158#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1159 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1160
1161/** @def PGM_PAGE_GET_TD_IDX
1162 * Gets the @a idx tracking data member.
1163 * @returns idx.
1164 * @param a_pPage Pointer to the physical guest page tracking structure.
1165 */
1166#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1167 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1168#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1169 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1170
1171
1172/** Max number of locks on a page. */
1173#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1174
1175/** Get the read lock count.
1176 * @returns count.
1177 * @param a_pPage Pointer to the physical guest page tracking structure.
1178 */
1179#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1180
1181/** Get the write lock count.
1182 * @returns count.
1183 * @param a_pPage Pointer to the physical guest page tracking structure.
1184 */
1185#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1186
1187/** Decrement the read lock counter.
1188 * @param a_pPage Pointer to the physical guest page tracking structure.
1189 */
1190#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1191
1192/** Decrement the write lock counter.
1193 * @param a_pPage Pointer to the physical guest page tracking structure.
1194 */
1195#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1196
1197/** Increment the read lock counter.
1198 * @param a_pPage Pointer to the physical guest page tracking structure.
1199 */
1200#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1201
1202/** Increment the write lock counter.
1203 * @param a_pPage Pointer to the physical guest page tracking structure.
1204 */
1205#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1206
1207
1208/** Gets the NEM state.
1209 * @returns NEM state value (two bits).
1210 * @param a_pPage Pointer to the physical guest page tracking structure.
1211 */
1212#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1213
1214/** Sets the NEM state.
1215 * @param a_pPage Pointer to the physical guest page tracking structure.
1216 * @param a_u2State The NEM state value (specific to NEM impl.).
1217 */
1218#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1219 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1220
1221
1222#if 0
1223/** Enables sanity checking of write monitoring using CRC-32. */
1224# define PGMLIVESAVERAMPAGE_WITH_CRC32
1225#endif
1226
1227/**
1228 * Per page live save tracking data.
1229 */
1230typedef struct PGMLIVESAVERAMPAGE
1231{
1232 /** Number of times it has been dirtied. */
1233 uint32_t cDirtied : 24;
1234 /** Whether it is currently dirty. */
1235 uint32_t fDirty : 1;
1236 /** Ignore the page.
1237 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1238 * deal with these after pausing the VM and DevPCI have said it bit about
1239 * remappings. */
1240 uint32_t fIgnore : 1;
1241 /** Was a ZERO page last time around. */
1242 uint32_t fZero : 1;
1243 /** Was a SHARED page last time around. */
1244 uint32_t fShared : 1;
1245 /** Whether the page is/was write monitored in a previous pass. */
1246 uint32_t fWriteMonitored : 1;
1247 /** Whether the page is/was write monitored earlier in this pass. */
1248 uint32_t fWriteMonitoredJustNow : 1;
1249 /** Bits reserved for future use. */
1250 uint32_t u2Reserved : 2;
1251#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1252 /** CRC-32 for the page. This is for internal consistency checks. */
1253 uint32_t u32Crc;
1254#endif
1255} PGMLIVESAVERAMPAGE;
1256#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1258#else
1259AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1260#endif
1261/** Pointer to the per page live save tracking data. */
1262typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1263
1264/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1265#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1266
1267
1268/**
1269 * RAM range for GC Phys to HC Phys conversion.
1270 *
1271 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1272 * conversions too, but we'll let MM handle that for now.
1273 *
1274 * This structure is used by linked lists in both GC and HC.
1275 */
1276typedef struct PGMRAMRANGE
1277{
1278 /** Start of the range. Page aligned. */
1279 RTGCPHYS GCPhys;
1280 /** Size of the range. (Page aligned of course). */
1281 RTGCPHYS cb;
1282 /** Pointer to the next RAM range - for R3. */
1283 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1284 /** Pointer to the next RAM range - for R0. */
1285 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1286 /** PGM_RAM_RANGE_FLAGS_* flags. */
1287 uint32_t fFlags;
1288 uint32_t fPadding1;
1289 /** Last address in the range (inclusive). Page aligned (-1). */
1290 RTGCPHYS GCPhysLast;
1291 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1292 R3PTRTYPE(void *) pvR3;
1293 /** Live save per page tracking data. */
1294 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1295 /** The range description. */
1296 R3PTRTYPE(const char *) pszDesc;
1297 /** Pointer to self - R0 pointer. */
1298 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1299
1300 /** Pointer to the left search three node - ring-3 context. */
1301 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1302 /** Pointer to the right search three node - ring-3 context. */
1303 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1304 /** Pointer to the left search three node - ring-0 context. */
1305 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1306 /** Pointer to the right search three node - ring-0 context. */
1307 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1308
1309 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1310#if HC_ARCH_BITS == 32
1311 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1312#endif
1313 /** Array of physical guest page tracking structures. */
1314 PGMPAGE aPages[1];
1315} PGMRAMRANGE;
1316/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1317typedef PGMRAMRANGE *PPGMRAMRANGE;
1318
1319/** @name PGMRAMRANGE::fFlags
1320 * @{ */
1321/** The RAM range is floating around as an independent guest mapping. */
1322#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1323/** Ad hoc RAM range for an ROM mapping. */
1324#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1325/** Ad hoc RAM range for an MMIO mapping. */
1326#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1327/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1328#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1329/** @} */
1330
1331/** Tests if a RAM range is an ad hoc one or not.
1332 * @returns true/false.
1333 * @param pRam The RAM range.
1334 */
1335#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1336 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1337
1338/** The number of entries in the RAM range TLBs (there is one for each
1339 * context). Must be a power of two. */
1340#define PGM_RAMRANGE_TLB_ENTRIES 8
1341
1342/**
1343 * Calculates the RAM range TLB index for the physical address.
1344 *
1345 * @returns RAM range TLB index.
1346 * @param a_GCPhys The guest physical address.
1347 */
1348#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1349
1350
1351
1352/**
1353 * Per page tracking structure for ROM image.
1354 *
1355 * A ROM image may have a shadow page, in which case we may have two pages
1356 * backing it. This structure contains the PGMPAGE for both while
1357 * PGMRAMRANGE have a copy of the active one. It is important that these
1358 * aren't out of sync in any regard other than page pool tracking data.
1359 */
1360typedef struct PGMROMPAGE
1361{
1362 /** The page structure for the virgin ROM page. */
1363 PGMPAGE Virgin;
1364 /** The page structure for the shadow RAM page. */
1365 PGMPAGE Shadow;
1366 /** The current protection setting. */
1367 PGMROMPROT enmProt;
1368 /** Live save status information. Makes use of unused alignment space. */
1369 struct
1370 {
1371 /** The previous protection value. */
1372 uint8_t u8Prot;
1373 /** Written to flag set by the handler. */
1374 bool fWrittenTo;
1375 /** Whether the shadow page is dirty or not. */
1376 bool fDirty;
1377 /** Whether it was dirtied in the recently. */
1378 bool fDirtiedRecently;
1379 } LiveSave;
1380} PGMROMPAGE;
1381AssertCompileSizeAlignment(PGMROMPAGE, 8);
1382/** Pointer to a ROM page tracking structure. */
1383typedef PGMROMPAGE *PPGMROMPAGE;
1384
1385
1386/**
1387 * A registered ROM image.
1388 *
1389 * This is needed to keep track of ROM image since they generally intrude
1390 * into a PGMRAMRANGE. It also keeps track of additional info like the
1391 * two page sets (read-only virgin and read-write shadow), the current
1392 * state of each page.
1393 *
1394 * Because access handlers cannot easily be executed in a different
1395 * context, the ROM ranges needs to be accessible and in all contexts.
1396 */
1397typedef struct PGMROMRANGE
1398{
1399 /** Pointer to the next range - R3. */
1400 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1401 /** Pointer to the next range - R0. */
1402 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1403 /** Address of the range. */
1404 RTGCPHYS GCPhys;
1405 /** Address of the last byte in the range. */
1406 RTGCPHYS GCPhysLast;
1407 /** Size of the range. */
1408 RTGCPHYS cb;
1409 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1410 uint32_t fFlags;
1411 /** The saved state range ID. */
1412 uint8_t idSavedState;
1413 /** Alignment padding. */
1414 uint8_t au8Alignment[3];
1415 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1416 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1417 /** The size bits pvOriginal points to. */
1418 uint32_t cbOriginal;
1419 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1420 * This is used for strictness checks. */
1421 R3PTRTYPE(const void *) pvOriginal;
1422 /** The ROM description. */
1423 R3PTRTYPE(const char *) pszDesc;
1424 /** The per page tracking structures. */
1425 PGMROMPAGE aPages[1];
1426} PGMROMRANGE;
1427/** Pointer to a ROM range. */
1428typedef PGMROMRANGE *PPGMROMRANGE;
1429
1430
1431/**
1432 * Live save per page data for an MMIO2 page.
1433 *
1434 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1435 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1436 * CRC-32 for detecting changes as well as special handling of zero pages. This
1437 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1438 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1439 * because of speed (2.5x and 6x slower).)
1440 *
1441 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1442 * save but normally is disabled. Since we can write monitor guest
1443 * accesses on our own, we only need this for host accesses. Shouldn't be
1444 * too difficult for DevVGA, VMMDev might be doable, the planned
1445 * networking fun will be fun since it involves ring-0.
1446 */
1447typedef struct PGMLIVESAVEMMIO2PAGE
1448{
1449 /** Set if the page is considered dirty. */
1450 bool fDirty;
1451 /** The number of scans this page has remained unchanged for.
1452 * Only updated for dirty pages. */
1453 uint8_t cUnchangedScans;
1454 /** Whether this page was zero at the last scan. */
1455 bool fZero;
1456 /** Alignment padding. */
1457 bool fReserved;
1458 /** CRC-32 for the first half of the page.
1459 * This is used together with u32CrcH2 to quickly detect changes in the page
1460 * during the non-final passes. */
1461 uint32_t u32CrcH1;
1462 /** CRC-32 for the second half of the page. */
1463 uint32_t u32CrcH2;
1464 /** SHA-1 for the saved page.
1465 * This is used in the final pass to skip pages without changes. */
1466 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1467} PGMLIVESAVEMMIO2PAGE;
1468/** Pointer to a live save status data for an MMIO2 page. */
1469typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1470
1471/**
1472 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1473 *
1474 * There are a few reason why we need to keep track of these registrations. One
1475 * of them is the deregistration & cleanup stuff, while another is that the
1476 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1477 * range list.
1478 *
1479 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1480 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1481 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1482 * overlap we will free all the existing RAM pages and put in the ram range
1483 * pages instead.
1484 */
1485typedef struct PGMREGMMIORANGE
1486{
1487 /** The owner of the range. (a device) */
1488 PPDMDEVINSR3 pDevInsR3;
1489 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1490 RTR3PTR pvR3;
1491 /** Pointer to the next range - R3. */
1492 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1493 /** Flags (PGMREGMMIORANGE_F_XXX). */
1494 uint16_t fFlags;
1495 /** The sub device number (internal PCI config (CFGM) number). */
1496 uint8_t iSubDev;
1497 /** The PCI region number. */
1498 uint8_t iRegion;
1499 /** The saved state range ID. */
1500 uint8_t idSavedState;
1501 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1502 uint8_t idMmio2;
1503 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1504 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1505 /** The real size.
1506 * This may be larger than indicated by RamRange.cb if the range has been
1507 * reduced during saved state loading. */
1508 RTGCPHYS cbReal;
1509 /** Pointer to the physical handler for MMIO. */
1510 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1511 /** Live save per page tracking data for MMIO2. */
1512 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1513 /** The associated RAM range. */
1514 PGMRAMRANGE RamRange;
1515} PGMREGMMIORANGE;
1516AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1517/** Pointer to a MMIO2 or pre-registered MMIO range. */
1518typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1519
1520/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1521 * @{ */
1522/** Set if it's an MMIO2 range. */
1523#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1524/** Set if this is the first chunk in the MMIO2 range. */
1525#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1526/** Set if this is the last chunk in the MMIO2 range. */
1527#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1528/** Set if the whole range is mapped. */
1529#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1530/** Set if it's overlapping, clear if not. */
1531#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1532/** @} */
1533
1534
1535/** @name Internal MMIO2 constants.
1536 * @{ */
1537/** The maximum number of MMIO2 ranges. */
1538#define PGM_MMIO2_MAX_RANGES 8
1539/** The maximum number of pages in a MMIO2 range. */
1540#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1541/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1542#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1543/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1544#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1545/** Gets the MMIO2 page index from an MMIO2 page ID. */
1546#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1547/** @} */
1548
1549
1550
1551/**
1552 * PGMPhysRead/Write cache entry
1553 */
1554typedef struct PGMPHYSCACHEENTRY
1555{
1556 /** R3 pointer to physical page. */
1557 R3PTRTYPE(uint8_t *) pbR3;
1558 /** GC Physical address for cache entry */
1559 RTGCPHYS GCPhys;
1560#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1561 RTGCPHYS u32Padding0; /**< alignment padding. */
1562#endif
1563} PGMPHYSCACHEENTRY;
1564
1565/**
1566 * PGMPhysRead/Write cache to reduce REM memory access overhead
1567 */
1568typedef struct PGMPHYSCACHE
1569{
1570 /** Bitmap of valid cache entries */
1571 uint64_t aEntries;
1572 /** Cache entries */
1573 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1574} PGMPHYSCACHE;
1575
1576
1577/** Pointer to an allocation chunk ring-3 mapping. */
1578typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1579/** Pointer to an allocation chunk ring-3 mapping pointer. */
1580typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1581
1582/**
1583 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1584 *
1585 * The primary tree (Core) uses the chunk id as key.
1586 */
1587typedef struct PGMCHUNKR3MAP
1588{
1589 /** The key is the chunk id. */
1590 AVLU32NODECORE Core;
1591 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1592 * selection. */
1593 uint32_t iLastUsed;
1594 /** The current reference count. */
1595 uint32_t volatile cRefs;
1596 /** The current permanent reference count. */
1597 uint32_t volatile cPermRefs;
1598 /** The mapping address. */
1599 void *pv;
1600} PGMCHUNKR3MAP;
1601
1602/**
1603 * Allocation chunk ring-3 mapping TLB entry.
1604 */
1605typedef struct PGMCHUNKR3MAPTLBE
1606{
1607 /** The chunk id. */
1608 uint32_t volatile idChunk;
1609#if HC_ARCH_BITS == 64
1610 uint32_t u32Padding; /**< alignment padding. */
1611#endif
1612 /** The chunk map. */
1613#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1614 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1615#else
1616 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1617#endif
1618} PGMCHUNKR3MAPTLBE;
1619/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1620typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1621
1622/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1623 * @remark Must be a power of two value. */
1624#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1625
1626/**
1627 * Allocation chunk ring-3 mapping TLB.
1628 *
1629 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1630 * At first glance this might look kinda odd since AVL trees are
1631 * supposed to give the most optimal lookup times of all trees
1632 * due to their balancing. However, take a tree with 1023 nodes
1633 * in it, that's 10 levels, meaning that most searches has to go
1634 * down 9 levels before they find what they want. This isn't fast
1635 * compared to a TLB hit. There is the factor of cache misses,
1636 * and of course the problem with trees and branch prediction.
1637 * This is why we use TLBs in front of most of the trees.
1638 *
1639 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1640 * difficult when we switch to the new inlined AVL trees (from kStuff).
1641 */
1642typedef struct PGMCHUNKR3MAPTLB
1643{
1644 /** The TLB entries. */
1645 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1646} PGMCHUNKR3MAPTLB;
1647
1648/**
1649 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1650 * @returns Chunk TLB index.
1651 * @param idChunk The Chunk ID.
1652 */
1653#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1654
1655
1656/**
1657 * Ring-3 guest page mapping TLB entry.
1658 * @remarks used in ring-0 as well at the moment.
1659 */
1660typedef struct PGMPAGER3MAPTLBE
1661{
1662 /** Address of the page. */
1663 RTGCPHYS volatile GCPhys;
1664 /** The guest page. */
1665#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1666 R3PTRTYPE(PPGMPAGE) volatile pPage;
1667#else
1668 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1669#endif
1670 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1671#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1672 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1673#else
1674 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1675#endif
1676 /** The address */
1677#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1678 R3PTRTYPE(void *) volatile pv;
1679#else
1680 R3R0PTRTYPE(void *) volatile pv;
1681#endif
1682#if HC_ARCH_BITS == 32
1683 uint32_t u32Padding; /**< alignment padding. */
1684#endif
1685} PGMPAGER3MAPTLBE;
1686/** Pointer to an entry in the HC physical TLB. */
1687typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1688
1689
1690/** The number of entries in the ring-3 guest page mapping TLB.
1691 * @remarks The value must be a power of two. */
1692#define PGM_PAGER3MAPTLB_ENTRIES 256
1693
1694/**
1695 * Ring-3 guest page mapping TLB.
1696 * @remarks used in ring-0 as well at the moment.
1697 */
1698typedef struct PGMPAGER3MAPTLB
1699{
1700 /** The TLB entries. */
1701 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1702} PGMPAGER3MAPTLB;
1703/** Pointer to the ring-3 guest page mapping TLB. */
1704typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1705
1706/**
1707 * Calculates the index of the TLB entry for the specified guest page.
1708 * @returns Physical TLB index.
1709 * @param GCPhys The guest physical address.
1710 */
1711#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1712
1713
1714/**
1715 * Raw-mode context dynamic mapping cache entry.
1716 *
1717 * Because of raw-mode context being reloctable and all relocations are applied
1718 * in ring-3, this has to be defined here and be RC specific.
1719 *
1720 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1721 */
1722typedef struct PGMRCDYNMAPENTRY
1723{
1724 /** The physical address of the currently mapped page.
1725 * This is duplicate for three reasons: cache locality, cache policy of the PT
1726 * mappings and sanity checks. */
1727 RTHCPHYS HCPhys;
1728 /** Pointer to the page. */
1729 RTRCPTR pvPage;
1730 /** The number of references. */
1731 int32_t volatile cRefs;
1732 /** PTE pointer union. */
1733 struct PGMRCDYNMAPENTRY_PPTE
1734 {
1735 /** PTE pointer, 32-bit legacy version. */
1736 RCPTRTYPE(PX86PTE) pLegacy;
1737 /** PTE pointer, PAE version. */
1738 RCPTRTYPE(PX86PTEPAE) pPae;
1739 } uPte;
1740} PGMRCDYNMAPENTRY;
1741/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1742typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1743
1744
1745/**
1746 * Dynamic mapping cache for the raw-mode context.
1747 *
1748 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1749 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1750 * so that we can perform relocations from PGMR3Relocate. This has the
1751 * consequence that we must have separate ring-0 and raw-mode context versions
1752 * of this struct even if they share the basic elements.
1753 *
1754 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1755 */
1756typedef struct PGMRCDYNMAP
1757{
1758 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1759 uint32_t u32Magic;
1760 /** Array for tracking and managing the pages. */
1761 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1762 /** The cache size given as a number of pages. */
1763 uint32_t cPages;
1764 /** The current load.
1765 * This does not include guard pages. */
1766 uint32_t cLoad;
1767 /** The max load ever.
1768 * This is maintained to get trigger adding of more mapping space. */
1769 uint32_t cMaxLoad;
1770 /** The number of guard pages. */
1771 uint32_t cGuardPages;
1772 /** The number of users (protected by hInitLock). */
1773 uint32_t cUsers;
1774} PGMRCDYNMAP;
1775/** Pointer to the dynamic cache for the raw-mode context. */
1776typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1777
1778
1779/**
1780 * Mapping cache usage set entry.
1781 *
1782 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1783 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1784 * cache. If it's extended to include ring-3, well, then something
1785 * will have be changed here...
1786 */
1787typedef struct PGMMAPSETENTRY
1788{
1789 /** Pointer to the page. */
1790 RTR0PTR pvPage;
1791 /** The mapping cache index. */
1792 uint16_t iPage;
1793 /** The number of references.
1794 * The max is UINT16_MAX - 1. */
1795 uint16_t cRefs;
1796 /** The number inlined references.
1797 * The max is UINT16_MAX - 1. */
1798 uint16_t cInlinedRefs;
1799 /** Unreferences. */
1800 uint16_t cUnrefs;
1801
1802#if HC_ARCH_BITS == 32
1803 uint32_t u32Alignment1;
1804#endif
1805 /** The physical address for this entry. */
1806 RTHCPHYS HCPhys;
1807} PGMMAPSETENTRY;
1808AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1809AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1810/** Pointer to a mapping cache usage set entry. */
1811typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1812
1813/**
1814 * Mapping cache usage set.
1815 *
1816 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1817 * done during exits / traps. The set is
1818 */
1819typedef struct PGMMAPSET
1820{
1821 /** The number of occupied entries.
1822 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1823 * dynamic mappings. */
1824 uint32_t cEntries;
1825 /** The start of the current subset.
1826 * This is UINT32_MAX if no subset is currently open. */
1827 uint32_t iSubset;
1828 /** The index of the current CPU, only valid if the set is open. */
1829 int32_t iCpu;
1830 uint32_t alignment;
1831 /** The entries. */
1832 PGMMAPSETENTRY aEntries[64];
1833 /** HCPhys -> iEntry fast lookup table.
1834 * Use PGMMAPSET_HASH for hashing.
1835 * The entries may or may not be valid, check against cEntries. */
1836 uint8_t aiHashTable[128];
1837} PGMMAPSET;
1838AssertCompileSizeAlignment(PGMMAPSET, 8);
1839/** Pointer to the mapping cache set. */
1840typedef PGMMAPSET *PPGMMAPSET;
1841
1842/** PGMMAPSET::cEntries value for a closed set. */
1843#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1844
1845/** Hash function for aiHashTable. */
1846#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1847
1848
1849/** @name Context neutral page mapper TLB.
1850 *
1851 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1852 * code is writting in a kind of context neutral way. Time will show whether
1853 * this actually makes sense or not...
1854 *
1855 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1856 * context ends up using a global mapping cache on some platforms
1857 * (darwin).
1858 *
1859 * @{ */
1860/** @typedef PPGMPAGEMAPTLB
1861 * The page mapper TLB pointer type for the current context. */
1862/** @typedef PPGMPAGEMAPTLB
1863 * The page mapper TLB entry pointer type for the current context. */
1864/** @typedef PPGMPAGEMAPTLB
1865 * The page mapper TLB entry pointer pointer type for the current context. */
1866/** @def PGM_PAGEMAPTLB_ENTRIES
1867 * The number of TLB entries in the page mapper TLB for the current context. */
1868/** @def PGM_PAGEMAPTLB_IDX
1869 * Calculate the TLB index for a guest physical address.
1870 * @returns The TLB index.
1871 * @param GCPhys The guest physical address. */
1872/** @typedef PPGMPAGEMAP
1873 * Pointer to a page mapper unit for current context. */
1874/** @typedef PPPGMPAGEMAP
1875 * Pointer to a page mapper unit pointer for current context. */
1876#if defined(IN_RING0) && 0
1877// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1878// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1879// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1880//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1881//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1882// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1883// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1884#else
1885 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1886 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1887 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1888# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1889# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1890 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1891 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1892#endif
1893/** @} */
1894
1895
1896/** @name PGM Pool Indexes.
1897 * Aka. the unique shadow page identifier.
1898 * @{ */
1899/** NIL page pool IDX. */
1900#define NIL_PGMPOOL_IDX 0
1901/** The first normal index. There used to be 5 fictive pages up front, now
1902 * there is only the NIL page. */
1903#define PGMPOOL_IDX_FIRST 1
1904/** The last valid index. (inclusive, 14 bits) */
1905#define PGMPOOL_IDX_LAST 0x3fff
1906/** @} */
1907
1908/** The NIL index for the parent chain. */
1909#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1910#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1911
1912/**
1913 * Node in the chain linking a shadowed page to it's parent (user).
1914 */
1915#pragma pack(1)
1916typedef struct PGMPOOLUSER
1917{
1918 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1919 uint16_t iNext;
1920 /** The user page index. */
1921 uint16_t iUser;
1922 /** Index into the user table. */
1923 uint32_t iUserTable;
1924} PGMPOOLUSER, *PPGMPOOLUSER;
1925typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1926#pragma pack()
1927
1928
1929/** The NIL index for the phys ext chain. */
1930#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1931/** The NIL pte index for a phys ext chain slot. */
1932#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1933
1934/**
1935 * Node in the chain of physical cross reference extents.
1936 * @todo Calling this an 'extent' is not quite right, find a better name.
1937 * @todo find out the optimal size of the aidx array
1938 */
1939#pragma pack(1)
1940typedef struct PGMPOOLPHYSEXT
1941{
1942 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1943 uint16_t iNext;
1944 /** Alignment. */
1945 uint16_t u16Align;
1946 /** The user page index. */
1947 uint16_t aidx[3];
1948 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1949 uint16_t apte[3];
1950} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1951typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1952#pragma pack()
1953
1954
1955/**
1956 * The kind of page that's being shadowed.
1957 */
1958typedef enum PGMPOOLKIND
1959{
1960 /** The virtual invalid 0 entry. */
1961 PGMPOOLKIND_INVALID = 0,
1962 /** The entry is free (=unused). */
1963 PGMPOOLKIND_FREE,
1964
1965 /** Shw: 32-bit page table; Gst: no paging. */
1966 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1967 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1968 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1969 /** Shw: 32-bit page table; Gst: 4MB page. */
1970 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1971 /** Shw: PAE page table; Gst: no paging. */
1972 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1973 /** Shw: PAE page table; Gst: 32-bit page table. */
1974 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1975 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1976 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1977 /** Shw: PAE page table; Gst: PAE page table. */
1978 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1979 /** Shw: PAE page table; Gst: 2MB page. */
1980 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1981
1982 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1983 PGMPOOLKIND_32BIT_PD,
1984 /** Shw: 32-bit page directory. Gst: no paging. */
1985 PGMPOOLKIND_32BIT_PD_PHYS,
1986 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1987 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1988 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1989 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1990 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1991 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1992 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1993 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1994 /** Shw: PAE page directory; Gst: PAE page directory. */
1995 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1996 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1997 PGMPOOLKIND_PAE_PD_PHYS,
1998
1999 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2000 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2001 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2002 PGMPOOLKIND_PAE_PDPT,
2003 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2004 PGMPOOLKIND_PAE_PDPT_PHYS,
2005
2006 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2007 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2008 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2009 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2010 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2011 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2012 /** Shw: 64-bit page directory table; Gst: no paging. */
2013 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2014
2015 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2016 PGMPOOLKIND_64BIT_PML4,
2017
2018 /** Shw: EPT page directory pointer table; Gst: no paging. */
2019 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2020 /** Shw: EPT page directory table; Gst: no paging. */
2021 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2022 /** Shw: EPT page table; Gst: no paging. */
2023 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2024
2025 /** Shw: Root Nested paging table. */
2026 PGMPOOLKIND_ROOT_NESTED,
2027
2028 /** The last valid entry. */
2029 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2030} PGMPOOLKIND;
2031
2032/**
2033 * The access attributes of the page; only applies to big pages.
2034 */
2035typedef enum
2036{
2037 PGMPOOLACCESS_DONTCARE = 0,
2038 PGMPOOLACCESS_USER_RW,
2039 PGMPOOLACCESS_USER_R,
2040 PGMPOOLACCESS_USER_RW_NX,
2041 PGMPOOLACCESS_USER_R_NX,
2042 PGMPOOLACCESS_SUPERVISOR_RW,
2043 PGMPOOLACCESS_SUPERVISOR_R,
2044 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2045 PGMPOOLACCESS_SUPERVISOR_R_NX
2046} PGMPOOLACCESS;
2047
2048/**
2049 * The tracking data for a page in the pool.
2050 */
2051typedef struct PGMPOOLPAGE
2052{
2053 /** AVL node code with the (HC) physical address of this page. */
2054 AVLOHCPHYSNODECORE Core;
2055 /** Pointer to the R3 mapping of the page. */
2056#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2057 R3PTRTYPE(void *) pvPageR3;
2058#else
2059 R3R0PTRTYPE(void *) pvPageR3;
2060#endif
2061#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2062 uint32_t Alignment0;
2063#endif
2064 /** The guest physical address. */
2065 RTGCPHYS GCPhys;
2066 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2067 uint8_t enmKind;
2068 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2069 uint8_t enmAccess;
2070 /** This supplements enmKind and enmAccess */
2071 bool fA20Enabled : 1;
2072
2073 /** Used to indicate that the page is zeroed. */
2074 bool fZeroed : 1;
2075 /** Used to indicate that a PT has non-global entries. */
2076 bool fSeenNonGlobal : 1;
2077 /** Used to indicate that we're monitoring writes to the guest page. */
2078 bool fMonitored : 1;
2079 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2080 * (All pages are in the age list.) */
2081 bool fCached : 1;
2082 /** This is used by the R3 access handlers when invoked by an async thread.
2083 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2084 bool volatile fReusedFlushPending : 1;
2085 /** Used to mark the page as dirty (write monitoring is temporarily
2086 * off). */
2087 bool fDirty : 1;
2088 bool fPadding1 : 1;
2089 bool fPadding2;
2090
2091 /** The index of this page. */
2092 uint16_t idx;
2093 /** The next entry in the list this page currently resides in.
2094 * It's either in the free list or in the GCPhys hash. */
2095 uint16_t iNext;
2096 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2097 uint16_t iUserHead;
2098 /** The number of present entries. */
2099 uint16_t cPresent;
2100 /** The first entry in the table which is present. */
2101 uint16_t iFirstPresent;
2102 /** The number of modifications to the monitored page. */
2103 uint16_t cModifications;
2104 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2105 uint16_t iModifiedNext;
2106 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2107 uint16_t iModifiedPrev;
2108 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2109 uint16_t iMonitoredNext;
2110 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2111 uint16_t iMonitoredPrev;
2112 /** The next page in the age list. */
2113 uint16_t iAgeNext;
2114 /** The previous page in the age list. */
2115 uint16_t iAgePrev;
2116 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2117 uint8_t idxDirtyEntry;
2118
2119 /** @name Access handler statistics to determine whether the guest is
2120 * (re)initializing a page table.
2121 * @{ */
2122 RTGCPTR GCPtrLastAccessHandlerRip;
2123 RTGCPTR GCPtrLastAccessHandlerFault;
2124 uint64_t cLastAccessHandler;
2125 /** @} */
2126 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2127 uint32_t volatile cLocked;
2128#if GC_ARCH_BITS == 64
2129 uint32_t u32Alignment3;
2130#endif
2131# ifdef VBOX_STRICT
2132 RTGCPTR GCPtrDirtyFault;
2133# endif
2134} PGMPOOLPAGE;
2135/** Pointer to a pool page. */
2136typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2137/** Pointer to a const pool page. */
2138typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2139/** Pointer to a pool page pointer. */
2140typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2141
2142
2143/** The hash table size. */
2144# define PGMPOOL_HASH_SIZE 0x40
2145/** The hash function. */
2146# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2147
2148
2149/**
2150 * The shadow page pool instance data.
2151 *
2152 * It's all one big allocation made at init time, except for the
2153 * pages that is. The user nodes follows immediately after the
2154 * page structures.
2155 */
2156typedef struct PGMPOOL
2157{
2158 /** The VM handle - R3 Ptr. */
2159 PVMR3 pVMR3;
2160 /** The VM handle - R0 Ptr. */
2161 R0PTRTYPE(PVMCC) pVMR0;
2162 /** The max pool size. This includes the special IDs. */
2163 uint16_t cMaxPages;
2164 /** The current pool size. */
2165 uint16_t cCurPages;
2166 /** The head of the free page list. */
2167 uint16_t iFreeHead;
2168 /* Padding. */
2169 uint16_t u16Padding;
2170 /** Head of the chain of free user nodes. */
2171 uint16_t iUserFreeHead;
2172 /** The number of user nodes we've allocated. */
2173 uint16_t cMaxUsers;
2174 /** The number of present page table entries in the entire pool. */
2175 uint32_t cPresent;
2176 /** Pointer to the array of user nodes - R3 pointer. */
2177 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2178 /** Pointer to the array of user nodes - R0 pointer. */
2179 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2180 /** Head of the chain of free phys ext nodes. */
2181 uint16_t iPhysExtFreeHead;
2182 /** The number of user nodes we've allocated. */
2183 uint16_t cMaxPhysExts;
2184 uint32_t u32Padding0b;
2185 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2186 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2187 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2188 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2189 /** Hash table for GCPhys addresses. */
2190 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2191 /** The head of the age list. */
2192 uint16_t iAgeHead;
2193 /** The tail of the age list. */
2194 uint16_t iAgeTail;
2195 /** Set if the cache is enabled. */
2196 bool fCacheEnabled;
2197 /** Alignment padding. */
2198 bool afPadding1[3];
2199 /** Head of the list of modified pages. */
2200 uint16_t iModifiedHead;
2201 /** The current number of modified pages. */
2202 uint16_t cModifiedPages;
2203 /** Physical access handler type registration handle. */
2204 PGMPHYSHANDLERTYPE hAccessHandlerType;
2205 /** Next available slot (in aDirtyPages). */
2206 uint32_t idxFreeDirtyPage;
2207 /** Number of active dirty pages. */
2208 uint32_t cDirtyPages;
2209 /** Array of current dirty pgm pool page indices. */
2210 uint16_t aidxDirtyPages[16];
2211 /** Array running in parallel to aidxDirtyPages with the page data. */
2212 struct
2213 {
2214 uint64_t aPage[512];
2215 } aDirtyPages[16];
2216
2217 /** The number of pages currently in use. */
2218 uint16_t cUsedPages;
2219#ifdef VBOX_WITH_STATISTICS
2220 /** The high water mark for cUsedPages. */
2221 uint16_t cUsedPagesHigh;
2222 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2223 /** Profiling pgmPoolAlloc(). */
2224 STAMPROFILEADV StatAlloc;
2225 /** Profiling pgmR3PoolClearDoIt(). */
2226 STAMPROFILE StatClearAll;
2227 /** Profiling pgmR3PoolReset(). */
2228 STAMPROFILE StatR3Reset;
2229 /** Profiling pgmPoolFlushPage(). */
2230 STAMPROFILE StatFlushPage;
2231 /** Profiling pgmPoolFree(). */
2232 STAMPROFILE StatFree;
2233 /** Counting explicit flushes by PGMPoolFlushPage(). */
2234 STAMCOUNTER StatForceFlushPage;
2235 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2236 STAMCOUNTER StatForceFlushDirtyPage;
2237 /** Counting flushes for reused pages. */
2238 STAMCOUNTER StatForceFlushReused;
2239 /** Profiling time spent zeroing pages. */
2240 STAMPROFILE StatZeroPage;
2241 /** Profiling of pgmPoolTrackDeref. */
2242 STAMPROFILE StatTrackDeref;
2243 /** Profiling pgmTrackFlushGCPhysPT. */
2244 STAMPROFILE StatTrackFlushGCPhysPT;
2245 /** Profiling pgmTrackFlushGCPhysPTs. */
2246 STAMPROFILE StatTrackFlushGCPhysPTs;
2247 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2248 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2249 /** Number of times we've been out of user records. */
2250 STAMCOUNTER StatTrackFreeUpOneUser;
2251 /** Nr of flushed entries. */
2252 STAMCOUNTER StatTrackFlushEntry;
2253 /** Nr of updated entries. */
2254 STAMCOUNTER StatTrackFlushEntryKeep;
2255 /** Profiling deref activity related tracking GC physical pages. */
2256 STAMPROFILE StatTrackDerefGCPhys;
2257 /** Number of linear searches for a HCPhys in the ram ranges. */
2258 STAMCOUNTER StatTrackLinearRamSearches;
2259 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2260 STAMCOUNTER StamTrackPhysExtAllocFailures;
2261
2262 /** Profiling the RC/R0 \#PF access handler. */
2263 STAMPROFILE StatMonitorPfRZ;
2264 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2265 STAMPROFILE StatMonitorPfRZHandled;
2266 /** Times we've failed interpreting the instruction. */
2267 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2268 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2269 STAMPROFILE StatMonitorPfRZFlushPage;
2270 /* Times we've detected a page table reinit. */
2271 STAMCOUNTER StatMonitorPfRZFlushReinit;
2272 /** Counting flushes for pages that are modified too often. */
2273 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2274 /** Times we've detected fork(). */
2275 STAMCOUNTER StatMonitorPfRZFork;
2276 /** Times we've failed interpreting a patch code instruction. */
2277 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2278 /** Times we've failed interpreting a patch code instruction during flushing. */
2279 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2280 /** The number of times we've seen rep prefixes we can't handle. */
2281 STAMCOUNTER StatMonitorPfRZRepPrefix;
2282 /** Profiling the REP STOSD cases we've handled. */
2283 STAMPROFILE StatMonitorPfRZRepStosd;
2284
2285 /** Profiling the R0/RC regular access handler. */
2286 STAMPROFILE StatMonitorRZ;
2287 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2288 STAMPROFILE StatMonitorRZFlushPage;
2289 /** Per access size counts indexed by size minus 1, last for larger. */
2290 STAMCOUNTER aStatMonitorRZSizes[16+3];
2291 /** Missaligned access counts indexed by offset - 1. */
2292 STAMCOUNTER aStatMonitorRZMisaligned[7];
2293
2294 /** Nr of handled PT faults. */
2295 STAMCOUNTER StatMonitorRZFaultPT;
2296 /** Nr of handled PD faults. */
2297 STAMCOUNTER StatMonitorRZFaultPD;
2298 /** Nr of handled PDPT faults. */
2299 STAMCOUNTER StatMonitorRZFaultPDPT;
2300 /** Nr of handled PML4 faults. */
2301 STAMCOUNTER StatMonitorRZFaultPML4;
2302
2303 /** Profiling the R3 access handler. */
2304 STAMPROFILE StatMonitorR3;
2305 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2306 STAMPROFILE StatMonitorR3FlushPage;
2307 /** Per access size counts indexed by size minus 1, last for larger. */
2308 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2309 /** Missaligned access counts indexed by offset - 1. */
2310 STAMCOUNTER aStatMonitorR3Misaligned[7];
2311 /** Nr of handled PT faults. */
2312 STAMCOUNTER StatMonitorR3FaultPT;
2313 /** Nr of handled PD faults. */
2314 STAMCOUNTER StatMonitorR3FaultPD;
2315 /** Nr of handled PDPT faults. */
2316 STAMCOUNTER StatMonitorR3FaultPDPT;
2317 /** Nr of handled PML4 faults. */
2318 STAMCOUNTER StatMonitorR3FaultPML4;
2319
2320 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2321 STAMCOUNTER StatResetDirtyPages;
2322 /** Times we've called pgmPoolAddDirtyPage. */
2323 STAMCOUNTER StatDirtyPage;
2324 /** Times we've had to flush duplicates for dirty page management. */
2325 STAMCOUNTER StatDirtyPageDupFlush;
2326 /** Times we've had to flush because of overflow. */
2327 STAMCOUNTER StatDirtyPageOverFlowFlush;
2328
2329 /** The high water mark for cModifiedPages. */
2330 uint16_t cModifiedPagesHigh;
2331 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2332
2333 /** The number of cache hits. */
2334 STAMCOUNTER StatCacheHits;
2335 /** The number of cache misses. */
2336 STAMCOUNTER StatCacheMisses;
2337 /** The number of times we've got a conflict of 'kind' in the cache. */
2338 STAMCOUNTER StatCacheKindMismatches;
2339 /** Number of times we've been out of pages. */
2340 STAMCOUNTER StatCacheFreeUpOne;
2341 /** The number of cacheable allocations. */
2342 STAMCOUNTER StatCacheCacheable;
2343 /** The number of uncacheable allocations. */
2344 STAMCOUNTER StatCacheUncacheable;
2345#else
2346 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2347#endif
2348 /** The AVL tree for looking up a page by its HC physical address. */
2349 AVLOHCPHYSTREE HCPhysTree;
2350 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2351 /** Array of pages. (cMaxPages in length)
2352 * The Id is the index into thist array.
2353 */
2354 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2355} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2356AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2357AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2358AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2359#ifdef VBOX_WITH_STATISTICS
2360AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2361#endif
2362AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2363
2364
2365/** @def PGMPOOL_PAGE_2_PTR
2366 * Maps a pool page pool into the current context.
2367 *
2368 * @returns VBox status code.
2369 * @param a_pVM Pointer to the VM.
2370 * @param a_pPage The pool page.
2371 *
2372 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2373 * small page window employeed by that function. Be careful.
2374 * @remark There is no need to assert on the result.
2375 */
2376#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2377# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2378#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2379# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2380DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2381{
2382 AssertPtr(a_pPage);
2383 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2384 return a_pPage->pvPageR3;
2385}
2386#else
2387# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2388#endif
2389
2390
2391/** @def PGMPOOL_PAGE_2_PTR_V2
2392 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2393 *
2394 * @returns VBox status code.
2395 * @param a_pVM Pointer to the VM.
2396 * @param a_pVCpu The current CPU.
2397 * @param a_pPage The pool page.
2398 *
2399 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2400 * small page window employeed by that function. Be careful.
2401 * @remark There is no need to assert on the result.
2402 */
2403#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2404# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2405#else
2406# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2407#endif
2408
2409
2410/** @name Per guest page tracking data.
2411 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2412 * is to use more bits for it and split it up later on. But for now we'll play
2413 * safe and change as little as possible.
2414 *
2415 * The 16-bit word has two parts:
2416 *
2417 * The first 14-bit forms the @a idx field. It is either the index of a page in
2418 * the shadow page pool, or and index into the extent list.
2419 *
2420 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2421 * shadow page pool references to the page. If cRefs equals
2422 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2423 * (misnomer) table and not the shadow page pool.
2424 *
2425 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2426 * the 16-bit word.
2427 *
2428 * @{ */
2429/** The shift count for getting to the cRefs part. */
2430#define PGMPOOL_TD_CREFS_SHIFT 14
2431/** The mask applied after shifting the tracking data down by
2432 * PGMPOOL_TD_CREFS_SHIFT. */
2433#define PGMPOOL_TD_CREFS_MASK 0x3
2434/** The cRefs value used to indicate that the idx is the head of a
2435 * physical cross reference list. */
2436#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2437/** The shift used to get idx. */
2438#define PGMPOOL_TD_IDX_SHIFT 0
2439/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2440#define PGMPOOL_TD_IDX_MASK 0x3fff
2441/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2442 * simply too many mappings of this page. */
2443#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2444
2445/** @def PGMPOOL_TD_MAKE
2446 * Makes a 16-bit tracking data word.
2447 *
2448 * @returns tracking data.
2449 * @param cRefs The @a cRefs field. Must be within bounds!
2450 * @param idx The @a idx field. Must also be within bounds! */
2451#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2452
2453/** @def PGMPOOL_TD_GET_CREFS
2454 * Get the @a cRefs field from a tracking data word.
2455 *
2456 * @returns The @a cRefs field
2457 * @param u16 The tracking data word.
2458 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2459 * non-zero @a u16. */
2460#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2461
2462/** @def PGMPOOL_TD_GET_IDX
2463 * Get the @a idx field from a tracking data word.
2464 *
2465 * @returns The @a idx field
2466 * @param u16 The tracking data word. */
2467#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2468/** @} */
2469
2470
2471
2472/** @name A20 gate macros
2473 * @{ */
2474#define PGM_WITH_A20
2475#ifdef PGM_WITH_A20
2476# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2477# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2478# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2479 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2480# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2481#else
2482# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2483# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2484# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2485# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2486#endif
2487/** @} */
2488
2489
2490/**
2491 * Roots and anchors for trees and list employing self relative offsets as
2492 * pointers.
2493 *
2494 * When using self-relative offsets instead of pointers, the offsets needs to be
2495 * the same in all offsets. Thus the roots and anchors needs to live on the
2496 * hyper heap just like the nodes.
2497 */
2498typedef struct PGMTREES
2499{
2500 /** List of physical access handler types (offset pointers) of type
2501 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2502 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2503 /** Physical access handlers (AVL range+offsetptr tree). */
2504 AVLROGCPHYSTREE PhysHandlers;
2505} PGMTREES;
2506/** Pointer to PGM trees. */
2507typedef PGMTREES *PPGMTREES;
2508
2509
2510/**
2511 * Page fault guest state for the AMD64 paging mode.
2512 */
2513typedef struct PGMPTWALKCORE
2514{
2515 /** The guest virtual address that is being resolved by the walk
2516 * (input). */
2517 RTGCPTR GCPtr;
2518
2519 /** The guest physical address that is the result of the walk.
2520 * @remarks only valid if fSucceeded is set. */
2521 RTGCPHYS GCPhys;
2522
2523 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2524 bool fSucceeded;
2525 /** The level problem arrised at.
2526 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2527 * level 8. This is 0 on success. */
2528 uint8_t uLevel;
2529 /** Set if the page isn't present. */
2530 bool fNotPresent;
2531 /** Encountered a bad physical address. */
2532 bool fBadPhysAddr;
2533 /** Set if there was reserved bit violations. */
2534 bool fRsvdError;
2535 /** Set if it involves a big page (2/4 MB). */
2536 bool fBigPage;
2537 /** Set if it involves a gigantic page (1 GB). */
2538 bool fGigantPage;
2539 /** The effective X86_PTE_US flag for the address. */
2540 bool fEffectiveUS;
2541 /** The effective X86_PTE_RW flag for the address. */
2542 bool fEffectiveRW;
2543 /** The effective X86_PTE_NX flag for the address. */
2544 bool fEffectiveNX;
2545 bool afPadding1[2];
2546 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2547 * The NX bit is inverted and shifted down 63 places to bit 0. */
2548 uint32_t fEffective;
2549} PGMPTWALKCORE;
2550
2551/** @name PGMPTWALKCORE::fEffective bits.
2552 * @{ */
2553/** Effective execute bit (!NX). */
2554#define PGMPTWALK_EFF_X UINT32_C(1)
2555/** Effective write access bit. */
2556#define PGMPTWALK_EFF_RW X86_PTE_RW
2557/** Effective user-mode access bit. */
2558#define PGMPTWALK_EFF_US X86_PTE_US
2559/** Effective write through cache bit. */
2560#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2561/** Effective cache disabled bit. */
2562#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2563/** Effective accessed bit. */
2564#define PGMPTWALK_EFF_A X86_PTE_A
2565/** The dirty bit of the final entry. */
2566#define PGMPTWALK_EFF_D X86_PTE_D
2567/** The PAT bit of the final entry. */
2568#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2569/** The global bit of the final entry. */
2570#define PGMPTWALK_EFF_G X86_PTE_G
2571/** @} */
2572
2573
2574/**
2575 * Guest page table walk for the AMD64 mode.
2576 */
2577typedef struct PGMPTWALKGSTAMD64
2578{
2579 /** The common core. */
2580 PGMPTWALKCORE Core;
2581
2582 PX86PML4 pPml4;
2583 PX86PML4E pPml4e;
2584 X86PML4E Pml4e;
2585
2586 PX86PDPT pPdpt;
2587 PX86PDPE pPdpe;
2588 X86PDPE Pdpe;
2589
2590 PX86PDPAE pPd;
2591 PX86PDEPAE pPde;
2592 X86PDEPAE Pde;
2593
2594 PX86PTPAE pPt;
2595 PX86PTEPAE pPte;
2596 X86PTEPAE Pte;
2597} PGMPTWALKGSTAMD64;
2598/** Pointer to a AMD64 guest page table walk. */
2599typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2600/** Pointer to a const AMD64 guest page table walk. */
2601typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2602
2603/**
2604 * Guest page table walk for the PAE mode.
2605 */
2606typedef struct PGMPTWALKGSTPAE
2607{
2608 /** The common core. */
2609 PGMPTWALKCORE Core;
2610
2611 PX86PDPT pPdpt;
2612 PX86PDPE pPdpe;
2613 X86PDPE Pdpe;
2614
2615 PX86PDPAE pPd;
2616 PX86PDEPAE pPde;
2617 X86PDEPAE Pde;
2618
2619 PX86PTPAE pPt;
2620 PX86PTEPAE pPte;
2621 X86PTEPAE Pte;
2622} PGMPTWALKGSTPAE;
2623/** Pointer to a PAE guest page table walk. */
2624typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2625/** Pointer to a const AMD64 guest page table walk. */
2626typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2627
2628/**
2629 * Guest page table walk for the 32-bit mode.
2630 */
2631typedef struct PGMPTWALKGST32BIT
2632{
2633 /** The common core. */
2634 PGMPTWALKCORE Core;
2635
2636 PX86PD pPd;
2637 PX86PDE pPde;
2638 X86PDE Pde;
2639
2640 PX86PT pPt;
2641 PX86PTE pPte;
2642 X86PTE Pte;
2643} PGMPTWALKGST32BIT;
2644/** Pointer to a 32-bit guest page table walk. */
2645typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2646/** Pointer to a const 32-bit guest page table walk. */
2647typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2648
2649/**
2650 * Which part of PGMPTWALKGST that is valid.
2651 */
2652typedef enum PGMPTWALKGSTTYPE
2653{
2654 /** Customary invalid 0 value. */
2655 PGMPTWALKGSTTYPE_INVALID = 0,
2656 /** PGMPTWALKGST::u.Amd64 is valid. */
2657 PGMPTWALKGSTTYPE_AMD64,
2658 /** PGMPTWALKGST::u.Pae is valid. */
2659 PGMPTWALKGSTTYPE_PAE,
2660 /** PGMPTWALKGST::u.Legacy is valid. */
2661 PGMPTWALKGSTTYPE_32BIT,
2662 /** Customary 32-bit type hack. */
2663 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2664} PGMPTWALKGSTTYPE;
2665
2666/**
2667 * Combined guest page table walk result.
2668 */
2669typedef struct PGMPTWALKGST
2670{
2671 union
2672 {
2673 /** The page walker core - always valid. */
2674 PGMPTWALKCORE Core;
2675 /** The page walker for AMD64. */
2676 PGMPTWALKGSTAMD64 Amd64;
2677 /** The page walker for PAE (32-bit). */
2678 PGMPTWALKGSTPAE Pae;
2679 /** The page walker for 32-bit paging (called legacy due to C naming
2680 * convension). */
2681 PGMPTWALKGST32BIT Legacy;
2682 } u;
2683 /** Indicates which part of the union is valid. */
2684 PGMPTWALKGSTTYPE enmType;
2685} PGMPTWALKGST;
2686/** Pointer to a combined guest page table walk result. */
2687typedef PGMPTWALKGST *PPGMPTWALKGST;
2688/** Pointer to a read-only combined guest page table walk result. */
2689typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2690
2691
2692/** @name Paging mode macros
2693 * @{
2694 */
2695#ifdef IN_RING3
2696# define PGM_CTX(a,b) a##R3##b
2697# define PGM_CTX_STR(a,b) a "R3" b
2698# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2699#elif defined(IN_RING0)
2700# define PGM_CTX(a,b) a##R0##b
2701# define PGM_CTX_STR(a,b) a "R0" b
2702# define PGM_CTX_DECL(type) VMMDECL(type)
2703#else
2704# error "Not IN_RING3 or IN_RING0!"
2705#endif
2706
2707#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2708#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2709#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2710#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2711#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2712#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2713#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2714#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2715#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2716#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2717#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2718#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2719#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2720#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2721#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2722#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2723
2724#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2725#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2726#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2727#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2728#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2729#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2730#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2731#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2732#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2733#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2734#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2735#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2736#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2737#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2738#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2739#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2740#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2741#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2742#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2743#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2744#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2745#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2746#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2747#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2748#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2749
2750/* Shw_Gst */
2751#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2752#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2753#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2754#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2755#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2756#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2757#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2758#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2759#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2760#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2761#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2762#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2763#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2764#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2765#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2766#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2767#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2768#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2769#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2770#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2771#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2772#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2773#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2774#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2775#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2776#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2777#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2778#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2779#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2780#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2781#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2782#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2783#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2784#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2785
2786#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2787#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2788#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2789#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2790#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2791#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2792#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2793#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2794#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2795#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2796#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2797#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2798#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2799#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2800#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2801#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2802#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2803#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2804#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2805#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2806#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2807#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2808#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2809#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2810#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2811#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2812#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2813#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2814
2815#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2816#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2817#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2818#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2819#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2820#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2821#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2822#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2823#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2824#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2825#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2826#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2827#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2828#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2829#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2830#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2831#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2832#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2833#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2834#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2835#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2836#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2837#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2838#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2839#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2840#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2841#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2842#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2843#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2844
2845#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2846/** @} */
2847
2848
2849/**
2850 * Function pointers for guest paging.
2851 */
2852typedef struct PGMMODEDATAGST
2853{
2854 /** The guest mode type. */
2855 uint32_t uType;
2856 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
2857 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
2858 DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
2859 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2860 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPUCC pVCpu);
2861#ifdef IN_RING3
2862 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPUCC pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
2863#endif
2864} PGMMODEDATAGST;
2865
2866/** The length of g_aPgmGuestModeData. */
2867#ifdef VBOX_WITH_64_BITS_GUESTS
2868# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2869#else
2870# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2871#endif
2872/** The guest mode data array. */
2873extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2874
2875
2876/**
2877 * Function pointers for shadow paging.
2878 */
2879typedef struct PGMMODEDATASHW
2880{
2881 /** The shadow mode type. */
2882 uint32_t uType;
2883 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
2884 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2885 uint64_t fMask, uint32_t fOpFlags);
2886 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode);
2887 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPUCC pVCpu);
2888#ifdef IN_RING3
2889 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPUCC pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
2890#endif
2891} PGMMODEDATASHW;
2892
2893/** The length of g_aPgmShadowModeData. */
2894#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2895/** The shadow mode data array. */
2896extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2897
2898
2899/**
2900 * Function pointers for guest+shadow paging.
2901 */
2902typedef struct PGMMODEDATABTH
2903{
2904 /** The shadow mode type. */
2905 uint32_t uShwType;
2906 /** The guest mode type. */
2907 uint32_t uGstType;
2908
2909 DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
2910 DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
2911 DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
2912 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
2913 DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2914 DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPUCC pVCpu);
2915 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2916#ifndef IN_RING3
2917 DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
2918#endif
2919#ifdef VBOX_STRICT
2920 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
2921#endif
2922} PGMMODEDATABTH;
2923
2924/** The length of g_aPgmBothModeData. */
2925#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2926/** The guest+shadow mode data array. */
2927extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2928
2929
2930#ifdef VBOX_WITH_STATISTICS
2931/**
2932 * PGM statistics.
2933 *
2934 * These lives on the heap when compiled in as they would otherwise waste
2935 * unnecessary space in release builds.
2936 */
2937typedef struct PGMSTATS
2938{
2939 /* R3 only: */
2940 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2941 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2942
2943 /* R3+RZ */
2944 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2945 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2946 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2947 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2948 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2949 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2950 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2951 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2952 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2953 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2954 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2955 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2956 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2957 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2958 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2959 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2960 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2961 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2962 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2963 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2964 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2965 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2966/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2967 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2968 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2969/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2970
2971 /* RC only: */
2972 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2973 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2974
2975 STAMCOUNTER StatRZPhysRead;
2976 STAMCOUNTER StatRZPhysReadBytes;
2977 STAMCOUNTER StatRZPhysWrite;
2978 STAMCOUNTER StatRZPhysWriteBytes;
2979 STAMCOUNTER StatR3PhysRead;
2980 STAMCOUNTER StatR3PhysReadBytes;
2981 STAMCOUNTER StatR3PhysWrite;
2982 STAMCOUNTER StatR3PhysWriteBytes;
2983 STAMCOUNTER StatRCPhysRead;
2984 STAMCOUNTER StatRCPhysReadBytes;
2985 STAMCOUNTER StatRCPhysWrite;
2986 STAMCOUNTER StatRCPhysWriteBytes;
2987
2988 STAMCOUNTER StatRZPhysSimpleRead;
2989 STAMCOUNTER StatRZPhysSimpleReadBytes;
2990 STAMCOUNTER StatRZPhysSimpleWrite;
2991 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2992 STAMCOUNTER StatR3PhysSimpleRead;
2993 STAMCOUNTER StatR3PhysSimpleReadBytes;
2994 STAMCOUNTER StatR3PhysSimpleWrite;
2995 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2996 STAMCOUNTER StatRCPhysSimpleRead;
2997 STAMCOUNTER StatRCPhysSimpleReadBytes;
2998 STAMCOUNTER StatRCPhysSimpleWrite;
2999 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3000
3001 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3002 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3003 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3004 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3005 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3006 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3007 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3008
3009 /** Time spent by the host OS for large page allocation. */
3010 STAMPROFILE StatAllocLargePage;
3011 /** Time spent clearing the newly allocated large pages. */
3012 STAMPROFILE StatClearLargePage;
3013 /** The number of times allocating a large pages takes more than the allowed period. */
3014 STAMCOUNTER StatLargePageOverflow;
3015 /** pgmPhysIsValidLargePage profiling - R3 */
3016 STAMPROFILE StatR3IsValidLargePage;
3017 /** pgmPhysIsValidLargePage profiling - RZ*/
3018 STAMPROFILE StatRZIsValidLargePage;
3019
3020 STAMPROFILE StatChunkAging;
3021 STAMPROFILE StatChunkFindCandidate;
3022 STAMPROFILE StatChunkUnmap;
3023 STAMPROFILE StatChunkMap;
3024} PGMSTATS;
3025#endif /* VBOX_WITH_STATISTICS */
3026
3027
3028/**
3029 * Converts a PGM pointer into a VM pointer.
3030 * @returns Pointer to the VM structure the PGM is part of.
3031 * @param pPGM Pointer to PGM instance data.
3032 */
3033#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3034
3035/**
3036 * PGM Data (part of VM)
3037 */
3038typedef struct PGM
3039{
3040 /** Offset to the VM structure. */
3041 int32_t offVM;
3042 /** Offset of the PGMCPU structure relative to VMCPU. */
3043 int32_t offVCpuPGM;
3044
3045 /** @cfgm{/RamPreAlloc, boolean, false}
3046 * Indicates whether the base RAM should all be allocated before starting
3047 * the VM (default), or if it should be allocated when first written to.
3048 */
3049 bool fRamPreAlloc;
3050 /** Indicates whether write monitoring is currently in use.
3051 * This is used to prevent conflicts between live saving and page sharing
3052 * detection. */
3053 bool fPhysWriteMonitoringEngaged;
3054 /** Set if the CPU has less than 52-bit physical address width.
3055 * This is used */
3056 bool fLessThan52PhysicalAddressBits;
3057 /** Set when nested paging is active.
3058 * This is meant to save calls to HMIsNestedPagingActive and let the
3059 * compilers optimize the code better. Whether we use nested paging or
3060 * not is something we find out during VMM initialization and we won't
3061 * change this later on. */
3062 bool fNestedPaging;
3063 /** The host paging mode. (This is what SUPLib reports.) */
3064 SUPPAGINGMODE enmHostMode;
3065 /** We're not in a state which permits writes to guest memory.
3066 * (Only used in strict builds.) */
3067 bool fNoMorePhysWrites;
3068 /** @cfgm{/PageFusionAllowed, boolean, false}
3069 * Whether page fusion is allowed. */
3070 bool fPageFusionAllowed;
3071 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3072 * Whether PCI passthrough is enabled. */
3073 bool fPciPassthrough;
3074 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3075 uint8_t cMmio2Regions;
3076 /** Restore original ROM page content when resetting after loading state.
3077 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3078 * enables the VM to start using an updated ROM without requiring powering
3079 * down the VM, just rebooting or resetting it. */
3080 bool fRestoreRomPagesOnReset;
3081 /** Whether to automatically clear all RAM pages on reset. */
3082 bool fZeroRamPagesOnReset;
3083 /** Alignment padding. */
3084 bool afAlignment3[7];
3085
3086 /** Indicates that PGMR3FinalizeMappings has been called and that further
3087 * PGMR3MapIntermediate calls will be rejected. */
3088 bool fFinalizedMappings;
3089 /** If set no conflict checks are required. */
3090 bool fMappingsFixed;
3091 /** If set if restored as fixed but we were unable to re-fixate at the old
3092 * location because of room or address incompatibilities. */
3093 bool fMappingsFixedRestored;
3094 /** Size of fixed mapping.
3095 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3096 uint32_t cbMappingFixed;
3097 /** Generation ID for the RAM ranges. This member is incremented everytime
3098 * a RAM range is linked or unlinked. */
3099 uint32_t volatile idRamRangesGen;
3100
3101 /** Base address (GC) of fixed mapping.
3102 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3103 RTGCPTR GCPtrMappingFixed;
3104 /** The address of the previous RAM range mapping. */
3105 RTGCPTR GCPtrPrevRamRangeMapping;
3106
3107 /** Physical access handler type for ROM protection. */
3108 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3109 /** Alignment padding. */
3110 uint32_t u32Padding;
3111
3112 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3113 RTGCPHYS GCPhys4MBPSEMask;
3114 /** Mask containing the invalid bits of a guest physical address.
3115 * @remarks this does not stop at bit 52. */
3116 RTGCPHYS GCPhysInvAddrMask;
3117
3118
3119 /** RAM range TLB for R3. */
3120 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3121 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3122 * This is sorted by physical address and contains no overlapping ranges. */
3123 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3124 /** Root of the RAM range search tree for ring-3. */
3125 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3126 /** PGM offset based trees - R3 Ptr. */
3127 R3PTRTYPE(PPGMTREES) pTreesR3;
3128 /** Caching the last physical handler we looked up in R3. */
3129 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3130 /** Shadow Page Pool - R3 Ptr. */
3131 R3PTRTYPE(PPGMPOOL) pPoolR3;
3132#ifndef PGM_WITHOUT_MAPPINGS
3133 /** Linked list of GC mappings - for HC.
3134 * The list is sorted ascending on address. */
3135 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3136#endif
3137 /** Pointer to the list of ROM ranges - for R3.
3138 * This is sorted by physical address and contains no overlapping ranges. */
3139 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3140 /** Pointer to the list of MMIO2 ranges - for R3.
3141 * Registration order. */
3142 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3143 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3144 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3145
3146 /** RAM range TLB for R0. */
3147 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3148 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3149 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3150 /** Root of the RAM range search tree for ring-0. */
3151 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3152 /** PGM offset based trees - R0 Ptr. */
3153 R0PTRTYPE(PPGMTREES) pTreesR0;
3154 /** Caching the last physical handler we looked up in R0. */
3155 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3156 /** Shadow Page Pool - R0 Ptr. */
3157 R0PTRTYPE(PPGMPOOL) pPoolR0;
3158#ifndef PGM_WITHOUT_MAPPINGS
3159 /** Linked list of GC mappings - for R0.
3160 * The list is sorted ascending on address. */
3161 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3162 RTR0PTR R0PtrAlignment0;
3163#endif
3164 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3165 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3166 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3167 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3168
3169#ifndef PGM_WITHOUT_MAPPINGS
3170 /** Pointer to the 5 page CR3 content mapping.
3171 * The first page is always the CR3 (in some form) while the 4 other pages
3172 * are used for the PDs in PAE mode. */
3173 RTGCPTR GCPtrCR3Mapping;
3174
3175 /** @name Intermediate Context
3176 * @{ */
3177 /** Pointer to the intermediate page directory - Normal. */
3178 R3PTRTYPE(PX86PD) pInterPD;
3179 /** Pointer to the intermediate page tables - Normal.
3180 * There are two page tables, one for the identity mapping and one for
3181 * the host context mapping (of the core code). */
3182 R3PTRTYPE(PX86PT) apInterPTs[2];
3183 /** Pointer to the intermediate page tables - PAE. */
3184 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3185 /** Pointer to the intermediate page directory - PAE. */
3186 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3187 /** Pointer to the intermediate page directory - PAE. */
3188 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3189 /** Pointer to the intermediate page-map level 4 - AMD64. */
3190 R3PTRTYPE(PX86PML4) pInterPaePML4;
3191 /** Pointer to the intermediate page directory - AMD64. */
3192 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3193 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3194 RTHCPHYS HCPhysInterPD;
3195 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3196 RTHCPHYS HCPhysInterPaePDPT;
3197 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3198 RTHCPHYS HCPhysInterPaePML4;
3199 /** @} */
3200#endif
3201
3202#ifndef PGM_WITHOUT_MAPPINGS
3203 /** Base address of the dynamic page mapping area.
3204 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3205 *
3206 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3207 * work out. Some cleaning up of the initialization that would
3208 * remove this memory is yet to be done...
3209 */
3210 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3211 /** The address of the raw-mode context mapping cache. */
3212 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3213 /** The address of the ring-0 mapping cache if we're making use of it. */
3214 RTR0PTR pvR0DynMapUsed;
3215#endif
3216
3217 /** Hack: Number of deprecated page mapping locks taken by the current lock
3218 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3219 uint32_t cDeprecatedPageLocks;
3220 /** Alignment padding. */
3221 uint32_t au32Alignment2[1];
3222
3223
3224 /** PGM critical section.
3225 * This protects the physical, ram ranges, and the page flag updating (some of
3226 * it anyway).
3227 */
3228 PDMCRITSECT CritSectX;
3229
3230 /**
3231 * Data associated with managing the ring-3 mappings of the allocation chunks.
3232 */
3233 struct
3234 {
3235 /** The chunk mapping TLB. */
3236 PGMCHUNKR3MAPTLB Tlb;
3237 /** The chunk tree, ordered by chunk id. */
3238#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3239 R3PTRTYPE(PAVLU32NODECORE) pTree;
3240#else
3241 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3242#endif
3243#if HC_ARCH_BITS == 32
3244 uint32_t u32Alignment0;
3245#endif
3246 /** The number of mapped chunks. */
3247 uint32_t c;
3248 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3249 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3250 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3251 uint32_t cMax;
3252 /** The current time. This is incremented whenever a chunk is inserted. */
3253 uint32_t iNow;
3254 /** Alignment padding. */
3255 uint32_t au32Alignment1[3];
3256 } ChunkR3Map;
3257
3258 /** The page mapping TLB for ring-3. */
3259 PGMPAGER3MAPTLB PhysTlbR3;
3260 /** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3261 PGMPAGER3MAPTLB PhysTlbR0;
3262
3263 /** @name The zero page.
3264 * @{ */
3265 /** The host physical address of the zero page. */
3266 RTHCPHYS HCPhysZeroPg;
3267 /** The ring-3 mapping of the zero page. */
3268 RTR3PTR pvZeroPgR3;
3269 /** The ring-0 mapping of the zero page. */
3270 RTR0PTR pvZeroPgR0;
3271 /** The GC mapping of the zero page. */
3272 RTRCPTR pvZeroPgRC;
3273 RTRCPTR RCPtrAlignment3;
3274 /** @}*/
3275
3276 /** @name The Invalid MMIO page.
3277 * This page is filled with 0xfeedface.
3278 * @{ */
3279 /** The host physical address of the invalid MMIO page. */
3280 RTHCPHYS HCPhysMmioPg;
3281 /** The host pysical address of the invalid MMIO page plus all invalid
3282 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3283 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3284 RTHCPHYS HCPhysInvMmioPg;
3285 /** The ring-3 mapping of the invalid MMIO page. */
3286 RTR3PTR pvMmioPgR3;
3287#if HC_ARCH_BITS == 32
3288 RTR3PTR R3PtrAlignment4;
3289#endif
3290 /** @} */
3291
3292
3293 /** The number of handy pages. */
3294 uint32_t cHandyPages;
3295
3296 /** The number of large handy pages. */
3297 uint32_t cLargeHandyPages;
3298
3299 /**
3300 * Array of handy pages.
3301 *
3302 * This array is used in a two way communication between pgmPhysAllocPage
3303 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3304 * an intermediary.
3305 *
3306 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3307 * (The current size of 32 pages, means 128 KB of handy memory.)
3308 */
3309 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3310
3311 /**
3312 * Array of large handy pages. (currently size 1)
3313 *
3314 * This array is used in a two way communication between pgmPhysAllocLargePage
3315 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3316 * an intermediary.
3317 */
3318 GMMPAGEDESC aLargeHandyPage[1];
3319
3320 /**
3321 * Live save data.
3322 */
3323 struct
3324 {
3325 /** Per type statistics. */
3326 struct
3327 {
3328 /** The number of ready pages. */
3329 uint32_t cReadyPages;
3330 /** The number of dirty pages. */
3331 uint32_t cDirtyPages;
3332 /** The number of ready zero pages. */
3333 uint32_t cZeroPages;
3334 /** The number of write monitored pages. */
3335 uint32_t cMonitoredPages;
3336 } Rom,
3337 Mmio2,
3338 Ram;
3339 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3340 uint32_t cIgnoredPages;
3341 /** Indicates that a live save operation is active. */
3342 bool fActive;
3343 /** Padding. */
3344 bool afReserved[2];
3345 /** The next history index. */
3346 uint8_t iDirtyPagesHistory;
3347 /** History of the total amount of dirty pages. */
3348 uint32_t acDirtyPagesHistory[64];
3349 /** Short term dirty page average. */
3350 uint32_t cDirtyPagesShort;
3351 /** Long term dirty page average. */
3352 uint32_t cDirtyPagesLong;
3353 /** The number of saved pages. This is used to get some kind of estimate of the
3354 * link speed so we can decide when we're done. It is reset after the first
3355 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3356 * zero pages. */
3357 uint64_t cSavedPages;
3358 /** The nanosecond timestamp when cSavedPages was 0. */
3359 uint64_t uSaveStartNS;
3360 /** Pages per second (for statistics). */
3361 uint32_t cPagesPerSecond;
3362 uint32_t cAlignment;
3363 } LiveSave;
3364
3365 /** @name Error injection.
3366 * @{ */
3367 /** Inject handy page allocation errors pretending we're completely out of
3368 * memory. */
3369 bool volatile fErrInjHandyPages;
3370 /** Padding. */
3371 bool afReserved[3];
3372 /** @} */
3373
3374 /** @name Release Statistics
3375 * @{ */
3376 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3377 uint32_t cPrivatePages; /**< The number of private pages. */
3378 uint32_t cSharedPages; /**< The number of shared pages. */
3379 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3380 uint32_t cZeroPages; /**< The number of zero backed pages. */
3381 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3382 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3383 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3384 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3385 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3386 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3387 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3388 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3389 uint32_t cLargePages; /**< The number of large pages. */
3390 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3391/* uint32_t aAlignment4[1]; */
3392
3393 /** The number of times we were forced to change the hypervisor region location. */
3394 STAMCOUNTER cRelocations;
3395
3396 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3397 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3398 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3399
3400 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3401 /** @} */
3402
3403#ifdef VBOX_WITH_STATISTICS
3404 /** @name Statistics on the heap.
3405 * @{ */
3406 R3PTRTYPE(PGMSTATS *) pStatsR3;
3407 R0PTRTYPE(PGMSTATS *) pStatsR0;
3408 /** @} */
3409#endif
3410} PGM;
3411#ifndef IN_TSTVMSTRUCTGC /* HACK */
3412# ifndef PGM_WITHOUT_MAPPINGS
3413AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3414# endif
3415AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3416# ifndef PGM_WITHOUT_MAPPINGS
3417AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3418# endif
3419AssertCompileMemberAlignment(PGM, CritSectX, 8);
3420AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3421AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3422AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3423AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3424AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3425AssertCompileMemberAlignment(PGM, cRelocations, 8);
3426#endif /* !IN_TSTVMSTRUCTGC */
3427/** Pointer to the PGM instance data. */
3428typedef PGM *PPGM;
3429
3430
3431
3432typedef struct PGMCPUSTATS
3433{
3434 /* Common */
3435 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3436 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3437
3438 /* R0 only: */
3439 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3440 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3441
3442 /* RZ only: */
3443 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3444 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3445 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3446 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3447 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3448 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3449 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3450 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3451 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3452 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3453 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3454 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3455 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3456 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3457 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3458 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3459 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3460 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3461 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3462 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3463 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3464 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3465 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3466 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3467 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3468 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3469 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3470 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3471 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3472 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3473 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3474 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3475 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3476 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3477 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3478 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3479 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3480 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3481 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3482 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3483 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3484 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3485 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3486 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3487 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3488 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3489 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3490 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3491 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3492 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3493 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3494 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3495 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3496 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3497 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3498 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3499 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3500 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3501 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3502 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3503 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3504 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3505 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3506 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3507 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3508 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3509 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3510 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3511 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3512 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3513 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3514 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3515 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3516
3517 /* HC - R3 and (maybe) R0: */
3518
3519 /* RZ & R3: */
3520 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3521 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3522 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3523 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3524 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3525 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3526 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3527 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3528 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3529 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3530 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3531 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3532 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3533 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3534 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3535 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3536 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3537 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3538 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3539 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3540 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3541 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3542 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3543 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3544 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3545 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3546 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3547 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3548 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3549 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3550 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3551 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3552 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3553 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3554 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3555 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3556 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3557 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3558 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3559 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3560 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3561 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3562 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3563 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3564 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3565 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3566 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3567 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3568
3569 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3570 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3571 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3572 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3573 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3574 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3575 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3576 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3577 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3578 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3579 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3580 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3581 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3582 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3583 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3584 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3585 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3586 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3587 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3588 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3589 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3590 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3591 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3592 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3593 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3594 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3595 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3596 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3597 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3598 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3599 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3600 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3601 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3602 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3603 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3604 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3605 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3606 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3607 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3608 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3609 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3610 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3611 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3612 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3613 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3614 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3615 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3616 /** @} */
3617} PGMCPUSTATS;
3618
3619
3620/**
3621 * Converts a PGMCPU pointer into a VM pointer.
3622 * @returns Pointer to the VM structure the PGM is part of.
3623 * @param pPGM Pointer to PGMCPU instance data.
3624 */
3625#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3626
3627/**
3628 * Converts a PGMCPU pointer into a PGM pointer.
3629 * @returns Pointer to the VM structure the PGM is part of.
3630 * @param pPGMCpu Pointer to PGMCPU instance data.
3631 */
3632#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3633
3634/**
3635 * PGMCPU Data (part of VMCPU).
3636 */
3637typedef struct PGMCPU
3638{
3639 /** Offset to the VM structure. */
3640 int32_t offVM;
3641 /** Offset to the VMCPU structure. */
3642 int32_t offVCpu;
3643 /** Offset of the PGM structure relative to VMCPU. */
3644 int32_t offPGM;
3645 uint32_t uPadding0; /**< structure size alignment. */
3646
3647#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3648 /** Automatically tracked physical memory mapping set.
3649 * Ring-0 and strict raw-mode builds. */
3650 PGMMAPSET AutoSet;
3651#endif
3652
3653 /** A20 gate mask.
3654 * Our current approach to A20 emulation is to let REM do it and don't bother
3655 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3656 * But whould need arrise, we'll subject physical addresses to this mask. */
3657 RTGCPHYS GCPhysA20Mask;
3658 /** A20 gate state - boolean! */
3659 bool fA20Enabled;
3660 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3661 bool fNoExecuteEnabled;
3662 /** Unused bits. */
3663 bool afUnused[2];
3664
3665 /** What needs syncing (PGM_SYNC_*).
3666 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3667 * PGMFlushTLB, and PGMR3Load. */
3668 uint32_t fSyncFlags;
3669
3670 /** The shadow paging mode. */
3671 PGMMODE enmShadowMode;
3672 /** The guest paging mode. */
3673 PGMMODE enmGuestMode;
3674 /** Guest mode data table index (PGM_TYPE_XXX). */
3675 uint8_t volatile idxGuestModeData;
3676 /** Shadow mode data table index (PGM_TYPE_XXX). */
3677 uint8_t volatile idxShadowModeData;
3678 /** Both mode data table index (complicated). */
3679 uint8_t volatile idxBothModeData;
3680 /** Alignment padding. */
3681 uint8_t abPadding[5];
3682
3683 /** The current physical address represented in the guest CR3 register. */
3684 RTGCPHYS GCPhysCR3;
3685
3686 /** @name 32-bit Guest Paging.
3687 * @{ */
3688 /** The guest's page directory, R3 pointer. */
3689 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3690#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3691 /** The guest's page directory, R0 pointer. */
3692 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3693#endif
3694 /** Mask containing the MBZ bits of a big page PDE. */
3695 uint32_t fGst32BitMbzBigPdeMask;
3696 /** Set if the page size extension (PSE) is enabled. */
3697 bool fGst32BitPageSizeExtension;
3698 /** Alignment padding. */
3699 bool afAlignment2[3];
3700 /** @} */
3701
3702 /** @name PAE Guest Paging.
3703 * @{ */
3704 /** The guest's page directory pointer table, R3 pointer. */
3705 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3706#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3707 /** The guest's page directory pointer table, R0 pointer. */
3708 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3709#endif
3710
3711 /** The guest's page directories, R3 pointers.
3712 * These are individual pointers and don't have to be adjacent.
3713 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3714 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3715 /** The guest's page directories, R0 pointers.
3716 * Same restrictions as apGstPaePDsR3. */
3717#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3718 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3719#endif
3720 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3721 * @todo Remove this and use aGstPaePdpeRegs instead? */
3722 RTGCPHYS aGCPhysGstPaePDs[4];
3723 /** The values of the 4 PDPE CPU registers (PAE). */
3724 X86PDPE aGstPaePdpeRegs[4];
3725 /** The physical addresses of the monitored guest page directories (PAE). */
3726 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3727 /** Mask containing the MBZ PTE bits. */
3728 uint64_t fGstPaeMbzPteMask;
3729 /** Mask containing the MBZ PDE bits. */
3730 uint64_t fGstPaeMbzPdeMask;
3731 /** Mask containing the MBZ big page PDE bits. */
3732 uint64_t fGstPaeMbzBigPdeMask;
3733 /** Mask containing the MBZ PDPE bits. */
3734 uint64_t fGstPaeMbzPdpeMask;
3735 /** @} */
3736
3737 /** @name AMD64 Guest Paging.
3738 * @{ */
3739 /** The guest's page directory pointer table, R3 pointer. */
3740 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3741#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3742 /** The guest's page directory pointer table, R0 pointer. */
3743 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3744#else
3745 RTR0PTR alignment6b; /**< alignment equalizer. */
3746#endif
3747 /** Mask containing the MBZ PTE bits. */
3748 uint64_t fGstAmd64MbzPteMask;
3749 /** Mask containing the MBZ PDE bits. */
3750 uint64_t fGstAmd64MbzPdeMask;
3751 /** Mask containing the MBZ big page PDE bits. */
3752 uint64_t fGstAmd64MbzBigPdeMask;
3753 /** Mask containing the MBZ PDPE bits. */
3754 uint64_t fGstAmd64MbzPdpeMask;
3755 /** Mask containing the MBZ big page PDPE bits. */
3756 uint64_t fGstAmd64MbzBigPdpeMask;
3757 /** Mask containing the MBZ PML4E bits. */
3758 uint64_t fGstAmd64MbzPml4eMask;
3759 /** Mask containing the PDPE bits that we shadow. */
3760 uint64_t fGstAmd64ShadowedPdpeMask;
3761 /** Mask containing the PML4E bits that we shadow. */
3762 uint64_t fGstAmd64ShadowedPml4eMask;
3763 /** @} */
3764
3765 /** @name PAE and AMD64 Guest Paging.
3766 * @{ */
3767 /** Mask containing the PTE bits that we shadow. */
3768 uint64_t fGst64ShadowedPteMask;
3769 /** Mask containing the PDE bits that we shadow. */
3770 uint64_t fGst64ShadowedPdeMask;
3771 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3772 uint64_t fGst64ShadowedBigPdeMask;
3773 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3774 uint64_t fGst64ShadowedBigPde4PteMask;
3775 /** @} */
3776
3777 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3778 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3779 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3780 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3781 /** @} */
3782
3783 /** For saving stack space, the disassembler state is allocated here instead of
3784 * on the stack. */
3785 DISCPUSTATE DisState;
3786
3787 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3788 uint64_t cNetwareWp0Hacks;
3789
3790 /** Count the number of pgm pool access handler calls. */
3791 uint64_t cPoolAccessHandler;
3792
3793 /** @name Release Statistics
3794 * @{ */
3795 /** The number of times the guest has switched mode since last reset or statistics reset. */
3796 STAMCOUNTER cGuestModeChanges;
3797 /** The number of times the guest has switched mode since last reset or statistics reset. */
3798 STAMCOUNTER cA20Changes;
3799 /** @} */
3800
3801#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3802 /** @name Statistics
3803 * @{ */
3804 /** R0: Pointer to the statistics. */
3805 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3806 /** R0: Which statistic this \#PF should be attributed to. */
3807 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3808 /** R3: Pointer to the statistics. */
3809 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3810 /** Alignment padding. */
3811 RTR3PTR pPaddingR3;
3812 /** @} */
3813#endif /* VBOX_WITH_STATISTICS */
3814} PGMCPU;
3815/** Pointer to the per-cpu PGM data. */
3816typedef PGMCPU *PPGMCPU;
3817
3818
3819/** @name PGM::fSyncFlags Flags
3820 * @note Was part of saved state a long time ago.
3821 * @{
3822 */
3823/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3824/** Always sync CR3. */
3825#define PGM_SYNC_ALWAYS RT_BIT(1)
3826/** Check monitoring on next CR3 (re)load and invalidate page.
3827 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3828#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3829/** Check guest mapping in SyncCR3. */
3830#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3831/** Clear the page pool (a light weight flush). */
3832#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3833#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3834/** @} */
3835
3836
3837RT_C_DECLS_BEGIN
3838
3839#if defined(VBOX_STRICT) && defined(IN_RING3)
3840int pgmLockDebug(PVMCC pVM, RT_SRC_POS_DECL);
3841# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
3842#else
3843int pgmLock(PVMCC pVM);
3844#endif
3845void pgmUnlock(PVM pVM);
3846/**
3847 * Asserts that the caller owns the PDM lock.
3848 * This is the internal variant of PGMIsLockOwner.
3849 * @param a_pVM Pointer to the VM.
3850 */
3851#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
3852/**
3853 * Asserts that the caller owns the PDM lock.
3854 * This is the internal variant of PGMIsLockOwner.
3855 * @param a_pVM Pointer to the VM.
3856 * @param a_pVCpu The current CPU handle.
3857 */
3858#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
3859
3860#ifndef PGM_WITHOUT_MAPPINGS
3861int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3862int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3863int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3864int pgmMapResolveConflicts(PVM pVM);
3865PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3866DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3867#endif /* !PGM_WITHOUT_MAPPINGS */
3868
3869int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3870 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3871int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3872int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3873int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
3874int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3875void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3876bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3877void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3878DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3879int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3880
3881int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3882int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3883int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3884int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3885int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3886void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3887int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3888int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3889int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3890int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3891int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3892int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3893int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3894int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3895int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3896int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3897void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3898PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3899#ifndef IN_RING3
3900DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3901DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3902DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3903#endif
3904int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3905 PGMPAGETYPE enmNewType);
3906void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3907void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3908void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
3909PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3910PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3911PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3912int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3913int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3914
3915#ifdef IN_RING3
3916void pgmR3PhysRelinkRamRanges(PVM pVM);
3917int pgmR3PhysRamPreAllocate(PVM pVM);
3918int pgmR3PhysRamReset(PVM pVM);
3919int pgmR3PhysRomReset(PVM pVM);
3920int pgmR3PhysRamZeroAll(PVM pVM);
3921int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3922int pgmR3PhysRamTerm(PVM pVM);
3923void pgmR3PhysRomTerm(PVM pVM);
3924void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3925
3926int pgmR3PoolInit(PVM pVM);
3927void pgmR3PoolRelocate(PVM pVM);
3928void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3929void pgmR3PoolReset(PVM pVM);
3930void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3931DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3932void pgmR3PoolWriteProtectPages(PVM pVM);
3933
3934#endif /* IN_RING3 */
3935#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3936int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3937int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3938# ifdef LOG_ENABLED
3939void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3940# else
3941void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3942# endif
3943#endif
3944int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3945 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3946void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3947void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3948int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3949void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3950PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3951PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3952int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3953bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
3954void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3955int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3956void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3957uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3958void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3959void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3960void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3961PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3962#ifndef IN_RING3
3963DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3964#endif
3965
3966void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3967void pgmPoolResetDirtyPages(PVMCC pVM);
3968void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3969
3970int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3971int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3972void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3973
3974#ifndef PGM_WITHOUT_MAPPINGS
3975void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3976void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3977int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3978int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3979#endif
3980
3981int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3982int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3983int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3984
3985int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3986int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3987int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3988int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3989int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3990int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3991
3992# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3993FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3994FNDBGCCMD pgmR3CmdShowSharedModules;
3995# endif
3996
3997void pgmLogState(PVM pVM);
3998
3999RT_C_DECLS_END
4000
4001/** @} */
4002
4003#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4004
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