PGMInternal.h@ 82819

Last change on this file since 82819 was 82819, checked in by vboxsync, 5 years ago
PGMInternal.h: doxygen fix.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 182.8 KB

Line
1	/* $Id: PGMInternal.h 82819 2020-01-22 11:13:12Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/hm_vmx.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/avl.h>
43	#include <iprt/critsect.h>
44	#include <iprt/list-off32.h>
45	#include <iprt/sha.h>
46
47
48
49	/** @defgroup grp_pgm_int Internals
50	* @ingroup grp_pgm
51	* @internal
52	* @{
53	*/
54
55
56	/** @name PGM Compile Time Config
57	* @{
58	*/
59
60	/**
61	* Indicates that there are no guest mappings in the shadow tables.
62	*
63	* Note! In ring-3 the macro is also used to exclude the managment of the
64	* intermediate context page tables. On 32-bit systems we use the intermediate
65	* context to support 64-bit guest execution. Thus, we cannot fully make it
66	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67	*
68	* In raw-mode context there are by design always guest mappings (the code is
69	* executed from one), while in ring-0 there are none at all. Neither context
70	* manages the page tables for intermediate switcher context, that's all done in
71	* ring-3.
72	*
73	* Update 6.1: It is always defined now, in pgm.h
74	*/
75	#if defined(IN_RING0) \
76	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
77	&& ( HC_ARCH_BITS != 32 \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# undef PGM_WITHOUT_MAPPINGS
82	# define PGM_WITHOUT_MAPPINGS
83	#endif
84
85	/**
86	* Check and skip global PDEs for non-global flushes
87	*/
88	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90	/**
91	* Optimization for PAE page tables that are modified often
92	*/
93	//#if 0 /* disabled again while debugging */
94	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	//#endif
96
97	/**
98	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
99	*/
100	#define PGM_WITH_LARGE_PAGES
101
102	/**
103	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
104	* VMX_EXIT_EPT_MISCONFIG.
105	*/
106	#define PGM_WITH_MMIO_OPTIMIZATIONS
107
108	/**
109	* Sync N pages instead of a whole page table
110	*/
111	#define PGM_SYNC_N_PAGES
112
113	/**
114	* Number of pages to sync during a page fault
115	*
116	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118	*
119	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120	* world switch overhead, so let's sync more.
121	*/
122	# ifdef IN_RING0
123	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125	* but ~5% fewer faults.
126	*/
127	# define PGM_SYNC_NR_PAGES 32
128	#else
129	# define PGM_SYNC_NR_PAGES 8
130	#endif
131
132	/**
133	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134	*/
135	#define PGM_MAX_PHYSCACHE_ENTRIES 64
136	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139	/** @def PGMPOOL_CFG_MAX_GROW
140	* The maximum number of pages to add to the pool in one go.
141	*/
142	#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
143
144	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
146	*/
147	#ifdef VBOX_STRICT
148	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149	#endif
150
151	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152	* Enables the experimental lazy page allocation code. */
153	#ifdef DOXYGEN_RUNNING
154	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155	#endif
156
157	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158	* Enables real write monitoring of pages, i.e. mapping them read-only and
159	* only making them writable when getting a write access \#PF. */
160	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162	/** @} */
163
164
165	/** @name PDPT and PML4 flags.
166	* These are placed in the three bits available for system programs in
167	* the PDPT and PML4 entries.
168	* @{ */
169	/** The entry is a permanent one and it's must always be present.
170	* Never free such an entry. */
171	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172	/** Mapping (hypervisor allocated pagetable). */
173	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174	/** @} */
175
176	/** @name Page directory flags.
177	* These are placed in the three bits available for system programs in
178	* the page directory entries.
179	* @{ */
180	/** Indicates the original entry was a big page.
181	* @remarks This is currently only used for statistics and can be recycled. */
182	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED_32BIT 6
213	#define PGM_TYPE_NESTED_PAE 7
214	#define PGM_TYPE_NESTED_AMD64 8
215	#define PGM_TYPE_EPT 9
216	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
217	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
218	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
219	/** @} */
220
221	/** Macro for checking if the guest is using paging.
222	* @param uGstType PGM_TYPE_*
223	* @param uShwType PGM_TYPE_*
224	* @remark ASSUMES certain order of the PGM_TYPE_* values.
225	*/
226	#define PGM_WITH_PAGING(uGstType, uShwType) \
227	( (uGstType) >= PGM_TYPE_32BIT \
228	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
229
230	/** Macro for checking if the guest supports the NX bit.
231	* @param uGstType PGM_TYPE_*
232	* @param uShwType PGM_TYPE_*
233	* @remark ASSUMES certain order of the PGM_TYPE_* values.
234	*/
235	#define PGM_WITH_NX(uGstType, uShwType) \
236	( (uGstType) >= PGM_TYPE_PAE \
237	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
238
239	/** Macro for checking for nested or EPT.
240	* @param uType PGM_TYPE_*
241	*/
242	#define PGM_TYPE_IS_NESTED(uType) \
243	( (uType) == PGM_TYPE_NESTED_32BIT \
244	\|\| (uType) == PGM_TYPE_NESTED_PAE \
245	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
246
247	/** Macro for checking for nested or EPT.
248	* @param uType PGM_TYPE_*
249	*/
250	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
251	( (uType) == PGM_TYPE_NESTED_32BIT \
252	\|\| (uType) == PGM_TYPE_NESTED_PAE \
253	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
254	\|\| (uType) == PGM_TYPE_EPT)
255
256
257
258	/** @def PGM_HCPHYS_2_PTR
259	* Maps a HC physical page pool address to a virtual address.
260	*
261	* @returns VBox status code.
262	* @param pVM The cross context VM structure.
263	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
264	* @param HCPhys The HC physical address to map to a virtual one.
265	* @param ppv Where to store the virtual address. No need to cast
266	* this.
267	*
268	* @remark There is no need to assert on the result.
269	*/
270	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
271
272	/** @def PGM_GCPHYS_2_PTR_V2
273	* Maps a GC physical page address to a virtual address.
274	*
275	* @returns VBox status code.
276	* @param pVM The cross context VM structure.
277	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
278	* @param GCPhys The GC physical address to map to a virtual one.
279	* @param ppv Where to store the virtual address. No need to cast this.
280	*
281	* @remark Use with care as we don't have so much dynamic mapping space in
282	* ring-0 on 32-bit darwin and in RC.
283	* @remark There is no need to assert on the result.
284	*/
285	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
286	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
287	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
288	#else
289	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
290	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
291	#endif
292
293	/** @def PGM_GCPHYS_2_PTR
294	* Maps a GC physical page address to a virtual address.
295	*
296	* @returns VBox status code.
297	* @param pVM The cross context VM structure.
298	* @param GCPhys The GC physical address to map to a virtual one.
299	* @param ppv Where to store the virtual address. No need to cast this.
300	*
301	* @remark Use with care as we don't have so much dynamic mapping space in
302	* ring-0 on 32-bit darwin and in RC.
303	* @remark There is no need to assert on the result.
304	*/
305	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
306
307	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
308	* Maps a GC physical page address to a virtual address.
309	*
310	* @returns VBox status code.
311	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
312	* @param GCPhys The GC physical address to map to a virtual one.
313	* @param ppv Where to store the virtual address. No need to cast this.
314	*
315	* @remark Use with care as we don't have so much dynamic mapping space in
316	* ring-0 on 32-bit darwin and in RC.
317	* @remark There is no need to assert on the result.
318	*/
319	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
320
321	/** @def PGM_GCPHYS_2_PTR_EX
322	* Maps a unaligned GC physical page address to a virtual address.
323	*
324	* @returns VBox status code.
325	* @param pVM The cross context VM structure.
326	* @param GCPhys The GC physical address to map to a virtual one.
327	* @param ppv Where to store the virtual address. No need to cast this.
328	*
329	* @remark Use with care as we don't have so much dynamic mapping space in
330	* ring-0 on 32-bit darwin and in RC.
331	* @remark There is no need to assert on the result.
332	*/
333	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
334	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
335	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
336	#else
337	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
338	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
339	#endif
340
341	/** @def PGM_DYNMAP_UNUSED_HINT
342	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
343	* is no longer used.
344	*
345	* For best effect only apply this to the page that was mapped most recently.
346	*
347	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
348	* @param pvPage The pool page.
349	*/
350	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
351	# ifdef LOG_ENABLED
352	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
353	# else
354	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
355	# endif
356	#else
357	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
358	#endif
359
360	/** @def PGM_DYNMAP_UNUSED_HINT_VM
361	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
362	* is no longer used.
363	*
364	* For best effect only apply this to the page that was mapped most recently.
365	*
366	* @param pVM The cross context VM structure.
367	* @param pvPage The pool page.
368	*/
369	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
370
371
372	/** @def PGM_INVL_PG
373	* Invalidates a page.
374	*
375	* @param pVCpu The cross context virtual CPU structure.
376	* @param GCVirt The virtual address of the page to invalidate.
377	*/
378	#ifdef IN_RING0
379	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
380	#elif defined(IN_RING3)
381	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
382	#else
383	# error "Not IN_RING0 or IN_RING3!"
384	#endif
385
386	/** @def PGM_INVL_PG_ALL_VCPU
387	* Invalidates a page on all VCPUs
388	*
389	* @param pVM The cross context VM structure.
390	* @param GCVirt The virtual address of the page to invalidate.
391	*/
392	#ifdef IN_RING0
393	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
394	#else
395	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
396	#endif
397
398	/** @def PGM_INVL_BIG_PG
399	* Invalidates a 4MB page directory entry.
400	*
401	* @param pVCpu The cross context virtual CPU structure.
402	* @param GCVirt The virtual address within the page directory to invalidate.
403	*/
404	#ifdef IN_RING0
405	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
406	#else
407	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
408	#endif
409
410	/** @def PGM_INVL_VCPU_TLBS()
411	* Invalidates the TLBs of the specified VCPU
412	*
413	* @param pVCpu The cross context virtual CPU structure.
414	*/
415	#ifdef IN_RING0
416	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
417	#else
418	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
419	#endif
420
421	/** @def PGM_INVL_ALL_VCPU_TLBS()
422	* Invalidates the TLBs of all VCPUs
423	*
424	* @param pVM The cross context VM structure.
425	*/
426	#ifdef IN_RING0
427	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
428	#else
429	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
430	#endif
431
432
433	/** @name Safer Shadow PAE PT/PTE
434	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
435	* present.
436	*
437	* @{
438	*/
439	#if 1
440	/**
441	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
442	* invalid entries for present.
443	* @sa X86PTEPAE.
444	*/
445	typedef union PGMSHWPTEPAE
446	{
447	/** Unsigned integer view */
448	X86PGPAEUINT uCareful;
449	/* Not other views. */
450	} PGMSHWPTEPAE;
451
452	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
453	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
454	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
455	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
456	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
457	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
458	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
459	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
460	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
461	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
462	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
463	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
464	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
465	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
466	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
467	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
468
469	/**
470	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
471	* invalid entries for present.
472	* @sa X86PTPAE.
473	*/
474	typedef struct PGMSHWPTPAE
475	{
476	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
477	} PGMSHWPTPAE;
478
479	#else
480	typedef X86PTEPAE PGMSHWPTEPAE;
481	typedef X86PTPAE PGMSHWPTPAE;
482	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
483	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
484	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
485	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
486	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
487	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
488	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
489	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
490	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
491	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
492	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
493	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
494	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
495	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
496	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
497	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
498
499	#endif
500
501	/** Pointer to a shadow PAE PTE. */
502	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
503	/** Pointer to a const shadow PAE PTE. */
504	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
505
506	/** Pointer to a shadow PAE page table. */
507	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
508	/** Pointer to a const shadow PAE page table. */
509	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
510	/** @} */
511
512	#ifndef PGM_WITHOUT_MAPPINGS
513
514	/** Size of the GCPtrConflict array in PGMMAPPING.
515	* @remarks Must be a power of two. */
516	# define PGMMAPPING_CONFLICT_MAX 8
517
518	/**
519	* Structure for tracking GC Mappings.
520	*
521	* This structure is used by linked list in both GC and HC.
522	*/
523	typedef struct PGMMAPPING
524	{
525	/** Pointer to next entry. */
526	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
527	/** Pointer to next entry. */
528	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
529	/** Indicate whether this entry is finalized. */
530	bool fFinalized;
531	bool afPadding[7];
532	/** Start Virtual address. */
533	RTGCPTR GCPtr;
534	/** Last Virtual address (inclusive). */
535	RTGCPTR GCPtrLast;
536	/** Range size (bytes). */
537	RTGCPTR cb;
538	/** Pointer to relocation callback function. */
539	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
540	/** User argument to the callback. */
541	R3PTRTYPE(void *) pvUser;
542	/** Mapping description / name. For easing debugging. */
543	R3PTRTYPE(const char *) pszDesc;
544	/** Last 8 addresses that caused conflicts. */
545	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
546	/** Number of conflicts for this hypervisor mapping. */
547	uint32_t cConflicts;
548	/** Number of page tables. */
549	uint32_t cPTs;
550
551	/** Array of page table mapping data. Each entry
552	* describes one page table. The array can be longer
553	* than the declared length.
554	*/
555	struct
556	{
557	/** The HC physical address of the page table. */
558	RTHCPHYS HCPhysPT;
559	/** The HC physical address of the first PAE page table. */
560	RTHCPHYS HCPhysPaePT0;
561	/** The HC physical address of the second PAE page table. */
562	RTHCPHYS HCPhysPaePT1;
563	/** The HC virtual address of the 32-bit page table. */
564	R3PTRTYPE(PX86PT) pPTR3;
565	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
566	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
567	/** The R0 virtual address of the 32-bit page table. */
568	R0PTRTYPE(PX86PT) pPTR0;
569	/** The R0 virtual address of the two PAE page table. */
570	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571	} aPTs[1];
572	} PGMMAPPING;
573	/** Pointer to structure for tracking GC Mappings. */
574	typedef struct PGMMAPPING *PPGMMAPPING;
575
576	#endif /* !PGM_WITHOUT_MAPPINGS */
577
578
579	/**
580	* Physical page access handler type registration.
581	*/
582	typedef struct PGMPHYSHANDLERTYPEINT
583	{
584	/** Number of references. */
585	uint32_t volatile cRefs;
586	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
587	uint32_t u32Magic;
588	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
589	RTLISTOFF32NODE ListNode;
590	/** The kind of accesses we're handling. */
591	PGMPHYSHANDLERKIND enmKind;
592	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
593	uint32_t uState;
594	/** Pointer to R3 callback function. */
595	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
596	/** Pointer to R0 callback function. */
597	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
598	/** Pointer to R0 callback function for \#PFs. */
599	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
600	/** Description / Name. For easing debugging. */
601	R3PTRTYPE(const char *) pszDesc;
602	} PGMPHYSHANDLERTYPEINT;
603	/** Pointer to a physical access handler type registration. */
604	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
605	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
606	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
607	/** Magic value for the physical handler callbacks. */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
609
610	/**
611	* Converts a handle to a pointer.
612	* @returns PPGMPHYSHANDLERTYPEINT
613	* @param a_pVM The cross context VM structure.
614	* @param a_hType Physical access handler type handle.
615	*/
616	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
617
618
619	/**
620	* Physical page access handler structure.
621	*
622	* This is used to keep track of physical address ranges
623	* which are being monitored in some kind of way.
624	*/
625	typedef struct PGMPHYSHANDLER
626	{
627	AVLROGCPHYSNODECORE Core;
628	/** Number of pages to update. */
629	uint32_t cPages;
630	/** Set if we have pages that have been aliased. */
631	uint32_t cAliasedPages;
632	/** Set if we have pages that have temporarily been disabled. */
633	uint32_t cTmpOffPages;
634	/** Registered handler type handle (heap offset). */
635	PGMPHYSHANDLERTYPE hType;
636	/** User argument for R3 handlers. */
637	R3PTRTYPE(void *) pvUserR3;
638	/** User argument for R0 handlers. */
639	R0PTRTYPE(void *) pvUserR0;
640	/** Description / Name. For easing debugging. */
641	R3PTRTYPE(const char *) pszDesc;
642	#ifdef VBOX_WITH_STATISTICS
643	/** Profiling of this handler. */
644	STAMPROFILE Stat;
645	#endif
646	} PGMPHYSHANDLER;
647	/** Pointer to a physical page access handler structure. */
648	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
649
650	/**
651	* Gets the type record for a physical handler (no reference added).
652	* @returns PPGMPHYSHANDLERTYPEINT
653	* @param a_pVM The cross context VM structure.
654	* @param a_pPhysHandler Pointer to the physical handler structure
655	* (PGMPHYSHANDLER).
656	*/
657	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
658
659
660	/**
661	* A Physical Guest Page tracking structure.
662	*
663	* The format of this structure is complicated because we have to fit a lot
664	* of information into as few bits as possible. The format is also subject
665	* to change (there is one coming up soon). Which means that for we'll be
666	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
667	* accesses to the structure.
668	*/
669	typedef union PGMPAGE
670	{
671	/** Structured view. */
672	struct
673	{
674	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
675	uint64_t u2HandlerPhysStateY : 2;
676	/** 3:2 - Paging structure needed to map the page
677	* (PGM_PAGE_PDE_TYPE_). /
678	uint64_t u2PDETypeY : 2;
679	/** 4 - Unused (was used by FTE for dirty tracking). */
680	uint64_t fUnused1 : 1;
681	/** 5 - Flag indicating that a write monitored page was written to
682	* when set. */
683	uint64_t fWrittenToY : 1;
684	/** 7:6 - Unused. */
685	uint64_t u2Unused0 : 2;
686	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
687	uint64_t u2Unused1 : 2;
688	/** 11:10 - NEM state bits. */
689	uint64_t u2NemStateY : 2;
690	/** 12:48 - The host physical frame number (shift left to get the
691	* address). */
692	uint64_t HCPhysFN : 36;
693	/** 50:48 - The page state. */
694	uint64_t uStateY : 3;
695	/** 51:53 - The page type (PGMPAGETYPE). */
696	uint64_t uTypeY : 3;
697	/** 63:54 - PTE index for usage tracking (page pool). */
698	uint64_t u10PteIdx : 10;
699
700	/** The GMM page ID.
701	* @remarks In the current implementation, MMIO2 and pages aliased to
702	* MMIO2 pages will be exploiting this field to calculate the
703	* ring-3 mapping address corresponding to the page.
704	* Later we may consider including MMIO2 management into GMM. */
705	uint32_t idPage;
706	/** Usage tracking (page pool). */
707	uint16_t u16TrackingY;
708	/** The number of read locks on this page. */
709	uint8_t cReadLocksY;
710	/** The number of write locks on this page. */
711	uint8_t cWriteLocksY;
712	} s;
713
714	/** 64-bit integer view. */
715	uint64_t au64[2];
716	/** 16-bit view. */
717	uint32_t au32[4];
718	/** 16-bit view. */
719	uint16_t au16[8];
720	/** 8-bit view. */
721	uint8_t au8[16];
722	} PGMPAGE;
723	AssertCompileSize(PGMPAGE, 16);
724	/** Pointer to a physical guest page. */
725	typedef PGMPAGE *PPGMPAGE;
726	/** Pointer to a const physical guest page. */
727	typedef const PGMPAGE *PCPGMPAGE;
728	/** Pointer to a physical guest page pointer. */
729	typedef PPGMPAGE *PPPGMPAGE;
730
731
732	/**
733	* Clears the page structure.
734	* @param a_pPage Pointer to the physical guest page tracking structure.
735	*/
736	#define PGM_PAGE_CLEAR(a_pPage) \
737	do { \
738	(a_pPage)->au64[0] = 0; \
739	(a_pPage)->au64[1] = 0; \
740	} while (0)
741
742	/**
743	* Initializes the page structure.
744	* @param a_pPage Pointer to the physical guest page tracking structure.
745	* @param a_HCPhys The host physical address of the page.
746	* @param a_idPage The (GMM) page ID of the page.
747	* @param a_uType The page type (PGMPAGETYPE).
748	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
749	*/
750	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
751	do { \
752	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
753	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
754	(a_pPage)->au64[0] = SetHCPhysTmp; \
755	(a_pPage)->au64[1] = 0; \
756	(a_pPage)->s.idPage = (a_idPage); \
757	(a_pPage)->s.uStateY = (a_uState); \
758	(a_pPage)->s.uTypeY = (a_uType); \
759	} while (0)
760
761	/**
762	* Initializes the page structure of a ZERO page.
763	* @param a_pPage Pointer to the physical guest page tracking structure.
764	* @param a_pVM The VM handle (for getting the zero page address).
765	* @param a_uType The page type (PGMPAGETYPE).
766	*/
767	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
768	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
769
770
771	/** @name The Page state, PGMPAGE::uStateY.
772	* @{ */
773	/** The zero page.
774	* This is a per-VM page that's never ever mapped writable. */
775	#define PGM_PAGE_STATE_ZERO 0U
776	/** A allocated page.
777	* This is a per-VM page allocated from the page pool (or wherever
778	* we get MMIO2 pages from if the type is MMIO2).
779	*/
780	#define PGM_PAGE_STATE_ALLOCATED 1U
781	/** A allocated page that's being monitored for writes.
782	* The shadow page table mappings are read-only. When a write occurs, the
783	* fWrittenTo member is set, the page remapped as read-write and the state
784	* moved back to allocated. */
785	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
786	/** The page is shared, aka. copy-on-write.
787	* This is a page that's shared with other VMs. */
788	#define PGM_PAGE_STATE_SHARED 3U
789	/** The page is ballooned, so no longer available for this VM. */
790	#define PGM_PAGE_STATE_BALLOONED 4U
791	/** @} */
792
793
794	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
795	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
796	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
797	#else
798	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
799	#endif
800
801	/**
802	* Gets the page state.
803	* @returns page state (PGM_PAGE_STATE_*).
804	* @param a_pPage Pointer to the physical guest page tracking structure.
805	*
806	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
807	* builds.
808	*/
809	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
810	#if defined(__GNUC__) && defined(VBOX_STRICT)
811	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
812	#else
813	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
814	#endif
815
816	/**
817	* Sets the page state.
818	* @param a_pVM The VM handle, only used for lock ownership assertions.
819	* @param a_pPage Pointer to the physical guest page tracking structure.
820	* @param a_uState The new page state.
821	*/
822	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
823	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
824
825
826	/**
827	* Gets the host physical address of the guest page.
828	* @returns host physical address (RTHCPHYS).
829	* @param a_pPage Pointer to the physical guest page tracking structure.
830	*
831	* @remarks In strict builds on gcc platforms, this macro will make some ugly
832	* assumption about a valid pVM variable/parameter being in the
833	* current context. It will use this pVM variable to assert that the
834	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
835	* pVM is not around.
836	*/
837	#if 0
838	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
839	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
840	#else
841	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
842	# if defined(__GNUC__) && defined(VBOX_STRICT)
843	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
844	# else
845	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
846	# endif
847	#endif
848
849	/**
850	* Sets the host physical address of the guest page.
851	*
852	* @param a_pVM The VM handle, only used for lock ownership assertions.
853	* @param a_pPage Pointer to the physical guest page tracking structure.
854	* @param a_HCPhys The new host physical address.
855	*/
856	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
857	do { \
858	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
859	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
860	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
861	PGM_PAGE_ASSERT_LOCK(a_pVM); \
862	} while (0)
863
864	/**
865	* Get the Page ID.
866	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
867	* @param a_pPage Pointer to the physical guest page tracking structure.
868	*/
869	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
870
871	/**
872	* Sets the Page ID.
873	* @param a_pVM The VM handle, only used for lock ownership assertions.
874	* @param a_pPage Pointer to the physical guest page tracking structure.
875	* @param a_idPage The new page ID.
876	*/
877	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
878	do { \
879	(a_pPage)->s.idPage = (a_idPage); \
880	PGM_PAGE_ASSERT_LOCK(a_pVM); \
881	} while (0)
882
883	/**
884	* Get the Chunk ID.
885	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
886	* @param a_pPage Pointer to the physical guest page tracking structure.
887	*/
888	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
889
890	/**
891	* Get the index of the page within the allocation chunk.
892	* @returns The page index.
893	* @param a_pPage Pointer to the physical guest page tracking structure.
894	*/
895	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
896
897	/**
898	* Gets the page type.
899	* @returns The page type.
900	* @param a_pPage Pointer to the physical guest page tracking structure.
901	*
902	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
903	* builds.
904	*/
905	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
906	#if defined(__GNUC__) && defined(VBOX_STRICT)
907	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
908	#else
909	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
910	#endif
911
912	/**
913	* Sets the page type.
914	*
915	* @param a_pVM The VM handle, only used for lock ownership assertions.
916	* @param a_pPage Pointer to the physical guest page tracking structure.
917	* @param a_enmType The new page type (PGMPAGETYPE).
918	*/
919	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
920	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
921
922	/**
923	* Gets the page table index
924	* @returns The page table index.
925	* @param a_pPage Pointer to the physical guest page tracking structure.
926	*/
927	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
928
929	/**
930	* Sets the page table index.
931	* @param a_pVM The VM handle, only used for lock ownership assertions.
932	* @param a_pPage Pointer to the physical guest page tracking structure.
933	* @param a_iPte New page table index.
934	*/
935	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
936	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
937
938	/**
939	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
940	* @returns true/false.
941	* @param a_pPage Pointer to the physical guest page tracking structure.
942	*/
943	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
944
945	/**
946	* Checks if the page is marked for MMIO, including both aliases.
947	* @returns true/false.
948	* @param a_pPage Pointer to the physical guest page tracking structure.
949	*/
950	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
951	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
952	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
953	)
954
955	/**
956	* Checks if the page is marked for MMIO, including special aliases.
957	* @returns true/false.
958	* @param a_pPage Pointer to the physical guest page tracking structure.
959	*/
960	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
961	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
962
963	/**
964	* Checks if the page is a special aliased MMIO page.
965	* @returns true/false.
966	* @param a_pPage Pointer to the physical guest page tracking structure.
967	*/
968	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
969
970	/**
971	* Checks if the page is backed by the ZERO page.
972	* @returns true/false.
973	* @param a_pPage Pointer to the physical guest page tracking structure.
974	*/
975	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
976
977	/**
978	* Checks if the page is backed by a SHARED page.
979	* @returns true/false.
980	* @param a_pPage Pointer to the physical guest page tracking structure.
981	*/
982	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
983
984	/**
985	* Checks if the page is ballooned.
986	* @returns true/false.
987	* @param a_pPage Pointer to the physical guest page tracking structure.
988	*/
989	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
990
991	/**
992	* Checks if the page is allocated.
993	* @returns true/false.
994	* @param a_pPage Pointer to the physical guest page tracking structure.
995	*/
996	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
997
998	/**
999	* Marks the page as written to (for GMM change monitoring).
1000	* @param a_pVM The VM handle, only used for lock ownership assertions.
1001	* @param a_pPage Pointer to the physical guest page tracking structure.
1002	*/
1003	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1004	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1005
1006	/**
1007	* Clears the written-to indicator.
1008	* @param a_pVM The VM handle, only used for lock ownership assertions.
1009	* @param a_pPage Pointer to the physical guest page tracking structure.
1010	*/
1011	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1012	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1013
1014	/**
1015	* Checks if the page was marked as written-to.
1016	* @returns true/false.
1017	* @param a_pPage Pointer to the physical guest page tracking structure.
1018	*/
1019	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1020
1021
1022	/** @name PT usage values (PGMPAGE::u2PDEType).
1023	*
1024	* @{ */
1025	/** Either as a PT or PDE. */
1026	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1027	/** Must use a page table to map the range. */
1028	#define PGM_PAGE_PDE_TYPE_PT 1
1029	/** Can use a page directory entry to map the continuous range. */
1030	#define PGM_PAGE_PDE_TYPE_PDE 2
1031	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1032	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1033	/** @} */
1034
1035	/**
1036	* Set the PDE type of the page
1037	* @param a_pVM The VM handle, only used for lock ownership assertions.
1038	* @param a_pPage Pointer to the physical guest page tracking structure.
1039	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1040	*/
1041	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1042	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1043
1044	/**
1045	* Checks if the page was marked being part of a large page
1046	* @returns true/false.
1047	* @param a_pPage Pointer to the physical guest page tracking structure.
1048	*/
1049	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1050
1051	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1052	*
1053	* @remarks The values are assigned in order of priority, so we can calculate
1054	* the correct state for a page with different handlers installed.
1055	* @{ */
1056	/** No handler installed. */
1057	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1058	/** Monitoring is temporarily disabled. */
1059	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1060	/** Write access is monitored. */
1061	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1062	/** All access is monitored. */
1063	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1064	/** @} */
1065
1066	/**
1067	* Gets the physical access handler state of a page.
1068	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1069	* @param a_pPage Pointer to the physical guest page tracking structure.
1070	*/
1071	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1072
1073	/**
1074	* Sets the physical access handler state of a page.
1075	* @param a_pPage Pointer to the physical guest page tracking structure.
1076	* @param a_uState The new state value.
1077	*/
1078	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1079	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1080
1081	/**
1082	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1083	* @returns true/false
1084	* @param a_pPage Pointer to the physical guest page tracking structure.
1085	*/
1086	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1087	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1088
1089	/**
1090	* Checks if the page has any active physical access handlers.
1091	* @returns true/false
1092	* @param a_pPage Pointer to the physical guest page tracking structure.
1093	*/
1094	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1095	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1096
1097	/**
1098	* Checks if the page has any access handlers, including temporarily disabled ones.
1099	* @returns true/false
1100	* @param a_pPage Pointer to the physical guest page tracking structure.
1101	*/
1102	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1103	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1104
1105	/**
1106	* Checks if the page has any active access handlers.
1107	* @returns true/false
1108	* @param a_pPage Pointer to the physical guest page tracking structure.
1109	*/
1110	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1111	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1112
1113	/**
1114	* Checks if the page has any active access handlers catching all accesses.
1115	* @returns true/false
1116	* @param a_pPage Pointer to the physical guest page tracking structure.
1117	*/
1118	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1119	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1120
1121
1122	/** @def PGM_PAGE_GET_TRACKING
1123	* Gets the packed shadow page pool tracking data associated with a guest page.
1124	* @returns uint16_t containing the data.
1125	* @param a_pPage Pointer to the physical guest page tracking structure.
1126	*/
1127	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1128	#if defined(__GNUC__) && defined(VBOX_STRICT)
1129	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1130	#else
1131	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1132	#endif
1133
1134	/** @def PGM_PAGE_SET_TRACKING
1135	* Sets the packed shadow page pool tracking data associated with a guest page.
1136	* @param a_pVM The VM handle, only used for lock ownership assertions.
1137	* @param a_pPage Pointer to the physical guest page tracking structure.
1138	* @param a_u16TrackingData The tracking data to store.
1139	*/
1140	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1141	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1142
1143	/** @def PGM_PAGE_GET_TD_CREFS
1144	* Gets the @a cRefs tracking data member.
1145	* @returns cRefs.
1146	* @param a_pPage Pointer to the physical guest page tracking structure.
1147	*/
1148	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1149	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1150	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1151	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1152
1153	/** @def PGM_PAGE_GET_TD_IDX
1154	* Gets the @a idx tracking data member.
1155	* @returns idx.
1156	* @param a_pPage Pointer to the physical guest page tracking structure.
1157	*/
1158	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1159	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1160	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1161	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1162
1163
1164	/** Max number of locks on a page. */
1165	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1166
1167	/** Get the read lock count.
1168	* @returns count.
1169	* @param a_pPage Pointer to the physical guest page tracking structure.
1170	*/
1171	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1172
1173	/** Get the write lock count.
1174	* @returns count.
1175	* @param a_pPage Pointer to the physical guest page tracking structure.
1176	*/
1177	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1178
1179	/** Decrement the read lock counter.
1180	* @param a_pPage Pointer to the physical guest page tracking structure.
1181	*/
1182	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1183
1184	/** Decrement the write lock counter.
1185	* @param a_pPage Pointer to the physical guest page tracking structure.
1186	*/
1187	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1188
1189	/** Increment the read lock counter.
1190	* @param a_pPage Pointer to the physical guest page tracking structure.
1191	*/
1192	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1193
1194	/** Increment the write lock counter.
1195	* @param a_pPage Pointer to the physical guest page tracking structure.
1196	*/
1197	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1198
1199
1200	/** Gets the NEM state.
1201	* @returns NEM state value (two bits).
1202	* @param a_pPage Pointer to the physical guest page tracking structure.
1203	*/
1204	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1205
1206	/** Sets the NEM state.
1207	* @param a_pPage Pointer to the physical guest page tracking structure.
1208	* @param a_u2State The NEM state value (specific to NEM impl.).
1209	*/
1210	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1211	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1212
1213
1214	#if 0
1215	/** Enables sanity checking of write monitoring using CRC-32. */
1216	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1217	#endif
1218
1219	/**
1220	* Per page live save tracking data.
1221	*/
1222	typedef struct PGMLIVESAVERAMPAGE
1223	{
1224	/** Number of times it has been dirtied. */
1225	uint32_t cDirtied : 24;
1226	/** Whether it is currently dirty. */
1227	uint32_t fDirty : 1;
1228	/** Ignore the page.
1229	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1230	* deal with these after pausing the VM and DevPCI have said it bit about
1231	* remappings. */
1232	uint32_t fIgnore : 1;
1233	/** Was a ZERO page last time around. */
1234	uint32_t fZero : 1;
1235	/** Was a SHARED page last time around. */
1236	uint32_t fShared : 1;
1237	/** Whether the page is/was write monitored in a previous pass. */
1238	uint32_t fWriteMonitored : 1;
1239	/** Whether the page is/was write monitored earlier in this pass. */
1240	uint32_t fWriteMonitoredJustNow : 1;
1241	/** Bits reserved for future use. */
1242	uint32_t u2Reserved : 2;
1243	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1244	/** CRC-32 for the page. This is for internal consistency checks. */
1245	uint32_t u32Crc;
1246	#endif
1247	} PGMLIVESAVERAMPAGE;
1248	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1249	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1250	#else
1251	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1252	#endif
1253	/** Pointer to the per page live save tracking data. */
1254	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1255
1256	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1257	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1258
1259
1260	/**
1261	* RAM range for GC Phys to HC Phys conversion.
1262	*
1263	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1264	* conversions too, but we'll let MM handle that for now.
1265	*
1266	* This structure is used by linked lists in both GC and HC.
1267	*/
1268	typedef struct PGMRAMRANGE
1269	{
1270	/** Start of the range. Page aligned. */
1271	RTGCPHYS GCPhys;
1272	/** Size of the range. (Page aligned of course). */
1273	RTGCPHYS cb;
1274	/** Pointer to the next RAM range - for R3. */
1275	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1276	/** Pointer to the next RAM range - for R0. */
1277	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1278	/** PGM_RAM_RANGE_FLAGS_* flags. */
1279	uint32_t fFlags;
1280	uint32_t fPadding1;
1281	/** Last address in the range (inclusive). Page aligned (-1). */
1282	RTGCPHYS GCPhysLast;
1283	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1284	R3PTRTYPE(void *) pvR3;
1285	/** Live save per page tracking data. */
1286	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1287	/** The range description. */
1288	R3PTRTYPE(const char *) pszDesc;
1289	/** Pointer to self - R0 pointer. */
1290	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1291
1292	/** Pointer to the left search three node - ring-3 context. */
1293	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1294	/** Pointer to the right search three node - ring-3 context. */
1295	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1296	/** Pointer to the left search three node - ring-0 context. */
1297	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1298	/** Pointer to the right search three node - ring-0 context. */
1299	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1300
1301	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1302	#if HC_ARCH_BITS == 32
1303	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1304	#endif
1305	/** Array of physical guest page tracking structures. */
1306	PGMPAGE aPages[1];
1307	} PGMRAMRANGE;
1308	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1309	typedef PGMRAMRANGE *PPGMRAMRANGE;
1310
1311	/** @name PGMRAMRANGE::fFlags
1312	* @{ */
1313	/** The RAM range is floating around as an independent guest mapping. */
1314	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1315	/** Ad hoc RAM range for an ROM mapping. */
1316	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1317	/** Ad hoc RAM range for an MMIO mapping. */
1318	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1319	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1320	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1321	/** @} */
1322
1323	/** Tests if a RAM range is an ad hoc one or not.
1324	* @returns true/false.
1325	* @param pRam The RAM range.
1326	*/
1327	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1328	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1329
1330	/** The number of entries in the RAM range TLBs (there is one for each
1331	* context). Must be a power of two. */
1332	#define PGM_RAMRANGE_TLB_ENTRIES 8
1333
1334	/**
1335	* Calculates the RAM range TLB index for the physical address.
1336	*
1337	* @returns RAM range TLB index.
1338	* @param a_GCPhys The guest physical address.
1339	*/
1340	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1341
1342
1343
1344	/**
1345	* Per page tracking structure for ROM image.
1346	*
1347	* A ROM image may have a shadow page, in which case we may have two pages
1348	* backing it. This structure contains the PGMPAGE for both while
1349	* PGMRAMRANGE have a copy of the active one. It is important that these
1350	* aren't out of sync in any regard other than page pool tracking data.
1351	*/
1352	typedef struct PGMROMPAGE
1353	{
1354	/** The page structure for the virgin ROM page. */
1355	PGMPAGE Virgin;
1356	/** The page structure for the shadow RAM page. */
1357	PGMPAGE Shadow;
1358	/** The current protection setting. */
1359	PGMROMPROT enmProt;
1360	/** Live save status information. Makes use of unused alignment space. */
1361	struct
1362	{
1363	/** The previous protection value. */
1364	uint8_t u8Prot;
1365	/** Written to flag set by the handler. */
1366	bool fWrittenTo;
1367	/** Whether the shadow page is dirty or not. */
1368	bool fDirty;
1369	/** Whether it was dirtied in the recently. */
1370	bool fDirtiedRecently;
1371	} LiveSave;
1372	} PGMROMPAGE;
1373	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1374	/** Pointer to a ROM page tracking structure. */
1375	typedef PGMROMPAGE *PPGMROMPAGE;
1376
1377
1378	/**
1379	* A registered ROM image.
1380	*
1381	* This is needed to keep track of ROM image since they generally intrude
1382	* into a PGMRAMRANGE. It also keeps track of additional info like the
1383	* two page sets (read-only virgin and read-write shadow), the current
1384	* state of each page.
1385	*
1386	* Because access handlers cannot easily be executed in a different
1387	* context, the ROM ranges needs to be accessible and in all contexts.
1388	*/
1389	typedef struct PGMROMRANGE
1390	{
1391	/** Pointer to the next range - R3. */
1392	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1393	/** Pointer to the next range - R0. */
1394	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1395	/** Address of the range. */
1396	RTGCPHYS GCPhys;
1397	/** Address of the last byte in the range. */
1398	RTGCPHYS GCPhysLast;
1399	/** Size of the range. */
1400	RTGCPHYS cb;
1401	/** The flags (PGMPHYS_ROM_FLAGS_). /
1402	uint32_t fFlags;
1403	/** The saved state range ID. */
1404	uint8_t idSavedState;
1405	/** Alignment padding. */
1406	uint8_t au8Alignment[3];
1407	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1408	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1409	/** The size bits pvOriginal points to. */
1410	uint32_t cbOriginal;
1411	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1412	* This is used for strictness checks. */
1413	R3PTRTYPE(const void *) pvOriginal;
1414	/** The ROM description. */
1415	R3PTRTYPE(const char *) pszDesc;
1416	/** The per page tracking structures. */
1417	PGMROMPAGE aPages[1];
1418	} PGMROMRANGE;
1419	/** Pointer to a ROM range. */
1420	typedef PGMROMRANGE *PPGMROMRANGE;
1421
1422
1423	/**
1424	* Live save per page data for an MMIO2 page.
1425	*
1426	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1427	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1428	* CRC-32 for detecting changes as well as special handling of zero pages. This
1429	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1430	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1431	* because of speed (2.5x and 6x slower).)
1432	*
1433	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1434	* save but normally is disabled. Since we can write monitor guest
1435	* accesses on our own, we only need this for host accesses. Shouldn't be
1436	* too difficult for DevVGA, VMMDev might be doable, the planned
1437	* networking fun will be fun since it involves ring-0.
1438	*/
1439	typedef struct PGMLIVESAVEMMIO2PAGE
1440	{
1441	/** Set if the page is considered dirty. */
1442	bool fDirty;
1443	/** The number of scans this page has remained unchanged for.
1444	* Only updated for dirty pages. */
1445	uint8_t cUnchangedScans;
1446	/** Whether this page was zero at the last scan. */
1447	bool fZero;
1448	/** Alignment padding. */
1449	bool fReserved;
1450	/** CRC-32 for the first half of the page.
1451	* This is used together with u32CrcH2 to quickly detect changes in the page
1452	* during the non-final passes. */
1453	uint32_t u32CrcH1;
1454	/** CRC-32 for the second half of the page. */
1455	uint32_t u32CrcH2;
1456	/** SHA-1 for the saved page.
1457	* This is used in the final pass to skip pages without changes. */
1458	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1459	} PGMLIVESAVEMMIO2PAGE;
1460	/** Pointer to a live save status data for an MMIO2 page. */
1461	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1462
1463	/**
1464	* A registered MMIO2 (= Device RAM) range.
1465	*
1466	* There are a few reason why we need to keep track of these registrations. One
1467	* of them is the deregistration & cleanup stuff, while another is that the
1468	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1469	* range list.
1470	*
1471	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1472	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1473	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1474	* overlap we will free all the existing RAM pages and put in the ram range
1475	* pages instead.
1476	*/
1477	typedef struct PGMREGMMIO2RANGE
1478	{
1479	/** The owner of the range. (a device) */
1480	PPDMDEVINSR3 pDevInsR3;
1481	/** Pointer to the ring-3 mapping of the allocation. */
1482	RTR3PTR pvR3;
1483	#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1484	/** Pointer to the ring-0 mapping of the allocation. */
1485	RTR0PTR pvR0;
1486	#endif
1487	/** Pointer to the next range - R3. */
1488	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1489	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1490	uint16_t fFlags;
1491	/** The sub device number (internal PCI config (CFGM) number). */
1492	uint8_t iSubDev;
1493	/** The PCI region number. */
1494	uint8_t iRegion;
1495	/** The saved state range ID. */
1496	uint8_t idSavedState;
1497	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1498	uint8_t idMmio2;
1499	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1500	#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1501	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1502	#else
1503	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1504	#endif
1505	/** The real size.
1506	* This may be larger than indicated by RamRange.cb if the range has been
1507	* reduced during saved state loading. */
1508	RTGCPHYS cbReal;
1509	/** Pointer to the physical handler for MMIO. */
1510	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1511	/** Live save per page tracking data for MMIO2. */
1512	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1513	/** The associated RAM range. */
1514	PGMRAMRANGE RamRange;
1515	} PGMREGMMIO2RANGE;
1516	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1517	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1518	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1519
1520	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1521	* @{ */
1522	/** Set if it's an MMIO2 range.
1523	* @note Historical. For a while we did some of the MMIO this way too. */
1524	#define PGMREGMMIO2RANGE_F_MMIO2 UINT16_C(0x0001)
1525	/** Set if this is the first chunk in the MMIO2 range. */
1526	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1527	/** Set if this is the last chunk in the MMIO2 range. */
1528	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0004)
1529	/** Set if the whole range is mapped. */
1530	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0008)
1531	/** Set if it's overlapping, clear if not. */
1532	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0010)
1533	/** @} */
1534
1535
1536	/** @name Internal MMIO2 constants.
1537	* @{ */
1538	/** The maximum number of MMIO2 ranges. */
1539	#define PGM_MMIO2_MAX_RANGES 32
1540	/** The maximum number of pages in a MMIO2 range. */
1541	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1542	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1543	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1544	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1545	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1546	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1547	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1548	/** @} */
1549
1550
1551
1552	/**
1553	* PGMPhysRead/Write cache entry
1554	*/
1555	typedef struct PGMPHYSCACHEENTRY
1556	{
1557	/** R3 pointer to physical page. */
1558	R3PTRTYPE(uint8_t *) pbR3;
1559	/** GC Physical address for cache entry */
1560	RTGCPHYS GCPhys;
1561	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1562	RTGCPHYS u32Padding0; /*< alignment padding. /
1563	#endif
1564	} PGMPHYSCACHEENTRY;
1565
1566	/**
1567	* PGMPhysRead/Write cache to reduce REM memory access overhead
1568	*/
1569	typedef struct PGMPHYSCACHE
1570	{
1571	/** Bitmap of valid cache entries */
1572	uint64_t aEntries;
1573	/** Cache entries */
1574	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1575	} PGMPHYSCACHE;
1576
1577
1578	/** @name Ring-3 page mapping TLBs
1579	* @{ */
1580
1581	/** Pointer to an allocation chunk ring-3 mapping. */
1582	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1583	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1584	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1585
1586	/**
1587	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1588	*
1589	* The primary tree (Core) uses the chunk id as key.
1590	*/
1591	typedef struct PGMCHUNKR3MAP
1592	{
1593	/** The key is the chunk id. */
1594	AVLU32NODECORE Core;
1595	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1596	* selection. */
1597	uint32_t iLastUsed;
1598	/** The current reference count. */
1599	uint32_t volatile cRefs;
1600	/** The current permanent reference count. */
1601	uint32_t volatile cPermRefs;
1602	/** The mapping address. */
1603	void *pv;
1604	} PGMCHUNKR3MAP;
1605
1606	/**
1607	* Allocation chunk ring-3 mapping TLB entry.
1608	*/
1609	typedef struct PGMCHUNKR3MAPTLBE
1610	{
1611	/** The chunk id. */
1612	uint32_t volatile idChunk;
1613	#if HC_ARCH_BITS == 64
1614	uint32_t u32Padding; /*< alignment padding. /
1615	#endif
1616	/** The chunk map. */
1617	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1618	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1619	#else
1620	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1621	#endif
1622	} PGMCHUNKR3MAPTLBE;
1623	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1624	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1625
1626	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1627	* @remark Must be a power of two value. */
1628	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1629
1630	/**
1631	* Allocation chunk ring-3 mapping TLB.
1632	*
1633	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1634	* At first glance this might look kinda odd since AVL trees are
1635	* supposed to give the most optimal lookup times of all trees
1636	* due to their balancing. However, take a tree with 1023 nodes
1637	* in it, that's 10 levels, meaning that most searches has to go
1638	* down 9 levels before they find what they want. This isn't fast
1639	* compared to a TLB hit. There is the factor of cache misses,
1640	* and of course the problem with trees and branch prediction.
1641	* This is why we use TLBs in front of most of the trees.
1642	*
1643	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1644	* difficult when we switch to the new inlined AVL trees (from kStuff).
1645	*/
1646	typedef struct PGMCHUNKR3MAPTLB
1647	{
1648	/** The TLB entries. */
1649	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1650	} PGMCHUNKR3MAPTLB;
1651
1652	/**
1653	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1654	* @returns Chunk TLB index.
1655	* @param idChunk The Chunk ID.
1656	*/
1657	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1658
1659
1660	/**
1661	* Ring-3 guest page mapping TLB entry.
1662	* @remarks used in ring-0 as well at the moment.
1663	*/
1664	typedef struct PGMPAGER3MAPTLBE
1665	{
1666	/** Address of the page. */
1667	RTGCPHYS volatile GCPhys;
1668	/** The guest page. */
1669	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1670	R3PTRTYPE(PPGMPAGE) volatile pPage;
1671	#else
1672	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1673	#endif
1674	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1675	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1676	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1677	#else
1678	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1679	#endif
1680	/** The address */
1681	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1682	R3PTRTYPE(void *) volatile pv;
1683	#else
1684	R3R0PTRTYPE(void *) volatile pv;
1685	#endif
1686	#if HC_ARCH_BITS == 32
1687	uint32_t u32Padding; /*< alignment padding. /
1688	#endif
1689	} PGMPAGER3MAPTLBE;
1690	/** Pointer to an entry in the HC physical TLB. */
1691	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1692
1693
1694	/** The number of entries in the ring-3 guest page mapping TLB.
1695	* @remarks The value must be a power of two. */
1696	#define PGM_PAGER3MAPTLB_ENTRIES 256
1697
1698	/**
1699	* Ring-3 guest page mapping TLB.
1700	* @remarks used in ring-0 as well at the moment.
1701	*/
1702	typedef struct PGMPAGER3MAPTLB
1703	{
1704	/** The TLB entries. */
1705	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1706	} PGMPAGER3MAPTLB;
1707	/** Pointer to the ring-3 guest page mapping TLB. */
1708	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1709
1710	/**
1711	* Calculates the index of the TLB entry for the specified guest page.
1712	* @returns Physical TLB index.
1713	* @param GCPhys The guest physical address.
1714	*/
1715	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1716
1717	/** @} */
1718
1719	#if defined(VBOX_WITH_RAM_IN_KERNEL) \|\| defined(DOXYGEN_RUNNING)
1720	/** @name Ring-0 page mapping TLB
1721	* @{ */
1722	/**
1723	* Ring-0 guest page mapping TLB entry.
1724	*/
1725	typedef struct PGMPAGER0MAPTLBE
1726	{
1727	/** Address of the page. */
1728	RTGCPHYS volatile GCPhys;
1729	/** The guest page. */
1730	R0PTRTYPE(PPGMPAGE) volatile pPage;
1731	/** The address */
1732	R0PTRTYPE(void *) volatile pv;
1733	} PGMPAGER0MAPTLBE;
1734	/** Pointer to an entry in the HC physical TLB. */
1735	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1736
1737
1738	/** The number of entries in the ring-3 guest page mapping TLB.
1739	* @remarks The value must be a power of two. */
1740	#define PGM_PAGER0MAPTLB_ENTRIES 256
1741
1742	/**
1743	* Ring-3 guest page mapping TLB.
1744	* @remarks used in ring-0 as well at the moment.
1745	*/
1746	typedef struct PGMPAGER0MAPTLB
1747	{
1748	/** The TLB entries. */
1749	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1750	} PGMPAGER0MAPTLB;
1751	/** Pointer to the ring-3 guest page mapping TLB. */
1752	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1753
1754	/**
1755	* Calculates the index of the TLB entry for the specified guest page.
1756	* @returns Physical TLB index.
1757	* @param GCPhys The guest physical address.
1758	*/
1759	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1760	/** @} */
1761	#endif /* VBOX_WITH_RAM_IN_KERNEL \|\| DOXYGEN_RUNNING */
1762
1763	/**
1764	* Raw-mode context dynamic mapping cache entry.
1765	*
1766	* Because of raw-mode context being reloctable and all relocations are applied
1767	* in ring-3, this has to be defined here and be RC specific.
1768	*
1769	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1770	*/
1771	typedef struct PGMRCDYNMAPENTRY
1772	{
1773	/** The physical address of the currently mapped page.
1774	* This is duplicate for three reasons: cache locality, cache policy of the PT
1775	* mappings and sanity checks. */
1776	RTHCPHYS HCPhys;
1777	/** Pointer to the page. */
1778	RTRCPTR pvPage;
1779	/** The number of references. */
1780	int32_t volatile cRefs;
1781	/** PTE pointer union. */
1782	struct PGMRCDYNMAPENTRY_PPTE
1783	{
1784	/** PTE pointer, 32-bit legacy version. */
1785	RCPTRTYPE(PX86PTE) pLegacy;
1786	/** PTE pointer, PAE version. */
1787	RCPTRTYPE(PX86PTEPAE) pPae;
1788	} uPte;
1789	} PGMRCDYNMAPENTRY;
1790	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1791	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1792
1793
1794	/**
1795	* Dynamic mapping cache for the raw-mode context.
1796	*
1797	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1798	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1799	* so that we can perform relocations from PGMR3Relocate. This has the
1800	* consequence that we must have separate ring-0 and raw-mode context versions
1801	* of this struct even if they share the basic elements.
1802	*
1803	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1804	*/
1805	typedef struct PGMRCDYNMAP
1806	{
1807	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1808	uint32_t u32Magic;
1809	/** Array for tracking and managing the pages. */
1810	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1811	/** The cache size given as a number of pages. */
1812	uint32_t cPages;
1813	/** The current load.
1814	* This does not include guard pages. */
1815	uint32_t cLoad;
1816	/** The max load ever.
1817	* This is maintained to get trigger adding of more mapping space. */
1818	uint32_t cMaxLoad;
1819	/** The number of guard pages. */
1820	uint32_t cGuardPages;
1821	/** The number of users (protected by hInitLock). */
1822	uint32_t cUsers;
1823	} PGMRCDYNMAP;
1824	/** Pointer to the dynamic cache for the raw-mode context. */
1825	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1826
1827
1828	/**
1829	* Mapping cache usage set entry.
1830	*
1831	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1832	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1833	* cache. If it's extended to include ring-3, well, then something
1834	* will have be changed here...
1835	*/
1836	typedef struct PGMMAPSETENTRY
1837	{
1838	/** Pointer to the page. */
1839	RTR0PTR pvPage;
1840	/** The mapping cache index. */
1841	uint16_t iPage;
1842	/** The number of references.
1843	* The max is UINT16_MAX - 1. */
1844	uint16_t cRefs;
1845	/** The number inlined references.
1846	* The max is UINT16_MAX - 1. */
1847	uint16_t cInlinedRefs;
1848	/** Unreferences. */
1849	uint16_t cUnrefs;
1850
1851	#if HC_ARCH_BITS == 32
1852	uint32_t u32Alignment1;
1853	#endif
1854	/** The physical address for this entry. */
1855	RTHCPHYS HCPhys;
1856	} PGMMAPSETENTRY;
1857	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1858	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1859	/** Pointer to a mapping cache usage set entry. */
1860	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1861
1862	/**
1863	* Mapping cache usage set.
1864	*
1865	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1866	* done during exits / traps. The set is
1867	*/
1868	typedef struct PGMMAPSET
1869	{
1870	/** The number of occupied entries.
1871	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1872	* dynamic mappings. */
1873	uint32_t cEntries;
1874	/** The start of the current subset.
1875	* This is UINT32_MAX if no subset is currently open. */
1876	uint32_t iSubset;
1877	/** The index of the current CPU, only valid if the set is open. */
1878	int32_t iCpu;
1879	uint32_t alignment;
1880	/** The entries. */
1881	PGMMAPSETENTRY aEntries[64];
1882	/** HCPhys -> iEntry fast lookup table.
1883	* Use PGMMAPSET_HASH for hashing.
1884	* The entries may or may not be valid, check against cEntries. */
1885	uint8_t aiHashTable[128];
1886	} PGMMAPSET;
1887	AssertCompileSizeAlignment(PGMMAPSET, 8);
1888	/** Pointer to the mapping cache set. */
1889	typedef PGMMAPSET *PPGMMAPSET;
1890
1891	/** PGMMAPSET::cEntries value for a closed set. */
1892	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1893
1894	/** Hash function for aiHashTable. */
1895	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1896
1897
1898	/** @name Context neutral page mapper TLB.
1899	*
1900	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1901	* code is writting in a kind of context neutral way. Time will show whether
1902	* this actually makes sense or not...
1903	*
1904	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1905	* context ends up using a global mapping cache on some platforms
1906	* (darwin).
1907	*
1908	* @{ */
1909	/** @typedef PPGMPAGEMAPTLB
1910	* The page mapper TLB pointer type for the current context. */
1911	/** @typedef PPGMPAGEMAPTLB
1912	* The page mapper TLB entry pointer type for the current context. */
1913	/** @typedef PPGMPAGEMAPTLB
1914	* The page mapper TLB entry pointer pointer type for the current context. */
1915	/** @def PGM_PAGEMAPTLB_ENTRIES
1916	* The number of TLB entries in the page mapper TLB for the current context. */
1917	/** @def PGM_PAGEMAPTLB_IDX
1918	* Calculate the TLB index for a guest physical address.
1919	* @returns The TLB index.
1920	* @param GCPhys The guest physical address. */
1921	/** @typedef PPGMPAGEMAP
1922	* Pointer to a page mapper unit for current context. */
1923	/** @typedef PPPGMPAGEMAP
1924	* Pointer to a page mapper unit pointer for current context. */
1925	#if defined(IN_RING0) && defined(VBOX_WITH_RAM_IN_KERNEL)
1926	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1927	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1928	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1929	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1930	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1931	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1932	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1933	#else
1934	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1935	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1936	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1937	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1938	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1939	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1940	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1941	#endif
1942	/** @} */
1943
1944
1945	/** @name PGM Pool Indexes.
1946	* Aka. the unique shadow page identifier.
1947	* @{ */
1948	/** NIL page pool IDX. */
1949	#define NIL_PGMPOOL_IDX 0
1950	/** The first normal index. There used to be 5 fictive pages up front, now
1951	* there is only the NIL page. */
1952	#define PGMPOOL_IDX_FIRST 1
1953	/** The last valid index. (inclusive, 14 bits) */
1954	#define PGMPOOL_IDX_LAST 0x3fff
1955	/** @} */
1956
1957	/** The NIL index for the parent chain. */
1958	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1959	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1960
1961	/**
1962	* Node in the chain linking a shadowed page to it's parent (user).
1963	*/
1964	#pragma pack(1)
1965	typedef struct PGMPOOLUSER
1966	{
1967	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1968	uint16_t iNext;
1969	/** The user page index. */
1970	uint16_t iUser;
1971	/** Index into the user table. */
1972	uint32_t iUserTable;
1973	} PGMPOOLUSER, *PPGMPOOLUSER;
1974	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1975	#pragma pack()
1976
1977
1978	/** The NIL index for the phys ext chain. */
1979	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1980	/** The NIL pte index for a phys ext chain slot. */
1981	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1982
1983	/**
1984	* Node in the chain of physical cross reference extents.
1985	* @todo Calling this an 'extent' is not quite right, find a better name.
1986	* @todo find out the optimal size of the aidx array
1987	*/
1988	#pragma pack(1)
1989	typedef struct PGMPOOLPHYSEXT
1990	{
1991	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1992	uint16_t iNext;
1993	/** Alignment. */
1994	uint16_t u16Align;
1995	/** The user page index. */
1996	uint16_t aidx[3];
1997	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1998	uint16_t apte[3];
1999	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2000	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2001	#pragma pack()
2002
2003
2004	/**
2005	* The kind of page that's being shadowed.
2006	*/
2007	typedef enum PGMPOOLKIND
2008	{
2009	/** The virtual invalid 0 entry. */
2010	PGMPOOLKIND_INVALID = 0,
2011	/** The entry is free (=unused). */
2012	PGMPOOLKIND_FREE,
2013
2014	/** Shw: 32-bit page table; Gst: no paging. */
2015	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2016	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2017	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2018	/** Shw: 32-bit page table; Gst: 4MB page. */
2019	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2020	/** Shw: PAE page table; Gst: no paging. */
2021	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2022	/** Shw: PAE page table; Gst: 32-bit page table. */
2023	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2024	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2025	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2026	/** Shw: PAE page table; Gst: PAE page table. */
2027	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2028	/** Shw: PAE page table; Gst: 2MB page. */
2029	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2030
2031	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2032	PGMPOOLKIND_32BIT_PD,
2033	/** Shw: 32-bit page directory. Gst: no paging. */
2034	PGMPOOLKIND_32BIT_PD_PHYS,
2035	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2036	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2037	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2038	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2039	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2040	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2041	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2042	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2043	/** Shw: PAE page directory; Gst: PAE page directory. */
2044	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2045	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2046	PGMPOOLKIND_PAE_PD_PHYS,
2047
2048	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2049	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2050	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2051	PGMPOOLKIND_PAE_PDPT,
2052	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2053	PGMPOOLKIND_PAE_PDPT_PHYS,
2054
2055	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2056	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2057	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2058	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2059	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2060	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2061	/** Shw: 64-bit page directory table; Gst: no paging. */
2062	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2063
2064	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2065	PGMPOOLKIND_64BIT_PML4,
2066
2067	/** Shw: EPT page directory pointer table; Gst: no paging. */
2068	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2069	/** Shw: EPT page directory table; Gst: no paging. */
2070	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2071	/** Shw: EPT page table; Gst: no paging. */
2072	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2073
2074	/** Shw: Root Nested paging table. */
2075	PGMPOOLKIND_ROOT_NESTED,
2076
2077	/** The last valid entry. */
2078	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2079	} PGMPOOLKIND;
2080
2081	/**
2082	* The access attributes of the page; only applies to big pages.
2083	*/
2084	typedef enum
2085	{
2086	PGMPOOLACCESS_DONTCARE = 0,
2087	PGMPOOLACCESS_USER_RW,
2088	PGMPOOLACCESS_USER_R,
2089	PGMPOOLACCESS_USER_RW_NX,
2090	PGMPOOLACCESS_USER_R_NX,
2091	PGMPOOLACCESS_SUPERVISOR_RW,
2092	PGMPOOLACCESS_SUPERVISOR_R,
2093	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2094	PGMPOOLACCESS_SUPERVISOR_R_NX
2095	} PGMPOOLACCESS;
2096
2097	/**
2098	* The tracking data for a page in the pool.
2099	*/
2100	typedef struct PGMPOOLPAGE
2101	{
2102	/** AVL node code with the (HC) physical address of this page. */
2103	AVLOHCPHYSNODECORE Core;
2104	/** Pointer to the R3 mapping of the page. */
2105	R3PTRTYPE(void *) pvPageR3;
2106	/** Pointer to the R0 mapping of the page. */
2107	R0PTRTYPE(void *) pvPageR0;
2108	/** The guest physical address. */
2109	RTGCPHYS GCPhys;
2110	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2111	uint8_t enmKind;
2112	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2113	uint8_t enmAccess;
2114	/** This supplements enmKind and enmAccess */
2115	bool fA20Enabled : 1;
2116
2117	/** Used to indicate that the page is zeroed. */
2118	bool fZeroed : 1;
2119	/** Used to indicate that a PT has non-global entries. */
2120	bool fSeenNonGlobal : 1;
2121	/** Used to indicate that we're monitoring writes to the guest page. */
2122	bool fMonitored : 1;
2123	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2124	* (All pages are in the age list.) */
2125	bool fCached : 1;
2126	/** This is used by the R3 access handlers when invoked by an async thread.
2127	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2128	bool volatile fReusedFlushPending : 1;
2129	/** Used to mark the page as dirty (write monitoring is temporarily
2130	* off). */
2131	bool fDirty : 1;
2132	bool fPadding1 : 1;
2133	bool fPadding2;
2134
2135	/** The index of this page. */
2136	uint16_t idx;
2137	/** The next entry in the list this page currently resides in.
2138	* It's either in the free list or in the GCPhys hash. */
2139	uint16_t iNext;
2140	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2141	uint16_t iUserHead;
2142	/** The number of present entries. */
2143	uint16_t cPresent;
2144	/** The first entry in the table which is present. */
2145	uint16_t iFirstPresent;
2146	/** The number of modifications to the monitored page. */
2147	uint16_t cModifications;
2148	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2149	uint16_t iModifiedNext;
2150	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2151	uint16_t iModifiedPrev;
2152	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2153	uint16_t iMonitoredNext;
2154	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2155	uint16_t iMonitoredPrev;
2156	/** The next page in the age list. */
2157	uint16_t iAgeNext;
2158	/** The previous page in the age list. */
2159	uint16_t iAgePrev;
2160	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2161	uint8_t idxDirtyEntry;
2162
2163	/** @name Access handler statistics to determine whether the guest is
2164	* (re)initializing a page table.
2165	* @{ */
2166	RTGCPTR GCPtrLastAccessHandlerRip;
2167	RTGCPTR GCPtrLastAccessHandlerFault;
2168	uint64_t cLastAccessHandler;
2169	/** @} */
2170	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2171	uint32_t volatile cLocked;
2172	#if GC_ARCH_BITS == 64
2173	uint32_t u32Alignment3;
2174	#endif
2175	# ifdef VBOX_STRICT
2176	RTGCPTR GCPtrDirtyFault;
2177	# endif
2178	} PGMPOOLPAGE;
2179	/** Pointer to a pool page. */
2180	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2181	/** Pointer to a const pool page. */
2182	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2183	/** Pointer to a pool page pointer. */
2184	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2185
2186
2187	/** The hash table size. */
2188	# define PGMPOOL_HASH_SIZE 0x40
2189	/** The hash function. */
2190	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2191
2192
2193	/**
2194	* The shadow page pool instance data.
2195	*
2196	* It's all one big allocation made at init time, except for the
2197	* pages that is. The user nodes follows immediately after the
2198	* page structures.
2199	*/
2200	typedef struct PGMPOOL
2201	{
2202	/** The VM handle - R3 Ptr. */
2203	PVMR3 pVMR3;
2204	/** The VM handle - R0 Ptr. */
2205	R0PTRTYPE(PVMCC) pVMR0;
2206	/** The max pool size. This includes the special IDs. */
2207	uint16_t cMaxPages;
2208	/** The current pool size. */
2209	uint16_t cCurPages;
2210	/** The head of the free page list. */
2211	uint16_t iFreeHead;
2212	/* Padding. */
2213	uint16_t u16Padding;
2214	/** Head of the chain of free user nodes. */
2215	uint16_t iUserFreeHead;
2216	/** The number of user nodes we've allocated. */
2217	uint16_t cMaxUsers;
2218	/** The number of present page table entries in the entire pool. */
2219	uint32_t cPresent;
2220	/** Pointer to the array of user nodes - R3 pointer. */
2221	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2222	/** Pointer to the array of user nodes - R0 pointer. */
2223	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2224	/** Head of the chain of free phys ext nodes. */
2225	uint16_t iPhysExtFreeHead;
2226	/** The number of user nodes we've allocated. */
2227	uint16_t cMaxPhysExts;
2228	uint32_t u32Padding0b;
2229	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2230	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2231	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2232	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2233	/** Hash table for GCPhys addresses. */
2234	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2235	/** The head of the age list. */
2236	uint16_t iAgeHead;
2237	/** The tail of the age list. */
2238	uint16_t iAgeTail;
2239	/** Set if the cache is enabled. */
2240	bool fCacheEnabled;
2241	/** Alignment padding. */
2242	bool afPadding1[3];
2243	/** Head of the list of modified pages. */
2244	uint16_t iModifiedHead;
2245	/** The current number of modified pages. */
2246	uint16_t cModifiedPages;
2247	/** Physical access handler type registration handle. */
2248	PGMPHYSHANDLERTYPE hAccessHandlerType;
2249	/** Next available slot (in aDirtyPages). */
2250	uint32_t idxFreeDirtyPage;
2251	/** Number of active dirty pages. */
2252	uint32_t cDirtyPages;
2253	/** Array of current dirty pgm pool page indices. */
2254	uint16_t aidxDirtyPages[16];
2255	/** Array running in parallel to aidxDirtyPages with the page data. */
2256	struct
2257	{
2258	uint64_t aPage[512];
2259	} aDirtyPages[16];
2260
2261	/** The number of pages currently in use. */
2262	uint16_t cUsedPages;
2263	#ifdef VBOX_WITH_STATISTICS
2264	/** The high water mark for cUsedPages. */
2265	uint16_t cUsedPagesHigh;
2266	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2267	/** Profiling pgmPoolAlloc(). */
2268	STAMPROFILEADV StatAlloc;
2269	/** Profiling pgmR3PoolClearDoIt(). */
2270	STAMPROFILE StatClearAll;
2271	/** Profiling pgmR3PoolReset(). */
2272	STAMPROFILE StatR3Reset;
2273	/** Profiling pgmPoolFlushPage(). */
2274	STAMPROFILE StatFlushPage;
2275	/** Profiling pgmPoolFree(). */
2276	STAMPROFILE StatFree;
2277	/** Counting explicit flushes by PGMPoolFlushPage(). */
2278	STAMCOUNTER StatForceFlushPage;
2279	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2280	STAMCOUNTER StatForceFlushDirtyPage;
2281	/** Counting flushes for reused pages. */
2282	STAMCOUNTER StatForceFlushReused;
2283	/** Profiling time spent zeroing pages. */
2284	STAMPROFILE StatZeroPage;
2285	/** Profiling of pgmPoolTrackDeref. */
2286	STAMPROFILE StatTrackDeref;
2287	/** Profiling pgmTrackFlushGCPhysPT. */
2288	STAMPROFILE StatTrackFlushGCPhysPT;
2289	/** Profiling pgmTrackFlushGCPhysPTs. */
2290	STAMPROFILE StatTrackFlushGCPhysPTs;
2291	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2292	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2293	/** Number of times we've been out of user records. */
2294	STAMCOUNTER StatTrackFreeUpOneUser;
2295	/** Nr of flushed entries. */
2296	STAMCOUNTER StatTrackFlushEntry;
2297	/** Nr of updated entries. */
2298	STAMCOUNTER StatTrackFlushEntryKeep;
2299	/** Profiling deref activity related tracking GC physical pages. */
2300	STAMPROFILE StatTrackDerefGCPhys;
2301	/** Number of linear searches for a HCPhys in the ram ranges. */
2302	STAMCOUNTER StatTrackLinearRamSearches;
2303	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2304	STAMCOUNTER StamTrackPhysExtAllocFailures;
2305
2306	/** Profiling the RC/R0 \#PF access handler. */
2307	STAMPROFILE StatMonitorPfRZ;
2308	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2309	STAMPROFILE StatMonitorPfRZHandled;
2310	/** Times we've failed interpreting the instruction. */
2311	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2312	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2313	STAMPROFILE StatMonitorPfRZFlushPage;
2314	/** Times we've detected a page table reinit. */
2315	STAMCOUNTER StatMonitorPfRZFlushReinit;
2316	/** Counting flushes for pages that are modified too often. */
2317	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2318	/** Times we've detected fork(). */
2319	STAMCOUNTER StatMonitorPfRZFork;
2320	/** Times we've failed interpreting a patch code instruction. */
2321	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2322	/** Times we've failed interpreting a patch code instruction during flushing. */
2323	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2324	/** The number of times we've seen rep prefixes we can't handle. */
2325	STAMCOUNTER StatMonitorPfRZRepPrefix;
2326	/** Profiling the REP STOSD cases we've handled. */
2327	STAMPROFILE StatMonitorPfRZRepStosd;
2328
2329	/** Profiling the R0/RC regular access handler. */
2330	STAMPROFILE StatMonitorRZ;
2331	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2332	STAMPROFILE StatMonitorRZFlushPage;
2333	/** Per access size counts indexed by size minus 1, last for larger. */
2334	STAMCOUNTER aStatMonitorRZSizes[16+3];
2335	/** Missaligned access counts indexed by offset - 1. */
2336	STAMCOUNTER aStatMonitorRZMisaligned[7];
2337
2338	/** Nr of handled PT faults. */
2339	STAMCOUNTER StatMonitorRZFaultPT;
2340	/** Nr of handled PD faults. */
2341	STAMCOUNTER StatMonitorRZFaultPD;
2342	/** Nr of handled PDPT faults. */
2343	STAMCOUNTER StatMonitorRZFaultPDPT;
2344	/** Nr of handled PML4 faults. */
2345	STAMCOUNTER StatMonitorRZFaultPML4;
2346
2347	/** Profiling the R3 access handler. */
2348	STAMPROFILE StatMonitorR3;
2349	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2350	STAMPROFILE StatMonitorR3FlushPage;
2351	/** Per access size counts indexed by size minus 1, last for larger. */
2352	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2353	/** Missaligned access counts indexed by offset - 1. */
2354	STAMCOUNTER aStatMonitorR3Misaligned[7];
2355	/** Nr of handled PT faults. */
2356	STAMCOUNTER StatMonitorR3FaultPT;
2357	/** Nr of handled PD faults. */
2358	STAMCOUNTER StatMonitorR3FaultPD;
2359	/** Nr of handled PDPT faults. */
2360	STAMCOUNTER StatMonitorR3FaultPDPT;
2361	/** Nr of handled PML4 faults. */
2362	STAMCOUNTER StatMonitorR3FaultPML4;
2363
2364	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2365	STAMCOUNTER StatResetDirtyPages;
2366	/** Times we've called pgmPoolAddDirtyPage. */
2367	STAMCOUNTER StatDirtyPage;
2368	/** Times we've had to flush duplicates for dirty page management. */
2369	STAMCOUNTER StatDirtyPageDupFlush;
2370	/** Times we've had to flush because of overflow. */
2371	STAMCOUNTER StatDirtyPageOverFlowFlush;
2372
2373	/** The high water mark for cModifiedPages. */
2374	uint16_t cModifiedPagesHigh;
2375	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2376
2377	/** The number of cache hits. */
2378	STAMCOUNTER StatCacheHits;
2379	/** The number of cache misses. */
2380	STAMCOUNTER StatCacheMisses;
2381	/** The number of times we've got a conflict of 'kind' in the cache. */
2382	STAMCOUNTER StatCacheKindMismatches;
2383	/** Number of times we've been out of pages. */
2384	STAMCOUNTER StatCacheFreeUpOne;
2385	/** The number of cacheable allocations. */
2386	STAMCOUNTER StatCacheCacheable;
2387	/** The number of uncacheable allocations. */
2388	STAMCOUNTER StatCacheUncacheable;
2389	#else
2390	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2391	#endif
2392	/** Profiling PGMR0PoolGrow(). */
2393	STAMPROFILE StatGrow;
2394	/** The AVL tree for looking up a page by its HC physical address. */
2395	AVLOHCPHYSTREE HCPhysTree;
2396	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2397	/** Array of pages. (cMaxPages in length)
2398	* The Id is the index into thist array.
2399	*/
2400	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2401	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2402	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2403	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2404	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2405	#ifdef VBOX_WITH_STATISTICS
2406	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2407	#endif
2408	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2409
2410
2411	/** @def PGMPOOL_PAGE_2_PTR
2412	* Maps a pool page pool into the current context.
2413	*
2414	* @returns VBox status code.
2415	* @param a_pVM Pointer to the VM.
2416	* @param a_pPage The pool page.
2417	*
2418	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2419	* small page window employeed by that function. Be careful.
2420	* @remark There is no need to assert on the result.
2421	*/
2422	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2423	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2424	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2425	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2426	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2427	{
2428	RT_NOREF(pszCaller);
2429	AssertPtr(a_pPage);
2430	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2431	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2432	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2433	return a_pPage->CTX_SUFF(pvPage);
2434	}
2435	#else
2436	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2437	#endif
2438
2439
2440	/** @def PGMPOOL_PAGE_2_PTR_V2
2441	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2442	*
2443	* @returns VBox status code.
2444	* @param a_pVM Pointer to the VM.
2445	* @param a_pVCpu The current CPU.
2446	* @param a_pPage The pool page.
2447	*
2448	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2449	* small page window employeed by that function. Be careful.
2450	* @remark There is no need to assert on the result.
2451	*/
2452	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2453	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2454	#else
2455	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2456	#endif
2457
2458
2459	/** @name Per guest page tracking data.
2460	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2461	* is to use more bits for it and split it up later on. But for now we'll play
2462	* safe and change as little as possible.
2463	*
2464	* The 16-bit word has two parts:
2465	*
2466	* The first 14-bit forms the @a idx field. It is either the index of a page in
2467	* the shadow page pool, or and index into the extent list.
2468	*
2469	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2470	* shadow page pool references to the page. If cRefs equals
2471	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2472	* (misnomer) table and not the shadow page pool.
2473	*
2474	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2475	* the 16-bit word.
2476	*
2477	* @{ */
2478	/** The shift count for getting to the cRefs part. */
2479	#define PGMPOOL_TD_CREFS_SHIFT 14
2480	/** The mask applied after shifting the tracking data down by
2481	* PGMPOOL_TD_CREFS_SHIFT. */
2482	#define PGMPOOL_TD_CREFS_MASK 0x3
2483	/** The cRefs value used to indicate that the idx is the head of a
2484	* physical cross reference list. */
2485	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2486	/** The shift used to get idx. */
2487	#define PGMPOOL_TD_IDX_SHIFT 0
2488	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2489	#define PGMPOOL_TD_IDX_MASK 0x3fff
2490	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2491	* simply too many mappings of this page. */
2492	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2493
2494	/** @def PGMPOOL_TD_MAKE
2495	* Makes a 16-bit tracking data word.
2496	*
2497	* @returns tracking data.
2498	* @param cRefs The @a cRefs field. Must be within bounds!
2499	* @param idx The @a idx field. Must also be within bounds! */
2500	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2501
2502	/** @def PGMPOOL_TD_GET_CREFS
2503	* Get the @a cRefs field from a tracking data word.
2504	*
2505	* @returns The @a cRefs field
2506	* @param u16 The tracking data word.
2507	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2508	* non-zero @a u16. */
2509	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2510
2511	/** @def PGMPOOL_TD_GET_IDX
2512	* Get the @a idx field from a tracking data word.
2513	*
2514	* @returns The @a idx field
2515	* @param u16 The tracking data word. */
2516	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2517	/** @} */
2518
2519
2520
2521	/** @name A20 gate macros
2522	* @{ */
2523	#define PGM_WITH_A20
2524	#ifdef PGM_WITH_A20
2525	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2526	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2527	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2528	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2529	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2530	#else
2531	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2532	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2533	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2534	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2535	#endif
2536	/** @} */
2537
2538
2539	/**
2540	* Roots and anchors for trees and list employing self relative offsets as
2541	* pointers.
2542	*
2543	* When using self-relative offsets instead of pointers, the offsets needs to be
2544	* the same in all offsets. Thus the roots and anchors needs to live on the
2545	* hyper heap just like the nodes.
2546	*/
2547	typedef struct PGMTREES
2548	{
2549	/** List of physical access handler types (offset pointers) of type
2550	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2551	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2552	/** Physical access handlers (AVL range+offsetptr tree). */
2553	AVLROGCPHYSTREE PhysHandlers;
2554	} PGMTREES;
2555	/** Pointer to PGM trees. */
2556	typedef PGMTREES *PPGMTREES;
2557
2558
2559	/**
2560	* Page fault guest state for the AMD64 paging mode.
2561	*/
2562	typedef struct PGMPTWALKCORE
2563	{
2564	/** The guest virtual address that is being resolved by the walk
2565	* (input). */
2566	RTGCPTR GCPtr;
2567
2568	/** The guest physical address that is the result of the walk.
2569	* @remarks only valid if fSucceeded is set. */
2570	RTGCPHYS GCPhys;
2571
2572	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2573	bool fSucceeded;
2574	/** The level problem arrised at.
2575	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2576	* level 8. This is 0 on success. */
2577	uint8_t uLevel;
2578	/** Set if the page isn't present. */
2579	bool fNotPresent;
2580	/** Encountered a bad physical address. */
2581	bool fBadPhysAddr;
2582	/** Set if there was reserved bit violations. */
2583	bool fRsvdError;
2584	/** Set if it involves a big page (2/4 MB). */
2585	bool fBigPage;
2586	/** Set if it involves a gigantic page (1 GB). */
2587	bool fGigantPage;
2588	/** The effective X86_PTE_US flag for the address. */
2589	bool fEffectiveUS;
2590	/** The effective X86_PTE_RW flag for the address. */
2591	bool fEffectiveRW;
2592	/** The effective X86_PTE_NX flag for the address. */
2593	bool fEffectiveNX;
2594	bool afPadding1[2];
2595	/** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2596	* The NX bit is inverted and shifted down 63 places to bit 0. */
2597	uint32_t fEffective;
2598	} PGMPTWALKCORE;
2599
2600	/** @name PGMPTWALKCORE::fEffective bits.
2601	* @{ */
2602	/** Effective execute bit (!NX). */
2603	#define PGMPTWALK_EFF_X UINT32_C(1)
2604	/** Effective write access bit. */
2605	#define PGMPTWALK_EFF_RW X86_PTE_RW
2606	/** Effective user-mode access bit. */
2607	#define PGMPTWALK_EFF_US X86_PTE_US
2608	/** Effective write through cache bit. */
2609	#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2610	/** Effective cache disabled bit. */
2611	#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2612	/** Effective accessed bit. */
2613	#define PGMPTWALK_EFF_A X86_PTE_A
2614	/** The dirty bit of the final entry. */
2615	#define PGMPTWALK_EFF_D X86_PTE_D
2616	/** The PAT bit of the final entry. */
2617	#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2618	/** The global bit of the final entry. */
2619	#define PGMPTWALK_EFF_G X86_PTE_G
2620	/** @} */
2621
2622
2623	/**
2624	* Guest page table walk for the AMD64 mode.
2625	*/
2626	typedef struct PGMPTWALKGSTAMD64
2627	{
2628	/** The common core. */
2629	PGMPTWALKCORE Core;
2630
2631	PX86PML4 pPml4;
2632	PX86PML4E pPml4e;
2633	X86PML4E Pml4e;
2634
2635	PX86PDPT pPdpt;
2636	PX86PDPE pPdpe;
2637	X86PDPE Pdpe;
2638
2639	PX86PDPAE pPd;
2640	PX86PDEPAE pPde;
2641	X86PDEPAE Pde;
2642
2643	PX86PTPAE pPt;
2644	PX86PTEPAE pPte;
2645	X86PTEPAE Pte;
2646	} PGMPTWALKGSTAMD64;
2647	/** Pointer to a AMD64 guest page table walk. */
2648	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2649	/** Pointer to a const AMD64 guest page table walk. */
2650	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2651
2652	/**
2653	* Guest page table walk for the PAE mode.
2654	*/
2655	typedef struct PGMPTWALKGSTPAE
2656	{
2657	/** The common core. */
2658	PGMPTWALKCORE Core;
2659
2660	PX86PDPT pPdpt;
2661	PX86PDPE pPdpe;
2662	X86PDPE Pdpe;
2663
2664	PX86PDPAE pPd;
2665	PX86PDEPAE pPde;
2666	X86PDEPAE Pde;
2667
2668	PX86PTPAE pPt;
2669	PX86PTEPAE pPte;
2670	X86PTEPAE Pte;
2671	} PGMPTWALKGSTPAE;
2672	/** Pointer to a PAE guest page table walk. */
2673	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2674	/** Pointer to a const AMD64 guest page table walk. */
2675	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2676
2677	/**
2678	* Guest page table walk for the 32-bit mode.
2679	*/
2680	typedef struct PGMPTWALKGST32BIT
2681	{
2682	/** The common core. */
2683	PGMPTWALKCORE Core;
2684
2685	PX86PD pPd;
2686	PX86PDE pPde;
2687	X86PDE Pde;
2688
2689	PX86PT pPt;
2690	PX86PTE pPte;
2691	X86PTE Pte;
2692	} PGMPTWALKGST32BIT;
2693	/** Pointer to a 32-bit guest page table walk. */
2694	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2695	/** Pointer to a const 32-bit guest page table walk. */
2696	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2697
2698	/**
2699	* Which part of PGMPTWALKGST that is valid.
2700	*/
2701	typedef enum PGMPTWALKGSTTYPE
2702	{
2703	/** Customary invalid 0 value. */
2704	PGMPTWALKGSTTYPE_INVALID = 0,
2705	/** PGMPTWALKGST::u.Amd64 is valid. */
2706	PGMPTWALKGSTTYPE_AMD64,
2707	/** PGMPTWALKGST::u.Pae is valid. */
2708	PGMPTWALKGSTTYPE_PAE,
2709	/** PGMPTWALKGST::u.Legacy is valid. */
2710	PGMPTWALKGSTTYPE_32BIT,
2711	/** Customary 32-bit type hack. */
2712	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2713	} PGMPTWALKGSTTYPE;
2714
2715	/**
2716	* Combined guest page table walk result.
2717	*/
2718	typedef struct PGMPTWALKGST
2719	{
2720	union
2721	{
2722	/** The page walker core - always valid. */
2723	PGMPTWALKCORE Core;
2724	/** The page walker for AMD64. */
2725	PGMPTWALKGSTAMD64 Amd64;
2726	/** The page walker for PAE (32-bit). */
2727	PGMPTWALKGSTPAE Pae;
2728	/** The page walker for 32-bit paging (called legacy due to C naming
2729	* convension). */
2730	PGMPTWALKGST32BIT Legacy;
2731	} u;
2732	/** Indicates which part of the union is valid. */
2733	PGMPTWALKGSTTYPE enmType;
2734	} PGMPTWALKGST;
2735	/** Pointer to a combined guest page table walk result. */
2736	typedef PGMPTWALKGST *PPGMPTWALKGST;
2737	/** Pointer to a read-only combined guest page table walk result. */
2738	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2739
2740
2741	/** @name Paging mode macros
2742	* @{
2743	*/
2744	#ifdef IN_RING3
2745	# define PGM_CTX(a,b) a##R3##b
2746	# define PGM_CTX_STR(a,b) a "R3" b
2747	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2748	#elif defined(IN_RING0)
2749	# define PGM_CTX(a,b) a##R0##b
2750	# define PGM_CTX_STR(a,b) a "R0" b
2751	# define PGM_CTX_DECL(type) VMMDECL(type)
2752	#else
2753	# error "Not IN_RING3 or IN_RING0!"
2754	#endif
2755
2756	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2757	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2758	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2759	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2760	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2761	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2762	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2763	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2764	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2765	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2766	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2767	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2768	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2769	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2770	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2771	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2772
2773	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2774	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2775	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2776	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2777	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2778	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2779	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2780	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2781	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2782	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2783	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2784	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2785	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2786	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2787	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2788	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2789	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2790	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2791	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2792	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2793	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2794	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2795	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2796	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2797	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2798
2799	/* Shw_Gst */
2800	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2801	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2802	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2803	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2804	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2805	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2806	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2807	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2808	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2809	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2810	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2811	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2812	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2813	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2814	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2815	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2816	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2817	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2818	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2819	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2820	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2821	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2822	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2823	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2824	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2825	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2826	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2827	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2828	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2829	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2830	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2831	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2832	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2833	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2834
2835	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2836	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2837	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2838	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2839	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2840	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2841	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2842	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2843	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2844	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2845	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2846	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2847	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2848	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2849	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2850	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2851	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2852	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2853	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2854	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2855	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2856	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2857	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2858	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2859	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2860	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2861	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2862	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2863
2864	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2865	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2866	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2867	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2868	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2869	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2870	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2871	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2872	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2873	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2874	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2875	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2876	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2877	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2878	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2879	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2880	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2881	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2882	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2883	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2884	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2885	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2886	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2887	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2888	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2889	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2890	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2891	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2892	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2893
2894	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2895	/** @} */
2896
2897
2898	/**
2899	* Function pointers for guest paging.
2900	*/
2901	typedef struct PGMMODEDATAGST
2902	{
2903	/** The guest mode type. */
2904	uint32_t uType;
2905	DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
2906	DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
2907	DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
2908	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2909	DECLCALLBACKMEMBER(int, pfnExit)(PVMCPUCC pVCpu);
2910	#ifdef IN_RING3
2911	DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPUCC pVCpu, RTGCPTR offDelta); /*< Only in ring-3. /
2912	#endif
2913	} PGMMODEDATAGST;
2914
2915	/** The length of g_aPgmGuestModeData. */
2916	#ifdef VBOX_WITH_64_BITS_GUESTS
2917	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2918	#else
2919	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2920	#endif
2921	/** The guest mode data array. */
2922	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2923
2924
2925	/**
2926	* Function pointers for shadow paging.
2927	*/
2928	typedef struct PGMMODEDATASHW
2929	{
2930	/** The shadow mode type. */
2931	uint32_t uType;
2932	DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
2933	DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2934	uint64_t fMask, uint32_t fOpFlags);
2935	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, bool fIs64BitsPagingMode);
2936	DECLCALLBACKMEMBER(int, pfnExit)(PVMCPUCC pVCpu);
2937	#ifdef IN_RING3
2938	DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPUCC pVCpu, RTGCPTR offDelta); /*< Only in ring-3. /
2939	#endif
2940	} PGMMODEDATASHW;
2941
2942	/** The length of g_aPgmShadowModeData. */
2943	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2944	/** The shadow mode data array. */
2945	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2946
2947
2948	/**
2949	* Function pointers for guest+shadow paging.
2950	*/
2951	typedef struct PGMMODEDATABTH
2952	{
2953	/** The shadow mode type. */
2954	uint32_t uShwType;
2955	/** The guest mode type. */
2956	uint32_t uGstType;
2957
2958	DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
2959	DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
2960	DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
2961	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
2962	DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2963	DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPUCC pVCpu);
2964	DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
2965	#ifndef IN_RING3
2966	DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
2967	#endif
2968	#ifdef VBOX_STRICT
2969	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
2970	#endif
2971	} PGMMODEDATABTH;
2972
2973	/** The length of g_aPgmBothModeData. */
2974	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2975	/** The guest+shadow mode data array. */
2976	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2977
2978
2979	#ifdef VBOX_WITH_STATISTICS
2980	/**
2981	* PGM statistics.
2982	*
2983	* These lives on the heap when compiled in as they would otherwise waste
2984	* unnecessary space in release builds.
2985	*/
2986	typedef struct PGMSTATS
2987	{
2988	/* R3 only: */
2989	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2990	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2991
2992	/* R3+RZ */
2993	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2994	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2995	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2996	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2997	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2998	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2999	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3000	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3001	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3002	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3003	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3004	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3005	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3006	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3007	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3008	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3009	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3010	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3011	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3012	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3013	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3014	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3015	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3016	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3017	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3018	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3019
3020	/* RC only: */
3021	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3022	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3023
3024	STAMCOUNTER StatRZPhysRead;
3025	STAMCOUNTER StatRZPhysReadBytes;
3026	STAMCOUNTER StatRZPhysWrite;
3027	STAMCOUNTER StatRZPhysWriteBytes;
3028	STAMCOUNTER StatR3PhysRead;
3029	STAMCOUNTER StatR3PhysReadBytes;
3030	STAMCOUNTER StatR3PhysWrite;
3031	STAMCOUNTER StatR3PhysWriteBytes;
3032	STAMCOUNTER StatRCPhysRead;
3033	STAMCOUNTER StatRCPhysReadBytes;
3034	STAMCOUNTER StatRCPhysWrite;
3035	STAMCOUNTER StatRCPhysWriteBytes;
3036
3037	STAMCOUNTER StatRZPhysSimpleRead;
3038	STAMCOUNTER StatRZPhysSimpleReadBytes;
3039	STAMCOUNTER StatRZPhysSimpleWrite;
3040	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3041	STAMCOUNTER StatR3PhysSimpleRead;
3042	STAMCOUNTER StatR3PhysSimpleReadBytes;
3043	STAMCOUNTER StatR3PhysSimpleWrite;
3044	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3045	STAMCOUNTER StatRCPhysSimpleRead;
3046	STAMCOUNTER StatRCPhysSimpleReadBytes;
3047	STAMCOUNTER StatRCPhysSimpleWrite;
3048	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3049
3050	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3051	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3052	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3053	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3054	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3055	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3056	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3057
3058	/** Time spent by the host OS for large page allocation. */
3059	STAMPROFILE StatAllocLargePage;
3060	/** Time spent clearing the newly allocated large pages. */
3061	STAMPROFILE StatClearLargePage;
3062	/** The number of times allocating a large pages takes more than the allowed period. */
3063	STAMCOUNTER StatLargePageOverflow;
3064	/** pgmPhysIsValidLargePage profiling - R3 */
3065	STAMPROFILE StatR3IsValidLargePage;
3066	/** pgmPhysIsValidLargePage profiling - RZ*/
3067	STAMPROFILE StatRZIsValidLargePage;
3068
3069	STAMPROFILE StatChunkAging;
3070	STAMPROFILE StatChunkFindCandidate;
3071	STAMPROFILE StatChunkUnmap;
3072	STAMPROFILE StatChunkMap;
3073	} PGMSTATS;
3074	#endif /* VBOX_WITH_STATISTICS */
3075
3076
3077	/**
3078	* Converts a PGM pointer into a VM pointer.
3079	* @returns Pointer to the VM structure the PGM is part of.
3080	* @param pPGM Pointer to PGM instance data.
3081	*/
3082	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3083
3084	/**
3085	* PGM Data (part of VM)
3086	*/
3087	typedef struct PGM
3088	{
3089	/** Offset to the VM structure. */
3090	int32_t offVM;
3091	/** Offset of the PGMCPU structure relative to VMCPU. */
3092	int32_t offVCpuPGM;
3093
3094	/** @cfgm{/RamPreAlloc, boolean, false}
3095	* Indicates whether the base RAM should all be allocated before starting
3096	* the VM (default), or if it should be allocated when first written to.
3097	*/
3098	bool fRamPreAlloc;
3099	/** Indicates whether write monitoring is currently in use.
3100	* This is used to prevent conflicts between live saving and page sharing
3101	* detection. */
3102	bool fPhysWriteMonitoringEngaged;
3103	/** Set if the CPU has less than 52-bit physical address width.
3104	* This is used */
3105	bool fLessThan52PhysicalAddressBits;
3106	/** Set when nested paging is active.
3107	* This is meant to save calls to HMIsNestedPagingActive and let the
3108	* compilers optimize the code better. Whether we use nested paging or
3109	* not is something we find out during VMM initialization and we won't
3110	* change this later on. */
3111	bool fNestedPaging;
3112	/** The host paging mode. (This is what SUPLib reports.) */
3113	SUPPAGINGMODE enmHostMode;
3114	/** We're not in a state which permits writes to guest memory.
3115	* (Only used in strict builds.) */
3116	bool fNoMorePhysWrites;
3117	/** @cfgm{/PageFusionAllowed, boolean, false}
3118	* Whether page fusion is allowed. */
3119	bool fPageFusionAllowed;
3120	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3121	* Whether PCI passthrough is enabled. */
3122	bool fPciPassthrough;
3123	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3124	uint8_t cMmio2Regions;
3125	/** Restore original ROM page content when resetting after loading state.
3126	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3127	* enables the VM to start using an updated ROM without requiring powering
3128	* down the VM, just rebooting or resetting it. */
3129	bool fRestoreRomPagesOnReset;
3130	/** Whether to automatically clear all RAM pages on reset. */
3131	bool fZeroRamPagesOnReset;
3132	/** Alignment padding. */
3133	bool afAlignment3[7];
3134
3135	/** Indicates that PGMR3FinalizeMappings has been called and that further
3136	* PGMR3MapIntermediate calls will be rejected. */
3137	bool fFinalizedMappings;
3138	/** If set no conflict checks are required. */
3139	bool fMappingsFixed;
3140	/** If set if restored as fixed but we were unable to re-fixate at the old
3141	* location because of room or address incompatibilities. */
3142	bool fMappingsFixedRestored;
3143	/** Size of fixed mapping.
3144	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3145	uint32_t cbMappingFixed;
3146	/** Generation ID for the RAM ranges. This member is incremented everytime
3147	* a RAM range is linked or unlinked. */
3148	uint32_t volatile idRamRangesGen;
3149
3150	/** Base address (GC) of fixed mapping.
3151	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3152	RTGCPTR GCPtrMappingFixed;
3153	/** The address of the previous RAM range mapping. */
3154	RTGCPTR GCPtrPrevRamRangeMapping;
3155
3156	/** Physical access handler type for ROM protection. */
3157	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3158	/** Alignment padding. */
3159	uint32_t u32Padding;
3160
3161	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3162	RTGCPHYS GCPhys4MBPSEMask;
3163	/** Mask containing the invalid bits of a guest physical address.
3164	* @remarks this does not stop at bit 52. */
3165	RTGCPHYS GCPhysInvAddrMask;
3166
3167
3168	/** RAM range TLB for R3. */
3169	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3170	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3171	* This is sorted by physical address and contains no overlapping ranges. */
3172	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3173	/** Root of the RAM range search tree for ring-3. */
3174	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3175	/** PGM offset based trees - R3 Ptr. */
3176	R3PTRTYPE(PPGMTREES) pTreesR3;
3177	/** Caching the last physical handler we looked up in R3. */
3178	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3179	/** Shadow Page Pool - R3 Ptr. */
3180	R3PTRTYPE(PPGMPOOL) pPoolR3;
3181	#ifndef PGM_WITHOUT_MAPPINGS
3182	/** Linked list of GC mappings - for HC.
3183	* The list is sorted ascending on address. */
3184	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3185	#endif
3186	/** Pointer to the list of ROM ranges - for R3.
3187	* This is sorted by physical address and contains no overlapping ranges. */
3188	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3189	/** Pointer to the list of MMIO2 ranges - for R3.
3190	* Registration order. */
3191	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3192	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3193	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3194
3195	/** RAM range TLB for R0. */
3196	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3197	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3198	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3199	/** Root of the RAM range search tree for ring-0. */
3200	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3201	/** PGM offset based trees - R0 Ptr. */
3202	R0PTRTYPE(PPGMTREES) pTreesR0;
3203	/** Caching the last physical handler we looked up in R0. */
3204	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3205	/** Shadow Page Pool - R0 Ptr. */
3206	R0PTRTYPE(PPGMPOOL) pPoolR0;
3207	#ifndef PGM_WITHOUT_MAPPINGS
3208	/** Linked list of GC mappings - for R0.
3209	* The list is sorted ascending on address. */
3210	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3211	RTR0PTR R0PtrAlignment0;
3212	#endif
3213	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3214	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3215	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3216	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3217
3218	#ifndef PGM_WITHOUT_MAPPINGS
3219	/** Pointer to the 5 page CR3 content mapping.
3220	* The first page is always the CR3 (in some form) while the 4 other pages
3221	* are used for the PDs in PAE mode. */
3222	RTGCPTR GCPtrCR3Mapping;
3223
3224	/** @name Intermediate Context
3225	* @{ */
3226	/** Pointer to the intermediate page directory - Normal. */
3227	R3PTRTYPE(PX86PD) pInterPD;
3228	/** Pointer to the intermediate page tables - Normal.
3229	* There are two page tables, one for the identity mapping and one for
3230	* the host context mapping (of the core code). */
3231	R3PTRTYPE(PX86PT) apInterPTs[2];
3232	/** Pointer to the intermediate page tables - PAE. */
3233	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3234	/** Pointer to the intermediate page directory - PAE. */
3235	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3236	/** Pointer to the intermediate page directory - PAE. */
3237	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3238	/** Pointer to the intermediate page-map level 4 - AMD64. */
3239	R3PTRTYPE(PX86PML4) pInterPaePML4;
3240	/** Pointer to the intermediate page directory - AMD64. */
3241	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3242	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3243	RTHCPHYS HCPhysInterPD;
3244	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3245	RTHCPHYS HCPhysInterPaePDPT;
3246	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3247	RTHCPHYS HCPhysInterPaePML4;
3248	/** @} */
3249	#endif
3250
3251	#ifndef PGM_WITHOUT_MAPPINGS
3252	/** Base address of the dynamic page mapping area.
3253	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3254	*
3255	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3256	* work out. Some cleaning up of the initialization that would
3257	* remove this memory is yet to be done...
3258	*/
3259	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3260	/** The address of the raw-mode context mapping cache. */
3261	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3262	/** The address of the ring-0 mapping cache if we're making use of it. */
3263	RTR0PTR pvR0DynMapUsed;
3264	#endif
3265
3266	/** Hack: Number of deprecated page mapping locks taken by the current lock
3267	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3268	uint32_t cDeprecatedPageLocks;
3269	/** Alignment padding. */
3270	uint32_t au32Alignment2[1];
3271
3272
3273	/** PGM critical section.
3274	* This protects the physical, ram ranges, and the page flag updating (some of
3275	* it anyway).
3276	*/
3277	PDMCRITSECT CritSectX;
3278
3279	/**
3280	* Data associated with managing the ring-3 mappings of the allocation chunks.
3281	*/
3282	struct
3283	{
3284	/** The chunk mapping TLB. */
3285	PGMCHUNKR3MAPTLB Tlb;
3286	/** The chunk tree, ordered by chunk id. */
3287	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
3288	R3PTRTYPE(PAVLU32NODECORE) pTree;
3289	#else
3290	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3291	#endif
3292	#if HC_ARCH_BITS == 32
3293	uint32_t u32Alignment0;
3294	#endif
3295	/** The number of mapped chunks. */
3296	uint32_t c;
3297	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3298	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3299	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3300	uint32_t cMax;
3301	/** The current time. This is incremented whenever a chunk is inserted. */
3302	uint32_t iNow;
3303	/** Alignment padding. */
3304	uint32_t au32Alignment1[3];
3305	} ChunkR3Map;
3306
3307	/** The page mapping TLB for ring-3. */
3308	PGMPAGER3MAPTLB PhysTlbR3;
3309	#ifdef VBOX_WITH_RAM_IN_KERNEL
3310	/** The page mapping TLB for ring-0. */
3311	PGMPAGER0MAPTLB PhysTlbR0;
3312	#else
3313	/** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3314	PGMPAGER3MAPTLB PhysTlbR0;
3315	#endif
3316
3317	/** @name The zero page.
3318	* @{ */
3319	/** The host physical address of the zero page. */
3320	RTHCPHYS HCPhysZeroPg;
3321	/** The ring-3 mapping of the zero page. */
3322	RTR3PTR pvZeroPgR3;
3323	/** The ring-0 mapping of the zero page. */
3324	RTR0PTR pvZeroPgR0;
3325	/** The GC mapping of the zero page. */
3326	RTRCPTR pvZeroPgRC;
3327	RTRCPTR RCPtrAlignment3;
3328	/** @}*/
3329
3330	/** @name The Invalid MMIO page.
3331	* This page is filled with 0xfeedface.
3332	* @{ */
3333	/** The host physical address of the invalid MMIO page. */
3334	RTHCPHYS HCPhysMmioPg;
3335	/** The host pysical address of the invalid MMIO page plus all invalid
3336	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3337	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3338	RTHCPHYS HCPhysInvMmioPg;
3339	/** The ring-3 mapping of the invalid MMIO page. */
3340	RTR3PTR pvMmioPgR3;
3341	#if HC_ARCH_BITS == 32
3342	RTR3PTR R3PtrAlignment4;
3343	#endif
3344	/** @} */
3345
3346
3347	/** The number of handy pages. */
3348	uint32_t cHandyPages;
3349
3350	/** The number of large handy pages. */
3351	uint32_t cLargeHandyPages;
3352
3353	/**
3354	* Array of handy pages.
3355	*
3356	* This array is used in a two way communication between pgmPhysAllocPage
3357	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3358	* an intermediary.
3359	*
3360	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3361	* (The current size of 32 pages, means 128 KB of handy memory.)
3362	*/
3363	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3364
3365	/**
3366	* Array of large handy pages. (currently size 1)
3367	*
3368	* This array is used in a two way communication between pgmPhysAllocLargePage
3369	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3370	* an intermediary.
3371	*/
3372	GMMPAGEDESC aLargeHandyPage[1];
3373
3374	/**
3375	* Live save data.
3376	*/
3377	struct
3378	{
3379	/** Per type statistics. */
3380	struct
3381	{
3382	/** The number of ready pages. */
3383	uint32_t cReadyPages;
3384	/** The number of dirty pages. */
3385	uint32_t cDirtyPages;
3386	/** The number of ready zero pages. */
3387	uint32_t cZeroPages;
3388	/** The number of write monitored pages. */
3389	uint32_t cMonitoredPages;
3390	} Rom,
3391	Mmio2,
3392	Ram;
3393	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3394	uint32_t cIgnoredPages;
3395	/** Indicates that a live save operation is active. */
3396	bool fActive;
3397	/** Padding. */
3398	bool afReserved[2];
3399	/** The next history index. */
3400	uint8_t iDirtyPagesHistory;
3401	/** History of the total amount of dirty pages. */
3402	uint32_t acDirtyPagesHistory[64];
3403	/** Short term dirty page average. */
3404	uint32_t cDirtyPagesShort;
3405	/** Long term dirty page average. */
3406	uint32_t cDirtyPagesLong;
3407	/** The number of saved pages. This is used to get some kind of estimate of the
3408	* link speed so we can decide when we're done. It is reset after the first
3409	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3410	* zero pages. */
3411	uint64_t cSavedPages;
3412	/** The nanosecond timestamp when cSavedPages was 0. */
3413	uint64_t uSaveStartNS;
3414	/** Pages per second (for statistics). */
3415	uint32_t cPagesPerSecond;
3416	uint32_t cAlignment;
3417	} LiveSave;
3418
3419	/** @name Error injection.
3420	* @{ */
3421	/** Inject handy page allocation errors pretending we're completely out of
3422	* memory. */
3423	bool volatile fErrInjHandyPages;
3424	/** Padding. */
3425	bool afReserved[3];
3426	/** @} */
3427
3428	/** @name Release Statistics
3429	* @{ */
3430	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3431	uint32_t cPrivatePages; /*< The number of private pages. /
3432	uint32_t cSharedPages; /*< The number of shared pages. /
3433	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3434	uint32_t cZeroPages; /*< The number of zero backed pages. /
3435	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3436	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3437	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3438	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3439	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3440	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3441	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3442	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3443	uint32_t cLargePages; /*< The number of large pages. /
3444	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3445	/* uint32_t aAlignment4[1]; */
3446
3447	/** The number of times we were forced to change the hypervisor region location. */
3448	STAMCOUNTER cRelocations;
3449
3450	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3451	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3452	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3453
3454	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3455	/** @} */
3456
3457	#ifdef VBOX_WITH_STATISTICS
3458	/** @name Statistics on the heap.
3459	* @{ */
3460	R3PTRTYPE(PGMSTATS *) pStatsR3;
3461	R0PTRTYPE(PGMSTATS *) pStatsR0;
3462	/** @} */
3463	#endif
3464	} PGM;
3465	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3466	# ifndef PGM_WITHOUT_MAPPINGS
3467	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3468	# endif
3469	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3470	# ifndef PGM_WITHOUT_MAPPINGS
3471	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3472	# endif
3473	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3474	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3475	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3476	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3477	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3478	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3479	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3480	#endif /* !IN_TSTVMSTRUCTGC */
3481	/** Pointer to the PGM instance data. */
3482	typedef PGM *PPGM;
3483
3484
3485
3486	typedef struct PGMCPUSTATS
3487	{
3488	/* Common */
3489	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3490	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3491
3492	/* R0 only: */
3493	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3494	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3495
3496	/* RZ only: */
3497	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3498	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3499	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3500	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3501	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3502	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3503	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3504	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3505	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3506	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3507	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3508	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3509	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3510	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3511	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3512	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3513	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3514	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3515	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3516	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3517	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3518	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3519	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3520	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3521	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3522	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3523	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3524	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3525	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3526	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3527	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3528	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3529	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3530	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3531	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3532	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3533	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3534	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3535	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3536	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3537	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3538	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3539	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3540	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3541	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3542	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3543	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3544	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3545	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3546	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3547	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3548	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3549	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3550	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3551	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3552	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3553	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3554	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3555	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3556	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3557	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3558	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3559	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3560	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3561	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3562	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3563	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3564	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3565	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3566	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3567	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3568	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3569	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3570
3571	/* HC - R3 and (maybe) R0: */
3572
3573	/* RZ & R3: */
3574	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3575	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3576	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3577	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3578	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3579	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3580	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3581	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3582	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3583	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3584	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3585	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3586	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3587	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3588	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3589	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3590	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3591	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3592	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3593	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3594	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3595	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3596	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3597	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3598	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3599	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3600	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3601	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3602	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3603	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3604	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3605	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3606	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3607	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3608	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3609	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3610	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3611	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3612	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3613	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3614	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3615	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3616	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3617	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3618	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3619	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3620	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3621	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3622
3623	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3624	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3625	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3626	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3627	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3628	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3629	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3630	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3631	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3632	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3633	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3634	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3635	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3636	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3637	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3638	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3639	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3640	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3641	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3642	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3643	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3644	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3645	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3646	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3647	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3648	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3649	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3650	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3651	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3652	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3653	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3654	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3655	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3656	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3657	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3658	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3659	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3660	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3661	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3662	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3663	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3664	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3665	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3666	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3667	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3668	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3669	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3670	} PGMCPUSTATS;
3671
3672
3673	/**
3674	* Converts a PGMCPU pointer into a VM pointer.
3675	* @returns Pointer to the VM structure the PGM is part of.
3676	* @param pPGM Pointer to PGMCPU instance data.
3677	*/
3678	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3679
3680	/**
3681	* Converts a PGMCPU pointer into a PGM pointer.
3682	* @returns Pointer to the VM structure the PGM is part of.
3683	* @param pPGMCpu Pointer to PGMCPU instance data.
3684	*/
3685	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3686
3687	/**
3688	* PGMCPU Data (part of VMCPU).
3689	*/
3690	typedef struct PGMCPU
3691	{
3692	/** Offset to the VM structure. */
3693	int32_t offVM;
3694	/** Offset to the VMCPU structure. */
3695	int32_t offVCpu;
3696	/** Offset of the PGM structure relative to VMCPU. */
3697	int32_t offPGM;
3698	uint32_t uPadding0; /*< structure size alignment. /
3699
3700	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3701	/** Automatically tracked physical memory mapping set.
3702	* Ring-0 and strict raw-mode builds. */
3703	PGMMAPSET AutoSet;
3704	#endif
3705
3706	/** A20 gate mask.
3707	* Our current approach to A20 emulation is to let REM do it and don't bother
3708	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3709	* But whould need arrise, we'll subject physical addresses to this mask. */
3710	RTGCPHYS GCPhysA20Mask;
3711	/** A20 gate state - boolean! */
3712	bool fA20Enabled;
3713	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3714	bool fNoExecuteEnabled;
3715	/** Unused bits. */
3716	bool afUnused[2];
3717
3718	/** What needs syncing (PGM_SYNC_*).
3719	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3720	* PGMFlushTLB, and PGMR3Load. */
3721	uint32_t fSyncFlags;
3722
3723	/** The shadow paging mode. */
3724	PGMMODE enmShadowMode;
3725	/** The guest paging mode. */
3726	PGMMODE enmGuestMode;
3727	/** Guest mode data table index (PGM_TYPE_XXX). */
3728	uint8_t volatile idxGuestModeData;
3729	/** Shadow mode data table index (PGM_TYPE_XXX). */
3730	uint8_t volatile idxShadowModeData;
3731	/** Both mode data table index (complicated). */
3732	uint8_t volatile idxBothModeData;
3733	/** Alignment padding. */
3734	uint8_t abPadding[5];
3735
3736	/** The current physical address represented in the guest CR3 register. */
3737	RTGCPHYS GCPhysCR3;
3738
3739	/** @name 32-bit Guest Paging.
3740	* @{ */
3741	/** The guest's page directory, R3 pointer. */
3742	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3743	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3744	/** The guest's page directory, R0 pointer. */
3745	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3746	#endif
3747	/** Mask containing the MBZ bits of a big page PDE. */
3748	uint32_t fGst32BitMbzBigPdeMask;
3749	/** Set if the page size extension (PSE) is enabled. */
3750	bool fGst32BitPageSizeExtension;
3751	/** Alignment padding. */
3752	bool afAlignment2[3];
3753	/** @} */
3754
3755	/** @name PAE Guest Paging.
3756	* @{ */
3757	/** The guest's page directory pointer table, R3 pointer. */
3758	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3759	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3760	/** The guest's page directory pointer table, R0 pointer. */
3761	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3762	#endif
3763
3764	/** The guest's page directories, R3 pointers.
3765	* These are individual pointers and don't have to be adjacent.
3766	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3767	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3768	/** The guest's page directories, R0 pointers.
3769	* Same restrictions as apGstPaePDsR3. */
3770	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3771	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3772	#endif
3773	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3774	* @todo Remove this and use aGstPaePdpeRegs instead? */
3775	RTGCPHYS aGCPhysGstPaePDs[4];
3776	/** The values of the 4 PDPE CPU registers (PAE). */
3777	X86PDPE aGstPaePdpeRegs[4];
3778	/** The physical addresses of the monitored guest page directories (PAE). */
3779	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3780	/** Mask containing the MBZ PTE bits. */
3781	uint64_t fGstPaeMbzPteMask;
3782	/** Mask containing the MBZ PDE bits. */
3783	uint64_t fGstPaeMbzPdeMask;
3784	/** Mask containing the MBZ big page PDE bits. */
3785	uint64_t fGstPaeMbzBigPdeMask;
3786	/** Mask containing the MBZ PDPE bits. */
3787	uint64_t fGstPaeMbzPdpeMask;
3788	/** @} */
3789
3790	/** @name AMD64 Guest Paging.
3791	* @{ */
3792	/** The guest's page directory pointer table, R3 pointer. */
3793	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3794	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3795	/** The guest's page directory pointer table, R0 pointer. */
3796	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3797	#else
3798	RTR0PTR alignment6b; /*< alignment equalizer. /
3799	#endif
3800	/** Mask containing the MBZ PTE bits. */
3801	uint64_t fGstAmd64MbzPteMask;
3802	/** Mask containing the MBZ PDE bits. */
3803	uint64_t fGstAmd64MbzPdeMask;
3804	/** Mask containing the MBZ big page PDE bits. */
3805	uint64_t fGstAmd64MbzBigPdeMask;
3806	/** Mask containing the MBZ PDPE bits. */
3807	uint64_t fGstAmd64MbzPdpeMask;
3808	/** Mask containing the MBZ big page PDPE bits. */
3809	uint64_t fGstAmd64MbzBigPdpeMask;
3810	/** Mask containing the MBZ PML4E bits. */
3811	uint64_t fGstAmd64MbzPml4eMask;
3812	/** Mask containing the PDPE bits that we shadow. */
3813	uint64_t fGstAmd64ShadowedPdpeMask;
3814	/** Mask containing the PML4E bits that we shadow. */
3815	uint64_t fGstAmd64ShadowedPml4eMask;
3816	/** @} */
3817
3818	/** @name PAE and AMD64 Guest Paging.
3819	* @{ */
3820	/** Mask containing the PTE bits that we shadow. */
3821	uint64_t fGst64ShadowedPteMask;
3822	/** Mask containing the PDE bits that we shadow. */
3823	uint64_t fGst64ShadowedPdeMask;
3824	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3825	uint64_t fGst64ShadowedBigPdeMask;
3826	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3827	uint64_t fGst64ShadowedBigPde4PteMask;
3828	/** @} */
3829
3830	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3831	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3832	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3833	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3834
3835	/** For saving stack space, the disassembler state is allocated here instead of
3836	* on the stack. */
3837	DISCPUSTATE DisState;
3838
3839	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3840	uint64_t cNetwareWp0Hacks;
3841
3842	/** Count the number of pgm pool access handler calls. */
3843	uint64_t cPoolAccessHandler;
3844
3845	/** @name Release Statistics
3846	* @{ */
3847	/** The number of times the guest has switched mode since last reset or statistics reset. */
3848	STAMCOUNTER cGuestModeChanges;
3849	/** The number of times the guest has switched mode since last reset or statistics reset. */
3850	STAMCOUNTER cA20Changes;
3851	/** @} */
3852
3853	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3854	/** @name Statistics
3855	* @{ */
3856	/** R0: Pointer to the statistics. */
3857	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3858	/** R0: Which statistic this \#PF should be attributed to. */
3859	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3860	/** R3: Pointer to the statistics. */
3861	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3862	/** Alignment padding. */
3863	RTR3PTR pPaddingR3;
3864	/** @} */
3865	#endif /* VBOX_WITH_STATISTICS */
3866	} PGMCPU;
3867	/** Pointer to the per-cpu PGM data. */
3868	typedef PGMCPU *PPGMCPU;
3869
3870
3871	/** @name PGM::fSyncFlags Flags
3872	* @note Was part of saved state a long time ago.
3873	* @{
3874	*/
3875	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3876	/** Always sync CR3. */
3877	#define PGM_SYNC_ALWAYS RT_BIT(1)
3878	/** Check monitoring on next CR3 (re)load and invalidate page.
3879	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3880	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3881	/** Check guest mapping in SyncCR3. */
3882	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3883	/** Clear the page pool (a light weight flush). */
3884	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3885	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3886	/** @} */
3887
3888
3889	/**
3890	* PGM GVM instance data.
3891	*/
3892	typedef struct PGMR0PERVM
3893	{
3894	/** @name PGM Pool related stuff.
3895	* @{ */
3896	/** Critical section for serializing pool growth. */
3897	RTCRITSECT PoolGrowCritSect;
3898	/** The memory objects for the pool pages. */
3899	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3900	/** The ring-3 mapping objects for the pool pages. */
3901	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3902	/** @} */
3903	} PGMR0PERVM;
3904
3905	RT_C_DECLS_BEGIN
3906
3907	#if defined(VBOX_STRICT) && defined(IN_RING3)
3908	int pgmLockDebug(PVMCC pVM, RT_SRC_POS_DECL);
3909	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
3910	#else
3911	int pgmLock(PVMCC pVM);
3912	#endif
3913	void pgmUnlock(PVM pVM);
3914	/**
3915	* Asserts that the caller owns the PDM lock.
3916	* This is the internal variant of PGMIsLockOwner.
3917	* @param a_pVM Pointer to the VM.
3918	*/
3919	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
3920	/**
3921	* Asserts that the caller owns the PDM lock.
3922	* This is the internal variant of PGMIsLockOwner.
3923	* @param a_pVM Pointer to the VM.
3924	* @param a_pVCpu The current CPU handle.
3925	*/
3926	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
3927
3928	#ifndef PGM_WITHOUT_MAPPINGS
3929	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3930	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3931	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3932	int pgmMapResolveConflicts(PVM pVM);
3933	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3934	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3935	#endif /* !PGM_WITHOUT_MAPPINGS */
3936
3937	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3938	RTRCPTR pvUserRC, R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3939	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3940	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3941	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
3942	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3943	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3944	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3945	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3946	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3947	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3948
3949	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3950	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3951	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3952	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3953	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3954	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3955	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3956	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3957	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3958	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3959	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3960	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3961	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3962	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3963	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3964	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3965	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3966	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3967	#ifndef IN_RING3
3968	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3969	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3970	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3971	#endif
3972	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3973	PGMPAGETYPE enmNewType);
3974	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3975	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3976	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
3977	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3978	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3979	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3980	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3981	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3982
3983	#ifdef IN_RING3
3984	void pgmR3PhysRelinkRamRanges(PVM pVM);
3985	int pgmR3PhysRamPreAllocate(PVM pVM);
3986	int pgmR3PhysRamReset(PVM pVM);
3987	int pgmR3PhysRomReset(PVM pVM);
3988	int pgmR3PhysRamZeroAll(PVM pVM);
3989	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3990	int pgmR3PhysRamTerm(PVM pVM);
3991	void pgmR3PhysRomTerm(PVM pVM);
3992	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3993
3994	int pgmR3PoolInit(PVM pVM);
3995	void pgmR3PoolRelocate(PVM pVM);
3996	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3997	void pgmR3PoolReset(PVM pVM);
3998	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3999	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4000	void pgmR3PoolWriteProtectPages(PVM pVM);
4001
4002	#endif /* IN_RING3 */
4003	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4004	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4005	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4006	# ifdef LOG_ENABLED
4007	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4008	# else
4009	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4010	# endif
4011	#endif
4012	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4013	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4014	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4015	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4016	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4017	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4018	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4019	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4020	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
4021	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
4022	bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4023	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
4024	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4025	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4026	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4027	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4028	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4029	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4030	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4031	#ifndef IN_RING3
4032	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4033	#endif
4034
4035	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4036	void pgmPoolResetDirtyPages(PVMCC pVM);
4037	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4038
4039	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4040	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4041	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4042
4043	#ifndef PGM_WITHOUT_MAPPINGS
4044	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4045	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4046	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4047	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4048	#endif
4049
4050	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4051	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4052	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4053
4054	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4055	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4056	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4057	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4058	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4059	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4060
4061	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4062	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4063	FNDBGCCMD pgmR3CmdShowSharedModules;
4064	# endif
4065
4066	void pgmLogState(PVM pVM);
4067
4068	RT_C_DECLS_END
4069
4070	/** @} */
4071
4072	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4073

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 82819

Download in other formats: