PGMInternal.h@ 86461

Last change on this file since 86461 was 86461, checked in by vboxsync, 4 years ago
VMM/PGM: Don't check for, or even define, PGM_PDFLAGS_MAPPING when PGM_WITHOUT_MAPPINGS is active (the default now).
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 182.7 KB

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1	/* $Id: PGMInternal.h 86461 2020-10-06 16:40:59Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/hm_vmx.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/avl.h>
43	#include <iprt/critsect.h>
44	#include <iprt/list-off32.h>
45	#include <iprt/sha.h>
46
47
48
49	/** @defgroup grp_pgm_int Internals
50	* @ingroup grp_pgm
51	* @internal
52	* @{
53	*/
54
55
56	/** @name PGM Compile Time Config
57	* @{
58	*/
59
60	/**
61	* Indicates that there are no guest mappings in the shadow tables.
62	*
63	* Note! In ring-3 the macro is also used to exclude the managment of the
64	* intermediate context page tables. On 32-bit systems we use the intermediate
65	* context to support 64-bit guest execution. Thus, we cannot fully make it
66	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67	*
68	* In raw-mode context there are by design always guest mappings (the code is
69	* executed from one), while in ring-0 there are none at all. Neither context
70	* manages the page tables for intermediate switcher context, that's all done in
71	* ring-3.
72	*
73	* Update 6.1: It is always defined now, in pgm.h
74	*/
75	#if defined(IN_RING0) \
76	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
77	&& ( HC_ARCH_BITS != 32 \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# undef PGM_WITHOUT_MAPPINGS
82	# define PGM_WITHOUT_MAPPINGS
83	#endif
84
85	/**
86	* Check and skip global PDEs for non-global flushes
87	*/
88	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90	/**
91	* Optimization for PAE page tables that are modified often
92	*/
93	//#if 0 /* disabled again while debugging */
94	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	//#endif
96
97	/**
98	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
99	*/
100	#define PGM_WITH_LARGE_PAGES
101
102	/**
103	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
104	* VMX_EXIT_EPT_MISCONFIG.
105	*/
106	#define PGM_WITH_MMIO_OPTIMIZATIONS
107
108	/**
109	* Sync N pages instead of a whole page table
110	*/
111	#define PGM_SYNC_N_PAGES
112
113	/**
114	* Number of pages to sync during a page fault
115	*
116	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118	*
119	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120	* world switch overhead, so let's sync more.
121	*/
122	# ifdef IN_RING0
123	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125	* but ~5% fewer faults.
126	*/
127	# define PGM_SYNC_NR_PAGES 32
128	#else
129	# define PGM_SYNC_NR_PAGES 8
130	#endif
131
132	/**
133	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134	*/
135	#define PGM_MAX_PHYSCACHE_ENTRIES 64
136	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139	/** @def PGMPOOL_CFG_MAX_GROW
140	* The maximum number of pages to add to the pool in one go.
141	*/
142	#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
143
144	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
146	*/
147	#ifdef VBOX_STRICT
148	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149	#endif
150
151	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152	* Enables the experimental lazy page allocation code. */
153	#ifdef DOXYGEN_RUNNING
154	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155	#endif
156
157	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158	* Enables real write monitoring of pages, i.e. mapping them read-only and
159	* only making them writable when getting a write access \#PF. */
160	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162	/** @} */
163
164
165	/** @name PDPT and PML4 flags.
166	* These are placed in the three bits available for system programs in
167	* the PDPT and PML4 entries.
168	* @{ */
169	/** The entry is a permanent one and it's must always be present.
170	* Never free such an entry. */
171	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172	/** Mapping (hypervisor allocated pagetable). */
173	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174	/** @} */
175
176	/** @name Page directory flags.
177	* These are placed in the three bits available for system programs in
178	* the page directory entries.
179	* @{ */
180	/** Indicates the original entry was a big page.
181	* @remarks This is currently only used for statistics and can be recycled. */
182	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
183	#ifndef PGM_WITHOUT_MAPPINGS
184	/** Mapping (hypervisor allocated pagetable). */
185	# define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
186	#endif
187	/** Made read-only to facilitate dirty bit tracking. */
188	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
189	/** @} */
190
191	/** @name Page flags.
192	* These are placed in the three bits available for system programs in
193	* the page entries.
194	* @{ */
195	/** Made read-only to facilitate dirty bit tracking. */
196	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
197
198	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
199	/** Scanned and approved by CSAM (tm).
200	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
201	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
202	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
203	#endif
204
205	/** @} */
206
207	/** @name Defines used to indicate the shadow and guest paging in the templates.
208	* @{ */
209	#define PGM_TYPE_REAL 1
210	#define PGM_TYPE_PROT 2
211	#define PGM_TYPE_32BIT 3
212	#define PGM_TYPE_PAE 4
213	#define PGM_TYPE_AMD64 5
214	#define PGM_TYPE_NESTED_32BIT 6
215	#define PGM_TYPE_NESTED_PAE 7
216	#define PGM_TYPE_NESTED_AMD64 8
217	#define PGM_TYPE_EPT 9
218	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
219	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
220	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
221	/** @} */
222
223	/** Macro for checking if the guest is using paging.
224	* @param uGstType PGM_TYPE_*
225	* @param uShwType PGM_TYPE_*
226	* @remark ASSUMES certain order of the PGM_TYPE_* values.
227	*/
228	#define PGM_WITH_PAGING(uGstType, uShwType) \
229	( (uGstType) >= PGM_TYPE_32BIT \
230	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
231
232	/** Macro for checking if the guest supports the NX bit.
233	* @param uGstType PGM_TYPE_*
234	* @param uShwType PGM_TYPE_*
235	* @remark ASSUMES certain order of the PGM_TYPE_* values.
236	*/
237	#define PGM_WITH_NX(uGstType, uShwType) \
238	( (uGstType) >= PGM_TYPE_PAE \
239	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241	/** Macro for checking for nested or EPT.
242	* @param uType PGM_TYPE_*
243	*/
244	#define PGM_TYPE_IS_NESTED(uType) \
245	( (uType) == PGM_TYPE_NESTED_32BIT \
246	\|\| (uType) == PGM_TYPE_NESTED_PAE \
247	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
248
249	/** Macro for checking for nested or EPT.
250	* @param uType PGM_TYPE_*
251	*/
252	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
253	( (uType) == PGM_TYPE_NESTED_32BIT \
254	\|\| (uType) == PGM_TYPE_NESTED_PAE \
255	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
256	\|\| (uType) == PGM_TYPE_EPT)
257
258
259
260	/** @def PGM_HCPHYS_2_PTR
261	* Maps a HC physical page pool address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
266	* @param HCPhys The HC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast
268	* this.
269	*
270	* @remark There is no need to assert on the result.
271	*/
272	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
273
274	/** @def PGM_GCPHYS_2_PTR_V2
275	* Maps a GC physical page address to a virtual address.
276	*
277	* @returns VBox status code.
278	* @param pVM The cross context VM structure.
279	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
280	* @param GCPhys The GC physical address to map to a virtual one.
281	* @param ppv Where to store the virtual address. No need to cast this.
282	*
283	* @remark Use with care as we don't have so much dynamic mapping space in
284	* ring-0 on 32-bit darwin and in RC.
285	* @remark There is no need to assert on the result.
286	*/
287	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
288	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
289	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
290	#else
291	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
292	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
293	#endif
294
295	/** @def PGM_GCPHYS_2_PTR
296	* Maps a GC physical page address to a virtual address.
297	*
298	* @returns VBox status code.
299	* @param pVM The cross context VM structure.
300	* @param GCPhys The GC physical address to map to a virtual one.
301	* @param ppv Where to store the virtual address. No need to cast this.
302	*
303	* @remark Use with care as we don't have so much dynamic mapping space in
304	* ring-0 on 32-bit darwin and in RC.
305	* @remark There is no need to assert on the result.
306	*/
307	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
308
309	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
310	* Maps a GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark Use with care as we don't have so much dynamic mapping space in
318	* ring-0 on 32-bit darwin and in RC.
319	* @remark There is no need to assert on the result.
320	*/
321	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
322
323	/** @def PGM_GCPHYS_2_PTR_EX
324	* Maps a unaligned GC physical page address to a virtual address.
325	*
326	* @returns VBox status code.
327	* @param pVM The cross context VM structure.
328	* @param GCPhys The GC physical address to map to a virtual one.
329	* @param ppv Where to store the virtual address. No need to cast this.
330	*
331	* @remark Use with care as we don't have so much dynamic mapping space in
332	* ring-0 on 32-bit darwin and in RC.
333	* @remark There is no need to assert on the result.
334	*/
335	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
336	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
337	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
338	#else
339	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
340	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
341	#endif
342
343	/** @def PGM_DYNMAP_UNUSED_HINT
344	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
345	* is no longer used.
346	*
347	* For best effect only apply this to the page that was mapped most recently.
348	*
349	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
350	* @param pvPage The pool page.
351	*/
352	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
353	# ifdef LOG_ENABLED
354	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
355	# else
356	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
357	# endif
358	#else
359	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
360	#endif
361
362	/** @def PGM_DYNMAP_UNUSED_HINT_VM
363	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
364	* is no longer used.
365	*
366	* For best effect only apply this to the page that was mapped most recently.
367	*
368	* @param pVM The cross context VM structure.
369	* @param pvPage The pool page.
370	*/
371	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
372
373
374	/** @def PGM_INVL_PG
375	* Invalidates a page.
376	*
377	* @param pVCpu The cross context virtual CPU structure.
378	* @param GCVirt The virtual address of the page to invalidate.
379	*/
380	#ifdef IN_RING0
381	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
382	#elif defined(IN_RING3)
383	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
384	#else
385	# error "Not IN_RING0 or IN_RING3!"
386	#endif
387
388	/** @def PGM_INVL_PG_ALL_VCPU
389	* Invalidates a page on all VCPUs
390	*
391	* @param pVM The cross context VM structure.
392	* @param GCVirt The virtual address of the page to invalidate.
393	*/
394	#ifdef IN_RING0
395	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
396	#else
397	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
398	#endif
399
400	/** @def PGM_INVL_BIG_PG
401	* Invalidates a 4MB page directory entry.
402	*
403	* @param pVCpu The cross context virtual CPU structure.
404	* @param GCVirt The virtual address within the page directory to invalidate.
405	*/
406	#ifdef IN_RING0
407	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
408	#else
409	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
410	#endif
411
412	/** @def PGM_INVL_VCPU_TLBS()
413	* Invalidates the TLBs of the specified VCPU
414	*
415	* @param pVCpu The cross context virtual CPU structure.
416	*/
417	#ifdef IN_RING0
418	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
419	#else
420	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
421	#endif
422
423	/** @def PGM_INVL_ALL_VCPU_TLBS()
424	* Invalidates the TLBs of all VCPUs
425	*
426	* @param pVM The cross context VM structure.
427	*/
428	#ifdef IN_RING0
429	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
430	#else
431	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
432	#endif
433
434
435	/** @name Safer Shadow PAE PT/PTE
436	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
437	* present.
438	*
439	* @{
440	*/
441	#if 1
442	/**
443	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
444	* invalid entries for present.
445	* @sa X86PTEPAE.
446	*/
447	typedef union PGMSHWPTEPAE
448	{
449	/** Unsigned integer view */
450	X86PGPAEUINT uCareful;
451	/* Not other views. */
452	} PGMSHWPTEPAE;
453
454	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
455	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
456	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
457	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
458	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
459	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
460	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
461	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
462	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
463	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
464	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
465	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
466	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
467	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
468	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
469	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
470
471	/**
472	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
473	* invalid entries for present.
474	* @sa X86PTPAE.
475	*/
476	typedef struct PGMSHWPTPAE
477	{
478	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
479	} PGMSHWPTPAE;
480
481	#else
482	typedef X86PTEPAE PGMSHWPTEPAE;
483	typedef X86PTPAE PGMSHWPTPAE;
484	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
485	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
486	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
487	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
488	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
489	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
490	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
491	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
492	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
493	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
494	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
495	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
496	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
497	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
498	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
499	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
500
501	#endif
502
503	/** Pointer to a shadow PAE PTE. */
504	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
505	/** Pointer to a const shadow PAE PTE. */
506	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
507
508	/** Pointer to a shadow PAE page table. */
509	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
510	/** Pointer to a const shadow PAE page table. */
511	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
512	/** @} */
513
514	#ifndef PGM_WITHOUT_MAPPINGS
515
516	/** Size of the GCPtrConflict array in PGMMAPPING.
517	* @remarks Must be a power of two. */
518	# define PGMMAPPING_CONFLICT_MAX 8
519
520	/**
521	* Structure for tracking GC Mappings.
522	*
523	* This structure is used by linked list in both GC and HC.
524	*/
525	typedef struct PGMMAPPING
526	{
527	/** Pointer to next entry. */
528	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
529	/** Pointer to next entry. */
530	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
531	/** Indicate whether this entry is finalized. */
532	bool fFinalized;
533	bool afPadding[7];
534	/** Start Virtual address. */
535	RTGCPTR GCPtr;
536	/** Last Virtual address (inclusive). */
537	RTGCPTR GCPtrLast;
538	/** Range size (bytes). */
539	RTGCPTR cb;
540	/** Pointer to relocation callback function. */
541	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
542	/** User argument to the callback. */
543	R3PTRTYPE(void *) pvUser;
544	/** Mapping description / name. For easing debugging. */
545	R3PTRTYPE(const char *) pszDesc;
546	/** Last 8 addresses that caused conflicts. */
547	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
548	/** Number of conflicts for this hypervisor mapping. */
549	uint32_t cConflicts;
550	/** Number of page tables. */
551	uint32_t cPTs;
552
553	/** Array of page table mapping data. Each entry
554	* describes one page table. The array can be longer
555	* than the declared length.
556	*/
557	struct
558	{
559	/** The HC physical address of the page table. */
560	RTHCPHYS HCPhysPT;
561	/** The HC physical address of the first PAE page table. */
562	RTHCPHYS HCPhysPaePT0;
563	/** The HC physical address of the second PAE page table. */
564	RTHCPHYS HCPhysPaePT1;
565	/** The HC virtual address of the 32-bit page table. */
566	R3PTRTYPE(PX86PT) pPTR3;
567	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
568	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
569	/** The R0 virtual address of the 32-bit page table. */
570	R0PTRTYPE(PX86PT) pPTR0;
571	/** The R0 virtual address of the two PAE page table. */
572	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
573	} aPTs[1];
574	} PGMMAPPING;
575	/** Pointer to structure for tracking GC Mappings. */
576	typedef struct PGMMAPPING *PPGMMAPPING;
577
578	#endif /* !PGM_WITHOUT_MAPPINGS */
579
580
581	/**
582	* Physical page access handler type registration.
583	*/
584	typedef struct PGMPHYSHANDLERTYPEINT
585	{
586	/** Number of references. */
587	uint32_t volatile cRefs;
588	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
589	uint32_t u32Magic;
590	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
591	RTLISTOFF32NODE ListNode;
592	/** The kind of accesses we're handling. */
593	PGMPHYSHANDLERKIND enmKind;
594	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
595	uint32_t uState;
596	/** Pointer to R3 callback function. */
597	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
598	/** Pointer to R0 callback function. */
599	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
600	/** Pointer to R0 callback function for \#PFs. */
601	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
602	/** Description / Name. For easing debugging. */
603	R3PTRTYPE(const char *) pszDesc;
604	} PGMPHYSHANDLERTYPEINT;
605	/** Pointer to a physical access handler type registration. */
606	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
607	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
609	/** Magic value for the physical handler callbacks. */
610	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
611
612	/**
613	* Converts a handle to a pointer.
614	* @returns PPGMPHYSHANDLERTYPEINT
615	* @param a_pVM The cross context VM structure.
616	* @param a_hType Physical access handler type handle.
617	*/
618	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
619
620
621	/**
622	* Physical page access handler structure.
623	*
624	* This is used to keep track of physical address ranges
625	* which are being monitored in some kind of way.
626	*/
627	typedef struct PGMPHYSHANDLER
628	{
629	AVLROGCPHYSNODECORE Core;
630	/** Number of pages to update. */
631	uint32_t cPages;
632	/** Set if we have pages that have been aliased. */
633	uint32_t cAliasedPages;
634	/** Set if we have pages that have temporarily been disabled. */
635	uint32_t cTmpOffPages;
636	/** Registered handler type handle (heap offset). */
637	PGMPHYSHANDLERTYPE hType;
638	/** User argument for R3 handlers. */
639	R3PTRTYPE(void *) pvUserR3;
640	/** User argument for R0 handlers. */
641	R0PTRTYPE(void *) pvUserR0;
642	/** Description / Name. For easing debugging. */
643	R3PTRTYPE(const char *) pszDesc;
644	#ifdef VBOX_WITH_STATISTICS
645	/** Profiling of this handler. */
646	STAMPROFILE Stat;
647	#endif
648	} PGMPHYSHANDLER;
649	/** Pointer to a physical page access handler structure. */
650	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
651
652	/**
653	* Gets the type record for a physical handler (no reference added).
654	* @returns PPGMPHYSHANDLERTYPEINT
655	* @param a_pVM The cross context VM structure.
656	* @param a_pPhysHandler Pointer to the physical handler structure
657	* (PGMPHYSHANDLER).
658	*/
659	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
660
661
662	/**
663	* A Physical Guest Page tracking structure.
664	*
665	* The format of this structure is complicated because we have to fit a lot
666	* of information into as few bits as possible. The format is also subject
667	* to change (there is one coming up soon). Which means that for we'll be
668	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
669	* accesses to the structure.
670	*/
671	typedef union PGMPAGE
672	{
673	/** Structured view. */
674	struct
675	{
676	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
677	uint64_t u2HandlerPhysStateY : 2;
678	/** 3:2 - Paging structure needed to map the page
679	* (PGM_PAGE_PDE_TYPE_). /
680	uint64_t u2PDETypeY : 2;
681	/** 4 - Unused (was used by FTE for dirty tracking). */
682	uint64_t fUnused1 : 1;
683	/** 5 - Flag indicating that a write monitored page was written to
684	* when set. */
685	uint64_t fWrittenToY : 1;
686	/** 7:6 - Unused. */
687	uint64_t u2Unused0 : 2;
688	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
689	uint64_t u2Unused1 : 2;
690	/** 11:10 - NEM state bits. */
691	uint64_t u2NemStateY : 2;
692	/** 12:48 - The host physical frame number (shift left to get the
693	* address). */
694	uint64_t HCPhysFN : 36;
695	/** 50:48 - The page state. */
696	uint64_t uStateY : 3;
697	/** 51:53 - The page type (PGMPAGETYPE). */
698	uint64_t uTypeY : 3;
699	/** 63:54 - PTE index for usage tracking (page pool). */
700	uint64_t u10PteIdx : 10;
701
702	/** The GMM page ID.
703	* @remarks In the current implementation, MMIO2 and pages aliased to
704	* MMIO2 pages will be exploiting this field to calculate the
705	* ring-3 mapping address corresponding to the page.
706	* Later we may consider including MMIO2 management into GMM. */
707	uint32_t idPage;
708	/** Usage tracking (page pool). */
709	uint16_t u16TrackingY;
710	/** The number of read locks on this page. */
711	uint8_t cReadLocksY;
712	/** The number of write locks on this page. */
713	uint8_t cWriteLocksY;
714	} s;
715
716	/** 64-bit integer view. */
717	uint64_t au64[2];
718	/** 16-bit view. */
719	uint32_t au32[4];
720	/** 16-bit view. */
721	uint16_t au16[8];
722	/** 8-bit view. */
723	uint8_t au8[16];
724	} PGMPAGE;
725	AssertCompileSize(PGMPAGE, 16);
726	/** Pointer to a physical guest page. */
727	typedef PGMPAGE *PPGMPAGE;
728	/** Pointer to a const physical guest page. */
729	typedef const PGMPAGE *PCPGMPAGE;
730	/** Pointer to a physical guest page pointer. */
731	typedef PPGMPAGE *PPPGMPAGE;
732
733
734	/**
735	* Clears the page structure.
736	* @param a_pPage Pointer to the physical guest page tracking structure.
737	*/
738	#define PGM_PAGE_CLEAR(a_pPage) \
739	do { \
740	(a_pPage)->au64[0] = 0; \
741	(a_pPage)->au64[1] = 0; \
742	} while (0)
743
744	/**
745	* Initializes the page structure.
746	* @param a_pPage Pointer to the physical guest page tracking structure.
747	* @param a_HCPhys The host physical address of the page.
748	* @param a_idPage The (GMM) page ID of the page.
749	* @param a_uType The page type (PGMPAGETYPE).
750	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
751	*/
752	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
753	do { \
754	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
755	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
756	(a_pPage)->au64[0] = SetHCPhysTmp; \
757	(a_pPage)->au64[1] = 0; \
758	(a_pPage)->s.idPage = (a_idPage); \
759	(a_pPage)->s.uStateY = (a_uState); \
760	(a_pPage)->s.uTypeY = (a_uType); \
761	} while (0)
762
763	/**
764	* Initializes the page structure of a ZERO page.
765	* @param a_pPage Pointer to the physical guest page tracking structure.
766	* @param a_pVM The VM handle (for getting the zero page address).
767	* @param a_uType The page type (PGMPAGETYPE).
768	*/
769	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
770	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
771
772
773	/** @name The Page state, PGMPAGE::uStateY.
774	* @{ */
775	/** The zero page.
776	* This is a per-VM page that's never ever mapped writable. */
777	#define PGM_PAGE_STATE_ZERO 0U
778	/** A allocated page.
779	* This is a per-VM page allocated from the page pool (or wherever
780	* we get MMIO2 pages from if the type is MMIO2).
781	*/
782	#define PGM_PAGE_STATE_ALLOCATED 1U
783	/** A allocated page that's being monitored for writes.
784	* The shadow page table mappings are read-only. When a write occurs, the
785	* fWrittenTo member is set, the page remapped as read-write and the state
786	* moved back to allocated. */
787	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
788	/** The page is shared, aka. copy-on-write.
789	* This is a page that's shared with other VMs. */
790	#define PGM_PAGE_STATE_SHARED 3U
791	/** The page is ballooned, so no longer available for this VM. */
792	#define PGM_PAGE_STATE_BALLOONED 4U
793	/** @} */
794
795
796	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
797	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
798	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
799	#else
800	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
801	#endif
802
803	/**
804	* Gets the page state.
805	* @returns page state (PGM_PAGE_STATE_*).
806	* @param a_pPage Pointer to the physical guest page tracking structure.
807	*
808	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
809	* builds.
810	*/
811	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
812	#if defined(__GNUC__) && defined(VBOX_STRICT)
813	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
814	#else
815	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
816	#endif
817
818	/**
819	* Sets the page state.
820	* @param a_pVM The VM handle, only used for lock ownership assertions.
821	* @param a_pPage Pointer to the physical guest page tracking structure.
822	* @param a_uState The new page state.
823	*/
824	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
825	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
826
827
828	/**
829	* Gets the host physical address of the guest page.
830	* @returns host physical address (RTHCPHYS).
831	* @param a_pPage Pointer to the physical guest page tracking structure.
832	*
833	* @remarks In strict builds on gcc platforms, this macro will make some ugly
834	* assumption about a valid pVM variable/parameter being in the
835	* current context. It will use this pVM variable to assert that the
836	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
837	* pVM is not around.
838	*/
839	#if 0
840	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
841	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
842	#else
843	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
844	# if defined(__GNUC__) && defined(VBOX_STRICT)
845	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
846	# else
847	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
848	# endif
849	#endif
850
851	/**
852	* Sets the host physical address of the guest page.
853	*
854	* @param a_pVM The VM handle, only used for lock ownership assertions.
855	* @param a_pPage Pointer to the physical guest page tracking structure.
856	* @param a_HCPhys The new host physical address.
857	*/
858	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
859	do { \
860	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
861	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
862	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
863	PGM_PAGE_ASSERT_LOCK(a_pVM); \
864	} while (0)
865
866	/**
867	* Get the Page ID.
868	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
869	* @param a_pPage Pointer to the physical guest page tracking structure.
870	*/
871	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
872
873	/**
874	* Sets the Page ID.
875	* @param a_pVM The VM handle, only used for lock ownership assertions.
876	* @param a_pPage Pointer to the physical guest page tracking structure.
877	* @param a_idPage The new page ID.
878	*/
879	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
880	do { \
881	(a_pPage)->s.idPage = (a_idPage); \
882	PGM_PAGE_ASSERT_LOCK(a_pVM); \
883	} while (0)
884
885	/**
886	* Get the Chunk ID.
887	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
888	* @param a_pPage Pointer to the physical guest page tracking structure.
889	*/
890	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
891
892	/**
893	* Get the index of the page within the allocation chunk.
894	* @returns The page index.
895	* @param a_pPage Pointer to the physical guest page tracking structure.
896	*/
897	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
898
899	/**
900	* Gets the page type.
901	* @returns The page type.
902	* @param a_pPage Pointer to the physical guest page tracking structure.
903	*
904	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
905	* builds.
906	*/
907	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
908	#if defined(__GNUC__) && defined(VBOX_STRICT)
909	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
910	#else
911	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
912	#endif
913
914	/**
915	* Sets the page type.
916	*
917	* @param a_pVM The VM handle, only used for lock ownership assertions.
918	* @param a_pPage Pointer to the physical guest page tracking structure.
919	* @param a_enmType The new page type (PGMPAGETYPE).
920	*/
921	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
922	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
923
924	/**
925	* Gets the page table index
926	* @returns The page table index.
927	* @param a_pPage Pointer to the physical guest page tracking structure.
928	*/
929	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
930
931	/**
932	* Sets the page table index.
933	* @param a_pVM The VM handle, only used for lock ownership assertions.
934	* @param a_pPage Pointer to the physical guest page tracking structure.
935	* @param a_iPte New page table index.
936	*/
937	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
938	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
939
940	/**
941	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
942	* @returns true/false.
943	* @param a_pPage Pointer to the physical guest page tracking structure.
944	*/
945	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
946
947	/**
948	* Checks if the page is marked for MMIO, including both aliases.
949	* @returns true/false.
950	* @param a_pPage Pointer to the physical guest page tracking structure.
951	*/
952	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
953	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
954	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
955	)
956
957	/**
958	* Checks if the page is marked for MMIO, including special aliases.
959	* @returns true/false.
960	* @param a_pPage Pointer to the physical guest page tracking structure.
961	*/
962	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
963	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
964
965	/**
966	* Checks if the page is a special aliased MMIO page.
967	* @returns true/false.
968	* @param a_pPage Pointer to the physical guest page tracking structure.
969	*/
970	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
971
972	/**
973	* Checks if the page is backed by the ZERO page.
974	* @returns true/false.
975	* @param a_pPage Pointer to the physical guest page tracking structure.
976	*/
977	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
978
979	/**
980	* Checks if the page is backed by a SHARED page.
981	* @returns true/false.
982	* @param a_pPage Pointer to the physical guest page tracking structure.
983	*/
984	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
985
986	/**
987	* Checks if the page is ballooned.
988	* @returns true/false.
989	* @param a_pPage Pointer to the physical guest page tracking structure.
990	*/
991	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
992
993	/**
994	* Checks if the page is allocated.
995	* @returns true/false.
996	* @param a_pPage Pointer to the physical guest page tracking structure.
997	*/
998	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
999
1000	/**
1001	* Marks the page as written to (for GMM change monitoring).
1002	* @param a_pVM The VM handle, only used for lock ownership assertions.
1003	* @param a_pPage Pointer to the physical guest page tracking structure.
1004	*/
1005	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1006	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1007
1008	/**
1009	* Clears the written-to indicator.
1010	* @param a_pVM The VM handle, only used for lock ownership assertions.
1011	* @param a_pPage Pointer to the physical guest page tracking structure.
1012	*/
1013	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1014	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1015
1016	/**
1017	* Checks if the page was marked as written-to.
1018	* @returns true/false.
1019	* @param a_pPage Pointer to the physical guest page tracking structure.
1020	*/
1021	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1022
1023
1024	/** @name PT usage values (PGMPAGE::u2PDEType).
1025	*
1026	* @{ */
1027	/** Either as a PT or PDE. */
1028	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1029	/** Must use a page table to map the range. */
1030	#define PGM_PAGE_PDE_TYPE_PT 1
1031	/** Can use a page directory entry to map the continuous range. */
1032	#define PGM_PAGE_PDE_TYPE_PDE 2
1033	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1034	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1035	/** @} */
1036
1037	/**
1038	* Set the PDE type of the page
1039	* @param a_pVM The VM handle, only used for lock ownership assertions.
1040	* @param a_pPage Pointer to the physical guest page tracking structure.
1041	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1042	*/
1043	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1044	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1045
1046	/**
1047	* Checks if the page was marked being part of a large page
1048	* @returns true/false.
1049	* @param a_pPage Pointer to the physical guest page tracking structure.
1050	*/
1051	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1052
1053	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1054	*
1055	* @remarks The values are assigned in order of priority, so we can calculate
1056	* the correct state for a page with different handlers installed.
1057	* @{ */
1058	/** No handler installed. */
1059	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1060	/** Monitoring is temporarily disabled. */
1061	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1062	/** Write access is monitored. */
1063	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1064	/** All access is monitored. */
1065	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1066	/** @} */
1067
1068	/**
1069	* Gets the physical access handler state of a page.
1070	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1071	* @param a_pPage Pointer to the physical guest page tracking structure.
1072	*/
1073	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1074
1075	/**
1076	* Sets the physical access handler state of a page.
1077	* @param a_pPage Pointer to the physical guest page tracking structure.
1078	* @param a_uState The new state value.
1079	*/
1080	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1081	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1082
1083	/**
1084	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1085	* @returns true/false
1086	* @param a_pPage Pointer to the physical guest page tracking structure.
1087	*/
1088	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1089	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1090
1091	/**
1092	* Checks if the page has any active physical access handlers.
1093	* @returns true/false
1094	* @param a_pPage Pointer to the physical guest page tracking structure.
1095	*/
1096	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1097	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1098
1099	/**
1100	* Checks if the page has any access handlers, including temporarily disabled ones.
1101	* @returns true/false
1102	* @param a_pPage Pointer to the physical guest page tracking structure.
1103	*/
1104	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1105	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1106
1107	/**
1108	* Checks if the page has any active access handlers.
1109	* @returns true/false
1110	* @param a_pPage Pointer to the physical guest page tracking structure.
1111	*/
1112	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1113	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1114
1115	/**
1116	* Checks if the page has any active access handlers catching all accesses.
1117	* @returns true/false
1118	* @param a_pPage Pointer to the physical guest page tracking structure.
1119	*/
1120	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1121	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1122
1123
1124	/** @def PGM_PAGE_GET_TRACKING
1125	* Gets the packed shadow page pool tracking data associated with a guest page.
1126	* @returns uint16_t containing the data.
1127	* @param a_pPage Pointer to the physical guest page tracking structure.
1128	*/
1129	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1130	#if defined(__GNUC__) && defined(VBOX_STRICT)
1131	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1132	#else
1133	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1134	#endif
1135
1136	/** @def PGM_PAGE_SET_TRACKING
1137	* Sets the packed shadow page pool tracking data associated with a guest page.
1138	* @param a_pVM The VM handle, only used for lock ownership assertions.
1139	* @param a_pPage Pointer to the physical guest page tracking structure.
1140	* @param a_u16TrackingData The tracking data to store.
1141	*/
1142	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1143	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1144
1145	/** @def PGM_PAGE_GET_TD_CREFS
1146	* Gets the @a cRefs tracking data member.
1147	* @returns cRefs.
1148	* @param a_pPage Pointer to the physical guest page tracking structure.
1149	*/
1150	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1151	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1152	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1153	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1154
1155	/** @def PGM_PAGE_GET_TD_IDX
1156	* Gets the @a idx tracking data member.
1157	* @returns idx.
1158	* @param a_pPage Pointer to the physical guest page tracking structure.
1159	*/
1160	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1161	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1162	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1163	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1164
1165
1166	/** Max number of locks on a page. */
1167	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1168
1169	/** Get the read lock count.
1170	* @returns count.
1171	* @param a_pPage Pointer to the physical guest page tracking structure.
1172	*/
1173	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1174
1175	/** Get the write lock count.
1176	* @returns count.
1177	* @param a_pPage Pointer to the physical guest page tracking structure.
1178	*/
1179	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1180
1181	/** Decrement the read lock counter.
1182	* @param a_pPage Pointer to the physical guest page tracking structure.
1183	*/
1184	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1185
1186	/** Decrement the write lock counter.
1187	* @param a_pPage Pointer to the physical guest page tracking structure.
1188	*/
1189	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1190
1191	/** Increment the read lock counter.
1192	* @param a_pPage Pointer to the physical guest page tracking structure.
1193	*/
1194	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1195
1196	/** Increment the write lock counter.
1197	* @param a_pPage Pointer to the physical guest page tracking structure.
1198	*/
1199	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1200
1201
1202	/** Gets the NEM state.
1203	* @returns NEM state value (two bits).
1204	* @param a_pPage Pointer to the physical guest page tracking structure.
1205	*/
1206	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1207
1208	/** Sets the NEM state.
1209	* @param a_pPage Pointer to the physical guest page tracking structure.
1210	* @param a_u2State The NEM state value (specific to NEM impl.).
1211	*/
1212	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1213	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1214
1215
1216	#if 0
1217	/** Enables sanity checking of write monitoring using CRC-32. */
1218	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1219	#endif
1220
1221	/**
1222	* Per page live save tracking data.
1223	*/
1224	typedef struct PGMLIVESAVERAMPAGE
1225	{
1226	/** Number of times it has been dirtied. */
1227	uint32_t cDirtied : 24;
1228	/** Whether it is currently dirty. */
1229	uint32_t fDirty : 1;
1230	/** Ignore the page.
1231	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1232	* deal with these after pausing the VM and DevPCI have said it bit about
1233	* remappings. */
1234	uint32_t fIgnore : 1;
1235	/** Was a ZERO page last time around. */
1236	uint32_t fZero : 1;
1237	/** Was a SHARED page last time around. */
1238	uint32_t fShared : 1;
1239	/** Whether the page is/was write monitored in a previous pass. */
1240	uint32_t fWriteMonitored : 1;
1241	/** Whether the page is/was write monitored earlier in this pass. */
1242	uint32_t fWriteMonitoredJustNow : 1;
1243	/** Bits reserved for future use. */
1244	uint32_t u2Reserved : 2;
1245	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1246	/** CRC-32 for the page. This is for internal consistency checks. */
1247	uint32_t u32Crc;
1248	#endif
1249	} PGMLIVESAVERAMPAGE;
1250	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1251	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1252	#else
1253	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1254	#endif
1255	/** Pointer to the per page live save tracking data. */
1256	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1257
1258	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1259	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1260
1261
1262	/**
1263	* RAM range for GC Phys to HC Phys conversion.
1264	*
1265	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1266	* conversions too, but we'll let MM handle that for now.
1267	*
1268	* This structure is used by linked lists in both GC and HC.
1269	*/
1270	typedef struct PGMRAMRANGE
1271	{
1272	/** Start of the range. Page aligned. */
1273	RTGCPHYS GCPhys;
1274	/** Size of the range. (Page aligned of course). */
1275	RTGCPHYS cb;
1276	/** Pointer to the next RAM range - for R3. */
1277	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1278	/** Pointer to the next RAM range - for R0. */
1279	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1280	/** PGM_RAM_RANGE_FLAGS_* flags. */
1281	uint32_t fFlags;
1282	uint32_t fPadding1;
1283	/** Last address in the range (inclusive). Page aligned (-1). */
1284	RTGCPHYS GCPhysLast;
1285	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1286	R3PTRTYPE(void *) pvR3;
1287	/** Live save per page tracking data. */
1288	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1289	/** The range description. */
1290	R3PTRTYPE(const char *) pszDesc;
1291	/** Pointer to self - R0 pointer. */
1292	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1293
1294	/** Pointer to the left search three node - ring-3 context. */
1295	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1296	/** Pointer to the right search three node - ring-3 context. */
1297	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1298	/** Pointer to the left search three node - ring-0 context. */
1299	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1300	/** Pointer to the right search three node - ring-0 context. */
1301	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1302
1303	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1304	#if HC_ARCH_BITS == 32
1305	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1306	#endif
1307	/** Array of physical guest page tracking structures. */
1308	PGMPAGE aPages[1];
1309	} PGMRAMRANGE;
1310	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1311	typedef PGMRAMRANGE *PPGMRAMRANGE;
1312
1313	/** @name PGMRAMRANGE::fFlags
1314	* @{ */
1315	/** The RAM range is floating around as an independent guest mapping. */
1316	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1317	/** Ad hoc RAM range for an ROM mapping. */
1318	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1319	/** Ad hoc RAM range for an MMIO mapping. */
1320	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1321	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1322	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1323	/** @} */
1324
1325	/** Tests if a RAM range is an ad hoc one or not.
1326	* @returns true/false.
1327	* @param pRam The RAM range.
1328	*/
1329	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1330	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1331
1332	/** The number of entries in the RAM range TLBs (there is one for each
1333	* context). Must be a power of two. */
1334	#define PGM_RAMRANGE_TLB_ENTRIES 8
1335
1336	/**
1337	* Calculates the RAM range TLB index for the physical address.
1338	*
1339	* @returns RAM range TLB index.
1340	* @param a_GCPhys The guest physical address.
1341	*/
1342	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1343
1344
1345
1346	/**
1347	* Per page tracking structure for ROM image.
1348	*
1349	* A ROM image may have a shadow page, in which case we may have two pages
1350	* backing it. This structure contains the PGMPAGE for both while
1351	* PGMRAMRANGE have a copy of the active one. It is important that these
1352	* aren't out of sync in any regard other than page pool tracking data.
1353	*/
1354	typedef struct PGMROMPAGE
1355	{
1356	/** The page structure for the virgin ROM page. */
1357	PGMPAGE Virgin;
1358	/** The page structure for the shadow RAM page. */
1359	PGMPAGE Shadow;
1360	/** The current protection setting. */
1361	PGMROMPROT enmProt;
1362	/** Live save status information. Makes use of unused alignment space. */
1363	struct
1364	{
1365	/** The previous protection value. */
1366	uint8_t u8Prot;
1367	/** Written to flag set by the handler. */
1368	bool fWrittenTo;
1369	/** Whether the shadow page is dirty or not. */
1370	bool fDirty;
1371	/** Whether it was dirtied in the recently. */
1372	bool fDirtiedRecently;
1373	} LiveSave;
1374	} PGMROMPAGE;
1375	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1376	/** Pointer to a ROM page tracking structure. */
1377	typedef PGMROMPAGE *PPGMROMPAGE;
1378
1379
1380	/**
1381	* A registered ROM image.
1382	*
1383	* This is needed to keep track of ROM image since they generally intrude
1384	* into a PGMRAMRANGE. It also keeps track of additional info like the
1385	* two page sets (read-only virgin and read-write shadow), the current
1386	* state of each page.
1387	*
1388	* Because access handlers cannot easily be executed in a different
1389	* context, the ROM ranges needs to be accessible and in all contexts.
1390	*/
1391	typedef struct PGMROMRANGE
1392	{
1393	/** Pointer to the next range - R3. */
1394	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1395	/** Pointer to the next range - R0. */
1396	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1397	/** Address of the range. */
1398	RTGCPHYS GCPhys;
1399	/** Address of the last byte in the range. */
1400	RTGCPHYS GCPhysLast;
1401	/** Size of the range. */
1402	RTGCPHYS cb;
1403	/** The flags (PGMPHYS_ROM_FLAGS_). /
1404	uint32_t fFlags;
1405	/** The saved state range ID. */
1406	uint8_t idSavedState;
1407	/** Alignment padding. */
1408	uint8_t au8Alignment[3];
1409	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1410	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1411	/** The size bits pvOriginal points to. */
1412	uint32_t cbOriginal;
1413	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1414	* This is used for strictness checks. */
1415	R3PTRTYPE(const void *) pvOriginal;
1416	/** The ROM description. */
1417	R3PTRTYPE(const char *) pszDesc;
1418	/** The per page tracking structures. */
1419	PGMROMPAGE aPages[1];
1420	} PGMROMRANGE;
1421	/** Pointer to a ROM range. */
1422	typedef PGMROMRANGE *PPGMROMRANGE;
1423
1424
1425	/**
1426	* Live save per page data for an MMIO2 page.
1427	*
1428	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1429	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1430	* CRC-32 for detecting changes as well as special handling of zero pages. This
1431	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1432	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1433	* because of speed (2.5x and 6x slower).)
1434	*
1435	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1436	* save but normally is disabled. Since we can write monitor guest
1437	* accesses on our own, we only need this for host accesses. Shouldn't be
1438	* too difficult for DevVGA, VMMDev might be doable, the planned
1439	* networking fun will be fun since it involves ring-0.
1440	*/
1441	typedef struct PGMLIVESAVEMMIO2PAGE
1442	{
1443	/** Set if the page is considered dirty. */
1444	bool fDirty;
1445	/** The number of scans this page has remained unchanged for.
1446	* Only updated for dirty pages. */
1447	uint8_t cUnchangedScans;
1448	/** Whether this page was zero at the last scan. */
1449	bool fZero;
1450	/** Alignment padding. */
1451	bool fReserved;
1452	/** CRC-32 for the first half of the page.
1453	* This is used together with u32CrcH2 to quickly detect changes in the page
1454	* during the non-final passes. */
1455	uint32_t u32CrcH1;
1456	/** CRC-32 for the second half of the page. */
1457	uint32_t u32CrcH2;
1458	/** SHA-1 for the saved page.
1459	* This is used in the final pass to skip pages without changes. */
1460	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1461	} PGMLIVESAVEMMIO2PAGE;
1462	/** Pointer to a live save status data for an MMIO2 page. */
1463	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1464
1465	/**
1466	* A registered MMIO2 (= Device RAM) range.
1467	*
1468	* There are a few reason why we need to keep track of these registrations. One
1469	* of them is the deregistration & cleanup stuff, while another is that the
1470	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1471	* range list.
1472	*
1473	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1474	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1475	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1476	* overlap we will free all the existing RAM pages and put in the ram range
1477	* pages instead.
1478	*/
1479	typedef struct PGMREGMMIO2RANGE
1480	{
1481	/** The owner of the range. (a device) */
1482	PPDMDEVINSR3 pDevInsR3;
1483	/** Pointer to the ring-3 mapping of the allocation. */
1484	RTR3PTR pvR3;
1485	#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1486	/** Pointer to the ring-0 mapping of the allocation. */
1487	RTR0PTR pvR0;
1488	#endif
1489	/** Pointer to the next range - R3. */
1490	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1491	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1492	uint16_t fFlags;
1493	/** The sub device number (internal PCI config (CFGM) number). */
1494	uint8_t iSubDev;
1495	/** The PCI region number. */
1496	uint8_t iRegion;
1497	/** The saved state range ID. */
1498	uint8_t idSavedState;
1499	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1500	uint8_t idMmio2;
1501	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1502	#if defined(VBOX_WITH_RAM_IN_KERNEL) && !defined(VBOX_WITH_LINEAR_HOST_PHYS_MEM)
1503	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1504	#else
1505	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1506	#endif
1507	/** The real size.
1508	* This may be larger than indicated by RamRange.cb if the range has been
1509	* reduced during saved state loading. */
1510	RTGCPHYS cbReal;
1511	/** Pointer to the physical handler for MMIO. */
1512	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1513	/** Live save per page tracking data for MMIO2. */
1514	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1515	/** The associated RAM range. */
1516	PGMRAMRANGE RamRange;
1517	} PGMREGMMIO2RANGE;
1518	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1519	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1520	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1521
1522	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1523	* @{ */
1524	/** Set if it's an MMIO2 range.
1525	* @note Historical. For a while we did some of the MMIO this way too. */
1526	#define PGMREGMMIO2RANGE_F_MMIO2 UINT16_C(0x0001)
1527	/** Set if this is the first chunk in the MMIO2 range. */
1528	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1529	/** Set if this is the last chunk in the MMIO2 range. */
1530	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0004)
1531	/** Set if the whole range is mapped. */
1532	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0008)
1533	/** Set if it's overlapping, clear if not. */
1534	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0010)
1535	/** @} */
1536
1537
1538	/** @name Internal MMIO2 constants.
1539	* @{ */
1540	/** The maximum number of MMIO2 ranges. */
1541	#define PGM_MMIO2_MAX_RANGES 32
1542	/** The maximum number of pages in a MMIO2 range. */
1543	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1544	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1545	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1546	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1547	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1548	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1549	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1550	/** @} */
1551
1552
1553
1554	/**
1555	* PGMPhysRead/Write cache entry
1556	*/
1557	typedef struct PGMPHYSCACHEENTRY
1558	{
1559	/** R3 pointer to physical page. */
1560	R3PTRTYPE(uint8_t *) pbR3;
1561	/** GC Physical address for cache entry */
1562	RTGCPHYS GCPhys;
1563	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1564	RTGCPHYS u32Padding0; /*< alignment padding. /
1565	#endif
1566	} PGMPHYSCACHEENTRY;
1567
1568	/**
1569	* PGMPhysRead/Write cache to reduce REM memory access overhead
1570	*/
1571	typedef struct PGMPHYSCACHE
1572	{
1573	/** Bitmap of valid cache entries */
1574	uint64_t aEntries;
1575	/** Cache entries */
1576	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1577	} PGMPHYSCACHE;
1578
1579
1580	/** @name Ring-3 page mapping TLBs
1581	* @{ */
1582
1583	/** Pointer to an allocation chunk ring-3 mapping. */
1584	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1585	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1586	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1587
1588	/**
1589	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1590	*
1591	* The primary tree (Core) uses the chunk id as key.
1592	*/
1593	typedef struct PGMCHUNKR3MAP
1594	{
1595	/** The key is the chunk id. */
1596	AVLU32NODECORE Core;
1597	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1598	* selection. */
1599	uint32_t iLastUsed;
1600	/** The current reference count. */
1601	uint32_t volatile cRefs;
1602	/** The current permanent reference count. */
1603	uint32_t volatile cPermRefs;
1604	/** The mapping address. */
1605	void *pv;
1606	} PGMCHUNKR3MAP;
1607
1608	/**
1609	* Allocation chunk ring-3 mapping TLB entry.
1610	*/
1611	typedef struct PGMCHUNKR3MAPTLBE
1612	{
1613	/** The chunk id. */
1614	uint32_t volatile idChunk;
1615	#if HC_ARCH_BITS == 64
1616	uint32_t u32Padding; /*< alignment padding. /
1617	#endif
1618	/** The chunk map. */
1619	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1620	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1621	#else
1622	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1623	#endif
1624	} PGMCHUNKR3MAPTLBE;
1625	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1626	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1627
1628	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1629	* @remark Must be a power of two value. */
1630	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1631
1632	/**
1633	* Allocation chunk ring-3 mapping TLB.
1634	*
1635	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1636	* At first glance this might look kinda odd since AVL trees are
1637	* supposed to give the most optimal lookup times of all trees
1638	* due to their balancing. However, take a tree with 1023 nodes
1639	* in it, that's 10 levels, meaning that most searches has to go
1640	* down 9 levels before they find what they want. This isn't fast
1641	* compared to a TLB hit. There is the factor of cache misses,
1642	* and of course the problem with trees and branch prediction.
1643	* This is why we use TLBs in front of most of the trees.
1644	*
1645	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1646	* difficult when we switch to the new inlined AVL trees (from kStuff).
1647	*/
1648	typedef struct PGMCHUNKR3MAPTLB
1649	{
1650	/** The TLB entries. */
1651	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1652	} PGMCHUNKR3MAPTLB;
1653
1654	/**
1655	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1656	* @returns Chunk TLB index.
1657	* @param idChunk The Chunk ID.
1658	*/
1659	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1660
1661
1662	/**
1663	* Ring-3 guest page mapping TLB entry.
1664	* @remarks used in ring-0 as well at the moment.
1665	*/
1666	typedef struct PGMPAGER3MAPTLBE
1667	{
1668	/** Address of the page. */
1669	RTGCPHYS volatile GCPhys;
1670	/** The guest page. */
1671	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1672	R3PTRTYPE(PPGMPAGE) volatile pPage;
1673	#else
1674	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1675	#endif
1676	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1677	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1678	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1679	#else
1680	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1681	#endif
1682	/** The address */
1683	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
1684	R3PTRTYPE(void *) volatile pv;
1685	#else
1686	R3R0PTRTYPE(void *) volatile pv;
1687	#endif
1688	#if HC_ARCH_BITS == 32
1689	uint32_t u32Padding; /*< alignment padding. /
1690	#endif
1691	} PGMPAGER3MAPTLBE;
1692	/** Pointer to an entry in the HC physical TLB. */
1693	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1694
1695
1696	/** The number of entries in the ring-3 guest page mapping TLB.
1697	* @remarks The value must be a power of two. */
1698	#define PGM_PAGER3MAPTLB_ENTRIES 256
1699
1700	/**
1701	* Ring-3 guest page mapping TLB.
1702	* @remarks used in ring-0 as well at the moment.
1703	*/
1704	typedef struct PGMPAGER3MAPTLB
1705	{
1706	/** The TLB entries. */
1707	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1708	} PGMPAGER3MAPTLB;
1709	/** Pointer to the ring-3 guest page mapping TLB. */
1710	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1711
1712	/**
1713	* Calculates the index of the TLB entry for the specified guest page.
1714	* @returns Physical TLB index.
1715	* @param GCPhys The guest physical address.
1716	*/
1717	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1718
1719	/** @} */
1720
1721	#if defined(VBOX_WITH_RAM_IN_KERNEL) \|\| defined(DOXYGEN_RUNNING)
1722	/** @name Ring-0 page mapping TLB
1723	* @{ */
1724	/**
1725	* Ring-0 guest page mapping TLB entry.
1726	*/
1727	typedef struct PGMPAGER0MAPTLBE
1728	{
1729	/** Address of the page. */
1730	RTGCPHYS volatile GCPhys;
1731	/** The guest page. */
1732	R0PTRTYPE(PPGMPAGE) volatile pPage;
1733	/** The address */
1734	R0PTRTYPE(void *) volatile pv;
1735	} PGMPAGER0MAPTLBE;
1736	/** Pointer to an entry in the HC physical TLB. */
1737	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1738
1739
1740	/** The number of entries in the ring-3 guest page mapping TLB.
1741	* @remarks The value must be a power of two. */
1742	#define PGM_PAGER0MAPTLB_ENTRIES 256
1743
1744	/**
1745	* Ring-3 guest page mapping TLB.
1746	* @remarks used in ring-0 as well at the moment.
1747	*/
1748	typedef struct PGMPAGER0MAPTLB
1749	{
1750	/** The TLB entries. */
1751	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1752	} PGMPAGER0MAPTLB;
1753	/** Pointer to the ring-3 guest page mapping TLB. */
1754	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1755
1756	/**
1757	* Calculates the index of the TLB entry for the specified guest page.
1758	* @returns Physical TLB index.
1759	* @param GCPhys The guest physical address.
1760	*/
1761	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1762	/** @} */
1763	#endif /* VBOX_WITH_RAM_IN_KERNEL \|\| DOXYGEN_RUNNING */
1764
1765	/**
1766	* Raw-mode context dynamic mapping cache entry.
1767	*
1768	* Because of raw-mode context being reloctable and all relocations are applied
1769	* in ring-3, this has to be defined here and be RC specific.
1770	*
1771	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1772	*/
1773	typedef struct PGMRCDYNMAPENTRY
1774	{
1775	/** The physical address of the currently mapped page.
1776	* This is duplicate for three reasons: cache locality, cache policy of the PT
1777	* mappings and sanity checks. */
1778	RTHCPHYS HCPhys;
1779	/** Pointer to the page. */
1780	RTRCPTR pvPage;
1781	/** The number of references. */
1782	int32_t volatile cRefs;
1783	/** PTE pointer union. */
1784	struct PGMRCDYNMAPENTRY_PPTE
1785	{
1786	/** PTE pointer, 32-bit legacy version. */
1787	RCPTRTYPE(PX86PTE) pLegacy;
1788	/** PTE pointer, PAE version. */
1789	RCPTRTYPE(PX86PTEPAE) pPae;
1790	} uPte;
1791	} PGMRCDYNMAPENTRY;
1792	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1793	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1794
1795
1796	/**
1797	* Dynamic mapping cache for the raw-mode context.
1798	*
1799	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1800	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1801	* so that we can perform relocations from PGMR3Relocate. This has the
1802	* consequence that we must have separate ring-0 and raw-mode context versions
1803	* of this struct even if they share the basic elements.
1804	*
1805	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1806	*/
1807	typedef struct PGMRCDYNMAP
1808	{
1809	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1810	uint32_t u32Magic;
1811	/** Array for tracking and managing the pages. */
1812	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1813	/** The cache size given as a number of pages. */
1814	uint32_t cPages;
1815	/** The current load.
1816	* This does not include guard pages. */
1817	uint32_t cLoad;
1818	/** The max load ever.
1819	* This is maintained to get trigger adding of more mapping space. */
1820	uint32_t cMaxLoad;
1821	/** The number of guard pages. */
1822	uint32_t cGuardPages;
1823	/** The number of users (protected by hInitLock). */
1824	uint32_t cUsers;
1825	} PGMRCDYNMAP;
1826	/** Pointer to the dynamic cache for the raw-mode context. */
1827	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1828
1829
1830	/**
1831	* Mapping cache usage set entry.
1832	*
1833	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1834	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1835	* cache. If it's extended to include ring-3, well, then something
1836	* will have be changed here...
1837	*/
1838	typedef struct PGMMAPSETENTRY
1839	{
1840	/** Pointer to the page. */
1841	RTR0PTR pvPage;
1842	/** The mapping cache index. */
1843	uint16_t iPage;
1844	/** The number of references.
1845	* The max is UINT16_MAX - 1. */
1846	uint16_t cRefs;
1847	/** The number inlined references.
1848	* The max is UINT16_MAX - 1. */
1849	uint16_t cInlinedRefs;
1850	/** Unreferences. */
1851	uint16_t cUnrefs;
1852
1853	#if HC_ARCH_BITS == 32
1854	uint32_t u32Alignment1;
1855	#endif
1856	/** The physical address for this entry. */
1857	RTHCPHYS HCPhys;
1858	} PGMMAPSETENTRY;
1859	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1860	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1861	/** Pointer to a mapping cache usage set entry. */
1862	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1863
1864	/**
1865	* Mapping cache usage set.
1866	*
1867	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1868	* done during exits / traps. The set is
1869	*/
1870	typedef struct PGMMAPSET
1871	{
1872	/** The number of occupied entries.
1873	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1874	* dynamic mappings. */
1875	uint32_t cEntries;
1876	/** The start of the current subset.
1877	* This is UINT32_MAX if no subset is currently open. */
1878	uint32_t iSubset;
1879	/** The index of the current CPU, only valid if the set is open. */
1880	int32_t iCpu;
1881	uint32_t alignment;
1882	/** The entries. */
1883	PGMMAPSETENTRY aEntries[64];
1884	/** HCPhys -> iEntry fast lookup table.
1885	* Use PGMMAPSET_HASH for hashing.
1886	* The entries may or may not be valid, check against cEntries. */
1887	uint8_t aiHashTable[128];
1888	} PGMMAPSET;
1889	AssertCompileSizeAlignment(PGMMAPSET, 8);
1890	/** Pointer to the mapping cache set. */
1891	typedef PGMMAPSET *PPGMMAPSET;
1892
1893	/** PGMMAPSET::cEntries value for a closed set. */
1894	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1895
1896	/** Hash function for aiHashTable. */
1897	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1898
1899
1900	/** @name Context neutral page mapper TLB.
1901	*
1902	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1903	* code is writting in a kind of context neutral way. Time will show whether
1904	* this actually makes sense or not...
1905	*
1906	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1907	* context ends up using a global mapping cache on some platforms
1908	* (darwin).
1909	*
1910	* @{ */
1911	/** @typedef PPGMPAGEMAPTLB
1912	* The page mapper TLB pointer type for the current context. */
1913	/** @typedef PPGMPAGEMAPTLB
1914	* The page mapper TLB entry pointer type for the current context. */
1915	/** @typedef PPGMPAGEMAPTLB
1916	* The page mapper TLB entry pointer pointer type for the current context. */
1917	/** @def PGM_PAGEMAPTLB_ENTRIES
1918	* The number of TLB entries in the page mapper TLB for the current context. */
1919	/** @def PGM_PAGEMAPTLB_IDX
1920	* Calculate the TLB index for a guest physical address.
1921	* @returns The TLB index.
1922	* @param GCPhys The guest physical address. */
1923	/** @typedef PPGMPAGEMAP
1924	* Pointer to a page mapper unit for current context. */
1925	/** @typedef PPPGMPAGEMAP
1926	* Pointer to a page mapper unit pointer for current context. */
1927	#if defined(IN_RING0) && defined(VBOX_WITH_RAM_IN_KERNEL)
1928	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1929	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1930	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1931	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1932	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1933	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1934	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1935	#else
1936	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1937	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1938	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1939	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1940	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1941	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1942	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1943	#endif
1944	/** @} */
1945
1946
1947	/** @name PGM Pool Indexes.
1948	* Aka. the unique shadow page identifier.
1949	* @{ */
1950	/** NIL page pool IDX. */
1951	#define NIL_PGMPOOL_IDX 0
1952	/** The first normal index. There used to be 5 fictive pages up front, now
1953	* there is only the NIL page. */
1954	#define PGMPOOL_IDX_FIRST 1
1955	/** The last valid index. (inclusive, 14 bits) */
1956	#define PGMPOOL_IDX_LAST 0x3fff
1957	/** @} */
1958
1959	/** The NIL index for the parent chain. */
1960	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1961	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1962
1963	/**
1964	* Node in the chain linking a shadowed page to it's parent (user).
1965	*/
1966	#pragma pack(1)
1967	typedef struct PGMPOOLUSER
1968	{
1969	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1970	uint16_t iNext;
1971	/** The user page index. */
1972	uint16_t iUser;
1973	/** Index into the user table. */
1974	uint32_t iUserTable;
1975	} PGMPOOLUSER, *PPGMPOOLUSER;
1976	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1977	#pragma pack()
1978
1979
1980	/** The NIL index for the phys ext chain. */
1981	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1982	/** The NIL pte index for a phys ext chain slot. */
1983	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1984
1985	/**
1986	* Node in the chain of physical cross reference extents.
1987	* @todo Calling this an 'extent' is not quite right, find a better name.
1988	* @todo find out the optimal size of the aidx array
1989	*/
1990	#pragma pack(1)
1991	typedef struct PGMPOOLPHYSEXT
1992	{
1993	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1994	uint16_t iNext;
1995	/** Alignment. */
1996	uint16_t u16Align;
1997	/** The user page index. */
1998	uint16_t aidx[3];
1999	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2000	uint16_t apte[3];
2001	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2002	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2003	#pragma pack()
2004
2005
2006	/**
2007	* The kind of page that's being shadowed.
2008	*/
2009	typedef enum PGMPOOLKIND
2010	{
2011	/** The virtual invalid 0 entry. */
2012	PGMPOOLKIND_INVALID = 0,
2013	/** The entry is free (=unused). */
2014	PGMPOOLKIND_FREE,
2015
2016	/** Shw: 32-bit page table; Gst: no paging. */
2017	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2018	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2019	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2020	/** Shw: 32-bit page table; Gst: 4MB page. */
2021	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2022	/** Shw: PAE page table; Gst: no paging. */
2023	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2024	/** Shw: PAE page table; Gst: 32-bit page table. */
2025	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2026	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2027	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2028	/** Shw: PAE page table; Gst: PAE page table. */
2029	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2030	/** Shw: PAE page table; Gst: 2MB page. */
2031	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2032
2033	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2034	PGMPOOLKIND_32BIT_PD,
2035	/** Shw: 32-bit page directory. Gst: no paging. */
2036	PGMPOOLKIND_32BIT_PD_PHYS,
2037	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2038	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2039	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2040	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2041	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2042	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2043	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2044	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2045	/** Shw: PAE page directory; Gst: PAE page directory. */
2046	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2047	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2048	PGMPOOLKIND_PAE_PD_PHYS,
2049
2050	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2051	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2052	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2053	PGMPOOLKIND_PAE_PDPT,
2054	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2055	PGMPOOLKIND_PAE_PDPT_PHYS,
2056
2057	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2058	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2059	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2060	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2061	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2062	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2063	/** Shw: 64-bit page directory table; Gst: no paging. */
2064	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2065
2066	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2067	PGMPOOLKIND_64BIT_PML4,
2068
2069	/** Shw: EPT page directory pointer table; Gst: no paging. */
2070	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2071	/** Shw: EPT page directory table; Gst: no paging. */
2072	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2073	/** Shw: EPT page table; Gst: no paging. */
2074	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2075
2076	/** Shw: Root Nested paging table. */
2077	PGMPOOLKIND_ROOT_NESTED,
2078
2079	/** The last valid entry. */
2080	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2081	} PGMPOOLKIND;
2082
2083	/**
2084	* The access attributes of the page; only applies to big pages.
2085	*/
2086	typedef enum
2087	{
2088	PGMPOOLACCESS_DONTCARE = 0,
2089	PGMPOOLACCESS_USER_RW,
2090	PGMPOOLACCESS_USER_R,
2091	PGMPOOLACCESS_USER_RW_NX,
2092	PGMPOOLACCESS_USER_R_NX,
2093	PGMPOOLACCESS_SUPERVISOR_RW,
2094	PGMPOOLACCESS_SUPERVISOR_R,
2095	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2096	PGMPOOLACCESS_SUPERVISOR_R_NX
2097	} PGMPOOLACCESS;
2098
2099	/**
2100	* The tracking data for a page in the pool.
2101	*/
2102	typedef struct PGMPOOLPAGE
2103	{
2104	/** AVL node code with the (HC) physical address of this page. */
2105	AVLOHCPHYSNODECORE Core;
2106	/** Pointer to the R3 mapping of the page. */
2107	R3PTRTYPE(void *) pvPageR3;
2108	/** Pointer to the R0 mapping of the page. */
2109	R0PTRTYPE(void *) pvPageR0;
2110	/** The guest physical address. */
2111	RTGCPHYS GCPhys;
2112	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2113	uint8_t enmKind;
2114	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2115	uint8_t enmAccess;
2116	/** This supplements enmKind and enmAccess */
2117	bool fA20Enabled : 1;
2118
2119	/** Used to indicate that the page is zeroed. */
2120	bool fZeroed : 1;
2121	/** Used to indicate that a PT has non-global entries. */
2122	bool fSeenNonGlobal : 1;
2123	/** Used to indicate that we're monitoring writes to the guest page. */
2124	bool fMonitored : 1;
2125	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2126	* (All pages are in the age list.) */
2127	bool fCached : 1;
2128	/** This is used by the R3 access handlers when invoked by an async thread.
2129	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2130	bool volatile fReusedFlushPending : 1;
2131	/** Used to mark the page as dirty (write monitoring is temporarily
2132	* off). */
2133	bool fDirty : 1;
2134	bool fPadding1 : 1;
2135	bool fPadding2;
2136
2137	/** The index of this page. */
2138	uint16_t idx;
2139	/** The next entry in the list this page currently resides in.
2140	* It's either in the free list or in the GCPhys hash. */
2141	uint16_t iNext;
2142	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2143	uint16_t iUserHead;
2144	/** The number of present entries. */
2145	uint16_t cPresent;
2146	/** The first entry in the table which is present. */
2147	uint16_t iFirstPresent;
2148	/** The number of modifications to the monitored page. */
2149	uint16_t cModifications;
2150	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2151	uint16_t iModifiedNext;
2152	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2153	uint16_t iModifiedPrev;
2154	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2155	uint16_t iMonitoredNext;
2156	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2157	uint16_t iMonitoredPrev;
2158	/** The next page in the age list. */
2159	uint16_t iAgeNext;
2160	/** The previous page in the age list. */
2161	uint16_t iAgePrev;
2162	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2163	uint8_t idxDirtyEntry;
2164
2165	/** @name Access handler statistics to determine whether the guest is
2166	* (re)initializing a page table.
2167	* @{ */
2168	RTGCPTR GCPtrLastAccessHandlerRip;
2169	RTGCPTR GCPtrLastAccessHandlerFault;
2170	uint64_t cLastAccessHandler;
2171	/** @} */
2172	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2173	uint32_t volatile cLocked;
2174	#if GC_ARCH_BITS == 64
2175	uint32_t u32Alignment3;
2176	#endif
2177	# ifdef VBOX_STRICT
2178	RTGCPTR GCPtrDirtyFault;
2179	# endif
2180	} PGMPOOLPAGE;
2181	/** Pointer to a pool page. */
2182	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2183	/** Pointer to a const pool page. */
2184	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2185	/** Pointer to a pool page pointer. */
2186	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2187
2188
2189	/** The hash table size. */
2190	# define PGMPOOL_HASH_SIZE 0x40
2191	/** The hash function. */
2192	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2193
2194
2195	/**
2196	* The shadow page pool instance data.
2197	*
2198	* It's all one big allocation made at init time, except for the
2199	* pages that is. The user nodes follows immediately after the
2200	* page structures.
2201	*/
2202	typedef struct PGMPOOL
2203	{
2204	/** The VM handle - R3 Ptr. */
2205	PVMR3 pVMR3;
2206	/** The VM handle - R0 Ptr. */
2207	R0PTRTYPE(PVMCC) pVMR0;
2208	/** The max pool size. This includes the special IDs. */
2209	uint16_t cMaxPages;
2210	/** The current pool size. */
2211	uint16_t cCurPages;
2212	/** The head of the free page list. */
2213	uint16_t iFreeHead;
2214	/* Padding. */
2215	uint16_t u16Padding;
2216	/** Head of the chain of free user nodes. */
2217	uint16_t iUserFreeHead;
2218	/** The number of user nodes we've allocated. */
2219	uint16_t cMaxUsers;
2220	/** The number of present page table entries in the entire pool. */
2221	uint32_t cPresent;
2222	/** Pointer to the array of user nodes - R3 pointer. */
2223	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2224	/** Pointer to the array of user nodes - R0 pointer. */
2225	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2226	/** Head of the chain of free phys ext nodes. */
2227	uint16_t iPhysExtFreeHead;
2228	/** The number of user nodes we've allocated. */
2229	uint16_t cMaxPhysExts;
2230	uint32_t u32Padding0b;
2231	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2232	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2233	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2234	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2235	/** Hash table for GCPhys addresses. */
2236	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2237	/** The head of the age list. */
2238	uint16_t iAgeHead;
2239	/** The tail of the age list. */
2240	uint16_t iAgeTail;
2241	/** Set if the cache is enabled. */
2242	bool fCacheEnabled;
2243	/** Alignment padding. */
2244	bool afPadding1[3];
2245	/** Head of the list of modified pages. */
2246	uint16_t iModifiedHead;
2247	/** The current number of modified pages. */
2248	uint16_t cModifiedPages;
2249	/** Physical access handler type registration handle. */
2250	PGMPHYSHANDLERTYPE hAccessHandlerType;
2251	/** Next available slot (in aDirtyPages). */
2252	uint32_t idxFreeDirtyPage;
2253	/** Number of active dirty pages. */
2254	uint32_t cDirtyPages;
2255	/** Array of current dirty pgm pool page indices. */
2256	uint16_t aidxDirtyPages[16];
2257	/** Array running in parallel to aidxDirtyPages with the page data. */
2258	struct
2259	{
2260	uint64_t aPage[512];
2261	} aDirtyPages[16];
2262
2263	/** The number of pages currently in use. */
2264	uint16_t cUsedPages;
2265	#ifdef VBOX_WITH_STATISTICS
2266	/** The high water mark for cUsedPages. */
2267	uint16_t cUsedPagesHigh;
2268	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2269	/** Profiling pgmPoolAlloc(). */
2270	STAMPROFILEADV StatAlloc;
2271	/** Profiling pgmR3PoolClearDoIt(). */
2272	STAMPROFILE StatClearAll;
2273	/** Profiling pgmR3PoolReset(). */
2274	STAMPROFILE StatR3Reset;
2275	/** Profiling pgmPoolFlushPage(). */
2276	STAMPROFILE StatFlushPage;
2277	/** Profiling pgmPoolFree(). */
2278	STAMPROFILE StatFree;
2279	/** Counting explicit flushes by PGMPoolFlushPage(). */
2280	STAMCOUNTER StatForceFlushPage;
2281	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2282	STAMCOUNTER StatForceFlushDirtyPage;
2283	/** Counting flushes for reused pages. */
2284	STAMCOUNTER StatForceFlushReused;
2285	/** Profiling time spent zeroing pages. */
2286	STAMPROFILE StatZeroPage;
2287	/** Profiling of pgmPoolTrackDeref. */
2288	STAMPROFILE StatTrackDeref;
2289	/** Profiling pgmTrackFlushGCPhysPT. */
2290	STAMPROFILE StatTrackFlushGCPhysPT;
2291	/** Profiling pgmTrackFlushGCPhysPTs. */
2292	STAMPROFILE StatTrackFlushGCPhysPTs;
2293	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2294	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2295	/** Number of times we've been out of user records. */
2296	STAMCOUNTER StatTrackFreeUpOneUser;
2297	/** Nr of flushed entries. */
2298	STAMCOUNTER StatTrackFlushEntry;
2299	/** Nr of updated entries. */
2300	STAMCOUNTER StatTrackFlushEntryKeep;
2301	/** Profiling deref activity related tracking GC physical pages. */
2302	STAMPROFILE StatTrackDerefGCPhys;
2303	/** Number of linear searches for a HCPhys in the ram ranges. */
2304	STAMCOUNTER StatTrackLinearRamSearches;
2305	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2306	STAMCOUNTER StamTrackPhysExtAllocFailures;
2307
2308	/** Profiling the RC/R0 \#PF access handler. */
2309	STAMPROFILE StatMonitorPfRZ;
2310	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2311	STAMPROFILE StatMonitorPfRZHandled;
2312	/** Times we've failed interpreting the instruction. */
2313	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2314	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2315	STAMPROFILE StatMonitorPfRZFlushPage;
2316	/** Times we've detected a page table reinit. */
2317	STAMCOUNTER StatMonitorPfRZFlushReinit;
2318	/** Counting flushes for pages that are modified too often. */
2319	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2320	/** Times we've detected fork(). */
2321	STAMCOUNTER StatMonitorPfRZFork;
2322	/** Times we've failed interpreting a patch code instruction. */
2323	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2324	/** Times we've failed interpreting a patch code instruction during flushing. */
2325	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2326	/** The number of times we've seen rep prefixes we can't handle. */
2327	STAMCOUNTER StatMonitorPfRZRepPrefix;
2328	/** Profiling the REP STOSD cases we've handled. */
2329	STAMPROFILE StatMonitorPfRZRepStosd;
2330
2331	/** Profiling the R0/RC regular access handler. */
2332	STAMPROFILE StatMonitorRZ;
2333	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2334	STAMPROFILE StatMonitorRZFlushPage;
2335	/** Per access size counts indexed by size minus 1, last for larger. */
2336	STAMCOUNTER aStatMonitorRZSizes[16+3];
2337	/** Missaligned access counts indexed by offset - 1. */
2338	STAMCOUNTER aStatMonitorRZMisaligned[7];
2339
2340	/** Nr of handled PT faults. */
2341	STAMCOUNTER StatMonitorRZFaultPT;
2342	/** Nr of handled PD faults. */
2343	STAMCOUNTER StatMonitorRZFaultPD;
2344	/** Nr of handled PDPT faults. */
2345	STAMCOUNTER StatMonitorRZFaultPDPT;
2346	/** Nr of handled PML4 faults. */
2347	STAMCOUNTER StatMonitorRZFaultPML4;
2348
2349	/** Profiling the R3 access handler. */
2350	STAMPROFILE StatMonitorR3;
2351	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2352	STAMPROFILE StatMonitorR3FlushPage;
2353	/** Per access size counts indexed by size minus 1, last for larger. */
2354	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2355	/** Missaligned access counts indexed by offset - 1. */
2356	STAMCOUNTER aStatMonitorR3Misaligned[7];
2357	/** Nr of handled PT faults. */
2358	STAMCOUNTER StatMonitorR3FaultPT;
2359	/** Nr of handled PD faults. */
2360	STAMCOUNTER StatMonitorR3FaultPD;
2361	/** Nr of handled PDPT faults. */
2362	STAMCOUNTER StatMonitorR3FaultPDPT;
2363	/** Nr of handled PML4 faults. */
2364	STAMCOUNTER StatMonitorR3FaultPML4;
2365
2366	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2367	STAMCOUNTER StatResetDirtyPages;
2368	/** Times we've called pgmPoolAddDirtyPage. */
2369	STAMCOUNTER StatDirtyPage;
2370	/** Times we've had to flush duplicates for dirty page management. */
2371	STAMCOUNTER StatDirtyPageDupFlush;
2372	/** Times we've had to flush because of overflow. */
2373	STAMCOUNTER StatDirtyPageOverFlowFlush;
2374
2375	/** The high water mark for cModifiedPages. */
2376	uint16_t cModifiedPagesHigh;
2377	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2378
2379	/** The number of cache hits. */
2380	STAMCOUNTER StatCacheHits;
2381	/** The number of cache misses. */
2382	STAMCOUNTER StatCacheMisses;
2383	/** The number of times we've got a conflict of 'kind' in the cache. */
2384	STAMCOUNTER StatCacheKindMismatches;
2385	/** Number of times we've been out of pages. */
2386	STAMCOUNTER StatCacheFreeUpOne;
2387	/** The number of cacheable allocations. */
2388	STAMCOUNTER StatCacheCacheable;
2389	/** The number of uncacheable allocations. */
2390	STAMCOUNTER StatCacheUncacheable;
2391	#else
2392	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2393	#endif
2394	/** Profiling PGMR0PoolGrow(). */
2395	STAMPROFILE StatGrow;
2396	/** The AVL tree for looking up a page by its HC physical address. */
2397	AVLOHCPHYSTREE HCPhysTree;
2398	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2399	/** Array of pages. (cMaxPages in length)
2400	* The Id is the index into thist array.
2401	*/
2402	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2403	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2404	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2405	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2406	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2407	#ifdef VBOX_WITH_STATISTICS
2408	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2409	#endif
2410	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2411
2412
2413	/** @def PGMPOOL_PAGE_2_PTR
2414	* Maps a pool page pool into the current context.
2415	*
2416	* @returns VBox status code.
2417	* @param a_pVM Pointer to the VM.
2418	* @param a_pPage The pool page.
2419	*
2420	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2421	* small page window employeed by that function. Be careful.
2422	* @remark There is no need to assert on the result.
2423	*/
2424	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2425	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2426	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2427	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2428	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2429	{
2430	RT_NOREF(pszCaller);
2431	AssertPtr(a_pPage);
2432	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2433	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2434	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2435	return a_pPage->CTX_SUFF(pvPage);
2436	}
2437	#else
2438	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2439	#endif
2440
2441
2442	/** @def PGMPOOL_PAGE_2_PTR_V2
2443	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2444	*
2445	* @returns VBox status code.
2446	* @param a_pVM Pointer to the VM.
2447	* @param a_pVCpu The current CPU.
2448	* @param a_pPage The pool page.
2449	*
2450	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2451	* small page window employeed by that function. Be careful.
2452	* @remark There is no need to assert on the result.
2453	*/
2454	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2455	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2456	#else
2457	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2458	#endif
2459
2460
2461	/** @name Per guest page tracking data.
2462	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2463	* is to use more bits for it and split it up later on. But for now we'll play
2464	* safe and change as little as possible.
2465	*
2466	* The 16-bit word has two parts:
2467	*
2468	* The first 14-bit forms the @a idx field. It is either the index of a page in
2469	* the shadow page pool, or and index into the extent list.
2470	*
2471	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2472	* shadow page pool references to the page. If cRefs equals
2473	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2474	* (misnomer) table and not the shadow page pool.
2475	*
2476	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2477	* the 16-bit word.
2478	*
2479	* @{ */
2480	/** The shift count for getting to the cRefs part. */
2481	#define PGMPOOL_TD_CREFS_SHIFT 14
2482	/** The mask applied after shifting the tracking data down by
2483	* PGMPOOL_TD_CREFS_SHIFT. */
2484	#define PGMPOOL_TD_CREFS_MASK 0x3
2485	/** The cRefs value used to indicate that the idx is the head of a
2486	* physical cross reference list. */
2487	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2488	/** The shift used to get idx. */
2489	#define PGMPOOL_TD_IDX_SHIFT 0
2490	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2491	#define PGMPOOL_TD_IDX_MASK 0x3fff
2492	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2493	* simply too many mappings of this page. */
2494	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2495
2496	/** @def PGMPOOL_TD_MAKE
2497	* Makes a 16-bit tracking data word.
2498	*
2499	* @returns tracking data.
2500	* @param cRefs The @a cRefs field. Must be within bounds!
2501	* @param idx The @a idx field. Must also be within bounds! */
2502	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2503
2504	/** @def PGMPOOL_TD_GET_CREFS
2505	* Get the @a cRefs field from a tracking data word.
2506	*
2507	* @returns The @a cRefs field
2508	* @param u16 The tracking data word.
2509	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2510	* non-zero @a u16. */
2511	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2512
2513	/** @def PGMPOOL_TD_GET_IDX
2514	* Get the @a idx field from a tracking data word.
2515	*
2516	* @returns The @a idx field
2517	* @param u16 The tracking data word. */
2518	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2519	/** @} */
2520
2521
2522
2523	/** @name A20 gate macros
2524	* @{ */
2525	#define PGM_WITH_A20
2526	#ifdef PGM_WITH_A20
2527	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2528	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2529	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2530	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2531	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2532	#else
2533	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2534	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2535	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2536	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2537	#endif
2538	/** @} */
2539
2540
2541	/**
2542	* Roots and anchors for trees and list employing self relative offsets as
2543	* pointers.
2544	*
2545	* When using self-relative offsets instead of pointers, the offsets needs to be
2546	* the same in all offsets. Thus the roots and anchors needs to live on the
2547	* hyper heap just like the nodes.
2548	*/
2549	typedef struct PGMTREES
2550	{
2551	/** List of physical access handler types (offset pointers) of type
2552	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2553	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2554	/** Physical access handlers (AVL range+offsetptr tree). */
2555	AVLROGCPHYSTREE PhysHandlers;
2556	} PGMTREES;
2557	/** Pointer to PGM trees. */
2558	typedef PGMTREES *PPGMTREES;
2559
2560
2561	/**
2562	* Page fault guest state for the AMD64 paging mode.
2563	*/
2564	typedef struct PGMPTWALKCORE
2565	{
2566	/** The guest virtual address that is being resolved by the walk
2567	* (input). */
2568	RTGCPTR GCPtr;
2569
2570	/** The guest physical address that is the result of the walk.
2571	* @remarks only valid if fSucceeded is set. */
2572	RTGCPHYS GCPhys;
2573
2574	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2575	bool fSucceeded;
2576	/** The level problem arrised at.
2577	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2578	* level 8. This is 0 on success. */
2579	uint8_t uLevel;
2580	/** Set if the page isn't present. */
2581	bool fNotPresent;
2582	/** Encountered a bad physical address. */
2583	bool fBadPhysAddr;
2584	/** Set if there was reserved bit violations. */
2585	bool fRsvdError;
2586	/** Set if it involves a big page (2/4 MB). */
2587	bool fBigPage;
2588	/** Set if it involves a gigantic page (1 GB). */
2589	bool fGigantPage;
2590	/** The effective X86_PTE_US flag for the address. */
2591	bool fEffectiveUS;
2592	/** The effective X86_PTE_RW flag for the address. */
2593	bool fEffectiveRW;
2594	/** The effective X86_PTE_NX flag for the address. */
2595	bool fEffectiveNX;
2596	bool afPadding1[2];
2597	/** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2598	* The NX bit is inverted and shifted down 63 places to bit 0. */
2599	uint32_t fEffective;
2600	} PGMPTWALKCORE;
2601
2602	/** @name PGMPTWALKCORE::fEffective bits.
2603	* @{ */
2604	/** Effective execute bit (!NX). */
2605	#define PGMPTWALK_EFF_X UINT32_C(1)
2606	/** Effective write access bit. */
2607	#define PGMPTWALK_EFF_RW X86_PTE_RW
2608	/** Effective user-mode access bit. */
2609	#define PGMPTWALK_EFF_US X86_PTE_US
2610	/** Effective write through cache bit. */
2611	#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2612	/** Effective cache disabled bit. */
2613	#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2614	/** Effective accessed bit. */
2615	#define PGMPTWALK_EFF_A X86_PTE_A
2616	/** The dirty bit of the final entry. */
2617	#define PGMPTWALK_EFF_D X86_PTE_D
2618	/** The PAT bit of the final entry. */
2619	#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2620	/** The global bit of the final entry. */
2621	#define PGMPTWALK_EFF_G X86_PTE_G
2622	/** @} */
2623
2624
2625	/**
2626	* Guest page table walk for the AMD64 mode.
2627	*/
2628	typedef struct PGMPTWALKGSTAMD64
2629	{
2630	/** The common core. */
2631	PGMPTWALKCORE Core;
2632
2633	PX86PML4 pPml4;
2634	PX86PML4E pPml4e;
2635	X86PML4E Pml4e;
2636
2637	PX86PDPT pPdpt;
2638	PX86PDPE pPdpe;
2639	X86PDPE Pdpe;
2640
2641	PX86PDPAE pPd;
2642	PX86PDEPAE pPde;
2643	X86PDEPAE Pde;
2644
2645	PX86PTPAE pPt;
2646	PX86PTEPAE pPte;
2647	X86PTEPAE Pte;
2648	} PGMPTWALKGSTAMD64;
2649	/** Pointer to a AMD64 guest page table walk. */
2650	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2651	/** Pointer to a const AMD64 guest page table walk. */
2652	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2653
2654	/**
2655	* Guest page table walk for the PAE mode.
2656	*/
2657	typedef struct PGMPTWALKGSTPAE
2658	{
2659	/** The common core. */
2660	PGMPTWALKCORE Core;
2661
2662	PX86PDPT pPdpt;
2663	PX86PDPE pPdpe;
2664	X86PDPE Pdpe;
2665
2666	PX86PDPAE pPd;
2667	PX86PDEPAE pPde;
2668	X86PDEPAE Pde;
2669
2670	PX86PTPAE pPt;
2671	PX86PTEPAE pPte;
2672	X86PTEPAE Pte;
2673	} PGMPTWALKGSTPAE;
2674	/** Pointer to a PAE guest page table walk. */
2675	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2676	/** Pointer to a const AMD64 guest page table walk. */
2677	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2678
2679	/**
2680	* Guest page table walk for the 32-bit mode.
2681	*/
2682	typedef struct PGMPTWALKGST32BIT
2683	{
2684	/** The common core. */
2685	PGMPTWALKCORE Core;
2686
2687	PX86PD pPd;
2688	PX86PDE pPde;
2689	X86PDE Pde;
2690
2691	PX86PT pPt;
2692	PX86PTE pPte;
2693	X86PTE Pte;
2694	} PGMPTWALKGST32BIT;
2695	/** Pointer to a 32-bit guest page table walk. */
2696	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2697	/** Pointer to a const 32-bit guest page table walk. */
2698	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2699
2700	/**
2701	* Which part of PGMPTWALKGST that is valid.
2702	*/
2703	typedef enum PGMPTWALKGSTTYPE
2704	{
2705	/** Customary invalid 0 value. */
2706	PGMPTWALKGSTTYPE_INVALID = 0,
2707	/** PGMPTWALKGST::u.Amd64 is valid. */
2708	PGMPTWALKGSTTYPE_AMD64,
2709	/** PGMPTWALKGST::u.Pae is valid. */
2710	PGMPTWALKGSTTYPE_PAE,
2711	/** PGMPTWALKGST::u.Legacy is valid. */
2712	PGMPTWALKGSTTYPE_32BIT,
2713	/** Customary 32-bit type hack. */
2714	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2715	} PGMPTWALKGSTTYPE;
2716
2717	/**
2718	* Combined guest page table walk result.
2719	*/
2720	typedef struct PGMPTWALKGST
2721	{
2722	union
2723	{
2724	/** The page walker core - always valid. */
2725	PGMPTWALKCORE Core;
2726	/** The page walker for AMD64. */
2727	PGMPTWALKGSTAMD64 Amd64;
2728	/** The page walker for PAE (32-bit). */
2729	PGMPTWALKGSTPAE Pae;
2730	/** The page walker for 32-bit paging (called legacy due to C naming
2731	* convension). */
2732	PGMPTWALKGST32BIT Legacy;
2733	} u;
2734	/** Indicates which part of the union is valid. */
2735	PGMPTWALKGSTTYPE enmType;
2736	} PGMPTWALKGST;
2737	/** Pointer to a combined guest page table walk result. */
2738	typedef PGMPTWALKGST *PPGMPTWALKGST;
2739	/** Pointer to a read-only combined guest page table walk result. */
2740	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2741
2742
2743	/** @name Paging mode macros
2744	* @{
2745	*/
2746	#ifdef IN_RING3
2747	# define PGM_CTX(a,b) a##R3##b
2748	# define PGM_CTX_STR(a,b) a "R3" b
2749	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2750	#elif defined(IN_RING0)
2751	# define PGM_CTX(a,b) a##R0##b
2752	# define PGM_CTX_STR(a,b) a "R0" b
2753	# define PGM_CTX_DECL(type) VMMDECL(type)
2754	#else
2755	# error "Not IN_RING3 or IN_RING0!"
2756	#endif
2757
2758	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2759	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2760	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2761	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2762	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2763	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2764	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2765	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2766	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2767	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2768	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2769	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2770	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2771	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2772	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2773	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2774
2775	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2776	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2777	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2778	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2779	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2780	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2781	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2782	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2783	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2784	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2785	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2786	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2787	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2788	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2789	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2790	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2791	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2792	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2793	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2794	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2795	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2796	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2797	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2798	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2799	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2800
2801	/* Shw_Gst */
2802	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2803	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2804	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2805	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2806	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2807	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2808	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2809	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2810	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2811	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2812	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2813	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2814	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2815	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2816	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2817	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2818	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2819	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2820	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2821	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2822	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2823	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2824	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2825	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2826	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2827	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2828	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2829	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2830	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2831	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2832	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2833	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2834	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2835	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2836
2837	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2838	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2839	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2840	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2841	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2842	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2843	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2844	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2845	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2846	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2847	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2848	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2849	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2850	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2851	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2852	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2853	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2854	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2855	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2856	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2857	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2858	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2859	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2860	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2861	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2862	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2863	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2864	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2865
2866	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2867	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2868	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2869	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2870	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2871	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2872	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2873	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2874	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2875	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2876	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2877	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2878	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2879	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2880	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2881	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2882	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2883	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2884	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2885	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2886	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2887	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2888	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2889	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2890	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2891	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2892	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2893	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2894	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2895
2896	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2897	/** @} */
2898
2899
2900	/**
2901	* Function pointers for guest paging.
2902	*/
2903	typedef struct PGMMODEDATAGST
2904	{
2905	/** The guest mode type. */
2906	uint32_t uType;
2907	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2908	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2909	DECLCALLBACKMEMBER(int, pfnGetPDE,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2910	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2911	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2912	#ifdef IN_RING3
2913	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2914	#endif
2915	} PGMMODEDATAGST;
2916
2917	/** The length of g_aPgmGuestModeData. */
2918	#ifdef VBOX_WITH_64_BITS_GUESTS
2919	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2920	#else
2921	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2922	#endif
2923	/** The guest mode data array. */
2924	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2925
2926
2927	/**
2928	* Function pointers for shadow paging.
2929	*/
2930	typedef struct PGMMODEDATASHW
2931	{
2932	/** The shadow mode type. */
2933	uint32_t uType;
2934	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2935	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2936	uint64_t fMask, uint32_t fOpFlags));
2937	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2938	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2939	#ifdef IN_RING3
2940	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2941	#endif
2942	} PGMMODEDATASHW;
2943
2944	/** The length of g_aPgmShadowModeData. */
2945	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2946	/** The shadow mode data array. */
2947	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2948
2949
2950	/**
2951	* Function pointers for guest+shadow paging.
2952	*/
2953	typedef struct PGMMODEDATABTH
2954	{
2955	/** The shadow mode type. */
2956	uint32_t uShwType;
2957	/** The guest mode type. */
2958	uint32_t uGstType;
2959
2960	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2961	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2962	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2963	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2964	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2965	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2966	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2967	#ifndef IN_RING3
2968	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2969	#endif
2970	#ifdef VBOX_STRICT
2971	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2972	#endif
2973	} PGMMODEDATABTH;
2974
2975	/** The length of g_aPgmBothModeData. */
2976	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2977	/** The guest+shadow mode data array. */
2978	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2979
2980
2981	#ifdef VBOX_WITH_STATISTICS
2982	/**
2983	* PGM statistics.
2984	*
2985	* These lives on the heap when compiled in as they would otherwise waste
2986	* unnecessary space in release builds.
2987	*/
2988	typedef struct PGMSTATS
2989	{
2990	/* R3 only: */
2991	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2992	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2993
2994	/* R3+RZ */
2995	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2996	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2997	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2998	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2999	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3000	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3001	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3002	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3003	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3004	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3005	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3006	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3007	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3008	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3009	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3010	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3011	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3012	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3013	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3014	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3015	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3016	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3017	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3018	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3019	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3020	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3021
3022	/* RC only: */
3023	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3024	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3025
3026	STAMCOUNTER StatRZPhysRead;
3027	STAMCOUNTER StatRZPhysReadBytes;
3028	STAMCOUNTER StatRZPhysWrite;
3029	STAMCOUNTER StatRZPhysWriteBytes;
3030	STAMCOUNTER StatR3PhysRead;
3031	STAMCOUNTER StatR3PhysReadBytes;
3032	STAMCOUNTER StatR3PhysWrite;
3033	STAMCOUNTER StatR3PhysWriteBytes;
3034	STAMCOUNTER StatRCPhysRead;
3035	STAMCOUNTER StatRCPhysReadBytes;
3036	STAMCOUNTER StatRCPhysWrite;
3037	STAMCOUNTER StatRCPhysWriteBytes;
3038
3039	STAMCOUNTER StatRZPhysSimpleRead;
3040	STAMCOUNTER StatRZPhysSimpleReadBytes;
3041	STAMCOUNTER StatRZPhysSimpleWrite;
3042	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3043	STAMCOUNTER StatR3PhysSimpleRead;
3044	STAMCOUNTER StatR3PhysSimpleReadBytes;
3045	STAMCOUNTER StatR3PhysSimpleWrite;
3046	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3047	STAMCOUNTER StatRCPhysSimpleRead;
3048	STAMCOUNTER StatRCPhysSimpleReadBytes;
3049	STAMCOUNTER StatRCPhysSimpleWrite;
3050	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3051
3052	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3053	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3054	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3055	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3056	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3057	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3058	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3059
3060	/** Time spent by the host OS for large page allocation. */
3061	STAMPROFILE StatAllocLargePage;
3062	/** Time spent clearing the newly allocated large pages. */
3063	STAMPROFILE StatClearLargePage;
3064	/** The number of times allocating a large pages takes more than the allowed period. */
3065	STAMCOUNTER StatLargePageOverflow;
3066	/** pgmPhysIsValidLargePage profiling - R3 */
3067	STAMPROFILE StatR3IsValidLargePage;
3068	/** pgmPhysIsValidLargePage profiling - RZ*/
3069	STAMPROFILE StatRZIsValidLargePage;
3070
3071	STAMPROFILE StatChunkAging;
3072	STAMPROFILE StatChunkFindCandidate;
3073	STAMPROFILE StatChunkUnmap;
3074	STAMPROFILE StatChunkMap;
3075	} PGMSTATS;
3076	#endif /* VBOX_WITH_STATISTICS */
3077
3078
3079	/**
3080	* Converts a PGM pointer into a VM pointer.
3081	* @returns Pointer to the VM structure the PGM is part of.
3082	* @param pPGM Pointer to PGM instance data.
3083	*/
3084	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3085
3086	/**
3087	* PGM Data (part of VM)
3088	*/
3089	typedef struct PGM
3090	{
3091	/** Offset to the VM structure. */
3092	int32_t offVM;
3093	/** Offset of the PGMCPU structure relative to VMCPU. */
3094	int32_t offVCpuPGM;
3095
3096	/** @cfgm{/RamPreAlloc, boolean, false}
3097	* Indicates whether the base RAM should all be allocated before starting
3098	* the VM (default), or if it should be allocated when first written to.
3099	*/
3100	bool fRamPreAlloc;
3101	/** Indicates whether write monitoring is currently in use.
3102	* This is used to prevent conflicts between live saving and page sharing
3103	* detection. */
3104	bool fPhysWriteMonitoringEngaged;
3105	/** Set if the CPU has less than 52-bit physical address width.
3106	* This is used */
3107	bool fLessThan52PhysicalAddressBits;
3108	/** Set when nested paging is active.
3109	* This is meant to save calls to HMIsNestedPagingActive and let the
3110	* compilers optimize the code better. Whether we use nested paging or
3111	* not is something we find out during VMM initialization and we won't
3112	* change this later on. */
3113	bool fNestedPaging;
3114	/** The host paging mode. (This is what SUPLib reports.) */
3115	SUPPAGINGMODE enmHostMode;
3116	/** We're not in a state which permits writes to guest memory.
3117	* (Only used in strict builds.) */
3118	bool fNoMorePhysWrites;
3119	/** @cfgm{/PageFusionAllowed, boolean, false}
3120	* Whether page fusion is allowed. */
3121	bool fPageFusionAllowed;
3122	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3123	* Whether PCI passthrough is enabled. */
3124	bool fPciPassthrough;
3125	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3126	uint8_t cMmio2Regions;
3127	/** Restore original ROM page content when resetting after loading state.
3128	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3129	* enables the VM to start using an updated ROM without requiring powering
3130	* down the VM, just rebooting or resetting it. */
3131	bool fRestoreRomPagesOnReset;
3132	/** Whether to automatically clear all RAM pages on reset. */
3133	bool fZeroRamPagesOnReset;
3134	/** Alignment padding. */
3135	bool afAlignment3[7];
3136
3137	/** Indicates that PGMR3FinalizeMappings has been called and that further
3138	* PGMR3MapIntermediate calls will be rejected. */
3139	bool fFinalizedMappings;
3140	/** If set no conflict checks are required. */
3141	bool fMappingsFixed;
3142	/** If set if restored as fixed but we were unable to re-fixate at the old
3143	* location because of room or address incompatibilities. */
3144	bool fMappingsFixedRestored;
3145	/** Size of fixed mapping.
3146	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3147	uint32_t cbMappingFixed;
3148	/** Generation ID for the RAM ranges. This member is incremented everytime
3149	* a RAM range is linked or unlinked. */
3150	uint32_t volatile idRamRangesGen;
3151
3152	/** Base address (GC) of fixed mapping.
3153	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3154	RTGCPTR GCPtrMappingFixed;
3155	/** The address of the previous RAM range mapping. */
3156	RTGCPTR GCPtrPrevRamRangeMapping;
3157
3158	/** Physical access handler type for ROM protection. */
3159	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3160	/** Alignment padding. */
3161	uint32_t u32Padding;
3162
3163	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3164	RTGCPHYS GCPhys4MBPSEMask;
3165	/** Mask containing the invalid bits of a guest physical address.
3166	* @remarks this does not stop at bit 52. */
3167	RTGCPHYS GCPhysInvAddrMask;
3168
3169
3170	/** RAM range TLB for R3. */
3171	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3172	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3173	* This is sorted by physical address and contains no overlapping ranges. */
3174	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3175	/** Root of the RAM range search tree for ring-3. */
3176	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3177	/** PGM offset based trees - R3 Ptr. */
3178	R3PTRTYPE(PPGMTREES) pTreesR3;
3179	/** Caching the last physical handler we looked up in R3. */
3180	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3181	/** Shadow Page Pool - R3 Ptr. */
3182	R3PTRTYPE(PPGMPOOL) pPoolR3;
3183	#ifndef PGM_WITHOUT_MAPPINGS
3184	/** Linked list of GC mappings - for HC.
3185	* The list is sorted ascending on address. */
3186	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3187	#endif
3188	/** Pointer to the list of ROM ranges - for R3.
3189	* This is sorted by physical address and contains no overlapping ranges. */
3190	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3191	/** Pointer to the list of MMIO2 ranges - for R3.
3192	* Registration order. */
3193	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3194	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3195	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3196
3197	/** RAM range TLB for R0. */
3198	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3199	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3200	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3201	/** Root of the RAM range search tree for ring-0. */
3202	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3203	/** PGM offset based trees - R0 Ptr. */
3204	R0PTRTYPE(PPGMTREES) pTreesR0;
3205	/** Caching the last physical handler we looked up in R0. */
3206	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3207	/** Shadow Page Pool - R0 Ptr. */
3208	R0PTRTYPE(PPGMPOOL) pPoolR0;
3209	#ifndef PGM_WITHOUT_MAPPINGS
3210	/** Linked list of GC mappings - for R0.
3211	* The list is sorted ascending on address. */
3212	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3213	RTR0PTR R0PtrAlignment0;
3214	#endif
3215	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3216	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3217	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3218	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3219
3220	#ifndef PGM_WITHOUT_MAPPINGS
3221	/** Pointer to the 5 page CR3 content mapping.
3222	* The first page is always the CR3 (in some form) while the 4 other pages
3223	* are used for the PDs in PAE mode. */
3224	RTGCPTR GCPtrCR3Mapping;
3225
3226	/** @name Intermediate Context
3227	* @{ */
3228	/** Pointer to the intermediate page directory - Normal. */
3229	R3PTRTYPE(PX86PD) pInterPD;
3230	/** Pointer to the intermediate page tables - Normal.
3231	* There are two page tables, one for the identity mapping and one for
3232	* the host context mapping (of the core code). */
3233	R3PTRTYPE(PX86PT) apInterPTs[2];
3234	/** Pointer to the intermediate page tables - PAE. */
3235	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3236	/** Pointer to the intermediate page directory - PAE. */
3237	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3238	/** Pointer to the intermediate page directory - PAE. */
3239	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3240	/** Pointer to the intermediate page-map level 4 - AMD64. */
3241	R3PTRTYPE(PX86PML4) pInterPaePML4;
3242	/** Pointer to the intermediate page directory - AMD64. */
3243	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3244	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3245	RTHCPHYS HCPhysInterPD;
3246	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3247	RTHCPHYS HCPhysInterPaePDPT;
3248	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3249	RTHCPHYS HCPhysInterPaePML4;
3250	/** @} */
3251	#endif
3252
3253	#ifndef PGM_WITHOUT_MAPPINGS
3254	/** Base address of the dynamic page mapping area.
3255	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3256	*
3257	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3258	* work out. Some cleaning up of the initialization that would
3259	* remove this memory is yet to be done...
3260	*/
3261	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3262	/** The address of the raw-mode context mapping cache. */
3263	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3264	/** The address of the ring-0 mapping cache if we're making use of it. */
3265	RTR0PTR pvR0DynMapUsed;
3266	#endif
3267
3268	/** Hack: Number of deprecated page mapping locks taken by the current lock
3269	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3270	uint32_t cDeprecatedPageLocks;
3271	/** Alignment padding. */
3272	uint32_t au32Alignment2[1];
3273
3274
3275	/** PGM critical section.
3276	* This protects the physical, ram ranges, and the page flag updating (some of
3277	* it anyway).
3278	*/
3279	PDMCRITSECT CritSectX;
3280
3281	/**
3282	* Data associated with managing the ring-3 mappings of the allocation chunks.
3283	*/
3284	struct
3285	{
3286	/** The chunk mapping TLB. */
3287	PGMCHUNKR3MAPTLB Tlb;
3288	/** The chunk tree, ordered by chunk id. */
3289	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAM_IN_KERNEL)
3290	R3PTRTYPE(PAVLU32NODECORE) pTree;
3291	#else
3292	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3293	#endif
3294	#if HC_ARCH_BITS == 32
3295	uint32_t u32Alignment0;
3296	#endif
3297	/** The number of mapped chunks. */
3298	uint32_t c;
3299	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3300	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3301	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3302	uint32_t cMax;
3303	/** The current time. This is incremented whenever a chunk is inserted. */
3304	uint32_t iNow;
3305	/** Alignment padding. */
3306	uint32_t au32Alignment1[3];
3307	} ChunkR3Map;
3308
3309	/** The page mapping TLB for ring-3. */
3310	PGMPAGER3MAPTLB PhysTlbR3;
3311	#ifdef VBOX_WITH_RAM_IN_KERNEL
3312	/** The page mapping TLB for ring-0. */
3313	PGMPAGER0MAPTLB PhysTlbR0;
3314	#else
3315	/** The page mapping TLB for ring-0 (still using ring-3 mappings). */
3316	PGMPAGER3MAPTLB PhysTlbR0;
3317	#endif
3318
3319	/** @name The zero page.
3320	* @{ */
3321	/** The host physical address of the zero page. */
3322	RTHCPHYS HCPhysZeroPg;
3323	/** The ring-3 mapping of the zero page. */
3324	RTR3PTR pvZeroPgR3;
3325	/** The ring-0 mapping of the zero page. */
3326	RTR0PTR pvZeroPgR0;
3327	/** The GC mapping of the zero page. */
3328	RTRCPTR pvZeroPgRC;
3329	RTRCPTR RCPtrAlignment3;
3330	/** @}*/
3331
3332	/** @name The Invalid MMIO page.
3333	* This page is filled with 0xfeedface.
3334	* @{ */
3335	/** The host physical address of the invalid MMIO page. */
3336	RTHCPHYS HCPhysMmioPg;
3337	/** The host pysical address of the invalid MMIO page plus all invalid
3338	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3339	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3340	RTHCPHYS HCPhysInvMmioPg;
3341	/** The ring-3 mapping of the invalid MMIO page. */
3342	RTR3PTR pvMmioPgR3;
3343	#if HC_ARCH_BITS == 32
3344	RTR3PTR R3PtrAlignment4;
3345	#endif
3346	/** @} */
3347
3348
3349	/** The number of handy pages. */
3350	uint32_t cHandyPages;
3351
3352	/** The number of large handy pages. */
3353	uint32_t cLargeHandyPages;
3354
3355	/**
3356	* Array of handy pages.
3357	*
3358	* This array is used in a two way communication between pgmPhysAllocPage
3359	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3360	* an intermediary.
3361	*
3362	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3363	* (The current size of 32 pages, means 128 KB of handy memory.)
3364	*/
3365	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3366
3367	/**
3368	* Array of large handy pages. (currently size 1)
3369	*
3370	* This array is used in a two way communication between pgmPhysAllocLargePage
3371	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3372	* an intermediary.
3373	*/
3374	GMMPAGEDESC aLargeHandyPage[1];
3375
3376	/**
3377	* Live save data.
3378	*/
3379	struct
3380	{
3381	/** Per type statistics. */
3382	struct
3383	{
3384	/** The number of ready pages. */
3385	uint32_t cReadyPages;
3386	/** The number of dirty pages. */
3387	uint32_t cDirtyPages;
3388	/** The number of ready zero pages. */
3389	uint32_t cZeroPages;
3390	/** The number of write monitored pages. */
3391	uint32_t cMonitoredPages;
3392	} Rom,
3393	Mmio2,
3394	Ram;
3395	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3396	uint32_t cIgnoredPages;
3397	/** Indicates that a live save operation is active. */
3398	bool fActive;
3399	/** Padding. */
3400	bool afReserved[2];
3401	/** The next history index. */
3402	uint8_t iDirtyPagesHistory;
3403	/** History of the total amount of dirty pages. */
3404	uint32_t acDirtyPagesHistory[64];
3405	/** Short term dirty page average. */
3406	uint32_t cDirtyPagesShort;
3407	/** Long term dirty page average. */
3408	uint32_t cDirtyPagesLong;
3409	/** The number of saved pages. This is used to get some kind of estimate of the
3410	* link speed so we can decide when we're done. It is reset after the first
3411	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3412	* zero pages. */
3413	uint64_t cSavedPages;
3414	/** The nanosecond timestamp when cSavedPages was 0. */
3415	uint64_t uSaveStartNS;
3416	/** Pages per second (for statistics). */
3417	uint32_t cPagesPerSecond;
3418	uint32_t cAlignment;
3419	} LiveSave;
3420
3421	/** @name Error injection.
3422	* @{ */
3423	/** Inject handy page allocation errors pretending we're completely out of
3424	* memory. */
3425	bool volatile fErrInjHandyPages;
3426	/** Padding. */
3427	bool afReserved[3];
3428	/** @} */
3429
3430	/** @name Release Statistics
3431	* @{ */
3432	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3433	uint32_t cPrivatePages; /*< The number of private pages. /
3434	uint32_t cSharedPages; /*< The number of shared pages. /
3435	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3436	uint32_t cZeroPages; /*< The number of zero backed pages. /
3437	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3438	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3439	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3440	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3441	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3442	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3443	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3444	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3445	uint32_t cLargePages; /*< The number of large pages. /
3446	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3447	/* uint32_t aAlignment4[1]; */
3448
3449	/** The number of times we were forced to change the hypervisor region location. */
3450	STAMCOUNTER cRelocations;
3451
3452	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3453	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3454	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3455
3456	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3457	/** @} */
3458
3459	#ifdef VBOX_WITH_STATISTICS
3460	/** @name Statistics on the heap.
3461	* @{ */
3462	R3PTRTYPE(PGMSTATS *) pStatsR3;
3463	R0PTRTYPE(PGMSTATS *) pStatsR0;
3464	/** @} */
3465	#endif
3466	} PGM;
3467	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3468	# ifndef PGM_WITHOUT_MAPPINGS
3469	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3470	# endif
3471	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3472	# ifndef PGM_WITHOUT_MAPPINGS
3473	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3474	# endif
3475	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3476	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3477	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3478	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3479	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3480	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3481	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3482	#endif /* !IN_TSTVMSTRUCTGC */
3483	/** Pointer to the PGM instance data. */
3484	typedef PGM *PPGM;
3485
3486
3487
3488	typedef struct PGMCPUSTATS
3489	{
3490	/* Common */
3491	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3492	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3493
3494	/* R0 only: */
3495	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3496	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3497
3498	/* RZ only: */
3499	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3500	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3501	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3502	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3503	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3504	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3505	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3506	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3507	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3508	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3509	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3510	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3511	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3512	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3513	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3514	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3515	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3516	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3517	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3518	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3519	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3520	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3521	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3522	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3523	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3524	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3525	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3526	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3527	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3528	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3529	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3530	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3531	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3532	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3533	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3534	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3535	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3536	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3537	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3538	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3539	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3540	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3541	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3542	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3543	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3544	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3545	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3546	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3547	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3548	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3549	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3550	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3551	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3552	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3553	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3554	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3555	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3556	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3557	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3558	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3559	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3560	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3561	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3562	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3563	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3564	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3565	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3566	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3567	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3568	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3569	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3570	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3571	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3572
3573	/* HC - R3 and (maybe) R0: */
3574
3575	/* RZ & R3: */
3576	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3577	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3578	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3579	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3580	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3581	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3582	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3583	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3584	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3585	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3586	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3587	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3588	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3589	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3590	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3591	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3592	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3593	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3594	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3595	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3596	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3597	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3598	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3599	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3600	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3601	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3602	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3603	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3604	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3605	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3606	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3607	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3608	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3609	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3610	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3611	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3612	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3613	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3614	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3615	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3616	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3617	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3618	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3619	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3620	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3621	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3622	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3623	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3624
3625	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3626	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3627	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3628	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3629	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3630	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3631	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3632	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3633	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3634	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3635	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3636	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3637	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3638	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3639	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3640	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3641	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3642	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3643	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3644	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3645	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3646	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3647	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3648	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3649	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3650	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3651	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3652	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3653	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3654	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3655	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3656	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3657	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3658	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3659	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3660	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3661	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3662	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3663	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3664	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3665	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3666	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3667	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3668	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3669	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3670	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3671	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3672	} PGMCPUSTATS;
3673
3674
3675	/**
3676	* Converts a PGMCPU pointer into a VM pointer.
3677	* @returns Pointer to the VM structure the PGM is part of.
3678	* @param pPGM Pointer to PGMCPU instance data.
3679	*/
3680	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3681
3682	/**
3683	* Converts a PGMCPU pointer into a PGM pointer.
3684	* @returns Pointer to the VM structure the PGM is part of.
3685	* @param pPGMCpu Pointer to PGMCPU instance data.
3686	*/
3687	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3688
3689	/**
3690	* PGMCPU Data (part of VMCPU).
3691	*/
3692	typedef struct PGMCPU
3693	{
3694	/** Offset to the VM structure. */
3695	int32_t offVM;
3696	/** Offset to the VMCPU structure. */
3697	int32_t offVCpu;
3698	/** Offset of the PGM structure relative to VMCPU. */
3699	int32_t offPGM;
3700	uint32_t uPadding0; /*< structure size alignment. /
3701
3702	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3703	/** Automatically tracked physical memory mapping set.
3704	* Ring-0 and strict raw-mode builds. */
3705	PGMMAPSET AutoSet;
3706	#endif
3707
3708	/** A20 gate mask.
3709	* Our current approach to A20 emulation is to let REM do it and don't bother
3710	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3711	* But whould need arrise, we'll subject physical addresses to this mask. */
3712	RTGCPHYS GCPhysA20Mask;
3713	/** A20 gate state - boolean! */
3714	bool fA20Enabled;
3715	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3716	bool fNoExecuteEnabled;
3717	/** Unused bits. */
3718	bool afUnused[2];
3719
3720	/** What needs syncing (PGM_SYNC_*).
3721	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3722	* PGMFlushTLB, and PGMR3Load. */
3723	uint32_t fSyncFlags;
3724
3725	/** The shadow paging mode. */
3726	PGMMODE enmShadowMode;
3727	/** The guest paging mode. */
3728	PGMMODE enmGuestMode;
3729	/** Guest mode data table index (PGM_TYPE_XXX). */
3730	uint8_t volatile idxGuestModeData;
3731	/** Shadow mode data table index (PGM_TYPE_XXX). */
3732	uint8_t volatile idxShadowModeData;
3733	/** Both mode data table index (complicated). */
3734	uint8_t volatile idxBothModeData;
3735	/** Alignment padding. */
3736	uint8_t abPadding[5];
3737
3738	/** The current physical address represented in the guest CR3 register. */
3739	RTGCPHYS GCPhysCR3;
3740
3741	/** @name 32-bit Guest Paging.
3742	* @{ */
3743	/** The guest's page directory, R3 pointer. */
3744	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3745	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3746	/** The guest's page directory, R0 pointer. */
3747	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3748	#endif
3749	/** Mask containing the MBZ bits of a big page PDE. */
3750	uint32_t fGst32BitMbzBigPdeMask;
3751	/** Set if the page size extension (PSE) is enabled. */
3752	bool fGst32BitPageSizeExtension;
3753	/** Alignment padding. */
3754	bool afAlignment2[3];
3755	/** @} */
3756
3757	/** @name PAE Guest Paging.
3758	* @{ */
3759	/** The guest's page directory pointer table, R3 pointer. */
3760	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3761	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3762	/** The guest's page directory pointer table, R0 pointer. */
3763	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3764	#endif
3765
3766	/** The guest's page directories, R3 pointers.
3767	* These are individual pointers and don't have to be adjacent.
3768	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3769	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3770	/** The guest's page directories, R0 pointers.
3771	* Same restrictions as apGstPaePDsR3. */
3772	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3773	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3774	#endif
3775	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3776	* @todo Remove this and use aGstPaePdpeRegs instead? */
3777	RTGCPHYS aGCPhysGstPaePDs[4];
3778	/** The values of the 4 PDPE CPU registers (PAE). */
3779	X86PDPE aGstPaePdpeRegs[4];
3780	/** The physical addresses of the monitored guest page directories (PAE). */
3781	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3782	/** Mask containing the MBZ PTE bits. */
3783	uint64_t fGstPaeMbzPteMask;
3784	/** Mask containing the MBZ PDE bits. */
3785	uint64_t fGstPaeMbzPdeMask;
3786	/** Mask containing the MBZ big page PDE bits. */
3787	uint64_t fGstPaeMbzBigPdeMask;
3788	/** Mask containing the MBZ PDPE bits. */
3789	uint64_t fGstPaeMbzPdpeMask;
3790	/** @} */
3791
3792	/** @name AMD64 Guest Paging.
3793	* @{ */
3794	/** The guest's page directory pointer table, R3 pointer. */
3795	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3796	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3797	/** The guest's page directory pointer table, R0 pointer. */
3798	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3799	#else
3800	RTR0PTR alignment6b; /*< alignment equalizer. /
3801	#endif
3802	/** Mask containing the MBZ PTE bits. */
3803	uint64_t fGstAmd64MbzPteMask;
3804	/** Mask containing the MBZ PDE bits. */
3805	uint64_t fGstAmd64MbzPdeMask;
3806	/** Mask containing the MBZ big page PDE bits. */
3807	uint64_t fGstAmd64MbzBigPdeMask;
3808	/** Mask containing the MBZ PDPE bits. */
3809	uint64_t fGstAmd64MbzPdpeMask;
3810	/** Mask containing the MBZ big page PDPE bits. */
3811	uint64_t fGstAmd64MbzBigPdpeMask;
3812	/** Mask containing the MBZ PML4E bits. */
3813	uint64_t fGstAmd64MbzPml4eMask;
3814	/** Mask containing the PDPE bits that we shadow. */
3815	uint64_t fGstAmd64ShadowedPdpeMask;
3816	/** Mask containing the PML4E bits that we shadow. */
3817	uint64_t fGstAmd64ShadowedPml4eMask;
3818	/** @} */
3819
3820	/** @name PAE and AMD64 Guest Paging.
3821	* @{ */
3822	/** Mask containing the PTE bits that we shadow. */
3823	uint64_t fGst64ShadowedPteMask;
3824	/** Mask containing the PDE bits that we shadow. */
3825	uint64_t fGst64ShadowedPdeMask;
3826	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3827	uint64_t fGst64ShadowedBigPdeMask;
3828	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3829	uint64_t fGst64ShadowedBigPde4PteMask;
3830	/** @} */
3831
3832	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3833	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3834	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3835	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3836
3837	/** For saving stack space, the disassembler state is allocated here instead of
3838	* on the stack. */
3839	DISCPUSTATE DisState;
3840
3841	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3842	uint64_t cNetwareWp0Hacks;
3843
3844	/** Count the number of pgm pool access handler calls. */
3845	uint64_t cPoolAccessHandler;
3846
3847	/** @name Release Statistics
3848	* @{ */
3849	/** The number of times the guest has switched mode since last reset or statistics reset. */
3850	STAMCOUNTER cGuestModeChanges;
3851	/** The number of times the guest has switched mode since last reset or statistics reset. */
3852	STAMCOUNTER cA20Changes;
3853	/** @} */
3854
3855	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3856	/** @name Statistics
3857	* @{ */
3858	/** R0: Pointer to the statistics. */
3859	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3860	/** R0: Which statistic this \#PF should be attributed to. */
3861	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3862	/** R3: Pointer to the statistics. */
3863	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3864	/** Alignment padding. */
3865	RTR3PTR pPaddingR3;
3866	/** @} */
3867	#endif /* VBOX_WITH_STATISTICS */
3868	} PGMCPU;
3869	/** Pointer to the per-cpu PGM data. */
3870	typedef PGMCPU *PPGMCPU;
3871
3872
3873	/** @name PGM::fSyncFlags Flags
3874	* @note Was part of saved state a long time ago.
3875	* @{
3876	*/
3877	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3878	/** Always sync CR3. */
3879	#define PGM_SYNC_ALWAYS RT_BIT(1)
3880	/** Check monitoring on next CR3 (re)load and invalidate page.
3881	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3882	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3883	/** Check guest mapping in SyncCR3. */
3884	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3885	/** Clear the page pool (a light weight flush). */
3886	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3887	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3888	/** @} */
3889
3890
3891	/**
3892	* PGM GVM instance data.
3893	*/
3894	typedef struct PGMR0PERVM
3895	{
3896	/** @name PGM Pool related stuff.
3897	* @{ */
3898	/** Critical section for serializing pool growth. */
3899	RTCRITSECT PoolGrowCritSect;
3900	/** The memory objects for the pool pages. */
3901	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3902	/** The ring-3 mapping objects for the pool pages. */
3903	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3904	/** @} */
3905	} PGMR0PERVM;
3906
3907	RT_C_DECLS_BEGIN
3908
3909	#if defined(VBOX_STRICT) && defined(IN_RING3)
3910	int pgmLockDebug(PVMCC pVM, RT_SRC_POS_DECL);
3911	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
3912	#else
3913	int pgmLock(PVMCC pVM);
3914	#endif
3915	void pgmUnlock(PVM pVM);
3916	/**
3917	* Asserts that the caller owns the PDM lock.
3918	* This is the internal variant of PGMIsLockOwner.
3919	* @param a_pVM Pointer to the VM.
3920	*/
3921	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
3922	/**
3923	* Asserts that the caller owns the PDM lock.
3924	* This is the internal variant of PGMIsLockOwner.
3925	* @param a_pVM Pointer to the VM.
3926	* @param a_pVCpu The current CPU handle.
3927	*/
3928	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
3929
3930	#ifndef PGM_WITHOUT_MAPPINGS
3931	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3932	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3933	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3934	int pgmMapResolveConflicts(PVM pVM);
3935	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3936	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3937	#endif /* !PGM_WITHOUT_MAPPINGS */
3938
3939	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3940	RTRCPTR pvUserRC, R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3941	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3942	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3943	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
3944	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3945	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3946	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3947	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3948	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3949	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3950
3951	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3952	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3953	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3954	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3955	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3956	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3957	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3958	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3959	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3960	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3961	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3962	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3963	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3964	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3965	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3966	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3967	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3968	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3969	#ifndef IN_RING3
3970	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3971	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3972	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3973	#endif
3974	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3975	PGMPAGETYPE enmNewType);
3976	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3977	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3978	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
3979	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3980	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3981	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3982	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3983	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3984
3985	#ifdef IN_RING3
3986	void pgmR3PhysRelinkRamRanges(PVM pVM);
3987	int pgmR3PhysRamPreAllocate(PVM pVM);
3988	int pgmR3PhysRamReset(PVM pVM);
3989	int pgmR3PhysRomReset(PVM pVM);
3990	int pgmR3PhysRamZeroAll(PVM pVM);
3991	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3992	int pgmR3PhysRamTerm(PVM pVM);
3993	void pgmR3PhysRomTerm(PVM pVM);
3994	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3995
3996	int pgmR3PoolInit(PVM pVM);
3997	void pgmR3PoolRelocate(PVM pVM);
3998	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3999	void pgmR3PoolReset(PVM pVM);
4000	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4001	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4002	void pgmR3PoolWriteProtectPages(PVM pVM);
4003
4004	#endif /* IN_RING3 */
4005	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4006	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4007	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4008	# ifdef LOG_ENABLED
4009	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4010	# else
4011	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4012	# endif
4013	#endif
4014	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4015	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4016	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4017	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4018	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4019	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4020	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4021	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4022	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
4023	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
4024	bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys);
4025	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
4026	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4027	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4028	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4029	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4030	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4031	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4032	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4033	#ifndef IN_RING3
4034	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4035	#endif
4036
4037	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4038	void pgmPoolResetDirtyPages(PVMCC pVM);
4039	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4040
4041	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4042	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4043	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4044
4045	#ifndef PGM_WITHOUT_MAPPINGS
4046	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4047	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4048	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4049	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4050	#endif
4051
4052	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4053	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4054	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4055
4056	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
4057	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
4058	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4059	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
4060	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4061	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4062
4063	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4064	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4065	FNDBGCCMD pgmR3CmdShowSharedModules;
4066	# endif
4067
4068	void pgmLogState(PVM pVM);
4069
4070	RT_C_DECLS_END
4071
4072	/** @} */
4073
4074	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
4075

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 86461

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