PGMInternal.h@ 91016

Last change on this file since 91016 was 91016, checked in by vboxsync, 3 years ago
VMM/PGM,++: Kicked out VBOX_WITH_2X_4GB_ADDR_SPACE and the DynMap code used by it and raw-mode. Kept this around in case we wanted to reuse it for SMAP workarounds, but that's no longer needed. bugref:9517 bugref:9627
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 175.9 KB

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1	/* $Id: PGMInternal.h 91016 2021-08-31 01:23:53Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/hm_vmx.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/avl.h>
43	#include <iprt/critsect.h>
44	#include <iprt/list-off32.h>
45	#include <iprt/sha.h>
46
47
48
49	/** @defgroup grp_pgm_int Internals
50	* @ingroup grp_pgm
51	* @internal
52	* @{
53	*/
54
55
56	/** @name PGM Compile Time Config
57	* @{
58	*/
59
60	/**
61	* Indicates that there are no guest mappings in the shadow tables.
62	*
63	* Note! In ring-3 the macro is also used to exclude the managment of the
64	* intermediate context page tables. On 32-bit systems we use the intermediate
65	* context to support 64-bit guest execution. Thus, we cannot fully make it
66	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
67	*
68	* In raw-mode context there are by design always guest mappings (the code is
69	* executed from one), while in ring-0 there are none at all. Neither context
70	* manages the page tables for intermediate switcher context, that's all done in
71	* ring-3.
72	*
73	* Update 6.1: It is always defined now, in pgm.h
74	*/
75	#if defined(IN_RING0) \
76	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
77	&& ( HC_ARCH_BITS != 32 \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# undef PGM_WITHOUT_MAPPINGS
82	# define PGM_WITHOUT_MAPPINGS
83	#endif
84
85	/**
86	* Check and skip global PDEs for non-global flushes
87	*/
88	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
89
90	/**
91	* Optimization for PAE page tables that are modified often
92	*/
93	//#if 0 /* disabled again while debugging */
94	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	//#endif
96
97	/**
98	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
99	*/
100	#define PGM_WITH_LARGE_PAGES
101
102	/**
103	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
104	* VMX_EXIT_EPT_MISCONFIG.
105	*/
106	#define PGM_WITH_MMIO_OPTIMIZATIONS
107
108	/**
109	* Sync N pages instead of a whole page table
110	*/
111	#define PGM_SYNC_N_PAGES
112
113	/**
114	* Number of pages to sync during a page fault
115	*
116	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118	*
119	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120	* world switch overhead, so let's sync more.
121	*/
122	# ifdef IN_RING0
123	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125	* but ~5% fewer faults.
126	*/
127	# define PGM_SYNC_NR_PAGES 32
128	#else
129	# define PGM_SYNC_NR_PAGES 8
130	#endif
131
132	/**
133	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134	*/
135	#define PGM_MAX_PHYSCACHE_ENTRIES 64
136	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139	/** @def PGMPOOL_CFG_MAX_GROW
140	* The maximum number of pages to add to the pool in one go.
141	*/
142	#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
143
144	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
146	*/
147	#ifdef VBOX_STRICT
148	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149	#endif
150
151	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152	* Enables the experimental lazy page allocation code. */
153	#ifdef DOXYGEN_RUNNING
154	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155	#endif
156
157	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158	* Enables real write monitoring of pages, i.e. mapping them read-only and
159	* only making them writable when getting a write access \#PF. */
160	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162	/** @} */
163
164
165	/** @name PDPT and PML4 flags.
166	* These are placed in the three bits available for system programs in
167	* the PDPT and PML4 entries.
168	* @{ */
169	/** The entry is a permanent one and it's must always be present.
170	* Never free such an entry. */
171	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172	#ifndef PGM_WITHOUT_MAPPINGS
173	/** Mapping (hypervisor allocated pagetable). */
174	# define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
175	# define PGM_PML4_FLAGS RT_BIT_64(11)
176	#endif
177	/** PGM specific bits in PML4 entries. */
178	#define PGM_PML4_FLAGS 0
179	/** PGM specific bits in PDPT entries. */
180	#ifndef PGM_WITHOUT_MAPPINGS
181	# define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT \| PGM_PLXFLAGS_MAPPING)
182	#else
183	# define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
184	#endif
185	/** @} */
186
187	/** @name Page directory flags.
188	* These are placed in the three bits available for system programs in
189	* the page directory entries.
190	* @{ */
191	/** Indicates the original entry was a big page.
192	* @remarks This is currently only used for statistics and can be recycled. */
193	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
194	#ifndef PGM_WITHOUT_MAPPINGS
195	/** Mapping (hypervisor allocated pagetable). */
196	# define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
197	#endif
198	/** Made read-only to facilitate dirty bit tracking. */
199	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
200	/** @} */
201
202	/** @name Page flags.
203	* These are placed in the three bits available for system programs in
204	* the page entries.
205	* @{ */
206	/** Made read-only to facilitate dirty bit tracking. */
207	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
208
209	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
210	/** Scanned and approved by CSAM (tm).
211	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
212	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
213	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
214	#endif
215
216	/** @} */
217
218	/** @name Defines used to indicate the shadow and guest paging in the templates.
219	* @{ */
220	#define PGM_TYPE_REAL 1
221	#define PGM_TYPE_PROT 2
222	#define PGM_TYPE_32BIT 3
223	#define PGM_TYPE_PAE 4
224	#define PGM_TYPE_AMD64 5
225	#define PGM_TYPE_NESTED_32BIT 6
226	#define PGM_TYPE_NESTED_PAE 7
227	#define PGM_TYPE_NESTED_AMD64 8
228	#define PGM_TYPE_EPT 9
229	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
230	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
231	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
232	/** @} */
233
234	/** Macro for checking if the guest is using paging.
235	* @param uGstType PGM_TYPE_*
236	* @param uShwType PGM_TYPE_*
237	* @remark ASSUMES certain order of the PGM_TYPE_* values.
238	*/
239	#define PGM_WITH_PAGING(uGstType, uShwType) \
240	( (uGstType) >= PGM_TYPE_32BIT \
241	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
242
243	/** Macro for checking if the guest supports the NX bit.
244	* @param uGstType PGM_TYPE_*
245	* @param uShwType PGM_TYPE_*
246	* @remark ASSUMES certain order of the PGM_TYPE_* values.
247	*/
248	#define PGM_WITH_NX(uGstType, uShwType) \
249	( (uGstType) >= PGM_TYPE_PAE \
250	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
251
252	/** Macro for checking for nested or EPT.
253	* @param uType PGM_TYPE_*
254	*/
255	#define PGM_TYPE_IS_NESTED(uType) \
256	( (uType) == PGM_TYPE_NESTED_32BIT \
257	\|\| (uType) == PGM_TYPE_NESTED_PAE \
258	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
259
260	/** Macro for checking for nested or EPT.
261	* @param uType PGM_TYPE_*
262	*/
263	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
264	( (uType) == PGM_TYPE_NESTED_32BIT \
265	\|\| (uType) == PGM_TYPE_NESTED_PAE \
266	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
267	\|\| (uType) == PGM_TYPE_EPT)
268
269
270
271	/** @def PGM_HCPHYS_2_PTR
272	* Maps a HC physical page pool address to a virtual address.
273	*
274	* @returns VBox status code.
275	* @param pVM The cross context VM structure.
276	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
277	* @param HCPhys The HC physical address to map to a virtual one.
278	* @param ppv Where to store the virtual address. No need to cast
279	* this.
280	*
281	* @remark There is no need to assert on the result.
282	*/
283	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
284
285	/** @def PGM_GCPHYS_2_PTR_V2
286	* Maps a GC physical page address to a virtual address.
287	*
288	* @returns VBox status code.
289	* @param pVM The cross context VM structure.
290	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
291	* @param GCPhys The GC physical address to map to a virtual one.
292	* @param ppv Where to store the virtual address. No need to cast this.
293	*
294	* @remark Use with care as we don't have so much dynamic mapping space in
295	* ring-0 on 32-bit darwin and in RC.
296	* @remark There is no need to assert on the result.
297	*/
298	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
299	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
300
301	/** @def PGM_GCPHYS_2_PTR
302	* Maps a GC physical page address to a virtual address.
303	*
304	* @returns VBox status code.
305	* @param pVM The cross context VM structure.
306	* @param GCPhys The GC physical address to map to a virtual one.
307	* @param ppv Where to store the virtual address. No need to cast this.
308	*
309	* @remark Use with care as we don't have so much dynamic mapping space in
310	* ring-0 on 32-bit darwin and in RC.
311	* @remark There is no need to assert on the result.
312	*/
313	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
314
315	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
316	* Maps a GC physical page address to a virtual address.
317	*
318	* @returns VBox status code.
319	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
320	* @param GCPhys The GC physical address to map to a virtual one.
321	* @param ppv Where to store the virtual address. No need to cast this.
322	*
323	* @remark Use with care as we don't have so much dynamic mapping space in
324	* ring-0 on 32-bit darwin and in RC.
325	* @remark There is no need to assert on the result.
326	*/
327	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
328
329	/** @def PGM_GCPHYS_2_PTR_EX
330	* Maps a unaligned GC physical page address to a virtual address.
331	*
332	* @returns VBox status code.
333	* @param pVM The cross context VM structure.
334	* @param GCPhys The GC physical address to map to a virtual one.
335	* @param ppv Where to store the virtual address. No need to cast this.
336	*
337	* @remark Use with care as we don't have so much dynamic mapping space in
338	* ring-0 on 32-bit darwin and in RC.
339	* @remark There is no need to assert on the result.
340	*/
341	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
342	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
343
344	/** @def PGM_DYNMAP_UNUSED_HINT
345	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
346	* is no longer used.
347	*
348	* For best effect only apply this to the page that was mapped most recently.
349	*
350	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
351	* @param pvPage The pool page.
352	*/
353	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
354
355	/** @def PGM_DYNMAP_UNUSED_HINT_VM
356	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
357	* is no longer used.
358	*
359	* For best effect only apply this to the page that was mapped most recently.
360	*
361	* @param pVM The cross context VM structure.
362	* @param pvPage The pool page.
363	*/
364	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
365
366
367	/** @def PGM_INVL_PG
368	* Invalidates a page.
369	*
370	* @param pVCpu The cross context virtual CPU structure.
371	* @param GCVirt The virtual address of the page to invalidate.
372	*/
373	#ifdef IN_RING0
374	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
375	#elif defined(IN_RING3)
376	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
377	#else
378	# error "Not IN_RING0 or IN_RING3!"
379	#endif
380
381	/** @def PGM_INVL_PG_ALL_VCPU
382	* Invalidates a page on all VCPUs
383	*
384	* @param pVM The cross context VM structure.
385	* @param GCVirt The virtual address of the page to invalidate.
386	*/
387	#ifdef IN_RING0
388	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
389	#else
390	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
391	#endif
392
393	/** @def PGM_INVL_BIG_PG
394	* Invalidates a 4MB page directory entry.
395	*
396	* @param pVCpu The cross context virtual CPU structure.
397	* @param GCVirt The virtual address within the page directory to invalidate.
398	*/
399	#ifdef IN_RING0
400	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
401	#else
402	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
403	#endif
404
405	/** @def PGM_INVL_VCPU_TLBS()
406	* Invalidates the TLBs of the specified VCPU
407	*
408	* @param pVCpu The cross context virtual CPU structure.
409	*/
410	#ifdef IN_RING0
411	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
412	#else
413	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
414	#endif
415
416	/** @def PGM_INVL_ALL_VCPU_TLBS()
417	* Invalidates the TLBs of all VCPUs
418	*
419	* @param pVM The cross context VM structure.
420	*/
421	#ifdef IN_RING0
422	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
423	#else
424	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
425	#endif
426
427
428	/** @name Safer Shadow PAE PT/PTE
429	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
430	* present.
431	*
432	* @{
433	*/
434	#if 1
435	/**
436	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
437	* invalid entries for present.
438	* @sa X86PTEPAE.
439	*/
440	typedef union PGMSHWPTEPAE
441	{
442	/** Unsigned integer view */
443	X86PGPAEUINT uCareful;
444	/* Not other views. */
445	} PGMSHWPTEPAE;
446
447	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
448	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
449	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
450	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
451	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
452	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
453	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
454	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
455	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
456	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
457	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
458	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
459	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
461	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
462	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
463
464	/**
465	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
466	* invalid entries for present.
467	* @sa X86PTPAE.
468	*/
469	typedef struct PGMSHWPTPAE
470	{
471	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
472	} PGMSHWPTPAE;
473
474	#else
475	typedef X86PTEPAE PGMSHWPTEPAE;
476	typedef X86PTPAE PGMSHWPTPAE;
477	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
478	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
479	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
480	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
481	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
482	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
483	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
484	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
485	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
486	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
487	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
488	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
489	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
491	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
492	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
493
494	#endif
495
496	/** Pointer to a shadow PAE PTE. */
497	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
498	/** Pointer to a const shadow PAE PTE. */
499	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
500
501	/** Pointer to a shadow PAE page table. */
502	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
503	/** Pointer to a const shadow PAE page table. */
504	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
505	/** @} */
506
507	#ifndef PGM_WITHOUT_MAPPINGS
508
509	/** Size of the GCPtrConflict array in PGMMAPPING.
510	* @remarks Must be a power of two. */
511	# define PGMMAPPING_CONFLICT_MAX 8
512
513	/**
514	* Structure for tracking GC Mappings.
515	*
516	* This structure is used by linked list in both GC and HC.
517	*/
518	typedef struct PGMMAPPING
519	{
520	/** Pointer to next entry. */
521	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522	/** Pointer to next entry. */
523	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524	/** Indicate whether this entry is finalized. */
525	bool fFinalized;
526	bool afPadding[7];
527	/** Start Virtual address. */
528	RTGCPTR GCPtr;
529	/** Last Virtual address (inclusive). */
530	RTGCPTR GCPtrLast;
531	/** Range size (bytes). */
532	RTGCPTR cb;
533	/** Pointer to relocation callback function. */
534	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
535	/** User argument to the callback. */
536	R3PTRTYPE(void *) pvUser;
537	/** Mapping description / name. For easing debugging. */
538	R3PTRTYPE(const char *) pszDesc;
539	/** Last 8 addresses that caused conflicts. */
540	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
541	/** Number of conflicts for this hypervisor mapping. */
542	uint32_t cConflicts;
543	/** Number of page tables. */
544	uint32_t cPTs;
545
546	/** Array of page table mapping data. Each entry
547	* describes one page table. The array can be longer
548	* than the declared length.
549	*/
550	struct
551	{
552	/** The HC physical address of the page table. */
553	RTHCPHYS HCPhysPT;
554	/** The HC physical address of the first PAE page table. */
555	RTHCPHYS HCPhysPaePT0;
556	/** The HC physical address of the second PAE page table. */
557	RTHCPHYS HCPhysPaePT1;
558	/** The HC virtual address of the 32-bit page table. */
559	R3PTRTYPE(PX86PT) pPTR3;
560	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
561	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
562	/** The R0 virtual address of the 32-bit page table. */
563	R0PTRTYPE(PX86PT) pPTR0;
564	/** The R0 virtual address of the two PAE page table. */
565	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
566	} aPTs[1];
567	} PGMMAPPING;
568	/** Pointer to structure for tracking GC Mappings. */
569	typedef struct PGMMAPPING *PPGMMAPPING;
570
571	#endif /* !PGM_WITHOUT_MAPPINGS */
572
573
574	/**
575	* Physical page access handler type registration.
576	*/
577	typedef struct PGMPHYSHANDLERTYPEINT
578	{
579	/** Number of references. */
580	uint32_t volatile cRefs;
581	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
582	uint32_t u32Magic;
583	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
584	RTLISTOFF32NODE ListNode;
585	/** The kind of accesses we're handling. */
586	PGMPHYSHANDLERKIND enmKind;
587	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
588	uint32_t uState;
589	/** Pointer to R3 callback function. */
590	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
591	/** Pointer to R0 callback function. */
592	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
593	/** Pointer to R0 callback function for \#PFs. */
594	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
595	/** Description / Name. For easing debugging. */
596	R3PTRTYPE(const char *) pszDesc;
597	} PGMPHYSHANDLERTYPEINT;
598	/** Pointer to a physical access handler type registration. */
599	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
600	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
601	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
602	/** Magic value for the physical handler callbacks. */
603	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
604
605	/**
606	* Converts a handle to a pointer.
607	* @returns PPGMPHYSHANDLERTYPEINT
608	* @param a_pVM The cross context VM structure.
609	* @param a_hType Physical access handler type handle.
610	*/
611	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
612
613
614	/**
615	* Physical page access handler structure.
616	*
617	* This is used to keep track of physical address ranges
618	* which are being monitored in some kind of way.
619	*/
620	typedef struct PGMPHYSHANDLER
621	{
622	AVLROGCPHYSNODECORE Core;
623	/** Number of pages to update. */
624	uint32_t cPages;
625	/** Set if we have pages that have been aliased. */
626	uint32_t cAliasedPages;
627	/** Set if we have pages that have temporarily been disabled. */
628	uint32_t cTmpOffPages;
629	/** Registered handler type handle (heap offset). */
630	PGMPHYSHANDLERTYPE hType;
631	/** User argument for R3 handlers. */
632	R3PTRTYPE(void *) pvUserR3;
633	/** User argument for R0 handlers. */
634	R0PTRTYPE(void *) pvUserR0;
635	/** Description / Name. For easing debugging. */
636	R3PTRTYPE(const char *) pszDesc;
637	#ifdef VBOX_WITH_STATISTICS
638	/** Profiling of this handler. */
639	STAMPROFILE Stat;
640	#endif
641	} PGMPHYSHANDLER;
642	/** Pointer to a physical page access handler structure. */
643	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
644
645	/**
646	* Gets the type record for a physical handler (no reference added).
647	* @returns PPGMPHYSHANDLERTYPEINT
648	* @param a_pVM The cross context VM structure.
649	* @param a_pPhysHandler Pointer to the physical handler structure
650	* (PGMPHYSHANDLER).
651	*/
652	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
653
654
655	/**
656	* A Physical Guest Page tracking structure.
657	*
658	* The format of this structure is complicated because we have to fit a lot
659	* of information into as few bits as possible. The format is also subject
660	* to change (there is one coming up soon). Which means that for we'll be
661	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
662	* accesses to the structure.
663	*/
664	typedef union PGMPAGE
665	{
666	/** Structured view. */
667	struct
668	{
669	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
670	uint64_t u2HandlerPhysStateY : 2;
671	/** 3:2 - Paging structure needed to map the page
672	* (PGM_PAGE_PDE_TYPE_). /
673	uint64_t u2PDETypeY : 2;
674	/** 4 - Unused (was used by FTE for dirty tracking). */
675	uint64_t fUnused1 : 1;
676	/** 5 - Flag indicating that a write monitored page was written to
677	* when set. */
678	uint64_t fWrittenToY : 1;
679	/** 7:6 - Unused. */
680	uint64_t u2Unused0 : 2;
681	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
682	uint64_t u2Unused1 : 2;
683	/** 11:10 - NEM state bits. */
684	uint64_t u2NemStateY : 2;
685	/** 12:48 - The host physical frame number (shift left to get the
686	* address). */
687	uint64_t HCPhysFN : 36;
688	/** 50:48 - The page state. */
689	uint64_t uStateY : 3;
690	/** 51:53 - The page type (PGMPAGETYPE). */
691	uint64_t uTypeY : 3;
692	/** 63:54 - PTE index for usage tracking (page pool). */
693	uint64_t u10PteIdx : 10;
694
695	/** The GMM page ID.
696	* @remarks In the current implementation, MMIO2 and pages aliased to
697	* MMIO2 pages will be exploiting this field to calculate the
698	* ring-3 mapping address corresponding to the page.
699	* Later we may consider including MMIO2 management into GMM. */
700	uint32_t idPage;
701	/** Usage tracking (page pool). */
702	uint16_t u16TrackingY;
703	/** The number of read locks on this page. */
704	uint8_t cReadLocksY;
705	/** The number of write locks on this page. */
706	uint8_t cWriteLocksY;
707	} s;
708
709	/** 64-bit integer view. */
710	uint64_t au64[2];
711	/** 16-bit view. */
712	uint32_t au32[4];
713	/** 16-bit view. */
714	uint16_t au16[8];
715	/** 8-bit view. */
716	uint8_t au8[16];
717	} PGMPAGE;
718	AssertCompileSize(PGMPAGE, 16);
719	/** Pointer to a physical guest page. */
720	typedef PGMPAGE *PPGMPAGE;
721	/** Pointer to a const physical guest page. */
722	typedef const PGMPAGE *PCPGMPAGE;
723	/** Pointer to a physical guest page pointer. */
724	typedef PPGMPAGE *PPPGMPAGE;
725
726
727	/**
728	* Clears the page structure.
729	* @param a_pPage Pointer to the physical guest page tracking structure.
730	*/
731	#define PGM_PAGE_CLEAR(a_pPage) \
732	do { \
733	(a_pPage)->au64[0] = 0; \
734	(a_pPage)->au64[1] = 0; \
735	} while (0)
736
737	/**
738	* Initializes the page structure.
739	* @param a_pPage Pointer to the physical guest page tracking structure.
740	* @param a_HCPhys The host physical address of the page.
741	* @param a_idPage The (GMM) page ID of the page.
742	* @param a_uType The page type (PGMPAGETYPE).
743	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
744	*/
745	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
746	do { \
747	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
748	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
749	(a_pPage)->au64[0] = SetHCPhysTmp; \
750	(a_pPage)->au64[1] = 0; \
751	(a_pPage)->s.idPage = (a_idPage); \
752	(a_pPage)->s.uStateY = (a_uState); \
753	(a_pPage)->s.uTypeY = (a_uType); \
754	} while (0)
755
756	/**
757	* Initializes the page structure of a ZERO page.
758	* @param a_pPage Pointer to the physical guest page tracking structure.
759	* @param a_pVM The VM handle (for getting the zero page address).
760	* @param a_uType The page type (PGMPAGETYPE).
761	*/
762	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
763	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
764
765
766	/** @name The Page state, PGMPAGE::uStateY.
767	* @{ */
768	/** The zero page.
769	* This is a per-VM page that's never ever mapped writable. */
770	#define PGM_PAGE_STATE_ZERO 0U
771	/** A allocated page.
772	* This is a per-VM page allocated from the page pool (or wherever
773	* we get MMIO2 pages from if the type is MMIO2).
774	*/
775	#define PGM_PAGE_STATE_ALLOCATED 1U
776	/** A allocated page that's being monitored for writes.
777	* The shadow page table mappings are read-only. When a write occurs, the
778	* fWrittenTo member is set, the page remapped as read-write and the state
779	* moved back to allocated. */
780	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
781	/** The page is shared, aka. copy-on-write.
782	* This is a page that's shared with other VMs. */
783	#define PGM_PAGE_STATE_SHARED 3U
784	/** The page is ballooned, so no longer available for this VM. */
785	#define PGM_PAGE_STATE_BALLOONED 4U
786	/** @} */
787
788
789	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
790	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
791	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
792	#else
793	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
794	#endif
795
796	/**
797	* Gets the page state.
798	* @returns page state (PGM_PAGE_STATE_*).
799	* @param a_pPage Pointer to the physical guest page tracking structure.
800	*
801	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
802	* builds.
803	*/
804	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
805	#if defined(__GNUC__) && defined(VBOX_STRICT)
806	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
807	#else
808	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
809	#endif
810
811	/**
812	* Sets the page state.
813	* @param a_pVM The VM handle, only used for lock ownership assertions.
814	* @param a_pPage Pointer to the physical guest page tracking structure.
815	* @param a_uState The new page state.
816	*/
817	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
818	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
819
820
821	/**
822	* Gets the host physical address of the guest page.
823	* @returns host physical address (RTHCPHYS).
824	* @param a_pPage Pointer to the physical guest page tracking structure.
825	*
826	* @remarks In strict builds on gcc platforms, this macro will make some ugly
827	* assumption about a valid pVM variable/parameter being in the
828	* current context. It will use this pVM variable to assert that the
829	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
830	* pVM is not around.
831	*/
832	#if 0
833	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
834	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
835	#else
836	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
837	# if defined(__GNUC__) && defined(VBOX_STRICT)
838	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
839	# else
840	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
841	# endif
842	#endif
843
844	/**
845	* Sets the host physical address of the guest page.
846	*
847	* @param a_pVM The VM handle, only used for lock ownership assertions.
848	* @param a_pPage Pointer to the physical guest page tracking structure.
849	* @param a_HCPhys The new host physical address.
850	*/
851	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
852	do { \
853	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
854	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
855	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
856	PGM_PAGE_ASSERT_LOCK(a_pVM); \
857	} while (0)
858
859	/**
860	* Get the Page ID.
861	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
862	* @param a_pPage Pointer to the physical guest page tracking structure.
863	*/
864	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
865
866	/**
867	* Sets the Page ID.
868	* @param a_pVM The VM handle, only used for lock ownership assertions.
869	* @param a_pPage Pointer to the physical guest page tracking structure.
870	* @param a_idPage The new page ID.
871	*/
872	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
873	do { \
874	(a_pPage)->s.idPage = (a_idPage); \
875	PGM_PAGE_ASSERT_LOCK(a_pVM); \
876	} while (0)
877
878	/**
879	* Get the Chunk ID.
880	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
881	* @param a_pPage Pointer to the physical guest page tracking structure.
882	*/
883	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
884
885	/**
886	* Get the index of the page within the allocation chunk.
887	* @returns The page index.
888	* @param a_pPage Pointer to the physical guest page tracking structure.
889	*/
890	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
891
892	/**
893	* Gets the page type.
894	* @returns The page type.
895	* @param a_pPage Pointer to the physical guest page tracking structure.
896	*
897	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
898	* builds.
899	*/
900	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
901	#if defined(__GNUC__) && defined(VBOX_STRICT)
902	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
903	#else
904	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
905	#endif
906
907	/**
908	* Sets the page type.
909	*
910	* @param a_pVM The VM handle, only used for lock ownership assertions.
911	* @param a_pPage Pointer to the physical guest page tracking structure.
912	* @param a_enmType The new page type (PGMPAGETYPE).
913	*/
914	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
915	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
916
917	/**
918	* Gets the page table index
919	* @returns The page table index.
920	* @param a_pPage Pointer to the physical guest page tracking structure.
921	*/
922	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
923
924	/**
925	* Sets the page table index.
926	* @param a_pVM The VM handle, only used for lock ownership assertions.
927	* @param a_pPage Pointer to the physical guest page tracking structure.
928	* @param a_iPte New page table index.
929	*/
930	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
931	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
932
933	/**
934	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
935	* @returns true/false.
936	* @param a_pPage Pointer to the physical guest page tracking structure.
937	*/
938	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
939
940	/**
941	* Checks if the page is marked for MMIO, including both aliases.
942	* @returns true/false.
943	* @param a_pPage Pointer to the physical guest page tracking structure.
944	*/
945	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
946	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
947	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
948	)
949
950	/**
951	* Checks if the page is marked for MMIO, including special aliases.
952	* @returns true/false.
953	* @param a_pPage Pointer to the physical guest page tracking structure.
954	*/
955	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
956	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
957
958	/**
959	* Checks if the page is a special aliased MMIO page.
960	* @returns true/false.
961	* @param a_pPage Pointer to the physical guest page tracking structure.
962	*/
963	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
964
965	/**
966	* Checks if the page is backed by the ZERO page.
967	* @returns true/false.
968	* @param a_pPage Pointer to the physical guest page tracking structure.
969	*/
970	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
971
972	/**
973	* Checks if the page is backed by a SHARED page.
974	* @returns true/false.
975	* @param a_pPage Pointer to the physical guest page tracking structure.
976	*/
977	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
978
979	/**
980	* Checks if the page is ballooned.
981	* @returns true/false.
982	* @param a_pPage Pointer to the physical guest page tracking structure.
983	*/
984	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
985
986	/**
987	* Checks if the page is allocated.
988	* @returns true/false.
989	* @param a_pPage Pointer to the physical guest page tracking structure.
990	*/
991	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
992
993	/**
994	* Marks the page as written to (for GMM change monitoring).
995	* @param a_pVM The VM handle, only used for lock ownership assertions.
996	* @param a_pPage Pointer to the physical guest page tracking structure.
997	*/
998	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
999	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1000
1001	/**
1002	* Clears the written-to indicator.
1003	* @param a_pVM The VM handle, only used for lock ownership assertions.
1004	* @param a_pPage Pointer to the physical guest page tracking structure.
1005	*/
1006	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1007	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1008
1009	/**
1010	* Checks if the page was marked as written-to.
1011	* @returns true/false.
1012	* @param a_pPage Pointer to the physical guest page tracking structure.
1013	*/
1014	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1015
1016
1017	/** @name PT usage values (PGMPAGE::u2PDEType).
1018	*
1019	* @{ */
1020	/** Either as a PT or PDE. */
1021	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1022	/** Must use a page table to map the range. */
1023	#define PGM_PAGE_PDE_TYPE_PT 1
1024	/** Can use a page directory entry to map the continuous range. */
1025	#define PGM_PAGE_PDE_TYPE_PDE 2
1026	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1027	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1028	/** @} */
1029
1030	/**
1031	* Set the PDE type of the page
1032	* @param a_pVM The VM handle, only used for lock ownership assertions.
1033	* @param a_pPage Pointer to the physical guest page tracking structure.
1034	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1035	*/
1036	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1037	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1038
1039	/**
1040	* Checks if the page was marked being part of a large page
1041	* @returns true/false.
1042	* @param a_pPage Pointer to the physical guest page tracking structure.
1043	*/
1044	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1045
1046	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1047	*
1048	* @remarks The values are assigned in order of priority, so we can calculate
1049	* the correct state for a page with different handlers installed.
1050	* @{ */
1051	/** No handler installed. */
1052	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1053	/** Monitoring is temporarily disabled. */
1054	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1055	/** Write access is monitored. */
1056	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1057	/** All access is monitored. */
1058	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1059	/** @} */
1060
1061	/**
1062	* Gets the physical access handler state of a page.
1063	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1064	* @param a_pPage Pointer to the physical guest page tracking structure.
1065	*/
1066	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1067
1068	/**
1069	* Sets the physical access handler state of a page.
1070	* @param a_pPage Pointer to the physical guest page tracking structure.
1071	* @param a_uState The new state value.
1072	*/
1073	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1074	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1075
1076	/**
1077	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1078	* @returns true/false
1079	* @param a_pPage Pointer to the physical guest page tracking structure.
1080	*/
1081	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1082	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1083
1084	/**
1085	* Checks if the page has any active physical access handlers.
1086	* @returns true/false
1087	* @param a_pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1090	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1091
1092	/**
1093	* Checks if the page has any access handlers, including temporarily disabled ones.
1094	* @returns true/false
1095	* @param a_pPage Pointer to the physical guest page tracking structure.
1096	*/
1097	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1098	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1099
1100	/**
1101	* Checks if the page has any active access handlers.
1102	* @returns true/false
1103	* @param a_pPage Pointer to the physical guest page tracking structure.
1104	*/
1105	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1106	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1107
1108	/**
1109	* Checks if the page has any active access handlers catching all accesses.
1110	* @returns true/false
1111	* @param a_pPage Pointer to the physical guest page tracking structure.
1112	*/
1113	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1114	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1115
1116
1117	/** @def PGM_PAGE_GET_TRACKING
1118	* Gets the packed shadow page pool tracking data associated with a guest page.
1119	* @returns uint16_t containing the data.
1120	* @param a_pPage Pointer to the physical guest page tracking structure.
1121	*/
1122	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1123	#if defined(__GNUC__) && defined(VBOX_STRICT)
1124	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1125	#else
1126	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1127	#endif
1128
1129	/** @def PGM_PAGE_SET_TRACKING
1130	* Sets the packed shadow page pool tracking data associated with a guest page.
1131	* @param a_pVM The VM handle, only used for lock ownership assertions.
1132	* @param a_pPage Pointer to the physical guest page tracking structure.
1133	* @param a_u16TrackingData The tracking data to store.
1134	*/
1135	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1136	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1137
1138	/** @def PGM_PAGE_GET_TD_CREFS
1139	* Gets the @a cRefs tracking data member.
1140	* @returns cRefs.
1141	* @param a_pPage Pointer to the physical guest page tracking structure.
1142	*/
1143	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1144	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1145	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1146	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1147
1148	/** @def PGM_PAGE_GET_TD_IDX
1149	* Gets the @a idx tracking data member.
1150	* @returns idx.
1151	* @param a_pPage Pointer to the physical guest page tracking structure.
1152	*/
1153	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1154	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1155	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1156	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1157
1158
1159	/** Max number of locks on a page. */
1160	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1161
1162	/** Get the read lock count.
1163	* @returns count.
1164	* @param a_pPage Pointer to the physical guest page tracking structure.
1165	*/
1166	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1167
1168	/** Get the write lock count.
1169	* @returns count.
1170	* @param a_pPage Pointer to the physical guest page tracking structure.
1171	*/
1172	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1173
1174	/** Decrement the read lock counter.
1175	* @param a_pPage Pointer to the physical guest page tracking structure.
1176	*/
1177	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1178
1179	/** Decrement the write lock counter.
1180	* @param a_pPage Pointer to the physical guest page tracking structure.
1181	*/
1182	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1183
1184	/** Increment the read lock counter.
1185	* @param a_pPage Pointer to the physical guest page tracking structure.
1186	*/
1187	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1188
1189	/** Increment the write lock counter.
1190	* @param a_pPage Pointer to the physical guest page tracking structure.
1191	*/
1192	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1193
1194
1195	/** Gets the NEM state.
1196	* @returns NEM state value (two bits).
1197	* @param a_pPage Pointer to the physical guest page tracking structure.
1198	*/
1199	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1200
1201	/** Sets the NEM state.
1202	* @param a_pPage Pointer to the physical guest page tracking structure.
1203	* @param a_u2State The NEM state value (specific to NEM impl.).
1204	*/
1205	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1206	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1207
1208
1209	#if 0
1210	/** Enables sanity checking of write monitoring using CRC-32. */
1211	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1212	#endif
1213
1214	/**
1215	* Per page live save tracking data.
1216	*/
1217	typedef struct PGMLIVESAVERAMPAGE
1218	{
1219	/** Number of times it has been dirtied. */
1220	uint32_t cDirtied : 24;
1221	/** Whether it is currently dirty. */
1222	uint32_t fDirty : 1;
1223	/** Ignore the page.
1224	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1225	* deal with these after pausing the VM and DevPCI have said it bit about
1226	* remappings. */
1227	uint32_t fIgnore : 1;
1228	/** Was a ZERO page last time around. */
1229	uint32_t fZero : 1;
1230	/** Was a SHARED page last time around. */
1231	uint32_t fShared : 1;
1232	/** Whether the page is/was write monitored in a previous pass. */
1233	uint32_t fWriteMonitored : 1;
1234	/** Whether the page is/was write monitored earlier in this pass. */
1235	uint32_t fWriteMonitoredJustNow : 1;
1236	/** Bits reserved for future use. */
1237	uint32_t u2Reserved : 2;
1238	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1239	/** CRC-32 for the page. This is for internal consistency checks. */
1240	uint32_t u32Crc;
1241	#endif
1242	} PGMLIVESAVERAMPAGE;
1243	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1244	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1245	#else
1246	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1247	#endif
1248	/** Pointer to the per page live save tracking data. */
1249	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1250
1251	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1252	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1253
1254
1255	/**
1256	* RAM range for GC Phys to HC Phys conversion.
1257	*
1258	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1259	* conversions too, but we'll let MM handle that for now.
1260	*
1261	* This structure is used by linked lists in both GC and HC.
1262	*/
1263	typedef struct PGMRAMRANGE
1264	{
1265	/** Start of the range. Page aligned. */
1266	RTGCPHYS GCPhys;
1267	/** Size of the range. (Page aligned of course). */
1268	RTGCPHYS cb;
1269	/** Pointer to the next RAM range - for R3. */
1270	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1271	/** Pointer to the next RAM range - for R0. */
1272	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1273	/** PGM_RAM_RANGE_FLAGS_* flags. */
1274	uint32_t fFlags;
1275	uint32_t fPadding1;
1276	/** Last address in the range (inclusive). Page aligned (-1). */
1277	RTGCPHYS GCPhysLast;
1278	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1279	R3PTRTYPE(void *) pvR3;
1280	/** Live save per page tracking data. */
1281	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1282	/** The range description. */
1283	R3PTRTYPE(const char *) pszDesc;
1284	/** Pointer to self - R0 pointer. */
1285	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1286
1287	/** Pointer to the left search three node - ring-3 context. */
1288	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1289	/** Pointer to the right search three node - ring-3 context. */
1290	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1291	/** Pointer to the left search three node - ring-0 context. */
1292	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1293	/** Pointer to the right search three node - ring-0 context. */
1294	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1295
1296	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1297	#if HC_ARCH_BITS == 32
1298	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1299	#endif
1300	/** Array of physical guest page tracking structures. */
1301	PGMPAGE aPages[1];
1302	} PGMRAMRANGE;
1303	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1304	typedef PGMRAMRANGE *PPGMRAMRANGE;
1305
1306	/** @name PGMRAMRANGE::fFlags
1307	* @{ */
1308	/** The RAM range is floating around as an independent guest mapping. */
1309	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1310	/** Ad hoc RAM range for an ROM mapping. */
1311	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1312	/** Ad hoc RAM range for an MMIO mapping. */
1313	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1314	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1315	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1316	/** @} */
1317
1318	/** Tests if a RAM range is an ad hoc one or not.
1319	* @returns true/false.
1320	* @param pRam The RAM range.
1321	*/
1322	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1323	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1324
1325	/** The number of entries in the RAM range TLBs (there is one for each
1326	* context). Must be a power of two. */
1327	#define PGM_RAMRANGE_TLB_ENTRIES 8
1328
1329	/**
1330	* Calculates the RAM range TLB index for the physical address.
1331	*
1332	* @returns RAM range TLB index.
1333	* @param a_GCPhys The guest physical address.
1334	*/
1335	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1336
1337
1338
1339	/**
1340	* Per page tracking structure for ROM image.
1341	*
1342	* A ROM image may have a shadow page, in which case we may have two pages
1343	* backing it. This structure contains the PGMPAGE for both while
1344	* PGMRAMRANGE have a copy of the active one. It is important that these
1345	* aren't out of sync in any regard other than page pool tracking data.
1346	*/
1347	typedef struct PGMROMPAGE
1348	{
1349	/** The page structure for the virgin ROM page. */
1350	PGMPAGE Virgin;
1351	/** The page structure for the shadow RAM page. */
1352	PGMPAGE Shadow;
1353	/** The current protection setting. */
1354	PGMROMPROT enmProt;
1355	/** Live save status information. Makes use of unused alignment space. */
1356	struct
1357	{
1358	/** The previous protection value. */
1359	uint8_t u8Prot;
1360	/** Written to flag set by the handler. */
1361	bool fWrittenTo;
1362	/** Whether the shadow page is dirty or not. */
1363	bool fDirty;
1364	/** Whether it was dirtied in the recently. */
1365	bool fDirtiedRecently;
1366	} LiveSave;
1367	} PGMROMPAGE;
1368	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1369	/** Pointer to a ROM page tracking structure. */
1370	typedef PGMROMPAGE *PPGMROMPAGE;
1371
1372
1373	/**
1374	* A registered ROM image.
1375	*
1376	* This is needed to keep track of ROM image since they generally intrude
1377	* into a PGMRAMRANGE. It also keeps track of additional info like the
1378	* two page sets (read-only virgin and read-write shadow), the current
1379	* state of each page.
1380	*
1381	* Because access handlers cannot easily be executed in a different
1382	* context, the ROM ranges needs to be accessible and in all contexts.
1383	*/
1384	typedef struct PGMROMRANGE
1385	{
1386	/** Pointer to the next range - R3. */
1387	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1388	/** Pointer to the next range - R0. */
1389	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1390	/** Address of the range. */
1391	RTGCPHYS GCPhys;
1392	/** Address of the last byte in the range. */
1393	RTGCPHYS GCPhysLast;
1394	/** Size of the range. */
1395	RTGCPHYS cb;
1396	/** The flags (PGMPHYS_ROM_FLAGS_). /
1397	uint32_t fFlags;
1398	/** The saved state range ID. */
1399	uint8_t idSavedState;
1400	/** Alignment padding. */
1401	uint8_t au8Alignment[3];
1402	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1403	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1404	/** The size bits pvOriginal points to. */
1405	uint32_t cbOriginal;
1406	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1407	* This is used for strictness checks. */
1408	R3PTRTYPE(const void *) pvOriginal;
1409	/** The ROM description. */
1410	R3PTRTYPE(const char *) pszDesc;
1411	/** The per page tracking structures. */
1412	PGMROMPAGE aPages[1];
1413	} PGMROMRANGE;
1414	/** Pointer to a ROM range. */
1415	typedef PGMROMRANGE *PPGMROMRANGE;
1416
1417
1418	/**
1419	* Live save per page data for an MMIO2 page.
1420	*
1421	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1422	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1423	* CRC-32 for detecting changes as well as special handling of zero pages. This
1424	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1425	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1426	* because of speed (2.5x and 6x slower).)
1427	*
1428	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1429	* save but normally is disabled. Since we can write monitor guest
1430	* accesses on our own, we only need this for host accesses. Shouldn't be
1431	* too difficult for DevVGA, VMMDev might be doable, the planned
1432	* networking fun will be fun since it involves ring-0.
1433	*/
1434	typedef struct PGMLIVESAVEMMIO2PAGE
1435	{
1436	/** Set if the page is considered dirty. */
1437	bool fDirty;
1438	/** The number of scans this page has remained unchanged for.
1439	* Only updated for dirty pages. */
1440	uint8_t cUnchangedScans;
1441	/** Whether this page was zero at the last scan. */
1442	bool fZero;
1443	/** Alignment padding. */
1444	bool fReserved;
1445	/** CRC-32 for the first half of the page.
1446	* This is used together with u32CrcH2 to quickly detect changes in the page
1447	* during the non-final passes. */
1448	uint32_t u32CrcH1;
1449	/** CRC-32 for the second half of the page. */
1450	uint32_t u32CrcH2;
1451	/** SHA-1 for the saved page.
1452	* This is used in the final pass to skip pages without changes. */
1453	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1454	} PGMLIVESAVEMMIO2PAGE;
1455	/** Pointer to a live save status data for an MMIO2 page. */
1456	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1457
1458	/**
1459	* A registered MMIO2 (= Device RAM) range.
1460	*
1461	* There are a few reason why we need to keep track of these registrations. One
1462	* of them is the deregistration & cleanup stuff, while another is that the
1463	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1464	* range list.
1465	*
1466	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1467	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1468	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1469	* overlap we will free all the existing RAM pages and put in the ram range
1470	* pages instead.
1471	*/
1472	typedef struct PGMREGMMIO2RANGE
1473	{
1474	/** The owner of the range. (a device) */
1475	PPDMDEVINSR3 pDevInsR3;
1476	/** Pointer to the ring-3 mapping of the allocation. */
1477	RTR3PTR pvR3;
1478	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1479	/** Pointer to the ring-0 mapping of the allocation. */
1480	RTR0PTR pvR0;
1481	#endif
1482	/** Pointer to the next range - R3. */
1483	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1484	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1485	uint16_t fFlags;
1486	/** The sub device number (internal PCI config (CFGM) number). */
1487	uint8_t iSubDev;
1488	/** The PCI region number. */
1489	uint8_t iRegion;
1490	/** The saved state range ID. */
1491	uint8_t idSavedState;
1492	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1493	uint8_t idMmio2;
1494	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1495	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1496	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1497	#else
1498	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1499	#endif
1500	/** The real size.
1501	* This may be larger than indicated by RamRange.cb if the range has been
1502	* reduced during saved state loading. */
1503	RTGCPHYS cbReal;
1504	/** Pointer to the physical handler for MMIO. */
1505	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1506	/** Live save per page tracking data for MMIO2. */
1507	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1508	/** The associated RAM range. */
1509	PGMRAMRANGE RamRange;
1510	} PGMREGMMIO2RANGE;
1511	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1512	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1513	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1514
1515	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1516	* @{ */
1517	/** Set if it's an MMIO2 range.
1518	* @note Historical. For a while we did some of the MMIO this way too. */
1519	#define PGMREGMMIO2RANGE_F_MMIO2 UINT16_C(0x0001)
1520	/** Set if this is the first chunk in the MMIO2 range. */
1521	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1522	/** Set if this is the last chunk in the MMIO2 range. */
1523	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0004)
1524	/** Set if the whole range is mapped. */
1525	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0008)
1526	/** Set if it's overlapping, clear if not. */
1527	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0010)
1528	/** @} */
1529
1530
1531	/** @name Internal MMIO2 constants.
1532	* @{ */
1533	/** The maximum number of MMIO2 ranges. */
1534	#define PGM_MMIO2_MAX_RANGES 32
1535	/** The maximum number of pages in a MMIO2 range. */
1536	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1537	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1538	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1539	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1540	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1541	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1542	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1543	/** @} */
1544
1545
1546
1547	/**
1548	* PGMPhysRead/Write cache entry
1549	*/
1550	typedef struct PGMPHYSCACHEENTRY
1551	{
1552	/** R3 pointer to physical page. */
1553	R3PTRTYPE(uint8_t *) pbR3;
1554	/** GC Physical address for cache entry */
1555	RTGCPHYS GCPhys;
1556	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1557	RTGCPHYS u32Padding0; /*< alignment padding. /
1558	#endif
1559	} PGMPHYSCACHEENTRY;
1560
1561	/**
1562	* PGMPhysRead/Write cache to reduce REM memory access overhead
1563	*/
1564	typedef struct PGMPHYSCACHE
1565	{
1566	/** Bitmap of valid cache entries */
1567	uint64_t aEntries;
1568	/** Cache entries */
1569	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1570	} PGMPHYSCACHE;
1571
1572
1573	/** @name Ring-3 page mapping TLBs
1574	* @{ */
1575
1576	/** Pointer to an allocation chunk ring-3 mapping. */
1577	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1578	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1579	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1580
1581	/**
1582	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1583	*
1584	* The primary tree (Core) uses the chunk id as key.
1585	*/
1586	typedef struct PGMCHUNKR3MAP
1587	{
1588	/** The key is the chunk id. */
1589	AVLU32NODECORE Core;
1590	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1591	* selection. */
1592	uint32_t iLastUsed;
1593	/** The current reference count. */
1594	uint32_t volatile cRefs;
1595	/** The current permanent reference count. */
1596	uint32_t volatile cPermRefs;
1597	/** The mapping address. */
1598	void *pv;
1599	} PGMCHUNKR3MAP;
1600
1601	/**
1602	* Allocation chunk ring-3 mapping TLB entry.
1603	*/
1604	typedef struct PGMCHUNKR3MAPTLBE
1605	{
1606	/** The chunk id. */
1607	uint32_t volatile idChunk;
1608	#if HC_ARCH_BITS == 64
1609	uint32_t u32Padding; /*< alignment padding. /
1610	#endif
1611	/** The chunk map. */
1612	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1613	} PGMCHUNKR3MAPTLBE;
1614	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1615	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1616
1617	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1618	* @remark Must be a power of two value. */
1619	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1620
1621	/**
1622	* Allocation chunk ring-3 mapping TLB.
1623	*
1624	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1625	* At first glance this might look kinda odd since AVL trees are
1626	* supposed to give the most optimal lookup times of all trees
1627	* due to their balancing. However, take a tree with 1023 nodes
1628	* in it, that's 10 levels, meaning that most searches has to go
1629	* down 9 levels before they find what they want. This isn't fast
1630	* compared to a TLB hit. There is the factor of cache misses,
1631	* and of course the problem with trees and branch prediction.
1632	* This is why we use TLBs in front of most of the trees.
1633	*
1634	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1635	* difficult when we switch to the new inlined AVL trees (from kStuff).
1636	*/
1637	typedef struct PGMCHUNKR3MAPTLB
1638	{
1639	/** The TLB entries. */
1640	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1641	} PGMCHUNKR3MAPTLB;
1642
1643	/**
1644	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1645	* @returns Chunk TLB index.
1646	* @param idChunk The Chunk ID.
1647	*/
1648	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1649
1650
1651	/**
1652	* Ring-3 guest page mapping TLB entry.
1653	* @remarks used in ring-0 as well at the moment.
1654	*/
1655	typedef struct PGMPAGER3MAPTLBE
1656	{
1657	/** Address of the page. */
1658	RTGCPHYS volatile GCPhys;
1659	/** The guest page. */
1660	R3PTRTYPE(PPGMPAGE) volatile pPage;
1661	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1662	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1663	/** The address */
1664	R3PTRTYPE(void *) volatile pv;
1665	#if HC_ARCH_BITS == 32
1666	uint32_t u32Padding; /*< alignment padding. /
1667	#endif
1668	} PGMPAGER3MAPTLBE;
1669	/** Pointer to an entry in the HC physical TLB. */
1670	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1671
1672
1673	/** The number of entries in the ring-3 guest page mapping TLB.
1674	* @remarks The value must be a power of two. */
1675	#define PGM_PAGER3MAPTLB_ENTRIES 256
1676
1677	/**
1678	* Ring-3 guest page mapping TLB.
1679	* @remarks used in ring-0 as well at the moment.
1680	*/
1681	typedef struct PGMPAGER3MAPTLB
1682	{
1683	/** The TLB entries. */
1684	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1685	} PGMPAGER3MAPTLB;
1686	/** Pointer to the ring-3 guest page mapping TLB. */
1687	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1688
1689	/**
1690	* Calculates the index of the TLB entry for the specified guest page.
1691	* @returns Physical TLB index.
1692	* @param GCPhys The guest physical address.
1693	*/
1694	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1695
1696	/** @} */
1697
1698
1699	/** @name Ring-0 page mapping TLB
1700	* @{ */
1701	/**
1702	* Ring-0 guest page mapping TLB entry.
1703	*/
1704	typedef struct PGMPAGER0MAPTLBE
1705	{
1706	/** Address of the page. */
1707	RTGCPHYS volatile GCPhys;
1708	/** The guest page. */
1709	R0PTRTYPE(PPGMPAGE) volatile pPage;
1710	/** The address */
1711	R0PTRTYPE(void *) volatile pv;
1712	} PGMPAGER0MAPTLBE;
1713	/** Pointer to an entry in the HC physical TLB. */
1714	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1715
1716
1717	/** The number of entries in the ring-3 guest page mapping TLB.
1718	* @remarks The value must be a power of two. */
1719	#define PGM_PAGER0MAPTLB_ENTRIES 256
1720
1721	/**
1722	* Ring-3 guest page mapping TLB.
1723	* @remarks used in ring-0 as well at the moment.
1724	*/
1725	typedef struct PGMPAGER0MAPTLB
1726	{
1727	/** The TLB entries. */
1728	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1729	} PGMPAGER0MAPTLB;
1730	/** Pointer to the ring-3 guest page mapping TLB. */
1731	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1732
1733	/**
1734	* Calculates the index of the TLB entry for the specified guest page.
1735	* @returns Physical TLB index.
1736	* @param GCPhys The guest physical address.
1737	*/
1738	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1739	/** @} */
1740
1741
1742	/** @name Context neutral page mapper TLB.
1743	*
1744	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1745	* code is writting in a kind of context neutral way. Time will show whether
1746	* this actually makes sense or not...
1747	*
1748	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1749	* context ends up using a global mapping cache on some platforms
1750	* (darwin).
1751	*
1752	* @{ */
1753	/** @typedef PPGMPAGEMAPTLB
1754	* The page mapper TLB pointer type for the current context. */
1755	/** @typedef PPGMPAGEMAPTLB
1756	* The page mapper TLB entry pointer type for the current context. */
1757	/** @typedef PPGMPAGEMAPTLB
1758	* The page mapper TLB entry pointer pointer type for the current context. */
1759	/** @def PGM_PAGEMAPTLB_ENTRIES
1760	* The number of TLB entries in the page mapper TLB for the current context. */
1761	/** @def PGM_PAGEMAPTLB_IDX
1762	* Calculate the TLB index for a guest physical address.
1763	* @returns The TLB index.
1764	* @param GCPhys The guest physical address. */
1765	/** @typedef PPGMPAGEMAP
1766	* Pointer to a page mapper unit for current context. */
1767	/** @typedef PPPGMPAGEMAP
1768	* Pointer to a page mapper unit pointer for current context. */
1769	#if defined(IN_RING0)
1770	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1771	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1772	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1773	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1774	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1775	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1776	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1777	#else
1778	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1779	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1780	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1781	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1782	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1783	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1784	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1785	#endif
1786	/** @} */
1787
1788
1789	/** @name PGM Pool Indexes.
1790	* Aka. the unique shadow page identifier.
1791	* @{ */
1792	/** NIL page pool IDX. */
1793	#define NIL_PGMPOOL_IDX 0
1794	/** The first normal index. There used to be 5 fictive pages up front, now
1795	* there is only the NIL page. */
1796	#define PGMPOOL_IDX_FIRST 1
1797	/** The last valid index. (inclusive, 14 bits) */
1798	#define PGMPOOL_IDX_LAST 0x3fff
1799	/** @} */
1800
1801	/** The NIL index for the parent chain. */
1802	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1803	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1804
1805	/**
1806	* Node in the chain linking a shadowed page to it's parent (user).
1807	*/
1808	#pragma pack(1)
1809	typedef struct PGMPOOLUSER
1810	{
1811	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1812	uint16_t iNext;
1813	/** The user page index. */
1814	uint16_t iUser;
1815	/** Index into the user table. */
1816	uint32_t iUserTable;
1817	} PGMPOOLUSER, *PPGMPOOLUSER;
1818	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1819	#pragma pack()
1820
1821
1822	/** The NIL index for the phys ext chain. */
1823	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1824	/** The NIL pte index for a phys ext chain slot. */
1825	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1826
1827	/**
1828	* Node in the chain of physical cross reference extents.
1829	* @todo Calling this an 'extent' is not quite right, find a better name.
1830	* @todo find out the optimal size of the aidx array
1831	*/
1832	#pragma pack(1)
1833	typedef struct PGMPOOLPHYSEXT
1834	{
1835	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1836	uint16_t iNext;
1837	/** Alignment. */
1838	uint16_t u16Align;
1839	/** The user page index. */
1840	uint16_t aidx[3];
1841	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1842	uint16_t apte[3];
1843	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1844	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1845	#pragma pack()
1846
1847
1848	/**
1849	* The kind of page that's being shadowed.
1850	*/
1851	typedef enum PGMPOOLKIND
1852	{
1853	/** The virtual invalid 0 entry. */
1854	PGMPOOLKIND_INVALID = 0,
1855	/** The entry is free (=unused). */
1856	PGMPOOLKIND_FREE,
1857
1858	/** Shw: 32-bit page table; Gst: no paging. */
1859	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1860	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1861	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1862	/** Shw: 32-bit page table; Gst: 4MB page. */
1863	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1864	/** Shw: PAE page table; Gst: no paging. */
1865	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1866	/** Shw: PAE page table; Gst: 32-bit page table. */
1867	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1868	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1869	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1870	/** Shw: PAE page table; Gst: PAE page table. */
1871	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1872	/** Shw: PAE page table; Gst: 2MB page. */
1873	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1874
1875	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1876	PGMPOOLKIND_32BIT_PD,
1877	/** Shw: 32-bit page directory. Gst: no paging. */
1878	PGMPOOLKIND_32BIT_PD_PHYS,
1879	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1880	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1881	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1882	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1883	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1884	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1885	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1886	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1887	/** Shw: PAE page directory; Gst: PAE page directory. */
1888	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1889	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1890	PGMPOOLKIND_PAE_PD_PHYS,
1891
1892	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1893	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1894	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1895	PGMPOOLKIND_PAE_PDPT,
1896	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1897	PGMPOOLKIND_PAE_PDPT_PHYS,
1898
1899	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1900	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1901	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1902	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1903	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1904	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1905	/** Shw: 64-bit page directory table; Gst: no paging. */
1906	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1907
1908	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1909	PGMPOOLKIND_64BIT_PML4,
1910
1911	/** Shw: EPT page directory pointer table; Gst: no paging. */
1912	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1913	/** Shw: EPT page directory table; Gst: no paging. */
1914	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1915	/** Shw: EPT page table; Gst: no paging. */
1916	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1917
1918	/** Shw: Root Nested paging table. */
1919	PGMPOOLKIND_ROOT_NESTED,
1920
1921	/** The last valid entry. */
1922	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1923	} PGMPOOLKIND;
1924
1925	/**
1926	* The access attributes of the page; only applies to big pages.
1927	*/
1928	typedef enum
1929	{
1930	PGMPOOLACCESS_DONTCARE = 0,
1931	PGMPOOLACCESS_USER_RW,
1932	PGMPOOLACCESS_USER_R,
1933	PGMPOOLACCESS_USER_RW_NX,
1934	PGMPOOLACCESS_USER_R_NX,
1935	PGMPOOLACCESS_SUPERVISOR_RW,
1936	PGMPOOLACCESS_SUPERVISOR_R,
1937	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1938	PGMPOOLACCESS_SUPERVISOR_R_NX
1939	} PGMPOOLACCESS;
1940
1941	/**
1942	* The tracking data for a page in the pool.
1943	*/
1944	typedef struct PGMPOOLPAGE
1945	{
1946	/** AVL node code with the (HC) physical address of this page. */
1947	AVLOHCPHYSNODECORE Core;
1948	/** Pointer to the R3 mapping of the page. */
1949	R3PTRTYPE(void *) pvPageR3;
1950	/** Pointer to the R0 mapping of the page. */
1951	R0PTRTYPE(void *) pvPageR0;
1952	/** The guest physical address. */
1953	RTGCPHYS GCPhys;
1954	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1955	uint8_t enmKind;
1956	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1957	uint8_t enmAccess;
1958	/** This supplements enmKind and enmAccess */
1959	bool fA20Enabled : 1;
1960
1961	/** Used to indicate that the page is zeroed. */
1962	bool fZeroed : 1;
1963	/** Used to indicate that a PT has non-global entries. */
1964	bool fSeenNonGlobal : 1;
1965	/** Used to indicate that we're monitoring writes to the guest page. */
1966	bool fMonitored : 1;
1967	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1968	* (All pages are in the age list.) */
1969	bool fCached : 1;
1970	/** This is used by the R3 access handlers when invoked by an async thread.
1971	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1972	bool volatile fReusedFlushPending : 1;
1973	/** Used to mark the page as dirty (write monitoring is temporarily
1974	* off). */
1975	bool fDirty : 1;
1976	bool fPadding1 : 1;
1977	bool fPadding2;
1978
1979	/** The index of this page. */
1980	uint16_t idx;
1981	/** The next entry in the list this page currently resides in.
1982	* It's either in the free list or in the GCPhys hash. */
1983	uint16_t iNext;
1984	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1985	uint16_t iUserHead;
1986	/** The number of present entries. */
1987	uint16_t cPresent;
1988	/** The first entry in the table which is present. */
1989	uint16_t iFirstPresent;
1990	/** The number of modifications to the monitored page. */
1991	uint16_t cModifications;
1992	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1993	uint16_t iModifiedNext;
1994	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1995	uint16_t iModifiedPrev;
1996	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1997	uint16_t iMonitoredNext;
1998	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1999	uint16_t iMonitoredPrev;
2000	/** The next page in the age list. */
2001	uint16_t iAgeNext;
2002	/** The previous page in the age list. */
2003	uint16_t iAgePrev;
2004	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2005	uint8_t idxDirtyEntry;
2006
2007	/** @name Access handler statistics to determine whether the guest is
2008	* (re)initializing a page table.
2009	* @{ */
2010	RTGCPTR GCPtrLastAccessHandlerRip;
2011	RTGCPTR GCPtrLastAccessHandlerFault;
2012	uint64_t cLastAccessHandler;
2013	/** @} */
2014	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2015	uint32_t volatile cLocked;
2016	#if GC_ARCH_BITS == 64
2017	uint32_t u32Alignment3;
2018	#endif
2019	# ifdef VBOX_STRICT
2020	RTGCPTR GCPtrDirtyFault;
2021	# endif
2022	} PGMPOOLPAGE;
2023	/** Pointer to a pool page. */
2024	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2025	/** Pointer to a const pool page. */
2026	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2027	/** Pointer to a pool page pointer. */
2028	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2029
2030
2031	/** The hash table size. */
2032	# define PGMPOOL_HASH_SIZE 0x40
2033	/** The hash function. */
2034	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2035
2036
2037	/**
2038	* The shadow page pool instance data.
2039	*
2040	* It's all one big allocation made at init time, except for the
2041	* pages that is. The user nodes follows immediately after the
2042	* page structures.
2043	*/
2044	typedef struct PGMPOOL
2045	{
2046	/** The VM handle - R3 Ptr. */
2047	PVMR3 pVMR3;
2048	/** The VM handle - R0 Ptr. */
2049	R0PTRTYPE(PVMCC) pVMR0;
2050	/** The max pool size. This includes the special IDs. */
2051	uint16_t cMaxPages;
2052	/** The current pool size. */
2053	uint16_t cCurPages;
2054	/** The head of the free page list. */
2055	uint16_t iFreeHead;
2056	/* Padding. */
2057	uint16_t u16Padding;
2058	/** Head of the chain of free user nodes. */
2059	uint16_t iUserFreeHead;
2060	/** The number of user nodes we've allocated. */
2061	uint16_t cMaxUsers;
2062	/** The number of present page table entries in the entire pool. */
2063	uint32_t cPresent;
2064	/** Pointer to the array of user nodes - R3 pointer. */
2065	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2066	/** Pointer to the array of user nodes - R0 pointer. */
2067	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2068	/** Head of the chain of free phys ext nodes. */
2069	uint16_t iPhysExtFreeHead;
2070	/** The number of user nodes we've allocated. */
2071	uint16_t cMaxPhysExts;
2072	uint32_t u32Padding0b;
2073	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2074	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2075	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2076	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2077	/** Hash table for GCPhys addresses. */
2078	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2079	/** The head of the age list. */
2080	uint16_t iAgeHead;
2081	/** The tail of the age list. */
2082	uint16_t iAgeTail;
2083	/** Set if the cache is enabled. */
2084	bool fCacheEnabled;
2085	/** Alignment padding. */
2086	bool afPadding1[3];
2087	/** Head of the list of modified pages. */
2088	uint16_t iModifiedHead;
2089	/** The current number of modified pages. */
2090	uint16_t cModifiedPages;
2091	/** Physical access handler type registration handle. */
2092	PGMPHYSHANDLERTYPE hAccessHandlerType;
2093	/** Next available slot (in aDirtyPages). */
2094	uint32_t idxFreeDirtyPage;
2095	/** Number of active dirty pages. */
2096	uint32_t cDirtyPages;
2097	/** Array of current dirty pgm pool page indices. */
2098	uint16_t aidxDirtyPages[16];
2099	/** Array running in parallel to aidxDirtyPages with the page data. */
2100	struct
2101	{
2102	uint64_t aPage[512];
2103	} aDirtyPages[16];
2104
2105	/** The number of pages currently in use. */
2106	uint16_t cUsedPages;
2107	#ifdef VBOX_WITH_STATISTICS
2108	/** The high water mark for cUsedPages. */
2109	uint16_t cUsedPagesHigh;
2110	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2111	/** Profiling pgmPoolAlloc(). */
2112	STAMPROFILEADV StatAlloc;
2113	/** Profiling pgmR3PoolClearDoIt(). */
2114	STAMPROFILE StatClearAll;
2115	/** Profiling pgmR3PoolReset(). */
2116	STAMPROFILE StatR3Reset;
2117	/** Profiling pgmPoolFlushPage(). */
2118	STAMPROFILE StatFlushPage;
2119	/** Profiling pgmPoolFree(). */
2120	STAMPROFILE StatFree;
2121	/** Counting explicit flushes by PGMPoolFlushPage(). */
2122	STAMCOUNTER StatForceFlushPage;
2123	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2124	STAMCOUNTER StatForceFlushDirtyPage;
2125	/** Counting flushes for reused pages. */
2126	STAMCOUNTER StatForceFlushReused;
2127	/** Profiling time spent zeroing pages. */
2128	STAMPROFILE StatZeroPage;
2129	/** Profiling of pgmPoolTrackDeref. */
2130	STAMPROFILE StatTrackDeref;
2131	/** Profiling pgmTrackFlushGCPhysPT. */
2132	STAMPROFILE StatTrackFlushGCPhysPT;
2133	/** Profiling pgmTrackFlushGCPhysPTs. */
2134	STAMPROFILE StatTrackFlushGCPhysPTs;
2135	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2136	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2137	/** Number of times we've been out of user records. */
2138	STAMCOUNTER StatTrackFreeUpOneUser;
2139	/** Nr of flushed entries. */
2140	STAMCOUNTER StatTrackFlushEntry;
2141	/** Nr of updated entries. */
2142	STAMCOUNTER StatTrackFlushEntryKeep;
2143	/** Profiling deref activity related tracking GC physical pages. */
2144	STAMPROFILE StatTrackDerefGCPhys;
2145	/** Number of linear searches for a HCPhys in the ram ranges. */
2146	STAMCOUNTER StatTrackLinearRamSearches;
2147	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2148	STAMCOUNTER StamTrackPhysExtAllocFailures;
2149
2150	/** Profiling the RC/R0 \#PF access handler. */
2151	STAMPROFILE StatMonitorPfRZ;
2152	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2153	STAMPROFILE StatMonitorPfRZHandled;
2154	/** Times we've failed interpreting the instruction. */
2155	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2156	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2157	STAMPROFILE StatMonitorPfRZFlushPage;
2158	/** Times we've detected a page table reinit. */
2159	STAMCOUNTER StatMonitorPfRZFlushReinit;
2160	/** Counting flushes for pages that are modified too often. */
2161	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2162	/** Times we've detected fork(). */
2163	STAMCOUNTER StatMonitorPfRZFork;
2164	/** Times we've failed interpreting a patch code instruction. */
2165	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2166	/** Times we've failed interpreting a patch code instruction during flushing. */
2167	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2168	/** The number of times we've seen rep prefixes we can't handle. */
2169	STAMCOUNTER StatMonitorPfRZRepPrefix;
2170	/** Profiling the REP STOSD cases we've handled. */
2171	STAMPROFILE StatMonitorPfRZRepStosd;
2172
2173	/** Profiling the R0/RC regular access handler. */
2174	STAMPROFILE StatMonitorRZ;
2175	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2176	STAMPROFILE StatMonitorRZFlushPage;
2177	/** Per access size counts indexed by size minus 1, last for larger. */
2178	STAMCOUNTER aStatMonitorRZSizes[16+3];
2179	/** Missaligned access counts indexed by offset - 1. */
2180	STAMCOUNTER aStatMonitorRZMisaligned[7];
2181
2182	/** Nr of handled PT faults. */
2183	STAMCOUNTER StatMonitorRZFaultPT;
2184	/** Nr of handled PD faults. */
2185	STAMCOUNTER StatMonitorRZFaultPD;
2186	/** Nr of handled PDPT faults. */
2187	STAMCOUNTER StatMonitorRZFaultPDPT;
2188	/** Nr of handled PML4 faults. */
2189	STAMCOUNTER StatMonitorRZFaultPML4;
2190
2191	/** Profiling the R3 access handler. */
2192	STAMPROFILE StatMonitorR3;
2193	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2194	STAMPROFILE StatMonitorR3FlushPage;
2195	/** Per access size counts indexed by size minus 1, last for larger. */
2196	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2197	/** Missaligned access counts indexed by offset - 1. */
2198	STAMCOUNTER aStatMonitorR3Misaligned[7];
2199	/** Nr of handled PT faults. */
2200	STAMCOUNTER StatMonitorR3FaultPT;
2201	/** Nr of handled PD faults. */
2202	STAMCOUNTER StatMonitorR3FaultPD;
2203	/** Nr of handled PDPT faults. */
2204	STAMCOUNTER StatMonitorR3FaultPDPT;
2205	/** Nr of handled PML4 faults. */
2206	STAMCOUNTER StatMonitorR3FaultPML4;
2207
2208	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2209	STAMCOUNTER StatResetDirtyPages;
2210	/** Times we've called pgmPoolAddDirtyPage. */
2211	STAMCOUNTER StatDirtyPage;
2212	/** Times we've had to flush duplicates for dirty page management. */
2213	STAMCOUNTER StatDirtyPageDupFlush;
2214	/** Times we've had to flush because of overflow. */
2215	STAMCOUNTER StatDirtyPageOverFlowFlush;
2216
2217	/** The high water mark for cModifiedPages. */
2218	uint16_t cModifiedPagesHigh;
2219	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2220
2221	/** The number of cache hits. */
2222	STAMCOUNTER StatCacheHits;
2223	/** The number of cache misses. */
2224	STAMCOUNTER StatCacheMisses;
2225	/** The number of times we've got a conflict of 'kind' in the cache. */
2226	STAMCOUNTER StatCacheKindMismatches;
2227	/** Number of times we've been out of pages. */
2228	STAMCOUNTER StatCacheFreeUpOne;
2229	/** The number of cacheable allocations. */
2230	STAMCOUNTER StatCacheCacheable;
2231	/** The number of uncacheable allocations. */
2232	STAMCOUNTER StatCacheUncacheable;
2233	#else
2234	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2235	#endif
2236	/** Profiling PGMR0PoolGrow(). */
2237	STAMPROFILE StatGrow;
2238	/** The AVL tree for looking up a page by its HC physical address. */
2239	AVLOHCPHYSTREE HCPhysTree;
2240	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2241	/** Array of pages. (cMaxPages in length)
2242	* The Id is the index into thist array.
2243	*/
2244	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2245	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2246	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2247	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2248	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2249	#ifdef VBOX_WITH_STATISTICS
2250	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2251	#endif
2252	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2253
2254
2255	/** @def PGMPOOL_PAGE_2_PTR
2256	* Maps a pool page pool into the current context.
2257	*
2258	* @returns VBox status code.
2259	* @param a_pVM Pointer to the VM.
2260	* @param a_pPage The pool page.
2261	*
2262	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2263	* small page window employeed by that function. Be careful.
2264	* @remark There is no need to assert on the result.
2265	*/
2266	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2267	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2268	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2269	{
2270	RT_NOREF(pszCaller);
2271	AssertPtr(a_pPage);
2272	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2273	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2274	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2275	return a_pPage->CTX_SUFF(pvPage);
2276	}
2277	#else
2278	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2279	#endif
2280
2281
2282	/** @def PGMPOOL_PAGE_2_PTR_V2
2283	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2284	*
2285	* @returns VBox status code.
2286	* @param a_pVM Pointer to the VM.
2287	* @param a_pVCpu The current CPU.
2288	* @param a_pPage The pool page.
2289	*
2290	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2291	* small page window employeed by that function. Be careful.
2292	* @remark There is no need to assert on the result.
2293	*/
2294	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2295
2296
2297	/** @name Per guest page tracking data.
2298	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2299	* is to use more bits for it and split it up later on. But for now we'll play
2300	* safe and change as little as possible.
2301	*
2302	* The 16-bit word has two parts:
2303	*
2304	* The first 14-bit forms the @a idx field. It is either the index of a page in
2305	* the shadow page pool, or and index into the extent list.
2306	*
2307	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2308	* shadow page pool references to the page. If cRefs equals
2309	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2310	* (misnomer) table and not the shadow page pool.
2311	*
2312	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2313	* the 16-bit word.
2314	*
2315	* @{ */
2316	/** The shift count for getting to the cRefs part. */
2317	#define PGMPOOL_TD_CREFS_SHIFT 14
2318	/** The mask applied after shifting the tracking data down by
2319	* PGMPOOL_TD_CREFS_SHIFT. */
2320	#define PGMPOOL_TD_CREFS_MASK 0x3
2321	/** The cRefs value used to indicate that the idx is the head of a
2322	* physical cross reference list. */
2323	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2324	/** The shift used to get idx. */
2325	#define PGMPOOL_TD_IDX_SHIFT 0
2326	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2327	#define PGMPOOL_TD_IDX_MASK 0x3fff
2328	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2329	* simply too many mappings of this page. */
2330	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2331
2332	/** @def PGMPOOL_TD_MAKE
2333	* Makes a 16-bit tracking data word.
2334	*
2335	* @returns tracking data.
2336	* @param cRefs The @a cRefs field. Must be within bounds!
2337	* @param idx The @a idx field. Must also be within bounds! */
2338	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2339
2340	/** @def PGMPOOL_TD_GET_CREFS
2341	* Get the @a cRefs field from a tracking data word.
2342	*
2343	* @returns The @a cRefs field
2344	* @param u16 The tracking data word.
2345	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2346	* non-zero @a u16. */
2347	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2348
2349	/** @def PGMPOOL_TD_GET_IDX
2350	* Get the @a idx field from a tracking data word.
2351	*
2352	* @returns The @a idx field
2353	* @param u16 The tracking data word. */
2354	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2355	/** @} */
2356
2357
2358
2359	/** @name A20 gate macros
2360	* @{ */
2361	#define PGM_WITH_A20
2362	#ifdef PGM_WITH_A20
2363	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2364	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2365	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2366	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2367	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2368	#else
2369	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2370	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2371	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2372	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2373	#endif
2374	/** @} */
2375
2376
2377	/**
2378	* Roots and anchors for trees and list employing self relative offsets as
2379	* pointers.
2380	*
2381	* When using self-relative offsets instead of pointers, the offsets needs to be
2382	* the same in all offsets. Thus the roots and anchors needs to live on the
2383	* hyper heap just like the nodes.
2384	*/
2385	typedef struct PGMTREES
2386	{
2387	/** List of physical access handler types (offset pointers) of type
2388	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2389	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2390	/** Physical access handlers (AVL range+offsetptr tree). */
2391	AVLROGCPHYSTREE PhysHandlers;
2392	} PGMTREES;
2393	/** Pointer to PGM trees. */
2394	typedef PGMTREES *PPGMTREES;
2395
2396
2397	/**
2398	* Page fault guest state for the AMD64 paging mode.
2399	*/
2400	typedef struct PGMPTWALKCORE
2401	{
2402	/** The guest virtual address that is being resolved by the walk
2403	* (input). */
2404	RTGCPTR GCPtr;
2405
2406	/** The guest physical address that is the result of the walk.
2407	* @remarks only valid if fSucceeded is set. */
2408	RTGCPHYS GCPhys;
2409
2410	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2411	bool fSucceeded;
2412	/** The level problem arrised at.
2413	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2414	* level 8. This is 0 on success. */
2415	uint8_t uLevel;
2416	/** Set if the page isn't present. */
2417	bool fNotPresent;
2418	/** Encountered a bad physical address. */
2419	bool fBadPhysAddr;
2420	/** Set if there was reserved bit violations. */
2421	bool fRsvdError;
2422	/** Set if it involves a big page (2/4 MB). */
2423	bool fBigPage;
2424	/** Set if it involves a gigantic page (1 GB). */
2425	bool fGigantPage;
2426	/** The effective X86_PTE_US flag for the address. */
2427	bool fEffectiveUS;
2428	/** The effective X86_PTE_RW flag for the address. */
2429	bool fEffectiveRW;
2430	/** The effective X86_PTE_NX flag for the address. */
2431	bool fEffectiveNX;
2432	bool afPadding1[2];
2433	/** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2434	* The NX bit is inverted and shifted down 63 places to bit 0. */
2435	uint32_t fEffective;
2436	} PGMPTWALKCORE;
2437
2438	/** @name PGMPTWALKCORE::fEffective bits.
2439	* @{ */
2440	/** Effective execute bit (!NX). */
2441	#define PGMPTWALK_EFF_X UINT32_C(1)
2442	/** Effective write access bit. */
2443	#define PGMPTWALK_EFF_RW X86_PTE_RW
2444	/** Effective user-mode access bit. */
2445	#define PGMPTWALK_EFF_US X86_PTE_US
2446	/** Effective write through cache bit. */
2447	#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2448	/** Effective cache disabled bit. */
2449	#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2450	/** Effective accessed bit. */
2451	#define PGMPTWALK_EFF_A X86_PTE_A
2452	/** The dirty bit of the final entry. */
2453	#define PGMPTWALK_EFF_D X86_PTE_D
2454	/** The PAT bit of the final entry. */
2455	#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2456	/** The global bit of the final entry. */
2457	#define PGMPTWALK_EFF_G X86_PTE_G
2458	/** @} */
2459
2460
2461	/**
2462	* Guest page table walk for the AMD64 mode.
2463	*/
2464	typedef struct PGMPTWALKGSTAMD64
2465	{
2466	/** The common core. */
2467	PGMPTWALKCORE Core;
2468
2469	PX86PML4 pPml4;
2470	PX86PML4E pPml4e;
2471	X86PML4E Pml4e;
2472
2473	PX86PDPT pPdpt;
2474	PX86PDPE pPdpe;
2475	X86PDPE Pdpe;
2476
2477	PX86PDPAE pPd;
2478	PX86PDEPAE pPde;
2479	X86PDEPAE Pde;
2480
2481	PX86PTPAE pPt;
2482	PX86PTEPAE pPte;
2483	X86PTEPAE Pte;
2484	} PGMPTWALKGSTAMD64;
2485	/** Pointer to a AMD64 guest page table walk. */
2486	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2487	/** Pointer to a const AMD64 guest page table walk. */
2488	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2489
2490	/**
2491	* Guest page table walk for the PAE mode.
2492	*/
2493	typedef struct PGMPTWALKGSTPAE
2494	{
2495	/** The common core. */
2496	PGMPTWALKCORE Core;
2497
2498	PX86PDPT pPdpt;
2499	PX86PDPE pPdpe;
2500	X86PDPE Pdpe;
2501
2502	PX86PDPAE pPd;
2503	PX86PDEPAE pPde;
2504	X86PDEPAE Pde;
2505
2506	PX86PTPAE pPt;
2507	PX86PTEPAE pPte;
2508	X86PTEPAE Pte;
2509	} PGMPTWALKGSTPAE;
2510	/** Pointer to a PAE guest page table walk. */
2511	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2512	/** Pointer to a const AMD64 guest page table walk. */
2513	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2514
2515	/**
2516	* Guest page table walk for the 32-bit mode.
2517	*/
2518	typedef struct PGMPTWALKGST32BIT
2519	{
2520	/** The common core. */
2521	PGMPTWALKCORE Core;
2522
2523	PX86PD pPd;
2524	PX86PDE pPde;
2525	X86PDE Pde;
2526
2527	PX86PT pPt;
2528	PX86PTE pPte;
2529	X86PTE Pte;
2530	} PGMPTWALKGST32BIT;
2531	/** Pointer to a 32-bit guest page table walk. */
2532	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2533	/** Pointer to a const 32-bit guest page table walk. */
2534	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2535
2536	/**
2537	* Which part of PGMPTWALKGST that is valid.
2538	*/
2539	typedef enum PGMPTWALKGSTTYPE
2540	{
2541	/** Customary invalid 0 value. */
2542	PGMPTWALKGSTTYPE_INVALID = 0,
2543	/** PGMPTWALKGST::u.Amd64 is valid. */
2544	PGMPTWALKGSTTYPE_AMD64,
2545	/** PGMPTWALKGST::u.Pae is valid. */
2546	PGMPTWALKGSTTYPE_PAE,
2547	/** PGMPTWALKGST::u.Legacy is valid. */
2548	PGMPTWALKGSTTYPE_32BIT,
2549	/** Customary 32-bit type hack. */
2550	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2551	} PGMPTWALKGSTTYPE;
2552
2553	/**
2554	* Combined guest page table walk result.
2555	*/
2556	typedef struct PGMPTWALKGST
2557	{
2558	union
2559	{
2560	/** The page walker core - always valid. */
2561	PGMPTWALKCORE Core;
2562	/** The page walker for AMD64. */
2563	PGMPTWALKGSTAMD64 Amd64;
2564	/** The page walker for PAE (32-bit). */
2565	PGMPTWALKGSTPAE Pae;
2566	/** The page walker for 32-bit paging (called legacy due to C naming
2567	* convension). */
2568	PGMPTWALKGST32BIT Legacy;
2569	} u;
2570	/** Indicates which part of the union is valid. */
2571	PGMPTWALKGSTTYPE enmType;
2572	} PGMPTWALKGST;
2573	/** Pointer to a combined guest page table walk result. */
2574	typedef PGMPTWALKGST *PPGMPTWALKGST;
2575	/** Pointer to a read-only combined guest page table walk result. */
2576	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2577
2578
2579	/** @name Paging mode macros
2580	* @{
2581	*/
2582	#ifdef IN_RING3
2583	# define PGM_CTX(a,b) a##R3##b
2584	# define PGM_CTX_STR(a,b) a "R3" b
2585	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2586	#elif defined(IN_RING0)
2587	# define PGM_CTX(a,b) a##R0##b
2588	# define PGM_CTX_STR(a,b) a "R0" b
2589	# define PGM_CTX_DECL(type) VMMDECL(type)
2590	#else
2591	# error "Not IN_RING3 or IN_RING0!"
2592	#endif
2593
2594	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2595	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2596	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2597	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2598	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2599	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2600	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2601	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2602	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2603	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2604	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2605	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2606	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2607	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2608	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2609	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2610
2611	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2612	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2613	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2614	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2615	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2616	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2617	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2618	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2619	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2620	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2621	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2622	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2623	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2624	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2625	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2626	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2627	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2628	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2629	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2630	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2631	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2632	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2633	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2634	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2635	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2636
2637	/* Shw_Gst */
2638	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2639	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2640	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2641	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2642	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2643	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2644	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2645	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2646	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2647	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2648	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2649	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2650	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2651	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2652	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2653	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2654	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2655	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2656	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2657	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2658	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2659	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2660	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2661	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2662	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2663	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2664	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2665	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2666	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2667	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2668	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2669	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2670	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2671	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2672
2673	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2674	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2675	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2676	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2677	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2678	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2679	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2680	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2681	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2682	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2683	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2684	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2685	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2686	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2687	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2688	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2689	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2690	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2691	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2692	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2693	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2694	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2695	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2696	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2697	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2698	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2699	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2700	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2701
2702	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2703	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2704	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2705	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2706	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2707	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2708	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2709	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2710	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2711	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2712	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2713	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2714	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2715	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2716	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2717	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2718	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2719	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2720	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2721	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2722	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2723	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2724	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2725	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2726	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2727	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2728	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2729	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2730	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2731
2732	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2733	/** @} */
2734
2735
2736	/**
2737	* Function pointers for guest paging.
2738	*/
2739	typedef struct PGMMODEDATAGST
2740	{
2741	/** The guest mode type. */
2742	uint32_t uType;
2743	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2744	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2745	DECLCALLBACKMEMBER(int, pfnGetPDE,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2746	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2747	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2748	#ifdef IN_RING3
2749	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2750	#endif
2751	} PGMMODEDATAGST;
2752
2753	/** The length of g_aPgmGuestModeData. */
2754	#ifdef VBOX_WITH_64_BITS_GUESTS
2755	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2756	#else
2757	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2758	#endif
2759	/** The guest mode data array. */
2760	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2761
2762
2763	/**
2764	* Function pointers for shadow paging.
2765	*/
2766	typedef struct PGMMODEDATASHW
2767	{
2768	/** The shadow mode type. */
2769	uint32_t uType;
2770	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2771	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2772	uint64_t fMask, uint32_t fOpFlags));
2773	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2774	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2775	#ifdef IN_RING3
2776	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2777	#endif
2778	} PGMMODEDATASHW;
2779
2780	/** The length of g_aPgmShadowModeData. */
2781	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2782	/** The shadow mode data array. */
2783	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2784
2785
2786	/**
2787	* Function pointers for guest+shadow paging.
2788	*/
2789	typedef struct PGMMODEDATABTH
2790	{
2791	/** The shadow mode type. */
2792	uint32_t uShwType;
2793	/** The guest mode type. */
2794	uint32_t uGstType;
2795
2796	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2797	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2798	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2799	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2800	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2801	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2802	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2803	#ifndef IN_RING3
2804	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2805	#endif
2806	#ifdef VBOX_STRICT
2807	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2808	#endif
2809	} PGMMODEDATABTH;
2810
2811	/** The length of g_aPgmBothModeData. */
2812	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2813	/** The guest+shadow mode data array. */
2814	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2815
2816
2817	#ifdef VBOX_WITH_STATISTICS
2818	/**
2819	* PGM statistics.
2820	*
2821	* These lives on the heap when compiled in as they would otherwise waste
2822	* unnecessary space in release builds.
2823	*/
2824	typedef struct PGMSTATS
2825	{
2826	/* R3 only: */
2827	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2828	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2829
2830	/* R3+RZ */
2831	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2832	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2833	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2834	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2835	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2836	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2837	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2838	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2839	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2840	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2841	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2842	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2843	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2844	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2845	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2846	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2847	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2848	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2849	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2850	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2851	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2852	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2853	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2854	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2855	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2856	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2857
2858	/* RC only: */
2859	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2860	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2861
2862	STAMCOUNTER StatRZPhysRead;
2863	STAMCOUNTER StatRZPhysReadBytes;
2864	STAMCOUNTER StatRZPhysWrite;
2865	STAMCOUNTER StatRZPhysWriteBytes;
2866	STAMCOUNTER StatR3PhysRead;
2867	STAMCOUNTER StatR3PhysReadBytes;
2868	STAMCOUNTER StatR3PhysWrite;
2869	STAMCOUNTER StatR3PhysWriteBytes;
2870	STAMCOUNTER StatRCPhysRead;
2871	STAMCOUNTER StatRCPhysReadBytes;
2872	STAMCOUNTER StatRCPhysWrite;
2873	STAMCOUNTER StatRCPhysWriteBytes;
2874
2875	STAMCOUNTER StatRZPhysSimpleRead;
2876	STAMCOUNTER StatRZPhysSimpleReadBytes;
2877	STAMCOUNTER StatRZPhysSimpleWrite;
2878	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2879	STAMCOUNTER StatR3PhysSimpleRead;
2880	STAMCOUNTER StatR3PhysSimpleReadBytes;
2881	STAMCOUNTER StatR3PhysSimpleWrite;
2882	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2883	STAMCOUNTER StatRCPhysSimpleRead;
2884	STAMCOUNTER StatRCPhysSimpleReadBytes;
2885	STAMCOUNTER StatRCPhysSimpleWrite;
2886	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2887
2888	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2889	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2890	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2891	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2892	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2893	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2894	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2895
2896	/** Time spent by the host OS for large page allocation. */
2897	STAMPROFILE StatAllocLargePage;
2898	/** Time spent clearing the newly allocated large pages. */
2899	STAMPROFILE StatClearLargePage;
2900	/** The number of times allocating a large pages takes more than the allowed period. */
2901	STAMCOUNTER StatLargePageOverflow;
2902	/** pgmPhysIsValidLargePage profiling - R3 */
2903	STAMPROFILE StatR3IsValidLargePage;
2904	/** pgmPhysIsValidLargePage profiling - RZ*/
2905	STAMPROFILE StatRZIsValidLargePage;
2906
2907	STAMPROFILE StatChunkAging;
2908	STAMPROFILE StatChunkFindCandidate;
2909	STAMPROFILE StatChunkUnmap;
2910	STAMPROFILE StatChunkMap;
2911	} PGMSTATS;
2912	#endif /* VBOX_WITH_STATISTICS */
2913
2914
2915	/**
2916	* Converts a PGM pointer into a VM pointer.
2917	* @returns Pointer to the VM structure the PGM is part of.
2918	* @param pPGM Pointer to PGM instance data.
2919	*/
2920	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2921
2922	/**
2923	* PGM Data (part of VM)
2924	*/
2925	typedef struct PGM
2926	{
2927	/** Offset to the VM structure. */
2928	int32_t offVM;
2929	/** Offset of the PGMCPU structure relative to VMCPU. */
2930	int32_t offVCpuPGM;
2931
2932	/** @cfgm{/RamPreAlloc, boolean, false}
2933	* Indicates whether the base RAM should all be allocated before starting
2934	* the VM (default), or if it should be allocated when first written to.
2935	*/
2936	bool fRamPreAlloc;
2937	/** Indicates whether write monitoring is currently in use.
2938	* This is used to prevent conflicts between live saving and page sharing
2939	* detection. */
2940	bool fPhysWriteMonitoringEngaged;
2941	/** Set if the CPU has less than 52-bit physical address width.
2942	* This is used */
2943	bool fLessThan52PhysicalAddressBits;
2944	/** Set when nested paging is active.
2945	* This is meant to save calls to HMIsNestedPagingActive and let the
2946	* compilers optimize the code better. Whether we use nested paging or
2947	* not is something we find out during VMM initialization and we won't
2948	* change this later on. */
2949	bool fNestedPaging;
2950	/** The host paging mode. (This is what SUPLib reports.) */
2951	SUPPAGINGMODE enmHostMode;
2952	/** We're not in a state which permits writes to guest memory.
2953	* (Only used in strict builds.) */
2954	bool fNoMorePhysWrites;
2955	/** @cfgm{/PageFusionAllowed, boolean, false}
2956	* Whether page fusion is allowed. */
2957	bool fPageFusionAllowed;
2958	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2959	* Whether PCI passthrough is enabled. */
2960	bool fPciPassthrough;
2961	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2962	uint8_t cMmio2Regions;
2963	/** Restore original ROM page content when resetting after loading state.
2964	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2965	* enables the VM to start using an updated ROM without requiring powering
2966	* down the VM, just rebooting or resetting it. */
2967	bool fRestoreRomPagesOnReset;
2968	/** Whether to automatically clear all RAM pages on reset. */
2969	bool fZeroRamPagesOnReset;
2970	/** Alignment padding. */
2971	bool afAlignment3[7];
2972
2973	/** Indicates that PGMR3FinalizeMappings has been called and that further
2974	* PGMR3MapIntermediate calls will be rejected. */
2975	bool fFinalizedMappings;
2976	/** If set no conflict checks are required. */
2977	bool fMappingsFixed;
2978	/** If set if restored as fixed but we were unable to re-fixate at the old
2979	* location because of room or address incompatibilities. */
2980	bool fMappingsFixedRestored;
2981	/** Size of fixed mapping.
2982	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2983	uint32_t cbMappingFixed;
2984	/** Generation ID for the RAM ranges. This member is incremented everytime
2985	* a RAM range is linked or unlinked. */
2986	uint32_t volatile idRamRangesGen;
2987
2988	/** Base address (GC) of fixed mapping.
2989	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2990	RTGCPTR GCPtrMappingFixed;
2991	/** The address of the previous RAM range mapping. */
2992	RTGCPTR GCPtrPrevRamRangeMapping;
2993
2994	/** Physical access handler type for ROM protection. */
2995	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2996	/** Alignment padding. */
2997	uint32_t u32Padding;
2998
2999	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3000	RTGCPHYS GCPhys4MBPSEMask;
3001	/** Mask containing the invalid bits of a guest physical address.
3002	* @remarks this does not stop at bit 52. */
3003	RTGCPHYS GCPhysInvAddrMask;
3004
3005
3006	/** RAM range TLB for R3. */
3007	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3008	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3009	* This is sorted by physical address and contains no overlapping ranges. */
3010	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3011	/** Root of the RAM range search tree for ring-3. */
3012	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3013	/** PGM offset based trees - R3 Ptr. */
3014	R3PTRTYPE(PPGMTREES) pTreesR3;
3015	/** Caching the last physical handler we looked up in R3. */
3016	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3017	/** Shadow Page Pool - R3 Ptr. */
3018	R3PTRTYPE(PPGMPOOL) pPoolR3;
3019	#ifndef PGM_WITHOUT_MAPPINGS
3020	/** Linked list of GC mappings - for HC.
3021	* The list is sorted ascending on address. */
3022	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3023	#endif
3024	/** Pointer to the list of ROM ranges - for R3.
3025	* This is sorted by physical address and contains no overlapping ranges. */
3026	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3027	/** Pointer to the list of MMIO2 ranges - for R3.
3028	* Registration order. */
3029	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3030	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3031	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3032
3033	/** RAM range TLB for R0. */
3034	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3035	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3036	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3037	/** Root of the RAM range search tree for ring-0. */
3038	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3039	/** PGM offset based trees - R0 Ptr. */
3040	R0PTRTYPE(PPGMTREES) pTreesR0;
3041	/** Caching the last physical handler we looked up in R0. */
3042	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3043	/** Shadow Page Pool - R0 Ptr. */
3044	R0PTRTYPE(PPGMPOOL) pPoolR0;
3045	#ifndef PGM_WITHOUT_MAPPINGS
3046	/** Linked list of GC mappings - for R0.
3047	* The list is sorted ascending on address. */
3048	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3049	RTR0PTR R0PtrAlignment0;
3050	#endif
3051	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3052	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3053	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3054	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3055
3056	#ifndef PGM_WITHOUT_MAPPINGS
3057	/** Pointer to the 5 page CR3 content mapping.
3058	* The first page is always the CR3 (in some form) while the 4 other pages
3059	* are used for the PDs in PAE mode. */
3060	RTGCPTR GCPtrCR3Mapping;
3061
3062	/** @name Intermediate Context
3063	* @{ */
3064	/** Pointer to the intermediate page directory - Normal. */
3065	R3PTRTYPE(PX86PD) pInterPD;
3066	/** Pointer to the intermediate page tables - Normal.
3067	* There are two page tables, one for the identity mapping and one for
3068	* the host context mapping (of the core code). */
3069	R3PTRTYPE(PX86PT) apInterPTs[2];
3070	/** Pointer to the intermediate page tables - PAE. */
3071	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3072	/** Pointer to the intermediate page directory - PAE. */
3073	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3074	/** Pointer to the intermediate page directory - PAE. */
3075	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3076	/** Pointer to the intermediate page-map level 4 - AMD64. */
3077	R3PTRTYPE(PX86PML4) pInterPaePML4;
3078	/** Pointer to the intermediate page directory - AMD64. */
3079	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3080	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3081	RTHCPHYS HCPhysInterPD;
3082	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3083	RTHCPHYS HCPhysInterPaePDPT;
3084	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3085	RTHCPHYS HCPhysInterPaePML4;
3086	/** @} */
3087	#endif
3088
3089	#ifndef PGM_WITHOUT_MAPPINGS
3090	/** Base address of the dynamic page mapping area.
3091	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3092	*
3093	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3094	* work out. Some cleaning up of the initialization that would
3095	* remove this memory is yet to be done...
3096	*/
3097	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3098	/** The address of the raw-mode context mapping cache. */
3099	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3100	/** The address of the ring-0 mapping cache if we're making use of it. */
3101	RTR0PTR pvR0DynMapUsed;
3102	#endif
3103
3104	/** Hack: Number of deprecated page mapping locks taken by the current lock
3105	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3106	uint32_t cDeprecatedPageLocks;
3107	/** Alignment padding. */
3108	uint32_t au32Alignment2[1];
3109
3110
3111	/** PGM critical section.
3112	* This protects the physical, ram ranges, and the page flag updating (some of
3113	* it anyway).
3114	*/
3115	PDMCRITSECT CritSectX;
3116
3117	/**
3118	* Data associated with managing the ring-3 mappings of the allocation chunks.
3119	*/
3120	struct
3121	{
3122	/** The chunk mapping TLB. */
3123	PGMCHUNKR3MAPTLB Tlb;
3124	/** The chunk tree, ordered by chunk id. */
3125	R3PTRTYPE(PAVLU32NODECORE) pTree;
3126	#if HC_ARCH_BITS == 32
3127	uint32_t u32Alignment0;
3128	#endif
3129	/** The number of mapped chunks. */
3130	uint32_t c;
3131	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3132	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3133	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3134	uint32_t cMax;
3135	/** The current time. This is incremented whenever a chunk is inserted. */
3136	uint32_t iNow;
3137	/** Alignment padding. */
3138	uint32_t au32Alignment1[3];
3139	} ChunkR3Map;
3140
3141	/** The page mapping TLB for ring-3. */
3142	PGMPAGER3MAPTLB PhysTlbR3;
3143	/** The page mapping TLB for ring-0. */
3144	PGMPAGER0MAPTLB PhysTlbR0;
3145
3146	/** @name The zero page.
3147	* @{ */
3148	/** The host physical address of the zero page. */
3149	RTHCPHYS HCPhysZeroPg;
3150	/** The ring-3 mapping of the zero page. */
3151	RTR3PTR pvZeroPgR3;
3152	/** The ring-0 mapping of the zero page. */
3153	RTR0PTR pvZeroPgR0;
3154	/** The GC mapping of the zero page. */
3155	RTRCPTR pvZeroPgRC;
3156	RTRCPTR RCPtrAlignment3;
3157	/** @}*/
3158
3159	/** @name The Invalid MMIO page.
3160	* This page is filled with 0xfeedface.
3161	* @{ */
3162	/** The host physical address of the invalid MMIO page. */
3163	RTHCPHYS HCPhysMmioPg;
3164	/** The host pysical address of the invalid MMIO page plus all invalid
3165	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3166	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3167	RTHCPHYS HCPhysInvMmioPg;
3168	/** The ring-3 mapping of the invalid MMIO page. */
3169	RTR3PTR pvMmioPgR3;
3170	#if HC_ARCH_BITS == 32
3171	RTR3PTR R3PtrAlignment4;
3172	#endif
3173	/** @} */
3174
3175
3176	/** The number of handy pages. */
3177	uint32_t cHandyPages;
3178
3179	/** The number of large handy pages. */
3180	uint32_t cLargeHandyPages;
3181
3182	/**
3183	* Array of handy pages.
3184	*
3185	* This array is used in a two way communication between pgmPhysAllocPage
3186	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3187	* an intermediary.
3188	*
3189	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3190	* (The current size of 32 pages, means 128 KB of handy memory.)
3191	*/
3192	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3193
3194	/**
3195	* Array of large handy pages. (currently size 1)
3196	*
3197	* This array is used in a two way communication between pgmPhysAllocLargePage
3198	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3199	* an intermediary.
3200	*/
3201	GMMPAGEDESC aLargeHandyPage[1];
3202
3203	/**
3204	* Live save data.
3205	*/
3206	struct
3207	{
3208	/** Per type statistics. */
3209	struct
3210	{
3211	/** The number of ready pages. */
3212	uint32_t cReadyPages;
3213	/** The number of dirty pages. */
3214	uint32_t cDirtyPages;
3215	/** The number of ready zero pages. */
3216	uint32_t cZeroPages;
3217	/** The number of write monitored pages. */
3218	uint32_t cMonitoredPages;
3219	} Rom,
3220	Mmio2,
3221	Ram;
3222	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3223	uint32_t cIgnoredPages;
3224	/** Indicates that a live save operation is active. */
3225	bool fActive;
3226	/** Padding. */
3227	bool afReserved[2];
3228	/** The next history index. */
3229	uint8_t iDirtyPagesHistory;
3230	/** History of the total amount of dirty pages. */
3231	uint32_t acDirtyPagesHistory[64];
3232	/** Short term dirty page average. */
3233	uint32_t cDirtyPagesShort;
3234	/** Long term dirty page average. */
3235	uint32_t cDirtyPagesLong;
3236	/** The number of saved pages. This is used to get some kind of estimate of the
3237	* link speed so we can decide when we're done. It is reset after the first
3238	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3239	* zero pages. */
3240	uint64_t cSavedPages;
3241	/** The nanosecond timestamp when cSavedPages was 0. */
3242	uint64_t uSaveStartNS;
3243	/** Pages per second (for statistics). */
3244	uint32_t cPagesPerSecond;
3245	uint32_t cAlignment;
3246	} LiveSave;
3247
3248	/** @name Error injection.
3249	* @{ */
3250	/** Inject handy page allocation errors pretending we're completely out of
3251	* memory. */
3252	bool volatile fErrInjHandyPages;
3253	/** Padding. */
3254	bool afReserved[3];
3255	/** @} */
3256
3257	/** @name Release Statistics
3258	* @{ */
3259	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3260	uint32_t cPrivatePages; /*< The number of private pages. /
3261	uint32_t cSharedPages; /*< The number of shared pages. /
3262	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3263	uint32_t cZeroPages; /*< The number of zero backed pages. /
3264	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3265	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3266	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3267	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3268	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3269	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3270	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3271	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3272	uint32_t cLargePages; /*< The number of large pages. /
3273	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3274	/* uint32_t aAlignment4[1]; */
3275
3276	/** The number of times we were forced to change the hypervisor region location. */
3277	STAMCOUNTER cRelocations;
3278
3279	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3280	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3281	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3282
3283	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3284	/** @} */
3285
3286	#ifdef VBOX_WITH_STATISTICS
3287	/** @name Statistics on the heap.
3288	* @{ */
3289	R3PTRTYPE(PGMSTATS *) pStatsR3;
3290	R0PTRTYPE(PGMSTATS *) pStatsR0;
3291	/** @} */
3292	#endif
3293	} PGM;
3294	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3295	# ifndef PGM_WITHOUT_MAPPINGS
3296	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3297	# endif
3298	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3299	# ifndef PGM_WITHOUT_MAPPINGS
3300	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3301	# endif
3302	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3303	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3304	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3305	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3306	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3307	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3308	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3309	#endif /* !IN_TSTVMSTRUCTGC */
3310	/** Pointer to the PGM instance data. */
3311	typedef PGM *PPGM;
3312
3313
3314
3315	typedef struct PGMCPUSTATS
3316	{
3317	/* Common */
3318	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3319	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3320
3321	/* R0 only: */
3322	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3323	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3324
3325	/* RZ only: */
3326	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3327	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3328	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3329	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3330	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3331	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3332	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3333	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3334	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3335	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3336	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3337	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3338	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3339	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3340	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3341	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3342	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3343	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3344	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3345	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3346	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3347	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3348	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3349	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3350	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3351	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3352	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3353	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3354	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3355	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3356	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3357	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3358	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3359	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3360	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3361	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3362	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3363	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3364	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3365	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3366	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3367	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3368	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3369	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3370	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3371	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3372	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3373	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3374	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3375	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3376	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3377	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3378	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3379	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3380	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3381	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3382	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3383	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3384	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3385	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3386	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3387	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3388	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3389	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3390	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3391	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3392	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3393	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3394	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3395	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3396	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3397	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3398	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3399
3400	/* HC - R3 and (maybe) R0: */
3401
3402	/* RZ & R3: */
3403	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3404	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3405	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3406	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3407	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3408	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3409	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3410	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3411	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3412	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3413	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3414	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3415	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3416	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3417	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3418	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3419	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3420	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3421	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3422	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3423	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3424	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3425	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3426	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3427	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3428	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3429	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3430	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3431	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3432	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3433	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3434	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3435	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3436	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3437	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3438	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3439	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3440	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3441	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3442	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3443	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3444	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3445	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3446	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3447	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3448	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3449	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3450	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3451
3452	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3453	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3454	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3455	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3456	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3457	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3458	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3459	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3460	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3461	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3462	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3463	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3464	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3465	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3466	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3467	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3468	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3469	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3470	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3471	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3472	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3473	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3474	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3475	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3476	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3477	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3478	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3479	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3480	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3481	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3482	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3483	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3484	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3485	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3486	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3487	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3488	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3489	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3490	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3491	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3492	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3493	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3494	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3495	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3496	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3497	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3498	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3499	} PGMCPUSTATS;
3500
3501
3502	/**
3503	* Converts a PGMCPU pointer into a VM pointer.
3504	* @returns Pointer to the VM structure the PGM is part of.
3505	* @param pPGM Pointer to PGMCPU instance data.
3506	*/
3507	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3508
3509	/**
3510	* Converts a PGMCPU pointer into a PGM pointer.
3511	* @returns Pointer to the VM structure the PGM is part of.
3512	* @param pPGMCpu Pointer to PGMCPU instance data.
3513	*/
3514	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3515
3516	/**
3517	* PGMCPU Data (part of VMCPU).
3518	*/
3519	typedef struct PGMCPU
3520	{
3521	/** Offset to the VM structure. */
3522	int32_t offVM;
3523	/** Offset to the VMCPU structure. */
3524	int32_t offVCpu;
3525	/** Offset of the PGM structure relative to VMCPU. */
3526	int32_t offPGM;
3527	uint32_t uPadding0; /*< structure size alignment. /
3528
3529	/** A20 gate mask.
3530	* Our current approach to A20 emulation is to let REM do it and don't bother
3531	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3532	* But whould need arrise, we'll subject physical addresses to this mask. */
3533	RTGCPHYS GCPhysA20Mask;
3534	/** A20 gate state - boolean! */
3535	bool fA20Enabled;
3536	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3537	bool fNoExecuteEnabled;
3538	/** Unused bits. */
3539	bool afUnused[2];
3540
3541	/** What needs syncing (PGM_SYNC_*).
3542	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3543	* PGMFlushTLB, and PGMR3Load. */
3544	uint32_t fSyncFlags;
3545
3546	/** The shadow paging mode. */
3547	PGMMODE enmShadowMode;
3548	/** The guest paging mode. */
3549	PGMMODE enmGuestMode;
3550	/** Guest mode data table index (PGM_TYPE_XXX). */
3551	uint8_t volatile idxGuestModeData;
3552	/** Shadow mode data table index (PGM_TYPE_XXX). */
3553	uint8_t volatile idxShadowModeData;
3554	/** Both mode data table index (complicated). */
3555	uint8_t volatile idxBothModeData;
3556	/** Alignment padding. */
3557	uint8_t abPadding[5];
3558
3559	/** The current physical address represented in the guest CR3 register. */
3560	RTGCPHYS GCPhysCR3;
3561
3562	/** @name 32-bit Guest Paging.
3563	* @{ */
3564	/** The guest's page directory, R3 pointer. */
3565	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3566	/** The guest's page directory, R0 pointer. */
3567	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3568	/** Mask containing the MBZ bits of a big page PDE. */
3569	uint32_t fGst32BitMbzBigPdeMask;
3570	/** Set if the page size extension (PSE) is enabled. */
3571	bool fGst32BitPageSizeExtension;
3572	/** Alignment padding. */
3573	bool afAlignment2[3];
3574	/** @} */
3575
3576	/** @name PAE Guest Paging.
3577	* @{ */
3578	/** The guest's page directory pointer table, R3 pointer. */
3579	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3580	/** The guest's page directory pointer table, R0 pointer. */
3581	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3582
3583	/** The guest's page directories, R3 pointers.
3584	* These are individual pointers and don't have to be adjacent.
3585	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3586	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3587	/** The guest's page directories, R0 pointers.
3588	* Same restrictions as apGstPaePDsR3. */
3589	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3590	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3591	RTGCPHYS aGCPhysGstPaePDs[4];
3592	/** The values of the 4 PDPE CPU registers (PAE).
3593	* @todo Not really maintained by PGM atm, only by VT-x in EPT mode. Should
3594	* load on cr3 load and use instead of guest memory version like real
3595	* HW. We probably should move these to the CPUMCTX and treat them
3596	* like the rest of the register wrt exporting to VT-x and import back. */
3597	X86PDPE aGstPaePdpeRegs[4];
3598	/** The physical addresses of the monitored guest page directories (PAE). */
3599	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3600	/** Mask containing the MBZ PTE bits. */
3601	uint64_t fGstPaeMbzPteMask;
3602	/** Mask containing the MBZ PDE bits. */
3603	uint64_t fGstPaeMbzPdeMask;
3604	/** Mask containing the MBZ big page PDE bits. */
3605	uint64_t fGstPaeMbzBigPdeMask;
3606	/** Mask containing the MBZ PDPE bits. */
3607	uint64_t fGstPaeMbzPdpeMask;
3608	/** @} */
3609
3610	/** @name AMD64 Guest Paging.
3611	* @{ */
3612	/** The guest's page directory pointer table, R3 pointer. */
3613	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3614	/** The guest's page directory pointer table, R0 pointer. */
3615	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3616	/** Mask containing the MBZ PTE bits. */
3617	uint64_t fGstAmd64MbzPteMask;
3618	/** Mask containing the MBZ PDE bits. */
3619	uint64_t fGstAmd64MbzPdeMask;
3620	/** Mask containing the MBZ big page PDE bits. */
3621	uint64_t fGstAmd64MbzBigPdeMask;
3622	/** Mask containing the MBZ PDPE bits. */
3623	uint64_t fGstAmd64MbzPdpeMask;
3624	/** Mask containing the MBZ big page PDPE bits. */
3625	uint64_t fGstAmd64MbzBigPdpeMask;
3626	/** Mask containing the MBZ PML4E bits. */
3627	uint64_t fGstAmd64MbzPml4eMask;
3628	/** Mask containing the PDPE bits that we shadow. */
3629	uint64_t fGstAmd64ShadowedPdpeMask;
3630	/** Mask containing the PML4E bits that we shadow. */
3631	uint64_t fGstAmd64ShadowedPml4eMask;
3632	/** @} */
3633
3634	/** @name PAE and AMD64 Guest Paging.
3635	* @{ */
3636	/** Mask containing the PTE bits that we shadow. */
3637	uint64_t fGst64ShadowedPteMask;
3638	/** Mask containing the PDE bits that we shadow. */
3639	uint64_t fGst64ShadowedPdeMask;
3640	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3641	uint64_t fGst64ShadowedBigPdeMask;
3642	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3643	uint64_t fGst64ShadowedBigPde4PteMask;
3644	/** @} */
3645
3646	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3647	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3648	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3649	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3650
3651	/** For saving stack space, the disassembler state is allocated here instead of
3652	* on the stack. */
3653	DISCPUSTATE DisState;
3654
3655	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3656	uint64_t cNetwareWp0Hacks;
3657
3658	/** Count the number of pgm pool access handler calls. */
3659	uint64_t cPoolAccessHandler;
3660
3661	/** @name Release Statistics
3662	* @{ */
3663	/** The number of times the guest has switched mode since last reset or statistics reset. */
3664	STAMCOUNTER cGuestModeChanges;
3665	/** The number of times the guest has switched mode since last reset or statistics reset. */
3666	STAMCOUNTER cA20Changes;
3667	/** @} */
3668
3669	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3670	/** @name Statistics
3671	* @{ */
3672	/** R0: Pointer to the statistics. */
3673	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3674	/** R0: Which statistic this \#PF should be attributed to. */
3675	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3676	/** R3: Pointer to the statistics. */
3677	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3678	/** Alignment padding. */
3679	RTR3PTR pPaddingR3;
3680	/** @} */
3681	#endif /* VBOX_WITH_STATISTICS */
3682	} PGMCPU;
3683	/** Pointer to the per-cpu PGM data. */
3684	typedef PGMCPU *PPGMCPU;
3685
3686
3687	/** @name PGM::fSyncFlags Flags
3688	* @note Was part of saved state a long time ago.
3689	* @{
3690	*/
3691	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3692	/** Always sync CR3. */
3693	#define PGM_SYNC_ALWAYS RT_BIT(1)
3694	/** Check monitoring on next CR3 (re)load and invalidate page.
3695	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3696	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3697	/** Check guest mapping in SyncCR3. */
3698	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3699	/** Clear the page pool (a light weight flush). */
3700	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3701	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3702	/** @} */
3703
3704
3705	/**
3706	* PGM GVM instance data.
3707	*/
3708	typedef struct PGMR0PERVM
3709	{
3710	/** @name PGM Pool related stuff.
3711	* @{ */
3712	/** Critical section for serializing pool growth. */
3713	RTCRITSECT PoolGrowCritSect;
3714	/** The memory objects for the pool pages. */
3715	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3716	/** The ring-3 mapping objects for the pool pages. */
3717	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3718	/** @} */
3719	} PGMR0PERVM;
3720
3721	RT_C_DECLS_BEGIN
3722
3723	#if defined(VBOX_STRICT)
3724	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3725	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3726	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3727	#else
3728	int pgmLock(PVMCC pVM, bool fVoid);
3729	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3730	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3731	#endif
3732	void pgmUnlock(PVMCC pVM);
3733	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3734	/**
3735	* Asserts that the caller owns the PDM lock.
3736	* This is the internal variant of PGMIsLockOwner.
3737	* @param a_pVM Pointer to the VM.
3738	*/
3739	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3740	/**
3741	* Asserts that the caller owns the PDM lock.
3742	* This is the internal variant of PGMIsLockOwner.
3743	* @param a_pVM Pointer to the VM.
3744	* @param a_pVCpu The current CPU handle.
3745	*/
3746	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3747
3748	#ifndef PGM_WITHOUT_MAPPINGS
3749	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3750	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3751	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3752	int pgmMapResolveConflicts(PVM pVM);
3753	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3754	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3755	#endif /* !PGM_WITHOUT_MAPPINGS */
3756
3757	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3758	RTRCPTR pvUserRC, R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3759	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3760	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3761	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
3762	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3763	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3764	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3765	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3766	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3767	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3768
3769	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3770	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3771	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3772	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3773	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3774	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3775	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3776	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3777	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3778	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3779	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3780	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3781	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3782	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3783	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3784	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3785	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3786	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3787	#ifndef IN_RING3
3788	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3789	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3790	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3791	#endif
3792	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3793	PGMPAGETYPE enmNewType);
3794	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3795	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3796	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3797	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3798	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3799	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3800	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3801	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3802
3803	#ifdef IN_RING3
3804	void pgmR3PhysRelinkRamRanges(PVM pVM);
3805	int pgmR3PhysRamPreAllocate(PVM pVM);
3806	int pgmR3PhysRamReset(PVM pVM);
3807	int pgmR3PhysRomReset(PVM pVM);
3808	int pgmR3PhysRamZeroAll(PVM pVM);
3809	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3810	int pgmR3PhysRamTerm(PVM pVM);
3811	void pgmR3PhysRomTerm(PVM pVM);
3812	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3813
3814	int pgmR3PoolInit(PVM pVM);
3815	void pgmR3PoolRelocate(PVM pVM);
3816	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3817	void pgmR3PoolReset(PVM pVM);
3818	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3819	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3820	void pgmR3PoolWriteProtectPages(PVM pVM);
3821
3822	#endif /* IN_RING3 */
3823	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3824	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3825	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3826	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3827	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3828	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3829	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3830	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3831	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3832	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3833	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3834	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3835	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3836	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3837	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3838	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3839	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3840	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3841	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3842	#ifndef IN_RING3
3843	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3844	#endif
3845
3846	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3847	void pgmPoolResetDirtyPages(PVMCC pVM);
3848	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3849
3850	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3851	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3852	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3853
3854	#ifndef PGM_WITHOUT_MAPPINGS
3855	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3856	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3857	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3858	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3859	#endif
3860
3861	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3862	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3863	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3864
3865	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3866	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3867	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3868	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3869	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3870	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3871
3872	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3873	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3874	FNDBGCCMD pgmR3CmdShowSharedModules;
3875	# endif
3876
3877	void pgmLogState(PVM pVM);
3878
3879	RT_C_DECLS_END
3880
3881	/** @} */
3882
3883	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3884

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 91016

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