PGMInternal.h@ 91929

Last change on this file since 91929 was 91929, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Laid out PGM_BF_PTWALK_EFF_* bitfields including the new EPT bits. There should be sufficient room for future bits like supervisor shadow stack, suppress VE exception etc. Made it as a bitfield rather than just flags since EPT memory type fields occupy more than 1 bit and may be required in the future.
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File size: 173.2 KB

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1	/* $Id: PGMInternal.h 91929 2021-10-21 10:12:24Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <VBox/vmm/hm_vmx.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/avl.h>
43	#include <iprt/critsect.h>
44	#include <iprt/list-off32.h>
45	#include <iprt/sha.h>
46
47
48
49	/** @defgroup grp_pgm_int Internals
50	* @ingroup grp_pgm
51	* @internal
52	* @{
53	*/
54
55
56	/** @name PGM Compile Time Config
57	* @{
58	*/
59
60	/**
61	* Check and skip global PDEs for non-global flushes
62	*/
63	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
64
65	/**
66	* Optimization for PAE page tables that are modified often
67	*/
68	//#if 0 /* disabled again while debugging */
69	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
70	//#endif
71
72	/**
73	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
74	*/
75	#define PGM_WITH_LARGE_PAGES
76
77	/**
78	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
79	* VMX_EXIT_EPT_MISCONFIG.
80	*/
81	#define PGM_WITH_MMIO_OPTIMIZATIONS
82
83	/**
84	* Sync N pages instead of a whole page table
85	*/
86	#define PGM_SYNC_N_PAGES
87
88	/**
89	* Number of pages to sync during a page fault
90	*
91	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
92	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
93	*
94	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
95	* world switch overhead, so let's sync more.
96	*/
97	#ifdef IN_RING0
98	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
99	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
100	* but ~5% fewer faults.
101	*/
102	# define PGM_SYNC_NR_PAGES 32
103	#else
104	# define PGM_SYNC_NR_PAGES 8
105	#endif
106
107	/**
108	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
109	*/
110	#define PGM_MAX_PHYSCACHE_ENTRIES 64
111	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
112
113
114	/** @def PGMPOOL_CFG_MAX_GROW
115	* The maximum number of pages to add to the pool in one go.
116	*/
117	#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
118
119	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
120	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
121	*/
122	#ifdef VBOX_STRICT
123	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
124	#endif
125
126	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
127	* Enables the experimental lazy page allocation code. */
128	#ifdef DOXYGEN_RUNNING
129	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130	#endif
131
132	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
133	* Enables real write monitoring of pages, i.e. mapping them read-only and
134	* only making them writable when getting a write access \#PF. */
135	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
136
137	/** @def VBOX_WITH_PGM_NEM_MODE
138	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
139	* details. */
140	#ifdef DOXYGEN_RUNNING
141	# define VBOX_WITH_PGM_NEM_MODE
142	#endif
143
144	/** @} */
145
146
147	/** @name PDPT and PML4 flags.
148	* These are placed in the three bits available for system programs in
149	* the PDPT and PML4 entries.
150	* @{ */
151	/** The entry is a permanent one and it's must always be present.
152	* Never free such an entry. */
153	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154	/** PGM specific bits in PML4 entries. */
155	#define PGM_PML4_FLAGS 0
156	/** PGM specific bits in PDPT entries. */
157	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
158	/** @} */
159
160	/** @name Page directory flags.
161	* These are placed in the three bits available for system programs in
162	* the page directory entries.
163	* @{ */
164	/** Indicates the original entry was a big page.
165	* @remarks This is currently only used for statistics and can be recycled. */
166	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
167	/** Made read-only to facilitate dirty bit tracking. */
168	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169	/** @} */
170
171	/** @name Page flags.
172	* These are placed in the three bits available for system programs in
173	* the page entries.
174	* @{ */
175	/** Made read-only to facilitate dirty bit tracking. */
176	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179	/** Scanned and approved by CSAM (tm).
180	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
181	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
182	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183	#endif
184
185	/** @} */
186
187	/** @name Defines used to indicate the shadow and guest paging in the templates.
188	* @{ */
189	#define PGM_TYPE_REAL 1
190	#define PGM_TYPE_PROT 2
191	#define PGM_TYPE_32BIT 3
192	#define PGM_TYPE_PAE 4
193	#define PGM_TYPE_AMD64 5
194	#define PGM_TYPE_NESTED_32BIT 6
195	#define PGM_TYPE_NESTED_PAE 7
196	#define PGM_TYPE_NESTED_AMD64 8
197	#define PGM_TYPE_EPT 9
198	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
199	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
200	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
201	/** @} */
202
203	/** Macro for checking if the guest is using paging.
204	* @param uGstType PGM_TYPE_*
205	* @param uShwType PGM_TYPE_*
206	* @remark ASSUMES certain order of the PGM_TYPE_* values.
207	*/
208	#define PGM_WITH_PAGING(uGstType, uShwType) \
209	( (uGstType) >= PGM_TYPE_32BIT \
210	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
211
212	/** Macro for checking if the guest supports the NX bit.
213	* @param uGstType PGM_TYPE_*
214	* @param uShwType PGM_TYPE_*
215	* @remark ASSUMES certain order of the PGM_TYPE_* values.
216	*/
217	#define PGM_WITH_NX(uGstType, uShwType) \
218	( (uGstType) >= PGM_TYPE_PAE \
219	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
220
221	/** Macro for checking for nested.
222	* @param uType PGM_TYPE_*
223	*/
224	#define PGM_TYPE_IS_NESTED(uType) \
225	( (uType) == PGM_TYPE_NESTED_32BIT \
226	\|\| (uType) == PGM_TYPE_NESTED_PAE \
227	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
228
229	/** Macro for checking for nested or EPT.
230	* @param uType PGM_TYPE_*
231	*/
232	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
233	( (uType) == PGM_TYPE_NESTED_32BIT \
234	\|\| (uType) == PGM_TYPE_NESTED_PAE \
235	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
236	\|\| (uType) == PGM_TYPE_EPT)
237
238
239
240	/** @def PGM_HCPHYS_2_PTR
241	* Maps a HC physical page pool address to a virtual address.
242	*
243	* @returns VBox status code.
244	* @param pVM The cross context VM structure.
245	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
246	* @param HCPhys The HC physical address to map to a virtual one.
247	* @param ppv Where to store the virtual address. No need to cast
248	* this.
249	*
250	* @remark There is no need to assert on the result.
251	*/
252	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
253
254	/** @def PGM_GCPHYS_2_PTR_V2
255	* Maps a GC physical page address to a virtual address.
256	*
257	* @returns VBox status code.
258	* @param pVM The cross context VM structure.
259	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
260	* @param GCPhys The GC physical address to map to a virtual one.
261	* @param ppv Where to store the virtual address. No need to cast this.
262	*
263	* @remark Use with care as we don't have so much dynamic mapping space in
264	* ring-0 on 32-bit darwin and in RC.
265	* @remark There is no need to assert on the result.
266	*/
267	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
268	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
269
270	/** @def PGM_GCPHYS_2_PTR
271	* Maps a GC physical page address to a virtual address.
272	*
273	* @returns VBox status code.
274	* @param pVM The cross context VM structure.
275	* @param GCPhys The GC physical address to map to a virtual one.
276	* @param ppv Where to store the virtual address. No need to cast this.
277	*
278	* @remark Use with care as we don't have so much dynamic mapping space in
279	* ring-0 on 32-bit darwin and in RC.
280	* @remark There is no need to assert on the result.
281	*/
282	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
283
284	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
285	* Maps a GC physical page address to a virtual address.
286	*
287	* @returns VBox status code.
288	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
289	* @param GCPhys The GC physical address to map to a virtual one.
290	* @param ppv Where to store the virtual address. No need to cast this.
291	*
292	* @remark Use with care as we don't have so much dynamic mapping space in
293	* ring-0 on 32-bit darwin and in RC.
294	* @remark There is no need to assert on the result.
295	*/
296	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
297
298	/** @def PGM_GCPHYS_2_PTR_EX
299	* Maps a unaligned GC physical page address to a virtual address.
300	*
301	* @returns VBox status code.
302	* @param pVM The cross context VM structure.
303	* @param GCPhys The GC physical address to map to a virtual one.
304	* @param ppv Where to store the virtual address. No need to cast this.
305	*
306	* @remark Use with care as we don't have so much dynamic mapping space in
307	* ring-0 on 32-bit darwin and in RC.
308	* @remark There is no need to assert on the result.
309	*/
310	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
312
313	/** @def PGM_DYNMAP_UNUSED_HINT
314	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
315	* is no longer used.
316	*
317	* For best effect only apply this to the page that was mapped most recently.
318	*
319	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
320	* @param pvPage The pool page.
321	*/
322	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
323
324	/** @def PGM_DYNMAP_UNUSED_HINT_VM
325	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
326	* is no longer used.
327	*
328	* For best effect only apply this to the page that was mapped most recently.
329	*
330	* @param pVM The cross context VM structure.
331	* @param pvPage The pool page.
332	*/
333	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
334
335
336	/** @def PGM_INVL_PG
337	* Invalidates a page.
338	*
339	* @param pVCpu The cross context virtual CPU structure.
340	* @param GCVirt The virtual address of the page to invalidate.
341	*/
342	#ifdef IN_RING0
343	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
344	#elif defined(IN_RING3)
345	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
346	#else
347	# error "Not IN_RING0 or IN_RING3!"
348	#endif
349
350	/** @def PGM_INVL_PG_ALL_VCPU
351	* Invalidates a page on all VCPUs
352	*
353	* @param pVM The cross context VM structure.
354	* @param GCVirt The virtual address of the page to invalidate.
355	*/
356	#ifdef IN_RING0
357	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
358	#else
359	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
360	#endif
361
362	/** @def PGM_INVL_BIG_PG
363	* Invalidates a 4MB page directory entry.
364	*
365	* @param pVCpu The cross context virtual CPU structure.
366	* @param GCVirt The virtual address within the page directory to invalidate.
367	*/
368	#ifdef IN_RING0
369	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
370	#else
371	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
372	#endif
373
374	/** @def PGM_INVL_VCPU_TLBS()
375	* Invalidates the TLBs of the specified VCPU
376	*
377	* @param pVCpu The cross context virtual CPU structure.
378	*/
379	#ifdef IN_RING0
380	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
381	#else
382	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
383	#endif
384
385	/** @def PGM_INVL_ALL_VCPU_TLBS()
386	* Invalidates the TLBs of all VCPUs
387	*
388	* @param pVM The cross context VM structure.
389	*/
390	#ifdef IN_RING0
391	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
392	#else
393	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
394	#endif
395
396
397	/** @name Safer Shadow PAE PT/PTE
398	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
399	* present.
400	*
401	* @{
402	*/
403	#if 1
404	/**
405	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
406	* invalid entries for present.
407	* @sa X86PTEPAE.
408	*/
409	typedef union PGMSHWPTEPAE
410	{
411	/** Unsigned integer view */
412	X86PGPAEUINT uCareful;
413	/* Not other views. */
414	} PGMSHWPTEPAE;
415
416	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
417	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
418	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
419	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
420	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
421	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
422	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
423	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
424	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
425	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
426	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
427	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
428	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
429	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
430	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
431	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
432
433	/**
434	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
435	* invalid entries for present.
436	* @sa X86PTPAE.
437	*/
438	typedef struct PGMSHWPTPAE
439	{
440	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
441	} PGMSHWPTPAE;
442
443	#else
444	typedef X86PTEPAE PGMSHWPTEPAE;
445	typedef X86PTPAE PGMSHWPTPAE;
446	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
447	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
448	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
449	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
450	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
451	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
452	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
453	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
454	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
455	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
456	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
457	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
458	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
459	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
460	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
461	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
462
463	#endif
464
465	/** Pointer to a shadow PAE PTE. */
466	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
467	/** Pointer to a const shadow PAE PTE. */
468	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
469
470	/** Pointer to a shadow PAE page table. */
471	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
472	/** Pointer to a const shadow PAE page table. */
473	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
474	/** @} */
475
476
477	/**
478	* Physical page access handler type registration.
479	*/
480	typedef struct PGMPHYSHANDLERTYPEINT
481	{
482	/** Number of references. */
483	uint32_t volatile cRefs;
484	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
485	uint32_t u32Magic;
486	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
487	RTLISTOFF32NODE ListNode;
488	/** The kind of accesses we're handling. */
489	PGMPHYSHANDLERKIND enmKind;
490	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
491	uint32_t uState;
492	/** Pointer to R3 callback function. */
493	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
494	/** Pointer to R0 callback function. */
495	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
496	/** Pointer to R0 callback function for \#PFs. */
497	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
498	/** Description / Name. For easing debugging. */
499	R3PTRTYPE(const char *) pszDesc;
500	} PGMPHYSHANDLERTYPEINT;
501	/** Pointer to a physical access handler type registration. */
502	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
503	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
504	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
505	/** Magic value for the physical handler callbacks. */
506	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
507
508	/**
509	* Converts a handle to a pointer.
510	* @returns PPGMPHYSHANDLERTYPEINT
511	* @param a_pVM The cross context VM structure.
512	* @param a_hType Physical access handler type handle.
513	*/
514	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
515
516
517	/**
518	* Physical page access handler structure.
519	*
520	* This is used to keep track of physical address ranges
521	* which are being monitored in some kind of way.
522	*/
523	typedef struct PGMPHYSHANDLER
524	{
525	AVLROGCPHYSNODECORE Core;
526	/** Number of pages to update. */
527	uint32_t cPages;
528	/** Set if we have pages that have been aliased. */
529	uint32_t cAliasedPages;
530	/** Set if we have pages that have temporarily been disabled. */
531	uint32_t cTmpOffPages;
532	/** Registered handler type handle (heap offset). */
533	PGMPHYSHANDLERTYPE hType;
534	/** User argument for R3 handlers. */
535	R3PTRTYPE(void *) pvUserR3;
536	/** User argument for R0 handlers. */
537	R0PTRTYPE(void *) pvUserR0;
538	/** Description / Name. For easing debugging. */
539	R3PTRTYPE(const char *) pszDesc;
540	#ifdef VBOX_WITH_STATISTICS
541	/** Profiling of this handler. */
542	STAMPROFILE Stat;
543	#endif
544	} PGMPHYSHANDLER;
545	/** Pointer to a physical page access handler structure. */
546	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
547
548	/**
549	* Gets the type record for a physical handler (no reference added).
550	* @returns PPGMPHYSHANDLERTYPEINT
551	* @param a_pVM The cross context VM structure.
552	* @param a_pPhysHandler Pointer to the physical handler structure
553	* (PGMPHYSHANDLER).
554	*/
555	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
556
557
558	/**
559	* A Physical Guest Page tracking structure.
560	*
561	* The format of this structure is complicated because we have to fit a lot
562	* of information into as few bits as possible. The format is also subject
563	* to change (there is one coming up soon). Which means that for we'll be
564	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
565	* accesses to the structure.
566	*/
567	typedef union PGMPAGE
568	{
569	/** Structured view. */
570	struct
571	{
572	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
573	uint64_t u2HandlerPhysStateY : 2;
574	/** 3:2 - Paging structure needed to map the page
575	* (PGM_PAGE_PDE_TYPE_). /
576	uint64_t u2PDETypeY : 2;
577	/** 4 - Unused (was used by FTE for dirty tracking). */
578	uint64_t fUnused1 : 1;
579	/** 5 - Flag indicating that a write monitored page was written to
580	* when set. */
581	uint64_t fWrittenToY : 1;
582	/** 7:6 - Unused. */
583	uint64_t u2Unused0 : 2;
584	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
585	uint64_t u2Unused1 : 2;
586	/** 11:10 - NEM state bits. */
587	uint64_t u2NemStateY : 2;
588	/** 12:48 - The host physical frame number (shift left to get the
589	* address). */
590	uint64_t HCPhysFN : 36;
591	/** 50:48 - The page state. */
592	uint64_t uStateY : 3;
593	/** 51:53 - The page type (PGMPAGETYPE). */
594	uint64_t uTypeY : 3;
595	/** 63:54 - PTE index for usage tracking (page pool). */
596	uint64_t u10PteIdx : 10;
597
598	/** The GMM page ID.
599	* @remarks In the current implementation, MMIO2 and pages aliased to
600	* MMIO2 pages will be exploiting this field to calculate the
601	* ring-3 mapping address corresponding to the page.
602	* Later we may consider including MMIO2 management into GMM. */
603	uint32_t idPage;
604	/** Usage tracking (page pool). */
605	uint16_t u16TrackingY;
606	/** The number of read locks on this page. */
607	uint8_t cReadLocksY;
608	/** The number of write locks on this page. */
609	uint8_t cWriteLocksY;
610	} s;
611
612	/** 64-bit integer view. */
613	uint64_t au64[2];
614	/** 16-bit view. */
615	uint32_t au32[4];
616	/** 16-bit view. */
617	uint16_t au16[8];
618	/** 8-bit view. */
619	uint8_t au8[16];
620	} PGMPAGE;
621	AssertCompileSize(PGMPAGE, 16);
622	/** Pointer to a physical guest page. */
623	typedef PGMPAGE *PPGMPAGE;
624	/** Pointer to a const physical guest page. */
625	typedef const PGMPAGE *PCPGMPAGE;
626	/** Pointer to a physical guest page pointer. */
627	typedef PPGMPAGE *PPPGMPAGE;
628
629
630	/**
631	* Clears the page structure.
632	* @param a_pPage Pointer to the physical guest page tracking structure.
633	*/
634	#define PGM_PAGE_CLEAR(a_pPage) \
635	do { \
636	(a_pPage)->au64[0] = 0; \
637	(a_pPage)->au64[1] = 0; \
638	} while (0)
639
640	/**
641	* Initializes the page structure.
642	* @param a_pPage Pointer to the physical guest page tracking structure.
643	* @param a_HCPhys The host physical address of the page.
644	* @param a_idPage The (GMM) page ID of the page.
645	* @param a_uType The page type (PGMPAGETYPE).
646	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
647	*/
648	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
649	do { \
650	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
651	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
652	(a_pPage)->au64[0] = SetHCPhysTmp; \
653	(a_pPage)->au64[1] = 0; \
654	(a_pPage)->s.idPage = (a_idPage); \
655	(a_pPage)->s.uStateY = (a_uState); \
656	(a_pPage)->s.uTypeY = (a_uType); \
657	} while (0)
658
659	/**
660	* Initializes the page structure of a ZERO page.
661	* @param a_pPage Pointer to the physical guest page tracking structure.
662	* @param a_pVM The VM handle (for getting the zero page address).
663	* @param a_uType The page type (PGMPAGETYPE).
664	*/
665	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
666	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
667
668
669	/** @name The Page state, PGMPAGE::uStateY.
670	* @{ */
671	/** The zero page.
672	* This is a per-VM page that's never ever mapped writable. */
673	#define PGM_PAGE_STATE_ZERO 0U
674	/** A allocated page.
675	* This is a per-VM page allocated from the page pool (or wherever
676	* we get MMIO2 pages from if the type is MMIO2).
677	*/
678	#define PGM_PAGE_STATE_ALLOCATED 1U
679	/** A allocated page that's being monitored for writes.
680	* The shadow page table mappings are read-only. When a write occurs, the
681	* fWrittenTo member is set, the page remapped as read-write and the state
682	* moved back to allocated. */
683	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
684	/** The page is shared, aka. copy-on-write.
685	* This is a page that's shared with other VMs. */
686	#define PGM_PAGE_STATE_SHARED 3U
687	/** The page is ballooned, so no longer available for this VM. */
688	#define PGM_PAGE_STATE_BALLOONED 4U
689	/** @} */
690
691
692	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
693	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
694	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
695	#else
696	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
697	#endif
698
699	/**
700	* Gets the page state.
701	* @returns page state (PGM_PAGE_STATE_*).
702	* @param a_pPage Pointer to the physical guest page tracking structure.
703	*
704	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
705	* builds.
706	*/
707	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
708	#if defined(__GNUC__) && defined(VBOX_STRICT)
709	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
710	#else
711	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
712	#endif
713
714	/**
715	* Sets the page state.
716	* @param a_pVM The VM handle, only used for lock ownership assertions.
717	* @param a_pPage Pointer to the physical guest page tracking structure.
718	* @param a_uState The new page state.
719	*/
720	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
721	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
722
723
724	/**
725	* Gets the host physical address of the guest page.
726	* @returns host physical address (RTHCPHYS).
727	* @param a_pPage Pointer to the physical guest page tracking structure.
728	*
729	* @remarks In strict builds on gcc platforms, this macro will make some ugly
730	* assumption about a valid pVM variable/parameter being in the
731	* current context. It will use this pVM variable to assert that the
732	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
733	* pVM is not around.
734	*/
735	#if 0
736	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
737	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
738	#else
739	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
740	# if defined(__GNUC__) && defined(VBOX_STRICT)
741	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
742	# else
743	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
744	# endif
745	#endif
746
747	/**
748	* Sets the host physical address of the guest page.
749	*
750	* @param a_pVM The VM handle, only used for lock ownership assertions.
751	* @param a_pPage Pointer to the physical guest page tracking structure.
752	* @param a_HCPhys The new host physical address.
753	*/
754	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
755	do { \
756	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
757	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
758	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
759	PGM_PAGE_ASSERT_LOCK(a_pVM); \
760	} while (0)
761
762	/**
763	* Get the Page ID.
764	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
765	* @param a_pPage Pointer to the physical guest page tracking structure.
766	*/
767	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
768
769	/**
770	* Sets the Page ID.
771	* @param a_pVM The VM handle, only used for lock ownership assertions.
772	* @param a_pPage Pointer to the physical guest page tracking structure.
773	* @param a_idPage The new page ID.
774	*/
775	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
776	do { \
777	(a_pPage)->s.idPage = (a_idPage); \
778	PGM_PAGE_ASSERT_LOCK(a_pVM); \
779	} while (0)
780
781	/**
782	* Get the Chunk ID.
783	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
784	* @param a_pPage Pointer to the physical guest page tracking structure.
785	*/
786	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
787
788	/**
789	* Get the index of the page within the allocation chunk.
790	* @returns The page index.
791	* @param a_pPage Pointer to the physical guest page tracking structure.
792	*/
793	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
794
795	/**
796	* Gets the page type.
797	* @returns The page type.
798	* @param a_pPage Pointer to the physical guest page tracking structure.
799	*
800	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
801	* builds.
802	*/
803	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
804	#if defined(__GNUC__) && defined(VBOX_STRICT)
805	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
806	#else
807	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
808	#endif
809
810	/**
811	* Sets the page type.
812	*
813	* @param a_pVM The VM handle, only used for lock ownership assertions.
814	* @param a_pPage Pointer to the physical guest page tracking structure.
815	* @param a_enmType The new page type (PGMPAGETYPE).
816	*/
817	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
818	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
819
820	/**
821	* Gets the page table index
822	* @returns The page table index.
823	* @param a_pPage Pointer to the physical guest page tracking structure.
824	*/
825	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
826
827	/**
828	* Sets the page table index.
829	* @param a_pVM The VM handle, only used for lock ownership assertions.
830	* @param a_pPage Pointer to the physical guest page tracking structure.
831	* @param a_iPte New page table index.
832	*/
833	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
834	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
835
836	/**
837	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
838	* @returns true/false.
839	* @param a_pPage Pointer to the physical guest page tracking structure.
840	*/
841	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
842
843	/**
844	* Checks if the page is marked for MMIO, including both aliases.
845	* @returns true/false.
846	* @param a_pPage Pointer to the physical guest page tracking structure.
847	*/
848	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
849	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
850	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
851	)
852
853	/**
854	* Checks if the page is marked for MMIO, including special aliases.
855	* @returns true/false.
856	* @param a_pPage Pointer to the physical guest page tracking structure.
857	*/
858	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
859	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
860
861	/**
862	* Checks if the page is a special aliased MMIO page.
863	* @returns true/false.
864	* @param a_pPage Pointer to the physical guest page tracking structure.
865	*/
866	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
867
868	/**
869	* Checks if the page is backed by the ZERO page.
870	* @returns true/false.
871	* @param a_pPage Pointer to the physical guest page tracking structure.
872	*/
873	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
874
875	/**
876	* Checks if the page is backed by a SHARED page.
877	* @returns true/false.
878	* @param a_pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
881
882	/**
883	* Checks if the page is ballooned.
884	* @returns true/false.
885	* @param a_pPage Pointer to the physical guest page tracking structure.
886	*/
887	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
888
889	/**
890	* Checks if the page is allocated.
891	* @returns true/false.
892	* @param a_pPage Pointer to the physical guest page tracking structure.
893	*/
894	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
895
896	/**
897	* Marks the page as written to (for GMM change monitoring).
898	* @param a_pVM The VM handle, only used for lock ownership assertions.
899	* @param a_pPage Pointer to the physical guest page tracking structure.
900	*/
901	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
902	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
903
904	/**
905	* Clears the written-to indicator.
906	* @param a_pVM The VM handle, only used for lock ownership assertions.
907	* @param a_pPage Pointer to the physical guest page tracking structure.
908	*/
909	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
910	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
911
912	/**
913	* Checks if the page was marked as written-to.
914	* @returns true/false.
915	* @param a_pPage Pointer to the physical guest page tracking structure.
916	*/
917	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
918
919
920	/** @name PT usage values (PGMPAGE::u2PDEType).
921	*
922	* @{ */
923	/** Either as a PT or PDE. */
924	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
925	/** Must use a page table to map the range. */
926	#define PGM_PAGE_PDE_TYPE_PT 1
927	/** Can use a page directory entry to map the continuous range. */
928	#define PGM_PAGE_PDE_TYPE_PDE 2
929	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
930	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
931	/** @} */
932
933	/**
934	* Set the PDE type of the page
935	* @param a_pVM The VM handle, only used for lock ownership assertions.
936	* @param a_pPage Pointer to the physical guest page tracking structure.
937	* @param a_uType PGM_PAGE_PDE_TYPE_*.
938	*/
939	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
940	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
941
942	/**
943	* Checks if the page was marked being part of a large page
944	* @returns true/false.
945	* @param a_pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
948
949	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
950	*
951	* @remarks The values are assigned in order of priority, so we can calculate
952	* the correct state for a page with different handlers installed.
953	* @{ */
954	/** No handler installed. */
955	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
956	/** Monitoring is temporarily disabled. */
957	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
958	/** Write access is monitored. */
959	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
960	/** All access is monitored. */
961	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
962	/** @} */
963
964	/**
965	* Gets the physical access handler state of a page.
966	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
967	* @param a_pPage Pointer to the physical guest page tracking structure.
968	*/
969	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
970
971	/**
972	* Sets the physical access handler state of a page.
973	* @param a_pPage Pointer to the physical guest page tracking structure.
974	* @param a_uState The new state value.
975	*/
976	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
977	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
978
979	/**
980	* Checks if the page has any physical access handlers, including temporarily disabled ones.
981	* @returns true/false
982	* @param a_pPage Pointer to the physical guest page tracking structure.
983	*/
984	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
985	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
986
987	/**
988	* Checks if the page has any active physical access handlers.
989	* @returns true/false
990	* @param a_pPage Pointer to the physical guest page tracking structure.
991	*/
992	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
993	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
994
995	/**
996	* Checks if the page has any access handlers, including temporarily disabled ones.
997	* @returns true/false
998	* @param a_pPage Pointer to the physical guest page tracking structure.
999	*/
1000	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1001	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1002
1003	/**
1004	* Checks if the page has any active access handlers.
1005	* @returns true/false
1006	* @param a_pPage Pointer to the physical guest page tracking structure.
1007	*/
1008	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1009	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1010
1011	/**
1012	* Checks if the page has any active access handlers catching all accesses.
1013	* @returns true/false
1014	* @param a_pPage Pointer to the physical guest page tracking structure.
1015	*/
1016	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1017	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1018
1019
1020	/** @def PGM_PAGE_GET_TRACKING
1021	* Gets the packed shadow page pool tracking data associated with a guest page.
1022	* @returns uint16_t containing the data.
1023	* @param a_pPage Pointer to the physical guest page tracking structure.
1024	*/
1025	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1026	#if defined(__GNUC__) && defined(VBOX_STRICT)
1027	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1028	#else
1029	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1030	#endif
1031
1032	/** @def PGM_PAGE_SET_TRACKING
1033	* Sets the packed shadow page pool tracking data associated with a guest page.
1034	* @param a_pVM The VM handle, only used for lock ownership assertions.
1035	* @param a_pPage Pointer to the physical guest page tracking structure.
1036	* @param a_u16TrackingData The tracking data to store.
1037	*/
1038	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1039	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1040
1041	/** @def PGM_PAGE_GET_TD_CREFS
1042	* Gets the @a cRefs tracking data member.
1043	* @returns cRefs.
1044	* @param a_pPage Pointer to the physical guest page tracking structure.
1045	*/
1046	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1047	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1048	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1049	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1050
1051	/** @def PGM_PAGE_GET_TD_IDX
1052	* Gets the @a idx tracking data member.
1053	* @returns idx.
1054	* @param a_pPage Pointer to the physical guest page tracking structure.
1055	*/
1056	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1057	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1058	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1059	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1060
1061
1062	/** Max number of locks on a page. */
1063	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1064
1065	/** Get the read lock count.
1066	* @returns count.
1067	* @param a_pPage Pointer to the physical guest page tracking structure.
1068	*/
1069	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1070
1071	/** Get the write lock count.
1072	* @returns count.
1073	* @param a_pPage Pointer to the physical guest page tracking structure.
1074	*/
1075	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1076
1077	/** Decrement the read lock counter.
1078	* @param a_pPage Pointer to the physical guest page tracking structure.
1079	*/
1080	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1081
1082	/** Decrement the write lock counter.
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1086
1087	/** Increment the read lock counter.
1088	* @param a_pPage Pointer to the physical guest page tracking structure.
1089	*/
1090	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1091
1092	/** Increment the write lock counter.
1093	* @param a_pPage Pointer to the physical guest page tracking structure.
1094	*/
1095	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1096
1097
1098	/** Gets the NEM state.
1099	* @returns NEM state value (two bits).
1100	* @param a_pPage Pointer to the physical guest page tracking structure.
1101	*/
1102	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1103
1104	/** Sets the NEM state.
1105	* @param a_pPage Pointer to the physical guest page tracking structure.
1106	* @param a_u2State The NEM state value (specific to NEM impl.).
1107	*/
1108	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1109	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1110
1111
1112	#if 0
1113	/** Enables sanity checking of write monitoring using CRC-32. */
1114	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1115	#endif
1116
1117	/**
1118	* Per page live save tracking data.
1119	*/
1120	typedef struct PGMLIVESAVERAMPAGE
1121	{
1122	/** Number of times it has been dirtied. */
1123	uint32_t cDirtied : 24;
1124	/** Whether it is currently dirty. */
1125	uint32_t fDirty : 1;
1126	/** Ignore the page.
1127	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1128	* deal with these after pausing the VM and DevPCI have said it bit about
1129	* remappings. */
1130	uint32_t fIgnore : 1;
1131	/** Was a ZERO page last time around. */
1132	uint32_t fZero : 1;
1133	/** Was a SHARED page last time around. */
1134	uint32_t fShared : 1;
1135	/** Whether the page is/was write monitored in a previous pass. */
1136	uint32_t fWriteMonitored : 1;
1137	/** Whether the page is/was write monitored earlier in this pass. */
1138	uint32_t fWriteMonitoredJustNow : 1;
1139	/** Bits reserved for future use. */
1140	uint32_t u2Reserved : 2;
1141	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1142	/** CRC-32 for the page. This is for internal consistency checks. */
1143	uint32_t u32Crc;
1144	#endif
1145	} PGMLIVESAVERAMPAGE;
1146	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1147	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1148	#else
1149	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1150	#endif
1151	/** Pointer to the per page live save tracking data. */
1152	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1153
1154	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1155	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1156
1157
1158	/**
1159	* RAM range for GC Phys to HC Phys conversion.
1160	*
1161	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1162	* conversions too, but we'll let MM handle that for now.
1163	*
1164	* This structure is used by linked lists in both GC and HC.
1165	*/
1166	typedef struct PGMRAMRANGE
1167	{
1168	/** Start of the range. Page aligned. */
1169	RTGCPHYS GCPhys;
1170	/** Size of the range. (Page aligned of course). */
1171	RTGCPHYS cb;
1172	/** Pointer to the next RAM range - for R3. */
1173	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1174	/** Pointer to the next RAM range - for R0. */
1175	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1176	/** PGM_RAM_RANGE_FLAGS_* flags. */
1177	uint32_t fFlags;
1178	uint32_t fPadding1;
1179	/** Last address in the range (inclusive). Page aligned (-1). */
1180	RTGCPHYS GCPhysLast;
1181	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1182	R3PTRTYPE(void *) pvR3;
1183	/** Live save per page tracking data. */
1184	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1185	/** The range description. */
1186	R3PTRTYPE(const char *) pszDesc;
1187	/** Pointer to self - R0 pointer. */
1188	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1189
1190	/** Pointer to the left search three node - ring-3 context. */
1191	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1192	/** Pointer to the right search three node - ring-3 context. */
1193	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1194	/** Pointer to the left search three node - ring-0 context. */
1195	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1196	/** Pointer to the right search three node - ring-0 context. */
1197	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1198
1199	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1200	#if HC_ARCH_BITS == 32
1201	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1202	#endif
1203	/** Array of physical guest page tracking structures. */
1204	PGMPAGE aPages[1];
1205	} PGMRAMRANGE;
1206	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1207	typedef PGMRAMRANGE *PPGMRAMRANGE;
1208
1209	/** @name PGMRAMRANGE::fFlags
1210	* @{ */
1211	/** The RAM range is floating around as an independent guest mapping. */
1212	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1213	/** Ad hoc RAM range for an ROM mapping. */
1214	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1215	/** Ad hoc RAM range for an MMIO mapping. */
1216	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1217	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1218	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1219	/** @} */
1220
1221	/** Tests if a RAM range is an ad hoc one or not.
1222	* @returns true/false.
1223	* @param pRam The RAM range.
1224	*/
1225	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1226	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1227
1228	/** The number of entries in the RAM range TLBs (there is one for each
1229	* context). Must be a power of two. */
1230	#define PGM_RAMRANGE_TLB_ENTRIES 8
1231
1232	/**
1233	* Calculates the RAM range TLB index for the physical address.
1234	*
1235	* @returns RAM range TLB index.
1236	* @param a_GCPhys The guest physical address.
1237	*/
1238	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1239
1240	/**
1241	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1242	* mapping address.
1243	*/
1244	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1245	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1246
1247
1248	/**
1249	* Per page tracking structure for ROM image.
1250	*
1251	* A ROM image may have a shadow page, in which case we may have two pages
1252	* backing it. This structure contains the PGMPAGE for both while
1253	* PGMRAMRANGE have a copy of the active one. It is important that these
1254	* aren't out of sync in any regard other than page pool tracking data.
1255	*/
1256	typedef struct PGMROMPAGE
1257	{
1258	/** The page structure for the virgin ROM page. */
1259	PGMPAGE Virgin;
1260	/** The page structure for the shadow RAM page. */
1261	PGMPAGE Shadow;
1262	/** The current protection setting. */
1263	PGMROMPROT enmProt;
1264	/** Live save status information. Makes use of unused alignment space. */
1265	struct
1266	{
1267	/** The previous protection value. */
1268	uint8_t u8Prot;
1269	/** Written to flag set by the handler. */
1270	bool fWrittenTo;
1271	/** Whether the shadow page is dirty or not. */
1272	bool fDirty;
1273	/** Whether it was dirtied in the recently. */
1274	bool fDirtiedRecently;
1275	} LiveSave;
1276	} PGMROMPAGE;
1277	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1278	/** Pointer to a ROM page tracking structure. */
1279	typedef PGMROMPAGE *PPGMROMPAGE;
1280
1281
1282	/**
1283	* A registered ROM image.
1284	*
1285	* This is needed to keep track of ROM image since they generally intrude
1286	* into a PGMRAMRANGE. It also keeps track of additional info like the
1287	* two page sets (read-only virgin and read-write shadow), the current
1288	* state of each page.
1289	*
1290	* Because access handlers cannot easily be executed in a different
1291	* context, the ROM ranges needs to be accessible and in all contexts.
1292	*/
1293	typedef struct PGMROMRANGE
1294	{
1295	/** Pointer to the next range - R3. */
1296	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1297	/** Pointer to the next range - R0. */
1298	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1299	/** Address of the range. */
1300	RTGCPHYS GCPhys;
1301	/** Address of the last byte in the range. */
1302	RTGCPHYS GCPhysLast;
1303	/** Size of the range. */
1304	RTGCPHYS cb;
1305	/** The flags (PGMPHYS_ROM_FLAGS_). /
1306	uint8_t fFlags;
1307	/** The saved state range ID. */
1308	uint8_t idSavedState;
1309	/** Alignment padding. */
1310	uint8_t au8Alignment[2];
1311	/** The size bits pvOriginal points to. */
1312	uint32_t cbOriginal;
1313	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1314	* This is used for strictness checks. */
1315	R3PTRTYPE(const void *) pvOriginal;
1316	/** The ROM description. */
1317	R3PTRTYPE(const char *) pszDesc;
1318	#ifdef VBOX_WITH_PGM_NEM_MODE
1319	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1320	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1321	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1322	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1323	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1324	R3PTRTYPE(uint8_t *) pbR3Alternate;
1325	RTR3PTR pvAlignment2;
1326	#endif
1327	/** The per page tracking structures. */
1328	PGMROMPAGE aPages[1];
1329	} PGMROMRANGE;
1330	/** Pointer to a ROM range. */
1331	typedef PGMROMRANGE *PPGMROMRANGE;
1332
1333
1334	/**
1335	* Live save per page data for an MMIO2 page.
1336	*
1337	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1338	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1339	* CRC-32 for detecting changes as well as special handling of zero pages. This
1340	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1341	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1342	* because of speed (2.5x and 6x slower).)
1343	*
1344	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1345	* save but normally is disabled. Since we can write monitor guest
1346	* accesses on our own, we only need this for host accesses. Shouldn't be
1347	* too difficult for DevVGA, VMMDev might be doable, the planned
1348	* networking fun will be fun since it involves ring-0.
1349	*/
1350	typedef struct PGMLIVESAVEMMIO2PAGE
1351	{
1352	/** Set if the page is considered dirty. */
1353	bool fDirty;
1354	/** The number of scans this page has remained unchanged for.
1355	* Only updated for dirty pages. */
1356	uint8_t cUnchangedScans;
1357	/** Whether this page was zero at the last scan. */
1358	bool fZero;
1359	/** Alignment padding. */
1360	bool fReserved;
1361	/** CRC-32 for the first half of the page.
1362	* This is used together with u32CrcH2 to quickly detect changes in the page
1363	* during the non-final passes. */
1364	uint32_t u32CrcH1;
1365	/** CRC-32 for the second half of the page. */
1366	uint32_t u32CrcH2;
1367	/** SHA-1 for the saved page.
1368	* This is used in the final pass to skip pages without changes. */
1369	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1370	} PGMLIVESAVEMMIO2PAGE;
1371	/** Pointer to a live save status data for an MMIO2 page. */
1372	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1373
1374	/**
1375	* A registered MMIO2 (= Device RAM) range.
1376	*
1377	* There are a few reason why we need to keep track of these registrations. One
1378	* of them is the deregistration & cleanup stuff, while another is that the
1379	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1380	* range list.
1381	*
1382	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1383	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1384	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1385	* overlap we will free all the existing RAM pages and put in the ram range
1386	* pages instead.
1387	*/
1388	typedef struct PGMREGMMIO2RANGE
1389	{
1390	/** The owner of the range. (a device) */
1391	PPDMDEVINSR3 pDevInsR3;
1392	/** Pointer to the ring-3 mapping of the allocation. */
1393	RTR3PTR pvR3;
1394	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1395	/** Pointer to the ring-0 mapping of the allocation. */
1396	RTR0PTR pvR0;
1397	#endif
1398	/** Pointer to the next range - R3. */
1399	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1400	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1401	uint16_t fFlags;
1402	/** The sub device number (internal PCI config (CFGM) number). */
1403	uint8_t iSubDev;
1404	/** The PCI region number. */
1405	uint8_t iRegion;
1406	/** The saved state range ID. */
1407	uint8_t idSavedState;
1408	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1409	uint8_t idMmio2;
1410	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1411	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1412	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1413	#else
1414	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1415	#endif
1416	/** The real size.
1417	* This may be larger than indicated by RamRange.cb if the range has been
1418	* reduced during saved state loading. */
1419	RTGCPHYS cbReal;
1420	/** Pointer to the physical handler for MMIO. */
1421	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1422	/** Live save per page tracking data for MMIO2. */
1423	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1424	/** The associated RAM range. */
1425	PGMRAMRANGE RamRange;
1426	} PGMREGMMIO2RANGE;
1427	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1428	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1429	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1430
1431	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1432	* @{ */
1433	/** Set if it's an MMIO2 range.
1434	* @note Historical. For a while we did some of the MMIO this way too. */
1435	#define PGMREGMMIO2RANGE_F_MMIO2 UINT16_C(0x0001)
1436	/** Set if this is the first chunk in the MMIO2 range. */
1437	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1438	/** Set if this is the last chunk in the MMIO2 range. */
1439	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0004)
1440	/** Set if the whole range is mapped. */
1441	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0008)
1442	/** Set if it's overlapping, clear if not. */
1443	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0010)
1444	/** @} */
1445
1446
1447	/** @name Internal MMIO2 constants.
1448	* @{ */
1449	/** The maximum number of MMIO2 ranges. */
1450	#define PGM_MMIO2_MAX_RANGES 32
1451	/** The maximum number of pages in a MMIO2 range. */
1452	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1453	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1454	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1455	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1456	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1457	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1458	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1459	/** @} */
1460
1461
1462
1463	/**
1464	* PGMPhysRead/Write cache entry
1465	*/
1466	typedef struct PGMPHYSCACHEENTRY
1467	{
1468	/** R3 pointer to physical page. */
1469	R3PTRTYPE(uint8_t *) pbR3;
1470	/** GC Physical address for cache entry */
1471	RTGCPHYS GCPhys;
1472	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1473	RTGCPHYS u32Padding0; /*< alignment padding. /
1474	#endif
1475	} PGMPHYSCACHEENTRY;
1476
1477	/**
1478	* PGMPhysRead/Write cache to reduce REM memory access overhead
1479	*/
1480	typedef struct PGMPHYSCACHE
1481	{
1482	/** Bitmap of valid cache entries */
1483	uint64_t aEntries;
1484	/** Cache entries */
1485	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1486	} PGMPHYSCACHE;
1487
1488
1489	/** @name Ring-3 page mapping TLBs
1490	* @{ */
1491
1492	/** Pointer to an allocation chunk ring-3 mapping. */
1493	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1494	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1495	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1496
1497	/**
1498	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1499	*
1500	* The primary tree (Core) uses the chunk id as key.
1501	*/
1502	typedef struct PGMCHUNKR3MAP
1503	{
1504	/** The key is the chunk id. */
1505	AVLU32NODECORE Core;
1506	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1507	* selection. */
1508	uint32_t iLastUsed;
1509	/** The current reference count. */
1510	uint32_t volatile cRefs;
1511	/** The current permanent reference count. */
1512	uint32_t volatile cPermRefs;
1513	/** The mapping address. */
1514	void *pv;
1515	} PGMCHUNKR3MAP;
1516
1517	/**
1518	* Allocation chunk ring-3 mapping TLB entry.
1519	*/
1520	typedef struct PGMCHUNKR3MAPTLBE
1521	{
1522	/** The chunk id. */
1523	uint32_t volatile idChunk;
1524	#if HC_ARCH_BITS == 64
1525	uint32_t u32Padding; /*< alignment padding. /
1526	#endif
1527	/** The chunk map. */
1528	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1529	} PGMCHUNKR3MAPTLBE;
1530	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1531	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1532
1533	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1534	* @remark Must be a power of two value. */
1535	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1536
1537	/**
1538	* Allocation chunk ring-3 mapping TLB.
1539	*
1540	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1541	* At first glance this might look kinda odd since AVL trees are
1542	* supposed to give the most optimal lookup times of all trees
1543	* due to their balancing. However, take a tree with 1023 nodes
1544	* in it, that's 10 levels, meaning that most searches has to go
1545	* down 9 levels before they find what they want. This isn't fast
1546	* compared to a TLB hit. There is the factor of cache misses,
1547	* and of course the problem with trees and branch prediction.
1548	* This is why we use TLBs in front of most of the trees.
1549	*
1550	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1551	* difficult when we switch to the new inlined AVL trees (from kStuff).
1552	*/
1553	typedef struct PGMCHUNKR3MAPTLB
1554	{
1555	/** The TLB entries. */
1556	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1557	} PGMCHUNKR3MAPTLB;
1558
1559	/**
1560	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1561	* @returns Chunk TLB index.
1562	* @param idChunk The Chunk ID.
1563	*/
1564	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1565
1566
1567	/**
1568	* Ring-3 guest page mapping TLB entry.
1569	* @remarks used in ring-0 as well at the moment.
1570	*/
1571	typedef struct PGMPAGER3MAPTLBE
1572	{
1573	/** Address of the page. */
1574	RTGCPHYS volatile GCPhys;
1575	/** The guest page. */
1576	R3PTRTYPE(PPGMPAGE) volatile pPage;
1577	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1578	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1579	/** The address */
1580	R3PTRTYPE(void *) volatile pv;
1581	#if HC_ARCH_BITS == 32
1582	uint32_t u32Padding; /*< alignment padding. /
1583	#endif
1584	} PGMPAGER3MAPTLBE;
1585	/** Pointer to an entry in the HC physical TLB. */
1586	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1587
1588
1589	/** The number of entries in the ring-3 guest page mapping TLB.
1590	* @remarks The value must be a power of two. */
1591	#define PGM_PAGER3MAPTLB_ENTRIES 256
1592
1593	/**
1594	* Ring-3 guest page mapping TLB.
1595	* @remarks used in ring-0 as well at the moment.
1596	*/
1597	typedef struct PGMPAGER3MAPTLB
1598	{
1599	/** The TLB entries. */
1600	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1601	} PGMPAGER3MAPTLB;
1602	/** Pointer to the ring-3 guest page mapping TLB. */
1603	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1604
1605	/**
1606	* Calculates the index of the TLB entry for the specified guest page.
1607	* @returns Physical TLB index.
1608	* @param GCPhys The guest physical address.
1609	*/
1610	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1611
1612	/** @} */
1613
1614
1615	/** @name Ring-0 page mapping TLB
1616	* @{ */
1617	/**
1618	* Ring-0 guest page mapping TLB entry.
1619	*/
1620	typedef struct PGMPAGER0MAPTLBE
1621	{
1622	/** Address of the page. */
1623	RTGCPHYS volatile GCPhys;
1624	/** The guest page. */
1625	R0PTRTYPE(PPGMPAGE) volatile pPage;
1626	/** The address */
1627	R0PTRTYPE(void *) volatile pv;
1628	} PGMPAGER0MAPTLBE;
1629	/** Pointer to an entry in the HC physical TLB. */
1630	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1631
1632
1633	/** The number of entries in the ring-3 guest page mapping TLB.
1634	* @remarks The value must be a power of two. */
1635	#define PGM_PAGER0MAPTLB_ENTRIES 256
1636
1637	/**
1638	* Ring-3 guest page mapping TLB.
1639	* @remarks used in ring-0 as well at the moment.
1640	*/
1641	typedef struct PGMPAGER0MAPTLB
1642	{
1643	/** The TLB entries. */
1644	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1645	} PGMPAGER0MAPTLB;
1646	/** Pointer to the ring-3 guest page mapping TLB. */
1647	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1648
1649	/**
1650	* Calculates the index of the TLB entry for the specified guest page.
1651	* @returns Physical TLB index.
1652	* @param GCPhys The guest physical address.
1653	*/
1654	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1655	/** @} */
1656
1657
1658	/** @name Context neutral page mapper TLB.
1659	*
1660	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1661	* code is writting in a kind of context neutral way. Time will show whether
1662	* this actually makes sense or not...
1663	*
1664	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1665	* context ends up using a global mapping cache on some platforms
1666	* (darwin).
1667	*
1668	* @{ */
1669	/** @typedef PPGMPAGEMAPTLB
1670	* The page mapper TLB pointer type for the current context. */
1671	/** @typedef PPGMPAGEMAPTLB
1672	* The page mapper TLB entry pointer type for the current context. */
1673	/** @typedef PPGMPAGEMAPTLB
1674	* The page mapper TLB entry pointer pointer type for the current context. */
1675	/** @def PGM_PAGEMAPTLB_ENTRIES
1676	* The number of TLB entries in the page mapper TLB for the current context. */
1677	/** @def PGM_PAGEMAPTLB_IDX
1678	* Calculate the TLB index for a guest physical address.
1679	* @returns The TLB index.
1680	* @param GCPhys The guest physical address. */
1681	/** @typedef PPGMPAGEMAP
1682	* Pointer to a page mapper unit for current context. */
1683	/** @typedef PPPGMPAGEMAP
1684	* Pointer to a page mapper unit pointer for current context. */
1685	#if defined(IN_RING0)
1686	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1687	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1688	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1689	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1690	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1691	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1692	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1693	#else
1694	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1695	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1696	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1697	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1698	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1699	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1700	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1701	#endif
1702	/** @} */
1703
1704
1705	/** @name PGM Pool Indexes.
1706	* Aka. the unique shadow page identifier.
1707	* @{ */
1708	/** NIL page pool IDX. */
1709	#define NIL_PGMPOOL_IDX 0
1710	/** The first normal index. There used to be 5 fictive pages up front, now
1711	* there is only the NIL page. */
1712	#define PGMPOOL_IDX_FIRST 1
1713	/** The last valid index. (inclusive, 14 bits) */
1714	#define PGMPOOL_IDX_LAST 0x3fff
1715	/** @} */
1716
1717	/** The NIL index for the parent chain. */
1718	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1719	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1720
1721	/**
1722	* Node in the chain linking a shadowed page to it's parent (user).
1723	*/
1724	#pragma pack(1)
1725	typedef struct PGMPOOLUSER
1726	{
1727	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1728	uint16_t iNext;
1729	/** The user page index. */
1730	uint16_t iUser;
1731	/** Index into the user table. */
1732	uint32_t iUserTable;
1733	} PGMPOOLUSER, *PPGMPOOLUSER;
1734	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1735	#pragma pack()
1736
1737
1738	/** The NIL index for the phys ext chain. */
1739	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1740	/** The NIL pte index for a phys ext chain slot. */
1741	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1742
1743	/**
1744	* Node in the chain of physical cross reference extents.
1745	* @todo Calling this an 'extent' is not quite right, find a better name.
1746	* @todo find out the optimal size of the aidx array
1747	*/
1748	#pragma pack(1)
1749	typedef struct PGMPOOLPHYSEXT
1750	{
1751	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1752	uint16_t iNext;
1753	/** Alignment. */
1754	uint16_t u16Align;
1755	/** The user page index. */
1756	uint16_t aidx[3];
1757	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1758	uint16_t apte[3];
1759	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1760	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1761	#pragma pack()
1762
1763
1764	/**
1765	* The kind of page that's being shadowed.
1766	*/
1767	typedef enum PGMPOOLKIND
1768	{
1769	/** The virtual invalid 0 entry. */
1770	PGMPOOLKIND_INVALID = 0,
1771	/** The entry is free (=unused). */
1772	PGMPOOLKIND_FREE,
1773
1774	/** Shw: 32-bit page table; Gst: no paging. */
1775	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1776	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1777	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1778	/** Shw: 32-bit page table; Gst: 4MB page. */
1779	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1780	/** Shw: PAE page table; Gst: no paging. */
1781	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1782	/** Shw: PAE page table; Gst: 32-bit page table. */
1783	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1784	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1785	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1786	/** Shw: PAE page table; Gst: PAE page table. */
1787	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1788	/** Shw: PAE page table; Gst: 2MB page. */
1789	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1790
1791	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1792	PGMPOOLKIND_32BIT_PD,
1793	/** Shw: 32-bit page directory. Gst: no paging. */
1794	PGMPOOLKIND_32BIT_PD_PHYS,
1795	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1796	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1797	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1798	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1799	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1800	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1801	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1802	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1803	/** Shw: PAE page directory; Gst: PAE page directory. */
1804	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1805	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1806	PGMPOOLKIND_PAE_PD_PHYS,
1807
1808	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1809	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1810	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1811	PGMPOOLKIND_PAE_PDPT,
1812	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1813	PGMPOOLKIND_PAE_PDPT_PHYS,
1814
1815	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1816	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1817	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1818	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1819	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1820	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1821	/** Shw: 64-bit page directory table; Gst: no paging. */
1822	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1823
1824	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1825	PGMPOOLKIND_64BIT_PML4,
1826
1827	/** Shw: EPT page directory pointer table; Gst: no paging. */
1828	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1829	/** Shw: EPT page directory table; Gst: no paging. */
1830	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1831	/** Shw: EPT page table; Gst: no paging. */
1832	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1833
1834	/** Shw: Root Nested paging table. */
1835	PGMPOOLKIND_ROOT_NESTED,
1836
1837	/** The last valid entry. */
1838	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1839	} PGMPOOLKIND;
1840
1841	/**
1842	* The access attributes of the page; only applies to big pages.
1843	*/
1844	typedef enum
1845	{
1846	PGMPOOLACCESS_DONTCARE = 0,
1847	PGMPOOLACCESS_USER_RW,
1848	PGMPOOLACCESS_USER_R,
1849	PGMPOOLACCESS_USER_RW_NX,
1850	PGMPOOLACCESS_USER_R_NX,
1851	PGMPOOLACCESS_SUPERVISOR_RW,
1852	PGMPOOLACCESS_SUPERVISOR_R,
1853	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1854	PGMPOOLACCESS_SUPERVISOR_R_NX
1855	} PGMPOOLACCESS;
1856
1857	/**
1858	* The tracking data for a page in the pool.
1859	*/
1860	typedef struct PGMPOOLPAGE
1861	{
1862	/** AVL node code with the (HC) physical address of this page. */
1863	AVLOHCPHYSNODECORE Core;
1864	/** Pointer to the R3 mapping of the page. */
1865	R3PTRTYPE(void *) pvPageR3;
1866	/** Pointer to the R0 mapping of the page. */
1867	R0PTRTYPE(void *) pvPageR0;
1868	/** The guest physical address. */
1869	RTGCPHYS GCPhys;
1870	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1871	uint8_t enmKind;
1872	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1873	uint8_t enmAccess;
1874	/** This supplements enmKind and enmAccess */
1875	bool fA20Enabled : 1;
1876
1877	/** Used to indicate that the page is zeroed. */
1878	bool fZeroed : 1;
1879	/** Used to indicate that a PT has non-global entries. */
1880	bool fSeenNonGlobal : 1;
1881	/** Used to indicate that we're monitoring writes to the guest page. */
1882	bool fMonitored : 1;
1883	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1884	* (All pages are in the age list.) */
1885	bool fCached : 1;
1886	/** This is used by the R3 access handlers when invoked by an async thread.
1887	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1888	bool volatile fReusedFlushPending : 1;
1889	/** Used to mark the page as dirty (write monitoring is temporarily
1890	* off). */
1891	bool fDirty : 1;
1892	bool fPadding1 : 1;
1893	bool fPadding2;
1894
1895	/** The index of this page. */
1896	uint16_t idx;
1897	/** The next entry in the list this page currently resides in.
1898	* It's either in the free list or in the GCPhys hash. */
1899	uint16_t iNext;
1900	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1901	uint16_t iUserHead;
1902	/** The number of present entries. */
1903	uint16_t cPresent;
1904	/** The first entry in the table which is present. */
1905	uint16_t iFirstPresent;
1906	/** The number of modifications to the monitored page. */
1907	uint16_t cModifications;
1908	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1909	uint16_t iModifiedNext;
1910	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1911	uint16_t iModifiedPrev;
1912	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1913	uint16_t iMonitoredNext;
1914	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1915	uint16_t iMonitoredPrev;
1916	/** The next page in the age list. */
1917	uint16_t iAgeNext;
1918	/** The previous page in the age list. */
1919	uint16_t iAgePrev;
1920	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
1921	uint8_t idxDirtyEntry;
1922
1923	/** @name Access handler statistics to determine whether the guest is
1924	* (re)initializing a page table.
1925	* @{ */
1926	RTGCPTR GCPtrLastAccessHandlerRip;
1927	RTGCPTR GCPtrLastAccessHandlerFault;
1928	uint64_t cLastAccessHandler;
1929	/** @} */
1930	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
1931	uint32_t volatile cLocked;
1932	#if GC_ARCH_BITS == 64
1933	uint32_t u32Alignment3;
1934	#endif
1935	# ifdef VBOX_STRICT
1936	RTGCPTR GCPtrDirtyFault;
1937	# endif
1938	} PGMPOOLPAGE;
1939	/** Pointer to a pool page. */
1940	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
1941	/** Pointer to a const pool page. */
1942	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1943	/** Pointer to a pool page pointer. */
1944	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
1945
1946
1947	/** The hash table size. */
1948	# define PGMPOOL_HASH_SIZE 0x40
1949	/** The hash function. */
1950	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1951
1952
1953	/**
1954	* The shadow page pool instance data.
1955	*
1956	* It's all one big allocation made at init time, except for the
1957	* pages that is. The user nodes follows immediately after the
1958	* page structures.
1959	*/
1960	typedef struct PGMPOOL
1961	{
1962	/** The VM handle - R3 Ptr. */
1963	PVMR3 pVMR3;
1964	/** The VM handle - R0 Ptr. */
1965	R0PTRTYPE(PVMCC) pVMR0;
1966	/** The max pool size. This includes the special IDs. */
1967	uint16_t cMaxPages;
1968	/** The current pool size. */
1969	uint16_t cCurPages;
1970	/** The head of the free page list. */
1971	uint16_t iFreeHead;
1972	/* Padding. */
1973	uint16_t u16Padding;
1974	/** Head of the chain of free user nodes. */
1975	uint16_t iUserFreeHead;
1976	/** The number of user nodes we've allocated. */
1977	uint16_t cMaxUsers;
1978	/** The number of present page table entries in the entire pool. */
1979	uint32_t cPresent;
1980	/** Pointer to the array of user nodes - R3 pointer. */
1981	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1982	/** Pointer to the array of user nodes - R0 pointer. */
1983	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1984	/** Head of the chain of free phys ext nodes. */
1985	uint16_t iPhysExtFreeHead;
1986	/** The number of user nodes we've allocated. */
1987	uint16_t cMaxPhysExts;
1988	uint32_t u32Padding0b;
1989	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1990	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1991	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1992	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1993	/** Hash table for GCPhys addresses. */
1994	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1995	/** The head of the age list. */
1996	uint16_t iAgeHead;
1997	/** The tail of the age list. */
1998	uint16_t iAgeTail;
1999	/** Set if the cache is enabled. */
2000	bool fCacheEnabled;
2001	/** Alignment padding. */
2002	bool afPadding1[3];
2003	/** Head of the list of modified pages. */
2004	uint16_t iModifiedHead;
2005	/** The current number of modified pages. */
2006	uint16_t cModifiedPages;
2007	/** Physical access handler type registration handle. */
2008	PGMPHYSHANDLERTYPE hAccessHandlerType;
2009	/** Next available slot (in aDirtyPages). */
2010	uint32_t idxFreeDirtyPage;
2011	/** Number of active dirty pages. */
2012	uint32_t cDirtyPages;
2013	/** Array of current dirty pgm pool page indices. */
2014	uint16_t aidxDirtyPages[16];
2015	/** Array running in parallel to aidxDirtyPages with the page data. */
2016	struct
2017	{
2018	uint64_t aPage[512];
2019	} aDirtyPages[16];
2020
2021	/** The number of pages currently in use. */
2022	uint16_t cUsedPages;
2023	#ifdef VBOX_WITH_STATISTICS
2024	/** The high water mark for cUsedPages. */
2025	uint16_t cUsedPagesHigh;
2026	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2027	/** Profiling pgmPoolAlloc(). */
2028	STAMPROFILEADV StatAlloc;
2029	/** Profiling pgmR3PoolClearDoIt(). */
2030	STAMPROFILE StatClearAll;
2031	/** Profiling pgmR3PoolReset(). */
2032	STAMPROFILE StatR3Reset;
2033	/** Profiling pgmPoolFlushPage(). */
2034	STAMPROFILE StatFlushPage;
2035	/** Profiling pgmPoolFree(). */
2036	STAMPROFILE StatFree;
2037	/** Counting explicit flushes by PGMPoolFlushPage(). */
2038	STAMCOUNTER StatForceFlushPage;
2039	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2040	STAMCOUNTER StatForceFlushDirtyPage;
2041	/** Counting flushes for reused pages. */
2042	STAMCOUNTER StatForceFlushReused;
2043	/** Profiling time spent zeroing pages. */
2044	STAMPROFILE StatZeroPage;
2045	/** Profiling of pgmPoolTrackDeref. */
2046	STAMPROFILE StatTrackDeref;
2047	/** Profiling pgmTrackFlushGCPhysPT. */
2048	STAMPROFILE StatTrackFlushGCPhysPT;
2049	/** Profiling pgmTrackFlushGCPhysPTs. */
2050	STAMPROFILE StatTrackFlushGCPhysPTs;
2051	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2052	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2053	/** Number of times we've been out of user records. */
2054	STAMCOUNTER StatTrackFreeUpOneUser;
2055	/** Nr of flushed entries. */
2056	STAMCOUNTER StatTrackFlushEntry;
2057	/** Nr of updated entries. */
2058	STAMCOUNTER StatTrackFlushEntryKeep;
2059	/** Profiling deref activity related tracking GC physical pages. */
2060	STAMPROFILE StatTrackDerefGCPhys;
2061	/** Number of linear searches for a HCPhys in the ram ranges. */
2062	STAMCOUNTER StatTrackLinearRamSearches;
2063	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2064	STAMCOUNTER StamTrackPhysExtAllocFailures;
2065
2066	/** Profiling the RC/R0 \#PF access handler. */
2067	STAMPROFILE StatMonitorPfRZ;
2068	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2069	STAMPROFILE StatMonitorPfRZHandled;
2070	/** Times we've failed interpreting the instruction. */
2071	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2072	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2073	STAMPROFILE StatMonitorPfRZFlushPage;
2074	/** Times we've detected a page table reinit. */
2075	STAMCOUNTER StatMonitorPfRZFlushReinit;
2076	/** Counting flushes for pages that are modified too often. */
2077	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2078	/** Times we've detected fork(). */
2079	STAMCOUNTER StatMonitorPfRZFork;
2080	/** Times we've failed interpreting a patch code instruction. */
2081	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2082	/** Times we've failed interpreting a patch code instruction during flushing. */
2083	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2084	/** The number of times we've seen rep prefixes we can't handle. */
2085	STAMCOUNTER StatMonitorPfRZRepPrefix;
2086	/** Profiling the REP STOSD cases we've handled. */
2087	STAMPROFILE StatMonitorPfRZRepStosd;
2088
2089	/** Profiling the R0/RC regular access handler. */
2090	STAMPROFILE StatMonitorRZ;
2091	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2092	STAMPROFILE StatMonitorRZFlushPage;
2093	/** Per access size counts indexed by size minus 1, last for larger. */
2094	STAMCOUNTER aStatMonitorRZSizes[16+3];
2095	/** Missaligned access counts indexed by offset - 1. */
2096	STAMCOUNTER aStatMonitorRZMisaligned[7];
2097
2098	/** Nr of handled PT faults. */
2099	STAMCOUNTER StatMonitorRZFaultPT;
2100	/** Nr of handled PD faults. */
2101	STAMCOUNTER StatMonitorRZFaultPD;
2102	/** Nr of handled PDPT faults. */
2103	STAMCOUNTER StatMonitorRZFaultPDPT;
2104	/** Nr of handled PML4 faults. */
2105	STAMCOUNTER StatMonitorRZFaultPML4;
2106
2107	/** Profiling the R3 access handler. */
2108	STAMPROFILE StatMonitorR3;
2109	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2110	STAMPROFILE StatMonitorR3FlushPage;
2111	/** Per access size counts indexed by size minus 1, last for larger. */
2112	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2113	/** Missaligned access counts indexed by offset - 1. */
2114	STAMCOUNTER aStatMonitorR3Misaligned[7];
2115	/** Nr of handled PT faults. */
2116	STAMCOUNTER StatMonitorR3FaultPT;
2117	/** Nr of handled PD faults. */
2118	STAMCOUNTER StatMonitorR3FaultPD;
2119	/** Nr of handled PDPT faults. */
2120	STAMCOUNTER StatMonitorR3FaultPDPT;
2121	/** Nr of handled PML4 faults. */
2122	STAMCOUNTER StatMonitorR3FaultPML4;
2123
2124	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2125	STAMCOUNTER StatResetDirtyPages;
2126	/** Times we've called pgmPoolAddDirtyPage. */
2127	STAMCOUNTER StatDirtyPage;
2128	/** Times we've had to flush duplicates for dirty page management. */
2129	STAMCOUNTER StatDirtyPageDupFlush;
2130	/** Times we've had to flush because of overflow. */
2131	STAMCOUNTER StatDirtyPageOverFlowFlush;
2132
2133	/** The high water mark for cModifiedPages. */
2134	uint16_t cModifiedPagesHigh;
2135	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2136
2137	/** The number of cache hits. */
2138	STAMCOUNTER StatCacheHits;
2139	/** The number of cache misses. */
2140	STAMCOUNTER StatCacheMisses;
2141	/** The number of times we've got a conflict of 'kind' in the cache. */
2142	STAMCOUNTER StatCacheKindMismatches;
2143	/** Number of times we've been out of pages. */
2144	STAMCOUNTER StatCacheFreeUpOne;
2145	/** The number of cacheable allocations. */
2146	STAMCOUNTER StatCacheCacheable;
2147	/** The number of uncacheable allocations. */
2148	STAMCOUNTER StatCacheUncacheable;
2149	#else
2150	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2151	#endif
2152	/** Profiling PGMR0PoolGrow(). */
2153	STAMPROFILE StatGrow;
2154	/** The AVL tree for looking up a page by its HC physical address. */
2155	AVLOHCPHYSTREE HCPhysTree;
2156	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2157	/** Array of pages. (cMaxPages in length)
2158	* The Id is the index into thist array.
2159	*/
2160	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2161	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2162	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2163	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2164	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2165	#ifdef VBOX_WITH_STATISTICS
2166	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2167	#endif
2168	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2169
2170
2171	/** @def PGMPOOL_PAGE_2_PTR
2172	* Maps a pool page pool into the current context.
2173	*
2174	* @returns VBox status code.
2175	* @param a_pVM Pointer to the VM.
2176	* @param a_pPage The pool page.
2177	*
2178	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2179	* small page window employeed by that function. Be careful.
2180	* @remark There is no need to assert on the result.
2181	*/
2182	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2183	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2184	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2185	{
2186	RT_NOREF(pszCaller);
2187	AssertPtr(a_pPage);
2188	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2189	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2190	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2191	return a_pPage->CTX_SUFF(pvPage);
2192	}
2193	#else
2194	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2195	#endif
2196
2197
2198	/** @def PGMPOOL_PAGE_2_PTR_V2
2199	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2200	*
2201	* @returns VBox status code.
2202	* @param a_pVM Pointer to the VM.
2203	* @param a_pVCpu The current CPU.
2204	* @param a_pPage The pool page.
2205	*
2206	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2207	* small page window employeed by that function. Be careful.
2208	* @remark There is no need to assert on the result.
2209	*/
2210	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2211
2212
2213	/** @name Per guest page tracking data.
2214	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2215	* is to use more bits for it and split it up later on. But for now we'll play
2216	* safe and change as little as possible.
2217	*
2218	* The 16-bit word has two parts:
2219	*
2220	* The first 14-bit forms the @a idx field. It is either the index of a page in
2221	* the shadow page pool, or and index into the extent list.
2222	*
2223	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2224	* shadow page pool references to the page. If cRefs equals
2225	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2226	* (misnomer) table and not the shadow page pool.
2227	*
2228	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2229	* the 16-bit word.
2230	*
2231	* @{ */
2232	/** The shift count for getting to the cRefs part. */
2233	#define PGMPOOL_TD_CREFS_SHIFT 14
2234	/** The mask applied after shifting the tracking data down by
2235	* PGMPOOL_TD_CREFS_SHIFT. */
2236	#define PGMPOOL_TD_CREFS_MASK 0x3
2237	/** The cRefs value used to indicate that the idx is the head of a
2238	* physical cross reference list. */
2239	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2240	/** The shift used to get idx. */
2241	#define PGMPOOL_TD_IDX_SHIFT 0
2242	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2243	#define PGMPOOL_TD_IDX_MASK 0x3fff
2244	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2245	* simply too many mappings of this page. */
2246	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2247
2248	/** @def PGMPOOL_TD_MAKE
2249	* Makes a 16-bit tracking data word.
2250	*
2251	* @returns tracking data.
2252	* @param cRefs The @a cRefs field. Must be within bounds!
2253	* @param idx The @a idx field. Must also be within bounds! */
2254	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2255
2256	/** @def PGMPOOL_TD_GET_CREFS
2257	* Get the @a cRefs field from a tracking data word.
2258	*
2259	* @returns The @a cRefs field
2260	* @param u16 The tracking data word.
2261	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2262	* non-zero @a u16. */
2263	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2264
2265	/** @def PGMPOOL_TD_GET_IDX
2266	* Get the @a idx field from a tracking data word.
2267	*
2268	* @returns The @a idx field
2269	* @param u16 The tracking data word. */
2270	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2271	/** @} */
2272
2273
2274
2275	/** @name A20 gate macros
2276	* @{ */
2277	#define PGM_WITH_A20
2278	#ifdef PGM_WITH_A20
2279	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2280	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2281	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2282	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2283	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2284	#else
2285	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2286	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2287	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2288	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2289	#endif
2290	/** @} */
2291
2292
2293	/**
2294	* Roots and anchors for trees and list employing self relative offsets as
2295	* pointers.
2296	*
2297	* When using self-relative offsets instead of pointers, the offsets needs to be
2298	* the same in all offsets. Thus the roots and anchors needs to live on the
2299	* hyper heap just like the nodes.
2300	*/
2301	typedef struct PGMTREES
2302	{
2303	/** List of physical access handler types (offset pointers) of type
2304	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2305	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2306	/** Physical access handlers (AVL range+offsetptr tree). */
2307	AVLROGCPHYSTREE PhysHandlers;
2308	} PGMTREES;
2309	/** Pointer to PGM trees. */
2310	typedef PGMTREES *PPGMTREES;
2311
2312
2313	/**
2314	* Page fault guest state for the AMD64 paging mode.
2315	*/
2316	typedef struct PGMPTWALKCORE
2317	{
2318	/** The guest virtual address that is being resolved by the walk
2319	* (input). */
2320	RTGCPTR GCPtr;
2321
2322	/** The guest physical address that is the result of the walk.
2323	* @remarks only valid if fSucceeded is set. */
2324	RTGCPHYS GCPhys;
2325
2326	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2327	bool fSucceeded;
2328	/** The level problem arrised at.
2329	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2330	* level 8. This is 0 on success. */
2331	uint8_t uLevel;
2332	/** Set if the page isn't present. */
2333	bool fNotPresent;
2334	/** Encountered a bad physical address. */
2335	bool fBadPhysAddr;
2336	/** Set if there was reserved bit violations. */
2337	bool fRsvdError;
2338	/** Set if it involves a big page (2/4 MB). */
2339	bool fBigPage;
2340	/** Set if it involves a gigantic page (1 GB). */
2341	bool fGigantPage;
2342	/** The effective X86_PTE_US flag for the address. */
2343	bool fEffectiveUS;
2344	/** The effective X86_PTE_RW flag for the address. */
2345	bool fEffectiveRW;
2346	/** The effective X86_PTE_NX flag for the address. */
2347	bool fEffectiveNX;
2348	bool afPadding1[2];
2349	/** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2350	* The NX bit is inverted and shifted down 63 places to bit 0. */
2351	uint32_t fEffective;
2352	} PGMPTWALKCORE;
2353
2354	/** @name PGMPTWALKCORE::fEffective bits.
2355	* @{ */
2356	#if 0
2357	/** Effective execute bit (!NX). */
2358	#define PGMPTWALK_EFF_X RT_BIT_32(0)
2359	/** Effective read+write access bit. */
2360	#define PGMPTWALK_EFF_RW X86_PTE_RW
2361	/** Effective user-mode access bit. */
2362	#define PGMPTWALK_EFF_US X86_PTE_US
2363	/** Effective write through cache bit. */
2364	#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2365	/** Effective cache disabled bit. */
2366	#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2367	/** Effective accessed bit. */
2368	#define PGMPTWALK_EFF_A X86_PTE_A
2369	/** The dirty bit of the final entry. */
2370	#define PGMPTWALK_EFF_D X86_PTE_D
2371	/** The PAT bit of the final entry. */
2372	#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2373	/** The global bit of the final entry. */
2374	#define PGMPTWALK_EFF_G X86_PTE_G
2375	#endif
2376	/** Effective execute bit (!NX). */
2377	#define PGM_BF_PTWALK_EFF_X_SHIFT 0
2378	#define PGM_BF_PTWALK_EFF_X_MASK UINT32_C(0x00000001)
2379	/** Effective read+write access bit. */
2380	#define PGM_BF_PTWALK_EFF_RW_SHIFT 1
2381	#define PGM_BF_PTWALK_EFF_RW_MASK UINT32_C(0x00000002)
2382	/** Effective user-mode access bit. */
2383	#define PGM_BF_PTWALK_EFF_US_SHIFT 2
2384	#define PGM_BF_PTWALK_EFF_US_MASK UINT32_C(0x00000004)
2385	/** Effective write through cache bit. */
2386	#define PGM_BF_PTWALK_EFF_PWT_SHIFT 3
2387	#define PGM_BF_PTWALK_EFF_PWT_MASK UINT32_C(0x00000008)
2388	/** Effective cache disabled bit. */
2389	#define PGM_BF_PTWALK_EFF_PCD_SHIFT 4
2390	#define PGM_BF_PTWALK_EFF_PCD_MASK UINT32_C(0x00000010)
2391	/** Effective accessed bit. */
2392	#define PGM_BF_PTWALK_EFF_A_SHIFT 5
2393	#define PGM_BF_PTWALK_EFF_A_MASK UINT32_C(0x00000020)
2394	/** The dirty bit of the final entry. */
2395	#define PGM_BF_PTWALK_EFF_D_SHIFT 6
2396	#define PGM_BF_PTWALK_EFF_D_MASK UINT32_C(0x00000040)
2397	/** The PAT bit of the final entry. */
2398	#define PGM_BF_PTWALK_EFF_PAT_SHIFT 7
2399	#define PGM_BF_PTWALK_EFF_PAT_MASK UINT32_C(0x00000080)
2400	/** The global bit of the final entry. */
2401	#define PGM_BF_PTWALK_EFF_G_SHIFT 8
2402	#define PGM_BF_PTWALK_EFF_G_MASK UINT32_C(0x00000100)
2403	/** Reserved (bits 11:9) unused. */
2404	#define PGM_BF_PTWALK_EFF_RSVD_11_9_SHIFT 9
2405	#define PGM_BF_PTWALK_EFF_RSVD_11_9_MASK UINT32_C(0x00000e00)
2406	/** Effective read access bit - EPT only. */
2407	#define PGM_BF_PTWALK_EFF_R_SHIFT 12
2408	#define PGM_BF_PTWALK_EFF_R_MASK UINT32_C(0x00001000)
2409	/** Effective write access bit - EPT only. */
2410	#define PGM_BF_PTWALK_EFF_W_SHIFT 13
2411	#define PGM_BF_PTWALK_EFF_W_MASK UINT32_C(0x00002000)
2412	/** Effective execute access for supervisor-mode - EPT only. */
2413	#define PGM_BF_PTWALK_EFF_X_SUPER_SHIFT 14
2414	#define PGM_BF_PTWALK_EFF_X_SUPER_MASK UINT32_C(0x00004000)
2415	/** Reserved (bits 21:15) unused. */
2416	#define PGM_BF_PTWALK_EFF_RSVD_21_15_SHIFT 15
2417	#define PGM_BF_PTWALK_EFF_RSVD_21_15_MASK UINT32_C(0x003f8000)
2418	/** Effective execute access for user-mode - EPT only. */
2419	#define PGM_BF_PTWALK_EFF_X_USER_SHIFT 22
2420	#define PGM_BF_PTWALK_EFF_X_USER_MASK UINT32_C(0x00400000)
2421	/** Reserved (bits 31:23). */
2422	#define PGM_BF_PTWALK_EFF_RSVD_31_23_SHIFT 23
2423	#define PGM_BF_PTWALK_EFF_RSVD_31_23_MASK UINT32_C(0xff800000)
2424	RT_BF_ASSERT_COMPILE_CHECKS(PGM_BF_PTWALK_EFF_, UINT32_C(0), UINT32_MAX,
2425	(X, RW, US, PWT, PCD, A, D, PAT, G, RSVD_11_9, R, W, X_SUPER, RSVD_21_15, X_USER, RSVD_31_23));
2426	AssertCompile(PGM_BF_PTWALK_EFF_RW_SHIFT == X86_PTE_BIT_RW);
2427	AssertCompile(PGM_BF_PTWALK_EFF_US_SHIFT == X86_PTE_BIT_US);
2428	AssertCompile(PGM_BF_PTWALK_EFF_PWT_SHIFT == X86_PTE_BIT_PWT);
2429	AssertCompile(PGM_BF_PTWALK_EFF_PCD_SHIFT == X86_PTE_BIT_PCD);
2430	AssertCompile(PGM_BF_PTWALK_EFF_A_SHIFT == X86_PTE_BIT_A);
2431	AssertCompile(PGM_BF_PTWALK_EFF_D_SHIFT == X86_PTE_BIT_D);
2432	AssertCompile(PGM_BF_PTWALK_EFF_PAT_SHIFT == X86_PTE_BIT_PAT);
2433	AssertCompile(PGM_BF_PTWALK_EFF_G_SHIFT == X86_PTE_BIT_G);
2434	AssertCompile(PGM_BF_PTWALK_EFF_RW_MASK == X86_PTE_RW);
2435	AssertCompile(PGM_BF_PTWALK_EFF_US_MASK == X86_PTE_US);
2436	AssertCompile(PGM_BF_PTWALK_EFF_PWT_MASK == X86_PTE_PWT);
2437	AssertCompile(PGM_BF_PTWALK_EFF_PCD_MASK == X86_PTE_PCD);
2438	AssertCompile(PGM_BF_PTWALK_EFF_A_MASK == X86_PTE_A);
2439	AssertCompile(PGM_BF_PTWALK_EFF_D_MASK == X86_PTE_D);
2440	AssertCompile(PGM_BF_PTWALK_EFF_PAT_MASK == X86_PTE_PAT);
2441	AssertCompile(PGM_BF_PTWALK_EFF_G_MASK == X86_PTE_G);
2442	/** @} */
2443
2444
2445	/**
2446	* Guest page table walk for the AMD64 mode.
2447	*/
2448	typedef struct PGMPTWALKGSTAMD64
2449	{
2450	/** The common core. */
2451	PGMPTWALKCORE Core;
2452
2453	PX86PML4 pPml4;
2454	PX86PML4E pPml4e;
2455	X86PML4E Pml4e;
2456
2457	PX86PDPT pPdpt;
2458	PX86PDPE pPdpe;
2459	X86PDPE Pdpe;
2460
2461	PX86PDPAE pPd;
2462	PX86PDEPAE pPde;
2463	X86PDEPAE Pde;
2464
2465	PX86PTPAE pPt;
2466	PX86PTEPAE pPte;
2467	X86PTEPAE Pte;
2468	} PGMPTWALKGSTAMD64;
2469	/** Pointer to a AMD64 guest page table walk. */
2470	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2471	/** Pointer to a const AMD64 guest page table walk. */
2472	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2473
2474	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2475	/**
2476	* Guest page table walk for the EPT mode.
2477	*/
2478	typedef struct PGMPTWALKGSTEPT
2479	{
2480	/** The common core. */
2481	PGMPTWALKCORE Core;
2482
2483	PEPTPML4 pPml4;
2484	PEPTPML4E pPml4e;
2485	EPTPML4E Pml4e;
2486
2487	PEPTPDPT pPdpt;
2488	PEPTPDPTE pPdpte;
2489	EPTPDPTE Pdpte;
2490
2491	PEPTPD pPd;
2492	PEPTPDE pPde;
2493	EPTPDE Pde;
2494
2495	PEPTPT pPt;
2496	PEPTPTE pPte;
2497	EPTPTE Pte;
2498	} PGMPTWALKGSTEPT;
2499	/** Pointer to an EPT guest page table walk. */
2500	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2501	/** Pointer to a const EPT guest page table walk. */
2502	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2503	#endif
2504
2505	/**
2506	* Guest page table walk for the PAE mode.
2507	*/
2508	typedef struct PGMPTWALKGSTPAE
2509	{
2510	/** The common core. */
2511	PGMPTWALKCORE Core;
2512
2513	PX86PDPT pPdpt;
2514	PX86PDPE pPdpe;
2515	X86PDPE Pdpe;
2516
2517	PX86PDPAE pPd;
2518	PX86PDEPAE pPde;
2519	X86PDEPAE Pde;
2520
2521	PX86PTPAE pPt;
2522	PX86PTEPAE pPte;
2523	X86PTEPAE Pte;
2524	} PGMPTWALKGSTPAE;
2525	/** Pointer to a PAE guest page table walk. */
2526	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2527	/** Pointer to a const AMD64 guest page table walk. */
2528	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2529
2530	/**
2531	* Guest page table walk for the 32-bit mode.
2532	*/
2533	typedef struct PGMPTWALKGST32BIT
2534	{
2535	/** The common core. */
2536	PGMPTWALKCORE Core;
2537
2538	PX86PD pPd;
2539	PX86PDE pPde;
2540	X86PDE Pde;
2541
2542	PX86PT pPt;
2543	PX86PTE pPte;
2544	X86PTE Pte;
2545	} PGMPTWALKGST32BIT;
2546	/** Pointer to a 32-bit guest page table walk. */
2547	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2548	/** Pointer to a const 32-bit guest page table walk. */
2549	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2550
2551	/**
2552	* Which part of PGMPTWALKGST that is valid.
2553	*/
2554	typedef enum PGMPTWALKGSTTYPE
2555	{
2556	/** Customary invalid 0 value. */
2557	PGMPTWALKGSTTYPE_INVALID = 0,
2558	/** PGMPTWALKGST::u.Amd64 is valid. */
2559	PGMPTWALKGSTTYPE_AMD64,
2560	/** PGMPTWALKGST::u.Pae is valid. */
2561	PGMPTWALKGSTTYPE_PAE,
2562	/** PGMPTWALKGST::u.Legacy is valid. */
2563	PGMPTWALKGSTTYPE_32BIT,
2564	/** PGMPTWALKGST::u.Ept is valid. */
2565	PGMPTWALKGSTTYPE_EPT,
2566	/** Customary 32-bit type hack. */
2567	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2568	} PGMPTWALKGSTTYPE;
2569
2570	/**
2571	* Combined guest page table walk result.
2572	*/
2573	typedef struct PGMPTWALKGST
2574	{
2575	union
2576	{
2577	/** The page walker core - always valid. */
2578	PGMPTWALKCORE Core;
2579	/** The page walker for AMD64. */
2580	PGMPTWALKGSTAMD64 Amd64;
2581	/** The page walker for PAE (32-bit). */
2582	PGMPTWALKGSTPAE Pae;
2583	/** The page walker for 32-bit paging (called legacy due to C naming
2584	* convension). */
2585	PGMPTWALKGST32BIT Legacy;
2586	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2587	/** The page walker for EPT. */
2588	PGMPTWALKGSTEPT Ept;
2589	#endif
2590	} u;
2591	/** Indicates which part of the union is valid. */
2592	PGMPTWALKGSTTYPE enmType;
2593	} PGMPTWALKGST;
2594	/** Pointer to a combined guest page table walk result. */
2595	typedef PGMPTWALKGST *PPGMPTWALKGST;
2596	/** Pointer to a read-only combined guest page table walk result. */
2597	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2598
2599
2600	/** @name Paging mode macros
2601	* @{
2602	*/
2603	#ifdef IN_RING3
2604	# define PGM_CTX(a,b) a##R3##b
2605	# define PGM_CTX_STR(a,b) a "R3" b
2606	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2607	#elif defined(IN_RING0)
2608	# define PGM_CTX(a,b) a##R0##b
2609	# define PGM_CTX_STR(a,b) a "R0" b
2610	# define PGM_CTX_DECL(type) VMMDECL(type)
2611	#else
2612	# error "Not IN_RING3 or IN_RING0!"
2613	#endif
2614
2615	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2616	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2617	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2618	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2619	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2620	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2621	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2622	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2623	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2624	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2625	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2626	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2627	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2628	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2629	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2630	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2631	# define PGM_GST_NAME_EPT(name) PGM_CTX(pgm,GstEPT##name)
2632	# define PGM_GST_NAME_RC_EPT_STR(name) "pgmRCGstEPT" #name
2633	# define PGM_GST_NAME_R0_EPT_STR(name) "pgmR0GstEPT" #name
2634	#endif
2635	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2636
2637	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2638	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2639	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2640	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2641	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2642	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2643	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2644	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2645	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2646	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2647	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2648	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2649	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2650	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2651	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2652	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2653	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2654	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2655	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2656	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2657	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2658	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2659	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2660	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2661	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2662
2663	/* Shw_Gst */
2664	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2665	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2666	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2667	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2668	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2669	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2670	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2671	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2672	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2673	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2674	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2675	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2676	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2677	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2678	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2679	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2680	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2681	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2682	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2683	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2684	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2685	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2686	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2687	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2688	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2689	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2690	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2691	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2692	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2693	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2694	# define PGM_BTH_NAME_EPT_EPT(name) PGM_CTX(pgm,BthEPTEPT##name)
2695	#endif
2696	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2697	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2698	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2699	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2700	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2701
2702	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2703	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2704	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2705	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2706	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2707	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2708	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2709	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2710	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2711	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2712	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2713	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2714	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2715	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2716	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2717	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2718	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2719	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2720	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2721	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2722	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2723	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2724	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2725	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2726	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2727	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2728	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2729	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2730	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2731	# define PGM_BTH_NAME_RC_EPT_EPT_STR(name) "pgmRCBthEPTEPT" #name
2732	#endif
2733
2734	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2735	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2736	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2737	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2738	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2739	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2740	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2741	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2742	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2743	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2744	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2745	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2746	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2747	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2748	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2749	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2750	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2751	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2752	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2753	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2754	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2755	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2756	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2757	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2758	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2759	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2760	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2761	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2762	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2763	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2764	# define PGM_BTH_NAME_R0_EPT_EPT_STR(name) "pgmR0BthEPTEPT" #name
2765	#endif
2766
2767	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2768	/** @} */
2769
2770
2771	/**
2772	* Function pointers for guest paging.
2773	*/
2774	typedef struct PGMMODEDATAGST
2775	{
2776	/** The guest mode type. */
2777	uint32_t uType;
2778	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2779	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2780	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2781	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2782	#ifdef IN_RING3
2783	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2784	#endif
2785	} PGMMODEDATAGST;
2786
2787	/** The length of g_aPgmGuestModeData. */
2788	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2789	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_EPT + 1)
2790	#elif defined(VBOX_WITH_64_BITS_GUESTS)
2791	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2792	#else
2793	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2794	#endif
2795	/** The guest mode data array. */
2796	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2797
2798
2799	/**
2800	* Function pointers for shadow paging.
2801	*/
2802	typedef struct PGMMODEDATASHW
2803	{
2804	/** The shadow mode type. */
2805	uint32_t uType;
2806	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2807	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2808	uint64_t fMask, uint32_t fOpFlags));
2809	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2810	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2811	#ifdef IN_RING3
2812	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2813	#endif
2814	} PGMMODEDATASHW;
2815
2816	/** The length of g_aPgmShadowModeData. */
2817	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2818	/** The shadow mode data array. */
2819	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2820
2821
2822	/**
2823	* Function pointers for guest+shadow paging.
2824	*/
2825	typedef struct PGMMODEDATABTH
2826	{
2827	/** The shadow mode type. */
2828	uint32_t uShwType;
2829	/** The guest mode type. */
2830	uint32_t uGstType;
2831
2832	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2833	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2834	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2835	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2836	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3, bool fPdpesMapped));
2837	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2838	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2839	#ifndef IN_RING3
2840	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2841	#endif
2842	#ifdef VBOX_STRICT
2843	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2844	#endif
2845	} PGMMODEDATABTH;
2846
2847	/** The length of g_aPgmBothModeData. */
2848	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2849	/** The guest+shadow mode data array. */
2850	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2851
2852
2853	#ifdef VBOX_WITH_STATISTICS
2854	/**
2855	* PGM statistics.
2856	*/
2857	typedef struct PGMSTATS
2858	{
2859	/* R3 only: */
2860	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2861	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2862
2863	/* R3+RZ */
2864	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2865	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2866	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2867	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2868	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2869	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2870	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2871	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2872	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2873	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2874	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2875	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2876	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2877	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2878	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2879	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2880	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2881	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2882	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2883	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2884	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2885	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2886	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2887	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2888	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2889	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2890
2891	/* RC only: */
2892	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2893	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2894
2895	STAMCOUNTER StatRZPhysRead;
2896	STAMCOUNTER StatRZPhysReadBytes;
2897	STAMCOUNTER StatRZPhysWrite;
2898	STAMCOUNTER StatRZPhysWriteBytes;
2899	STAMCOUNTER StatR3PhysRead;
2900	STAMCOUNTER StatR3PhysReadBytes;
2901	STAMCOUNTER StatR3PhysWrite;
2902	STAMCOUNTER StatR3PhysWriteBytes;
2903	STAMCOUNTER StatRCPhysRead;
2904	STAMCOUNTER StatRCPhysReadBytes;
2905	STAMCOUNTER StatRCPhysWrite;
2906	STAMCOUNTER StatRCPhysWriteBytes;
2907
2908	STAMCOUNTER StatRZPhysSimpleRead;
2909	STAMCOUNTER StatRZPhysSimpleReadBytes;
2910	STAMCOUNTER StatRZPhysSimpleWrite;
2911	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2912	STAMCOUNTER StatR3PhysSimpleRead;
2913	STAMCOUNTER StatR3PhysSimpleReadBytes;
2914	STAMCOUNTER StatR3PhysSimpleWrite;
2915	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2916	STAMCOUNTER StatRCPhysSimpleRead;
2917	STAMCOUNTER StatRCPhysSimpleReadBytes;
2918	STAMCOUNTER StatRCPhysSimpleWrite;
2919	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2920
2921	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2922	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2923	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2924	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2925	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2926	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2927	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2928
2929	/** Time spent by the host OS for large page allocation. */
2930	STAMPROFILE StatAllocLargePage;
2931	/** Time spent clearing the newly allocated large pages. */
2932	STAMPROFILE StatClearLargePage;
2933	/** The number of times allocating a large pages takes more than the allowed period. */
2934	STAMCOUNTER StatLargePageOverflow;
2935	/** pgmPhysIsValidLargePage profiling - R3 */
2936	STAMPROFILE StatR3IsValidLargePage;
2937	/** pgmPhysIsValidLargePage profiling - RZ*/
2938	STAMPROFILE StatRZIsValidLargePage;
2939
2940	STAMPROFILE StatChunkAging;
2941	STAMPROFILE StatChunkFindCandidate;
2942	STAMPROFILE StatChunkUnmap;
2943	STAMPROFILE StatChunkMap;
2944	} PGMSTATS;
2945	#endif /* VBOX_WITH_STATISTICS */
2946
2947
2948	/**
2949	* PGM Data (part of VM)
2950	*/
2951	typedef struct PGM
2952	{
2953	/** @cfgm{/RamPreAlloc, boolean, false}
2954	* Indicates whether the base RAM should all be allocated before starting
2955	* the VM (default), or if it should be allocated when first written to.
2956	*/
2957	bool fRamPreAlloc;
2958	#ifdef VBOX_WITH_PGM_NEM_MODE
2959	/** Set if we're operating in NEM memory mode.
2960	*
2961	* NEM mode implies that memory is allocated in big chunks for each RAM range
2962	* rather than on demand page by page. Memory is also not locked and PGM has
2963	* therefore no physical addresses for them. Page sharing is out of the
2964	* question. Ballooning depends on the native execution engine, but probably
2965	* pointless as well. */
2966	bool fNemMode;
2967	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2968	#else
2969	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2970	#endif
2971	/** Indicates whether write monitoring is currently in use.
2972	* This is used to prevent conflicts between live saving and page sharing
2973	* detection. */
2974	bool fPhysWriteMonitoringEngaged;
2975	/** Set if the CPU has less than 52-bit physical address width.
2976	* This is used */
2977	bool fLessThan52PhysicalAddressBits;
2978	/** Set when nested paging is active.
2979	* This is meant to save calls to HMIsNestedPagingActive and let the
2980	* compilers optimize the code better. Whether we use nested paging or
2981	* not is something we find out during VMM initialization and we won't
2982	* change this later on. */
2983	bool fNestedPaging;
2984	/** We're not in a state which permits writes to guest memory.
2985	* (Only used in strict builds.) */
2986	bool fNoMorePhysWrites;
2987	/** @cfgm{/PageFusionAllowed, boolean, false}
2988	* Whether page fusion is allowed. */
2989	bool fPageFusionAllowed;
2990	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2991	* Whether PCI passthrough is enabled. */
2992	bool fPciPassthrough;
2993	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2994	uint8_t cMmio2Regions;
2995	/** Restore original ROM page content when resetting after loading state.
2996	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2997	* enables the VM to start using an updated ROM without requiring powering
2998	* down the VM, just rebooting or resetting it. */
2999	bool fRestoreRomPagesOnReset;
3000	/** Whether to automatically clear all RAM pages on reset. */
3001	bool fZeroRamPagesOnReset;
3002	/** Large page enabled flag. */
3003	bool fUseLargePages;
3004	/** Alignment padding. */
3005	#ifndef VBOX_WITH_PGM_NEM_MODE
3006	bool afAlignment3[1];
3007	#endif
3008	/** The host paging mode. (This is what SUPLib reports.) */
3009	SUPPAGINGMODE enmHostMode;
3010	bool afAlignment3b[2];
3011
3012	/** Generation ID for the RAM ranges. This member is incremented everytime
3013	* a RAM range is linked or unlinked. */
3014	uint32_t volatile idRamRangesGen;
3015
3016	/** Physical access handler type for ROM protection. */
3017	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3018	/** Alignment padding. */
3019	uint32_t u32Padding;
3020
3021	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3022	RTGCPHYS GCPhys4MBPSEMask;
3023	/** Mask containing the invalid bits of a guest physical address.
3024	* @remarks this does not stop at bit 52. */
3025	RTGCPHYS GCPhysInvAddrMask;
3026
3027
3028	/** RAM range TLB for R3. */
3029	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3030	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3031	* This is sorted by physical address and contains no overlapping ranges. */
3032	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3033	/** Root of the RAM range search tree for ring-3. */
3034	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3035	/** PGM offset based trees - R3 Ptr. */
3036	R3PTRTYPE(PPGMTREES) pTreesR3;
3037	/** Caching the last physical handler we looked up in R3. */
3038	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3039	/** Shadow Page Pool - R3 Ptr. */
3040	R3PTRTYPE(PPGMPOOL) pPoolR3;
3041	/** Pointer to the list of ROM ranges - for R3.
3042	* This is sorted by physical address and contains no overlapping ranges. */
3043	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3044	/** Pointer to the list of MMIO2 ranges - for R3.
3045	* Registration order. */
3046	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3047	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3048	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3049
3050	/** RAM range TLB for R0. */
3051	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3052	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3053	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3054	/** Root of the RAM range search tree for ring-0. */
3055	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3056	/** PGM offset based trees - R0 Ptr. */
3057	R0PTRTYPE(PPGMTREES) pTreesR0;
3058	/** Caching the last physical handler we looked up in R0. */
3059	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3060	/** Shadow Page Pool - R0 Ptr. */
3061	R0PTRTYPE(PPGMPOOL) pPoolR0;
3062	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3063	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3064	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3065	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3066
3067	/** Hack: Number of deprecated page mapping locks taken by the current lock
3068	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3069	uint32_t cDeprecatedPageLocks;
3070	/** Alignment padding. */
3071	uint32_t au32Alignment2[1];
3072
3073	/** PGM critical section.
3074	* This protects the physical, ram ranges, and the page flag updating (some of
3075	* it anyway).
3076	*/
3077	PDMCRITSECT CritSectX;
3078
3079	/**
3080	* Data associated with managing the ring-3 mappings of the allocation chunks.
3081	*/
3082	struct
3083	{
3084	/** The chunk mapping TLB. */
3085	PGMCHUNKR3MAPTLB Tlb;
3086	/** The chunk tree, ordered by chunk id. */
3087	R3PTRTYPE(PAVLU32NODECORE) pTree;
3088	#if HC_ARCH_BITS == 32
3089	uint32_t u32Alignment0;
3090	#endif
3091	/** The number of mapped chunks. */
3092	uint32_t c;
3093	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3094	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3095	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3096	uint32_t cMax;
3097	/** The current time. This is incremented whenever a chunk is inserted. */
3098	uint32_t iNow;
3099	/** Alignment padding. */
3100	uint32_t au32Alignment1[3];
3101	} ChunkR3Map;
3102
3103	/** The page mapping TLB for ring-3. */
3104	PGMPAGER3MAPTLB PhysTlbR3;
3105	/** The page mapping TLB for ring-0. */
3106	PGMPAGER0MAPTLB PhysTlbR0;
3107
3108	/** @name The zero page.
3109	* @{ */
3110	/** The host physical address of the zero page. */
3111	RTHCPHYS HCPhysZeroPg;
3112	/** The ring-3 mapping of the zero page. */
3113	RTR3PTR pvZeroPgR3;
3114	/** The ring-0 mapping of the zero page. */
3115	RTR0PTR pvZeroPgR0;
3116	/** The GC mapping of the zero page. */
3117	RTRCPTR pvZeroPgRC;
3118	RTRCPTR RCPtrAlignment3;
3119	/** @}*/
3120
3121	/** @name The Invalid MMIO page.
3122	* This page is filled with 0xfeedface.
3123	* @{ */
3124	/** The host physical address of the invalid MMIO page. */
3125	RTHCPHYS HCPhysMmioPg;
3126	/** The host pysical address of the invalid MMIO page plus all invalid
3127	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3128	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3129	RTHCPHYS HCPhysInvMmioPg;
3130	/** The ring-3 mapping of the invalid MMIO page. */
3131	RTR3PTR pvMmioPgR3;
3132	#if HC_ARCH_BITS == 32
3133	RTR3PTR R3PtrAlignment4;
3134	#endif
3135	/** @} */
3136
3137
3138	/** The number of handy pages. */
3139	uint32_t cHandyPages;
3140
3141	/** The number of large handy pages. */
3142	uint32_t cLargeHandyPages;
3143
3144	/**
3145	* Array of handy pages.
3146	*
3147	* This array is used in a two way communication between pgmPhysAllocPage
3148	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3149	* an intermediary.
3150	*
3151	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3152	* (The current size of 32 pages, means 128 KB of handy memory.)
3153	*/
3154	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3155
3156	/**
3157	* Array of large handy pages. (currently size 1)
3158	*
3159	* This array is used in a two way communication between pgmPhysAllocLargePage
3160	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3161	* an intermediary.
3162	*/
3163	GMMPAGEDESC aLargeHandyPage[1];
3164
3165	/**
3166	* Live save data.
3167	*/
3168	struct
3169	{
3170	/** Per type statistics. */
3171	struct
3172	{
3173	/** The number of ready pages. */
3174	uint32_t cReadyPages;
3175	/** The number of dirty pages. */
3176	uint32_t cDirtyPages;
3177	/** The number of ready zero pages. */
3178	uint32_t cZeroPages;
3179	/** The number of write monitored pages. */
3180	uint32_t cMonitoredPages;
3181	} Rom,
3182	Mmio2,
3183	Ram;
3184	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3185	uint32_t cIgnoredPages;
3186	/** Indicates that a live save operation is active. */
3187	bool fActive;
3188	/** Padding. */
3189	bool afReserved[2];
3190	/** The next history index. */
3191	uint8_t iDirtyPagesHistory;
3192	/** History of the total amount of dirty pages. */
3193	uint32_t acDirtyPagesHistory[64];
3194	/** Short term dirty page average. */
3195	uint32_t cDirtyPagesShort;
3196	/** Long term dirty page average. */
3197	uint32_t cDirtyPagesLong;
3198	/** The number of saved pages. This is used to get some kind of estimate of the
3199	* link speed so we can decide when we're done. It is reset after the first
3200	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3201	* zero pages. */
3202	uint64_t cSavedPages;
3203	/** The nanosecond timestamp when cSavedPages was 0. */
3204	uint64_t uSaveStartNS;
3205	/** Pages per second (for statistics). */
3206	uint32_t cPagesPerSecond;
3207	uint32_t cAlignment;
3208	} LiveSave;
3209
3210	/** @name Error injection.
3211	* @{ */
3212	/** Inject handy page allocation errors pretending we're completely out of
3213	* memory. */
3214	bool volatile fErrInjHandyPages;
3215	/** Padding. */
3216	bool afReserved[3];
3217	/** @} */
3218
3219	/** @name Release Statistics
3220	* @{ */
3221	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3222	uint32_t cPrivatePages; /*< The number of private pages. /
3223	uint32_t cSharedPages; /*< The number of shared pages. /
3224	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3225	uint32_t cZeroPages; /*< The number of zero backed pages. /
3226	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3227	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3228	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3229	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3230	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3231	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3232	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3233	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3234	uint32_t cLargePages; /*< The number of large pages. /
3235	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3236	/* uint32_t aAlignment4[1]; */
3237
3238	/** The number of times we were forced to change the hypervisor region location. */
3239	STAMCOUNTER cRelocations;
3240
3241	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3242	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3243	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3244
3245	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3246	/** @} */
3247
3248	#ifdef VBOX_WITH_STATISTICS
3249	/** These are optional statistics that used to be on the hyper heap. */
3250	PGMSTATS Stats;
3251	#endif
3252	} PGM;
3253	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3254	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3255	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3256	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3257	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3258	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3259	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3260	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3261	#endif /* !IN_TSTVMSTRUCTGC */
3262	/** Pointer to the PGM instance data. */
3263	typedef PGM *PPGM;
3264
3265
3266	#ifdef VBOX_WITH_STATISTICS
3267	/**
3268	* Per CPU statistis for PGM (used to be on the heap).
3269	*/
3270	typedef struct PGMCPUSTATS
3271	{
3272	/* Common */
3273	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3274	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3275
3276	/* R0 only: */
3277	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3278	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3279
3280	/* RZ only: */
3281	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3282	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3283	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3284	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3285	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3286	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3287	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3288	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3289	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3290	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3291	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3292	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3293	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3294	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3295	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3296	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3297	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3298	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3299	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3300	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3301	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3302	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3303	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3304	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3305	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3306	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3307	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3308	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3309	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3310	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3311	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3312	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3313	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3314	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3315	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3316	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3317	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3318	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3319	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3320	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3321	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3322	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3323	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3324	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3325	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3326	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3327	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3328	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3329	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3330	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3331	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3332	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3333	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3334	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3335	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3336	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3337	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3338	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3339	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3340	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3341	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3342	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3343	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3344	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3345	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3346	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3347	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3348	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3349	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3350	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3351
3352	/* HC - R3 and (maybe) R0: */
3353
3354	/* RZ & R3: */
3355	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3356	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3357	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3358	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3359	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3360	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3361	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3362	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3363	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3364	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3365	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3366	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3367	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3368	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3369	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3370	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3371	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3372	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3373	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3374	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3375	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3376	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3377	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3378	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3379	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3380	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3381	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3382	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3383	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3384	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3385	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3386	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3387	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3388	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3389	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3390	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3391	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3392	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3393	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3394	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3395	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3396	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3397	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3398	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3399	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3400	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3401	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3402
3403	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3404	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3405	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3406	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3407	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3408	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3409	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3410	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3411	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3412	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3413	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3414	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3415	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3416	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3417	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3418	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3419	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3420	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3421	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3422	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3423	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3424	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3425	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3426	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3427	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3428	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3429	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3430	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3431	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3432	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3433	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3434	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3435	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3436	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3437	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3438	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3439	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3440	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3441	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3442	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3443	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3444	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3445	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3446	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3447	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3448	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3449	} PGMCPUSTATS;
3450	#endif /* VBOX_WITH_STATISTICS */
3451
3452
3453	/**
3454	* PGMCPU Data (part of VMCPU).
3455	*/
3456	typedef struct PGMCPU
3457	{
3458	/** A20 gate mask.
3459	* Our current approach to A20 emulation is to let REM do it and don't bother
3460	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3461	* But whould need arrise, we'll subject physical addresses to this mask. */
3462	RTGCPHYS GCPhysA20Mask;
3463	/** A20 gate state - boolean! */
3464	bool fA20Enabled;
3465	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3466	bool fNoExecuteEnabled;
3467	/** Unused bits. */
3468	bool afUnused[2];
3469
3470	/** What needs syncing (PGM_SYNC_*).
3471	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3472	* PGMFlushTLB, and PGMR3Load. */
3473	uint32_t fSyncFlags;
3474
3475	/** The shadow paging mode. */
3476	PGMMODE enmShadowMode;
3477	/** The guest paging mode. */
3478	PGMMODE enmGuestMode;
3479	/** Guest mode data table index (PGM_TYPE_XXX). */
3480	uint8_t volatile idxGuestModeData;
3481	/** Shadow mode data table index (PGM_TYPE_XXX). */
3482	uint8_t volatile idxShadowModeData;
3483	/** Both mode data table index (complicated). */
3484	uint8_t volatile idxBothModeData;
3485	/** Alignment padding. */
3486	uint8_t abPadding[5];
3487
3488	/** The current physical address represented in the guest CR3 register. */
3489	RTGCPHYS GCPhysCR3;
3490
3491	/** @name 32-bit Guest Paging.
3492	* @{ */
3493	/** The guest's page directory, R3 pointer. */
3494	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3495	/** The guest's page directory, R0 pointer. */
3496	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3497	/** Mask containing the MBZ bits of a big page PDE. */
3498	uint32_t fGst32BitMbzBigPdeMask;
3499	/** Set if the page size extension (PSE) is enabled. */
3500	bool fGst32BitPageSizeExtension;
3501	/** Alignment padding. */
3502	bool afAlignment2[3];
3503	/** @} */
3504
3505	/** @name PAE Guest Paging.
3506	* @{ */
3507	/** The guest's page directory pointer table, R3 pointer. */
3508	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3509	/** The guest's page directory pointer table, R0 pointer. */
3510	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3511
3512	/** The guest's page directories, R3 pointers.
3513	* These are individual pointers and don't have to be adjacent.
3514	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3515	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3516	/** The guest's page directories, R0 pointers.
3517	* Same restrictions as apGstPaePDsR3. */
3518	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3519	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3520	RTGCPHYS aGCPhysGstPaePDs[4];
3521	/** The physical addresses of the monitored guest page directories (PAE). */
3522	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3523	/** Mask containing the MBZ PTE bits. */
3524	uint64_t fGstPaeMbzPteMask;
3525	/** Mask containing the MBZ PDE bits. */
3526	uint64_t fGstPaeMbzPdeMask;
3527	/** Mask containing the MBZ big page PDE bits. */
3528	uint64_t fGstPaeMbzBigPdeMask;
3529	/** Mask containing the MBZ PDPE bits. */
3530	uint64_t fGstPaeMbzPdpeMask;
3531	/** @} */
3532
3533	/** @name AMD64 Guest Paging.
3534	* @{ */
3535	/** The guest's page directory pointer table, R3 pointer. */
3536	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3537	/** The guest's page directory pointer table, R0 pointer. */
3538	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3539	/** Mask containing the MBZ PTE bits. */
3540	uint64_t fGstAmd64MbzPteMask;
3541	/** Mask containing the MBZ PDE bits. */
3542	uint64_t fGstAmd64MbzPdeMask;
3543	/** Mask containing the MBZ big page PDE bits. */
3544	uint64_t fGstAmd64MbzBigPdeMask;
3545	/** Mask containing the MBZ PDPE bits. */
3546	uint64_t fGstAmd64MbzPdpeMask;
3547	/** Mask containing the MBZ big page PDPE bits. */
3548	uint64_t fGstAmd64MbzBigPdpeMask;
3549	/** Mask containing the MBZ PML4E bits. */
3550	uint64_t fGstAmd64MbzPml4eMask;
3551	/** Mask containing the PDPE bits that we shadow. */
3552	uint64_t fGstAmd64ShadowedPdpeMask;
3553	/** Mask containing the PML4E bits that we shadow. */
3554	uint64_t fGstAmd64ShadowedPml4eMask;
3555	/** @} */
3556
3557	/** @name PAE and AMD64 Guest Paging.
3558	* @{ */
3559	/** Mask containing the PTE bits that we shadow. */
3560	uint64_t fGst64ShadowedPteMask;
3561	/** Mask containing the PDE bits that we shadow. */
3562	uint64_t fGst64ShadowedPdeMask;
3563	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3564	uint64_t fGst64ShadowedBigPdeMask;
3565	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3566	uint64_t fGst64ShadowedBigPde4PteMask;
3567	/** @} */
3568
3569	/** @name EPT Guest Paging.
3570	* @{ */
3571	/** The guest's page directory pointer table, R3 pointer. */
3572	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3573	/** The guest's page directory pointer table, R0 pointer. */
3574	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3575	/** Mask containing the MBZ PTE bits. */
3576	uint64_t fGstEptMbzPteMask;
3577	/** Mask containing the MBZ PDE bits. */
3578	uint64_t fGstEptMbzPdeMask;
3579	/** Mask containing the MBZ big page PDE bits. */
3580	uint64_t fGstEptMbzBigPdeMask;
3581	/** Mask containing the MBZ PDPE bits. */
3582	uint64_t fGstEptMbzPdpeMask;
3583	/** Mask containing the MBZ big page PDPE bits. */
3584	uint64_t fGstEptMbzBigPdpeMask;
3585	/** Mask containing the MBZ PML4E bits. */
3586	uint64_t fGstEptMbzPml4eMask;
3587	/** Mask to determine whether an entry is present. */
3588	uint64_t fGstEptPresentMask;
3589	/** Mask containing the PML4E bits that we shadow. */
3590	uint64_t fGstEptShadowedPml4eMask;
3591	/** Mask containing the PDPE bits that we shadow. */
3592	uint64_t fGstEptShadowedPdpeMask;
3593	/** Mask containing the big page PDPE bits that we shadow. */
3594	uint64_t fGstEptShadowedBigPdpeMask;
3595	/** Mask containing the PDE bits that we shadow. */
3596	uint64_t fGstEptShadowedPdeMask;
3597	/** Mask containing the big page PDE bits that we shadow. */
3598	uint64_t fGstEptShadowedBigPdeMask;
3599	/** Mask containing the PTE bits that we shadow. */
3600	uint64_t fGstEptShadowedPteMask;
3601	/** @} */
3602
3603	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3604	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3605	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3606	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3607
3608	/** For saving stack space, the disassembler state is allocated here instead of
3609	* on the stack. */
3610	DISCPUSTATE DisState;
3611
3612	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3613	uint64_t cNetwareWp0Hacks;
3614
3615	/** Count the number of pgm pool access handler calls. */
3616	uint64_t cPoolAccessHandler;
3617
3618	/** @name Release Statistics
3619	* @{ */
3620	/** The number of times the guest has switched mode since last reset or statistics reset. */
3621	STAMCOUNTER cGuestModeChanges;
3622	/** The number of times the guest has switched mode since last reset or statistics reset. */
3623	STAMCOUNTER cA20Changes;
3624	/** @} */
3625
3626	#ifdef VBOX_WITH_STATISTICS
3627	/** These are statistics that used to be on the hyper heap. */
3628	PGMCPUSTATS Stats;
3629	#endif
3630	} PGMCPU;
3631	/** Pointer to the per-cpu PGM data. */
3632	typedef PGMCPU *PPGMCPU;
3633
3634
3635	/** @name PGM::fSyncFlags Flags
3636	* @note Was part of saved state a long time ago.
3637	* @{
3638	*/
3639	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3640	/** Always sync CR3. */
3641	#define PGM_SYNC_ALWAYS RT_BIT(1)
3642	/** Check guest mapping in SyncCR3. */
3643	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3644	/** Clear the page pool (a light weight flush). */
3645	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3646	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3647	/** @} */
3648
3649
3650	/**
3651	* PGM GVMCPU instance data.
3652	*/
3653	typedef struct PGMR0PERVCPU
3654	{
3655	#ifdef VBOX_WITH_STATISTICS
3656	/** R0: Which statistic this \#PF should be attributed to. */
3657	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3658	#endif
3659	uint64_t u64Dummy;
3660	} PGMR0PERVCPU;
3661
3662
3663	/**
3664	* PGM GVM instance data.
3665	*/
3666	typedef struct PGMR0PERVM
3667	{
3668	/** @name PGM Pool related stuff.
3669	* @{ */
3670	/** Critical section for serializing pool growth. */
3671	RTCRITSECT PoolGrowCritSect;
3672	/** The memory objects for the pool pages. */
3673	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3674	/** The ring-3 mapping objects for the pool pages. */
3675	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3676	/** @} */
3677	} PGMR0PERVM;
3678
3679	RT_C_DECLS_BEGIN
3680
3681	#if defined(VBOX_STRICT)
3682	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3683	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3684	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3685	#else
3686	int pgmLock(PVMCC pVM, bool fVoid);
3687	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3688	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3689	#endif
3690	void pgmUnlock(PVMCC pVM);
3691	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3692	/**
3693	* Asserts that the caller owns the PDM lock.
3694	* This is the internal variant of PGMIsLockOwner.
3695	* @param a_pVM Pointer to the VM.
3696	*/
3697	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3698	/**
3699	* Asserts that the caller owns the PDM lock.
3700	* This is the internal variant of PGMIsLockOwner.
3701	* @param a_pVM Pointer to the VM.
3702	* @param a_pVCpu The current CPU handle.
3703	*/
3704	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3705
3706	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3707	RTRCPTR pvUserRC, R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3708	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3709	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3710	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3711	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3712	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3713	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3714	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3715	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3716	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3717
3718	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3719	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3720	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3721	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3722	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3723	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3724	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3725	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3726	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3727	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3728	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3729	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3730	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3731	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3732	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3733	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3734	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3735	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3736	#ifndef IN_RING3
3737	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3738	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3739	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3740	#endif
3741	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3742	PGMPAGETYPE enmNewType);
3743	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3744	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3745	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3746	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3747	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3748	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3749	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3750	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3751	#ifdef VBOX_WITH_NATIVE_NEM
3752	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3753	#endif
3754
3755	#ifdef IN_RING3
3756	void pgmR3PhysRelinkRamRanges(PVM pVM);
3757	int pgmR3PhysRamPreAllocate(PVM pVM);
3758	int pgmR3PhysRamReset(PVM pVM);
3759	int pgmR3PhysRomReset(PVM pVM);
3760	int pgmR3PhysRamZeroAll(PVM pVM);
3761	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3762	int pgmR3PhysRamTerm(PVM pVM);
3763	void pgmR3PhysRomTerm(PVM pVM);
3764	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3765
3766	int pgmR3PoolInit(PVM pVM);
3767	void pgmR3PoolRelocate(PVM pVM);
3768	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3769	void pgmR3PoolReset(PVM pVM);
3770	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3771	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3772	void pgmR3PoolWriteProtectPages(PVM pVM);
3773
3774	#endif /* IN_RING3 */
3775	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3776	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3777	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3778	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3779	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3780	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3781	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3782	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3783	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3784	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3785	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3786	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3787	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3788	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3789	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3790	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3791	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3792	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3793	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3794	#ifndef IN_RING3
3795	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3796	#endif
3797
3798	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3799	void pgmPoolResetDirtyPages(PVMCC pVM);
3800	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3801
3802	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3803	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3804	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3805
3806	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3807	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3808	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3809
3810	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3811	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3812	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3813	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3814	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3815	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3816	#endif
3817	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3818	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3819
3820	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3821	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3822	FNDBGCCMD pgmR3CmdShowSharedModules;
3823	# endif
3824
3825	void pgmLogState(PVM pVM);
3826
3827	RT_C_DECLS_END
3828
3829	/** @} */
3830
3831	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3832

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 91929

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