VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 92162

Last change on this file since 92162 was 92162, checked in by vboxsync, 3 years ago

VMM/PGM,DevVGA: Baked MMIO2 dirty page tracking into PGM, moving it out of DevVGA. Using the handler state to record a page as dirty (PGM_PAGE_HNDL_PHYS_STATE_DISABLED). bugref:10122
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1/* $Id: PGMInternal.h 92162 2021-10-31 23:34:31Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Check and skip global PDEs for non-global flushes
62 */
63#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
64
65/**
66 * Optimization for PAE page tables that are modified often
67 */
68//#if 0 /* disabled again while debugging */
69#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
70//#endif
71
72/**
73 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
74 */
75#define PGM_WITH_LARGE_PAGES
76
77/**
78 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
79 * VMX_EXIT_EPT_MISCONFIG.
80 */
81#define PGM_WITH_MMIO_OPTIMIZATIONS
82
83/**
84 * Sync N pages instead of a whole page table
85 */
86#define PGM_SYNC_N_PAGES
87
88/**
89 * Number of pages to sync during a page fault
90 *
91 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
92 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
93 *
94 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
95 * world switch overhead, so let's sync more.
96 */
97#ifdef IN_RING0
98/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
99 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
100 * but ~5% fewer faults.
101 */
102# define PGM_SYNC_NR_PAGES 32
103#else
104# define PGM_SYNC_NR_PAGES 8
105#endif
106
107/**
108 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
109 */
110#define PGM_MAX_PHYSCACHE_ENTRIES 64
111#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
112
113
114/** @def PGMPOOL_CFG_MAX_GROW
115 * The maximum number of pages to add to the pool in one go.
116 */
117#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
118
119/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
120 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
121 */
122#ifdef VBOX_STRICT
123# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
124#endif
125
126/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
127 * Enables the experimental lazy page allocation code. */
128#ifdef DOXYGEN_RUNNING
129# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130#endif
131
132/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
133 * Enables real write monitoring of pages, i.e. mapping them read-only and
134 * only making them writable when getting a write access \#PF. */
135#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
136
137/** @def VBOX_WITH_PGM_NEM_MODE
138 * Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
139 * details. */
140#ifdef DOXYGEN_RUNNING
141# define VBOX_WITH_PGM_NEM_MODE
142#endif
143
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** PGM specific bits in PML4 entries. */
155#define PGM_PML4_FLAGS 0
156/** PGM specific bits in PDPT entries. */
157#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
158/** @} */
159
160/** @name Page directory flags.
161 * These are placed in the three bits available for system programs in
162 * the page directory entries.
163 * @{ */
164/** Indicates the original entry was a big page.
165 * @remarks This is currently only used for statistics and can be recycled. */
166#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184
185/** @} */
186
187/** @name Defines used to indicate the shadow and guest paging in the templates.
188 * @{ */
189#define PGM_TYPE_REAL 1
190#define PGM_TYPE_PROT 2
191#define PGM_TYPE_32BIT 3
192#define PGM_TYPE_PAE 4
193#define PGM_TYPE_AMD64 5
194#define PGM_TYPE_NESTED_32BIT 6
195#define PGM_TYPE_NESTED_PAE 7
196#define PGM_TYPE_NESTED_AMD64 8
197#define PGM_TYPE_EPT 9
198#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
199#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
200#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
201/** @} */
202
203/** Macro for checking if the guest is using paging.
204 * @param uGstType PGM_TYPE_*
205 * @param uShwType PGM_TYPE_*
206 * @remark ASSUMES certain order of the PGM_TYPE_* values.
207 */
208#define PGM_WITH_PAGING(uGstType, uShwType) \
209 ( (uGstType) >= PGM_TYPE_32BIT \
210 && (uShwType) < PGM_TYPE_NESTED_32BIT)
211
212/** Macro for checking if the guest supports the NX bit.
213 * @param uGstType PGM_TYPE_*
214 * @param uShwType PGM_TYPE_*
215 * @remark ASSUMES certain order of the PGM_TYPE_* values.
216 */
217#define PGM_WITH_NX(uGstType, uShwType) \
218 ( (uGstType) >= PGM_TYPE_PAE \
219 && (uShwType) < PGM_TYPE_NESTED_32BIT)
220
221/** Macro for checking for nested.
222 * @param uType PGM_TYPE_*
223 */
224#define PGM_TYPE_IS_NESTED(uType) \
225 ( (uType) == PGM_TYPE_NESTED_32BIT \
226 || (uType) == PGM_TYPE_NESTED_PAE \
227 || (uType) == PGM_TYPE_NESTED_AMD64)
228
229/** Macro for checking for nested or EPT.
230 * @param uType PGM_TYPE_*
231 */
232#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
233 ( (uType) == PGM_TYPE_NESTED_32BIT \
234 || (uType) == PGM_TYPE_NESTED_PAE \
235 || (uType) == PGM_TYPE_NESTED_AMD64 \
236 || (uType) == PGM_TYPE_EPT)
237
238
239
240/** @def PGM_HCPHYS_2_PTR
241 * Maps a HC physical page pool address to a virtual address.
242 *
243 * @returns VBox status code.
244 * @param pVM The cross context VM structure.
245 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
246 * @param HCPhys The HC physical address to map to a virtual one.
247 * @param ppv Where to store the virtual address. No need to cast
248 * this.
249 *
250 * @remark There is no need to assert on the result.
251 */
252#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
253
254/** @def PGM_GCPHYS_2_PTR_V2
255 * Maps a GC physical page address to a virtual address.
256 *
257 * @returns VBox status code.
258 * @param pVM The cross context VM structure.
259 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
260 * @param GCPhys The GC physical address to map to a virtual one.
261 * @param ppv Where to store the virtual address. No need to cast this.
262 *
263 * @remark Use with care as we don't have so much dynamic mapping space in
264 * ring-0 on 32-bit darwin and in RC.
265 * @remark There is no need to assert on the result.
266 */
267#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
268 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
269
270/** @def PGM_GCPHYS_2_PTR
271 * Maps a GC physical page address to a virtual address.
272 *
273 * @returns VBox status code.
274 * @param pVM The cross context VM structure.
275 * @param GCPhys The GC physical address to map to a virtual one.
276 * @param ppv Where to store the virtual address. No need to cast this.
277 *
278 * @remark Use with care as we don't have so much dynamic mapping space in
279 * ring-0 on 32-bit darwin and in RC.
280 * @remark There is no need to assert on the result.
281 */
282#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
283
284/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
285 * Maps a GC physical page address to a virtual address.
286 *
287 * @returns VBox status code.
288 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark Use with care as we don't have so much dynamic mapping space in
293 * ring-0 on 32-bit darwin and in RC.
294 * @remark There is no need to assert on the result.
295 */
296#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
297
298/** @def PGM_GCPHYS_2_PTR_EX
299 * Maps a unaligned GC physical page address to a virtual address.
300 *
301 * @returns VBox status code.
302 * @param pVM The cross context VM structure.
303 * @param GCPhys The GC physical address to map to a virtual one.
304 * @param ppv Where to store the virtual address. No need to cast this.
305 *
306 * @remark Use with care as we don't have so much dynamic mapping space in
307 * ring-0 on 32-bit darwin and in RC.
308 * @remark There is no need to assert on the result.
309 */
310#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
312
313/** @def PGM_DYNMAP_UNUSED_HINT
314 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
315 * is no longer used.
316 *
317 * For best effect only apply this to the page that was mapped most recently.
318 *
319 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
320 * @param pvPage The pool page.
321 */
322#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
323
324/** @def PGM_DYNMAP_UNUSED_HINT_VM
325 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
326 * is no longer used.
327 *
328 * For best effect only apply this to the page that was mapped most recently.
329 *
330 * @param pVM The cross context VM structure.
331 * @param pvPage The pool page.
332 */
333#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
334
335
336/** @def PGM_INVL_PG
337 * Invalidates a page.
338 *
339 * @param pVCpu The cross context virtual CPU structure.
340 * @param GCVirt The virtual address of the page to invalidate.
341 */
342#ifdef IN_RING0
343# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
344#elif defined(IN_RING3)
345# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
346#else
347# error "Not IN_RING0 or IN_RING3!"
348#endif
349
350/** @def PGM_INVL_PG_ALL_VCPU
351 * Invalidates a page on all VCPUs
352 *
353 * @param pVM The cross context VM structure.
354 * @param GCVirt The virtual address of the page to invalidate.
355 */
356#ifdef IN_RING0
357# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_BIG_PG
363 * Invalidates a 4MB page directory entry.
364 *
365 * @param pVCpu The cross context virtual CPU structure.
366 * @param GCVirt The virtual address within the page directory to invalidate.
367 */
368#ifdef IN_RING0
369# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
370#else
371# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
372#endif
373
374/** @def PGM_INVL_VCPU_TLBS()
375 * Invalidates the TLBs of the specified VCPU
376 *
377 * @param pVCpu The cross context virtual CPU structure.
378 */
379#ifdef IN_RING0
380# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
381#else
382# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
383#endif
384
385/** @def PGM_INVL_ALL_VCPU_TLBS()
386 * Invalidates the TLBs of all VCPUs
387 *
388 * @param pVM The cross context VM structure.
389 */
390#ifdef IN_RING0
391# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
392#else
393# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
394#endif
395
396
397/** @name Safer Shadow PAE PT/PTE
398 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
399 * present.
400 *
401 * @{
402 */
403#if 1
404/**
405 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
406 * invalid entries for present.
407 * @sa X86PTEPAE.
408 */
409typedef union PGMSHWPTEPAE
410{
411 /** Unsigned integer view */
412 X86PGPAEUINT uCareful;
413 /* Not other views. */
414} PGMSHWPTEPAE;
415
416# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
417# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
418# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
419# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
420# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
421# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
422# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
423# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
424# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
425# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
426# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
427# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
428# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
429# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
430# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
431# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
432
433/**
434 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
435 * invalid entries for present.
436 * @sa X86PTPAE.
437 */
438typedef struct PGMSHWPTPAE
439{
440 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
441} PGMSHWPTPAE;
442
443#else
444typedef X86PTEPAE PGMSHWPTEPAE;
445typedef X86PTPAE PGMSHWPTPAE;
446# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
447# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
448# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
449# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
450# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
451# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
452# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
453# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
454# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
455# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
456# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
457# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
458# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
459# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
460# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
461# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
462
463#endif
464
465/** Pointer to a shadow PAE PTE. */
466typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
467/** Pointer to a const shadow PAE PTE. */
468typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
469
470/** Pointer to a shadow PAE page table. */
471typedef PGMSHWPTPAE *PPGMSHWPTPAE;
472/** Pointer to a const shadow PAE page table. */
473typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
474/** @} */
475
476
477/**
478 * Physical page access handler type registration.
479 */
480typedef struct PGMPHYSHANDLERTYPEINT
481{
482 /** Number of references. */
483 uint32_t volatile cRefs;
484 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
485 uint32_t u32Magic;
486 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
487 RTLISTOFF32NODE ListNode;
488 /** The kind of accesses we're handling. */
489 PGMPHYSHANDLERKIND enmKind;
490 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
491 uint8_t uState;
492 /** Whether to keep the PGM lock when calling the handler. */
493 bool fKeepPgmLock;
494 bool afPadding[2];
495 /** Pointer to R3 callback function. */
496 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
499 /** Pointer to R0 callback function for \#PFs. */
500 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
501 /** Description / Name. For easing debugging. */
502 R3PTRTYPE(const char *) pszDesc;
503} PGMPHYSHANDLERTYPEINT;
504/** Pointer to a physical access handler type registration. */
505typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
506/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
507#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
508/** Magic value for the physical handler callbacks. */
509#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
510
511/**
512 * Converts a handle to a pointer.
513 * @returns PPGMPHYSHANDLERTYPEINT
514 * @param a_pVM The cross context VM structure.
515 * @param a_hType Physical access handler type handle.
516 */
517#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
518
519
520/**
521 * Physical page access handler structure.
522 *
523 * This is used to keep track of physical address ranges
524 * which are being monitored in some kind of way.
525 */
526typedef struct PGMPHYSHANDLER
527{
528 AVLROGCPHYSNODECORE Core;
529 /** Number of pages to update. */
530 uint32_t cPages;
531 /** Set if we have pages that have been aliased. */
532 uint32_t cAliasedPages;
533 /** Set if we have pages that have temporarily been disabled. */
534 uint32_t cTmpOffPages;
535 /** Registered handler type handle (heap offset). */
536 PGMPHYSHANDLERTYPE hType;
537 /** User argument for R3 handlers. */
538 R3PTRTYPE(void *) pvUserR3;
539 /** User argument for R0 handlers. */
540 R0PTRTYPE(void *) pvUserR0;
541 /** Description / Name. For easing debugging. */
542 R3PTRTYPE(const char *) pszDesc;
543#ifdef VBOX_WITH_STATISTICS
544 /** Profiling of this handler. */
545 STAMPROFILE Stat;
546#endif
547} PGMPHYSHANDLER;
548/** Pointer to a physical page access handler structure. */
549typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
550
551/**
552 * Gets the type record for a physical handler (no reference added).
553 * @returns PPGMPHYSHANDLERTYPEINT
554 * @param a_pVM The cross context VM structure.
555 * @param a_pPhysHandler Pointer to the physical handler structure
556 * (PGMPHYSHANDLER).
557 */
558#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
559
560
561/**
562 * A Physical Guest Page tracking structure.
563 *
564 * The format of this structure is complicated because we have to fit a lot
565 * of information into as few bits as possible. The format is also subject
566 * to change (there is one coming up soon). Which means that for we'll be
567 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
568 * accesses to the structure.
569 */
570typedef union PGMPAGE
571{
572 /** Structured view. */
573 struct
574 {
575 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
576 uint64_t u2HandlerPhysStateY : 2;
577 /** 3:2 - Paging structure needed to map the page
578 * (PGM_PAGE_PDE_TYPE_*). */
579 uint64_t u2PDETypeY : 2;
580 /** 4 - Unused (was used by FTE for dirty tracking). */
581 uint64_t fUnused1 : 1;
582 /** 5 - Flag indicating that a write monitored page was written to
583 * when set. */
584 uint64_t fWrittenToY : 1;
585 /** 7:6 - Unused. */
586 uint64_t u2Unused0 : 2;
587 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
588 uint64_t u2Unused1 : 2;
589 /** 11:10 - NEM state bits. */
590 uint64_t u2NemStateY : 2;
591 /** 12:48 - The host physical frame number (shift left to get the
592 * address). */
593 uint64_t HCPhysFN : 36;
594 /** 50:48 - The page state. */
595 uint64_t uStateY : 3;
596 /** 51:53 - The page type (PGMPAGETYPE). */
597 uint64_t uTypeY : 3;
598 /** 63:54 - PTE index for usage tracking (page pool). */
599 uint64_t u10PteIdx : 10;
600
601 /** The GMM page ID.
602 * @remarks In the current implementation, MMIO2 and pages aliased to
603 * MMIO2 pages will be exploiting this field to calculate the
604 * ring-3 mapping address corresponding to the page.
605 * Later we may consider including MMIO2 management into GMM. */
606 uint32_t idPage;
607 /** Usage tracking (page pool). */
608 uint16_t u16TrackingY;
609 /** The number of read locks on this page. */
610 uint8_t cReadLocksY;
611 /** The number of write locks on this page. */
612 uint8_t cWriteLocksY;
613 } s;
614
615 /** 64-bit integer view. */
616 uint64_t au64[2];
617 /** 16-bit view. */
618 uint32_t au32[4];
619 /** 16-bit view. */
620 uint16_t au16[8];
621 /** 8-bit view. */
622 uint8_t au8[16];
623} PGMPAGE;
624AssertCompileSize(PGMPAGE, 16);
625/** Pointer to a physical guest page. */
626typedef PGMPAGE *PPGMPAGE;
627/** Pointer to a const physical guest page. */
628typedef const PGMPAGE *PCPGMPAGE;
629/** Pointer to a physical guest page pointer. */
630typedef PPGMPAGE *PPPGMPAGE;
631
632
633/**
634 * Clears the page structure.
635 * @param a_pPage Pointer to the physical guest page tracking structure.
636 */
637#define PGM_PAGE_CLEAR(a_pPage) \
638 do { \
639 (a_pPage)->au64[0] = 0; \
640 (a_pPage)->au64[1] = 0; \
641 } while (0)
642
643/**
644 * Initializes the page structure.
645 * @param a_pPage Pointer to the physical guest page tracking structure.
646 * @param a_HCPhys The host physical address of the page.
647 * @param a_idPage The (GMM) page ID of the page.
648 * @param a_uType The page type (PGMPAGETYPE).
649 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
650 */
651#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
652 do { \
653 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
654 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
655 (a_pPage)->au64[0] = SetHCPhysTmp; \
656 (a_pPage)->au64[1] = 0; \
657 (a_pPage)->s.idPage = (a_idPage); \
658 (a_pPage)->s.uStateY = (a_uState); \
659 (a_pPage)->s.uTypeY = (a_uType); \
660 } while (0)
661
662/**
663 * Initializes the page structure of a ZERO page.
664 * @param a_pPage Pointer to the physical guest page tracking structure.
665 * @param a_pVM The VM handle (for getting the zero page address).
666 * @param a_uType The page type (PGMPAGETYPE).
667 */
668#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
669 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
670
671
672/** @name The Page state, PGMPAGE::uStateY.
673 * @{ */
674/** The zero page.
675 * This is a per-VM page that's never ever mapped writable. */
676#define PGM_PAGE_STATE_ZERO 0U
677/** A allocated page.
678 * This is a per-VM page allocated from the page pool (or wherever
679 * we get MMIO2 pages from if the type is MMIO2).
680 */
681#define PGM_PAGE_STATE_ALLOCATED 1U
682/** A allocated page that's being monitored for writes.
683 * The shadow page table mappings are read-only. When a write occurs, the
684 * fWrittenTo member is set, the page remapped as read-write and the state
685 * moved back to allocated. */
686#define PGM_PAGE_STATE_WRITE_MONITORED 2U
687/** The page is shared, aka. copy-on-write.
688 * This is a page that's shared with other VMs. */
689#define PGM_PAGE_STATE_SHARED 3U
690/** The page is ballooned, so no longer available for this VM. */
691#define PGM_PAGE_STATE_BALLOONED 4U
692/** @} */
693
694
695/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
696#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
697# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
698#else
699# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
700#endif
701
702/**
703 * Gets the page state.
704 * @returns page state (PGM_PAGE_STATE_*).
705 * @param a_pPage Pointer to the physical guest page tracking structure.
706 *
707 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
708 * builds.
709 */
710#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
711#if defined(__GNUC__) && defined(VBOX_STRICT)
712# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
713#else
714# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
715#endif
716
717/**
718 * Sets the page state.
719 * @param a_pVM The VM handle, only used for lock ownership assertions.
720 * @param a_pPage Pointer to the physical guest page tracking structure.
721 * @param a_uState The new page state.
722 */
723#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
724 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
725
726
727/**
728 * Gets the host physical address of the guest page.
729 * @returns host physical address (RTHCPHYS).
730 * @param a_pPage Pointer to the physical guest page tracking structure.
731 *
732 * @remarks In strict builds on gcc platforms, this macro will make some ugly
733 * assumption about a valid pVM variable/parameter being in the
734 * current context. It will use this pVM variable to assert that the
735 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
736 * pVM is not around.
737 */
738#if 0
739# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
740# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
741#else
742# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
743# if defined(__GNUC__) && defined(VBOX_STRICT)
744# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
745# else
746# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
747# endif
748#endif
749
750/**
751 * Sets the host physical address of the guest page.
752 *
753 * @param a_pVM The VM handle, only used for lock ownership assertions.
754 * @param a_pPage Pointer to the physical guest page tracking structure.
755 * @param a_HCPhys The new host physical address.
756 */
757#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
758 do { \
759 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
760 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
761 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
762 PGM_PAGE_ASSERT_LOCK(a_pVM); \
763 } while (0)
764
765/**
766 * Get the Page ID.
767 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
768 * @param a_pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
771
772/**
773 * Sets the Page ID.
774 * @param a_pVM The VM handle, only used for lock ownership assertions.
775 * @param a_pPage Pointer to the physical guest page tracking structure.
776 * @param a_idPage The new page ID.
777 */
778#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
779 do { \
780 (a_pPage)->s.idPage = (a_idPage); \
781 PGM_PAGE_ASSERT_LOCK(a_pVM); \
782 } while (0)
783
784/**
785 * Get the Chunk ID.
786 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
787 * @param a_pPage Pointer to the physical guest page tracking structure.
788 */
789#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
790
791/**
792 * Get the index of the page within the allocation chunk.
793 * @returns The page index.
794 * @param a_pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
797
798/**
799 * Gets the page type.
800 * @returns The page type.
801 * @param a_pPage Pointer to the physical guest page tracking structure.
802 *
803 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
804 * builds.
805 */
806#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
807#if defined(__GNUC__) && defined(VBOX_STRICT)
808# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
809#else
810# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
811#endif
812
813/**
814 * Sets the page type.
815 *
816 * @param a_pVM The VM handle, only used for lock ownership assertions.
817 * @param a_pPage Pointer to the physical guest page tracking structure.
818 * @param a_enmType The new page type (PGMPAGETYPE).
819 */
820#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
821 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
822
823/**
824 * Gets the page table index
825 * @returns The page table index.
826 * @param a_pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
829
830/**
831 * Sets the page table index.
832 * @param a_pVM The VM handle, only used for lock ownership assertions.
833 * @param a_pPage Pointer to the physical guest page tracking structure.
834 * @param a_iPte New page table index.
835 */
836#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
837 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
838
839/**
840 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
841 * @returns true/false.
842 * @param a_pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
845
846/**
847 * Checks if the page is marked for MMIO, including both aliases.
848 * @returns true/false.
849 * @param a_pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
852 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
853 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
854 )
855
856/**
857 * Checks if the page is marked for MMIO, including special aliases.
858 * @returns true/false.
859 * @param a_pPage Pointer to the physical guest page tracking structure.
860 */
861#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
862 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
863
864/**
865 * Checks if the page is a special aliased MMIO page.
866 * @returns true/false.
867 * @param a_pPage Pointer to the physical guest page tracking structure.
868 */
869#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
870
871/**
872 * Checks if the page is backed by the ZERO page.
873 * @returns true/false.
874 * @param a_pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
877
878/**
879 * Checks if the page is backed by a SHARED page.
880 * @returns true/false.
881 * @param a_pPage Pointer to the physical guest page tracking structure.
882 */
883#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
884
885/**
886 * Checks if the page is ballooned.
887 * @returns true/false.
888 * @param a_pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
891
892/**
893 * Checks if the page is allocated.
894 * @returns true/false.
895 * @param a_pPage Pointer to the physical guest page tracking structure.
896 */
897#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
898
899/**
900 * Marks the page as written to (for GMM change monitoring).
901 * @param a_pVM The VM handle, only used for lock ownership assertions.
902 * @param a_pPage Pointer to the physical guest page tracking structure.
903 */
904#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
905 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
906
907/**
908 * Clears the written-to indicator.
909 * @param a_pVM The VM handle, only used for lock ownership assertions.
910 * @param a_pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
913 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
914
915/**
916 * Checks if the page was marked as written-to.
917 * @returns true/false.
918 * @param a_pPage Pointer to the physical guest page tracking structure.
919 */
920#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
921
922
923/** @name PT usage values (PGMPAGE::u2PDEType).
924 *
925 * @{ */
926/** Either as a PT or PDE. */
927#define PGM_PAGE_PDE_TYPE_DONTCARE 0
928/** Must use a page table to map the range. */
929#define PGM_PAGE_PDE_TYPE_PT 1
930/** Can use a page directory entry to map the continuous range. */
931#define PGM_PAGE_PDE_TYPE_PDE 2
932/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
933#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
934/** @} */
935
936/**
937 * Set the PDE type of the page
938 * @param a_pVM The VM handle, only used for lock ownership assertions.
939 * @param a_pPage Pointer to the physical guest page tracking structure.
940 * @param a_uType PGM_PAGE_PDE_TYPE_*.
941 */
942#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
943 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
944
945/**
946 * Checks if the page was marked being part of a large page
947 * @returns true/false.
948 * @param a_pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
951
952/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
953 *
954 * @remarks The values are assigned in order of priority, so we can calculate
955 * the correct state for a page with different handlers installed.
956 * @{ */
957/** No handler installed. */
958#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
959/** Monitoring is temporarily disabled. */
960#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
961/** Write access is monitored. */
962#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
963/** All access is monitored. */
964#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
965/** @} */
966
967/**
968 * Gets the physical access handler state of a page.
969 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
970 * @param a_pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
973
974/**
975 * Sets the physical access handler state of a page.
976 * @param a_pPage Pointer to the physical guest page tracking structure.
977 * @param a_uState The new state value.
978 */
979#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
980 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
981
982/**
983 * Checks if the page has any physical access handlers, including temporarily disabled ones.
984 * @returns true/false
985 * @param a_pPage Pointer to the physical guest page tracking structure.
986 */
987#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
988 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
989
990/**
991 * Checks if the page has any active physical access handlers.
992 * @returns true/false
993 * @param a_pPage Pointer to the physical guest page tracking structure.
994 */
995#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
996 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
997
998/**
999 * Checks if the page has any access handlers, including temporarily disabled ones.
1000 * @returns true/false
1001 * @param a_pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1004 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1005
1006/**
1007 * Checks if the page has any active access handlers.
1008 * @returns true/false
1009 * @param a_pPage Pointer to the physical guest page tracking structure.
1010 */
1011#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1012 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1013
1014/**
1015 * Checks if the page has any active access handlers catching all accesses.
1016 * @returns true/false
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1020 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1021
1022
1023/** @def PGM_PAGE_GET_TRACKING
1024 * Gets the packed shadow page pool tracking data associated with a guest page.
1025 * @returns uint16_t containing the data.
1026 * @param a_pPage Pointer to the physical guest page tracking structure.
1027 */
1028#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1029#if defined(__GNUC__) && defined(VBOX_STRICT)
1030# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1031#else
1032# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1033#endif
1034
1035/** @def PGM_PAGE_SET_TRACKING
1036 * Sets the packed shadow page pool tracking data associated with a guest page.
1037 * @param a_pVM The VM handle, only used for lock ownership assertions.
1038 * @param a_pPage Pointer to the physical guest page tracking structure.
1039 * @param a_u16TrackingData The tracking data to store.
1040 */
1041#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1042 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1043
1044/** @def PGM_PAGE_GET_TD_CREFS
1045 * Gets the @a cRefs tracking data member.
1046 * @returns cRefs.
1047 * @param a_pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1050 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1051#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1052 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1053
1054/** @def PGM_PAGE_GET_TD_IDX
1055 * Gets the @a idx tracking data member.
1056 * @returns idx.
1057 * @param a_pPage Pointer to the physical guest page tracking structure.
1058 */
1059#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1060 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1061#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1062 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1063
1064
1065/** Max number of locks on a page. */
1066#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1067
1068/** Get the read lock count.
1069 * @returns count.
1070 * @param a_pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1073
1074/** Get the write lock count.
1075 * @returns count.
1076 * @param a_pPage Pointer to the physical guest page tracking structure.
1077 */
1078#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1079
1080/** Decrement the read lock counter.
1081 * @param a_pPage Pointer to the physical guest page tracking structure.
1082 */
1083#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1084
1085/** Decrement the write lock counter.
1086 * @param a_pPage Pointer to the physical guest page tracking structure.
1087 */
1088#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1089
1090/** Increment the read lock counter.
1091 * @param a_pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1094
1095/** Increment the write lock counter.
1096 * @param a_pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1099
1100
1101/** Gets the NEM state.
1102 * @returns NEM state value (two bits).
1103 * @param a_pPage Pointer to the physical guest page tracking structure.
1104 */
1105#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1106
1107/** Sets the NEM state.
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 * @param a_u2State The NEM state value (specific to NEM impl.).
1110 */
1111#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1112 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1113
1114
1115#if 0
1116/** Enables sanity checking of write monitoring using CRC-32. */
1117# define PGMLIVESAVERAMPAGE_WITH_CRC32
1118#endif
1119
1120/**
1121 * Per page live save tracking data.
1122 */
1123typedef struct PGMLIVESAVERAMPAGE
1124{
1125 /** Number of times it has been dirtied. */
1126 uint32_t cDirtied : 24;
1127 /** Whether it is currently dirty. */
1128 uint32_t fDirty : 1;
1129 /** Ignore the page.
1130 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1131 * deal with these after pausing the VM and DevPCI have said it bit about
1132 * remappings. */
1133 uint32_t fIgnore : 1;
1134 /** Was a ZERO page last time around. */
1135 uint32_t fZero : 1;
1136 /** Was a SHARED page last time around. */
1137 uint32_t fShared : 1;
1138 /** Whether the page is/was write monitored in a previous pass. */
1139 uint32_t fWriteMonitored : 1;
1140 /** Whether the page is/was write monitored earlier in this pass. */
1141 uint32_t fWriteMonitoredJustNow : 1;
1142 /** Bits reserved for future use. */
1143 uint32_t u2Reserved : 2;
1144#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1145 /** CRC-32 for the page. This is for internal consistency checks. */
1146 uint32_t u32Crc;
1147#endif
1148} PGMLIVESAVERAMPAGE;
1149#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1150AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1151#else
1152AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1153#endif
1154/** Pointer to the per page live save tracking data. */
1155typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1156
1157/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1158#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1159
1160
1161/**
1162 * RAM range for GC Phys to HC Phys conversion.
1163 *
1164 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1165 * conversions too, but we'll let MM handle that for now.
1166 *
1167 * This structure is used by linked lists in both GC and HC.
1168 */
1169typedef struct PGMRAMRANGE
1170{
1171 /** Start of the range. Page aligned. */
1172 RTGCPHYS GCPhys;
1173 /** Size of the range. (Page aligned of course). */
1174 RTGCPHYS cb;
1175 /** Pointer to the next RAM range - for R3. */
1176 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1177 /** Pointer to the next RAM range - for R0. */
1178 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1179 /** PGM_RAM_RANGE_FLAGS_* flags. */
1180 uint32_t fFlags;
1181 uint32_t fPadding1;
1182 /** Last address in the range (inclusive). Page aligned (-1). */
1183 RTGCPHYS GCPhysLast;
1184 /** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1185 R3PTRTYPE(void *) pvR3;
1186 /** Live save per page tracking data. */
1187 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1188 /** The range description. */
1189 R3PTRTYPE(const char *) pszDesc;
1190 /** Pointer to self - R0 pointer. */
1191 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1192
1193 /** Pointer to the left search three node - ring-3 context. */
1194 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1195 /** Pointer to the right search three node - ring-3 context. */
1196 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1197 /** Pointer to the left search three node - ring-0 context. */
1198 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1199 /** Pointer to the right search three node - ring-0 context. */
1200 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1201
1202 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1203#if HC_ARCH_BITS == 32
1204 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1205#endif
1206 /** Array of physical guest page tracking structures. */
1207 PGMPAGE aPages[1];
1208} PGMRAMRANGE;
1209/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1210typedef PGMRAMRANGE *PPGMRAMRANGE;
1211
1212/** @name PGMRAMRANGE::fFlags
1213 * @{ */
1214/** The RAM range is floating around as an independent guest mapping. */
1215#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1216/** Ad hoc RAM range for an ROM mapping. */
1217#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1218/** Ad hoc RAM range for an MMIO mapping. */
1219#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1220/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1221#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1222/** @} */
1223
1224/** Tests if a RAM range is an ad hoc one or not.
1225 * @returns true/false.
1226 * @param pRam The RAM range.
1227 */
1228#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1229 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1230
1231/** The number of entries in the RAM range TLBs (there is one for each
1232 * context). Must be a power of two. */
1233#define PGM_RAMRANGE_TLB_ENTRIES 8
1234
1235/**
1236 * Calculates the RAM range TLB index for the physical address.
1237 *
1238 * @returns RAM range TLB index.
1239 * @param a_GCPhys The guest physical address.
1240 */
1241#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1242
1243/**
1244 * Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1245 * mapping address.
1246 */
1247#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1248 ( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1249
1250
1251/**
1252 * Per page tracking structure for ROM image.
1253 *
1254 * A ROM image may have a shadow page, in which case we may have two pages
1255 * backing it. This structure contains the PGMPAGE for both while
1256 * PGMRAMRANGE have a copy of the active one. It is important that these
1257 * aren't out of sync in any regard other than page pool tracking data.
1258 */
1259typedef struct PGMROMPAGE
1260{
1261 /** The page structure for the virgin ROM page. */
1262 PGMPAGE Virgin;
1263 /** The page structure for the shadow RAM page. */
1264 PGMPAGE Shadow;
1265 /** The current protection setting. */
1266 PGMROMPROT enmProt;
1267 /** Live save status information. Makes use of unused alignment space. */
1268 struct
1269 {
1270 /** The previous protection value. */
1271 uint8_t u8Prot;
1272 /** Written to flag set by the handler. */
1273 bool fWrittenTo;
1274 /** Whether the shadow page is dirty or not. */
1275 bool fDirty;
1276 /** Whether it was dirtied in the recently. */
1277 bool fDirtiedRecently;
1278 } LiveSave;
1279} PGMROMPAGE;
1280AssertCompileSizeAlignment(PGMROMPAGE, 8);
1281/** Pointer to a ROM page tracking structure. */
1282typedef PGMROMPAGE *PPGMROMPAGE;
1283
1284
1285/**
1286 * A registered ROM image.
1287 *
1288 * This is needed to keep track of ROM image since they generally intrude
1289 * into a PGMRAMRANGE. It also keeps track of additional info like the
1290 * two page sets (read-only virgin and read-write shadow), the current
1291 * state of each page.
1292 *
1293 * Because access handlers cannot easily be executed in a different
1294 * context, the ROM ranges needs to be accessible and in all contexts.
1295 */
1296typedef struct PGMROMRANGE
1297{
1298 /** Pointer to the next range - R3. */
1299 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1300 /** Pointer to the next range - R0. */
1301 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1302 /** Address of the range. */
1303 RTGCPHYS GCPhys;
1304 /** Address of the last byte in the range. */
1305 RTGCPHYS GCPhysLast;
1306 /** Size of the range. */
1307 RTGCPHYS cb;
1308 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1309 uint8_t fFlags;
1310 /** The saved state range ID. */
1311 uint8_t idSavedState;
1312 /** Alignment padding. */
1313 uint8_t au8Alignment[2];
1314 /** The size bits pvOriginal points to. */
1315 uint32_t cbOriginal;
1316 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1317 * This is used for strictness checks. */
1318 R3PTRTYPE(const void *) pvOriginal;
1319 /** The ROM description. */
1320 R3PTRTYPE(const char *) pszDesc;
1321#ifdef VBOX_WITH_PGM_NEM_MODE
1322 /** In simplified memory mode this provides alternate backing for shadowed ROMs.
1323 * - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1324 * - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1325 * - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1326 * - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1327 R3PTRTYPE(uint8_t *) pbR3Alternate;
1328 RTR3PTR pvAlignment2;
1329#endif
1330 /** The per page tracking structures. */
1331 PGMROMPAGE aPages[1];
1332} PGMROMRANGE;
1333/** Pointer to a ROM range. */
1334typedef PGMROMRANGE *PPGMROMRANGE;
1335
1336
1337/**
1338 * Live save per page data for an MMIO2 page.
1339 *
1340 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1341 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1342 * CRC-32 for detecting changes as well as special handling of zero pages. This
1343 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1344 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1345 * because of speed (2.5x and 6x slower).)
1346 *
1347 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1348 * save but normally is disabled. Since we can write monitor guest
1349 * accesses on our own, we only need this for host accesses. Shouldn't be
1350 * too difficult for DevVGA, VMMDev might be doable, the planned
1351 * networking fun will be fun since it involves ring-0.
1352 */
1353typedef struct PGMLIVESAVEMMIO2PAGE
1354{
1355 /** Set if the page is considered dirty. */
1356 bool fDirty;
1357 /** The number of scans this page has remained unchanged for.
1358 * Only updated for dirty pages. */
1359 uint8_t cUnchangedScans;
1360 /** Whether this page was zero at the last scan. */
1361 bool fZero;
1362 /** Alignment padding. */
1363 bool fReserved;
1364 /** CRC-32 for the first half of the page.
1365 * This is used together with u32CrcH2 to quickly detect changes in the page
1366 * during the non-final passes. */
1367 uint32_t u32CrcH1;
1368 /** CRC-32 for the second half of the page. */
1369 uint32_t u32CrcH2;
1370 /** SHA-1 for the saved page.
1371 * This is used in the final pass to skip pages without changes. */
1372 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1373} PGMLIVESAVEMMIO2PAGE;
1374/** Pointer to a live save status data for an MMIO2 page. */
1375typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1376
1377/**
1378 * A registered MMIO2 (= Device RAM) range.
1379 *
1380 * There are a few reason why we need to keep track of these registrations. One
1381 * of them is the deregistration & cleanup stuff, while another is that the
1382 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1383 * range list.
1384 *
1385 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1386 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1387 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1388 * overlap we will free all the existing RAM pages and put in the ram range
1389 * pages instead.
1390 */
1391typedef struct PGMREGMMIO2RANGE
1392{
1393 /** The owner of the range. (a device) */
1394 PPDMDEVINSR3 pDevInsR3;
1395 /** Pointer to the ring-3 mapping of the allocation. */
1396 RTR3PTR pvR3;
1397#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1398 /** Pointer to the ring-0 mapping of the allocation. */
1399 RTR0PTR pvR0;
1400#endif
1401 /** Pointer to the next range - R3. */
1402 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1403 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1404 uint16_t fFlags;
1405 /** The sub device number (internal PCI config (CFGM) number). */
1406 uint8_t iSubDev;
1407 /** The PCI region number. */
1408 uint8_t iRegion;
1409 /** The saved state range ID. */
1410 uint8_t idSavedState;
1411 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1412 uint8_t idMmio2;
1413 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1414#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1415 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1416#else
1417 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1418#endif
1419 /** The real size.
1420 * This may be larger than indicated by RamRange.cb if the range has been
1421 * reduced during saved state loading. */
1422 RTGCPHYS cbReal;
1423 /** Pointer to the physical handler for MMIO. */
1424 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1425 /** Live save per page tracking data for MMIO2. */
1426 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1427 /** The associated RAM range. */
1428 PGMRAMRANGE RamRange;
1429} PGMREGMMIO2RANGE;
1430AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1431/** Pointer to a MMIO2 or pre-registered MMIO range. */
1432typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1433
1434/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1435 * @{ */
1436/** Set if this is the first chunk in the MMIO2 range. */
1437#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1438/** Set if this is the last chunk in the MMIO2 range. */
1439#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1440/** Set if the whole range is mapped. */
1441#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1442/** Set if it's overlapping, clear if not. */
1443#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1444/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1445#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1446/** Set if the access handler is registered. */
1447#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1448/** Set if dirty page tracking is currently enabled. */
1449#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1450/** Set if there are dirty pages in the range. */
1451#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1452/** @} */
1453
1454
1455/** @name Internal MMIO2 constants.
1456 * @{ */
1457/** The maximum number of MMIO2 ranges. */
1458#define PGM_MMIO2_MAX_RANGES 32
1459/** The maximum number of pages in a MMIO2 range. */
1460#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1461/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1462#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1463/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1464#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1465/** Gets the MMIO2 page index from an MMIO2 page ID. */
1466#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1467/** @} */
1468
1469
1470
1471/**
1472 * PGMPhysRead/Write cache entry
1473 */
1474typedef struct PGMPHYSCACHEENTRY
1475{
1476 /** R3 pointer to physical page. */
1477 R3PTRTYPE(uint8_t *) pbR3;
1478 /** GC Physical address for cache entry */
1479 RTGCPHYS GCPhys;
1480#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1481 RTGCPHYS u32Padding0; /**< alignment padding. */
1482#endif
1483} PGMPHYSCACHEENTRY;
1484
1485/**
1486 * PGMPhysRead/Write cache to reduce REM memory access overhead
1487 */
1488typedef struct PGMPHYSCACHE
1489{
1490 /** Bitmap of valid cache entries */
1491 uint64_t aEntries;
1492 /** Cache entries */
1493 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1494} PGMPHYSCACHE;
1495
1496
1497/** @name Ring-3 page mapping TLBs
1498 * @{ */
1499
1500/** Pointer to an allocation chunk ring-3 mapping. */
1501typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1502/** Pointer to an allocation chunk ring-3 mapping pointer. */
1503typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1504
1505/**
1506 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1507 *
1508 * The primary tree (Core) uses the chunk id as key.
1509 */
1510typedef struct PGMCHUNKR3MAP
1511{
1512 /** The key is the chunk id. */
1513 AVLU32NODECORE Core;
1514 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1515 * selection. */
1516 uint32_t iLastUsed;
1517 /** The current reference count. */
1518 uint32_t volatile cRefs;
1519 /** The current permanent reference count. */
1520 uint32_t volatile cPermRefs;
1521 /** The mapping address. */
1522 void *pv;
1523} PGMCHUNKR3MAP;
1524
1525/**
1526 * Allocation chunk ring-3 mapping TLB entry.
1527 */
1528typedef struct PGMCHUNKR3MAPTLBE
1529{
1530 /** The chunk id. */
1531 uint32_t volatile idChunk;
1532#if HC_ARCH_BITS == 64
1533 uint32_t u32Padding; /**< alignment padding. */
1534#endif
1535 /** The chunk map. */
1536 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1537} PGMCHUNKR3MAPTLBE;
1538/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1539typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1540
1541/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1542 * @remark Must be a power of two value. */
1543#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1544
1545/**
1546 * Allocation chunk ring-3 mapping TLB.
1547 *
1548 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1549 * At first glance this might look kinda odd since AVL trees are
1550 * supposed to give the most optimal lookup times of all trees
1551 * due to their balancing. However, take a tree with 1023 nodes
1552 * in it, that's 10 levels, meaning that most searches has to go
1553 * down 9 levels before they find what they want. This isn't fast
1554 * compared to a TLB hit. There is the factor of cache misses,
1555 * and of course the problem with trees and branch prediction.
1556 * This is why we use TLBs in front of most of the trees.
1557 *
1558 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1559 * difficult when we switch to the new inlined AVL trees (from kStuff).
1560 */
1561typedef struct PGMCHUNKR3MAPTLB
1562{
1563 /** The TLB entries. */
1564 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1565} PGMCHUNKR3MAPTLB;
1566
1567/**
1568 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1569 * @returns Chunk TLB index.
1570 * @param idChunk The Chunk ID.
1571 */
1572#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1573
1574
1575/**
1576 * Ring-3 guest page mapping TLB entry.
1577 * @remarks used in ring-0 as well at the moment.
1578 */
1579typedef struct PGMPAGER3MAPTLBE
1580{
1581 /** Address of the page. */
1582 RTGCPHYS volatile GCPhys;
1583 /** The guest page. */
1584 R3PTRTYPE(PPGMPAGE) volatile pPage;
1585 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1586 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1587 /** The address */
1588 R3PTRTYPE(void *) volatile pv;
1589#if HC_ARCH_BITS == 32
1590 uint32_t u32Padding; /**< alignment padding. */
1591#endif
1592} PGMPAGER3MAPTLBE;
1593/** Pointer to an entry in the HC physical TLB. */
1594typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1595
1596
1597/** The number of entries in the ring-3 guest page mapping TLB.
1598 * @remarks The value must be a power of two. */
1599#define PGM_PAGER3MAPTLB_ENTRIES 256
1600
1601/**
1602 * Ring-3 guest page mapping TLB.
1603 * @remarks used in ring-0 as well at the moment.
1604 */
1605typedef struct PGMPAGER3MAPTLB
1606{
1607 /** The TLB entries. */
1608 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1609} PGMPAGER3MAPTLB;
1610/** Pointer to the ring-3 guest page mapping TLB. */
1611typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1612
1613/**
1614 * Calculates the index of the TLB entry for the specified guest page.
1615 * @returns Physical TLB index.
1616 * @param GCPhys The guest physical address.
1617 */
1618#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1619
1620/** @} */
1621
1622
1623/** @name Ring-0 page mapping TLB
1624 * @{ */
1625/**
1626 * Ring-0 guest page mapping TLB entry.
1627 */
1628typedef struct PGMPAGER0MAPTLBE
1629{
1630 /** Address of the page. */
1631 RTGCPHYS volatile GCPhys;
1632 /** The guest page. */
1633 R0PTRTYPE(PPGMPAGE) volatile pPage;
1634 /** The address */
1635 R0PTRTYPE(void *) volatile pv;
1636} PGMPAGER0MAPTLBE;
1637/** Pointer to an entry in the HC physical TLB. */
1638typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1639
1640
1641/** The number of entries in the ring-3 guest page mapping TLB.
1642 * @remarks The value must be a power of two. */
1643#define PGM_PAGER0MAPTLB_ENTRIES 256
1644
1645/**
1646 * Ring-3 guest page mapping TLB.
1647 * @remarks used in ring-0 as well at the moment.
1648 */
1649typedef struct PGMPAGER0MAPTLB
1650{
1651 /** The TLB entries. */
1652 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1653} PGMPAGER0MAPTLB;
1654/** Pointer to the ring-3 guest page mapping TLB. */
1655typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1656
1657/**
1658 * Calculates the index of the TLB entry for the specified guest page.
1659 * @returns Physical TLB index.
1660 * @param GCPhys The guest physical address.
1661 */
1662#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1663/** @} */
1664
1665
1666/** @name Context neutral page mapper TLB.
1667 *
1668 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1669 * code is writting in a kind of context neutral way. Time will show whether
1670 * this actually makes sense or not...
1671 *
1672 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1673 * context ends up using a global mapping cache on some platforms
1674 * (darwin).
1675 *
1676 * @{ */
1677/** @typedef PPGMPAGEMAPTLB
1678 * The page mapper TLB pointer type for the current context. */
1679/** @typedef PPGMPAGEMAPTLB
1680 * The page mapper TLB entry pointer type for the current context. */
1681/** @typedef PPGMPAGEMAPTLB
1682 * The page mapper TLB entry pointer pointer type for the current context. */
1683/** @def PGM_PAGEMAPTLB_ENTRIES
1684 * The number of TLB entries in the page mapper TLB for the current context. */
1685/** @def PGM_PAGEMAPTLB_IDX
1686 * Calculate the TLB index for a guest physical address.
1687 * @returns The TLB index.
1688 * @param GCPhys The guest physical address. */
1689/** @typedef PPGMPAGEMAP
1690 * Pointer to a page mapper unit for current context. */
1691/** @typedef PPPGMPAGEMAP
1692 * Pointer to a page mapper unit pointer for current context. */
1693#if defined(IN_RING0)
1694typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1695typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1696typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1697# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1698# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1699typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1700typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1701#else
1702typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1703typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1704typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1705# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1706# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1707typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1708typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1709#endif
1710/** @} */
1711
1712
1713/** @name PGM Pool Indexes.
1714 * Aka. the unique shadow page identifier.
1715 * @{ */
1716/** NIL page pool IDX. */
1717#define NIL_PGMPOOL_IDX 0
1718/** The first normal index. There used to be 5 fictive pages up front, now
1719 * there is only the NIL page. */
1720#define PGMPOOL_IDX_FIRST 1
1721/** The last valid index. (inclusive, 14 bits) */
1722#define PGMPOOL_IDX_LAST 0x3fff
1723/** @} */
1724
1725/** The NIL index for the parent chain. */
1726#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1727#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1728
1729/**
1730 * Node in the chain linking a shadowed page to it's parent (user).
1731 */
1732#pragma pack(1)
1733typedef struct PGMPOOLUSER
1734{
1735 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1736 uint16_t iNext;
1737 /** The user page index. */
1738 uint16_t iUser;
1739 /** Index into the user table. */
1740 uint32_t iUserTable;
1741} PGMPOOLUSER, *PPGMPOOLUSER;
1742typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1743#pragma pack()
1744
1745
1746/** The NIL index for the phys ext chain. */
1747#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1748/** The NIL pte index for a phys ext chain slot. */
1749#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1750
1751/**
1752 * Node in the chain of physical cross reference extents.
1753 * @todo Calling this an 'extent' is not quite right, find a better name.
1754 * @todo find out the optimal size of the aidx array
1755 */
1756#pragma pack(1)
1757typedef struct PGMPOOLPHYSEXT
1758{
1759 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1760 uint16_t iNext;
1761 /** Alignment. */
1762 uint16_t u16Align;
1763 /** The user page index. */
1764 uint16_t aidx[3];
1765 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1766 uint16_t apte[3];
1767} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1768typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1769#pragma pack()
1770
1771
1772/**
1773 * The kind of page that's being shadowed.
1774 */
1775typedef enum PGMPOOLKIND
1776{
1777 /** The virtual invalid 0 entry. */
1778 PGMPOOLKIND_INVALID = 0,
1779 /** The entry is free (=unused). */
1780 PGMPOOLKIND_FREE,
1781
1782 /** Shw: 32-bit page table; Gst: no paging. */
1783 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1784 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1785 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1786 /** Shw: 32-bit page table; Gst: 4MB page. */
1787 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1788 /** Shw: PAE page table; Gst: no paging. */
1789 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1790 /** Shw: PAE page table; Gst: 32-bit page table. */
1791 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1792 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1793 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1794 /** Shw: PAE page table; Gst: PAE page table. */
1795 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1796 /** Shw: PAE page table; Gst: 2MB page. */
1797 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1798
1799 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1800 PGMPOOLKIND_32BIT_PD,
1801 /** Shw: 32-bit page directory. Gst: no paging. */
1802 PGMPOOLKIND_32BIT_PD_PHYS,
1803 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1804 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1805 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1806 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1807 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1808 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1809 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1810 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1811 /** Shw: PAE page directory; Gst: PAE page directory. */
1812 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1813 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1814 PGMPOOLKIND_PAE_PD_PHYS,
1815
1816 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1817 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1818 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1819 PGMPOOLKIND_PAE_PDPT,
1820 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1821 PGMPOOLKIND_PAE_PDPT_PHYS,
1822
1823 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1824 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1825 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
1826 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1827 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1828 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1829 /** Shw: 64-bit page directory table; Gst: no paging. */
1830 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1831
1832 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1833 PGMPOOLKIND_64BIT_PML4,
1834
1835 /** Shw: EPT page directory pointer table; Gst: no paging. */
1836 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1837 /** Shw: EPT page directory table; Gst: no paging. */
1838 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1839 /** Shw: EPT page table; Gst: no paging. */
1840 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1841
1842 /** Shw: Root Nested paging table. */
1843 PGMPOOLKIND_ROOT_NESTED,
1844
1845 /** The last valid entry. */
1846 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1847} PGMPOOLKIND;
1848
1849/**
1850 * The access attributes of the page; only applies to big pages.
1851 */
1852typedef enum
1853{
1854 PGMPOOLACCESS_DONTCARE = 0,
1855 PGMPOOLACCESS_USER_RW,
1856 PGMPOOLACCESS_USER_R,
1857 PGMPOOLACCESS_USER_RW_NX,
1858 PGMPOOLACCESS_USER_R_NX,
1859 PGMPOOLACCESS_SUPERVISOR_RW,
1860 PGMPOOLACCESS_SUPERVISOR_R,
1861 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1862 PGMPOOLACCESS_SUPERVISOR_R_NX
1863} PGMPOOLACCESS;
1864
1865/**
1866 * The tracking data for a page in the pool.
1867 */
1868typedef struct PGMPOOLPAGE
1869{
1870 /** AVL node code with the (HC) physical address of this page. */
1871 AVLOHCPHYSNODECORE Core;
1872 /** Pointer to the R3 mapping of the page. */
1873 R3PTRTYPE(void *) pvPageR3;
1874 /** Pointer to the R0 mapping of the page. */
1875 R0PTRTYPE(void *) pvPageR0;
1876 /** The guest physical address. */
1877 RTGCPHYS GCPhys;
1878 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1879 uint8_t enmKind;
1880 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1881 uint8_t enmAccess;
1882 /** This supplements enmKind and enmAccess */
1883 bool fA20Enabled : 1;
1884
1885 /** Used to indicate that the page is zeroed. */
1886 bool fZeroed : 1;
1887 /** Used to indicate that a PT has non-global entries. */
1888 bool fSeenNonGlobal : 1;
1889 /** Used to indicate that we're monitoring writes to the guest page. */
1890 bool fMonitored : 1;
1891 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1892 * (All pages are in the age list.) */
1893 bool fCached : 1;
1894 /** This is used by the R3 access handlers when invoked by an async thread.
1895 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1896 bool volatile fReusedFlushPending : 1;
1897 /** Used to mark the page as dirty (write monitoring is temporarily
1898 * off). */
1899 bool fDirty : 1;
1900 bool fPadding1 : 1;
1901 bool fPadding2;
1902
1903 /** The index of this page. */
1904 uint16_t idx;
1905 /** The next entry in the list this page currently resides in.
1906 * It's either in the free list or in the GCPhys hash. */
1907 uint16_t iNext;
1908 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1909 uint16_t iUserHead;
1910 /** The number of present entries. */
1911 uint16_t cPresent;
1912 /** The first entry in the table which is present. */
1913 uint16_t iFirstPresent;
1914 /** The number of modifications to the monitored page. */
1915 uint16_t cModifications;
1916 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1917 uint16_t iModifiedNext;
1918 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1919 uint16_t iModifiedPrev;
1920 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1921 uint16_t iMonitoredNext;
1922 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1923 uint16_t iMonitoredPrev;
1924 /** The next page in the age list. */
1925 uint16_t iAgeNext;
1926 /** The previous page in the age list. */
1927 uint16_t iAgePrev;
1928 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
1929 uint8_t idxDirtyEntry;
1930
1931 /** @name Access handler statistics to determine whether the guest is
1932 * (re)initializing a page table.
1933 * @{ */
1934 RTGCPTR GCPtrLastAccessHandlerRip;
1935 RTGCPTR GCPtrLastAccessHandlerFault;
1936 uint64_t cLastAccessHandler;
1937 /** @} */
1938 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
1939 uint32_t volatile cLocked;
1940#if GC_ARCH_BITS == 64
1941 uint32_t u32Alignment3;
1942#endif
1943# ifdef VBOX_STRICT
1944 RTGCPTR GCPtrDirtyFault;
1945# endif
1946} PGMPOOLPAGE;
1947/** Pointer to a pool page. */
1948typedef PGMPOOLPAGE *PPGMPOOLPAGE;
1949/** Pointer to a const pool page. */
1950typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1951/** Pointer to a pool page pointer. */
1952typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
1953
1954
1955/** The hash table size. */
1956# define PGMPOOL_HASH_SIZE 0x40
1957/** The hash function. */
1958# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1959
1960
1961/**
1962 * The shadow page pool instance data.
1963 *
1964 * It's all one big allocation made at init time, except for the
1965 * pages that is. The user nodes follows immediately after the
1966 * page structures.
1967 */
1968typedef struct PGMPOOL
1969{
1970 /** The VM handle - R3 Ptr. */
1971 PVMR3 pVMR3;
1972 /** The VM handle - R0 Ptr. */
1973 R0PTRTYPE(PVMCC) pVMR0;
1974 /** The max pool size. This includes the special IDs. */
1975 uint16_t cMaxPages;
1976 /** The current pool size. */
1977 uint16_t cCurPages;
1978 /** The head of the free page list. */
1979 uint16_t iFreeHead;
1980 /* Padding. */
1981 uint16_t u16Padding;
1982 /** Head of the chain of free user nodes. */
1983 uint16_t iUserFreeHead;
1984 /** The number of user nodes we've allocated. */
1985 uint16_t cMaxUsers;
1986 /** The number of present page table entries in the entire pool. */
1987 uint32_t cPresent;
1988 /** Pointer to the array of user nodes - R3 pointer. */
1989 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1990 /** Pointer to the array of user nodes - R0 pointer. */
1991 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1992 /** Head of the chain of free phys ext nodes. */
1993 uint16_t iPhysExtFreeHead;
1994 /** The number of user nodes we've allocated. */
1995 uint16_t cMaxPhysExts;
1996 uint32_t u32Padding0b;
1997 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
1998 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1999 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2000 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2001 /** Hash table for GCPhys addresses. */
2002 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2003 /** The head of the age list. */
2004 uint16_t iAgeHead;
2005 /** The tail of the age list. */
2006 uint16_t iAgeTail;
2007 /** Set if the cache is enabled. */
2008 bool fCacheEnabled;
2009 /** Alignment padding. */
2010 bool afPadding1[3];
2011 /** Head of the list of modified pages. */
2012 uint16_t iModifiedHead;
2013 /** The current number of modified pages. */
2014 uint16_t cModifiedPages;
2015 /** Physical access handler type registration handle. */
2016 PGMPHYSHANDLERTYPE hAccessHandlerType;
2017 /** Next available slot (in aDirtyPages). */
2018 uint32_t idxFreeDirtyPage;
2019 /** Number of active dirty pages. */
2020 uint32_t cDirtyPages;
2021 /** Array of current dirty pgm pool page indices. */
2022 uint16_t aidxDirtyPages[16];
2023 /** Array running in parallel to aidxDirtyPages with the page data. */
2024 struct
2025 {
2026 uint64_t aPage[512];
2027 } aDirtyPages[16];
2028
2029 /** The number of pages currently in use. */
2030 uint16_t cUsedPages;
2031#ifdef VBOX_WITH_STATISTICS
2032 /** The high water mark for cUsedPages. */
2033 uint16_t cUsedPagesHigh;
2034 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2035 /** Profiling pgmPoolAlloc(). */
2036 STAMPROFILEADV StatAlloc;
2037 /** Profiling pgmR3PoolClearDoIt(). */
2038 STAMPROFILE StatClearAll;
2039 /** Profiling pgmR3PoolReset(). */
2040 STAMPROFILE StatR3Reset;
2041 /** Profiling pgmPoolFlushPage(). */
2042 STAMPROFILE StatFlushPage;
2043 /** Profiling pgmPoolFree(). */
2044 STAMPROFILE StatFree;
2045 /** Counting explicit flushes by PGMPoolFlushPage(). */
2046 STAMCOUNTER StatForceFlushPage;
2047 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2048 STAMCOUNTER StatForceFlushDirtyPage;
2049 /** Counting flushes for reused pages. */
2050 STAMCOUNTER StatForceFlushReused;
2051 /** Profiling time spent zeroing pages. */
2052 STAMPROFILE StatZeroPage;
2053 /** Profiling of pgmPoolTrackDeref. */
2054 STAMPROFILE StatTrackDeref;
2055 /** Profiling pgmTrackFlushGCPhysPT. */
2056 STAMPROFILE StatTrackFlushGCPhysPT;
2057 /** Profiling pgmTrackFlushGCPhysPTs. */
2058 STAMPROFILE StatTrackFlushGCPhysPTs;
2059 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2060 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2061 /** Number of times we've been out of user records. */
2062 STAMCOUNTER StatTrackFreeUpOneUser;
2063 /** Nr of flushed entries. */
2064 STAMCOUNTER StatTrackFlushEntry;
2065 /** Nr of updated entries. */
2066 STAMCOUNTER StatTrackFlushEntryKeep;
2067 /** Profiling deref activity related tracking GC physical pages. */
2068 STAMPROFILE StatTrackDerefGCPhys;
2069 /** Number of linear searches for a HCPhys in the ram ranges. */
2070 STAMCOUNTER StatTrackLinearRamSearches;
2071 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2072 STAMCOUNTER StamTrackPhysExtAllocFailures;
2073
2074 /** Profiling the RC/R0 \#PF access handler. */
2075 STAMPROFILE StatMonitorPfRZ;
2076 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2077 STAMPROFILE StatMonitorPfRZHandled;
2078 /** Times we've failed interpreting the instruction. */
2079 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2080 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2081 STAMPROFILE StatMonitorPfRZFlushPage;
2082 /** Times we've detected a page table reinit. */
2083 STAMCOUNTER StatMonitorPfRZFlushReinit;
2084 /** Counting flushes for pages that are modified too often. */
2085 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2086 /** Times we've detected fork(). */
2087 STAMCOUNTER StatMonitorPfRZFork;
2088 /** Times we've failed interpreting a patch code instruction. */
2089 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2090 /** Times we've failed interpreting a patch code instruction during flushing. */
2091 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2092 /** The number of times we've seen rep prefixes we can't handle. */
2093 STAMCOUNTER StatMonitorPfRZRepPrefix;
2094 /** Profiling the REP STOSD cases we've handled. */
2095 STAMPROFILE StatMonitorPfRZRepStosd;
2096
2097 /** Profiling the R0/RC regular access handler. */
2098 STAMPROFILE StatMonitorRZ;
2099 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2100 STAMPROFILE StatMonitorRZFlushPage;
2101 /** Per access size counts indexed by size minus 1, last for larger. */
2102 STAMCOUNTER aStatMonitorRZSizes[16+3];
2103 /** Missaligned access counts indexed by offset - 1. */
2104 STAMCOUNTER aStatMonitorRZMisaligned[7];
2105
2106 /** Nr of handled PT faults. */
2107 STAMCOUNTER StatMonitorRZFaultPT;
2108 /** Nr of handled PD faults. */
2109 STAMCOUNTER StatMonitorRZFaultPD;
2110 /** Nr of handled PDPT faults. */
2111 STAMCOUNTER StatMonitorRZFaultPDPT;
2112 /** Nr of handled PML4 faults. */
2113 STAMCOUNTER StatMonitorRZFaultPML4;
2114
2115 /** Profiling the R3 access handler. */
2116 STAMPROFILE StatMonitorR3;
2117 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2118 STAMPROFILE StatMonitorR3FlushPage;
2119 /** Per access size counts indexed by size minus 1, last for larger. */
2120 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2121 /** Missaligned access counts indexed by offset - 1. */
2122 STAMCOUNTER aStatMonitorR3Misaligned[7];
2123 /** Nr of handled PT faults. */
2124 STAMCOUNTER StatMonitorR3FaultPT;
2125 /** Nr of handled PD faults. */
2126 STAMCOUNTER StatMonitorR3FaultPD;
2127 /** Nr of handled PDPT faults. */
2128 STAMCOUNTER StatMonitorR3FaultPDPT;
2129 /** Nr of handled PML4 faults. */
2130 STAMCOUNTER StatMonitorR3FaultPML4;
2131
2132 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2133 STAMCOUNTER StatResetDirtyPages;
2134 /** Times we've called pgmPoolAddDirtyPage. */
2135 STAMCOUNTER StatDirtyPage;
2136 /** Times we've had to flush duplicates for dirty page management. */
2137 STAMCOUNTER StatDirtyPageDupFlush;
2138 /** Times we've had to flush because of overflow. */
2139 STAMCOUNTER StatDirtyPageOverFlowFlush;
2140
2141 /** The high water mark for cModifiedPages. */
2142 uint16_t cModifiedPagesHigh;
2143 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2144
2145 /** The number of cache hits. */
2146 STAMCOUNTER StatCacheHits;
2147 /** The number of cache misses. */
2148 STAMCOUNTER StatCacheMisses;
2149 /** The number of times we've got a conflict of 'kind' in the cache. */
2150 STAMCOUNTER StatCacheKindMismatches;
2151 /** Number of times we've been out of pages. */
2152 STAMCOUNTER StatCacheFreeUpOne;
2153 /** The number of cacheable allocations. */
2154 STAMCOUNTER StatCacheCacheable;
2155 /** The number of uncacheable allocations. */
2156 STAMCOUNTER StatCacheUncacheable;
2157#else
2158 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2159#endif
2160 /** Profiling PGMR0PoolGrow(). */
2161 STAMPROFILE StatGrow;
2162 /** The AVL tree for looking up a page by its HC physical address. */
2163 AVLOHCPHYSTREE HCPhysTree;
2164 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2165 /** Array of pages. (cMaxPages in length)
2166 * The Id is the index into thist array.
2167 */
2168 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2169} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2170AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2171AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2172AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2173#ifdef VBOX_WITH_STATISTICS
2174AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2175#endif
2176AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2177
2178
2179/** @def PGMPOOL_PAGE_2_PTR
2180 * Maps a pool page pool into the current context.
2181 *
2182 * @returns VBox status code.
2183 * @param a_pVM Pointer to the VM.
2184 * @param a_pPage The pool page.
2185 *
2186 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2187 * small page window employeed by that function. Be careful.
2188 * @remark There is no need to assert on the result.
2189 */
2190#if defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2191# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2192DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2193{
2194 RT_NOREF(pszCaller);
2195 AssertPtr(a_pPage);
2196 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2197 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2198 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2199 return a_pPage->CTX_SUFF(pvPage);
2200}
2201#else
2202# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2203#endif
2204
2205
2206/** @def PGMPOOL_PAGE_2_PTR_V2
2207 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2208 *
2209 * @returns VBox status code.
2210 * @param a_pVM Pointer to the VM.
2211 * @param a_pVCpu The current CPU.
2212 * @param a_pPage The pool page.
2213 *
2214 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2215 * small page window employeed by that function. Be careful.
2216 * @remark There is no need to assert on the result.
2217 */
2218#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2219
2220
2221/** @name Per guest page tracking data.
2222 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2223 * is to use more bits for it and split it up later on. But for now we'll play
2224 * safe and change as little as possible.
2225 *
2226 * The 16-bit word has two parts:
2227 *
2228 * The first 14-bit forms the @a idx field. It is either the index of a page in
2229 * the shadow page pool, or and index into the extent list.
2230 *
2231 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2232 * shadow page pool references to the page. If cRefs equals
2233 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2234 * (misnomer) table and not the shadow page pool.
2235 *
2236 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2237 * the 16-bit word.
2238 *
2239 * @{ */
2240/** The shift count for getting to the cRefs part. */
2241#define PGMPOOL_TD_CREFS_SHIFT 14
2242/** The mask applied after shifting the tracking data down by
2243 * PGMPOOL_TD_CREFS_SHIFT. */
2244#define PGMPOOL_TD_CREFS_MASK 0x3
2245/** The cRefs value used to indicate that the idx is the head of a
2246 * physical cross reference list. */
2247#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2248/** The shift used to get idx. */
2249#define PGMPOOL_TD_IDX_SHIFT 0
2250/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2251#define PGMPOOL_TD_IDX_MASK 0x3fff
2252/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2253 * simply too many mappings of this page. */
2254#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2255
2256/** @def PGMPOOL_TD_MAKE
2257 * Makes a 16-bit tracking data word.
2258 *
2259 * @returns tracking data.
2260 * @param cRefs The @a cRefs field. Must be within bounds!
2261 * @param idx The @a idx field. Must also be within bounds! */
2262#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2263
2264/** @def PGMPOOL_TD_GET_CREFS
2265 * Get the @a cRefs field from a tracking data word.
2266 *
2267 * @returns The @a cRefs field
2268 * @param u16 The tracking data word.
2269 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2270 * non-zero @a u16. */
2271#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2272
2273/** @def PGMPOOL_TD_GET_IDX
2274 * Get the @a idx field from a tracking data word.
2275 *
2276 * @returns The @a idx field
2277 * @param u16 The tracking data word. */
2278#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2279/** @} */
2280
2281
2282
2283/** @name A20 gate macros
2284 * @{ */
2285#define PGM_WITH_A20
2286#ifdef PGM_WITH_A20
2287# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2288# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2289# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2290 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2291# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2292#else
2293# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2294# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2295# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2296# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2297#endif
2298/** @} */
2299
2300
2301/**
2302 * Roots and anchors for trees and list employing self relative offsets as
2303 * pointers.
2304 *
2305 * When using self-relative offsets instead of pointers, the offsets needs to be
2306 * the same in all offsets. Thus the roots and anchors needs to live on the
2307 * hyper heap just like the nodes.
2308 */
2309typedef struct PGMTREES
2310{
2311 /** List of physical access handler types (offset pointers) of type
2312 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2313 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2314 /** Physical access handlers (AVL range+offsetptr tree). */
2315 AVLROGCPHYSTREE PhysHandlers;
2316} PGMTREES;
2317/** Pointer to PGM trees. */
2318typedef PGMTREES *PPGMTREES;
2319
2320
2321/**
2322 * Page fault guest state for the AMD64 paging mode.
2323 */
2324typedef struct PGMPTWALKCORE
2325{
2326 /** The guest virtual address that is being resolved by the walk
2327 * (input). */
2328 RTGCPTR GCPtr;
2329
2330 /** The guest physical address that is the result of the walk.
2331 * @remarks only valid if fSucceeded is set. */
2332 RTGCPHYS GCPhys;
2333
2334 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2335 bool fSucceeded;
2336 /** The level problem arrised at.
2337 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2338 * level 8. This is 0 on success. */
2339 uint8_t uLevel;
2340 /** Set if the page isn't present. */
2341 bool fNotPresent;
2342 /** Encountered a bad physical address. */
2343 bool fBadPhysAddr;
2344 /** Set if there was reserved bit violations. */
2345 bool fRsvdError;
2346 /** Set if it involves a big page (2/4 MB). */
2347 bool fBigPage;
2348 /** Set if it involves a gigantic page (1 GB). */
2349 bool fGigantPage;
2350 /** The effective X86_PTE_US flag for the address. */
2351 bool fEffectiveUS;
2352 /** The effective X86_PTE_RW flag for the address. */
2353 bool fEffectiveRW;
2354 /** The effective X86_PTE_NX flag for the address. */
2355 bool fEffectiveNX;
2356 bool afPadding1[2];
2357 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2358 * The NX bit is inverted and shifted down 63 places to bit 0. */
2359 uint32_t fEffective;
2360} PGMPTWALKCORE;
2361
2362/** @name PGMPTWALKCORE::fEffective bits.
2363 * @{ */
2364#if 0
2365/** Effective execute bit (!NX). */
2366#define PGMPTWALK_EFF_X UINT32_C(1)
2367/** Effective read+write access bit. */
2368#define PGMPTWALK_EFF_RW X86_PTE_RW
2369/** Effective user-mode access bit. */
2370#define PGMPTWALK_EFF_US X86_PTE_US
2371/** Effective write through cache bit. */
2372#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2373/** Effective cache disabled bit. */
2374#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2375/** Effective accessed bit. */
2376#define PGMPTWALK_EFF_A X86_PTE_A
2377/** The dirty bit of the final entry. */
2378#define PGMPTWALK_EFF_D X86_PTE_D
2379/** The PAT bit of the final entry. */
2380#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2381/** The global bit of the final entry. */
2382#define PGMPTWALK_EFF_G X86_PTE_G
2383#endif
2384/** Effective execute bit (!NX). */
2385#define PGM_BF_PTWALK_EFF_X_SHIFT 0
2386#define PGM_BF_PTWALK_EFF_X_MASK UINT32_C(0x00000001)
2387/** Effective read+write access bit. */
2388#define PGM_BF_PTWALK_EFF_RW_SHIFT 1
2389#define PGM_BF_PTWALK_EFF_RW_MASK UINT32_C(0x00000002)
2390/** Effective user-mode access bit. */
2391#define PGM_BF_PTWALK_EFF_US_SHIFT 2
2392#define PGM_BF_PTWALK_EFF_US_MASK UINT32_C(0x00000004)
2393/** Effective write through cache bit. */
2394#define PGM_BF_PTWALK_EFF_PWT_SHIFT 3
2395#define PGM_BF_PTWALK_EFF_PWT_MASK UINT32_C(0x00000008)
2396/** Effective cache disabled bit. */
2397#define PGM_BF_PTWALK_EFF_PCD_SHIFT 4
2398#define PGM_BF_PTWALK_EFF_PCD_MASK UINT32_C(0x00000010)
2399/** Effective accessed bit. */
2400#define PGM_BF_PTWALK_EFF_A_SHIFT 5
2401#define PGM_BF_PTWALK_EFF_A_MASK UINT32_C(0x00000020)
2402/** The dirty bit of the final entry. */
2403#define PGM_BF_PTWALK_EFF_D_SHIFT 6
2404#define PGM_BF_PTWALK_EFF_D_MASK UINT32_C(0x00000040)
2405/** The PAT bit of the final entry. */
2406#define PGM_BF_PTWALK_EFF_PAT_SHIFT 7
2407#define PGM_BF_PTWALK_EFF_PAT_MASK UINT32_C(0x00000080)
2408/** The global bit of the final entry. */
2409#define PGM_BF_PTWALK_EFF_G_SHIFT 8
2410#define PGM_BF_PTWALK_EFF_G_MASK UINT32_C(0x00000100)
2411/** Reserved (bits 11:9) unused. */
2412#define PGM_BF_PTWALK_EFF_RSVD_11_9_SHIFT 9
2413#define PGM_BF_PTWALK_EFF_RSVD_11_9_MASK UINT32_C(0x00000e00)
2414/** Effective read access bit - EPT only. */
2415#define PGM_BF_PTWALK_EFF_R_SHIFT 12
2416#define PGM_BF_PTWALK_EFF_R_MASK UINT32_C(0x00001000)
2417/** Effective write access bit - EPT only. */
2418#define PGM_BF_PTWALK_EFF_W_SHIFT 13
2419#define PGM_BF_PTWALK_EFF_W_MASK UINT32_C(0x00002000)
2420/** Effective execute access for supervisor-mode - EPT only. */
2421#define PGM_BF_PTWALK_EFF_X_SUPER_SHIFT 14
2422#define PGM_BF_PTWALK_EFF_X_SUPER_MASK UINT32_C(0x00004000)
2423/** Effective EPT memory type - EPT only. */
2424#define PGM_BF_PTWALK_EFF_MEMTYPE_SHIFT 15
2425#define PGM_BF_PTWALK_EFF_MEMTYPE_MASK UINT32_C(0x00038000)
2426/** Effective ignore PAT memory type - EPT only. */
2427#define PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT 18
2428#define PGM_BF_PTWALK_EFF_IGNORE_PAT_MASK UINT32_C(0x00040000)
2429/** Reserved (bits 21:19) unused. */
2430#define PGM_BF_PTWALK_EFF_RSVD_21_19_SHIFT 19
2431#define PGM_BF_PTWALK_EFF_RSVD_21_19_MASK UINT32_C(0x00380000)
2432/** Effective execute access for user-mode - EPT only. */
2433#define PGM_BF_PTWALK_EFF_X_USER_SHIFT 22
2434#define PGM_BF_PTWALK_EFF_X_USER_MASK UINT32_C(0x00400000)
2435/** Reserved (bits 31:23) - unused. */ /** @todo When implementing SUPER_SHW_STACK, Suppress \#VE put them in bits 24, 25 which corresponds to bit 12, 13 of EPT attributes. */
2436#define PGM_BF_PTWALK_EFF_RSVD_31_23_SHIFT 23
2437#define PGM_BF_PTWALK_EFF_RSVD_31_23_MASK UINT32_C(0xff800000)
2438RT_BF_ASSERT_COMPILE_CHECKS(PGM_BF_PTWALK_EFF_, UINT32_C(0), UINT32_MAX,
2439 (X, RW, US, PWT, PCD, A, D, PAT, G, RSVD_11_9, R, W, X_SUPER, MEMTYPE, IGNORE_PAT, RSVD_21_19,
2440 X_USER, RSVD_31_23));
2441
2442/** The bit count where the EPT specific bits begin. */
2443#define PGMPTWALK_EFF_EPT_ATTR_SHIFT PGM_BF_PTWALK_EFF_R_SHIFT
2444/** The mask of EPT bits (bits 31:ATTR_SHIFT). In the future we might choose to
2445 * use higher unused EPT bits for something else, in that case reduce this mask. */
2446#define PGMPTWALK_EFF_EPT_ATTR_MASK UINT32_C(0xfffff000)
2447
2448/* Verify bits match the regular PT bits. */
2449AssertCompile(PGM_BF_PTWALK_EFF_RW_SHIFT == X86_PTE_BIT_RW);
2450AssertCompile(PGM_BF_PTWALK_EFF_US_SHIFT == X86_PTE_BIT_US);
2451AssertCompile(PGM_BF_PTWALK_EFF_PWT_SHIFT == X86_PTE_BIT_PWT);
2452AssertCompile(PGM_BF_PTWALK_EFF_PCD_SHIFT == X86_PTE_BIT_PCD);
2453AssertCompile(PGM_BF_PTWALK_EFF_A_SHIFT == X86_PTE_BIT_A);
2454AssertCompile(PGM_BF_PTWALK_EFF_D_SHIFT == X86_PTE_BIT_D);
2455AssertCompile(PGM_BF_PTWALK_EFF_PAT_SHIFT == X86_PTE_BIT_PAT);
2456AssertCompile(PGM_BF_PTWALK_EFF_G_SHIFT == X86_PTE_BIT_G);
2457AssertCompile(PGM_BF_PTWALK_EFF_RW_MASK == X86_PTE_RW);
2458AssertCompile(PGM_BF_PTWALK_EFF_US_MASK == X86_PTE_US);
2459AssertCompile(PGM_BF_PTWALK_EFF_PWT_MASK == X86_PTE_PWT);
2460AssertCompile(PGM_BF_PTWALK_EFF_PCD_MASK == X86_PTE_PCD);
2461AssertCompile(PGM_BF_PTWALK_EFF_A_MASK == X86_PTE_A);
2462AssertCompile(PGM_BF_PTWALK_EFF_D_MASK == X86_PTE_D);
2463AssertCompile(PGM_BF_PTWALK_EFF_PAT_MASK == X86_PTE_PAT);
2464AssertCompile(PGM_BF_PTWALK_EFF_G_MASK == X86_PTE_G);
2465
2466/*
2467 * The following bits map 1:1 (left shifted by PGMPTWALK_EFF_EPT_ATTR_SHIFT bits) with
2468 * VMX EPT attribute bits because these are unique to EPT and fit within 32-bits:
2469 * - R, W, X_SUPER, MEMTYPE, IGNORE_PAT, X_USER.
2470 *
2471 * The following bits are moved to the regular PT bit positions because they already
2472 * exist for regular page tables:
2473 * - A, D.
2474 */
2475AssertCompile(PGM_BF_PTWALK_EFF_R_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_READ);
2476AssertCompile(PGM_BF_PTWALK_EFF_W_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_WRITE);
2477AssertCompile(PGM_BF_PTWALK_EFF_X_SUPER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_EXECUTE);
2478AssertCompile(PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_IGNORE_PAT);
2479AssertCompile(PGM_BF_PTWALK_EFF_X_USER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_USER_EXECUTE);
2480/** @} */
2481
2482
2483/**
2484 * Guest page table walk for the AMD64 mode.
2485 */
2486typedef struct PGMPTWALKGSTAMD64
2487{
2488 /** The common core. */
2489 PGMPTWALKCORE Core;
2490
2491 PX86PML4 pPml4;
2492 PX86PML4E pPml4e;
2493 X86PML4E Pml4e;
2494
2495 PX86PDPT pPdpt;
2496 PX86PDPE pPdpe;
2497 X86PDPE Pdpe;
2498
2499 PX86PDPAE pPd;
2500 PX86PDEPAE pPde;
2501 X86PDEPAE Pde;
2502
2503 PX86PTPAE pPt;
2504 PX86PTEPAE pPte;
2505 X86PTEPAE Pte;
2506} PGMPTWALKGSTAMD64;
2507/** Pointer to a AMD64 guest page table walk. */
2508typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2509/** Pointer to a const AMD64 guest page table walk. */
2510typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2511
2512#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2513/**
2514 * Guest page table walk for the EPT mode.
2515 */
2516typedef struct PGMPTWALKGSTEPT
2517{
2518 /** The common core. */
2519 PGMPTWALKCORE Core;
2520
2521 PEPTPML4 pPml4;
2522 PEPTPML4E pPml4e;
2523 EPTPML4E Pml4e;
2524
2525 PEPTPDPT pPdpt;
2526 PEPTPDPTE pPdpte;
2527 EPTPDPTE Pdpte;
2528
2529 PEPTPD pPd;
2530 PEPTPDE pPde;
2531 EPTPDE Pde;
2532
2533 PEPTPT pPt;
2534 PEPTPTE pPte;
2535 EPTPTE Pte;
2536} PGMPTWALKGSTEPT;
2537/** Pointer to an EPT guest page table walk. */
2538typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2539/** Pointer to a const EPT guest page table walk. */
2540typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2541#endif
2542
2543/**
2544 * Guest page table walk for the PAE mode.
2545 */
2546typedef struct PGMPTWALKGSTPAE
2547{
2548 /** The common core. */
2549 PGMPTWALKCORE Core;
2550
2551 PX86PDPT pPdpt;
2552 PX86PDPE pPdpe;
2553 X86PDPE Pdpe;
2554
2555 PX86PDPAE pPd;
2556 PX86PDEPAE pPde;
2557 X86PDEPAE Pde;
2558
2559 PX86PTPAE pPt;
2560 PX86PTEPAE pPte;
2561 X86PTEPAE Pte;
2562} PGMPTWALKGSTPAE;
2563/** Pointer to a PAE guest page table walk. */
2564typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2565/** Pointer to a const AMD64 guest page table walk. */
2566typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2567
2568/**
2569 * Guest page table walk for the 32-bit mode.
2570 */
2571typedef struct PGMPTWALKGST32BIT
2572{
2573 /** The common core. */
2574 PGMPTWALKCORE Core;
2575
2576 PX86PD pPd;
2577 PX86PDE pPde;
2578 X86PDE Pde;
2579
2580 PX86PT pPt;
2581 PX86PTE pPte;
2582 X86PTE Pte;
2583} PGMPTWALKGST32BIT;
2584/** Pointer to a 32-bit guest page table walk. */
2585typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2586/** Pointer to a const 32-bit guest page table walk. */
2587typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2588
2589/**
2590 * Which part of PGMPTWALKGST that is valid.
2591 */
2592typedef enum PGMPTWALKGSTTYPE
2593{
2594 /** Customary invalid 0 value. */
2595 PGMPTWALKGSTTYPE_INVALID = 0,
2596 /** PGMPTWALKGST::u.Amd64 is valid. */
2597 PGMPTWALKGSTTYPE_AMD64,
2598 /** PGMPTWALKGST::u.Pae is valid. */
2599 PGMPTWALKGSTTYPE_PAE,
2600 /** PGMPTWALKGST::u.Legacy is valid. */
2601 PGMPTWALKGSTTYPE_32BIT,
2602 /** PGMPTWALKGST::u.Ept is valid. */
2603 PGMPTWALKGSTTYPE_EPT,
2604 /** Customary 32-bit type hack. */
2605 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2606} PGMPTWALKGSTTYPE;
2607
2608/**
2609 * Combined guest page table walk result.
2610 */
2611typedef struct PGMPTWALKGST
2612{
2613 union
2614 {
2615 /** The page walker core - always valid. */
2616 PGMPTWALKCORE Core;
2617 /** The page walker for AMD64. */
2618 PGMPTWALKGSTAMD64 Amd64;
2619 /** The page walker for PAE (32-bit). */
2620 PGMPTWALKGSTPAE Pae;
2621 /** The page walker for 32-bit paging (called legacy due to C naming
2622 * convension). */
2623 PGMPTWALKGST32BIT Legacy;
2624#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2625 /** The page walker for EPT. */
2626 PGMPTWALKGSTEPT Ept;
2627#endif
2628 } u;
2629 /** Indicates which part of the union is valid. */
2630 PGMPTWALKGSTTYPE enmType;
2631} PGMPTWALKGST;
2632/** Pointer to a combined guest page table walk result. */
2633typedef PGMPTWALKGST *PPGMPTWALKGST;
2634/** Pointer to a read-only combined guest page table walk result. */
2635typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2636
2637
2638/** @name Paging mode macros
2639 * @{
2640 */
2641#ifdef IN_RING3
2642# define PGM_CTX(a,b) a##R3##b
2643# define PGM_CTX_STR(a,b) a "R3" b
2644# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2645#elif defined(IN_RING0)
2646# define PGM_CTX(a,b) a##R0##b
2647# define PGM_CTX_STR(a,b) a "R0" b
2648# define PGM_CTX_DECL(type) VMMDECL(type)
2649#else
2650# error "Not IN_RING3 or IN_RING0!"
2651#endif
2652
2653#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2654#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2655#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2656#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2657#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2658#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2659#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2660#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2661#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2662#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2663#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2664#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2665#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2666#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2667#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2668#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2669# define PGM_GST_NAME_EPT(name) PGM_CTX(pgm,GstEPT##name)
2670# define PGM_GST_NAME_RC_EPT_STR(name) "pgmRCGstEPT" #name
2671# define PGM_GST_NAME_R0_EPT_STR(name) "pgmR0GstEPT" #name
2672#endif
2673#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2674
2675#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2676#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2677#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2678#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2679#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2680#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2681#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2682#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2683#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2684#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2685#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2686#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2687#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2688#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2689#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2690#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2691#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2692#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2693#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2694#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2695#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2696#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2697#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2698#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2699#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2700
2701/* Shw_Gst */
2702#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2703#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2704#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2705#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2706#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2707#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2708#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2709#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2710#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2711#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2712#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2713#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2714#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2715#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2716#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2717#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2718#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2719#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2720#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2721#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2722#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2723#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2724#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2725#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2726#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2727#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2728#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2729#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2730#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2731#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2732# define PGM_BTH_NAME_EPT_EPT(name) PGM_CTX(pgm,BthEPTEPT##name)
2733#endif
2734#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2735#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2736#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2737#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2738#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2739
2740#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2741#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2742#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2743#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2744#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2745#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2746#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2747#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2748#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2749#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2750#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2751#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2752#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2753#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2754#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2755#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2756#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2757#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2758#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2759#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2760#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2761#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2762#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2763#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2764#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2765#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2766#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2767#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2768#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2769# define PGM_BTH_NAME_RC_EPT_EPT_STR(name) "pgmRCBthEPTEPT" #name
2770#endif
2771
2772#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2773#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2774#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2775#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2776#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2777#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2778#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2779#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2780#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2781#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2782#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2783#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2784#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2785#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2786#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2787#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2788#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2789#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2790#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2791#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2792#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2793#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2794#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2795#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2796#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2797#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2798#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2799#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2800#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2801#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2802# define PGM_BTH_NAME_R0_EPT_EPT_STR(name) "pgmR0BthEPTEPT" #name
2803#endif
2804
2805#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2806/** @} */
2807
2808
2809/**
2810 * Function pointers for guest paging.
2811 */
2812typedef struct PGMMODEDATAGST
2813{
2814 /** The guest mode type. */
2815 uint32_t uType;
2816 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2817 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2818 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2819 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2820#ifdef IN_RING3
2821 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2822#endif
2823} PGMMODEDATAGST;
2824
2825/** The length of g_aPgmGuestModeData. */
2826#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2827# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_EPT + 1)
2828#elif defined(VBOX_WITH_64_BITS_GUESTS)
2829# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2830#else
2831# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2832#endif
2833/** The guest mode data array. */
2834extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2835
2836
2837/**
2838 * Function pointers for shadow paging.
2839 */
2840typedef struct PGMMODEDATASHW
2841{
2842 /** The shadow mode type. */
2843 uint32_t uType;
2844 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2845 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2846 uint64_t fMask, uint32_t fOpFlags));
2847 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2848 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2849#ifdef IN_RING3
2850 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2851#endif
2852} PGMMODEDATASHW;
2853
2854/** The length of g_aPgmShadowModeData. */
2855#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2856/** The shadow mode data array. */
2857extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2858
2859
2860/**
2861 * Function pointers for guest+shadow paging.
2862 */
2863typedef struct PGMMODEDATABTH
2864{
2865 /** The shadow mode type. */
2866 uint32_t uShwType;
2867 /** The guest mode type. */
2868 uint32_t uGstType;
2869
2870 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2871 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2872 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2873 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2874 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3, bool fPdpesMapped));
2875 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2876 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2877#ifndef IN_RING3
2878 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2879#endif
2880#ifdef VBOX_STRICT
2881 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2882#endif
2883} PGMMODEDATABTH;
2884
2885/** The length of g_aPgmBothModeData. */
2886#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2887/** The guest+shadow mode data array. */
2888extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2889
2890
2891#ifdef VBOX_WITH_STATISTICS
2892/**
2893 * PGM statistics.
2894 */
2895typedef struct PGMSTATS
2896{
2897 /* R3 only: */
2898 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2899 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2900
2901 /* R3+RZ */
2902 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2903 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2904 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2905 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2906 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2907 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2908 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2909 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2910 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2911 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2912 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2913 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2914 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2915 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2916 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2917 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2918 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2919 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2920 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2921 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2922 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2923 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2924/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2925 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2926 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2927/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2928
2929 /* RC only: */
2930 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2931 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2932
2933 STAMCOUNTER StatRZPhysRead;
2934 STAMCOUNTER StatRZPhysReadBytes;
2935 STAMCOUNTER StatRZPhysWrite;
2936 STAMCOUNTER StatRZPhysWriteBytes;
2937 STAMCOUNTER StatR3PhysRead;
2938 STAMCOUNTER StatR3PhysReadBytes;
2939 STAMCOUNTER StatR3PhysWrite;
2940 STAMCOUNTER StatR3PhysWriteBytes;
2941 STAMCOUNTER StatRCPhysRead;
2942 STAMCOUNTER StatRCPhysReadBytes;
2943 STAMCOUNTER StatRCPhysWrite;
2944 STAMCOUNTER StatRCPhysWriteBytes;
2945
2946 STAMCOUNTER StatRZPhysSimpleRead;
2947 STAMCOUNTER StatRZPhysSimpleReadBytes;
2948 STAMCOUNTER StatRZPhysSimpleWrite;
2949 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2950 STAMCOUNTER StatR3PhysSimpleRead;
2951 STAMCOUNTER StatR3PhysSimpleReadBytes;
2952 STAMCOUNTER StatR3PhysSimpleWrite;
2953 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2954 STAMCOUNTER StatRCPhysSimpleRead;
2955 STAMCOUNTER StatRCPhysSimpleReadBytes;
2956 STAMCOUNTER StatRCPhysSimpleWrite;
2957 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2958
2959 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2960 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2961 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2962 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2963 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2964 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2965 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2966
2967 /** Time spent by the host OS for large page allocation. */
2968 STAMPROFILE StatAllocLargePage;
2969 /** Time spent clearing the newly allocated large pages. */
2970 STAMPROFILE StatClearLargePage;
2971 /** The number of times allocating a large pages takes more than the allowed period. */
2972 STAMCOUNTER StatLargePageOverflow;
2973 /** pgmPhysIsValidLargePage profiling - R3 */
2974 STAMPROFILE StatR3IsValidLargePage;
2975 /** pgmPhysIsValidLargePage profiling - RZ*/
2976 STAMPROFILE StatRZIsValidLargePage;
2977
2978 STAMPROFILE StatChunkAging;
2979 STAMPROFILE StatChunkFindCandidate;
2980 STAMPROFILE StatChunkUnmap;
2981 STAMPROFILE StatChunkMap;
2982} PGMSTATS;
2983#endif /* VBOX_WITH_STATISTICS */
2984
2985
2986/**
2987 * PGM Data (part of VM)
2988 */
2989typedef struct PGM
2990{
2991 /** @cfgm{/RamPreAlloc, boolean, false}
2992 * Indicates whether the base RAM should all be allocated before starting
2993 * the VM (default), or if it should be allocated when first written to.
2994 */
2995 bool fRamPreAlloc;
2996#ifdef VBOX_WITH_PGM_NEM_MODE
2997 /** Set if we're operating in NEM memory mode.
2998 *
2999 * NEM mode implies that memory is allocated in big chunks for each RAM range
3000 * rather than on demand page by page. Memory is also not locked and PGM has
3001 * therefore no physical addresses for them. Page sharing is out of the
3002 * question. Ballooning depends on the native execution engine, but probably
3003 * pointless as well. */
3004 bool fNemMode;
3005# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3006#else
3007# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3008#endif
3009 /** Indicates whether write monitoring is currently in use.
3010 * This is used to prevent conflicts between live saving and page sharing
3011 * detection. */
3012 bool fPhysWriteMonitoringEngaged;
3013 /** Set if the CPU has less than 52-bit physical address width.
3014 * This is used */
3015 bool fLessThan52PhysicalAddressBits;
3016 /** Set when nested paging is active.
3017 * This is meant to save calls to HMIsNestedPagingActive and let the
3018 * compilers optimize the code better. Whether we use nested paging or
3019 * not is something we find out during VMM initialization and we won't
3020 * change this later on. */
3021 bool fNestedPaging;
3022 /** We're not in a state which permits writes to guest memory.
3023 * (Only used in strict builds.) */
3024 bool fNoMorePhysWrites;
3025 /** @cfgm{/PageFusionAllowed, boolean, false}
3026 * Whether page fusion is allowed. */
3027 bool fPageFusionAllowed;
3028 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3029 * Whether PCI passthrough is enabled. */
3030 bool fPciPassthrough;
3031 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3032 uint8_t cMmio2Regions;
3033 /** Restore original ROM page content when resetting after loading state.
3034 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3035 * enables the VM to start using an updated ROM without requiring powering
3036 * down the VM, just rebooting or resetting it. */
3037 bool fRestoreRomPagesOnReset;
3038 /** Whether to automatically clear all RAM pages on reset. */
3039 bool fZeroRamPagesOnReset;
3040 /** Large page enabled flag. */
3041 bool fUseLargePages;
3042 /** Alignment padding. */
3043#ifndef VBOX_WITH_PGM_NEM_MODE
3044 bool afAlignment3[1];
3045#endif
3046 /** The host paging mode. (This is what SUPLib reports.) */
3047 SUPPAGINGMODE enmHostMode;
3048 bool afAlignment3b[2];
3049
3050 /** Generation ID for the RAM ranges. This member is incremented everytime
3051 * a RAM range is linked or unlinked. */
3052 uint32_t volatile idRamRangesGen;
3053
3054 /** Physical access handler type for ROM protection. */
3055 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3056 /** Physical access handler type for MMIO2 dirty page tracing. */
3057 PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3058
3059 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3060 RTGCPHYS GCPhys4MBPSEMask;
3061 /** Mask containing the invalid bits of a guest physical address.
3062 * @remarks this does not stop at bit 52. */
3063 RTGCPHYS GCPhysInvAddrMask;
3064
3065
3066 /** RAM range TLB for R3. */
3067 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3068 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3069 * This is sorted by physical address and contains no overlapping ranges. */
3070 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3071 /** Root of the RAM range search tree for ring-3. */
3072 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3073 /** PGM offset based trees - R3 Ptr. */
3074 R3PTRTYPE(PPGMTREES) pTreesR3;
3075 /** Caching the last physical handler we looked up in R3. */
3076 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3077 /** Shadow Page Pool - R3 Ptr. */
3078 R3PTRTYPE(PPGMPOOL) pPoolR3;
3079 /** Pointer to the list of ROM ranges - for R3.
3080 * This is sorted by physical address and contains no overlapping ranges. */
3081 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3082 /** Pointer to the list of MMIO2 ranges - for R3.
3083 * Registration order. */
3084 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3085 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3086 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3087
3088 /** RAM range TLB for R0. */
3089 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3090 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3091 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3092 /** Root of the RAM range search tree for ring-0. */
3093 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3094 /** PGM offset based trees - R0 Ptr. */
3095 R0PTRTYPE(PPGMTREES) pTreesR0;
3096 /** Caching the last physical handler we looked up in R0. */
3097 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3098 /** Shadow Page Pool - R0 Ptr. */
3099 R0PTRTYPE(PPGMPOOL) pPoolR0;
3100 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3101 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3102 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3103 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3104
3105 /** Hack: Number of deprecated page mapping locks taken by the current lock
3106 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3107 uint32_t cDeprecatedPageLocks;
3108 /** Alignment padding. */
3109 uint32_t au32Alignment2[1];
3110
3111 /** PGM critical section.
3112 * This protects the physical, ram ranges, and the page flag updating (some of
3113 * it anyway).
3114 */
3115 PDMCRITSECT CritSectX;
3116
3117 /**
3118 * Data associated with managing the ring-3 mappings of the allocation chunks.
3119 */
3120 struct
3121 {
3122 /** The chunk mapping TLB. */
3123 PGMCHUNKR3MAPTLB Tlb;
3124 /** The chunk tree, ordered by chunk id. */
3125 R3PTRTYPE(PAVLU32NODECORE) pTree;
3126#if HC_ARCH_BITS == 32
3127 uint32_t u32Alignment0;
3128#endif
3129 /** The number of mapped chunks. */
3130 uint32_t c;
3131 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3132 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3133 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3134 uint32_t cMax;
3135 /** The current time. This is incremented whenever a chunk is inserted. */
3136 uint32_t iNow;
3137 /** Alignment padding. */
3138 uint32_t au32Alignment1[3];
3139 } ChunkR3Map;
3140
3141 /** The page mapping TLB for ring-3. */
3142 PGMPAGER3MAPTLB PhysTlbR3;
3143 /** The page mapping TLB for ring-0. */
3144 PGMPAGER0MAPTLB PhysTlbR0;
3145
3146 /** @name The zero page.
3147 * @{ */
3148 /** The host physical address of the zero page. */
3149 RTHCPHYS HCPhysZeroPg;
3150 /** The ring-3 mapping of the zero page. */
3151 RTR3PTR pvZeroPgR3;
3152 /** The ring-0 mapping of the zero page. */
3153 RTR0PTR pvZeroPgR0;
3154 /** @}*/
3155
3156 /** @name The Invalid MMIO page.
3157 * This page is filled with 0xfeedface.
3158 * @{ */
3159 /** The host physical address of the invalid MMIO page. */
3160 RTHCPHYS HCPhysMmioPg;
3161 /** The host pysical address of the invalid MMIO page plus all invalid
3162 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3163 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3164 RTHCPHYS HCPhysInvMmioPg;
3165 /** The ring-3 mapping of the invalid MMIO page. */
3166 RTR3PTR pvMmioPgR3;
3167#if HC_ARCH_BITS == 32
3168 RTR3PTR R3PtrAlignment4;
3169#endif
3170 /** @} */
3171
3172
3173 /** The number of handy pages. */
3174 uint32_t cHandyPages;
3175
3176 /** The number of large handy pages. */
3177 uint32_t cLargeHandyPages;
3178
3179 /**
3180 * Array of handy pages.
3181 *
3182 * This array is used in a two way communication between pgmPhysAllocPage
3183 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3184 * an intermediary.
3185 *
3186 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3187 * (The current size of 32 pages, means 128 KB of handy memory.)
3188 */
3189 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3190
3191 /**
3192 * Array of large handy pages. (currently size 1)
3193 *
3194 * This array is used in a two way communication between pgmPhysAllocLargePage
3195 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3196 * an intermediary.
3197 */
3198 GMMPAGEDESC aLargeHandyPage[1];
3199
3200 /**
3201 * Live save data.
3202 */
3203 struct
3204 {
3205 /** Per type statistics. */
3206 struct
3207 {
3208 /** The number of ready pages. */
3209 uint32_t cReadyPages;
3210 /** The number of dirty pages. */
3211 uint32_t cDirtyPages;
3212 /** The number of ready zero pages. */
3213 uint32_t cZeroPages;
3214 /** The number of write monitored pages. */
3215 uint32_t cMonitoredPages;
3216 } Rom,
3217 Mmio2,
3218 Ram;
3219 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3220 uint32_t cIgnoredPages;
3221 /** Indicates that a live save operation is active. */
3222 bool fActive;
3223 /** Padding. */
3224 bool afReserved[2];
3225 /** The next history index. */
3226 uint8_t iDirtyPagesHistory;
3227 /** History of the total amount of dirty pages. */
3228 uint32_t acDirtyPagesHistory[64];
3229 /** Short term dirty page average. */
3230 uint32_t cDirtyPagesShort;
3231 /** Long term dirty page average. */
3232 uint32_t cDirtyPagesLong;
3233 /** The number of saved pages. This is used to get some kind of estimate of the
3234 * link speed so we can decide when we're done. It is reset after the first
3235 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3236 * zero pages. */
3237 uint64_t cSavedPages;
3238 /** The nanosecond timestamp when cSavedPages was 0. */
3239 uint64_t uSaveStartNS;
3240 /** Pages per second (for statistics). */
3241 uint32_t cPagesPerSecond;
3242 uint32_t cAlignment;
3243 } LiveSave;
3244
3245 /** @name Error injection.
3246 * @{ */
3247 /** Inject handy page allocation errors pretending we're completely out of
3248 * memory. */
3249 bool volatile fErrInjHandyPages;
3250 /** Padding. */
3251 bool afReserved[3];
3252 /** @} */
3253
3254 /** @name Release Statistics
3255 * @{ */
3256 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3257 uint32_t cPrivatePages; /**< The number of private pages. */
3258 uint32_t cSharedPages; /**< The number of shared pages. */
3259 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3260 uint32_t cZeroPages; /**< The number of zero backed pages. */
3261 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3262 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3263 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3264 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3265 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3266 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3267 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3268 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3269 uint32_t cLargePages; /**< The number of large pages. */
3270 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3271/* uint32_t aAlignment4[1]; */
3272
3273 /** The number of times we were forced to change the hypervisor region location. */
3274 STAMCOUNTER cRelocations;
3275
3276 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3277 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3278 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3279
3280 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3281 /** @} */
3282
3283#ifdef VBOX_WITH_STATISTICS
3284 /** These are optional statistics that used to be on the hyper heap. */
3285 PGMSTATS Stats;
3286#endif
3287} PGM;
3288#ifndef IN_TSTVMSTRUCTGC /* HACK */
3289AssertCompileMemberAlignment(PGM, CritSectX, 8);
3290AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3291AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3292AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3293AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3294AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3295AssertCompileMemberAlignment(PGM, cRelocations, 8);
3296#endif /* !IN_TSTVMSTRUCTGC */
3297/** Pointer to the PGM instance data. */
3298typedef PGM *PPGM;
3299
3300
3301#ifdef VBOX_WITH_STATISTICS
3302/**
3303 * Per CPU statistis for PGM (used to be on the heap).
3304 */
3305typedef struct PGMCPUSTATS
3306{
3307 /* Common */
3308 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3309 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3310
3311 /* R0 only: */
3312 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3313 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3314
3315 /* RZ only: */
3316 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3317 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3318 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3319 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3320 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3321 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3322 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3323 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3324 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3325 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3326 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3327 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3328 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3329 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3330 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3331 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3332 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3333 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3334 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3335 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3336 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3337 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3338 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3339 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3340 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3341 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3342 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3343 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3344 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3345 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3346 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3347 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3348 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3349 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3350 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3351 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3352 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3353 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3354 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3355 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3356 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3357 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3358 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3359 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3360 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3361 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3362 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3363 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3364 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3365 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3366 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3367 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3368 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3369 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3370 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3371 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3372 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3373 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3374 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3375 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3376 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3377 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3378 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3379 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3380 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3381 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3382 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3383 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3384 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3385 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3386
3387 /* HC - R3 and (maybe) R0: */
3388
3389 /* RZ & R3: */
3390 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3391 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3392 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3393 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3394 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3395 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3396 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3397 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3398 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3399 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3400 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3401 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3402 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3403 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3404 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3405 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3406 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3407 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3408 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3409 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3410 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3411 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3412 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3413 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3414 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3415 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3416 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3417 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3418 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3419 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3420 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3421 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3422 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3423 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3424 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3425 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3426 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3427 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3428 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3429 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3430 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3431 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3432 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3433 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3434 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3435 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3436 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3437
3438 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3439 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3440 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3441 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3442 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3443 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3444 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3445 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3446 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3447 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3448 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3449 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3450 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3451 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3452 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3453 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3454 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3455 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3456 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3457 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3458 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3459 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3460 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3461 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3462 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3463 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3464 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3465 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3466 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3467 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3468 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3469 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3470 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3471 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3472 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3473 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3474 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3475 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3476 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3477 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3478 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3479 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3480 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3481 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3482 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3483 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3484} PGMCPUSTATS;
3485#endif /* VBOX_WITH_STATISTICS */
3486
3487
3488/**
3489 * PGMCPU Data (part of VMCPU).
3490 */
3491typedef struct PGMCPU
3492{
3493 /** A20 gate mask.
3494 * Our current approach to A20 emulation is to let REM do it and don't bother
3495 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3496 * But whould need arrise, we'll subject physical addresses to this mask. */
3497 RTGCPHYS GCPhysA20Mask;
3498 /** A20 gate state - boolean! */
3499 bool fA20Enabled;
3500 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3501 bool fNoExecuteEnabled;
3502 /** Unused bits. */
3503 bool afUnused[2];
3504
3505 /** What needs syncing (PGM_SYNC_*).
3506 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3507 * PGMFlushTLB, and PGMR3Load. */
3508 uint32_t fSyncFlags;
3509
3510 /** The shadow paging mode. */
3511 PGMMODE enmShadowMode;
3512 /** The guest paging mode. */
3513 PGMMODE enmGuestMode;
3514 /** Guest mode data table index (PGM_TYPE_XXX). */
3515 uint8_t volatile idxGuestModeData;
3516 /** Shadow mode data table index (PGM_TYPE_XXX). */
3517 uint8_t volatile idxShadowModeData;
3518 /** Both mode data table index (complicated). */
3519 uint8_t volatile idxBothModeData;
3520 /** Alignment padding. */
3521 uint8_t abPadding[5];
3522
3523 /** The current physical address represented in the guest CR3 register. */
3524 RTGCPHYS GCPhysCR3;
3525
3526 /** @name 32-bit Guest Paging.
3527 * @{ */
3528 /** The guest's page directory, R3 pointer. */
3529 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3530 /** The guest's page directory, R0 pointer. */
3531 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3532 /** Mask containing the MBZ bits of a big page PDE. */
3533 uint32_t fGst32BitMbzBigPdeMask;
3534 /** Set if the page size extension (PSE) is enabled. */
3535 bool fGst32BitPageSizeExtension;
3536 /** Alignment padding. */
3537 bool afAlignment2[3];
3538 /** @} */
3539
3540 /** @name PAE Guest Paging.
3541 * @{ */
3542 /** The guest's page directory pointer table, R3 pointer. */
3543 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3544 /** The guest's page directory pointer table, R0 pointer. */
3545 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3546
3547 /** The guest's page directories, R3 pointers.
3548 * These are individual pointers and don't have to be adjacent.
3549 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3550 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3551 /** The guest's page directories, R0 pointers.
3552 * Same restrictions as apGstPaePDsR3. */
3553 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3554 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3555 RTGCPHYS aGCPhysGstPaePDs[4];
3556 /** The physical addresses of the monitored guest page directories (PAE). */
3557 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3558 /** Mask containing the MBZ PTE bits. */
3559 uint64_t fGstPaeMbzPteMask;
3560 /** Mask containing the MBZ PDE bits. */
3561 uint64_t fGstPaeMbzPdeMask;
3562 /** Mask containing the MBZ big page PDE bits. */
3563 uint64_t fGstPaeMbzBigPdeMask;
3564 /** Mask containing the MBZ PDPE bits. */
3565 uint64_t fGstPaeMbzPdpeMask;
3566 /** @} */
3567
3568 /** @name AMD64 Guest Paging.
3569 * @{ */
3570 /** The guest's page directory pointer table, R3 pointer. */
3571 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3572 /** The guest's page directory pointer table, R0 pointer. */
3573 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3574 /** Mask containing the MBZ PTE bits. */
3575 uint64_t fGstAmd64MbzPteMask;
3576 /** Mask containing the MBZ PDE bits. */
3577 uint64_t fGstAmd64MbzPdeMask;
3578 /** Mask containing the MBZ big page PDE bits. */
3579 uint64_t fGstAmd64MbzBigPdeMask;
3580 /** Mask containing the MBZ PDPE bits. */
3581 uint64_t fGstAmd64MbzPdpeMask;
3582 /** Mask containing the MBZ big page PDPE bits. */
3583 uint64_t fGstAmd64MbzBigPdpeMask;
3584 /** Mask containing the MBZ PML4E bits. */
3585 uint64_t fGstAmd64MbzPml4eMask;
3586 /** Mask containing the PDPE bits that we shadow. */
3587 uint64_t fGstAmd64ShadowedPdpeMask;
3588 /** Mask containing the PML4E bits that we shadow. */
3589 uint64_t fGstAmd64ShadowedPml4eMask;
3590 /** @} */
3591
3592 /** @name PAE and AMD64 Guest Paging.
3593 * @{ */
3594 /** Mask containing the PTE bits that we shadow. */
3595 uint64_t fGst64ShadowedPteMask;
3596 /** Mask containing the PDE bits that we shadow. */
3597 uint64_t fGst64ShadowedPdeMask;
3598 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3599 uint64_t fGst64ShadowedBigPdeMask;
3600 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3601 uint64_t fGst64ShadowedBigPde4PteMask;
3602 /** @} */
3603
3604 /** @name EPT Guest Paging.
3605 * @{ */
3606 /** The guest's page directory pointer table, R3 pointer. */
3607 R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3608 /** The guest's page directory pointer table, R0 pointer. */
3609 R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3610 /** The guest's EPT pointer (copy of virtual VMCS). */
3611 uint64_t uEptPtr;
3612 /** Mask containing the MBZ PTE bits. */
3613 uint64_t fGstEptMbzPteMask;
3614 /** Mask containing the MBZ PDE bits. */
3615 uint64_t fGstEptMbzPdeMask;
3616 /** Mask containing the MBZ big page (2M) PDE bits. */
3617 uint64_t fGstEptMbzBigPdeMask;
3618 /** Mask containing the MBZ PDPTE bits. */
3619 uint64_t fGstEptMbzPdpteMask;
3620 /** Mask containing the MBZ big page (1G) PDPTE bits. */
3621 uint64_t fGstEptMbzBigPdpteMask;
3622 /** Mask containing the MBZ PML4E bits. */
3623 uint64_t fGstEptMbzPml4eMask;
3624 /** Mask to determine whether an entry is present. */
3625 uint64_t fGstEptPresentMask;
3626 /** Mask containing the PML4E bits that we shadow. */
3627 uint64_t fGstEptShadowedPml4eMask;
3628 /** Mask containing the PDPE bits that we shadow. */
3629 uint64_t fGstEptShadowedPdpeMask;
3630 /** Mask containing the big page PDPE bits that we shadow. */
3631 uint64_t fGstEptShadowedBigPdpeMask;
3632 /** Mask containing the PDE bits that we shadow. */
3633 uint64_t fGstEptShadowedPdeMask;
3634 /** Mask containing the big page PDE bits that we shadow. */
3635 uint64_t fGstEptShadowedBigPdeMask;
3636 /** Mask containing the PTE bits that we shadow. */
3637 uint64_t fGstEptShadowedPteMask;
3638 /** @} */
3639
3640 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3641 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3642 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3643 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3644
3645 /** For saving stack space, the disassembler state is allocated here instead of
3646 * on the stack. */
3647 DISCPUSTATE DisState;
3648
3649 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3650 uint64_t cNetwareWp0Hacks;
3651
3652 /** Count the number of pgm pool access handler calls. */
3653 uint64_t cPoolAccessHandler;
3654
3655 /** @name Release Statistics
3656 * @{ */
3657 /** The number of times the guest has switched mode since last reset or statistics reset. */
3658 STAMCOUNTER cGuestModeChanges;
3659 /** The number of times the guest has switched mode since last reset or statistics reset. */
3660 STAMCOUNTER cA20Changes;
3661 /** @} */
3662
3663#ifdef VBOX_WITH_STATISTICS
3664 /** These are statistics that used to be on the hyper heap. */
3665 PGMCPUSTATS Stats;
3666#endif
3667} PGMCPU;
3668/** Pointer to the per-cpu PGM data. */
3669typedef PGMCPU *PPGMCPU;
3670
3671
3672/** @name PGM::fSyncFlags Flags
3673 * @note Was part of saved state a long time ago.
3674 * @{
3675 */
3676/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3677/** Always sync CR3. */
3678#define PGM_SYNC_ALWAYS RT_BIT(1)
3679/** Check guest mapping in SyncCR3. */
3680#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3681/** Clear the page pool (a light weight flush). */
3682#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3683#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3684/** @} */
3685
3686
3687/**
3688 * PGM GVMCPU instance data.
3689 */
3690typedef struct PGMR0PERVCPU
3691{
3692#ifdef VBOX_WITH_STATISTICS
3693 /** R0: Which statistic this \#PF should be attributed to. */
3694 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3695#endif
3696 uint64_t u64Dummy;
3697} PGMR0PERVCPU;
3698
3699
3700/**
3701 * PGM GVM instance data.
3702 */
3703typedef struct PGMR0PERVM
3704{
3705 /** @name PGM Pool related stuff.
3706 * @{ */
3707 /** Critical section for serializing pool growth. */
3708 RTCRITSECT PoolGrowCritSect;
3709 /** The memory objects for the pool pages. */
3710 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3711 /** The ring-3 mapping objects for the pool pages. */
3712 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3713 /** @} */
3714} PGMR0PERVM;
3715
3716RT_C_DECLS_BEGIN
3717
3718#if defined(VBOX_STRICT)
3719int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3720# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3721# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3722#else
3723int pgmLock(PVMCC pVM, bool fVoid);
3724# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3725# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3726#endif
3727void pgmUnlock(PVMCC pVM);
3728# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3729/**
3730 * Asserts that the caller owns the PDM lock.
3731 * This is the internal variant of PGMIsLockOwner.
3732 * @param a_pVM Pointer to the VM.
3733 */
3734#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3735/**
3736 * Asserts that the caller owns the PDM lock.
3737 * This is the internal variant of PGMIsLockOwner.
3738 * @param a_pVM Pointer to the VM.
3739 * @param a_pVCpu The current CPU handle.
3740 */
3741#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3742
3743int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3744 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3745int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3746int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3747int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3748int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3749void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3750bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3751void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3752DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3753DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3754int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3755
3756int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3757int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3758int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3759int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3760int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3761void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3762int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3763int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3764int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3765int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3766int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3767int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3768int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3769int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3770int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3771int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3772void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3773PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3774PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3775#ifndef IN_RING3
3776DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3777DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3778DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3779DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3780#endif
3781int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3782 PGMPAGETYPE enmNewType);
3783void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3784void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3785void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3786PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3787PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3788PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3789int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3790int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3791#ifdef VBOX_WITH_NATIVE_NEM
3792void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3793#endif
3794
3795#ifdef IN_RING3
3796void pgmR3PhysRelinkRamRanges(PVM pVM);
3797int pgmR3PhysRamPreAllocate(PVM pVM);
3798int pgmR3PhysRamReset(PVM pVM);
3799int pgmR3PhysRomReset(PVM pVM);
3800int pgmR3PhysRamZeroAll(PVM pVM);
3801int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3802int pgmR3PhysRamTerm(PVM pVM);
3803void pgmR3PhysRomTerm(PVM pVM);
3804void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3805
3806int pgmR3PoolInit(PVM pVM);
3807void pgmR3PoolRelocate(PVM pVM);
3808void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3809void pgmR3PoolReset(PVM pVM);
3810void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3811DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3812void pgmR3PoolWriteProtectPages(PVM pVM);
3813
3814#endif /* IN_RING3 */
3815int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3816 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3817void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3818void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3819int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3820void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3821PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3822PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3823int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3824int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3825bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3826void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3827int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3828void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3829uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3830void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3831void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3832void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3833PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3834#ifndef IN_RING3
3835DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3836#endif
3837
3838void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3839void pgmPoolResetDirtyPages(PVMCC pVM);
3840void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3841
3842int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3843int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3844void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3845
3846int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3847int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3848int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3849
3850int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3851int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3852int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3853int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3854#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3855int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3856#endif
3857int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3858int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3859
3860# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3861FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3862FNDBGCCMD pgmR3CmdShowSharedModules;
3863# endif
3864
3865void pgmLogState(PVM pVM);
3866
3867RT_C_DECLS_END
3868
3869/** @} */
3870
3871#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3872
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