VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 92170

Last change on this file since 92170 was 92170, checked in by vboxsync, 3 years ago

VMM/PGM,NEM: Let NEM handle dirty VRAM (MMIO2) page tracking. Saves lots of exits when using the VBoxVGA device or VMSVGA in non-VMSVGA mode. Added a 32-bit NEM field to the PGMRAMRANGE structure called uNemRange. bugref:10122
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1/* $Id: PGMInternal.h 92170 2021-11-01 22:06:25Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Check and skip global PDEs for non-global flushes
62 */
63#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
64
65/**
66 * Optimization for PAE page tables that are modified often
67 */
68//#if 0 /* disabled again while debugging */
69#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
70//#endif
71
72/**
73 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
74 */
75#define PGM_WITH_LARGE_PAGES
76
77/**
78 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
79 * VMX_EXIT_EPT_MISCONFIG.
80 */
81#define PGM_WITH_MMIO_OPTIMIZATIONS
82
83/**
84 * Sync N pages instead of a whole page table
85 */
86#define PGM_SYNC_N_PAGES
87
88/**
89 * Number of pages to sync during a page fault
90 *
91 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
92 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
93 *
94 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
95 * world switch overhead, so let's sync more.
96 */
97#ifdef IN_RING0
98/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
99 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
100 * but ~5% fewer faults.
101 */
102# define PGM_SYNC_NR_PAGES 32
103#else
104# define PGM_SYNC_NR_PAGES 8
105#endif
106
107/**
108 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
109 */
110#define PGM_MAX_PHYSCACHE_ENTRIES 64
111#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
112
113
114/** @def PGMPOOL_CFG_MAX_GROW
115 * The maximum number of pages to add to the pool in one go.
116 */
117#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
118
119/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
120 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
121 */
122#ifdef VBOX_STRICT
123# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
124#endif
125
126/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
127 * Enables the experimental lazy page allocation code. */
128#ifdef DOXYGEN_RUNNING
129# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130#endif
131
132/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
133 * Enables real write monitoring of pages, i.e. mapping them read-only and
134 * only making them writable when getting a write access \#PF. */
135#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
136
137/** @def VBOX_WITH_PGM_NEM_MODE
138 * Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
139 * details. */
140#ifdef DOXYGEN_RUNNING
141# define VBOX_WITH_PGM_NEM_MODE
142#endif
143
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** PGM specific bits in PML4 entries. */
155#define PGM_PML4_FLAGS 0
156/** PGM specific bits in PDPT entries. */
157#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
158/** @} */
159
160/** @name Page directory flags.
161 * These are placed in the three bits available for system programs in
162 * the page directory entries.
163 * @{ */
164/** Indicates the original entry was a big page.
165 * @remarks This is currently only used for statistics and can be recycled. */
166#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184
185/** @} */
186
187/** @name Defines used to indicate the shadow and guest paging in the templates.
188 * @{ */
189#define PGM_TYPE_REAL 1
190#define PGM_TYPE_PROT 2
191#define PGM_TYPE_32BIT 3
192#define PGM_TYPE_PAE 4
193#define PGM_TYPE_AMD64 5
194#define PGM_TYPE_NESTED_32BIT 6
195#define PGM_TYPE_NESTED_PAE 7
196#define PGM_TYPE_NESTED_AMD64 8
197#define PGM_TYPE_EPT 9
198#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
199#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
200#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
201/** @} */
202
203/** Macro for checking if the guest is using paging.
204 * @param uGstType PGM_TYPE_*
205 * @param uShwType PGM_TYPE_*
206 * @remark ASSUMES certain order of the PGM_TYPE_* values.
207 */
208#define PGM_WITH_PAGING(uGstType, uShwType) \
209 ( (uGstType) >= PGM_TYPE_32BIT \
210 && (uShwType) < PGM_TYPE_NESTED_32BIT)
211
212/** Macro for checking if the guest supports the NX bit.
213 * @param uGstType PGM_TYPE_*
214 * @param uShwType PGM_TYPE_*
215 * @remark ASSUMES certain order of the PGM_TYPE_* values.
216 */
217#define PGM_WITH_NX(uGstType, uShwType) \
218 ( (uGstType) >= PGM_TYPE_PAE \
219 && (uShwType) < PGM_TYPE_NESTED_32BIT)
220
221/** Macro for checking for nested.
222 * @param uType PGM_TYPE_*
223 */
224#define PGM_TYPE_IS_NESTED(uType) \
225 ( (uType) == PGM_TYPE_NESTED_32BIT \
226 || (uType) == PGM_TYPE_NESTED_PAE \
227 || (uType) == PGM_TYPE_NESTED_AMD64)
228
229/** Macro for checking for nested or EPT.
230 * @param uType PGM_TYPE_*
231 */
232#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
233 ( (uType) == PGM_TYPE_NESTED_32BIT \
234 || (uType) == PGM_TYPE_NESTED_PAE \
235 || (uType) == PGM_TYPE_NESTED_AMD64 \
236 || (uType) == PGM_TYPE_EPT)
237
238
239
240/** @def PGM_HCPHYS_2_PTR
241 * Maps a HC physical page pool address to a virtual address.
242 *
243 * @returns VBox status code.
244 * @param pVM The cross context VM structure.
245 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
246 * @param HCPhys The HC physical address to map to a virtual one.
247 * @param ppv Where to store the virtual address. No need to cast
248 * this.
249 *
250 * @remark There is no need to assert on the result.
251 */
252#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
253
254/** @def PGM_GCPHYS_2_PTR_V2
255 * Maps a GC physical page address to a virtual address.
256 *
257 * @returns VBox status code.
258 * @param pVM The cross context VM structure.
259 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
260 * @param GCPhys The GC physical address to map to a virtual one.
261 * @param ppv Where to store the virtual address. No need to cast this.
262 *
263 * @remark Use with care as we don't have so much dynamic mapping space in
264 * ring-0 on 32-bit darwin and in RC.
265 * @remark There is no need to assert on the result.
266 */
267#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
268 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
269
270/** @def PGM_GCPHYS_2_PTR
271 * Maps a GC physical page address to a virtual address.
272 *
273 * @returns VBox status code.
274 * @param pVM The cross context VM structure.
275 * @param GCPhys The GC physical address to map to a virtual one.
276 * @param ppv Where to store the virtual address. No need to cast this.
277 *
278 * @remark Use with care as we don't have so much dynamic mapping space in
279 * ring-0 on 32-bit darwin and in RC.
280 * @remark There is no need to assert on the result.
281 */
282#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
283
284/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
285 * Maps a GC physical page address to a virtual address.
286 *
287 * @returns VBox status code.
288 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
289 * @param GCPhys The GC physical address to map to a virtual one.
290 * @param ppv Where to store the virtual address. No need to cast this.
291 *
292 * @remark Use with care as we don't have so much dynamic mapping space in
293 * ring-0 on 32-bit darwin and in RC.
294 * @remark There is no need to assert on the result.
295 */
296#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
297
298/** @def PGM_GCPHYS_2_PTR_EX
299 * Maps a unaligned GC physical page address to a virtual address.
300 *
301 * @returns VBox status code.
302 * @param pVM The cross context VM structure.
303 * @param GCPhys The GC physical address to map to a virtual one.
304 * @param ppv Where to store the virtual address. No need to cast this.
305 *
306 * @remark Use with care as we don't have so much dynamic mapping space in
307 * ring-0 on 32-bit darwin and in RC.
308 * @remark There is no need to assert on the result.
309 */
310#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
312
313/** @def PGM_DYNMAP_UNUSED_HINT
314 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
315 * is no longer used.
316 *
317 * For best effect only apply this to the page that was mapped most recently.
318 *
319 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
320 * @param pvPage The pool page.
321 */
322#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
323
324/** @def PGM_DYNMAP_UNUSED_HINT_VM
325 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
326 * is no longer used.
327 *
328 * For best effect only apply this to the page that was mapped most recently.
329 *
330 * @param pVM The cross context VM structure.
331 * @param pvPage The pool page.
332 */
333#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
334
335
336/** @def PGM_INVL_PG
337 * Invalidates a page.
338 *
339 * @param pVCpu The cross context virtual CPU structure.
340 * @param GCVirt The virtual address of the page to invalidate.
341 */
342#ifdef IN_RING0
343# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
344#elif defined(IN_RING3)
345# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
346#else
347# error "Not IN_RING0 or IN_RING3!"
348#endif
349
350/** @def PGM_INVL_PG_ALL_VCPU
351 * Invalidates a page on all VCPUs
352 *
353 * @param pVM The cross context VM structure.
354 * @param GCVirt The virtual address of the page to invalidate.
355 */
356#ifdef IN_RING0
357# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_BIG_PG
363 * Invalidates a 4MB page directory entry.
364 *
365 * @param pVCpu The cross context virtual CPU structure.
366 * @param GCVirt The virtual address within the page directory to invalidate.
367 */
368#ifdef IN_RING0
369# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
370#else
371# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
372#endif
373
374/** @def PGM_INVL_VCPU_TLBS()
375 * Invalidates the TLBs of the specified VCPU
376 *
377 * @param pVCpu The cross context virtual CPU structure.
378 */
379#ifdef IN_RING0
380# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
381#else
382# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
383#endif
384
385/** @def PGM_INVL_ALL_VCPU_TLBS()
386 * Invalidates the TLBs of all VCPUs
387 *
388 * @param pVM The cross context VM structure.
389 */
390#ifdef IN_RING0
391# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
392#else
393# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
394#endif
395
396
397/** @name Safer Shadow PAE PT/PTE
398 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
399 * present.
400 *
401 * @{
402 */
403#if 1
404/**
405 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
406 * invalid entries for present.
407 * @sa X86PTEPAE.
408 */
409typedef union PGMSHWPTEPAE
410{
411 /** Unsigned integer view */
412 X86PGPAEUINT uCareful;
413 /* Not other views. */
414} PGMSHWPTEPAE;
415
416# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
417# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
418# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
419# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
420# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
421# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
422# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
423# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
424# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
425# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
426# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
427# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
428# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
429# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
430# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
431# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
432
433/**
434 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
435 * invalid entries for present.
436 * @sa X86PTPAE.
437 */
438typedef struct PGMSHWPTPAE
439{
440 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
441} PGMSHWPTPAE;
442
443#else
444typedef X86PTEPAE PGMSHWPTEPAE;
445typedef X86PTPAE PGMSHWPTPAE;
446# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
447# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
448# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
449# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
450# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
451# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
452# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
453# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
454# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
455# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
456# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
457# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
458# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
459# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
460# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
461# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
462
463#endif
464
465/** Pointer to a shadow PAE PTE. */
466typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
467/** Pointer to a const shadow PAE PTE. */
468typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
469
470/** Pointer to a shadow PAE page table. */
471typedef PGMSHWPTPAE *PPGMSHWPTPAE;
472/** Pointer to a const shadow PAE page table. */
473typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
474/** @} */
475
476
477/**
478 * Physical page access handler type registration.
479 */
480typedef struct PGMPHYSHANDLERTYPEINT
481{
482 /** Number of references. */
483 uint32_t volatile cRefs;
484 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
485 uint32_t u32Magic;
486 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
487 RTLISTOFF32NODE ListNode;
488 /** The kind of accesses we're handling. */
489 PGMPHYSHANDLERKIND enmKind;
490 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
491 uint8_t uState;
492 /** Whether to keep the PGM lock when calling the handler. */
493 bool fKeepPgmLock;
494 bool afPadding[2];
495 /** Pointer to R3 callback function. */
496 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
497 /** Pointer to R0 callback function. */
498 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
499 /** Pointer to R0 callback function for \#PFs. */
500 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
501 /** Description / Name. For easing debugging. */
502 R3PTRTYPE(const char *) pszDesc;
503} PGMPHYSHANDLERTYPEINT;
504/** Pointer to a physical access handler type registration. */
505typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
506/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
507#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
508/** Magic value for the physical handler callbacks. */
509#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
510
511/**
512 * Converts a handle to a pointer.
513 * @returns PPGMPHYSHANDLERTYPEINT
514 * @param a_pVM The cross context VM structure.
515 * @param a_hType Physical access handler type handle.
516 */
517#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
518
519
520/**
521 * Physical page access handler structure.
522 *
523 * This is used to keep track of physical address ranges
524 * which are being monitored in some kind of way.
525 */
526typedef struct PGMPHYSHANDLER
527{
528 AVLROGCPHYSNODECORE Core;
529 /** Number of pages to update. */
530 uint32_t cPages;
531 /** Set if we have pages that have been aliased. */
532 uint32_t cAliasedPages;
533 /** Set if we have pages that have temporarily been disabled. */
534 uint32_t cTmpOffPages;
535 /** Registered handler type handle (heap offset). */
536 PGMPHYSHANDLERTYPE hType;
537 /** User argument for R3 handlers. */
538 R3PTRTYPE(void *) pvUserR3;
539 /** User argument for R0 handlers. */
540 R0PTRTYPE(void *) pvUserR0;
541 /** Description / Name. For easing debugging. */
542 R3PTRTYPE(const char *) pszDesc;
543#ifdef VBOX_WITH_STATISTICS
544 /** Profiling of this handler. */
545 STAMPROFILE Stat;
546#endif
547} PGMPHYSHANDLER;
548/** Pointer to a physical page access handler structure. */
549typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
550
551/**
552 * Gets the type record for a physical handler (no reference added).
553 * @returns PPGMPHYSHANDLERTYPEINT
554 * @param a_pVM The cross context VM structure.
555 * @param a_pPhysHandler Pointer to the physical handler structure
556 * (PGMPHYSHANDLER).
557 */
558#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
559
560
561/**
562 * A Physical Guest Page tracking structure.
563 *
564 * The format of this structure is complicated because we have to fit a lot
565 * of information into as few bits as possible. The format is also subject
566 * to change (there is one coming up soon). Which means that for we'll be
567 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
568 * accesses to the structure.
569 */
570typedef union PGMPAGE
571{
572 /** Structured view. */
573 struct
574 {
575 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
576 uint64_t u2HandlerPhysStateY : 2;
577 /** 3:2 - Paging structure needed to map the page
578 * (PGM_PAGE_PDE_TYPE_*). */
579 uint64_t u2PDETypeY : 2;
580 /** 4 - Unused (was used by FTE for dirty tracking). */
581 uint64_t fUnused1 : 1;
582 /** 5 - Flag indicating that a write monitored page was written to
583 * when set. */
584 uint64_t fWrittenToY : 1;
585 /** 7:6 - Unused. */
586 uint64_t u2Unused0 : 2;
587 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
588 uint64_t u2Unused1 : 2;
589 /** 11:10 - NEM state bits. */
590 uint64_t u2NemStateY : 2;
591 /** 12:48 - The host physical frame number (shift left to get the
592 * address). */
593 uint64_t HCPhysFN : 36;
594 /** 50:48 - The page state. */
595 uint64_t uStateY : 3;
596 /** 51:53 - The page type (PGMPAGETYPE). */
597 uint64_t uTypeY : 3;
598 /** 63:54 - PTE index for usage tracking (page pool). */
599 uint64_t u10PteIdx : 10;
600
601 /** The GMM page ID.
602 * @remarks In the current implementation, MMIO2 and pages aliased to
603 * MMIO2 pages will be exploiting this field to calculate the
604 * ring-3 mapping address corresponding to the page.
605 * Later we may consider including MMIO2 management into GMM. */
606 uint32_t idPage;
607 /** Usage tracking (page pool). */
608 uint16_t u16TrackingY;
609 /** The number of read locks on this page. */
610 uint8_t cReadLocksY;
611 /** The number of write locks on this page. */
612 uint8_t cWriteLocksY;
613 } s;
614
615 /** 64-bit integer view. */
616 uint64_t au64[2];
617 /** 16-bit view. */
618 uint32_t au32[4];
619 /** 16-bit view. */
620 uint16_t au16[8];
621 /** 8-bit view. */
622 uint8_t au8[16];
623} PGMPAGE;
624AssertCompileSize(PGMPAGE, 16);
625/** Pointer to a physical guest page. */
626typedef PGMPAGE *PPGMPAGE;
627/** Pointer to a const physical guest page. */
628typedef const PGMPAGE *PCPGMPAGE;
629/** Pointer to a physical guest page pointer. */
630typedef PPGMPAGE *PPPGMPAGE;
631
632
633/**
634 * Clears the page structure.
635 * @param a_pPage Pointer to the physical guest page tracking structure.
636 */
637#define PGM_PAGE_CLEAR(a_pPage) \
638 do { \
639 (a_pPage)->au64[0] = 0; \
640 (a_pPage)->au64[1] = 0; \
641 } while (0)
642
643/**
644 * Initializes the page structure.
645 * @param a_pPage Pointer to the physical guest page tracking structure.
646 * @param a_HCPhys The host physical address of the page.
647 * @param a_idPage The (GMM) page ID of the page.
648 * @param a_uType The page type (PGMPAGETYPE).
649 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
650 */
651#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
652 do { \
653 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
654 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
655 (a_pPage)->au64[0] = SetHCPhysTmp; \
656 (a_pPage)->au64[1] = 0; \
657 (a_pPage)->s.idPage = (a_idPage); \
658 (a_pPage)->s.uStateY = (a_uState); \
659 (a_pPage)->s.uTypeY = (a_uType); \
660 } while (0)
661
662/**
663 * Initializes the page structure of a ZERO page.
664 * @param a_pPage Pointer to the physical guest page tracking structure.
665 * @param a_pVM The VM handle (for getting the zero page address).
666 * @param a_uType The page type (PGMPAGETYPE).
667 */
668#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
669 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
670
671
672/** @name The Page state, PGMPAGE::uStateY.
673 * @{ */
674/** The zero page.
675 * This is a per-VM page that's never ever mapped writable. */
676#define PGM_PAGE_STATE_ZERO 0U
677/** A allocated page.
678 * This is a per-VM page allocated from the page pool (or wherever
679 * we get MMIO2 pages from if the type is MMIO2).
680 */
681#define PGM_PAGE_STATE_ALLOCATED 1U
682/** A allocated page that's being monitored for writes.
683 * The shadow page table mappings are read-only. When a write occurs, the
684 * fWrittenTo member is set, the page remapped as read-write and the state
685 * moved back to allocated. */
686#define PGM_PAGE_STATE_WRITE_MONITORED 2U
687/** The page is shared, aka. copy-on-write.
688 * This is a page that's shared with other VMs. */
689#define PGM_PAGE_STATE_SHARED 3U
690/** The page is ballooned, so no longer available for this VM. */
691#define PGM_PAGE_STATE_BALLOONED 4U
692/** @} */
693
694
695/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
696#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
697# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
698#else
699# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
700#endif
701
702/**
703 * Gets the page state.
704 * @returns page state (PGM_PAGE_STATE_*).
705 * @param a_pPage Pointer to the physical guest page tracking structure.
706 *
707 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
708 * builds.
709 */
710#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
711#if defined(__GNUC__) && defined(VBOX_STRICT)
712# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
713#else
714# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
715#endif
716
717/**
718 * Sets the page state.
719 * @param a_pVM The VM handle, only used for lock ownership assertions.
720 * @param a_pPage Pointer to the physical guest page tracking structure.
721 * @param a_uState The new page state.
722 */
723#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
724 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
725
726
727/**
728 * Gets the host physical address of the guest page.
729 * @returns host physical address (RTHCPHYS).
730 * @param a_pPage Pointer to the physical guest page tracking structure.
731 *
732 * @remarks In strict builds on gcc platforms, this macro will make some ugly
733 * assumption about a valid pVM variable/parameter being in the
734 * current context. It will use this pVM variable to assert that the
735 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
736 * pVM is not around.
737 */
738#if 0
739# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
740# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
741#else
742# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
743# if defined(__GNUC__) && defined(VBOX_STRICT)
744# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
745# else
746# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
747# endif
748#endif
749
750/**
751 * Sets the host physical address of the guest page.
752 *
753 * @param a_pVM The VM handle, only used for lock ownership assertions.
754 * @param a_pPage Pointer to the physical guest page tracking structure.
755 * @param a_HCPhys The new host physical address.
756 */
757#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
758 do { \
759 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
760 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
761 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
762 PGM_PAGE_ASSERT_LOCK(a_pVM); \
763 } while (0)
764
765/**
766 * Get the Page ID.
767 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
768 * @param a_pPage Pointer to the physical guest page tracking structure.
769 */
770#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
771
772/**
773 * Sets the Page ID.
774 * @param a_pVM The VM handle, only used for lock ownership assertions.
775 * @param a_pPage Pointer to the physical guest page tracking structure.
776 * @param a_idPage The new page ID.
777 */
778#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
779 do { \
780 (a_pPage)->s.idPage = (a_idPage); \
781 PGM_PAGE_ASSERT_LOCK(a_pVM); \
782 } while (0)
783
784/**
785 * Get the Chunk ID.
786 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
787 * @param a_pPage Pointer to the physical guest page tracking structure.
788 */
789#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
790
791/**
792 * Get the index of the page within the allocation chunk.
793 * @returns The page index.
794 * @param a_pPage Pointer to the physical guest page tracking structure.
795 */
796#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
797
798/**
799 * Gets the page type.
800 * @returns The page type.
801 * @param a_pPage Pointer to the physical guest page tracking structure.
802 *
803 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
804 * builds.
805 */
806#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
807#if defined(__GNUC__) && defined(VBOX_STRICT)
808# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
809#else
810# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
811#endif
812
813/**
814 * Sets the page type.
815 *
816 * @param a_pVM The VM handle, only used for lock ownership assertions.
817 * @param a_pPage Pointer to the physical guest page tracking structure.
818 * @param a_enmType The new page type (PGMPAGETYPE).
819 */
820#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
821 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
822
823/**
824 * Gets the page table index
825 * @returns The page table index.
826 * @param a_pPage Pointer to the physical guest page tracking structure.
827 */
828#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
829
830/**
831 * Sets the page table index.
832 * @param a_pVM The VM handle, only used for lock ownership assertions.
833 * @param a_pPage Pointer to the physical guest page tracking structure.
834 * @param a_iPte New page table index.
835 */
836#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
837 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
838
839/**
840 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
841 * @returns true/false.
842 * @param a_pPage Pointer to the physical guest page tracking structure.
843 */
844#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
845
846/**
847 * Checks if the page is marked for MMIO, including both aliases.
848 * @returns true/false.
849 * @param a_pPage Pointer to the physical guest page tracking structure.
850 */
851#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
852 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
853 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
854 )
855
856/**
857 * Checks if the page is marked for MMIO, including special aliases.
858 * @returns true/false.
859 * @param a_pPage Pointer to the physical guest page tracking structure.
860 */
861#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
862 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
863
864/**
865 * Checks if the page is a special aliased MMIO page.
866 * @returns true/false.
867 * @param a_pPage Pointer to the physical guest page tracking structure.
868 */
869#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
870
871/**
872 * Checks if the page is backed by the ZERO page.
873 * @returns true/false.
874 * @param a_pPage Pointer to the physical guest page tracking structure.
875 */
876#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
877
878/**
879 * Checks if the page is backed by a SHARED page.
880 * @returns true/false.
881 * @param a_pPage Pointer to the physical guest page tracking structure.
882 */
883#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
884
885/**
886 * Checks if the page is ballooned.
887 * @returns true/false.
888 * @param a_pPage Pointer to the physical guest page tracking structure.
889 */
890#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
891
892/**
893 * Checks if the page is allocated.
894 * @returns true/false.
895 * @param a_pPage Pointer to the physical guest page tracking structure.
896 */
897#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
898
899/**
900 * Marks the page as written to (for GMM change monitoring).
901 * @param a_pVM The VM handle, only used for lock ownership assertions.
902 * @param a_pPage Pointer to the physical guest page tracking structure.
903 */
904#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
905 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
906
907/**
908 * Clears the written-to indicator.
909 * @param a_pVM The VM handle, only used for lock ownership assertions.
910 * @param a_pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
913 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
914
915/**
916 * Checks if the page was marked as written-to.
917 * @returns true/false.
918 * @param a_pPage Pointer to the physical guest page tracking structure.
919 */
920#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
921
922
923/** @name PT usage values (PGMPAGE::u2PDEType).
924 *
925 * @{ */
926/** Either as a PT or PDE. */
927#define PGM_PAGE_PDE_TYPE_DONTCARE 0
928/** Must use a page table to map the range. */
929#define PGM_PAGE_PDE_TYPE_PT 1
930/** Can use a page directory entry to map the continuous range. */
931#define PGM_PAGE_PDE_TYPE_PDE 2
932/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
933#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
934/** @} */
935
936/**
937 * Set the PDE type of the page
938 * @param a_pVM The VM handle, only used for lock ownership assertions.
939 * @param a_pPage Pointer to the physical guest page tracking structure.
940 * @param a_uType PGM_PAGE_PDE_TYPE_*.
941 */
942#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
943 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
944
945/**
946 * Checks if the page was marked being part of a large page
947 * @returns true/false.
948 * @param a_pPage Pointer to the physical guest page tracking structure.
949 */
950#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
951
952/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
953 *
954 * @remarks The values are assigned in order of priority, so we can calculate
955 * the correct state for a page with different handlers installed.
956 * @{ */
957/** No handler installed. */
958#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
959/** Monitoring is temporarily disabled. */
960#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
961/** Write access is monitored. */
962#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
963/** All access is monitored. */
964#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
965/** @} */
966
967/**
968 * Gets the physical access handler state of a page.
969 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
970 * @param a_pPage Pointer to the physical guest page tracking structure.
971 */
972#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
973
974/**
975 * Sets the physical access handler state of a page.
976 * @param a_pPage Pointer to the physical guest page tracking structure.
977 * @param a_uState The new state value.
978 */
979#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
980 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
981
982/**
983 * Checks if the page has any physical access handlers, including temporarily disabled ones.
984 * @returns true/false
985 * @param a_pPage Pointer to the physical guest page tracking structure.
986 */
987#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
988 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
989
990/**
991 * Checks if the page has any active physical access handlers.
992 * @returns true/false
993 * @param a_pPage Pointer to the physical guest page tracking structure.
994 */
995#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
996 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
997
998/**
999 * Checks if the page has any access handlers, including temporarily disabled ones.
1000 * @returns true/false
1001 * @param a_pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1004 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1005
1006/**
1007 * Checks if the page has any active access handlers.
1008 * @returns true/false
1009 * @param a_pPage Pointer to the physical guest page tracking structure.
1010 */
1011#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1012 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1013
1014/**
1015 * Checks if the page has any active access handlers catching all accesses.
1016 * @returns true/false
1017 * @param a_pPage Pointer to the physical guest page tracking structure.
1018 */
1019#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1020 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1021
1022
1023/** @def PGM_PAGE_GET_TRACKING
1024 * Gets the packed shadow page pool tracking data associated with a guest page.
1025 * @returns uint16_t containing the data.
1026 * @param a_pPage Pointer to the physical guest page tracking structure.
1027 */
1028#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1029#if defined(__GNUC__) && defined(VBOX_STRICT)
1030# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1031#else
1032# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1033#endif
1034
1035/** @def PGM_PAGE_SET_TRACKING
1036 * Sets the packed shadow page pool tracking data associated with a guest page.
1037 * @param a_pVM The VM handle, only used for lock ownership assertions.
1038 * @param a_pPage Pointer to the physical guest page tracking structure.
1039 * @param a_u16TrackingData The tracking data to store.
1040 */
1041#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1042 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1043
1044/** @def PGM_PAGE_GET_TD_CREFS
1045 * Gets the @a cRefs tracking data member.
1046 * @returns cRefs.
1047 * @param a_pPage Pointer to the physical guest page tracking structure.
1048 */
1049#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1050 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1051#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1052 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1053
1054/** @def PGM_PAGE_GET_TD_IDX
1055 * Gets the @a idx tracking data member.
1056 * @returns idx.
1057 * @param a_pPage Pointer to the physical guest page tracking structure.
1058 */
1059#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1060 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1061#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1062 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1063
1064
1065/** Max number of locks on a page. */
1066#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1067
1068/** Get the read lock count.
1069 * @returns count.
1070 * @param a_pPage Pointer to the physical guest page tracking structure.
1071 */
1072#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1073
1074/** Get the write lock count.
1075 * @returns count.
1076 * @param a_pPage Pointer to the physical guest page tracking structure.
1077 */
1078#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1079
1080/** Decrement the read lock counter.
1081 * @param a_pPage Pointer to the physical guest page tracking structure.
1082 */
1083#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1084
1085/** Decrement the write lock counter.
1086 * @param a_pPage Pointer to the physical guest page tracking structure.
1087 */
1088#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1089
1090/** Increment the read lock counter.
1091 * @param a_pPage Pointer to the physical guest page tracking structure.
1092 */
1093#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1094
1095/** Increment the write lock counter.
1096 * @param a_pPage Pointer to the physical guest page tracking structure.
1097 */
1098#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1099
1100
1101/** Gets the NEM state.
1102 * @returns NEM state value (two bits).
1103 * @param a_pPage Pointer to the physical guest page tracking structure.
1104 */
1105#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1106
1107/** Sets the NEM state.
1108 * @param a_pPage Pointer to the physical guest page tracking structure.
1109 * @param a_u2State The NEM state value (specific to NEM impl.).
1110 */
1111#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1112 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1113
1114
1115#if 0
1116/** Enables sanity checking of write monitoring using CRC-32. */
1117# define PGMLIVESAVERAMPAGE_WITH_CRC32
1118#endif
1119
1120/**
1121 * Per page live save tracking data.
1122 */
1123typedef struct PGMLIVESAVERAMPAGE
1124{
1125 /** Number of times it has been dirtied. */
1126 uint32_t cDirtied : 24;
1127 /** Whether it is currently dirty. */
1128 uint32_t fDirty : 1;
1129 /** Ignore the page.
1130 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1131 * deal with these after pausing the VM and DevPCI have said it bit about
1132 * remappings. */
1133 uint32_t fIgnore : 1;
1134 /** Was a ZERO page last time around. */
1135 uint32_t fZero : 1;
1136 /** Was a SHARED page last time around. */
1137 uint32_t fShared : 1;
1138 /** Whether the page is/was write monitored in a previous pass. */
1139 uint32_t fWriteMonitored : 1;
1140 /** Whether the page is/was write monitored earlier in this pass. */
1141 uint32_t fWriteMonitoredJustNow : 1;
1142 /** Bits reserved for future use. */
1143 uint32_t u2Reserved : 2;
1144#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1145 /** CRC-32 for the page. This is for internal consistency checks. */
1146 uint32_t u32Crc;
1147#endif
1148} PGMLIVESAVERAMPAGE;
1149#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1150AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1151#else
1152AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1153#endif
1154/** Pointer to the per page live save tracking data. */
1155typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1156
1157/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1158#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1159
1160
1161/**
1162 * RAM range for GC Phys to HC Phys conversion.
1163 *
1164 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1165 * conversions too, but we'll let MM handle that for now.
1166 *
1167 * This structure is used by linked lists in both GC and HC.
1168 */
1169typedef struct PGMRAMRANGE
1170{
1171 /** Start of the range. Page aligned. */
1172 RTGCPHYS GCPhys;
1173 /** Size of the range. (Page aligned of course). */
1174 RTGCPHYS cb;
1175 /** Pointer to the next RAM range - for R3. */
1176 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1177 /** Pointer to the next RAM range - for R0. */
1178 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1179 /** PGM_RAM_RANGE_FLAGS_* flags. */
1180 uint32_t fFlags;
1181 /** NEM specific info, UINT32_MAX if not used. */
1182 uint32_t uNemRange;
1183 /** Last address in the range (inclusive). Page aligned (-1). */
1184 RTGCPHYS GCPhysLast;
1185 /** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1186 R3PTRTYPE(void *) pvR3;
1187 /** Live save per page tracking data. */
1188 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1189 /** The range description. */
1190 R3PTRTYPE(const char *) pszDesc;
1191 /** Pointer to self - R0 pointer. */
1192 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1193
1194 /** Pointer to the left search three node - ring-3 context. */
1195 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1196 /** Pointer to the right search three node - ring-3 context. */
1197 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1198 /** Pointer to the left search three node - ring-0 context. */
1199 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1200 /** Pointer to the right search three node - ring-0 context. */
1201 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1202
1203 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1204#if HC_ARCH_BITS == 32
1205 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1206#endif
1207 /** Array of physical guest page tracking structures. */
1208 PGMPAGE aPages[1];
1209} PGMRAMRANGE;
1210/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1211typedef PGMRAMRANGE *PPGMRAMRANGE;
1212
1213/** @name PGMRAMRANGE::fFlags
1214 * @{ */
1215/** The RAM range is floating around as an independent guest mapping. */
1216#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1217/** Ad hoc RAM range for an ROM mapping. */
1218#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1219/** Ad hoc RAM range for an MMIO mapping. */
1220#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1221/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1222#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1223/** @} */
1224
1225/** Tests if a RAM range is an ad hoc one or not.
1226 * @returns true/false.
1227 * @param pRam The RAM range.
1228 */
1229#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1230 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1231
1232/** The number of entries in the RAM range TLBs (there is one for each
1233 * context). Must be a power of two. */
1234#define PGM_RAMRANGE_TLB_ENTRIES 8
1235
1236/**
1237 * Calculates the RAM range TLB index for the physical address.
1238 *
1239 * @returns RAM range TLB index.
1240 * @param a_GCPhys The guest physical address.
1241 */
1242#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1243
1244/**
1245 * Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1246 * mapping address.
1247 */
1248#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1249 ( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1250
1251
1252/**
1253 * Per page tracking structure for ROM image.
1254 *
1255 * A ROM image may have a shadow page, in which case we may have two pages
1256 * backing it. This structure contains the PGMPAGE for both while
1257 * PGMRAMRANGE have a copy of the active one. It is important that these
1258 * aren't out of sync in any regard other than page pool tracking data.
1259 */
1260typedef struct PGMROMPAGE
1261{
1262 /** The page structure for the virgin ROM page. */
1263 PGMPAGE Virgin;
1264 /** The page structure for the shadow RAM page. */
1265 PGMPAGE Shadow;
1266 /** The current protection setting. */
1267 PGMROMPROT enmProt;
1268 /** Live save status information. Makes use of unused alignment space. */
1269 struct
1270 {
1271 /** The previous protection value. */
1272 uint8_t u8Prot;
1273 /** Written to flag set by the handler. */
1274 bool fWrittenTo;
1275 /** Whether the shadow page is dirty or not. */
1276 bool fDirty;
1277 /** Whether it was dirtied in the recently. */
1278 bool fDirtiedRecently;
1279 } LiveSave;
1280} PGMROMPAGE;
1281AssertCompileSizeAlignment(PGMROMPAGE, 8);
1282/** Pointer to a ROM page tracking structure. */
1283typedef PGMROMPAGE *PPGMROMPAGE;
1284
1285
1286/**
1287 * A registered ROM image.
1288 *
1289 * This is needed to keep track of ROM image since they generally intrude
1290 * into a PGMRAMRANGE. It also keeps track of additional info like the
1291 * two page sets (read-only virgin and read-write shadow), the current
1292 * state of each page.
1293 *
1294 * Because access handlers cannot easily be executed in a different
1295 * context, the ROM ranges needs to be accessible and in all contexts.
1296 */
1297typedef struct PGMROMRANGE
1298{
1299 /** Pointer to the next range - R3. */
1300 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1301 /** Pointer to the next range - R0. */
1302 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1303 /** Address of the range. */
1304 RTGCPHYS GCPhys;
1305 /** Address of the last byte in the range. */
1306 RTGCPHYS GCPhysLast;
1307 /** Size of the range. */
1308 RTGCPHYS cb;
1309 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1310 uint8_t fFlags;
1311 /** The saved state range ID. */
1312 uint8_t idSavedState;
1313 /** Alignment padding. */
1314 uint8_t au8Alignment[2];
1315 /** The size bits pvOriginal points to. */
1316 uint32_t cbOriginal;
1317 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1318 * This is used for strictness checks. */
1319 R3PTRTYPE(const void *) pvOriginal;
1320 /** The ROM description. */
1321 R3PTRTYPE(const char *) pszDesc;
1322#ifdef VBOX_WITH_PGM_NEM_MODE
1323 /** In simplified memory mode this provides alternate backing for shadowed ROMs.
1324 * - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1325 * - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1326 * - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1327 * - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1328 R3PTRTYPE(uint8_t *) pbR3Alternate;
1329 RTR3PTR pvAlignment2;
1330#endif
1331 /** The per page tracking structures. */
1332 PGMROMPAGE aPages[1];
1333} PGMROMRANGE;
1334/** Pointer to a ROM range. */
1335typedef PGMROMRANGE *PPGMROMRANGE;
1336
1337
1338/**
1339 * Live save per page data for an MMIO2 page.
1340 *
1341 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1342 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1343 * CRC-32 for detecting changes as well as special handling of zero pages. This
1344 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1345 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1346 * because of speed (2.5x and 6x slower).)
1347 *
1348 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1349 * save but normally is disabled. Since we can write monitor guest
1350 * accesses on our own, we only need this for host accesses. Shouldn't be
1351 * too difficult for DevVGA, VMMDev might be doable, the planned
1352 * networking fun will be fun since it involves ring-0.
1353 */
1354typedef struct PGMLIVESAVEMMIO2PAGE
1355{
1356 /** Set if the page is considered dirty. */
1357 bool fDirty;
1358 /** The number of scans this page has remained unchanged for.
1359 * Only updated for dirty pages. */
1360 uint8_t cUnchangedScans;
1361 /** Whether this page was zero at the last scan. */
1362 bool fZero;
1363 /** Alignment padding. */
1364 bool fReserved;
1365 /** CRC-32 for the first half of the page.
1366 * This is used together with u32CrcH2 to quickly detect changes in the page
1367 * during the non-final passes. */
1368 uint32_t u32CrcH1;
1369 /** CRC-32 for the second half of the page. */
1370 uint32_t u32CrcH2;
1371 /** SHA-1 for the saved page.
1372 * This is used in the final pass to skip pages without changes. */
1373 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1374} PGMLIVESAVEMMIO2PAGE;
1375/** Pointer to a live save status data for an MMIO2 page. */
1376typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1377
1378/**
1379 * A registered MMIO2 (= Device RAM) range.
1380 *
1381 * There are a few reason why we need to keep track of these registrations. One
1382 * of them is the deregistration & cleanup stuff, while another is that the
1383 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1384 * range list.
1385 *
1386 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1387 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1388 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1389 * overlap we will free all the existing RAM pages and put in the ram range
1390 * pages instead.
1391 */
1392typedef struct PGMREGMMIO2RANGE
1393{
1394 /** The owner of the range. (a device) */
1395 PPDMDEVINSR3 pDevInsR3;
1396 /** Pointer to the ring-3 mapping of the allocation. */
1397 RTR3PTR pvR3;
1398#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1399 /** Pointer to the ring-0 mapping of the allocation. */
1400 RTR0PTR pvR0;
1401#endif
1402 /** Pointer to the next range - R3. */
1403 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1404 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1405 uint16_t fFlags;
1406 /** The sub device number (internal PCI config (CFGM) number). */
1407 uint8_t iSubDev;
1408 /** The PCI region number. */
1409 uint8_t iRegion;
1410 /** The saved state range ID. */
1411 uint8_t idSavedState;
1412 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1413 uint8_t idMmio2;
1414 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1415#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1416 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1417#else
1418 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1419#endif
1420 /** The real size.
1421 * This may be larger than indicated by RamRange.cb if the range has been
1422 * reduced during saved state loading. */
1423 RTGCPHYS cbReal;
1424 /** Pointer to the physical handler for MMIO.
1425 * If NEM is responsible for tracking dirty pages in simple memory mode, this
1426 * will be NULL. */
1427 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1428 /** Live save per page tracking data for MMIO2. */
1429 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1430 /** The associated RAM range. */
1431 PGMRAMRANGE RamRange;
1432} PGMREGMMIO2RANGE;
1433AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1434/** Pointer to a MMIO2 or pre-registered MMIO range. */
1435typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1436
1437/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1438 * @{ */
1439/** Set if this is the first chunk in the MMIO2 range. */
1440#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1441/** Set if this is the last chunk in the MMIO2 range. */
1442#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1443/** Set if the whole range is mapped. */
1444#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1445/** Set if it's overlapping, clear if not. */
1446#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1447/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1448#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1449/** Set if the access handler is registered. */
1450#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1451/** Set if dirty page tracking is currently enabled. */
1452#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1453/** Set if there are dirty pages in the range. */
1454#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1455/** @} */
1456
1457
1458/** @name Internal MMIO2 constants.
1459 * @{ */
1460/** The maximum number of MMIO2 ranges. */
1461#define PGM_MMIO2_MAX_RANGES 32
1462/** The maximum number of pages in a MMIO2 range. */
1463#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1464/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1465#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1466/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1467#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1468/** Gets the MMIO2 page index from an MMIO2 page ID. */
1469#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1470/** @} */
1471
1472
1473
1474/**
1475 * PGMPhysRead/Write cache entry
1476 */
1477typedef struct PGMPHYSCACHEENTRY
1478{
1479 /** R3 pointer to physical page. */
1480 R3PTRTYPE(uint8_t *) pbR3;
1481 /** GC Physical address for cache entry */
1482 RTGCPHYS GCPhys;
1483#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1484 RTGCPHYS u32Padding0; /**< alignment padding. */
1485#endif
1486} PGMPHYSCACHEENTRY;
1487
1488/**
1489 * PGMPhysRead/Write cache to reduce REM memory access overhead
1490 */
1491typedef struct PGMPHYSCACHE
1492{
1493 /** Bitmap of valid cache entries */
1494 uint64_t aEntries;
1495 /** Cache entries */
1496 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1497} PGMPHYSCACHE;
1498
1499
1500/** @name Ring-3 page mapping TLBs
1501 * @{ */
1502
1503/** Pointer to an allocation chunk ring-3 mapping. */
1504typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1505/** Pointer to an allocation chunk ring-3 mapping pointer. */
1506typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1507
1508/**
1509 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1510 *
1511 * The primary tree (Core) uses the chunk id as key.
1512 */
1513typedef struct PGMCHUNKR3MAP
1514{
1515 /** The key is the chunk id. */
1516 AVLU32NODECORE Core;
1517 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1518 * selection. */
1519 uint32_t iLastUsed;
1520 /** The current reference count. */
1521 uint32_t volatile cRefs;
1522 /** The current permanent reference count. */
1523 uint32_t volatile cPermRefs;
1524 /** The mapping address. */
1525 void *pv;
1526} PGMCHUNKR3MAP;
1527
1528/**
1529 * Allocation chunk ring-3 mapping TLB entry.
1530 */
1531typedef struct PGMCHUNKR3MAPTLBE
1532{
1533 /** The chunk id. */
1534 uint32_t volatile idChunk;
1535#if HC_ARCH_BITS == 64
1536 uint32_t u32Padding; /**< alignment padding. */
1537#endif
1538 /** The chunk map. */
1539 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1540} PGMCHUNKR3MAPTLBE;
1541/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1542typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1543
1544/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1545 * @remark Must be a power of two value. */
1546#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1547
1548/**
1549 * Allocation chunk ring-3 mapping TLB.
1550 *
1551 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1552 * At first glance this might look kinda odd since AVL trees are
1553 * supposed to give the most optimal lookup times of all trees
1554 * due to their balancing. However, take a tree with 1023 nodes
1555 * in it, that's 10 levels, meaning that most searches has to go
1556 * down 9 levels before they find what they want. This isn't fast
1557 * compared to a TLB hit. There is the factor of cache misses,
1558 * and of course the problem with trees and branch prediction.
1559 * This is why we use TLBs in front of most of the trees.
1560 *
1561 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1562 * difficult when we switch to the new inlined AVL trees (from kStuff).
1563 */
1564typedef struct PGMCHUNKR3MAPTLB
1565{
1566 /** The TLB entries. */
1567 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1568} PGMCHUNKR3MAPTLB;
1569
1570/**
1571 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1572 * @returns Chunk TLB index.
1573 * @param idChunk The Chunk ID.
1574 */
1575#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1576
1577
1578/**
1579 * Ring-3 guest page mapping TLB entry.
1580 * @remarks used in ring-0 as well at the moment.
1581 */
1582typedef struct PGMPAGER3MAPTLBE
1583{
1584 /** Address of the page. */
1585 RTGCPHYS volatile GCPhys;
1586 /** The guest page. */
1587 R3PTRTYPE(PPGMPAGE) volatile pPage;
1588 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1589 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1590 /** The address */
1591 R3PTRTYPE(void *) volatile pv;
1592#if HC_ARCH_BITS == 32
1593 uint32_t u32Padding; /**< alignment padding. */
1594#endif
1595} PGMPAGER3MAPTLBE;
1596/** Pointer to an entry in the HC physical TLB. */
1597typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1598
1599
1600/** The number of entries in the ring-3 guest page mapping TLB.
1601 * @remarks The value must be a power of two. */
1602#define PGM_PAGER3MAPTLB_ENTRIES 256
1603
1604/**
1605 * Ring-3 guest page mapping TLB.
1606 * @remarks used in ring-0 as well at the moment.
1607 */
1608typedef struct PGMPAGER3MAPTLB
1609{
1610 /** The TLB entries. */
1611 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1612} PGMPAGER3MAPTLB;
1613/** Pointer to the ring-3 guest page mapping TLB. */
1614typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1615
1616/**
1617 * Calculates the index of the TLB entry for the specified guest page.
1618 * @returns Physical TLB index.
1619 * @param GCPhys The guest physical address.
1620 */
1621#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1622
1623/** @} */
1624
1625
1626/** @name Ring-0 page mapping TLB
1627 * @{ */
1628/**
1629 * Ring-0 guest page mapping TLB entry.
1630 */
1631typedef struct PGMPAGER0MAPTLBE
1632{
1633 /** Address of the page. */
1634 RTGCPHYS volatile GCPhys;
1635 /** The guest page. */
1636 R0PTRTYPE(PPGMPAGE) volatile pPage;
1637 /** The address */
1638 R0PTRTYPE(void *) volatile pv;
1639} PGMPAGER0MAPTLBE;
1640/** Pointer to an entry in the HC physical TLB. */
1641typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1642
1643
1644/** The number of entries in the ring-3 guest page mapping TLB.
1645 * @remarks The value must be a power of two. */
1646#define PGM_PAGER0MAPTLB_ENTRIES 256
1647
1648/**
1649 * Ring-3 guest page mapping TLB.
1650 * @remarks used in ring-0 as well at the moment.
1651 */
1652typedef struct PGMPAGER0MAPTLB
1653{
1654 /** The TLB entries. */
1655 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1656} PGMPAGER0MAPTLB;
1657/** Pointer to the ring-3 guest page mapping TLB. */
1658typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1659
1660/**
1661 * Calculates the index of the TLB entry for the specified guest page.
1662 * @returns Physical TLB index.
1663 * @param GCPhys The guest physical address.
1664 */
1665#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1666/** @} */
1667
1668
1669/** @name Context neutral page mapper TLB.
1670 *
1671 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1672 * code is writting in a kind of context neutral way. Time will show whether
1673 * this actually makes sense or not...
1674 *
1675 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1676 * context ends up using a global mapping cache on some platforms
1677 * (darwin).
1678 *
1679 * @{ */
1680/** @typedef PPGMPAGEMAPTLB
1681 * The page mapper TLB pointer type for the current context. */
1682/** @typedef PPGMPAGEMAPTLB
1683 * The page mapper TLB entry pointer type for the current context. */
1684/** @typedef PPGMPAGEMAPTLB
1685 * The page mapper TLB entry pointer pointer type for the current context. */
1686/** @def PGM_PAGEMAPTLB_ENTRIES
1687 * The number of TLB entries in the page mapper TLB for the current context. */
1688/** @def PGM_PAGEMAPTLB_IDX
1689 * Calculate the TLB index for a guest physical address.
1690 * @returns The TLB index.
1691 * @param GCPhys The guest physical address. */
1692/** @typedef PPGMPAGEMAP
1693 * Pointer to a page mapper unit for current context. */
1694/** @typedef PPPGMPAGEMAP
1695 * Pointer to a page mapper unit pointer for current context. */
1696#if defined(IN_RING0)
1697typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1698typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1699typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1700# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1701# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1702typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1703typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1704#else
1705typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1706typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1707typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1708# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1709# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1710typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1711typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1712#endif
1713/** @} */
1714
1715
1716/** @name PGM Pool Indexes.
1717 * Aka. the unique shadow page identifier.
1718 * @{ */
1719/** NIL page pool IDX. */
1720#define NIL_PGMPOOL_IDX 0
1721/** The first normal index. There used to be 5 fictive pages up front, now
1722 * there is only the NIL page. */
1723#define PGMPOOL_IDX_FIRST 1
1724/** The last valid index. (inclusive, 14 bits) */
1725#define PGMPOOL_IDX_LAST 0x3fff
1726/** @} */
1727
1728/** The NIL index for the parent chain. */
1729#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1730#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1731
1732/**
1733 * Node in the chain linking a shadowed page to it's parent (user).
1734 */
1735#pragma pack(1)
1736typedef struct PGMPOOLUSER
1737{
1738 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1739 uint16_t iNext;
1740 /** The user page index. */
1741 uint16_t iUser;
1742 /** Index into the user table. */
1743 uint32_t iUserTable;
1744} PGMPOOLUSER, *PPGMPOOLUSER;
1745typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1746#pragma pack()
1747
1748
1749/** The NIL index for the phys ext chain. */
1750#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1751/** The NIL pte index for a phys ext chain slot. */
1752#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1753
1754/**
1755 * Node in the chain of physical cross reference extents.
1756 * @todo Calling this an 'extent' is not quite right, find a better name.
1757 * @todo find out the optimal size of the aidx array
1758 */
1759#pragma pack(1)
1760typedef struct PGMPOOLPHYSEXT
1761{
1762 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1763 uint16_t iNext;
1764 /** Alignment. */
1765 uint16_t u16Align;
1766 /** The user page index. */
1767 uint16_t aidx[3];
1768 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1769 uint16_t apte[3];
1770} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1771typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1772#pragma pack()
1773
1774
1775/**
1776 * The kind of page that's being shadowed.
1777 */
1778typedef enum PGMPOOLKIND
1779{
1780 /** The virtual invalid 0 entry. */
1781 PGMPOOLKIND_INVALID = 0,
1782 /** The entry is free (=unused). */
1783 PGMPOOLKIND_FREE,
1784
1785 /** Shw: 32-bit page table; Gst: no paging. */
1786 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1787 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1788 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1789 /** Shw: 32-bit page table; Gst: 4MB page. */
1790 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1791 /** Shw: PAE page table; Gst: no paging. */
1792 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1793 /** Shw: PAE page table; Gst: 32-bit page table. */
1794 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1795 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1796 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1797 /** Shw: PAE page table; Gst: PAE page table. */
1798 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1799 /** Shw: PAE page table; Gst: 2MB page. */
1800 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1801
1802 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1803 PGMPOOLKIND_32BIT_PD,
1804 /** Shw: 32-bit page directory. Gst: no paging. */
1805 PGMPOOLKIND_32BIT_PD_PHYS,
1806 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1807 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1808 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1809 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1810 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1811 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1812 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1813 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1814 /** Shw: PAE page directory; Gst: PAE page directory. */
1815 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1816 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1817 PGMPOOLKIND_PAE_PD_PHYS,
1818
1819 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1820 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1821 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1822 PGMPOOLKIND_PAE_PDPT,
1823 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1824 PGMPOOLKIND_PAE_PDPT_PHYS,
1825
1826 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1827 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1828 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
1829 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1830 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1831 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1832 /** Shw: 64-bit page directory table; Gst: no paging. */
1833 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1834
1835 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1836 PGMPOOLKIND_64BIT_PML4,
1837
1838 /** Shw: EPT page directory pointer table; Gst: no paging. */
1839 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1840 /** Shw: EPT page directory table; Gst: no paging. */
1841 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1842 /** Shw: EPT page table; Gst: no paging. */
1843 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1844
1845 /** Shw: Root Nested paging table. */
1846 PGMPOOLKIND_ROOT_NESTED,
1847
1848 /** The last valid entry. */
1849 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1850} PGMPOOLKIND;
1851
1852/**
1853 * The access attributes of the page; only applies to big pages.
1854 */
1855typedef enum
1856{
1857 PGMPOOLACCESS_DONTCARE = 0,
1858 PGMPOOLACCESS_USER_RW,
1859 PGMPOOLACCESS_USER_R,
1860 PGMPOOLACCESS_USER_RW_NX,
1861 PGMPOOLACCESS_USER_R_NX,
1862 PGMPOOLACCESS_SUPERVISOR_RW,
1863 PGMPOOLACCESS_SUPERVISOR_R,
1864 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1865 PGMPOOLACCESS_SUPERVISOR_R_NX
1866} PGMPOOLACCESS;
1867
1868/**
1869 * The tracking data for a page in the pool.
1870 */
1871typedef struct PGMPOOLPAGE
1872{
1873 /** AVL node code with the (HC) physical address of this page. */
1874 AVLOHCPHYSNODECORE Core;
1875 /** Pointer to the R3 mapping of the page. */
1876 R3PTRTYPE(void *) pvPageR3;
1877 /** Pointer to the R0 mapping of the page. */
1878 R0PTRTYPE(void *) pvPageR0;
1879 /** The guest physical address. */
1880 RTGCPHYS GCPhys;
1881 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1882 uint8_t enmKind;
1883 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1884 uint8_t enmAccess;
1885 /** This supplements enmKind and enmAccess */
1886 bool fA20Enabled : 1;
1887
1888 /** Used to indicate that the page is zeroed. */
1889 bool fZeroed : 1;
1890 /** Used to indicate that a PT has non-global entries. */
1891 bool fSeenNonGlobal : 1;
1892 /** Used to indicate that we're monitoring writes to the guest page. */
1893 bool fMonitored : 1;
1894 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1895 * (All pages are in the age list.) */
1896 bool fCached : 1;
1897 /** This is used by the R3 access handlers when invoked by an async thread.
1898 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1899 bool volatile fReusedFlushPending : 1;
1900 /** Used to mark the page as dirty (write monitoring is temporarily
1901 * off). */
1902 bool fDirty : 1;
1903 bool fPadding1 : 1;
1904 bool fPadding2;
1905
1906 /** The index of this page. */
1907 uint16_t idx;
1908 /** The next entry in the list this page currently resides in.
1909 * It's either in the free list or in the GCPhys hash. */
1910 uint16_t iNext;
1911 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1912 uint16_t iUserHead;
1913 /** The number of present entries. */
1914 uint16_t cPresent;
1915 /** The first entry in the table which is present. */
1916 uint16_t iFirstPresent;
1917 /** The number of modifications to the monitored page. */
1918 uint16_t cModifications;
1919 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1920 uint16_t iModifiedNext;
1921 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1922 uint16_t iModifiedPrev;
1923 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1924 uint16_t iMonitoredNext;
1925 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1926 uint16_t iMonitoredPrev;
1927 /** The next page in the age list. */
1928 uint16_t iAgeNext;
1929 /** The previous page in the age list. */
1930 uint16_t iAgePrev;
1931 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
1932 uint8_t idxDirtyEntry;
1933
1934 /** @name Access handler statistics to determine whether the guest is
1935 * (re)initializing a page table.
1936 * @{ */
1937 RTGCPTR GCPtrLastAccessHandlerRip;
1938 RTGCPTR GCPtrLastAccessHandlerFault;
1939 uint64_t cLastAccessHandler;
1940 /** @} */
1941 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
1942 uint32_t volatile cLocked;
1943#if GC_ARCH_BITS == 64
1944 uint32_t u32Alignment3;
1945#endif
1946# ifdef VBOX_STRICT
1947 RTGCPTR GCPtrDirtyFault;
1948# endif
1949} PGMPOOLPAGE;
1950/** Pointer to a pool page. */
1951typedef PGMPOOLPAGE *PPGMPOOLPAGE;
1952/** Pointer to a const pool page. */
1953typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1954/** Pointer to a pool page pointer. */
1955typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
1956
1957
1958/** The hash table size. */
1959# define PGMPOOL_HASH_SIZE 0x40
1960/** The hash function. */
1961# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1962
1963
1964/**
1965 * The shadow page pool instance data.
1966 *
1967 * It's all one big allocation made at init time, except for the
1968 * pages that is. The user nodes follows immediately after the
1969 * page structures.
1970 */
1971typedef struct PGMPOOL
1972{
1973 /** The VM handle - R3 Ptr. */
1974 PVMR3 pVMR3;
1975 /** The VM handle - R0 Ptr. */
1976 R0PTRTYPE(PVMCC) pVMR0;
1977 /** The max pool size. This includes the special IDs. */
1978 uint16_t cMaxPages;
1979 /** The current pool size. */
1980 uint16_t cCurPages;
1981 /** The head of the free page list. */
1982 uint16_t iFreeHead;
1983 /* Padding. */
1984 uint16_t u16Padding;
1985 /** Head of the chain of free user nodes. */
1986 uint16_t iUserFreeHead;
1987 /** The number of user nodes we've allocated. */
1988 uint16_t cMaxUsers;
1989 /** The number of present page table entries in the entire pool. */
1990 uint32_t cPresent;
1991 /** Pointer to the array of user nodes - R3 pointer. */
1992 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1993 /** Pointer to the array of user nodes - R0 pointer. */
1994 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1995 /** Head of the chain of free phys ext nodes. */
1996 uint16_t iPhysExtFreeHead;
1997 /** The number of user nodes we've allocated. */
1998 uint16_t cMaxPhysExts;
1999 uint32_t u32Padding0b;
2000 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2001 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2002 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2003 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2004 /** Hash table for GCPhys addresses. */
2005 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2006 /** The head of the age list. */
2007 uint16_t iAgeHead;
2008 /** The tail of the age list. */
2009 uint16_t iAgeTail;
2010 /** Set if the cache is enabled. */
2011 bool fCacheEnabled;
2012 /** Alignment padding. */
2013 bool afPadding1[3];
2014 /** Head of the list of modified pages. */
2015 uint16_t iModifiedHead;
2016 /** The current number of modified pages. */
2017 uint16_t cModifiedPages;
2018 /** Physical access handler type registration handle. */
2019 PGMPHYSHANDLERTYPE hAccessHandlerType;
2020 /** Next available slot (in aDirtyPages). */
2021 uint32_t idxFreeDirtyPage;
2022 /** Number of active dirty pages. */
2023 uint32_t cDirtyPages;
2024 /** Array of current dirty pgm pool page indices. */
2025 uint16_t aidxDirtyPages[16];
2026 /** Array running in parallel to aidxDirtyPages with the page data. */
2027 struct
2028 {
2029 uint64_t aPage[512];
2030 } aDirtyPages[16];
2031
2032 /** The number of pages currently in use. */
2033 uint16_t cUsedPages;
2034#ifdef VBOX_WITH_STATISTICS
2035 /** The high water mark for cUsedPages. */
2036 uint16_t cUsedPagesHigh;
2037 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2038 /** Profiling pgmPoolAlloc(). */
2039 STAMPROFILEADV StatAlloc;
2040 /** Profiling pgmR3PoolClearDoIt(). */
2041 STAMPROFILE StatClearAll;
2042 /** Profiling pgmR3PoolReset(). */
2043 STAMPROFILE StatR3Reset;
2044 /** Profiling pgmPoolFlushPage(). */
2045 STAMPROFILE StatFlushPage;
2046 /** Profiling pgmPoolFree(). */
2047 STAMPROFILE StatFree;
2048 /** Counting explicit flushes by PGMPoolFlushPage(). */
2049 STAMCOUNTER StatForceFlushPage;
2050 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2051 STAMCOUNTER StatForceFlushDirtyPage;
2052 /** Counting flushes for reused pages. */
2053 STAMCOUNTER StatForceFlushReused;
2054 /** Profiling time spent zeroing pages. */
2055 STAMPROFILE StatZeroPage;
2056 /** Profiling of pgmPoolTrackDeref. */
2057 STAMPROFILE StatTrackDeref;
2058 /** Profiling pgmTrackFlushGCPhysPT. */
2059 STAMPROFILE StatTrackFlushGCPhysPT;
2060 /** Profiling pgmTrackFlushGCPhysPTs. */
2061 STAMPROFILE StatTrackFlushGCPhysPTs;
2062 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2063 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2064 /** Number of times we've been out of user records. */
2065 STAMCOUNTER StatTrackFreeUpOneUser;
2066 /** Nr of flushed entries. */
2067 STAMCOUNTER StatTrackFlushEntry;
2068 /** Nr of updated entries. */
2069 STAMCOUNTER StatTrackFlushEntryKeep;
2070 /** Profiling deref activity related tracking GC physical pages. */
2071 STAMPROFILE StatTrackDerefGCPhys;
2072 /** Number of linear searches for a HCPhys in the ram ranges. */
2073 STAMCOUNTER StatTrackLinearRamSearches;
2074 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2075 STAMCOUNTER StamTrackPhysExtAllocFailures;
2076
2077 /** Profiling the RC/R0 \#PF access handler. */
2078 STAMPROFILE StatMonitorPfRZ;
2079 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2080 STAMPROFILE StatMonitorPfRZHandled;
2081 /** Times we've failed interpreting the instruction. */
2082 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2083 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2084 STAMPROFILE StatMonitorPfRZFlushPage;
2085 /** Times we've detected a page table reinit. */
2086 STAMCOUNTER StatMonitorPfRZFlushReinit;
2087 /** Counting flushes for pages that are modified too often. */
2088 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2089 /** Times we've detected fork(). */
2090 STAMCOUNTER StatMonitorPfRZFork;
2091 /** Times we've failed interpreting a patch code instruction. */
2092 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2093 /** Times we've failed interpreting a patch code instruction during flushing. */
2094 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2095 /** The number of times we've seen rep prefixes we can't handle. */
2096 STAMCOUNTER StatMonitorPfRZRepPrefix;
2097 /** Profiling the REP STOSD cases we've handled. */
2098 STAMPROFILE StatMonitorPfRZRepStosd;
2099
2100 /** Profiling the R0/RC regular access handler. */
2101 STAMPROFILE StatMonitorRZ;
2102 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2103 STAMPROFILE StatMonitorRZFlushPage;
2104 /** Per access size counts indexed by size minus 1, last for larger. */
2105 STAMCOUNTER aStatMonitorRZSizes[16+3];
2106 /** Missaligned access counts indexed by offset - 1. */
2107 STAMCOUNTER aStatMonitorRZMisaligned[7];
2108
2109 /** Nr of handled PT faults. */
2110 STAMCOUNTER StatMonitorRZFaultPT;
2111 /** Nr of handled PD faults. */
2112 STAMCOUNTER StatMonitorRZFaultPD;
2113 /** Nr of handled PDPT faults. */
2114 STAMCOUNTER StatMonitorRZFaultPDPT;
2115 /** Nr of handled PML4 faults. */
2116 STAMCOUNTER StatMonitorRZFaultPML4;
2117
2118 /** Profiling the R3 access handler. */
2119 STAMPROFILE StatMonitorR3;
2120 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2121 STAMPROFILE StatMonitorR3FlushPage;
2122 /** Per access size counts indexed by size minus 1, last for larger. */
2123 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2124 /** Missaligned access counts indexed by offset - 1. */
2125 STAMCOUNTER aStatMonitorR3Misaligned[7];
2126 /** Nr of handled PT faults. */
2127 STAMCOUNTER StatMonitorR3FaultPT;
2128 /** Nr of handled PD faults. */
2129 STAMCOUNTER StatMonitorR3FaultPD;
2130 /** Nr of handled PDPT faults. */
2131 STAMCOUNTER StatMonitorR3FaultPDPT;
2132 /** Nr of handled PML4 faults. */
2133 STAMCOUNTER StatMonitorR3FaultPML4;
2134
2135 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2136 STAMCOUNTER StatResetDirtyPages;
2137 /** Times we've called pgmPoolAddDirtyPage. */
2138 STAMCOUNTER StatDirtyPage;
2139 /** Times we've had to flush duplicates for dirty page management. */
2140 STAMCOUNTER StatDirtyPageDupFlush;
2141 /** Times we've had to flush because of overflow. */
2142 STAMCOUNTER StatDirtyPageOverFlowFlush;
2143
2144 /** The high water mark for cModifiedPages. */
2145 uint16_t cModifiedPagesHigh;
2146 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2147
2148 /** The number of cache hits. */
2149 STAMCOUNTER StatCacheHits;
2150 /** The number of cache misses. */
2151 STAMCOUNTER StatCacheMisses;
2152 /** The number of times we've got a conflict of 'kind' in the cache. */
2153 STAMCOUNTER StatCacheKindMismatches;
2154 /** Number of times we've been out of pages. */
2155 STAMCOUNTER StatCacheFreeUpOne;
2156 /** The number of cacheable allocations. */
2157 STAMCOUNTER StatCacheCacheable;
2158 /** The number of uncacheable allocations. */
2159 STAMCOUNTER StatCacheUncacheable;
2160#else
2161 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2162#endif
2163 /** Profiling PGMR0PoolGrow(). */
2164 STAMPROFILE StatGrow;
2165 /** The AVL tree for looking up a page by its HC physical address. */
2166 AVLOHCPHYSTREE HCPhysTree;
2167 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2168 /** Array of pages. (cMaxPages in length)
2169 * The Id is the index into thist array.
2170 */
2171 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2172} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2173AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2174AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2175AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2176#ifdef VBOX_WITH_STATISTICS
2177AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2178#endif
2179AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2180
2181
2182/** @def PGMPOOL_PAGE_2_PTR
2183 * Maps a pool page pool into the current context.
2184 *
2185 * @returns VBox status code.
2186 * @param a_pVM Pointer to the VM.
2187 * @param a_pPage The pool page.
2188 *
2189 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2190 * small page window employeed by that function. Be careful.
2191 * @remark There is no need to assert on the result.
2192 */
2193#if defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2194# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2195DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2196{
2197 RT_NOREF(pszCaller);
2198 AssertPtr(a_pPage);
2199 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2200 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2201 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2202 return a_pPage->CTX_SUFF(pvPage);
2203}
2204#else
2205# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2206#endif
2207
2208
2209/** @def PGMPOOL_PAGE_2_PTR_V2
2210 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2211 *
2212 * @returns VBox status code.
2213 * @param a_pVM Pointer to the VM.
2214 * @param a_pVCpu The current CPU.
2215 * @param a_pPage The pool page.
2216 *
2217 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2218 * small page window employeed by that function. Be careful.
2219 * @remark There is no need to assert on the result.
2220 */
2221#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2222
2223
2224/** @name Per guest page tracking data.
2225 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2226 * is to use more bits for it and split it up later on. But for now we'll play
2227 * safe and change as little as possible.
2228 *
2229 * The 16-bit word has two parts:
2230 *
2231 * The first 14-bit forms the @a idx field. It is either the index of a page in
2232 * the shadow page pool, or and index into the extent list.
2233 *
2234 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2235 * shadow page pool references to the page. If cRefs equals
2236 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2237 * (misnomer) table and not the shadow page pool.
2238 *
2239 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2240 * the 16-bit word.
2241 *
2242 * @{ */
2243/** The shift count for getting to the cRefs part. */
2244#define PGMPOOL_TD_CREFS_SHIFT 14
2245/** The mask applied after shifting the tracking data down by
2246 * PGMPOOL_TD_CREFS_SHIFT. */
2247#define PGMPOOL_TD_CREFS_MASK 0x3
2248/** The cRefs value used to indicate that the idx is the head of a
2249 * physical cross reference list. */
2250#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2251/** The shift used to get idx. */
2252#define PGMPOOL_TD_IDX_SHIFT 0
2253/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2254#define PGMPOOL_TD_IDX_MASK 0x3fff
2255/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2256 * simply too many mappings of this page. */
2257#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2258
2259/** @def PGMPOOL_TD_MAKE
2260 * Makes a 16-bit tracking data word.
2261 *
2262 * @returns tracking data.
2263 * @param cRefs The @a cRefs field. Must be within bounds!
2264 * @param idx The @a idx field. Must also be within bounds! */
2265#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2266
2267/** @def PGMPOOL_TD_GET_CREFS
2268 * Get the @a cRefs field from a tracking data word.
2269 *
2270 * @returns The @a cRefs field
2271 * @param u16 The tracking data word.
2272 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2273 * non-zero @a u16. */
2274#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2275
2276/** @def PGMPOOL_TD_GET_IDX
2277 * Get the @a idx field from a tracking data word.
2278 *
2279 * @returns The @a idx field
2280 * @param u16 The tracking data word. */
2281#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2282/** @} */
2283
2284
2285
2286/** @name A20 gate macros
2287 * @{ */
2288#define PGM_WITH_A20
2289#ifdef PGM_WITH_A20
2290# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2291# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2292# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2293 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2294# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2295#else
2296# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2297# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2298# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2299# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2300#endif
2301/** @} */
2302
2303
2304/**
2305 * Roots and anchors for trees and list employing self relative offsets as
2306 * pointers.
2307 *
2308 * When using self-relative offsets instead of pointers, the offsets needs to be
2309 * the same in all offsets. Thus the roots and anchors needs to live on the
2310 * hyper heap just like the nodes.
2311 */
2312typedef struct PGMTREES
2313{
2314 /** List of physical access handler types (offset pointers) of type
2315 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2316 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2317 /** Physical access handlers (AVL range+offsetptr tree). */
2318 AVLROGCPHYSTREE PhysHandlers;
2319} PGMTREES;
2320/** Pointer to PGM trees. */
2321typedef PGMTREES *PPGMTREES;
2322
2323
2324/**
2325 * Page fault guest state for the AMD64 paging mode.
2326 */
2327typedef struct PGMPTWALKCORE
2328{
2329 /** The guest virtual address that is being resolved by the walk
2330 * (input). */
2331 RTGCPTR GCPtr;
2332
2333 /** The guest physical address that is the result of the walk.
2334 * @remarks only valid if fSucceeded is set. */
2335 RTGCPHYS GCPhys;
2336
2337 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2338 bool fSucceeded;
2339 /** The level problem arrised at.
2340 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2341 * level 8. This is 0 on success. */
2342 uint8_t uLevel;
2343 /** Set if the page isn't present. */
2344 bool fNotPresent;
2345 /** Encountered a bad physical address. */
2346 bool fBadPhysAddr;
2347 /** Set if there was reserved bit violations. */
2348 bool fRsvdError;
2349 /** Set if it involves a big page (2/4 MB). */
2350 bool fBigPage;
2351 /** Set if it involves a gigantic page (1 GB). */
2352 bool fGigantPage;
2353 /** The effective X86_PTE_US flag for the address. */
2354 bool fEffectiveUS;
2355 /** The effective X86_PTE_RW flag for the address. */
2356 bool fEffectiveRW;
2357 /** The effective X86_PTE_NX flag for the address. */
2358 bool fEffectiveNX;
2359 bool afPadding1[2];
2360 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2361 * The NX bit is inverted and shifted down 63 places to bit 0. */
2362 uint32_t fEffective;
2363} PGMPTWALKCORE;
2364
2365/** @name PGMPTWALKCORE::fEffective bits.
2366 * @{ */
2367#if 0
2368/** Effective execute bit (!NX). */
2369#define PGMPTWALK_EFF_X UINT32_C(1)
2370/** Effective read+write access bit. */
2371#define PGMPTWALK_EFF_RW X86_PTE_RW
2372/** Effective user-mode access bit. */
2373#define PGMPTWALK_EFF_US X86_PTE_US
2374/** Effective write through cache bit. */
2375#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2376/** Effective cache disabled bit. */
2377#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2378/** Effective accessed bit. */
2379#define PGMPTWALK_EFF_A X86_PTE_A
2380/** The dirty bit of the final entry. */
2381#define PGMPTWALK_EFF_D X86_PTE_D
2382/** The PAT bit of the final entry. */
2383#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2384/** The global bit of the final entry. */
2385#define PGMPTWALK_EFF_G X86_PTE_G
2386#endif
2387/** Effective execute bit (!NX). */
2388#define PGM_BF_PTWALK_EFF_X_SHIFT 0
2389#define PGM_BF_PTWALK_EFF_X_MASK UINT32_C(0x00000001)
2390/** Effective read+write access bit. */
2391#define PGM_BF_PTWALK_EFF_RW_SHIFT 1
2392#define PGM_BF_PTWALK_EFF_RW_MASK UINT32_C(0x00000002)
2393/** Effective user-mode access bit. */
2394#define PGM_BF_PTWALK_EFF_US_SHIFT 2
2395#define PGM_BF_PTWALK_EFF_US_MASK UINT32_C(0x00000004)
2396/** Effective write through cache bit. */
2397#define PGM_BF_PTWALK_EFF_PWT_SHIFT 3
2398#define PGM_BF_PTWALK_EFF_PWT_MASK UINT32_C(0x00000008)
2399/** Effective cache disabled bit. */
2400#define PGM_BF_PTWALK_EFF_PCD_SHIFT 4
2401#define PGM_BF_PTWALK_EFF_PCD_MASK UINT32_C(0x00000010)
2402/** Effective accessed bit. */
2403#define PGM_BF_PTWALK_EFF_A_SHIFT 5
2404#define PGM_BF_PTWALK_EFF_A_MASK UINT32_C(0x00000020)
2405/** The dirty bit of the final entry. */
2406#define PGM_BF_PTWALK_EFF_D_SHIFT 6
2407#define PGM_BF_PTWALK_EFF_D_MASK UINT32_C(0x00000040)
2408/** The PAT bit of the final entry. */
2409#define PGM_BF_PTWALK_EFF_PAT_SHIFT 7
2410#define PGM_BF_PTWALK_EFF_PAT_MASK UINT32_C(0x00000080)
2411/** The global bit of the final entry. */
2412#define PGM_BF_PTWALK_EFF_G_SHIFT 8
2413#define PGM_BF_PTWALK_EFF_G_MASK UINT32_C(0x00000100)
2414/** Reserved (bits 11:9) unused. */
2415#define PGM_BF_PTWALK_EFF_RSVD_11_9_SHIFT 9
2416#define PGM_BF_PTWALK_EFF_RSVD_11_9_MASK UINT32_C(0x00000e00)
2417/** Effective read access bit - EPT only. */
2418#define PGM_BF_PTWALK_EFF_R_SHIFT 12
2419#define PGM_BF_PTWALK_EFF_R_MASK UINT32_C(0x00001000)
2420/** Effective write access bit - EPT only. */
2421#define PGM_BF_PTWALK_EFF_W_SHIFT 13
2422#define PGM_BF_PTWALK_EFF_W_MASK UINT32_C(0x00002000)
2423/** Effective execute access for supervisor-mode - EPT only. */
2424#define PGM_BF_PTWALK_EFF_X_SUPER_SHIFT 14
2425#define PGM_BF_PTWALK_EFF_X_SUPER_MASK UINT32_C(0x00004000)
2426/** Effective EPT memory type - EPT only. */
2427#define PGM_BF_PTWALK_EFF_MEMTYPE_SHIFT 15
2428#define PGM_BF_PTWALK_EFF_MEMTYPE_MASK UINT32_C(0x00038000)
2429/** Effective ignore PAT memory type - EPT only. */
2430#define PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT 18
2431#define PGM_BF_PTWALK_EFF_IGNORE_PAT_MASK UINT32_C(0x00040000)
2432/** Reserved (bits 21:19) unused. */
2433#define PGM_BF_PTWALK_EFF_RSVD_21_19_SHIFT 19
2434#define PGM_BF_PTWALK_EFF_RSVD_21_19_MASK UINT32_C(0x00380000)
2435/** Effective execute access for user-mode - EPT only. */
2436#define PGM_BF_PTWALK_EFF_X_USER_SHIFT 22
2437#define PGM_BF_PTWALK_EFF_X_USER_MASK UINT32_C(0x00400000)
2438/** Reserved (bits 31:23) - unused. */ /** @todo When implementing SUPER_SHW_STACK, Suppress \#VE put them in bits 24, 25 which corresponds to bit 12, 13 of EPT attributes. */
2439#define PGM_BF_PTWALK_EFF_RSVD_31_23_SHIFT 23
2440#define PGM_BF_PTWALK_EFF_RSVD_31_23_MASK UINT32_C(0xff800000)
2441RT_BF_ASSERT_COMPILE_CHECKS(PGM_BF_PTWALK_EFF_, UINT32_C(0), UINT32_MAX,
2442 (X, RW, US, PWT, PCD, A, D, PAT, G, RSVD_11_9, R, W, X_SUPER, MEMTYPE, IGNORE_PAT, RSVD_21_19,
2443 X_USER, RSVD_31_23));
2444
2445/** The bit count where the EPT specific bits begin. */
2446#define PGMPTWALK_EFF_EPT_ATTR_SHIFT PGM_BF_PTWALK_EFF_R_SHIFT
2447/** The mask of EPT bits (bits 31:ATTR_SHIFT). In the future we might choose to
2448 * use higher unused EPT bits for something else, in that case reduce this mask. */
2449#define PGMPTWALK_EFF_EPT_ATTR_MASK UINT32_C(0xfffff000)
2450
2451/* Verify bits match the regular PT bits. */
2452AssertCompile(PGM_BF_PTWALK_EFF_RW_SHIFT == X86_PTE_BIT_RW);
2453AssertCompile(PGM_BF_PTWALK_EFF_US_SHIFT == X86_PTE_BIT_US);
2454AssertCompile(PGM_BF_PTWALK_EFF_PWT_SHIFT == X86_PTE_BIT_PWT);
2455AssertCompile(PGM_BF_PTWALK_EFF_PCD_SHIFT == X86_PTE_BIT_PCD);
2456AssertCompile(PGM_BF_PTWALK_EFF_A_SHIFT == X86_PTE_BIT_A);
2457AssertCompile(PGM_BF_PTWALK_EFF_D_SHIFT == X86_PTE_BIT_D);
2458AssertCompile(PGM_BF_PTWALK_EFF_PAT_SHIFT == X86_PTE_BIT_PAT);
2459AssertCompile(PGM_BF_PTWALK_EFF_G_SHIFT == X86_PTE_BIT_G);
2460AssertCompile(PGM_BF_PTWALK_EFF_RW_MASK == X86_PTE_RW);
2461AssertCompile(PGM_BF_PTWALK_EFF_US_MASK == X86_PTE_US);
2462AssertCompile(PGM_BF_PTWALK_EFF_PWT_MASK == X86_PTE_PWT);
2463AssertCompile(PGM_BF_PTWALK_EFF_PCD_MASK == X86_PTE_PCD);
2464AssertCompile(PGM_BF_PTWALK_EFF_A_MASK == X86_PTE_A);
2465AssertCompile(PGM_BF_PTWALK_EFF_D_MASK == X86_PTE_D);
2466AssertCompile(PGM_BF_PTWALK_EFF_PAT_MASK == X86_PTE_PAT);
2467AssertCompile(PGM_BF_PTWALK_EFF_G_MASK == X86_PTE_G);
2468
2469/*
2470 * The following bits map 1:1 (left shifted by PGMPTWALK_EFF_EPT_ATTR_SHIFT bits) with
2471 * VMX EPT attribute bits because these are unique to EPT and fit within 32-bits:
2472 * - R, W, X_SUPER, MEMTYPE, IGNORE_PAT, X_USER.
2473 *
2474 * The following bits are moved to the regular PT bit positions because they already
2475 * exist for regular page tables:
2476 * - A, D.
2477 */
2478AssertCompile(PGM_BF_PTWALK_EFF_R_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_READ);
2479AssertCompile(PGM_BF_PTWALK_EFF_W_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_WRITE);
2480AssertCompile(PGM_BF_PTWALK_EFF_X_SUPER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_EXECUTE);
2481AssertCompile(PGM_BF_PTWALK_EFF_IGNORE_PAT_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_IGNORE_PAT);
2482AssertCompile(PGM_BF_PTWALK_EFF_X_USER_SHIFT - PGMPTWALK_EFF_EPT_ATTR_SHIFT == EPT_E_BIT_USER_EXECUTE);
2483/** @} */
2484
2485
2486/**
2487 * Guest page table walk for the AMD64 mode.
2488 */
2489typedef struct PGMPTWALKGSTAMD64
2490{
2491 /** The common core. */
2492 PGMPTWALKCORE Core;
2493
2494 PX86PML4 pPml4;
2495 PX86PML4E pPml4e;
2496 X86PML4E Pml4e;
2497
2498 PX86PDPT pPdpt;
2499 PX86PDPE pPdpe;
2500 X86PDPE Pdpe;
2501
2502 PX86PDPAE pPd;
2503 PX86PDEPAE pPde;
2504 X86PDEPAE Pde;
2505
2506 PX86PTPAE pPt;
2507 PX86PTEPAE pPte;
2508 X86PTEPAE Pte;
2509} PGMPTWALKGSTAMD64;
2510/** Pointer to a AMD64 guest page table walk. */
2511typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2512/** Pointer to a const AMD64 guest page table walk. */
2513typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2514
2515#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2516/**
2517 * Guest page table walk for the EPT mode.
2518 */
2519typedef struct PGMPTWALKGSTEPT
2520{
2521 /** The common core. */
2522 PGMPTWALKCORE Core;
2523
2524 PEPTPML4 pPml4;
2525 PEPTPML4E pPml4e;
2526 EPTPML4E Pml4e;
2527
2528 PEPTPDPT pPdpt;
2529 PEPTPDPTE pPdpte;
2530 EPTPDPTE Pdpte;
2531
2532 PEPTPD pPd;
2533 PEPTPDE pPde;
2534 EPTPDE Pde;
2535
2536 PEPTPT pPt;
2537 PEPTPTE pPte;
2538 EPTPTE Pte;
2539} PGMPTWALKGSTEPT;
2540/** Pointer to an EPT guest page table walk. */
2541typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2542/** Pointer to a const EPT guest page table walk. */
2543typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2544#endif
2545
2546/**
2547 * Guest page table walk for the PAE mode.
2548 */
2549typedef struct PGMPTWALKGSTPAE
2550{
2551 /** The common core. */
2552 PGMPTWALKCORE Core;
2553
2554 PX86PDPT pPdpt;
2555 PX86PDPE pPdpe;
2556 X86PDPE Pdpe;
2557
2558 PX86PDPAE pPd;
2559 PX86PDEPAE pPde;
2560 X86PDEPAE Pde;
2561
2562 PX86PTPAE pPt;
2563 PX86PTEPAE pPte;
2564 X86PTEPAE Pte;
2565} PGMPTWALKGSTPAE;
2566/** Pointer to a PAE guest page table walk. */
2567typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2568/** Pointer to a const AMD64 guest page table walk. */
2569typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2570
2571/**
2572 * Guest page table walk for the 32-bit mode.
2573 */
2574typedef struct PGMPTWALKGST32BIT
2575{
2576 /** The common core. */
2577 PGMPTWALKCORE Core;
2578
2579 PX86PD pPd;
2580 PX86PDE pPde;
2581 X86PDE Pde;
2582
2583 PX86PT pPt;
2584 PX86PTE pPte;
2585 X86PTE Pte;
2586} PGMPTWALKGST32BIT;
2587/** Pointer to a 32-bit guest page table walk. */
2588typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2589/** Pointer to a const 32-bit guest page table walk. */
2590typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2591
2592/**
2593 * Which part of PGMPTWALKGST that is valid.
2594 */
2595typedef enum PGMPTWALKGSTTYPE
2596{
2597 /** Customary invalid 0 value. */
2598 PGMPTWALKGSTTYPE_INVALID = 0,
2599 /** PGMPTWALKGST::u.Amd64 is valid. */
2600 PGMPTWALKGSTTYPE_AMD64,
2601 /** PGMPTWALKGST::u.Pae is valid. */
2602 PGMPTWALKGSTTYPE_PAE,
2603 /** PGMPTWALKGST::u.Legacy is valid. */
2604 PGMPTWALKGSTTYPE_32BIT,
2605 /** PGMPTWALKGST::u.Ept is valid. */
2606 PGMPTWALKGSTTYPE_EPT,
2607 /** Customary 32-bit type hack. */
2608 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2609} PGMPTWALKGSTTYPE;
2610
2611/**
2612 * Combined guest page table walk result.
2613 */
2614typedef struct PGMPTWALKGST
2615{
2616 union
2617 {
2618 /** The page walker core - always valid. */
2619 PGMPTWALKCORE Core;
2620 /** The page walker for AMD64. */
2621 PGMPTWALKGSTAMD64 Amd64;
2622 /** The page walker for PAE (32-bit). */
2623 PGMPTWALKGSTPAE Pae;
2624 /** The page walker for 32-bit paging (called legacy due to C naming
2625 * convension). */
2626 PGMPTWALKGST32BIT Legacy;
2627#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2628 /** The page walker for EPT. */
2629 PGMPTWALKGSTEPT Ept;
2630#endif
2631 } u;
2632 /** Indicates which part of the union is valid. */
2633 PGMPTWALKGSTTYPE enmType;
2634} PGMPTWALKGST;
2635/** Pointer to a combined guest page table walk result. */
2636typedef PGMPTWALKGST *PPGMPTWALKGST;
2637/** Pointer to a read-only combined guest page table walk result. */
2638typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2639
2640
2641/** @name Paging mode macros
2642 * @{
2643 */
2644#ifdef IN_RING3
2645# define PGM_CTX(a,b) a##R3##b
2646# define PGM_CTX_STR(a,b) a "R3" b
2647# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2648#elif defined(IN_RING0)
2649# define PGM_CTX(a,b) a##R0##b
2650# define PGM_CTX_STR(a,b) a "R0" b
2651# define PGM_CTX_DECL(type) VMMDECL(type)
2652#else
2653# error "Not IN_RING3 or IN_RING0!"
2654#endif
2655
2656#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2657#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2658#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2659#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2660#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2661#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2662#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2663#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2664#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2665#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2666#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2667#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2668#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2669#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2670#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2671#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2672# define PGM_GST_NAME_EPT(name) PGM_CTX(pgm,GstEPT##name)
2673# define PGM_GST_NAME_RC_EPT_STR(name) "pgmRCGstEPT" #name
2674# define PGM_GST_NAME_R0_EPT_STR(name) "pgmR0GstEPT" #name
2675#endif
2676#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2677
2678#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2679#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2680#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2681#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2682#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2683#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2684#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2685#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2686#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2687#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2688#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2689#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2690#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2691#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2692#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2693#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2694#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2695#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2696#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2697#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2698#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2699#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2700#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2701#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2702#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2703
2704/* Shw_Gst */
2705#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2706#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2707#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2708#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2709#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2710#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2711#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2712#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2713#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2714#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2715#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2716#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2717#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2718#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2719#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2720#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2721#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2722#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2723#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2724#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2725#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2726#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2727#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2728#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2729#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2730#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2731#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2732#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2733#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2734#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2735# define PGM_BTH_NAME_EPT_EPT(name) PGM_CTX(pgm,BthEPTEPT##name)
2736#endif
2737#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2738#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2739#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2740#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2741#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2742
2743#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2744#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2745#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2746#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2747#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2748#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2749#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2750#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2751#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2752#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2753#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2754#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2755#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2756#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2757#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2758#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2759#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2760#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2761#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2762#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2763#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2764#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2765#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2766#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2767#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2768#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2769#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2770#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2771#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2772# define PGM_BTH_NAME_RC_EPT_EPT_STR(name) "pgmRCBthEPTEPT" #name
2773#endif
2774
2775#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2776#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2777#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2778#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2779#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2780#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2781#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2782#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2783#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2784#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2785#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2786#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2787#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2788#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2789#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2790#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2791#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2792#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2793#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2794#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2795#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2796#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2797#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2798#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2799#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2800#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2801#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2802#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2803#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2804#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2805# define PGM_BTH_NAME_R0_EPT_EPT_STR(name) "pgmR0BthEPTEPT" #name
2806#endif
2807
2808#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2809/** @} */
2810
2811
2812/**
2813 * Function pointers for guest paging.
2814 */
2815typedef struct PGMMODEDATAGST
2816{
2817 /** The guest mode type. */
2818 uint32_t uType;
2819 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2820 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2821 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2822 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2823#ifdef IN_RING3
2824 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2825#endif
2826} PGMMODEDATAGST;
2827
2828/** The length of g_aPgmGuestModeData. */
2829#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
2830# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_EPT + 1)
2831#elif defined(VBOX_WITH_64_BITS_GUESTS)
2832# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2833#else
2834# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2835#endif
2836/** The guest mode data array. */
2837extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2838
2839
2840/**
2841 * Function pointers for shadow paging.
2842 */
2843typedef struct PGMMODEDATASHW
2844{
2845 /** The shadow mode type. */
2846 uint32_t uType;
2847 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2848 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2849 uint64_t fMask, uint32_t fOpFlags));
2850 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2851 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2852#ifdef IN_RING3
2853 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2854#endif
2855} PGMMODEDATASHW;
2856
2857/** The length of g_aPgmShadowModeData. */
2858#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2859/** The shadow mode data array. */
2860extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2861
2862
2863/**
2864 * Function pointers for guest+shadow paging.
2865 */
2866typedef struct PGMMODEDATABTH
2867{
2868 /** The shadow mode type. */
2869 uint32_t uShwType;
2870 /** The guest mode type. */
2871 uint32_t uGstType;
2872
2873 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2874 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2875 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2876 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2877 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3, bool fPdpesMapped));
2878 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2879 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2880#ifndef IN_RING3
2881 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2882#endif
2883#ifdef VBOX_STRICT
2884 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2885#endif
2886} PGMMODEDATABTH;
2887
2888/** The length of g_aPgmBothModeData. */
2889#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2890/** The guest+shadow mode data array. */
2891extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2892
2893
2894#ifdef VBOX_WITH_STATISTICS
2895/**
2896 * PGM statistics.
2897 */
2898typedef struct PGMSTATS
2899{
2900 /* R3 only: */
2901 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2902 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2903
2904 /* R3+RZ */
2905 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2906 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2907 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2908 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2909 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2910 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2911 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2912 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2913 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2914 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2915 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2916 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2917 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2918 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2919 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2920 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2921 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2922 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2923 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2924 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2925 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2926 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2927/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2928 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2929 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2930/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2931
2932 /* RC only: */
2933 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2934 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2935
2936 STAMCOUNTER StatRZPhysRead;
2937 STAMCOUNTER StatRZPhysReadBytes;
2938 STAMCOUNTER StatRZPhysWrite;
2939 STAMCOUNTER StatRZPhysWriteBytes;
2940 STAMCOUNTER StatR3PhysRead;
2941 STAMCOUNTER StatR3PhysReadBytes;
2942 STAMCOUNTER StatR3PhysWrite;
2943 STAMCOUNTER StatR3PhysWriteBytes;
2944 STAMCOUNTER StatRCPhysRead;
2945 STAMCOUNTER StatRCPhysReadBytes;
2946 STAMCOUNTER StatRCPhysWrite;
2947 STAMCOUNTER StatRCPhysWriteBytes;
2948
2949 STAMCOUNTER StatRZPhysSimpleRead;
2950 STAMCOUNTER StatRZPhysSimpleReadBytes;
2951 STAMCOUNTER StatRZPhysSimpleWrite;
2952 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2953 STAMCOUNTER StatR3PhysSimpleRead;
2954 STAMCOUNTER StatR3PhysSimpleReadBytes;
2955 STAMCOUNTER StatR3PhysSimpleWrite;
2956 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2957 STAMCOUNTER StatRCPhysSimpleRead;
2958 STAMCOUNTER StatRCPhysSimpleReadBytes;
2959 STAMCOUNTER StatRCPhysSimpleWrite;
2960 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2961
2962 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2963 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2964 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2965 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2966 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2967 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2968 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2969
2970 /** Time spent by the host OS for large page allocation. */
2971 STAMPROFILE StatAllocLargePage;
2972 /** Time spent clearing the newly allocated large pages. */
2973 STAMPROFILE StatClearLargePage;
2974 /** The number of times allocating a large pages takes more than the allowed period. */
2975 STAMCOUNTER StatLargePageOverflow;
2976 /** pgmPhysIsValidLargePage profiling - R3 */
2977 STAMPROFILE StatR3IsValidLargePage;
2978 /** pgmPhysIsValidLargePage profiling - RZ*/
2979 STAMPROFILE StatRZIsValidLargePage;
2980
2981 STAMPROFILE StatChunkAging;
2982 STAMPROFILE StatChunkFindCandidate;
2983 STAMPROFILE StatChunkUnmap;
2984 STAMPROFILE StatChunkMap;
2985} PGMSTATS;
2986#endif /* VBOX_WITH_STATISTICS */
2987
2988
2989/**
2990 * PGM Data (part of VM)
2991 */
2992typedef struct PGM
2993{
2994 /** @cfgm{/RamPreAlloc, boolean, false}
2995 * Indicates whether the base RAM should all be allocated before starting
2996 * the VM (default), or if it should be allocated when first written to.
2997 */
2998 bool fRamPreAlloc;
2999#ifdef VBOX_WITH_PGM_NEM_MODE
3000 /** Set if we're operating in NEM memory mode.
3001 *
3002 * NEM mode implies that memory is allocated in big chunks for each RAM range
3003 * rather than on demand page by page. Memory is also not locked and PGM has
3004 * therefore no physical addresses for them. Page sharing is out of the
3005 * question. Ballooning depends on the native execution engine, but probably
3006 * pointless as well. */
3007 bool fNemMode;
3008# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3009#else
3010# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3011#endif
3012 /** Indicates whether write monitoring is currently in use.
3013 * This is used to prevent conflicts between live saving and page sharing
3014 * detection. */
3015 bool fPhysWriteMonitoringEngaged;
3016 /** Set if the CPU has less than 52-bit physical address width.
3017 * This is used */
3018 bool fLessThan52PhysicalAddressBits;
3019 /** Set when nested paging is active.
3020 * This is meant to save calls to HMIsNestedPagingActive and let the
3021 * compilers optimize the code better. Whether we use nested paging or
3022 * not is something we find out during VMM initialization and we won't
3023 * change this later on. */
3024 bool fNestedPaging;
3025 /** We're not in a state which permits writes to guest memory.
3026 * (Only used in strict builds.) */
3027 bool fNoMorePhysWrites;
3028 /** @cfgm{/PageFusionAllowed, boolean, false}
3029 * Whether page fusion is allowed. */
3030 bool fPageFusionAllowed;
3031 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3032 * Whether PCI passthrough is enabled. */
3033 bool fPciPassthrough;
3034 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3035 uint8_t cMmio2Regions;
3036 /** Restore original ROM page content when resetting after loading state.
3037 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3038 * enables the VM to start using an updated ROM without requiring powering
3039 * down the VM, just rebooting or resetting it. */
3040 bool fRestoreRomPagesOnReset;
3041 /** Whether to automatically clear all RAM pages on reset. */
3042 bool fZeroRamPagesOnReset;
3043 /** Large page enabled flag. */
3044 bool fUseLargePages;
3045 /** Alignment padding. */
3046#ifndef VBOX_WITH_PGM_NEM_MODE
3047 bool afAlignment3[1];
3048#endif
3049 /** The host paging mode. (This is what SUPLib reports.) */
3050 SUPPAGINGMODE enmHostMode;
3051 bool afAlignment3b[2];
3052
3053 /** Generation ID for the RAM ranges. This member is incremented everytime
3054 * a RAM range is linked or unlinked. */
3055 uint32_t volatile idRamRangesGen;
3056
3057 /** Physical access handler type for ROM protection. */
3058 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3059 /** Physical access handler type for MMIO2 dirty page tracing. */
3060 PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3061
3062 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3063 RTGCPHYS GCPhys4MBPSEMask;
3064 /** Mask containing the invalid bits of a guest physical address.
3065 * @remarks this does not stop at bit 52. */
3066 RTGCPHYS GCPhysInvAddrMask;
3067
3068
3069 /** RAM range TLB for R3. */
3070 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3071 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3072 * This is sorted by physical address and contains no overlapping ranges. */
3073 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3074 /** Root of the RAM range search tree for ring-3. */
3075 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3076 /** PGM offset based trees - R3 Ptr. */
3077 R3PTRTYPE(PPGMTREES) pTreesR3;
3078 /** Caching the last physical handler we looked up in R3. */
3079 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3080 /** Shadow Page Pool - R3 Ptr. */
3081 R3PTRTYPE(PPGMPOOL) pPoolR3;
3082 /** Pointer to the list of ROM ranges - for R3.
3083 * This is sorted by physical address and contains no overlapping ranges. */
3084 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3085 /** Pointer to the list of MMIO2 ranges - for R3.
3086 * Registration order. */
3087 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3088 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3089 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3090
3091 /** RAM range TLB for R0. */
3092 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3093 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3094 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3095 /** Root of the RAM range search tree for ring-0. */
3096 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3097 /** PGM offset based trees - R0 Ptr. */
3098 R0PTRTYPE(PPGMTREES) pTreesR0;
3099 /** Caching the last physical handler we looked up in R0. */
3100 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3101 /** Shadow Page Pool - R0 Ptr. */
3102 R0PTRTYPE(PPGMPOOL) pPoolR0;
3103 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3104 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3105 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3106 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3107
3108 /** Hack: Number of deprecated page mapping locks taken by the current lock
3109 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3110 uint32_t cDeprecatedPageLocks;
3111 /** Alignment padding. */
3112 uint32_t au32Alignment2[1];
3113
3114 /** PGM critical section.
3115 * This protects the physical, ram ranges, and the page flag updating (some of
3116 * it anyway).
3117 */
3118 PDMCRITSECT CritSectX;
3119
3120 /**
3121 * Data associated with managing the ring-3 mappings of the allocation chunks.
3122 */
3123 struct
3124 {
3125 /** The chunk mapping TLB. */
3126 PGMCHUNKR3MAPTLB Tlb;
3127 /** The chunk tree, ordered by chunk id. */
3128 R3PTRTYPE(PAVLU32NODECORE) pTree;
3129#if HC_ARCH_BITS == 32
3130 uint32_t u32Alignment0;
3131#endif
3132 /** The number of mapped chunks. */
3133 uint32_t c;
3134 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3135 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3136 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3137 uint32_t cMax;
3138 /** The current time. This is incremented whenever a chunk is inserted. */
3139 uint32_t iNow;
3140 /** Alignment padding. */
3141 uint32_t au32Alignment1[3];
3142 } ChunkR3Map;
3143
3144 /** The page mapping TLB for ring-3. */
3145 PGMPAGER3MAPTLB PhysTlbR3;
3146 /** The page mapping TLB for ring-0. */
3147 PGMPAGER0MAPTLB PhysTlbR0;
3148
3149 /** @name The zero page.
3150 * @{ */
3151 /** The host physical address of the zero page. */
3152 RTHCPHYS HCPhysZeroPg;
3153 /** The ring-3 mapping of the zero page. */
3154 RTR3PTR pvZeroPgR3;
3155 /** The ring-0 mapping of the zero page. */
3156 RTR0PTR pvZeroPgR0;
3157 /** @}*/
3158
3159 /** @name The Invalid MMIO page.
3160 * This page is filled with 0xfeedface.
3161 * @{ */
3162 /** The host physical address of the invalid MMIO page. */
3163 RTHCPHYS HCPhysMmioPg;
3164 /** The host pysical address of the invalid MMIO page plus all invalid
3165 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3166 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3167 RTHCPHYS HCPhysInvMmioPg;
3168 /** The ring-3 mapping of the invalid MMIO page. */
3169 RTR3PTR pvMmioPgR3;
3170#if HC_ARCH_BITS == 32
3171 RTR3PTR R3PtrAlignment4;
3172#endif
3173 /** @} */
3174
3175
3176 /** The number of handy pages. */
3177 uint32_t cHandyPages;
3178
3179 /** The number of large handy pages. */
3180 uint32_t cLargeHandyPages;
3181
3182 /**
3183 * Array of handy pages.
3184 *
3185 * This array is used in a two way communication between pgmPhysAllocPage
3186 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3187 * an intermediary.
3188 *
3189 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3190 * (The current size of 32 pages, means 128 KB of handy memory.)
3191 */
3192 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3193
3194 /**
3195 * Array of large handy pages. (currently size 1)
3196 *
3197 * This array is used in a two way communication between pgmPhysAllocLargePage
3198 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3199 * an intermediary.
3200 */
3201 GMMPAGEDESC aLargeHandyPage[1];
3202
3203 /**
3204 * Live save data.
3205 */
3206 struct
3207 {
3208 /** Per type statistics. */
3209 struct
3210 {
3211 /** The number of ready pages. */
3212 uint32_t cReadyPages;
3213 /** The number of dirty pages. */
3214 uint32_t cDirtyPages;
3215 /** The number of ready zero pages. */
3216 uint32_t cZeroPages;
3217 /** The number of write monitored pages. */
3218 uint32_t cMonitoredPages;
3219 } Rom,
3220 Mmio2,
3221 Ram;
3222 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3223 uint32_t cIgnoredPages;
3224 /** Indicates that a live save operation is active. */
3225 bool fActive;
3226 /** Padding. */
3227 bool afReserved[2];
3228 /** The next history index. */
3229 uint8_t iDirtyPagesHistory;
3230 /** History of the total amount of dirty pages. */
3231 uint32_t acDirtyPagesHistory[64];
3232 /** Short term dirty page average. */
3233 uint32_t cDirtyPagesShort;
3234 /** Long term dirty page average. */
3235 uint32_t cDirtyPagesLong;
3236 /** The number of saved pages. This is used to get some kind of estimate of the
3237 * link speed so we can decide when we're done. It is reset after the first
3238 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3239 * zero pages. */
3240 uint64_t cSavedPages;
3241 /** The nanosecond timestamp when cSavedPages was 0. */
3242 uint64_t uSaveStartNS;
3243 /** Pages per second (for statistics). */
3244 uint32_t cPagesPerSecond;
3245 uint32_t cAlignment;
3246 } LiveSave;
3247
3248 /** @name Error injection.
3249 * @{ */
3250 /** Inject handy page allocation errors pretending we're completely out of
3251 * memory. */
3252 bool volatile fErrInjHandyPages;
3253 /** Padding. */
3254 bool afReserved[3];
3255 /** @} */
3256
3257 /** @name Release Statistics
3258 * @{ */
3259 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3260 uint32_t cPrivatePages; /**< The number of private pages. */
3261 uint32_t cSharedPages; /**< The number of shared pages. */
3262 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3263 uint32_t cZeroPages; /**< The number of zero backed pages. */
3264 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3265 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3266 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3267 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3268 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3269 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3270 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3271 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3272 uint32_t cLargePages; /**< The number of large pages. */
3273 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3274/* uint32_t aAlignment4[1]; */
3275
3276 /** The number of times we were forced to change the hypervisor region location. */
3277 STAMCOUNTER cRelocations;
3278
3279 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3280 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3281 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3282
3283 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3284 /** @} */
3285
3286#ifdef VBOX_WITH_STATISTICS
3287 /** These are optional statistics that used to be on the hyper heap. */
3288 PGMSTATS Stats;
3289#endif
3290} PGM;
3291#ifndef IN_TSTVMSTRUCTGC /* HACK */
3292AssertCompileMemberAlignment(PGM, CritSectX, 8);
3293AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3294AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3295AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3296AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3297AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3298AssertCompileMemberAlignment(PGM, cRelocations, 8);
3299#endif /* !IN_TSTVMSTRUCTGC */
3300/** Pointer to the PGM instance data. */
3301typedef PGM *PPGM;
3302
3303
3304#ifdef VBOX_WITH_STATISTICS
3305/**
3306 * Per CPU statistis for PGM (used to be on the heap).
3307 */
3308typedef struct PGMCPUSTATS
3309{
3310 /* Common */
3311 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3312 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3313
3314 /* R0 only: */
3315 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3316 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3317
3318 /* RZ only: */
3319 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3320 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3321 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3322 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3323 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3324 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3325 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3326 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3327 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3328 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3329 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3330 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3331 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3332 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3333 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3334 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3335 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3336 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3337 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3338 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3339 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3340 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3341 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3342 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3343 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3344 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3345 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3346 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3347 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3348 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3349 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3350 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3351 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3352 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3353 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3354 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3355 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3356 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3357 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3358 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3359 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3360 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3361 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3362 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3363 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3364 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3365 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3366 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3367 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3368 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3369 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3370 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3371 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3372 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3373 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3374 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3375 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3376 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3377 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3378 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3379 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3380 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3381 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3382 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3383 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3384 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3385 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3386 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3387 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3388 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3389
3390 /* HC - R3 and (maybe) R0: */
3391
3392 /* RZ & R3: */
3393 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3394 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3395 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3396 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3397 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3398 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3399 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3400 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3401 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3402 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3403 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3404 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3405 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3406 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3407 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3408 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3409 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3410 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3411 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3412 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3413 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3414 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3415 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3416 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3417 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3418 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3419 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3420 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3421 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3422 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3423 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3424 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3425 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3426 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3427 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3428 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3429 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3430 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3431 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3432 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3433 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3434 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3435 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3436 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3437 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3438 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3439 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3440
3441 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3442 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3443 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3444 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3445 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3446 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3447 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3448 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3449 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3450 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3451 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3452 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3453 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3454 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3455 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3456 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3457 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3458 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3459 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3460 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3461 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3462 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3463 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3464 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3465 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3466 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3467 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3468 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3469 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3470 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3471 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3472 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3473 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3474 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3475 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3476 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3477 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3478 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3479 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3480 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3481 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3482 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3483 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3484 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3485 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3486 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3487} PGMCPUSTATS;
3488#endif /* VBOX_WITH_STATISTICS */
3489
3490
3491/**
3492 * PGMCPU Data (part of VMCPU).
3493 */
3494typedef struct PGMCPU
3495{
3496 /** A20 gate mask.
3497 * Our current approach to A20 emulation is to let REM do it and don't bother
3498 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3499 * But whould need arrise, we'll subject physical addresses to this mask. */
3500 RTGCPHYS GCPhysA20Mask;
3501 /** A20 gate state - boolean! */
3502 bool fA20Enabled;
3503 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3504 bool fNoExecuteEnabled;
3505 /** Unused bits. */
3506 bool afUnused[2];
3507
3508 /** What needs syncing (PGM_SYNC_*).
3509 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3510 * PGMFlushTLB, and PGMR3Load. */
3511 uint32_t fSyncFlags;
3512
3513 /** The shadow paging mode. */
3514 PGMMODE enmShadowMode;
3515 /** The guest paging mode. */
3516 PGMMODE enmGuestMode;
3517 /** Guest mode data table index (PGM_TYPE_XXX). */
3518 uint8_t volatile idxGuestModeData;
3519 /** Shadow mode data table index (PGM_TYPE_XXX). */
3520 uint8_t volatile idxShadowModeData;
3521 /** Both mode data table index (complicated). */
3522 uint8_t volatile idxBothModeData;
3523 /** Alignment padding. */
3524 uint8_t abPadding[5];
3525
3526 /** The current physical address represented in the guest CR3 register. */
3527 RTGCPHYS GCPhysCR3;
3528
3529 /** @name 32-bit Guest Paging.
3530 * @{ */
3531 /** The guest's page directory, R3 pointer. */
3532 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3533 /** The guest's page directory, R0 pointer. */
3534 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3535 /** Mask containing the MBZ bits of a big page PDE. */
3536 uint32_t fGst32BitMbzBigPdeMask;
3537 /** Set if the page size extension (PSE) is enabled. */
3538 bool fGst32BitPageSizeExtension;
3539 /** Alignment padding. */
3540 bool afAlignment2[3];
3541 /** @} */
3542
3543 /** @name PAE Guest Paging.
3544 * @{ */
3545 /** The guest's page directory pointer table, R3 pointer. */
3546 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3547 /** The guest's page directory pointer table, R0 pointer. */
3548 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3549
3550 /** The guest's page directories, R3 pointers.
3551 * These are individual pointers and don't have to be adjacent.
3552 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3553 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3554 /** The guest's page directories, R0 pointers.
3555 * Same restrictions as apGstPaePDsR3. */
3556 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3557 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3558 RTGCPHYS aGCPhysGstPaePDs[4];
3559 /** The physical addresses of the monitored guest page directories (PAE). */
3560 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3561 /** Mask containing the MBZ PTE bits. */
3562 uint64_t fGstPaeMbzPteMask;
3563 /** Mask containing the MBZ PDE bits. */
3564 uint64_t fGstPaeMbzPdeMask;
3565 /** Mask containing the MBZ big page PDE bits. */
3566 uint64_t fGstPaeMbzBigPdeMask;
3567 /** Mask containing the MBZ PDPE bits. */
3568 uint64_t fGstPaeMbzPdpeMask;
3569 /** @} */
3570
3571 /** @name AMD64 Guest Paging.
3572 * @{ */
3573 /** The guest's page directory pointer table, R3 pointer. */
3574 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3575 /** The guest's page directory pointer table, R0 pointer. */
3576 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3577 /** Mask containing the MBZ PTE bits. */
3578 uint64_t fGstAmd64MbzPteMask;
3579 /** Mask containing the MBZ PDE bits. */
3580 uint64_t fGstAmd64MbzPdeMask;
3581 /** Mask containing the MBZ big page PDE bits. */
3582 uint64_t fGstAmd64MbzBigPdeMask;
3583 /** Mask containing the MBZ PDPE bits. */
3584 uint64_t fGstAmd64MbzPdpeMask;
3585 /** Mask containing the MBZ big page PDPE bits. */
3586 uint64_t fGstAmd64MbzBigPdpeMask;
3587 /** Mask containing the MBZ PML4E bits. */
3588 uint64_t fGstAmd64MbzPml4eMask;
3589 /** Mask containing the PDPE bits that we shadow. */
3590 uint64_t fGstAmd64ShadowedPdpeMask;
3591 /** Mask containing the PML4E bits that we shadow. */
3592 uint64_t fGstAmd64ShadowedPml4eMask;
3593 /** @} */
3594
3595 /** @name PAE and AMD64 Guest Paging.
3596 * @{ */
3597 /** Mask containing the PTE bits that we shadow. */
3598 uint64_t fGst64ShadowedPteMask;
3599 /** Mask containing the PDE bits that we shadow. */
3600 uint64_t fGst64ShadowedPdeMask;
3601 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3602 uint64_t fGst64ShadowedBigPdeMask;
3603 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3604 uint64_t fGst64ShadowedBigPde4PteMask;
3605 /** @} */
3606
3607 /** @name EPT Guest Paging.
3608 * @{ */
3609 /** The guest's page directory pointer table, R3 pointer. */
3610 R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3611 /** The guest's page directory pointer table, R0 pointer. */
3612 R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3613 /** The guest's EPT pointer (copy of virtual VMCS). */
3614 uint64_t uEptPtr;
3615 /** Mask containing the MBZ PTE bits. */
3616 uint64_t fGstEptMbzPteMask;
3617 /** Mask containing the MBZ PDE bits. */
3618 uint64_t fGstEptMbzPdeMask;
3619 /** Mask containing the MBZ big page (2M) PDE bits. */
3620 uint64_t fGstEptMbzBigPdeMask;
3621 /** Mask containing the MBZ PDPTE bits. */
3622 uint64_t fGstEptMbzPdpteMask;
3623 /** Mask containing the MBZ big page (1G) PDPTE bits. */
3624 uint64_t fGstEptMbzBigPdpteMask;
3625 /** Mask containing the MBZ PML4E bits. */
3626 uint64_t fGstEptMbzPml4eMask;
3627 /** Mask to determine whether an entry is present. */
3628 uint64_t fGstEptPresentMask;
3629 /** Mask containing the PML4E bits that we shadow. */
3630 uint64_t fGstEptShadowedPml4eMask;
3631 /** Mask containing the PDPE bits that we shadow. */
3632 uint64_t fGstEptShadowedPdpeMask;
3633 /** Mask containing the big page PDPE bits that we shadow. */
3634 uint64_t fGstEptShadowedBigPdpeMask;
3635 /** Mask containing the PDE bits that we shadow. */
3636 uint64_t fGstEptShadowedPdeMask;
3637 /** Mask containing the big page PDE bits that we shadow. */
3638 uint64_t fGstEptShadowedBigPdeMask;
3639 /** Mask containing the PTE bits that we shadow. */
3640 uint64_t fGstEptShadowedPteMask;
3641 /** @} */
3642
3643 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3644 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3645 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3646 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3647
3648 /** For saving stack space, the disassembler state is allocated here instead of
3649 * on the stack. */
3650 DISCPUSTATE DisState;
3651
3652 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3653 uint64_t cNetwareWp0Hacks;
3654
3655 /** Count the number of pgm pool access handler calls. */
3656 uint64_t cPoolAccessHandler;
3657
3658 /** @name Release Statistics
3659 * @{ */
3660 /** The number of times the guest has switched mode since last reset or statistics reset. */
3661 STAMCOUNTER cGuestModeChanges;
3662 /** The number of times the guest has switched mode since last reset or statistics reset. */
3663 STAMCOUNTER cA20Changes;
3664 /** @} */
3665
3666#ifdef VBOX_WITH_STATISTICS
3667 /** These are statistics that used to be on the hyper heap. */
3668 PGMCPUSTATS Stats;
3669#endif
3670} PGMCPU;
3671/** Pointer to the per-cpu PGM data. */
3672typedef PGMCPU *PPGMCPU;
3673
3674
3675/** @name PGM::fSyncFlags Flags
3676 * @note Was part of saved state a long time ago.
3677 * @{
3678 */
3679/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3680/** Always sync CR3. */
3681#define PGM_SYNC_ALWAYS RT_BIT(1)
3682/** Check guest mapping in SyncCR3. */
3683#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3684/** Clear the page pool (a light weight flush). */
3685#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3686#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3687/** @} */
3688
3689
3690/**
3691 * PGM GVMCPU instance data.
3692 */
3693typedef struct PGMR0PERVCPU
3694{
3695#ifdef VBOX_WITH_STATISTICS
3696 /** R0: Which statistic this \#PF should be attributed to. */
3697 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3698#endif
3699 uint64_t u64Dummy;
3700} PGMR0PERVCPU;
3701
3702
3703/**
3704 * PGM GVM instance data.
3705 */
3706typedef struct PGMR0PERVM
3707{
3708 /** @name PGM Pool related stuff.
3709 * @{ */
3710 /** Critical section for serializing pool growth. */
3711 RTCRITSECT PoolGrowCritSect;
3712 /** The memory objects for the pool pages. */
3713 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3714 /** The ring-3 mapping objects for the pool pages. */
3715 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3716 /** @} */
3717} PGMR0PERVM;
3718
3719RT_C_DECLS_BEGIN
3720
3721#if defined(VBOX_STRICT)
3722int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3723# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3724# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3725#else
3726int pgmLock(PVMCC pVM, bool fVoid);
3727# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3728# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3729#endif
3730void pgmUnlock(PVMCC pVM);
3731# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3732/**
3733 * Asserts that the caller owns the PDM lock.
3734 * This is the internal variant of PGMIsLockOwner.
3735 * @param a_pVM Pointer to the VM.
3736 */
3737#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3738/**
3739 * Asserts that the caller owns the PDM lock.
3740 * This is the internal variant of PGMIsLockOwner.
3741 * @param a_pVM Pointer to the VM.
3742 * @param a_pVCpu The current CPU handle.
3743 */
3744#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3745
3746int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3747 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3748int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3749int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3750int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3751int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3752void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3753bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3754void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3755DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3756DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3757int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3758
3759int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3760int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3761int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3762int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3763int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3764void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3765int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3766int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3767int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3768int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3769int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3770int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3771int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3772int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3773int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3774int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3775void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3776PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3777PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3778#ifndef IN_RING3
3779DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3780DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3781DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3782DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3783#endif
3784int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3785 PGMPAGETYPE enmNewType);
3786void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3787void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3788void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3789PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3790PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3791PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3792int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3793int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3794#ifdef VBOX_WITH_NATIVE_NEM
3795void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3796#endif
3797
3798#ifdef IN_RING3
3799void pgmR3PhysRelinkRamRanges(PVM pVM);
3800int pgmR3PhysRamPreAllocate(PVM pVM);
3801int pgmR3PhysRamReset(PVM pVM);
3802int pgmR3PhysRomReset(PVM pVM);
3803int pgmR3PhysRamZeroAll(PVM pVM);
3804int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3805int pgmR3PhysRamTerm(PVM pVM);
3806void pgmR3PhysRomTerm(PVM pVM);
3807void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3808
3809int pgmR3PoolInit(PVM pVM);
3810void pgmR3PoolRelocate(PVM pVM);
3811void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3812void pgmR3PoolReset(PVM pVM);
3813void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3814DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3815void pgmR3PoolWriteProtectPages(PVM pVM);
3816
3817#endif /* IN_RING3 */
3818int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3819 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3820void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3821void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3822int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3823void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3824PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3825PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3826int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3827int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3828bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3829void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3830int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3831void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3832uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3833void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3834void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3835void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3836PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3837#ifndef IN_RING3
3838DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3839#endif
3840
3841void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3842void pgmPoolResetDirtyPages(PVMCC pVM);
3843void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3844
3845int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3846int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3847void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3848
3849int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3850int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3851int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3852
3853int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3854int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3855int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3856int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3857#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3858int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3859#endif
3860int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3861int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3862
3863# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3864FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3865FNDBGCCMD pgmR3CmdShowSharedModules;
3866# endif
3867
3868void pgmLogState(PVM pVM);
3869
3870RT_C_DECLS_END
3871
3872/** @} */
3873
3874#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3875
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