VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 92381

Last change on this file since 92381 was 92381, checked in by vboxsync, 3 years ago

VMM/PGM: Don't flush the VCPU TLB unless necessary after allocating a large page, but make sure we check for mappings of the zero page. bugref:10093
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1/* $Id: PGMInternal.h 92381 2021-11-11 20:47:44Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19#define VMM_INCLUDED_SRC_include_PGMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/dbg.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/param.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/mm.h>
32#include <VBox/vmm/pdmcritsect.h>
33#include <VBox/vmm/pdmapi.h>
34#include <VBox/dis.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/log.h>
37#include <VBox/vmm/gmm.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <iprt/asm.h>
41#include <iprt/assert.h>
42#include <iprt/avl.h>
43#include <iprt/critsect.h>
44#include <iprt/list-off32.h>
45#include <iprt/sha.h>
46
47
48
49/** @defgroup grp_pgm_int Internals
50 * @ingroup grp_pgm
51 * @internal
52 * @{
53 */
54
55
56/** @name PGM Compile Time Config
57 * @{
58 */
59
60/**
61 * Check and skip global PDEs for non-global flushes
62 */
63#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
64
65/**
66 * Optimization for PAE page tables that are modified often
67 */
68//#if 0 /* disabled again while debugging */
69#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
70//#endif
71
72/**
73 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
74 */
75#define PGM_WITH_LARGE_PAGES
76
77/**
78 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
79 * VMX_EXIT_EPT_MISCONFIG.
80 */
81#define PGM_WITH_MMIO_OPTIMIZATIONS
82
83/**
84 * Sync N pages instead of a whole page table
85 */
86#define PGM_SYNC_N_PAGES
87
88/**
89 * Number of pages to sync during a page fault
90 *
91 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
92 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
93 *
94 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
95 * world switch overhead, so let's sync more.
96 */
97#ifdef IN_RING0
98/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
99 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
100 * but ~5% fewer faults.
101 */
102# define PGM_SYNC_NR_PAGES 32
103#else
104# define PGM_SYNC_NR_PAGES 8
105#endif
106
107/**
108 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
109 */
110#define PGM_MAX_PHYSCACHE_ENTRIES 64
111#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
112
113
114/** @def PGMPOOL_CFG_MAX_GROW
115 * The maximum number of pages to add to the pool in one go.
116 */
117#define PGMPOOL_CFG_MAX_GROW (_2M >> PAGE_SHIFT)
118
119/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
120 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
121 */
122#ifdef VBOX_STRICT
123# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
124#endif
125
126/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
127 * Enables the experimental lazy page allocation code. */
128#ifdef DOXYGEN_RUNNING
129# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
130#endif
131
132/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
133 * Enables real write monitoring of pages, i.e. mapping them read-only and
134 * only making them writable when getting a write access \#PF. */
135#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
136
137/** @def VBOX_WITH_PGM_NEM_MODE
138 * Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
139 * details. */
140#ifdef DOXYGEN_RUNNING
141# define VBOX_WITH_PGM_NEM_MODE
142#endif
143
144/** @} */
145
146
147/** @name PDPT and PML4 flags.
148 * These are placed in the three bits available for system programs in
149 * the PDPT and PML4 entries.
150 * @{ */
151/** The entry is a permanent one and it's must always be present.
152 * Never free such an entry. */
153#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154/** PGM specific bits in PML4 entries. */
155#define PGM_PML4_FLAGS 0
156/** PGM specific bits in PDPT entries. */
157#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
158/** @} */
159
160/** @name Page directory flags.
161 * These are placed in the three bits available for system programs in
162 * the page directory entries.
163 * @{ */
164/** Indicates the original entry was a big page.
165 * @remarks This is currently only used for statistics and can be recycled. */
166#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
167/** Made read-only to facilitate dirty bit tracking. */
168#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
169/** @} */
170
171/** @name Page flags.
172 * These are placed in the three bits available for system programs in
173 * the page entries.
174 * @{ */
175/** Made read-only to facilitate dirty bit tracking. */
176#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
177
178#ifndef PGM_PTFLAGS_CSAM_VALIDATED
179/** Scanned and approved by CSAM (tm).
180 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
181 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
182#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
183#endif
184
185/** @} */
186
187/** @name Defines used to indicate the shadow and guest paging in the templates.
188 * @{ */
189#define PGM_TYPE_REAL 1
190#define PGM_TYPE_PROT 2
191#define PGM_TYPE_32BIT 3
192#define PGM_TYPE_PAE 4
193#define PGM_TYPE_AMD64 5
194#define PGM_TYPE_NESTED_32BIT 6
195#define PGM_TYPE_NESTED_PAE 7
196#define PGM_TYPE_NESTED_AMD64 8
197#define PGM_TYPE_EPT 9
198#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
199#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
200#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
201/** @} */
202
203/** @name Defines used to indicate the second-level
204 * address translation (SLAT) modes in the templates.
205 * @{ */
206#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 1)
207#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 2)
208#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 3)
209#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 4)
210/** @} */
211
212/** Macro for checking if the guest is using paging.
213 * @param uGstType PGM_TYPE_*
214 * @param uShwType PGM_TYPE_*
215 * @remark ASSUMES certain order of the PGM_TYPE_* values.
216 */
217#define PGM_WITH_PAGING(uGstType, uShwType) \
218 ( (uGstType) >= PGM_TYPE_32BIT \
219 && (uShwType) < PGM_TYPE_NESTED_32BIT)
220
221/** Macro for checking if the guest supports the NX bit.
222 * @param uGstType PGM_TYPE_*
223 * @param uShwType PGM_TYPE_*
224 * @remark ASSUMES certain order of the PGM_TYPE_* values.
225 */
226#define PGM_WITH_NX(uGstType, uShwType) \
227 ( (uGstType) >= PGM_TYPE_PAE \
228 && (uShwType) < PGM_TYPE_NESTED_32BIT)
229
230/** Macro for checking for nested.
231 * @param uType PGM_TYPE_*
232 */
233#define PGM_TYPE_IS_NESTED(uType) \
234 ( (uType) == PGM_TYPE_NESTED_32BIT \
235 || (uType) == PGM_TYPE_NESTED_PAE \
236 || (uType) == PGM_TYPE_NESTED_AMD64)
237
238/** Macro for checking for nested or EPT.
239 * @param uType PGM_TYPE_*
240 */
241#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
242 ( (uType) == PGM_TYPE_NESTED_32BIT \
243 || (uType) == PGM_TYPE_NESTED_PAE \
244 || (uType) == PGM_TYPE_NESTED_AMD64 \
245 || (uType) == PGM_TYPE_EPT)
246
247
248
249/** @def PGM_HCPHYS_2_PTR
250 * Maps a HC physical page pool address to a virtual address.
251 *
252 * @returns VBox status code.
253 * @param pVM The cross context VM structure.
254 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
255 * @param HCPhys The HC physical address to map to a virtual one.
256 * @param ppv Where to store the virtual address. No need to cast
257 * this.
258 *
259 * @remark There is no need to assert on the result.
260 */
261#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
262
263/** @def PGM_GCPHYS_2_PTR_V2
264 * Maps a GC physical page address to a virtual address.
265 *
266 * @returns VBox status code.
267 * @param pVM The cross context VM structure.
268 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
269 * @param GCPhys The GC physical address to map to a virtual one.
270 * @param ppv Where to store the virtual address. No need to cast this.
271 *
272 * @remark Use with care as we don't have so much dynamic mapping space in
273 * ring-0 on 32-bit darwin and in RC.
274 * @remark There is no need to assert on the result.
275 */
276#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
277 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
278
279/** @def PGM_GCPHYS_2_PTR
280 * Maps a GC physical page address to a virtual address.
281 *
282 * @returns VBox status code.
283 * @param pVM The cross context VM structure.
284 * @param GCPhys The GC physical address to map to a virtual one.
285 * @param ppv Where to store the virtual address. No need to cast this.
286 *
287 * @remark Use with care as we don't have so much dynamic mapping space in
288 * ring-0 on 32-bit darwin and in RC.
289 * @remark There is no need to assert on the result.
290 */
291#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
292
293/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
294 * Maps a GC physical page address to a virtual address.
295 *
296 * @returns VBox status code.
297 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
298 * @param GCPhys The GC physical address to map to a virtual one.
299 * @param ppv Where to store the virtual address. No need to cast this.
300 *
301 * @remark Use with care as we don't have so much dynamic mapping space in
302 * ring-0 on 32-bit darwin and in RC.
303 * @remark There is no need to assert on the result.
304 */
305#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
306
307/** @def PGM_GCPHYS_2_PTR_EX
308 * Maps a unaligned GC physical page address to a virtual address.
309 *
310 * @returns VBox status code.
311 * @param pVM The cross context VM structure.
312 * @param GCPhys The GC physical address to map to a virtual one.
313 * @param ppv Where to store the virtual address. No need to cast this.
314 *
315 * @remark Use with care as we don't have so much dynamic mapping space in
316 * ring-0 on 32-bit darwin and in RC.
317 * @remark There is no need to assert on the result.
318 */
319#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
320 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
321
322/** @def PGM_DYNMAP_UNUSED_HINT
323 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
324 * is no longer used.
325 *
326 * For best effect only apply this to the page that was mapped most recently.
327 *
328 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
329 * @param pvPage The pool page.
330 */
331#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
332
333/** @def PGM_DYNMAP_UNUSED_HINT_VM
334 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335 * is no longer used.
336 *
337 * For best effect only apply this to the page that was mapped most recently.
338 *
339 * @param pVM The cross context VM structure.
340 * @param pvPage The pool page.
341 */
342#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
343
344
345/** @def PGM_INVL_PG
346 * Invalidates a page.
347 *
348 * @param pVCpu The cross context virtual CPU structure.
349 * @param GCVirt The virtual address of the page to invalidate.
350 */
351#ifdef IN_RING0
352# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
353#elif defined(IN_RING3)
354# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
355#else
356# error "Not IN_RING0 or IN_RING3!"
357#endif
358
359/** @def PGM_INVL_PG_ALL_VCPU
360 * Invalidates a page on all VCPUs
361 *
362 * @param pVM The cross context VM structure.
363 * @param GCVirt The virtual address of the page to invalidate.
364 */
365#ifdef IN_RING0
366# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
367#else
368# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
369#endif
370
371/** @def PGM_INVL_BIG_PG
372 * Invalidates a 4MB page directory entry.
373 *
374 * @param pVCpu The cross context virtual CPU structure.
375 * @param GCVirt The virtual address within the page directory to invalidate.
376 */
377#ifdef IN_RING0
378# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
379#else
380# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
381#endif
382
383/** @def PGM_INVL_VCPU_TLBS()
384 * Invalidates the TLBs of the specified VCPU
385 *
386 * @param pVCpu The cross context virtual CPU structure.
387 */
388#ifdef IN_RING0
389# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
390#else
391# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
392#endif
393
394/** @def PGM_INVL_ALL_VCPU_TLBS()
395 * Invalidates the TLBs of all VCPUs
396 *
397 * @param pVM The cross context VM structure.
398 */
399#ifdef IN_RING0
400# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
401#else
402# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
403#endif
404
405
406/** @name Safer Shadow PAE PT/PTE
407 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
408 * present.
409 *
410 * @{
411 */
412#if 1
413/**
414 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
415 * invalid entries for present.
416 * @sa X86PTEPAE.
417 */
418typedef union PGMSHWPTEPAE
419{
420 /** Unsigned integer view */
421 X86PGPAEUINT uCareful;
422 /* Not other views. */
423} PGMSHWPTEPAE;
424
425# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
426# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
427# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
428# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
429# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
430# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
431# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
432# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
433# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
434# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
435# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
436# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
437# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
438# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
439# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
440# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
441
442/**
443 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
444 * invalid entries for present.
445 * @sa X86PTPAE.
446 */
447typedef struct PGMSHWPTPAE
448{
449 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
450} PGMSHWPTPAE;
451
452#else
453typedef X86PTEPAE PGMSHWPTEPAE;
454typedef X86PTPAE PGMSHWPTPAE;
455# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
456# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
457# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
458# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
459# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
460# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
461# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
462# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
463# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
464# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
465# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
466# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
467# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
468# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
469# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
470# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
471
472#endif
473
474/** Pointer to a shadow PAE PTE. */
475typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
476/** Pointer to a const shadow PAE PTE. */
477typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
478
479/** Pointer to a shadow PAE page table. */
480typedef PGMSHWPTPAE *PPGMSHWPTPAE;
481/** Pointer to a const shadow PAE page table. */
482typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
483/** @} */
484
485
486/**
487 * Physical page access handler type registration.
488 */
489typedef struct PGMPHYSHANDLERTYPEINT
490{
491 /** Number of references. */
492 uint32_t volatile cRefs;
493 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
494 uint32_t u32Magic;
495 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
496 RTLISTOFF32NODE ListNode;
497 /** The kind of accesses we're handling. */
498 PGMPHYSHANDLERKIND enmKind;
499 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
500 uint8_t uState;
501 /** Whether to keep the PGM lock when calling the handler. */
502 bool fKeepPgmLock;
503 bool afPadding[2];
504 /** Pointer to R3 callback function. */
505 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
506 /** Pointer to R0 callback function. */
507 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
508 /** Pointer to R0 callback function for \#PFs. */
509 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
510 /** Description / Name. For easing debugging. */
511 R3PTRTYPE(const char *) pszDesc;
512} PGMPHYSHANDLERTYPEINT;
513/** Pointer to a physical access handler type registration. */
514typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
515/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
516#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
517/** Magic value for the physical handler callbacks. */
518#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
519
520/**
521 * Converts a handle to a pointer.
522 * @returns PPGMPHYSHANDLERTYPEINT
523 * @param a_pVM The cross context VM structure.
524 * @param a_hType Physical access handler type handle.
525 */
526#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
527
528
529/**
530 * Physical page access handler structure.
531 *
532 * This is used to keep track of physical address ranges
533 * which are being monitored in some kind of way.
534 */
535typedef struct PGMPHYSHANDLER
536{
537 AVLROGCPHYSNODECORE Core;
538 /** Number of pages to update. */
539 uint32_t cPages;
540 /** Set if we have pages that have been aliased. */
541 uint32_t cAliasedPages;
542 /** Set if we have pages that have temporarily been disabled. */
543 uint32_t cTmpOffPages;
544 /** Registered handler type handle (heap offset). */
545 PGMPHYSHANDLERTYPE hType;
546 /** User argument for R3 handlers. */
547 R3PTRTYPE(void *) pvUserR3;
548 /** User argument for R0 handlers. */
549 R0PTRTYPE(void *) pvUserR0;
550 /** Description / Name. For easing debugging. */
551 R3PTRTYPE(const char *) pszDesc;
552#ifdef VBOX_WITH_STATISTICS
553 /** Profiling of this handler. */
554 STAMPROFILE Stat;
555#endif
556} PGMPHYSHANDLER;
557/** Pointer to a physical page access handler structure. */
558typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
559
560/**
561 * Gets the type record for a physical handler (no reference added).
562 * @returns PPGMPHYSHANDLERTYPEINT
563 * @param a_pVM The cross context VM structure.
564 * @param a_pPhysHandler Pointer to the physical handler structure
565 * (PGMPHYSHANDLER).
566 */
567#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
568
569
570/**
571 * A Physical Guest Page tracking structure.
572 *
573 * The format of this structure is complicated because we have to fit a lot
574 * of information into as few bits as possible. The format is also subject
575 * to change (there is one coming up soon). Which means that for we'll be
576 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
577 * accesses to the structure.
578 */
579typedef union PGMPAGE
580{
581 /** Structured view. */
582 struct
583 {
584 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
585 uint64_t u2HandlerPhysStateY : 2;
586 /** 3:2 - Paging structure needed to map the page
587 * (PGM_PAGE_PDE_TYPE_*). */
588 uint64_t u2PDETypeY : 2;
589 /** 4 - Unused (was used by FTE for dirty tracking). */
590 uint64_t fUnused1 : 1;
591 /** 5 - Flag indicating that a write monitored page was written to
592 * when set. */
593 uint64_t fWrittenToY : 1;
594 /** 7:6 - Unused. */
595 uint64_t u2Unused0 : 2;
596 /** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_*). */
597 uint64_t u2Unused1 : 2;
598 /** 11:10 - NEM state bits. */
599 uint64_t u2NemStateY : 2;
600 /** 12:48 - The host physical frame number (shift left to get the
601 * address). */
602 uint64_t HCPhysFN : 36;
603 /** 50:48 - The page state. */
604 uint64_t uStateY : 3;
605 /** 51:53 - The page type (PGMPAGETYPE). */
606 uint64_t uTypeY : 3;
607 /** 63:54 - PTE index for usage tracking (page pool). */
608 uint64_t u10PteIdx : 10;
609
610 /** The GMM page ID.
611 * @remarks In the current implementation, MMIO2 and pages aliased to
612 * MMIO2 pages will be exploiting this field to calculate the
613 * ring-3 mapping address corresponding to the page.
614 * Later we may consider including MMIO2 management into GMM. */
615 uint32_t idPage;
616 /** Usage tracking (page pool). */
617 uint16_t u16TrackingY;
618 /** The number of read locks on this page. */
619 uint8_t cReadLocksY;
620 /** The number of write locks on this page. */
621 uint8_t cWriteLocksY;
622 } s;
623
624 /** 64-bit integer view. */
625 uint64_t au64[2];
626 /** 16-bit view. */
627 uint32_t au32[4];
628 /** 16-bit view. */
629 uint16_t au16[8];
630 /** 8-bit view. */
631 uint8_t au8[16];
632} PGMPAGE;
633AssertCompileSize(PGMPAGE, 16);
634/** Pointer to a physical guest page. */
635typedef PGMPAGE *PPGMPAGE;
636/** Pointer to a const physical guest page. */
637typedef const PGMPAGE *PCPGMPAGE;
638/** Pointer to a physical guest page pointer. */
639typedef PPGMPAGE *PPPGMPAGE;
640
641
642/**
643 * Clears the page structure.
644 * @param a_pPage Pointer to the physical guest page tracking structure.
645 */
646#define PGM_PAGE_CLEAR(a_pPage) \
647 do { \
648 (a_pPage)->au64[0] = 0; \
649 (a_pPage)->au64[1] = 0; \
650 } while (0)
651
652/**
653 * Initializes the page structure.
654 * @param a_pPage Pointer to the physical guest page tracking structure.
655 * @param a_HCPhys The host physical address of the page.
656 * @param a_idPage The (GMM) page ID of the page.
657 * @param a_uType The page type (PGMPAGETYPE).
658 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
659 */
660#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
661 do { \
662 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
663 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
664 (a_pPage)->au64[0] = SetHCPhysTmp; \
665 (a_pPage)->au64[1] = 0; \
666 (a_pPage)->s.idPage = (a_idPage); \
667 (a_pPage)->s.uStateY = (a_uState); \
668 (a_pPage)->s.uTypeY = (a_uType); \
669 } while (0)
670
671/**
672 * Initializes the page structure of a ZERO page.
673 * @param a_pPage Pointer to the physical guest page tracking structure.
674 * @param a_pVM The VM handle (for getting the zero page address).
675 * @param a_uType The page type (PGMPAGETYPE).
676 */
677#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
678 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
679
680
681/** @name The Page state, PGMPAGE::uStateY.
682 * @{ */
683/** The zero page.
684 * This is a per-VM page that's never ever mapped writable. */
685#define PGM_PAGE_STATE_ZERO 0U
686/** A allocated page.
687 * This is a per-VM page allocated from the page pool (or wherever
688 * we get MMIO2 pages from if the type is MMIO2).
689 */
690#define PGM_PAGE_STATE_ALLOCATED 1U
691/** A allocated page that's being monitored for writes.
692 * The shadow page table mappings are read-only. When a write occurs, the
693 * fWrittenTo member is set, the page remapped as read-write and the state
694 * moved back to allocated. */
695#define PGM_PAGE_STATE_WRITE_MONITORED 2U
696/** The page is shared, aka. copy-on-write.
697 * This is a page that's shared with other VMs. */
698#define PGM_PAGE_STATE_SHARED 3U
699/** The page is ballooned, so no longer available for this VM. */
700#define PGM_PAGE_STATE_BALLOONED 4U
701/** @} */
702
703
704/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
705#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
706# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
707#else
708# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
709#endif
710
711/**
712 * Gets the page state.
713 * @returns page state (PGM_PAGE_STATE_*).
714 * @param a_pPage Pointer to the physical guest page tracking structure.
715 *
716 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
717 * builds.
718 */
719#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
720#if defined(__GNUC__) && defined(VBOX_STRICT)
721# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
722#else
723# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
724#endif
725
726/**
727 * Sets the page state.
728 * @param a_pVM The VM handle, only used for lock ownership assertions.
729 * @param a_pPage Pointer to the physical guest page tracking structure.
730 * @param a_uState The new page state.
731 */
732#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
733 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
734
735
736/**
737 * Gets the host physical address of the guest page.
738 * @returns host physical address (RTHCPHYS).
739 * @param a_pPage Pointer to the physical guest page tracking structure.
740 *
741 * @remarks In strict builds on gcc platforms, this macro will make some ugly
742 * assumption about a valid pVM variable/parameter being in the
743 * current context. It will use this pVM variable to assert that the
744 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
745 * pVM is not around.
746 */
747#if 0
748# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
749# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
750#else
751# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
752# if defined(__GNUC__) && defined(VBOX_STRICT)
753# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
754# else
755# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
756# endif
757#endif
758
759/**
760 * Sets the host physical address of the guest page.
761 *
762 * @param a_pVM The VM handle, only used for lock ownership assertions.
763 * @param a_pPage Pointer to the physical guest page tracking structure.
764 * @param a_HCPhys The new host physical address.
765 */
766#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
767 do { \
768 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
769 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
770 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
771 PGM_PAGE_ASSERT_LOCK(a_pVM); \
772 } while (0)
773
774/**
775 * Get the Page ID.
776 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
777 * @param a_pPage Pointer to the physical guest page tracking structure.
778 */
779#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
780
781/**
782 * Sets the Page ID.
783 * @param a_pVM The VM handle, only used for lock ownership assertions.
784 * @param a_pPage Pointer to the physical guest page tracking structure.
785 * @param a_idPage The new page ID.
786 */
787#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
788 do { \
789 (a_pPage)->s.idPage = (a_idPage); \
790 PGM_PAGE_ASSERT_LOCK(a_pVM); \
791 } while (0)
792
793/**
794 * Get the Chunk ID.
795 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
796 * @param a_pPage Pointer to the physical guest page tracking structure.
797 */
798#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
799
800/**
801 * Get the index of the page within the allocation chunk.
802 * @returns The page index.
803 * @param a_pPage Pointer to the physical guest page tracking structure.
804 */
805#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
806
807/**
808 * Gets the page type.
809 * @returns The page type.
810 * @param a_pPage Pointer to the physical guest page tracking structure.
811 *
812 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
813 * builds.
814 */
815#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
816#if defined(__GNUC__) && defined(VBOX_STRICT)
817# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
818#else
819# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
820#endif
821
822/**
823 * Sets the page type.
824 *
825 * @param a_pVM The VM handle, only used for lock ownership assertions.
826 * @param a_pPage Pointer to the physical guest page tracking structure.
827 * @param a_enmType The new page type (PGMPAGETYPE).
828 */
829#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
830 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
831
832/**
833 * Gets the page table index
834 * @returns The page table index.
835 * @param a_pPage Pointer to the physical guest page tracking structure.
836 */
837#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
838
839/**
840 * Sets the page table index.
841 * @param a_pVM The VM handle, only used for lock ownership assertions.
842 * @param a_pPage Pointer to the physical guest page tracking structure.
843 * @param a_iPte New page table index.
844 */
845#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
846 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
847
848/**
849 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
850 * @returns true/false.
851 * @param a_pPage Pointer to the physical guest page tracking structure.
852 */
853#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
854
855/**
856 * Checks if the page is marked for MMIO, including both aliases.
857 * @returns true/false.
858 * @param a_pPage Pointer to the physical guest page tracking structure.
859 */
860#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
861 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
862 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
863 )
864
865/**
866 * Checks if the page is marked for MMIO, including special aliases.
867 * @returns true/false.
868 * @param a_pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
871 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
872
873/**
874 * Checks if the page is a special aliased MMIO page.
875 * @returns true/false.
876 * @param a_pPage Pointer to the physical guest page tracking structure.
877 */
878#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
879
880/**
881 * Checks if the page is backed by the ZERO page.
882 * @returns true/false.
883 * @param a_pPage Pointer to the physical guest page tracking structure.
884 */
885#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
886
887/**
888 * Checks if the page is backed by a SHARED page.
889 * @returns true/false.
890 * @param a_pPage Pointer to the physical guest page tracking structure.
891 */
892#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
893
894/**
895 * Checks if the page is ballooned.
896 * @returns true/false.
897 * @param a_pPage Pointer to the physical guest page tracking structure.
898 */
899#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
900
901/**
902 * Checks if the page is allocated.
903 * @returns true/false.
904 * @param a_pPage Pointer to the physical guest page tracking structure.
905 */
906#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
907
908/**
909 * Marks the page as written to (for GMM change monitoring).
910 * @param a_pVM The VM handle, only used for lock ownership assertions.
911 * @param a_pPage Pointer to the physical guest page tracking structure.
912 */
913#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
914 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
915
916/**
917 * Clears the written-to indicator.
918 * @param a_pVM The VM handle, only used for lock ownership assertions.
919 * @param a_pPage Pointer to the physical guest page tracking structure.
920 */
921#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
922 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
923
924/**
925 * Checks if the page was marked as written-to.
926 * @returns true/false.
927 * @param a_pPage Pointer to the physical guest page tracking structure.
928 */
929#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
930
931
932/** @name PT usage values (PGMPAGE::u2PDEType).
933 *
934 * @{ */
935/** Either as a PT or PDE. */
936#define PGM_PAGE_PDE_TYPE_DONTCARE 0
937/** Must use a page table to map the range. */
938#define PGM_PAGE_PDE_TYPE_PT 1
939/** Can use a page directory entry to map the continuous range. */
940#define PGM_PAGE_PDE_TYPE_PDE 2
941/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
942#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
943/** @} */
944
945/**
946 * Set the PDE type of the page
947 * @param a_pVM The VM handle, only used for lock ownership assertions.
948 * @param a_pPage Pointer to the physical guest page tracking structure.
949 * @param a_uType PGM_PAGE_PDE_TYPE_*.
950 */
951#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
952 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
953
954/**
955 * Checks if the page was marked being part of a large page
956 * @returns true/false.
957 * @param a_pPage Pointer to the physical guest page tracking structure.
958 */
959#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
960
961/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
962 *
963 * @remarks The values are assigned in order of priority, so we can calculate
964 * the correct state for a page with different handlers installed.
965 * @{ */
966/** No handler installed. */
967#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
968/** Monitoring is temporarily disabled. */
969#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
970/** Write access is monitored. */
971#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
972/** All access is monitored. */
973#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
974/** @} */
975
976/**
977 * Gets the physical access handler state of a page.
978 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
979 * @param a_pPage Pointer to the physical guest page tracking structure.
980 */
981#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
982
983/**
984 * Sets the physical access handler state of a page.
985 * @param a_pPage Pointer to the physical guest page tracking structure.
986 * @param a_uState The new state value.
987 */
988#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
989 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
990
991/**
992 * Checks if the page has any physical access handlers, including temporarily disabled ones.
993 * @returns true/false
994 * @param a_pPage Pointer to the physical guest page tracking structure.
995 */
996#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
997 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
998
999/**
1000 * Checks if the page has any active physical access handlers.
1001 * @returns true/false
1002 * @param a_pPage Pointer to the physical guest page tracking structure.
1003 */
1004#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1005 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1006
1007/**
1008 * Checks if the page has any access handlers, including temporarily disabled ones.
1009 * @returns true/false
1010 * @param a_pPage Pointer to the physical guest page tracking structure.
1011 */
1012#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1013 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1014
1015/**
1016 * Checks if the page has any active access handlers.
1017 * @returns true/false
1018 * @param a_pPage Pointer to the physical guest page tracking structure.
1019 */
1020#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1021 (PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1022
1023/**
1024 * Checks if the page has any active access handlers catching all accesses.
1025 * @returns true/false
1026 * @param a_pPage Pointer to the physical guest page tracking structure.
1027 */
1028#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1029 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1030
1031
1032/** @def PGM_PAGE_GET_TRACKING
1033 * Gets the packed shadow page pool tracking data associated with a guest page.
1034 * @returns uint16_t containing the data.
1035 * @param a_pPage Pointer to the physical guest page tracking structure.
1036 */
1037#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1038#if defined(__GNUC__) && defined(VBOX_STRICT)
1039# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1040#else
1041# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1042#endif
1043
1044/** @def PGM_PAGE_SET_TRACKING
1045 * Sets the packed shadow page pool tracking data associated with a guest page.
1046 * @param a_pVM The VM handle, only used for lock ownership assertions.
1047 * @param a_pPage Pointer to the physical guest page tracking structure.
1048 * @param a_u16TrackingData The tracking data to store.
1049 */
1050#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1051 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1052
1053/** @def PGM_PAGE_GET_TD_CREFS
1054 * Gets the @a cRefs tracking data member.
1055 * @returns cRefs.
1056 * @param a_pPage Pointer to the physical guest page tracking structure.
1057 */
1058#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1059 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1060#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1061 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1062
1063/** @def PGM_PAGE_GET_TD_IDX
1064 * Gets the @a idx tracking data member.
1065 * @returns idx.
1066 * @param a_pPage Pointer to the physical guest page tracking structure.
1067 */
1068#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1069 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1070#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1071 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1072
1073
1074/** Max number of locks on a page. */
1075#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1076
1077/** Get the read lock count.
1078 * @returns count.
1079 * @param a_pPage Pointer to the physical guest page tracking structure.
1080 */
1081#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1082
1083/** Get the write lock count.
1084 * @returns count.
1085 * @param a_pPage Pointer to the physical guest page tracking structure.
1086 */
1087#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1088
1089/** Decrement the read lock counter.
1090 * @param a_pPage Pointer to the physical guest page tracking structure.
1091 */
1092#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1093
1094/** Decrement the write lock counter.
1095 * @param a_pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1098
1099/** Increment the read lock counter.
1100 * @param a_pPage Pointer to the physical guest page tracking structure.
1101 */
1102#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1103
1104/** Increment the write lock counter.
1105 * @param a_pPage Pointer to the physical guest page tracking structure.
1106 */
1107#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1108
1109
1110/** Gets the NEM state.
1111 * @returns NEM state value (two bits).
1112 * @param a_pPage Pointer to the physical guest page tracking structure.
1113 */
1114#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1115
1116/** Sets the NEM state.
1117 * @param a_pPage Pointer to the physical guest page tracking structure.
1118 * @param a_u2State The NEM state value (specific to NEM impl.).
1119 */
1120#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1121 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1122
1123
1124#if 0
1125/** Enables sanity checking of write monitoring using CRC-32. */
1126# define PGMLIVESAVERAMPAGE_WITH_CRC32
1127#endif
1128
1129/**
1130 * Per page live save tracking data.
1131 */
1132typedef struct PGMLIVESAVERAMPAGE
1133{
1134 /** Number of times it has been dirtied. */
1135 uint32_t cDirtied : 24;
1136 /** Whether it is currently dirty. */
1137 uint32_t fDirty : 1;
1138 /** Ignore the page.
1139 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1140 * deal with these after pausing the VM and DevPCI have said it bit about
1141 * remappings. */
1142 uint32_t fIgnore : 1;
1143 /** Was a ZERO page last time around. */
1144 uint32_t fZero : 1;
1145 /** Was a SHARED page last time around. */
1146 uint32_t fShared : 1;
1147 /** Whether the page is/was write monitored in a previous pass. */
1148 uint32_t fWriteMonitored : 1;
1149 /** Whether the page is/was write monitored earlier in this pass. */
1150 uint32_t fWriteMonitoredJustNow : 1;
1151 /** Bits reserved for future use. */
1152 uint32_t u2Reserved : 2;
1153#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1154 /** CRC-32 for the page. This is for internal consistency checks. */
1155 uint32_t u32Crc;
1156#endif
1157} PGMLIVESAVERAMPAGE;
1158#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1159AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1160#else
1161AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1162#endif
1163/** Pointer to the per page live save tracking data. */
1164typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1165
1166/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1167#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1168
1169
1170/**
1171 * RAM range for GC Phys to HC Phys conversion.
1172 *
1173 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1174 * conversions too, but we'll let MM handle that for now.
1175 *
1176 * This structure is used by linked lists in both GC and HC.
1177 */
1178typedef struct PGMRAMRANGE
1179{
1180 /** Start of the range. Page aligned. */
1181 RTGCPHYS GCPhys;
1182 /** Size of the range. (Page aligned of course). */
1183 RTGCPHYS cb;
1184 /** Pointer to the next RAM range - for R3. */
1185 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1186 /** Pointer to the next RAM range - for R0. */
1187 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1188 /** PGM_RAM_RANGE_FLAGS_* flags. */
1189 uint32_t fFlags;
1190 /** NEM specific info, UINT32_MAX if not used. */
1191 uint32_t uNemRange;
1192 /** Last address in the range (inclusive). Page aligned (-1). */
1193 RTGCPHYS GCPhysLast;
1194 /** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1195 R3PTRTYPE(void *) pvR3;
1196 /** Live save per page tracking data. */
1197 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1198 /** The range description. */
1199 R3PTRTYPE(const char *) pszDesc;
1200 /** Pointer to self - R0 pointer. */
1201 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1202
1203 /** Pointer to the left search three node - ring-3 context. */
1204 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1205 /** Pointer to the right search three node - ring-3 context. */
1206 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1207 /** Pointer to the left search three node - ring-0 context. */
1208 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1209 /** Pointer to the right search three node - ring-0 context. */
1210 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1211
1212 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1213#if HC_ARCH_BITS == 32
1214 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1215#endif
1216 /** Array of physical guest page tracking structures. */
1217 PGMPAGE aPages[1];
1218} PGMRAMRANGE;
1219/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1220typedef PGMRAMRANGE *PPGMRAMRANGE;
1221
1222/** @name PGMRAMRANGE::fFlags
1223 * @{ */
1224/** The RAM range is floating around as an independent guest mapping. */
1225#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1226/** Ad hoc RAM range for an ROM mapping. */
1227#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1228/** Ad hoc RAM range for an MMIO mapping. */
1229#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1230/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1231#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1232/** @} */
1233
1234/** Tests if a RAM range is an ad hoc one or not.
1235 * @returns true/false.
1236 * @param pRam The RAM range.
1237 */
1238#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1239 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1240
1241/** The number of entries in the RAM range TLBs (there is one for each
1242 * context). Must be a power of two. */
1243#define PGM_RAMRANGE_TLB_ENTRIES 8
1244
1245/**
1246 * Calculates the RAM range TLB index for the physical address.
1247 *
1248 * @returns RAM range TLB index.
1249 * @param a_GCPhys The guest physical address.
1250 */
1251#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1252
1253/**
1254 * Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1255 * mapping address.
1256 */
1257#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1258 ( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1259
1260
1261/**
1262 * Per page tracking structure for ROM image.
1263 *
1264 * A ROM image may have a shadow page, in which case we may have two pages
1265 * backing it. This structure contains the PGMPAGE for both while
1266 * PGMRAMRANGE have a copy of the active one. It is important that these
1267 * aren't out of sync in any regard other than page pool tracking data.
1268 */
1269typedef struct PGMROMPAGE
1270{
1271 /** The page structure for the virgin ROM page. */
1272 PGMPAGE Virgin;
1273 /** The page structure for the shadow RAM page. */
1274 PGMPAGE Shadow;
1275 /** The current protection setting. */
1276 PGMROMPROT enmProt;
1277 /** Live save status information. Makes use of unused alignment space. */
1278 struct
1279 {
1280 /** The previous protection value. */
1281 uint8_t u8Prot;
1282 /** Written to flag set by the handler. */
1283 bool fWrittenTo;
1284 /** Whether the shadow page is dirty or not. */
1285 bool fDirty;
1286 /** Whether it was dirtied in the recently. */
1287 bool fDirtiedRecently;
1288 } LiveSave;
1289} PGMROMPAGE;
1290AssertCompileSizeAlignment(PGMROMPAGE, 8);
1291/** Pointer to a ROM page tracking structure. */
1292typedef PGMROMPAGE *PPGMROMPAGE;
1293
1294
1295/**
1296 * A registered ROM image.
1297 *
1298 * This is needed to keep track of ROM image since they generally intrude
1299 * into a PGMRAMRANGE. It also keeps track of additional info like the
1300 * two page sets (read-only virgin and read-write shadow), the current
1301 * state of each page.
1302 *
1303 * Because access handlers cannot easily be executed in a different
1304 * context, the ROM ranges needs to be accessible and in all contexts.
1305 */
1306typedef struct PGMROMRANGE
1307{
1308 /** Pointer to the next range - R3. */
1309 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1310 /** Pointer to the next range - R0. */
1311 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1312 /** Address of the range. */
1313 RTGCPHYS GCPhys;
1314 /** Address of the last byte in the range. */
1315 RTGCPHYS GCPhysLast;
1316 /** Size of the range. */
1317 RTGCPHYS cb;
1318 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1319 uint8_t fFlags;
1320 /** The saved state range ID. */
1321 uint8_t idSavedState;
1322 /** Alignment padding. */
1323 uint8_t au8Alignment[2];
1324 /** The size bits pvOriginal points to. */
1325 uint32_t cbOriginal;
1326 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1327 * This is used for strictness checks. */
1328 R3PTRTYPE(const void *) pvOriginal;
1329 /** The ROM description. */
1330 R3PTRTYPE(const char *) pszDesc;
1331#ifdef VBOX_WITH_PGM_NEM_MODE
1332 /** In simplified memory mode this provides alternate backing for shadowed ROMs.
1333 * - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1334 * - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1335 * - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1336 * - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1337 R3PTRTYPE(uint8_t *) pbR3Alternate;
1338 RTR3PTR pvAlignment2;
1339#endif
1340 /** The per page tracking structures. */
1341 PGMROMPAGE aPages[1];
1342} PGMROMRANGE;
1343/** Pointer to a ROM range. */
1344typedef PGMROMRANGE *PPGMROMRANGE;
1345
1346
1347/**
1348 * Live save per page data for an MMIO2 page.
1349 *
1350 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1351 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1352 * CRC-32 for detecting changes as well as special handling of zero pages. This
1353 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1354 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1355 * because of speed (2.5x and 6x slower).)
1356 *
1357 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1358 * save but normally is disabled. Since we can write monitor guest
1359 * accesses on our own, we only need this for host accesses. Shouldn't be
1360 * too difficult for DevVGA, VMMDev might be doable, the planned
1361 * networking fun will be fun since it involves ring-0.
1362 */
1363typedef struct PGMLIVESAVEMMIO2PAGE
1364{
1365 /** Set if the page is considered dirty. */
1366 bool fDirty;
1367 /** The number of scans this page has remained unchanged for.
1368 * Only updated for dirty pages. */
1369 uint8_t cUnchangedScans;
1370 /** Whether this page was zero at the last scan. */
1371 bool fZero;
1372 /** Alignment padding. */
1373 bool fReserved;
1374 /** CRC-32 for the first half of the page.
1375 * This is used together with u32CrcH2 to quickly detect changes in the page
1376 * during the non-final passes. */
1377 uint32_t u32CrcH1;
1378 /** CRC-32 for the second half of the page. */
1379 uint32_t u32CrcH2;
1380 /** SHA-1 for the saved page.
1381 * This is used in the final pass to skip pages without changes. */
1382 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1383} PGMLIVESAVEMMIO2PAGE;
1384/** Pointer to a live save status data for an MMIO2 page. */
1385typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1386
1387/**
1388 * A registered MMIO2 (= Device RAM) range.
1389 *
1390 * There are a few reason why we need to keep track of these registrations. One
1391 * of them is the deregistration & cleanup stuff, while another is that the
1392 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1393 * range list.
1394 *
1395 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1396 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1397 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1398 * overlap we will free all the existing RAM pages and put in the ram range
1399 * pages instead.
1400 */
1401typedef struct PGMREGMMIO2RANGE
1402{
1403 /** The owner of the range. (a device) */
1404 PPDMDEVINSR3 pDevInsR3;
1405 /** Pointer to the ring-3 mapping of the allocation. */
1406 RTR3PTR pvR3;
1407#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1408 /** Pointer to the ring-0 mapping of the allocation. */
1409 RTR0PTR pvR0;
1410#endif
1411 /** Pointer to the next range - R3. */
1412 R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1413 /** Flags (PGMREGMMIO2RANGE_F_XXX). */
1414 uint16_t fFlags;
1415 /** The sub device number (internal PCI config (CFGM) number). */
1416 uint8_t iSubDev;
1417 /** The PCI region number. */
1418 uint8_t iRegion;
1419 /** The saved state range ID. */
1420 uint8_t idSavedState;
1421 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1422 uint8_t idMmio2;
1423 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1424#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1425 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1426#else
1427 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1428#endif
1429 /** The real size.
1430 * This may be larger than indicated by RamRange.cb if the range has been
1431 * reduced during saved state loading. */
1432 RTGCPHYS cbReal;
1433 /** Pointer to the physical handler for MMIO.
1434 * If NEM is responsible for tracking dirty pages in simple memory mode, this
1435 * will be NULL. */
1436 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1437 /** Live save per page tracking data for MMIO2. */
1438 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1439 /** The associated RAM range. */
1440 PGMRAMRANGE RamRange;
1441} PGMREGMMIO2RANGE;
1442AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1443/** Pointer to a MMIO2 or pre-registered MMIO range. */
1444typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1445
1446/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1447 * @{ */
1448/** Set if this is the first chunk in the MMIO2 range. */
1449#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1450/** Set if this is the last chunk in the MMIO2 range. */
1451#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1452/** Set if the whole range is mapped. */
1453#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1454/** Set if it's overlapping, clear if not. */
1455#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1456/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1457#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1458/** Set if the access handler is registered. */
1459#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1460/** Set if dirty page tracking is currently enabled. */
1461#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1462/** Set if there are dirty pages in the range. */
1463#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1464/** @} */
1465
1466
1467/** @name Internal MMIO2 constants.
1468 * @{ */
1469/** The maximum number of MMIO2 ranges. */
1470#define PGM_MMIO2_MAX_RANGES 32
1471/** The maximum number of pages in a MMIO2 range. */
1472#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1473/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1474#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1475/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1476#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1477/** Gets the MMIO2 page index from an MMIO2 page ID. */
1478#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1479/** @} */
1480
1481
1482
1483/**
1484 * PGMPhysRead/Write cache entry
1485 */
1486typedef struct PGMPHYSCACHEENTRY
1487{
1488 /** R3 pointer to physical page. */
1489 R3PTRTYPE(uint8_t *) pbR3;
1490 /** GC Physical address for cache entry */
1491 RTGCPHYS GCPhys;
1492#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1493 RTGCPHYS u32Padding0; /**< alignment padding. */
1494#endif
1495} PGMPHYSCACHEENTRY;
1496
1497/**
1498 * PGMPhysRead/Write cache to reduce REM memory access overhead
1499 */
1500typedef struct PGMPHYSCACHE
1501{
1502 /** Bitmap of valid cache entries */
1503 uint64_t aEntries;
1504 /** Cache entries */
1505 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1506} PGMPHYSCACHE;
1507
1508
1509/** @name Ring-3 page mapping TLBs
1510 * @{ */
1511
1512/** Pointer to an allocation chunk ring-3 mapping. */
1513typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1514/** Pointer to an allocation chunk ring-3 mapping pointer. */
1515typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1516
1517/**
1518 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1519 *
1520 * The primary tree (Core) uses the chunk id as key.
1521 */
1522typedef struct PGMCHUNKR3MAP
1523{
1524 /** The key is the chunk id. */
1525 AVLU32NODECORE Core;
1526 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1527 * selection. */
1528 uint32_t iLastUsed;
1529 /** The current reference count. */
1530 uint32_t volatile cRefs;
1531 /** The current permanent reference count. */
1532 uint32_t volatile cPermRefs;
1533 /** The mapping address. */
1534 void *pv;
1535} PGMCHUNKR3MAP;
1536
1537/**
1538 * Allocation chunk ring-3 mapping TLB entry.
1539 */
1540typedef struct PGMCHUNKR3MAPTLBE
1541{
1542 /** The chunk id. */
1543 uint32_t volatile idChunk;
1544#if HC_ARCH_BITS == 64
1545 uint32_t u32Padding; /**< alignment padding. */
1546#endif
1547 /** The chunk map. */
1548 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1549} PGMCHUNKR3MAPTLBE;
1550/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1551typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1552
1553/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1554 * @remark Must be a power of two value. */
1555#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1556
1557/**
1558 * Allocation chunk ring-3 mapping TLB.
1559 *
1560 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1561 * At first glance this might look kinda odd since AVL trees are
1562 * supposed to give the most optimal lookup times of all trees
1563 * due to their balancing. However, take a tree with 1023 nodes
1564 * in it, that's 10 levels, meaning that most searches has to go
1565 * down 9 levels before they find what they want. This isn't fast
1566 * compared to a TLB hit. There is the factor of cache misses,
1567 * and of course the problem with trees and branch prediction.
1568 * This is why we use TLBs in front of most of the trees.
1569 *
1570 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1571 * difficult when we switch to the new inlined AVL trees (from kStuff).
1572 */
1573typedef struct PGMCHUNKR3MAPTLB
1574{
1575 /** The TLB entries. */
1576 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1577} PGMCHUNKR3MAPTLB;
1578
1579/**
1580 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1581 * @returns Chunk TLB index.
1582 * @param idChunk The Chunk ID.
1583 */
1584#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1585
1586
1587/**
1588 * Ring-3 guest page mapping TLB entry.
1589 * @remarks used in ring-0 as well at the moment.
1590 */
1591typedef struct PGMPAGER3MAPTLBE
1592{
1593 /** Address of the page. */
1594 RTGCPHYS volatile GCPhys;
1595 /** The guest page. */
1596 R3PTRTYPE(PPGMPAGE) volatile pPage;
1597 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1598 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1599 /** The address */
1600 R3PTRTYPE(void *) volatile pv;
1601#if HC_ARCH_BITS == 32
1602 uint32_t u32Padding; /**< alignment padding. */
1603#endif
1604} PGMPAGER3MAPTLBE;
1605/** Pointer to an entry in the HC physical TLB. */
1606typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1607
1608
1609/** The number of entries in the ring-3 guest page mapping TLB.
1610 * @remarks The value must be a power of two. */
1611#define PGM_PAGER3MAPTLB_ENTRIES 256
1612
1613/**
1614 * Ring-3 guest page mapping TLB.
1615 * @remarks used in ring-0 as well at the moment.
1616 */
1617typedef struct PGMPAGER3MAPTLB
1618{
1619 /** The TLB entries. */
1620 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1621} PGMPAGER3MAPTLB;
1622/** Pointer to the ring-3 guest page mapping TLB. */
1623typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1624
1625/**
1626 * Calculates the index of the TLB entry for the specified guest page.
1627 * @returns Physical TLB index.
1628 * @param GCPhys The guest physical address.
1629 */
1630#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1631
1632/** @} */
1633
1634
1635/** @name Ring-0 page mapping TLB
1636 * @{ */
1637/**
1638 * Ring-0 guest page mapping TLB entry.
1639 */
1640typedef struct PGMPAGER0MAPTLBE
1641{
1642 /** Address of the page. */
1643 RTGCPHYS volatile GCPhys;
1644 /** The guest page. */
1645 R0PTRTYPE(PPGMPAGE) volatile pPage;
1646 /** The address */
1647 R0PTRTYPE(void *) volatile pv;
1648} PGMPAGER0MAPTLBE;
1649/** Pointer to an entry in the HC physical TLB. */
1650typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1651
1652
1653/** The number of entries in the ring-3 guest page mapping TLB.
1654 * @remarks The value must be a power of two. */
1655#define PGM_PAGER0MAPTLB_ENTRIES 256
1656
1657/**
1658 * Ring-3 guest page mapping TLB.
1659 * @remarks used in ring-0 as well at the moment.
1660 */
1661typedef struct PGMPAGER0MAPTLB
1662{
1663 /** The TLB entries. */
1664 PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1665} PGMPAGER0MAPTLB;
1666/** Pointer to the ring-3 guest page mapping TLB. */
1667typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1668
1669/**
1670 * Calculates the index of the TLB entry for the specified guest page.
1671 * @returns Physical TLB index.
1672 * @param GCPhys The guest physical address.
1673 */
1674#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1675/** @} */
1676
1677
1678/** @name Context neutral page mapper TLB.
1679 *
1680 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1681 * code is writting in a kind of context neutral way. Time will show whether
1682 * this actually makes sense or not...
1683 *
1684 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1685 * context ends up using a global mapping cache on some platforms
1686 * (darwin).
1687 *
1688 * @{ */
1689/** @typedef PPGMPAGEMAPTLB
1690 * The page mapper TLB pointer type for the current context. */
1691/** @typedef PPGMPAGEMAPTLB
1692 * The page mapper TLB entry pointer type for the current context. */
1693/** @typedef PPGMPAGEMAPTLB
1694 * The page mapper TLB entry pointer pointer type for the current context. */
1695/** @def PGM_PAGEMAPTLB_ENTRIES
1696 * The number of TLB entries in the page mapper TLB for the current context. */
1697/** @def PGM_PAGEMAPTLB_IDX
1698 * Calculate the TLB index for a guest physical address.
1699 * @returns The TLB index.
1700 * @param GCPhys The guest physical address. */
1701/** @typedef PPGMPAGEMAP
1702 * Pointer to a page mapper unit for current context. */
1703/** @typedef PPPGMPAGEMAP
1704 * Pointer to a page mapper unit pointer for current context. */
1705#if defined(IN_RING0)
1706typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1707typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1708typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1709# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1710# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1711typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1712typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1713#else
1714typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1715typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1716typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1717# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1718# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1719typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1720typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1721#endif
1722/** @} */
1723
1724
1725/** @name PGM Pool Indexes.
1726 * Aka. the unique shadow page identifier.
1727 * @{ */
1728/** NIL page pool IDX. */
1729#define NIL_PGMPOOL_IDX 0
1730/** The first normal index. There used to be 5 fictive pages up front, now
1731 * there is only the NIL page. */
1732#define PGMPOOL_IDX_FIRST 1
1733/** The last valid index. (inclusive, 14 bits) */
1734#define PGMPOOL_IDX_LAST 0x3fff
1735/** @} */
1736
1737/** The NIL index for the parent chain. */
1738#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1739#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1740
1741/**
1742 * Node in the chain linking a shadowed page to it's parent (user).
1743 */
1744#pragma pack(1)
1745typedef struct PGMPOOLUSER
1746{
1747 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1748 uint16_t iNext;
1749 /** The user page index. */
1750 uint16_t iUser;
1751 /** Index into the user table. */
1752 uint32_t iUserTable;
1753} PGMPOOLUSER, *PPGMPOOLUSER;
1754typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1755#pragma pack()
1756
1757
1758/** The NIL index for the phys ext chain. */
1759#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1760/** The NIL pte index for a phys ext chain slot. */
1761#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1762
1763/**
1764 * Node in the chain of physical cross reference extents.
1765 * @todo Calling this an 'extent' is not quite right, find a better name.
1766 * @todo find out the optimal size of the aidx array
1767 */
1768#pragma pack(1)
1769typedef struct PGMPOOLPHYSEXT
1770{
1771 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1772 uint16_t iNext;
1773 /** Alignment. */
1774 uint16_t u16Align;
1775 /** The user page index. */
1776 uint16_t aidx[3];
1777 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1778 uint16_t apte[3];
1779} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1780typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1781#pragma pack()
1782
1783
1784/**
1785 * The kind of page that's being shadowed.
1786 */
1787typedef enum PGMPOOLKIND
1788{
1789 /** The virtual invalid 0 entry. */
1790 PGMPOOLKIND_INVALID = 0,
1791 /** The entry is free (=unused). */
1792 PGMPOOLKIND_FREE,
1793
1794 /** Shw: 32-bit page table; Gst: no paging. */
1795 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1796 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1797 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1798 /** Shw: 32-bit page table; Gst: 4MB page. */
1799 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1800 /** Shw: PAE page table; Gst: no paging. */
1801 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1802 /** Shw: PAE page table; Gst: 32-bit page table. */
1803 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1804 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1805 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1806 /** Shw: PAE page table; Gst: PAE page table. */
1807 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1808 /** Shw: PAE page table; Gst: 2MB page. */
1809 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1810
1811 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1812 PGMPOOLKIND_32BIT_PD,
1813 /** Shw: 32-bit page directory. Gst: no paging. */
1814 PGMPOOLKIND_32BIT_PD_PHYS,
1815 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1816 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1817 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1818 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1819 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1820 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1821 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1822 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1823 /** Shw: PAE page directory; Gst: PAE page directory. */
1824 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1825 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1826 PGMPOOLKIND_PAE_PD_PHYS,
1827
1828 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1829 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1830 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1831 PGMPOOLKIND_PAE_PDPT,
1832 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1833 PGMPOOLKIND_PAE_PDPT_PHYS,
1834
1835 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1836 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1837 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
1838 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1839 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1840 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1841 /** Shw: 64-bit page directory table; Gst: no paging. */
1842 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1843
1844 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1845 PGMPOOLKIND_64BIT_PML4,
1846
1847 /** Shw: EPT page directory pointer table; Gst: no paging. */
1848 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1849 /** Shw: EPT page directory table; Gst: no paging. */
1850 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1851 /** Shw: EPT page table; Gst: no paging. */
1852 PGMPOOLKIND_EPT_PT_FOR_PHYS,
1853
1854 /** Shw: Root Nested paging table. */
1855 PGMPOOLKIND_ROOT_NESTED,
1856
1857 /** The last valid entry. */
1858 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1859} PGMPOOLKIND;
1860
1861/**
1862 * The access attributes of the page; only applies to big pages.
1863 */
1864typedef enum
1865{
1866 PGMPOOLACCESS_DONTCARE = 0,
1867 PGMPOOLACCESS_USER_RW,
1868 PGMPOOLACCESS_USER_R,
1869 PGMPOOLACCESS_USER_RW_NX,
1870 PGMPOOLACCESS_USER_R_NX,
1871 PGMPOOLACCESS_SUPERVISOR_RW,
1872 PGMPOOLACCESS_SUPERVISOR_R,
1873 PGMPOOLACCESS_SUPERVISOR_RW_NX,
1874 PGMPOOLACCESS_SUPERVISOR_R_NX
1875} PGMPOOLACCESS;
1876
1877/**
1878 * The tracking data for a page in the pool.
1879 */
1880typedef struct PGMPOOLPAGE
1881{
1882 /** AVL node code with the (HC) physical address of this page. */
1883 AVLOHCPHYSNODECORE Core;
1884 /** Pointer to the R3 mapping of the page. */
1885 R3PTRTYPE(void *) pvPageR3;
1886 /** Pointer to the R0 mapping of the page. */
1887 R0PTRTYPE(void *) pvPageR0;
1888 /** The guest physical address. */
1889 RTGCPHYS GCPhys;
1890 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1891 uint8_t enmKind;
1892 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1893 uint8_t enmAccess;
1894 /** This supplements enmKind and enmAccess */
1895 bool fA20Enabled : 1;
1896
1897 /** Used to indicate that the page is zeroed. */
1898 bool fZeroed : 1;
1899 /** Used to indicate that a PT has non-global entries. */
1900 bool fSeenNonGlobal : 1;
1901 /** Used to indicate that we're monitoring writes to the guest page. */
1902 bool fMonitored : 1;
1903 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1904 * (All pages are in the age list.) */
1905 bool fCached : 1;
1906 /** This is used by the R3 access handlers when invoked by an async thread.
1907 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1908 bool volatile fReusedFlushPending : 1;
1909 /** Used to mark the page as dirty (write monitoring is temporarily
1910 * off). */
1911 bool fDirty : 1;
1912 bool fPadding1 : 1;
1913 bool fPadding2;
1914
1915 /** The index of this page. */
1916 uint16_t idx;
1917 /** The next entry in the list this page currently resides in.
1918 * It's either in the free list or in the GCPhys hash. */
1919 uint16_t iNext;
1920 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1921 uint16_t iUserHead;
1922 /** The number of present entries. */
1923 uint16_t cPresent;
1924 /** The first entry in the table which is present. */
1925 uint16_t iFirstPresent;
1926 /** The number of modifications to the monitored page. */
1927 uint16_t cModifications;
1928 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
1929 uint16_t iModifiedNext;
1930 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
1931 uint16_t iModifiedPrev;
1932 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1933 uint16_t iMonitoredNext;
1934 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1935 uint16_t iMonitoredPrev;
1936 /** The next page in the age list. */
1937 uint16_t iAgeNext;
1938 /** The previous page in the age list. */
1939 uint16_t iAgePrev;
1940 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
1941 uint8_t idxDirtyEntry;
1942
1943 /** @name Access handler statistics to determine whether the guest is
1944 * (re)initializing a page table.
1945 * @{ */
1946 RTGCPTR GCPtrLastAccessHandlerRip;
1947 RTGCPTR GCPtrLastAccessHandlerFault;
1948 uint64_t cLastAccessHandler;
1949 /** @} */
1950 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
1951 uint32_t volatile cLocked;
1952#if GC_ARCH_BITS == 64
1953 uint32_t u32Alignment3;
1954#endif
1955# ifdef VBOX_STRICT
1956 RTGCPTR GCPtrDirtyFault;
1957# endif
1958} PGMPOOLPAGE;
1959/** Pointer to a pool page. */
1960typedef PGMPOOLPAGE *PPGMPOOLPAGE;
1961/** Pointer to a const pool page. */
1962typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1963/** Pointer to a pool page pointer. */
1964typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
1965
1966
1967/** The hash table size. */
1968# define PGMPOOL_HASH_SIZE 0x40
1969/** The hash function. */
1970# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1971
1972
1973/**
1974 * The shadow page pool instance data.
1975 *
1976 * It's all one big allocation made at init time, except for the
1977 * pages that is. The user nodes follows immediately after the
1978 * page structures.
1979 */
1980typedef struct PGMPOOL
1981{
1982 /** The VM handle - R3 Ptr. */
1983 PVMR3 pVMR3;
1984 /** The VM handle - R0 Ptr. */
1985 R0PTRTYPE(PVMCC) pVMR0;
1986 /** The max pool size. This includes the special IDs. */
1987 uint16_t cMaxPages;
1988 /** The current pool size. */
1989 uint16_t cCurPages;
1990 /** The head of the free page list. */
1991 uint16_t iFreeHead;
1992 /* Padding. */
1993 uint16_t u16Padding;
1994 /** Head of the chain of free user nodes. */
1995 uint16_t iUserFreeHead;
1996 /** The number of user nodes we've allocated. */
1997 uint16_t cMaxUsers;
1998 /** The number of present page table entries in the entire pool. */
1999 uint32_t cPresent;
2000 /** Pointer to the array of user nodes - R3 pointer. */
2001 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2002 /** Pointer to the array of user nodes - R0 pointer. */
2003 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2004 /** Head of the chain of free phys ext nodes. */
2005 uint16_t iPhysExtFreeHead;
2006 /** The number of user nodes we've allocated. */
2007 uint16_t cMaxPhysExts;
2008 uint32_t u32Padding0b;
2009 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2010 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2011 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2012 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2013 /** Hash table for GCPhys addresses. */
2014 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2015 /** The head of the age list. */
2016 uint16_t iAgeHead;
2017 /** The tail of the age list. */
2018 uint16_t iAgeTail;
2019 /** Set if the cache is enabled. */
2020 bool fCacheEnabled;
2021 /** Alignment padding. */
2022 bool afPadding1[3];
2023 /** Head of the list of modified pages. */
2024 uint16_t iModifiedHead;
2025 /** The current number of modified pages. */
2026 uint16_t cModifiedPages;
2027 /** Physical access handler type registration handle. */
2028 PGMPHYSHANDLERTYPE hAccessHandlerType;
2029 /** Next available slot (in aDirtyPages). */
2030 uint32_t idxFreeDirtyPage;
2031 /** Number of active dirty pages. */
2032 uint32_t cDirtyPages;
2033 /** Array of current dirty pgm pool page indices. */
2034 uint16_t aidxDirtyPages[16];
2035 /** Array running in parallel to aidxDirtyPages with the page data. */
2036 struct
2037 {
2038 uint64_t aPage[512];
2039 } aDirtyPages[16];
2040
2041 /** The number of pages currently in use. */
2042 uint16_t cUsedPages;
2043#ifdef VBOX_WITH_STATISTICS
2044 /** The high water mark for cUsedPages. */
2045 uint16_t cUsedPagesHigh;
2046 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2047 /** Profiling pgmPoolAlloc(). */
2048 STAMPROFILEADV StatAlloc;
2049 /** Profiling pgmR3PoolClearDoIt(). */
2050 STAMPROFILE StatClearAll;
2051 /** Profiling pgmR3PoolReset(). */
2052 STAMPROFILE StatR3Reset;
2053 /** Profiling pgmPoolFlushPage(). */
2054 STAMPROFILE StatFlushPage;
2055 /** Profiling pgmPoolFree(). */
2056 STAMPROFILE StatFree;
2057 /** Counting explicit flushes by PGMPoolFlushPage(). */
2058 STAMCOUNTER StatForceFlushPage;
2059 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2060 STAMCOUNTER StatForceFlushDirtyPage;
2061 /** Counting flushes for reused pages. */
2062 STAMCOUNTER StatForceFlushReused;
2063 /** Profiling time spent zeroing pages. */
2064 STAMPROFILE StatZeroPage;
2065 /** Profiling of pgmPoolTrackDeref. */
2066 STAMPROFILE StatTrackDeref;
2067 /** Profiling pgmTrackFlushGCPhysPT. */
2068 STAMPROFILE StatTrackFlushGCPhysPT;
2069 /** Profiling pgmTrackFlushGCPhysPTs. */
2070 STAMPROFILE StatTrackFlushGCPhysPTs;
2071 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2072 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2073 /** Number of times we've been out of user records. */
2074 STAMCOUNTER StatTrackFreeUpOneUser;
2075 /** Nr of flushed entries. */
2076 STAMCOUNTER StatTrackFlushEntry;
2077 /** Nr of updated entries. */
2078 STAMCOUNTER StatTrackFlushEntryKeep;
2079 /** Profiling deref activity related tracking GC physical pages. */
2080 STAMPROFILE StatTrackDerefGCPhys;
2081 /** Number of linear searches for a HCPhys in the ram ranges. */
2082 STAMCOUNTER StatTrackLinearRamSearches;
2083 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2084 STAMCOUNTER StamTrackPhysExtAllocFailures;
2085
2086 /** Profiling the RC/R0 \#PF access handler. */
2087 STAMPROFILE StatMonitorPfRZ;
2088 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2089 STAMPROFILE StatMonitorPfRZHandled;
2090 /** Times we've failed interpreting the instruction. */
2091 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2092 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2093 STAMPROFILE StatMonitorPfRZFlushPage;
2094 /** Times we've detected a page table reinit. */
2095 STAMCOUNTER StatMonitorPfRZFlushReinit;
2096 /** Counting flushes for pages that are modified too often. */
2097 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2098 /** Times we've detected fork(). */
2099 STAMCOUNTER StatMonitorPfRZFork;
2100 /** Times we've failed interpreting a patch code instruction. */
2101 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2102 /** Times we've failed interpreting a patch code instruction during flushing. */
2103 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2104 /** The number of times we've seen rep prefixes we can't handle. */
2105 STAMCOUNTER StatMonitorPfRZRepPrefix;
2106 /** Profiling the REP STOSD cases we've handled. */
2107 STAMPROFILE StatMonitorPfRZRepStosd;
2108
2109 /** Profiling the R0/RC regular access handler. */
2110 STAMPROFILE StatMonitorRZ;
2111 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2112 STAMPROFILE StatMonitorRZFlushPage;
2113 /** Per access size counts indexed by size minus 1, last for larger. */
2114 STAMCOUNTER aStatMonitorRZSizes[16+3];
2115 /** Missaligned access counts indexed by offset - 1. */
2116 STAMCOUNTER aStatMonitorRZMisaligned[7];
2117
2118 /** Nr of handled PT faults. */
2119 STAMCOUNTER StatMonitorRZFaultPT;
2120 /** Nr of handled PD faults. */
2121 STAMCOUNTER StatMonitorRZFaultPD;
2122 /** Nr of handled PDPT faults. */
2123 STAMCOUNTER StatMonitorRZFaultPDPT;
2124 /** Nr of handled PML4 faults. */
2125 STAMCOUNTER StatMonitorRZFaultPML4;
2126
2127 /** Profiling the R3 access handler. */
2128 STAMPROFILE StatMonitorR3;
2129 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2130 STAMPROFILE StatMonitorR3FlushPage;
2131 /** Per access size counts indexed by size minus 1, last for larger. */
2132 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2133 /** Missaligned access counts indexed by offset - 1. */
2134 STAMCOUNTER aStatMonitorR3Misaligned[7];
2135 /** Nr of handled PT faults. */
2136 STAMCOUNTER StatMonitorR3FaultPT;
2137 /** Nr of handled PD faults. */
2138 STAMCOUNTER StatMonitorR3FaultPD;
2139 /** Nr of handled PDPT faults. */
2140 STAMCOUNTER StatMonitorR3FaultPDPT;
2141 /** Nr of handled PML4 faults. */
2142 STAMCOUNTER StatMonitorR3FaultPML4;
2143
2144 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2145 STAMCOUNTER StatResetDirtyPages;
2146 /** Times we've called pgmPoolAddDirtyPage. */
2147 STAMCOUNTER StatDirtyPage;
2148 /** Times we've had to flush duplicates for dirty page management. */
2149 STAMCOUNTER StatDirtyPageDupFlush;
2150 /** Times we've had to flush because of overflow. */
2151 STAMCOUNTER StatDirtyPageOverFlowFlush;
2152
2153 /** The high water mark for cModifiedPages. */
2154 uint16_t cModifiedPagesHigh;
2155 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2156
2157 /** The number of cache hits. */
2158 STAMCOUNTER StatCacheHits;
2159 /** The number of cache misses. */
2160 STAMCOUNTER StatCacheMisses;
2161 /** The number of times we've got a conflict of 'kind' in the cache. */
2162 STAMCOUNTER StatCacheKindMismatches;
2163 /** Number of times we've been out of pages. */
2164 STAMCOUNTER StatCacheFreeUpOne;
2165 /** The number of cacheable allocations. */
2166 STAMCOUNTER StatCacheCacheable;
2167 /** The number of uncacheable allocations. */
2168 STAMCOUNTER StatCacheUncacheable;
2169#else
2170 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2171#endif
2172 /** Profiling PGMR0PoolGrow(). */
2173 STAMPROFILE StatGrow;
2174 /** The AVL tree for looking up a page by its HC physical address. */
2175 AVLOHCPHYSTREE HCPhysTree;
2176 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2177 /** Array of pages. (cMaxPages in length)
2178 * The Id is the index into thist array.
2179 */
2180 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2181} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2182AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2183AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2184AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2185#ifdef VBOX_WITH_STATISTICS
2186AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2187#endif
2188AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2189
2190
2191/** @def PGMPOOL_PAGE_2_PTR
2192 * Maps a pool page pool into the current context.
2193 *
2194 * @returns VBox status code.
2195 * @param a_pVM Pointer to the VM.
2196 * @param a_pPage The pool page.
2197 *
2198 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2199 * small page window employeed by that function. Be careful.
2200 * @remark There is no need to assert on the result.
2201 */
2202#if defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2203# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2204DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2205{
2206 RT_NOREF(pszCaller);
2207 AssertPtr(a_pPage);
2208 AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2209 ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2210 a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2211 return a_pPage->CTX_SUFF(pvPage);
2212}
2213#else
2214# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2215#endif
2216
2217
2218/** @def PGMPOOL_PAGE_2_PTR_V2
2219 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2220 *
2221 * @returns VBox status code.
2222 * @param a_pVM Pointer to the VM.
2223 * @param a_pVCpu The current CPU.
2224 * @param a_pPage The pool page.
2225 *
2226 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2227 * small page window employeed by that function. Be careful.
2228 * @remark There is no need to assert on the result.
2229 */
2230#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2231
2232
2233/** @name Per guest page tracking data.
2234 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2235 * is to use more bits for it and split it up later on. But for now we'll play
2236 * safe and change as little as possible.
2237 *
2238 * The 16-bit word has two parts:
2239 *
2240 * The first 14-bit forms the @a idx field. It is either the index of a page in
2241 * the shadow page pool, or and index into the extent list.
2242 *
2243 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2244 * shadow page pool references to the page. If cRefs equals
2245 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2246 * (misnomer) table and not the shadow page pool.
2247 *
2248 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2249 * the 16-bit word.
2250 *
2251 * @{ */
2252/** The shift count for getting to the cRefs part. */
2253#define PGMPOOL_TD_CREFS_SHIFT 14
2254/** The mask applied after shifting the tracking data down by
2255 * PGMPOOL_TD_CREFS_SHIFT. */
2256#define PGMPOOL_TD_CREFS_MASK 0x3
2257/** The cRefs value used to indicate that the idx is the head of a
2258 * physical cross reference list. */
2259#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2260/** The shift used to get idx. */
2261#define PGMPOOL_TD_IDX_SHIFT 0
2262/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2263#define PGMPOOL_TD_IDX_MASK 0x3fff
2264/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2265 * simply too many mappings of this page. */
2266#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2267
2268/** @def PGMPOOL_TD_MAKE
2269 * Makes a 16-bit tracking data word.
2270 *
2271 * @returns tracking data.
2272 * @param cRefs The @a cRefs field. Must be within bounds!
2273 * @param idx The @a idx field. Must also be within bounds! */
2274#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2275
2276/** @def PGMPOOL_TD_GET_CREFS
2277 * Get the @a cRefs field from a tracking data word.
2278 *
2279 * @returns The @a cRefs field
2280 * @param u16 The tracking data word.
2281 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2282 * non-zero @a u16. */
2283#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2284
2285/** @def PGMPOOL_TD_GET_IDX
2286 * Get the @a idx field from a tracking data word.
2287 *
2288 * @returns The @a idx field
2289 * @param u16 The tracking data word. */
2290#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2291/** @} */
2292
2293
2294
2295/** @name A20 gate macros
2296 * @{ */
2297#define PGM_WITH_A20
2298#ifdef PGM_WITH_A20
2299# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2300# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2301# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2302 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2303# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2304#else
2305# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2306# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2307# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2308# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2309#endif
2310/** @} */
2311
2312
2313/**
2314 * Roots and anchors for trees and list employing self relative offsets as
2315 * pointers.
2316 *
2317 * When using self-relative offsets instead of pointers, the offsets needs to be
2318 * the same in all offsets. Thus the roots and anchors needs to live on the
2319 * hyper heap just like the nodes.
2320 */
2321typedef struct PGMTREES
2322{
2323 /** List of physical access handler types (offset pointers) of type
2324 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2325 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2326 /** Physical access handlers (AVL range+offsetptr tree). */
2327 AVLROGCPHYSTREE PhysHandlers;
2328} PGMTREES;
2329/** Pointer to PGM trees. */
2330typedef PGMTREES *PPGMTREES;
2331
2332
2333/** @name PGMPTATTRS
2334 *
2335 * PGM page-table attributes.
2336 *
2337 * This is VirtualBox's combined page table attributes. It combines regular page
2338 * table and Intel EPT attributes. It's 64-bit in size so there's ample room for
2339 * bits added in the future to EPT or regular page tables (for e.g. Protection Key).
2340 *
2341 * The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
2342 * attributes as these are unique to EPT and fit within 64-bits despite the shift:
2343 * - EPT_R : Read access.
2344 * - EPT_W : Write access.
2345 * - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
2346 * - EPT_MEMTYPE : EPT memory type.
2347 * - EPT_IGNORE_PAT: Ignore PAT memory type.
2348 * - EPT_X_USER : Execute access for user-mode linear addresses.
2349 *
2350 * For regular page tables, the R bit is always 1 (same as P bit).
2351 * For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
2352 *
2353 * The following EPT attributes are mapped to the following positions because they
2354 * exist in the regular page tables at these positions OR are exclusive to EPT and
2355 * have been mapped to arbitrarily chosen positions:
2356 * - EPT_A : Accessed (EPT bit 8 maps to bit 5).
2357 * - EPT_D : Dirty (EPT bit 9 maps to bit 6).
2358 * - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
2359 * - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
2360 *
2361 * Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
2362 * 11:9 in the regular page-table structures and to bit 11 in the EPT structures
2363 * respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
2364 * use by software and we may want to use/preserve them in the future.
2365 *
2366 * @{ */
2367typedef uint64_t PGMPTATTRS;
2368/** Pointer to a PGMPTATTRS type. */
2369typedef PGMPTATTRS *PPGMPTATTRS;
2370
2371/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
2372#define PGM_PTATTRS_R_SHIFT 0
2373#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
2374/** Write access bit (aka read/write bit for regular PT). */
2375#define PGM_PTATTRS_W_SHIFT 1
2376#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
2377/** User-mode access bit. */
2378#define PGM_PTATTRS_US_SHIFT 2
2379#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
2380/** Write through cache bit. */
2381#define PGM_PTATTRS_PWT_SHIFT 3
2382#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
2383/** Cache disabled bit. */
2384#define PGM_PTATTRS_PCD_SHIFT 4
2385#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
2386/** Accessed bit. */
2387#define PGM_PTATTRS_A_SHIFT 5
2388#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
2389/** Dirty bit. */
2390#define PGM_PTATTRS_D_SHIFT 6
2391#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
2392/** The PAT bit. */
2393#define PGM_PTATTRS_PAT_SHIFT 7
2394#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
2395/** The global bit. */
2396#define PGM_PTATTRS_G_SHIFT 8
2397#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
2398/** Reserved (bits 12:9) unused. */
2399#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
2400#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
2401/** Read access bit - EPT only. */
2402#define PGM_PTATTRS_EPT_R_SHIFT 13
2403#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
2404/** Write access bit - EPT only. */
2405#define PGM_PTATTRS_EPT_W_SHIFT 14
2406#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
2407/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
2408#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
2409#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
2410/** EPT memory type - EPT only. */
2411#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
2412#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
2413/** Ignore PAT memory type - EPT only. */
2414#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
2415#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
2416/** Reserved (bits 22:20) unused. */
2417#define PGM_PTATTRS_RSVD_22_20_SHIFT 20
2418#define PGM_PTATTRS_RSVD_22_20_MASK UINT64_C(0x0000000000700000)
2419/** Execute access for user-mode linear addresses - EPT only. */
2420#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
2421#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
2422/** Reserved (bit 23) - unused. */
2423#define PGM_PTATTRS_RSVD_23_SHIFT 24
2424#define PGM_PTATTRS_RSVD_23_MASK UINT64_C(0x0000000001000000)
2425/** Supervisor shadow stack - EPT only. */
2426#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT 25
2427#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT)
2428/** Suppress \#VE exception - EPT only. */
2429#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT 26
2430#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT)
2431/** Reserved (bits 62:27) - unused. */
2432#define PGM_PTATTRS_RSVD_62_27_SHIFT 27
2433#define PGM_PTATTRS_RSVD_62_27_MASK UINT64_C(0x7ffffffff8000000)
2434/** No-execute bit. */
2435#define PGM_PTATTRS_NX_SHIFT 63
2436#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
2437
2438RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
2439 (R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
2440 RSVD_22_20, EPT_X_USER, RSVD_23, EPT_SUPER_SHW_STACK, EPT_SUPPRESS_VE_XCPT, RSVD_62_27, NX));
2441
2442/** The bit position where the EPT specific attributes begin. */
2443#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
2444/** The mask of EPT bits (bits 26:ATTR_SHIFT). In the future we might choose to
2445 * use higher unused bits for something else, in that case adjust this mask. */
2446#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000000007ffe000)
2447
2448/** The mask of all PGM page attribute bits for regular page-tables. */
2449#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
2450 | PGM_PTATTRS_W_MASK \
2451 | PGM_PTATTRS_US_MASK \
2452 | PGM_PTATTRS_PWT_MASK \
2453 | PGM_PTATTRS_PCD_MASK \
2454 | PGM_PTATTRS_A_MASK \
2455 | PGM_PTATTRS_D_MASK \
2456 | PGM_PTATTRS_PAT_MASK \
2457 | PGM_PTATTRS_G_MASK \
2458 | PGM_PTATTRS_NX_MASK)
2459
2460/** The mask of all PGM page attribute bits for EPT. */
2461#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_R_MASK \
2462 | PGM_PTATTRS_W_MASK \
2463 | PGM_PTATTRS_A_MASK \
2464 | PGM_PTATTRS_D_MASK \
2465 | PGM_PTATTRS_EPT_R_MASK \
2466 | PGM_PTATTRS_EPT_W_MASK \
2467 | PGM_PTATTRS_EPT_X_SUPER \
2468 | PGM_PTATTRS_EPT_MEMTYPE \
2469 | PGM_PTATTRS_EPT_IGNORE_PAT \
2470 | PGM_PTATTRS_EPT_X_USER \
2471 | PGM_PTATTRS_EPT_SUPER_SHW_STACK \
2472 | PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT)
2473
2474/* The mask of all PGM page attribute bits (combined). */
2475#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK | PGM_PTATTRS_PT_VALID_MASK)
2476
2477/* Verify bits match the regular PT bits. */
2478AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
2479AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
2480AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
2481AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
2482AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
2483AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
2484AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
2485AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
2486AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
2487AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
2488AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
2489AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
2490AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
2491AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
2492AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
2493AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
2494
2495/* Verify those EPT bits that must map 1:1 (after shifting). */
2496AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
2497AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
2498AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
2499AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
2500AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
2501/** @} */
2502
2503
2504/**
2505 * Page fault guest state for the AMD64 paging mode.
2506 */
2507typedef struct PGMPTWALKCORE
2508{
2509 /** The guest virtual address that is being resolved by the walk
2510 * (input). */
2511 RTGCPTR GCPtr;
2512
2513 /** The nested-guest physical address that is being resolved if this is a
2514 * second-level walk (input).
2515 * @remarks only valid if fIsSlat is set. */
2516 RTGCPHYS GCPhysNested;
2517
2518 /** The guest physical address that is the result of the walk.
2519 * @remarks only valid if fSucceeded is set. */
2520 RTGCPHYS GCPhys;
2521
2522 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2523 bool fSucceeded;
2524 /** Whether this is a second-level translation. */
2525 bool fIsSlat;
2526 /** Whether the linear address (GCPtr) is valid and thus the cause for the
2527 * second-level translation. */
2528 bool fIsLinearAddrValid;
2529 /** The level problem arrised at.
2530 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2531 * level 8. This is 0 on success. */
2532 uint8_t uLevel;
2533 /** Set if the page isn't present. */
2534 bool fNotPresent;
2535 /** Encountered a bad physical address. */
2536 bool fBadPhysAddr;
2537 /** Set if there was reserved bit violations. */
2538 bool fRsvdError;
2539 /** Set if it involves a big page (2/4 MB). */
2540 bool fBigPage;
2541 /** Set if it involves a gigantic page (1 GB). */
2542 bool fGigantPage;
2543 bool afPadding[7];
2544 /** The effective attributes, PGM_PTATTRS_XXX. */
2545 PGMPTATTRS fEffective;
2546} PGMPTWALKCORE;
2547
2548/**
2549 * Guest page table walk for the AMD64 mode.
2550 */
2551typedef struct PGMPTWALKGSTAMD64
2552{
2553 /** The common core. */
2554 PGMPTWALKCORE Core;
2555
2556 PX86PML4 pPml4;
2557 PX86PML4E pPml4e;
2558 X86PML4E Pml4e;
2559
2560 PX86PDPT pPdpt;
2561 PX86PDPE pPdpe;
2562 X86PDPE Pdpe;
2563
2564 PX86PDPAE pPd;
2565 PX86PDEPAE pPde;
2566 X86PDEPAE Pde;
2567
2568 PX86PTPAE pPt;
2569 PX86PTEPAE pPte;
2570 X86PTEPAE Pte;
2571} PGMPTWALKGSTAMD64;
2572/** Pointer to a AMD64 guest page table walk. */
2573typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2574/** Pointer to a const AMD64 guest page table walk. */
2575typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2576
2577/**
2578 * Guest page table walk for the EPT mode.
2579 */
2580typedef struct PGMPTWALKGSTEPT
2581{
2582 /** The common core. */
2583 PGMPTWALKCORE Core;
2584
2585 PEPTPML4 pPml4;
2586 PEPTPML4E pPml4e;
2587 EPTPML4E Pml4e;
2588
2589 PEPTPDPT pPdpt;
2590 PEPTPDPTE pPdpte;
2591 EPTPDPTE Pdpte;
2592
2593 PEPTPD pPd;
2594 PEPTPDE pPde;
2595 EPTPDE Pde;
2596
2597 PEPTPT pPt;
2598 PEPTPTE pPte;
2599 EPTPTE Pte;
2600} PGMPTWALKGSTEPT;
2601/** Pointer to an EPT guest page table walk. */
2602typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2603/** Pointer to a const EPT guest page table walk. */
2604typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2605
2606/**
2607 * Guest page table walk for the PAE mode.
2608 */
2609typedef struct PGMPTWALKGSTPAE
2610{
2611 /** The common core. */
2612 PGMPTWALKCORE Core;
2613
2614 PX86PDPT pPdpt;
2615 PX86PDPE pPdpe;
2616 X86PDPE Pdpe;
2617
2618 PX86PDPAE pPd;
2619 PX86PDEPAE pPde;
2620 X86PDEPAE Pde;
2621
2622 PX86PTPAE pPt;
2623 PX86PTEPAE pPte;
2624 X86PTEPAE Pte;
2625} PGMPTWALKGSTPAE;
2626/** Pointer to a PAE guest page table walk. */
2627typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2628/** Pointer to a const AMD64 guest page table walk. */
2629typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2630
2631/**
2632 * Guest page table walk for the 32-bit mode.
2633 */
2634typedef struct PGMPTWALKGST32BIT
2635{
2636 /** The common core. */
2637 PGMPTWALKCORE Core;
2638
2639 PX86PD pPd;
2640 PX86PDE pPde;
2641 X86PDE Pde;
2642
2643 PX86PT pPt;
2644 PX86PTE pPte;
2645 X86PTE Pte;
2646} PGMPTWALKGST32BIT;
2647/** Pointer to a 32-bit guest page table walk. */
2648typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2649/** Pointer to a const 32-bit guest page table walk. */
2650typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2651
2652/**
2653 * Which part of PGMPTWALKGST that is valid.
2654 */
2655typedef enum PGMPTWALKGSTTYPE
2656{
2657 /** Customary invalid 0 value. */
2658 PGMPTWALKGSTTYPE_INVALID = 0,
2659 /** PGMPTWALKGST::u.Amd64 is valid. */
2660 PGMPTWALKGSTTYPE_AMD64,
2661 /** PGMPTWALKGST::u.Pae is valid. */
2662 PGMPTWALKGSTTYPE_PAE,
2663 /** PGMPTWALKGST::u.Legacy is valid. */
2664 PGMPTWALKGSTTYPE_32BIT,
2665 /** PGMPTWALKGST::u.Ept is valid. */
2666 PGMPTWALKGSTTYPE_EPT,
2667 /** Customary 32-bit type hack. */
2668 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2669} PGMPTWALKGSTTYPE;
2670
2671/**
2672 * Combined guest page table walk result.
2673 */
2674typedef struct PGMPTWALKGST
2675{
2676 union
2677 {
2678 /** The page walker core - always valid. */
2679 PGMPTWALKCORE Core;
2680 /** The page walker for AMD64. */
2681 PGMPTWALKGSTAMD64 Amd64;
2682 /** The page walker for PAE (32-bit). */
2683 PGMPTWALKGSTPAE Pae;
2684 /** The page walker for 32-bit paging (called legacy due to C naming
2685 * convension). */
2686 PGMPTWALKGST32BIT Legacy;
2687 /** The page walker for EPT (SLAT). */
2688 PGMPTWALKGSTEPT Ept;
2689 } u;
2690 /** Indicates which part of the union is valid. */
2691 PGMPTWALKGSTTYPE enmType;
2692} PGMPTWALKGST;
2693/** Pointer to a combined guest page table walk result. */
2694typedef PGMPTWALKGST *PPGMPTWALKGST;
2695/** Pointer to a read-only combined guest page table walk result. */
2696typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2697
2698
2699/** @name Paging mode macros
2700 * @{
2701 */
2702#ifdef IN_RING3
2703# define PGM_CTX(a,b) a##R3##b
2704# define PGM_CTX_STR(a,b) a "R3" b
2705# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2706#elif defined(IN_RING0)
2707# define PGM_CTX(a,b) a##R0##b
2708# define PGM_CTX_STR(a,b) a "R0" b
2709# define PGM_CTX_DECL(type) VMMDECL(type)
2710#else
2711# error "Not IN_RING3 or IN_RING0!"
2712#endif
2713
2714#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2715#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2716#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2717#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2718#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2719#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2720#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2721#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2722#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2723#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2724#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2725#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2726#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2727#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2728#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2729#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2730
2731#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2732#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2733#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2734#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2735
2736#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2737#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2738#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2739#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2740#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2741#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2742#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2743#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2744#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2745#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2746#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2747#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2748#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2749#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2750#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2751#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2752#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2753#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2754#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2755#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2756#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2757#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2758#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2759#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2760#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2761
2762/* Shw_Gst */
2763#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2764#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2765#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2766#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2767#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2768#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2769#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2770#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2771#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2772#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2773#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2774#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2775#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2776#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2777#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2778#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2779#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2780#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2781#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2782#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2783#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2784#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2785#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2786#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2787#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2788#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2789#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2790#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2791#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2792#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2793#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2794#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2795#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2796#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2797
2798#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2799#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2800#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2801#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2802#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2803#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2804#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2805#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2806#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2807#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2808#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2809#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2810#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2811#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2812#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2813#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2814#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2815#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2816#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2817#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2818#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2819#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2820#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2821#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2822#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2823#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2824#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2825#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2826
2827#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2828#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2829#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2830#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2831#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2832#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2833#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2834#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2835#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2836#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2837#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2838#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2839#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2840#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2841#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2842#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2843#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2844#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2845#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2846#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2847#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2848#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2849#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2850#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2851#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2852#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2853#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2854#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2855#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2856
2857#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2858/** @} */
2859
2860
2861/**
2862 * Function pointers for guest paging.
2863 */
2864typedef struct PGMMODEDATAGST
2865{
2866 /** The guest mode type. */
2867 uint32_t uType;
2868 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2869 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2870 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2871 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2872#ifdef IN_RING3
2873 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2874#endif
2875} PGMMODEDATAGST;
2876
2877/** The length of g_aPgmGuestModeData. */
2878#if VBOX_WITH_64_BITS_GUESTS
2879# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2880#else
2881# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2882#endif
2883/** The guest mode data array. */
2884extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2885
2886
2887/**
2888 * Function pointers for shadow paging.
2889 */
2890typedef struct PGMMODEDATASHW
2891{
2892 /** The shadow mode type. */
2893 uint32_t uType;
2894 DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2895 DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2896 uint64_t fMask, uint32_t fOpFlags));
2897 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2898 DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2899#ifdef IN_RING3
2900 DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /**< Only in ring-3. */
2901#endif
2902} PGMMODEDATASHW;
2903
2904/** The length of g_aPgmShadowModeData. */
2905#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2906/** The shadow mode data array. */
2907extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2908
2909
2910/**
2911 * Function pointers for guest+shadow paging.
2912 */
2913typedef struct PGMMODEDATABTH
2914{
2915 /** The shadow mode type. */
2916 uint32_t uShwType;
2917 /** The guest mode type. */
2918 uint32_t uGstType;
2919
2920 DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2921 DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2922 DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2923 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2924 DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3, bool fPdpesMapped));
2925 DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2926 DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2927#ifndef IN_RING3
2928 DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2929#endif
2930#ifdef VBOX_STRICT
2931 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2932#endif
2933} PGMMODEDATABTH;
2934
2935/** The length of g_aPgmBothModeData. */
2936#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2937/** The guest+shadow mode data array. */
2938extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2939
2940
2941#ifdef VBOX_WITH_STATISTICS
2942/**
2943 * PGM statistics.
2944 */
2945typedef struct PGMSTATS
2946{
2947 /* R3 only: */
2948 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2949 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2950
2951 /* R3+RZ */
2952 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2953 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2954 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2955 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2956 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2957 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2958 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2959 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2960 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2961 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2962 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
2963 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
2964 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
2965 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
2966 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2967 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2968 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2969 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2970 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2971 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2972 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2973 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2974/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2975 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2976 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2977/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2978
2979 /* RC only: */
2980 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2981 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2982
2983 STAMCOUNTER StatRZPhysRead;
2984 STAMCOUNTER StatRZPhysReadBytes;
2985 STAMCOUNTER StatRZPhysWrite;
2986 STAMCOUNTER StatRZPhysWriteBytes;
2987 STAMCOUNTER StatR3PhysRead;
2988 STAMCOUNTER StatR3PhysReadBytes;
2989 STAMCOUNTER StatR3PhysWrite;
2990 STAMCOUNTER StatR3PhysWriteBytes;
2991 STAMCOUNTER StatRCPhysRead;
2992 STAMCOUNTER StatRCPhysReadBytes;
2993 STAMCOUNTER StatRCPhysWrite;
2994 STAMCOUNTER StatRCPhysWriteBytes;
2995
2996 STAMCOUNTER StatRZPhysSimpleRead;
2997 STAMCOUNTER StatRZPhysSimpleReadBytes;
2998 STAMCOUNTER StatRZPhysSimpleWrite;
2999 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3000 STAMCOUNTER StatR3PhysSimpleRead;
3001 STAMCOUNTER StatR3PhysSimpleReadBytes;
3002 STAMCOUNTER StatR3PhysSimpleWrite;
3003 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3004 STAMCOUNTER StatRCPhysSimpleRead;
3005 STAMCOUNTER StatRCPhysSimpleReadBytes;
3006 STAMCOUNTER StatRCPhysSimpleWrite;
3007 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3008
3009 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3010 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3011 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3012 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3013 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3014 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3015 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3016
3017 STAMPROFILE StatLargePageSetup; /**< Time spent setting up newly allocated large pages. */
3018 /** pgmPhysIsValidLargePage profiling - R3 */
3019 STAMPROFILE StatR3IsValidLargePage;
3020 /** pgmPhysIsValidLargePage profiling - RZ*/
3021 STAMPROFILE StatRZIsValidLargePage;
3022
3023 STAMPROFILE StatChunkAging;
3024 STAMPROFILE StatChunkFindCandidate;
3025 STAMPROFILE StatChunkUnmap;
3026 STAMPROFILE StatChunkMap;
3027} PGMSTATS;
3028#endif /* VBOX_WITH_STATISTICS */
3029
3030
3031/**
3032 * PGM Data (part of VM)
3033 */
3034typedef struct PGM
3035{
3036 /** @cfgm{/RamPreAlloc, boolean, false}
3037 * Indicates whether the base RAM should all be allocated before starting
3038 * the VM (default), or if it should be allocated when first written to.
3039 */
3040 bool fRamPreAlloc;
3041#ifdef VBOX_WITH_PGM_NEM_MODE
3042 /** Set if we're operating in NEM memory mode.
3043 *
3044 * NEM mode implies that memory is allocated in big chunks for each RAM range
3045 * rather than on demand page by page. Memory is also not locked and PGM has
3046 * therefore no physical addresses for them. Page sharing is out of the
3047 * question. Ballooning depends on the native execution engine, but probably
3048 * pointless as well. */
3049 bool fNemMode;
3050# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
3051#else
3052# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
3053#endif
3054 /** Indicates whether write monitoring is currently in use.
3055 * This is used to prevent conflicts between live saving and page sharing
3056 * detection. */
3057 bool fPhysWriteMonitoringEngaged;
3058 /** Set if the CPU has less than 52-bit physical address width.
3059 * This is used */
3060 bool fLessThan52PhysicalAddressBits;
3061 /** Set when nested paging is active.
3062 * This is meant to save calls to HMIsNestedPagingActive and let the
3063 * compilers optimize the code better. Whether we use nested paging or
3064 * not is something we find out during VMM initialization and we won't
3065 * change this later on. */
3066 bool fNestedPaging;
3067 /** We're not in a state which permits writes to guest memory.
3068 * (Only used in strict builds.) */
3069 bool fNoMorePhysWrites;
3070 /** @cfgm{/PageFusionAllowed, boolean, false}
3071 * Whether page fusion is allowed. */
3072 bool fPageFusionAllowed;
3073 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3074 * Whether PCI passthrough is enabled. */
3075 bool fPciPassthrough;
3076 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3077 uint8_t cMmio2Regions;
3078 /** Restore original ROM page content when resetting after loading state.
3079 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3080 * enables the VM to start using an updated ROM without requiring powering
3081 * down the VM, just rebooting or resetting it. */
3082 bool fRestoreRomPagesOnReset;
3083 /** Whether to automatically clear all RAM pages on reset. */
3084 bool fZeroRamPagesOnReset;
3085 /** Large page enabled flag. */
3086 bool fUseLargePages;
3087 /** Alignment padding. */
3088#ifndef VBOX_WITH_PGM_NEM_MODE
3089 bool afAlignment3[1];
3090#endif
3091 /** The host paging mode. (This is what SUPLib reports.) */
3092 SUPPAGINGMODE enmHostMode;
3093 bool afAlignment3b[2];
3094
3095 /** Generation ID for the RAM ranges. This member is incremented everytime
3096 * a RAM range is linked or unlinked. */
3097 uint32_t volatile idRamRangesGen;
3098
3099 /** Physical access handler type for ROM protection. */
3100 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3101 /** Physical access handler type for MMIO2 dirty page tracing. */
3102 PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3103
3104 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3105 RTGCPHYS GCPhys4MBPSEMask;
3106 /** Mask containing the invalid bits of a guest physical address.
3107 * @remarks this does not stop at bit 52. */
3108 RTGCPHYS GCPhysInvAddrMask;
3109
3110
3111 /** RAM range TLB for R3. */
3112 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3113 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3114 * This is sorted by physical address and contains no overlapping ranges. */
3115 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3116 /** Root of the RAM range search tree for ring-3. */
3117 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3118 /** PGM offset based trees - R3 Ptr. */
3119 R3PTRTYPE(PPGMTREES) pTreesR3;
3120 /** Caching the last physical handler we looked up in R3. */
3121 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3122 /** Shadow Page Pool - R3 Ptr. */
3123 R3PTRTYPE(PPGMPOOL) pPoolR3;
3124 /** Pointer to the list of ROM ranges - for R3.
3125 * This is sorted by physical address and contains no overlapping ranges. */
3126 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3127 /** Pointer to the list of MMIO2 ranges - for R3.
3128 * Registration order. */
3129 R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3130 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3131 R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3132
3133 /** RAM range TLB for R0. */
3134 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3135 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3136 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3137 /** Root of the RAM range search tree for ring-0. */
3138 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3139 /** PGM offset based trees - R0 Ptr. */
3140 R0PTRTYPE(PPGMTREES) pTreesR0;
3141 /** Caching the last physical handler we looked up in R0. */
3142 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3143 /** Shadow Page Pool - R0 Ptr. */
3144 R0PTRTYPE(PPGMPOOL) pPoolR0;
3145 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3146 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3147 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3148 R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3149
3150 /** Hack: Number of deprecated page mapping locks taken by the current lock
3151 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3152 uint32_t cDeprecatedPageLocks;
3153 /** Alignment padding. */
3154 uint32_t au32Alignment2[1];
3155
3156 /** PGM critical section.
3157 * This protects the physical, ram ranges, and the page flag updating (some of
3158 * it anyway).
3159 */
3160 PDMCRITSECT CritSectX;
3161
3162 /**
3163 * Data associated with managing the ring-3 mappings of the allocation chunks.
3164 */
3165 struct
3166 {
3167 /** The chunk mapping TLB. */
3168 PGMCHUNKR3MAPTLB Tlb;
3169 /** The chunk tree, ordered by chunk id. */
3170 R3PTRTYPE(PAVLU32NODECORE) pTree;
3171#if HC_ARCH_BITS == 32
3172 uint32_t u32Alignment0;
3173#endif
3174 /** The number of mapped chunks. */
3175 uint32_t c;
3176 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3177 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3178 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3179 uint32_t cMax;
3180 /** The current time. This is incremented whenever a chunk is inserted. */
3181 uint32_t iNow;
3182 /** Alignment padding. */
3183 uint32_t au32Alignment1[3];
3184 } ChunkR3Map;
3185
3186 /** The page mapping TLB for ring-3. */
3187 PGMPAGER3MAPTLB PhysTlbR3;
3188 /** The page mapping TLB for ring-0. */
3189 PGMPAGER0MAPTLB PhysTlbR0;
3190
3191 /** @name The zero page.
3192 * @{ */
3193 /** The host physical address of the zero page. */
3194 RTHCPHYS HCPhysZeroPg;
3195 /** The ring-3 mapping of the zero page. */
3196 RTR3PTR pvZeroPgR3;
3197 /** The ring-0 mapping of the zero page. */
3198 RTR0PTR pvZeroPgR0;
3199 /** @}*/
3200
3201 /** @name The Invalid MMIO page.
3202 * This page is filled with 0xfeedface.
3203 * @{ */
3204 /** The host physical address of the invalid MMIO page. */
3205 RTHCPHYS HCPhysMmioPg;
3206 /** The host pysical address of the invalid MMIO page plus all invalid
3207 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3208 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3209 RTHCPHYS HCPhysInvMmioPg;
3210 /** The ring-3 mapping of the invalid MMIO page. */
3211 RTR3PTR pvMmioPgR3;
3212#if HC_ARCH_BITS == 32
3213 RTR3PTR R3PtrAlignment4;
3214#endif
3215 /** @} */
3216
3217
3218 /** The number of handy pages. */
3219 uint32_t cHandyPages;
3220
3221 /** The number of large handy pages. */
3222 uint32_t cLargeHandyPages;
3223
3224 /**
3225 * Array of handy pages.
3226 *
3227 * This array is used in a two way communication between pgmPhysAllocPage
3228 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3229 * an intermediary.
3230 *
3231 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3232 * (The current size of 32 pages, means 128 KB of handy memory.)
3233 */
3234 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3235
3236 /**
3237 * Array of large handy pages. (currently size 1)
3238 *
3239 * This array is used in a two way communication between pgmPhysAllocLargePage
3240 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3241 * an intermediary.
3242 */
3243 GMMPAGEDESC aLargeHandyPage[1];
3244 /** When to try allocate large pages again after a failure. */
3245 uint64_t nsLargePageRetry;
3246 /** Number of repeated long allocation times. */
3247 uint32_t cLargePageLongAllocRepeats;
3248 uint32_t uPadding5;
3249
3250 /**
3251 * Live save data.
3252 */
3253 struct
3254 {
3255 /** Per type statistics. */
3256 struct
3257 {
3258 /** The number of ready pages. */
3259 uint32_t cReadyPages;
3260 /** The number of dirty pages. */
3261 uint32_t cDirtyPages;
3262 /** The number of ready zero pages. */
3263 uint32_t cZeroPages;
3264 /** The number of write monitored pages. */
3265 uint32_t cMonitoredPages;
3266 } Rom,
3267 Mmio2,
3268 Ram;
3269 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3270 uint32_t cIgnoredPages;
3271 /** Indicates that a live save operation is active. */
3272 bool fActive;
3273 /** Padding. */
3274 bool afReserved[2];
3275 /** The next history index. */
3276 uint8_t iDirtyPagesHistory;
3277 /** History of the total amount of dirty pages. */
3278 uint32_t acDirtyPagesHistory[64];
3279 /** Short term dirty page average. */
3280 uint32_t cDirtyPagesShort;
3281 /** Long term dirty page average. */
3282 uint32_t cDirtyPagesLong;
3283 /** The number of saved pages. This is used to get some kind of estimate of the
3284 * link speed so we can decide when we're done. It is reset after the first
3285 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3286 * zero pages. */
3287 uint64_t cSavedPages;
3288 /** The nanosecond timestamp when cSavedPages was 0. */
3289 uint64_t uSaveStartNS;
3290 /** Pages per second (for statistics). */
3291 uint32_t cPagesPerSecond;
3292 uint32_t cAlignment;
3293 } LiveSave;
3294
3295 /** @name Error injection.
3296 * @{ */
3297 /** Inject handy page allocation errors pretending we're completely out of
3298 * memory. */
3299 bool volatile fErrInjHandyPages;
3300 /** Padding. */
3301 bool afReserved[3];
3302 /** @} */
3303
3304 /** @name Release Statistics
3305 * @{ */
3306 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3307 uint32_t cPrivatePages; /**< The number of private pages. */
3308 uint32_t cSharedPages; /**< The number of shared pages. */
3309 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3310 uint32_t cZeroPages; /**< The number of zero backed pages. */
3311 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3312 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3313 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3314 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3315 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3316 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3317 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3318 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3319 uint32_t cLargePages; /**< The number of large pages. */
3320 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3321/* uint32_t aAlignment4[1]; */
3322
3323 STAMPROFILE StatLargePageAlloc; /**< Time spent by the host OS for large page allocation. */
3324 STAMCOUNTER StatLargePageOverflow; /**< The number of times allocating a large pages takes more than the allowed period. */
3325 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3326 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3327 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3328 STAMCOUNTER StatLargePageTlbFlush; /**< The number of a full VCPU TLB flush was required after allocation. */
3329 STAMCOUNTER StatLargePageZeroEvict; /**< The number of zero page mappings we had to evict when allocating a large page. */
3330
3331 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3332
3333 STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /**< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. */
3334 /** @} */
3335
3336#ifdef VBOX_WITH_STATISTICS
3337 /** These are optional statistics that used to be on the hyper heap. */
3338 PGMSTATS Stats;
3339#endif
3340} PGM;
3341#ifndef IN_TSTVMSTRUCTGC /* HACK */
3342AssertCompileMemberAlignment(PGM, CritSectX, 8);
3343AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3344AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3345AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3346AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3347AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3348#endif /* !IN_TSTVMSTRUCTGC */
3349/** Pointer to the PGM instance data. */
3350typedef PGM *PPGM;
3351
3352
3353#ifdef VBOX_WITH_STATISTICS
3354/**
3355 * Per CPU statistis for PGM (used to be on the heap).
3356 */
3357typedef struct PGMCPUSTATS
3358{
3359 /* Common */
3360 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3361 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3362
3363 /* R0 only: */
3364 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3365 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3366
3367 /* RZ only: */
3368 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3369 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3370 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3371 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3372 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3373 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3374 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3375 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3376 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3377 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3378 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3379 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3380 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3381 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3382 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3383 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3384 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3385 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3386 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3387 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3388 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3389 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3390 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3391 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3392 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3393 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3394 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3395 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3396 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3397 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3398 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3399 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3400 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3401 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3402 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3403 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3404 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3405 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3406 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3407 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3408 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3409 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3410 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3411 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3412 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3413 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3414 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3415 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3416 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3417 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3418 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3419 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3420 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3421 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3422 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3423 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3424 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3425 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3426 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3427 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3428 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3429 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3430 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3431 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3432 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3433 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3434 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3435 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3436 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3437 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3438
3439 /* HC - R3 and (maybe) R0: */
3440
3441 /* RZ & R3: */
3442 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3443 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3444 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3445 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3446 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3447 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3448 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3449 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3450 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3451 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3452 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3453 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3454 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3455 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3456 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3457 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3458 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3459 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3460 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3461 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3462 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3463 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3464 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3465 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3466 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3467 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3468 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3469 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3470 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3471 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3472 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3473 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3474 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3475 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3476 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3477 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3478 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3479 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3480 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3481 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3482 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3483 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3484 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3485 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3486 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3487 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3488 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3489
3490 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3491 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3492 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3493 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3494 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3495 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3496 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3497 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3498 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3499 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3500 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3501 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3502 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3503 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3504 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3505 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3506 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3507 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3508 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3509 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3510 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3511 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3512 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3513 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3514 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3515 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3516 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3517 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3518 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3519 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3520 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3521 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3522 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3523 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3524 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3525 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3526 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3527 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3528 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3529 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3530 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3531 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3532 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3533 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3534 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3535 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3536} PGMCPUSTATS;
3537#endif /* VBOX_WITH_STATISTICS */
3538
3539
3540/**
3541 * PGMCPU Data (part of VMCPU).
3542 */
3543typedef struct PGMCPU
3544{
3545 /** A20 gate mask.
3546 * Our current approach to A20 emulation is to let REM do it and don't bother
3547 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3548 * But whould need arrise, we'll subject physical addresses to this mask. */
3549 RTGCPHYS GCPhysA20Mask;
3550 /** A20 gate state - boolean! */
3551 bool fA20Enabled;
3552 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3553 bool fNoExecuteEnabled;
3554 /** Unused bits. */
3555 bool afUnused[2];
3556
3557 /** What needs syncing (PGM_SYNC_*).
3558 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3559 * PGMFlushTLB, and PGMR3Load. */
3560 uint32_t fSyncFlags;
3561
3562 /** The shadow paging mode. */
3563 PGMMODE enmShadowMode;
3564 /** The guest paging mode. */
3565 PGMMODE enmGuestMode;
3566 /** The guest second level address translation mode. */
3567 PGMSLAT enmGuestSlatMode;
3568 /** Guest mode data table index (PGM_TYPE_XXX). */
3569 uint8_t volatile idxGuestModeData;
3570 /** Shadow mode data table index (PGM_TYPE_XXX). */
3571 uint8_t volatile idxShadowModeData;
3572 /** Both mode data table index (complicated). */
3573 uint8_t volatile idxBothModeData;
3574 /** Alignment padding. */
3575 uint8_t abPadding[1];
3576
3577 /** The current physical address represented in the guest CR3 register. */
3578 RTGCPHYS GCPhysCR3;
3579
3580 /** @name 32-bit Guest Paging.
3581 * @{ */
3582 /** The guest's page directory, R3 pointer. */
3583 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3584 /** The guest's page directory, R0 pointer. */
3585 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3586 /** Mask containing the MBZ bits of a big page PDE. */
3587 uint32_t fGst32BitMbzBigPdeMask;
3588 /** Set if the page size extension (PSE) is enabled. */
3589 bool fGst32BitPageSizeExtension;
3590 /** Alignment padding. */
3591 bool afAlignment2[3];
3592 /** @} */
3593
3594 /** @name PAE Guest Paging.
3595 * @{ */
3596 /** The guest's page directory pointer table, R3 pointer. */
3597 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3598 /** The guest's page directory pointer table, R0 pointer. */
3599 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3600
3601 /** The guest's page directories, R3 pointers.
3602 * These are individual pointers and don't have to be adjacent.
3603 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3604 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3605 /** The guest's page directories, R0 pointers.
3606 * Same restrictions as apGstPaePDsR3. */
3607 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3608 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3609 RTGCPHYS aGCPhysGstPaePDs[4];
3610 /** The physical addresses of the monitored guest page directories (PAE). */
3611 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3612 /** Mask containing the MBZ PTE bits. */
3613 uint64_t fGstPaeMbzPteMask;
3614 /** Mask containing the MBZ PDE bits. */
3615 uint64_t fGstPaeMbzPdeMask;
3616 /** Mask containing the MBZ big page PDE bits. */
3617 uint64_t fGstPaeMbzBigPdeMask;
3618 /** Mask containing the MBZ PDPE bits. */
3619 uint64_t fGstPaeMbzPdpeMask;
3620 /** @} */
3621
3622 /** @name AMD64 Guest Paging.
3623 * @{ */
3624 /** The guest's page directory pointer table, R3 pointer. */
3625 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3626 /** The guest's page directory pointer table, R0 pointer. */
3627 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3628 /** Mask containing the MBZ PTE bits. */
3629 uint64_t fGstAmd64MbzPteMask;
3630 /** Mask containing the MBZ PDE bits. */
3631 uint64_t fGstAmd64MbzPdeMask;
3632 /** Mask containing the MBZ big page PDE bits. */
3633 uint64_t fGstAmd64MbzBigPdeMask;
3634 /** Mask containing the MBZ PDPE bits. */
3635 uint64_t fGstAmd64MbzPdpeMask;
3636 /** Mask containing the MBZ big page PDPE bits. */
3637 uint64_t fGstAmd64MbzBigPdpeMask;
3638 /** Mask containing the MBZ PML4E bits. */
3639 uint64_t fGstAmd64MbzPml4eMask;
3640 /** Mask containing the PDPE bits that we shadow. */
3641 uint64_t fGstAmd64ShadowedPdpeMask;
3642 /** Mask containing the PML4E bits that we shadow. */
3643 uint64_t fGstAmd64ShadowedPml4eMask;
3644 /** @} */
3645
3646 /** @name PAE and AMD64 Guest Paging.
3647 * @{ */
3648 /** Mask containing the PTE bits that we shadow. */
3649 uint64_t fGst64ShadowedPteMask;
3650 /** Mask containing the PDE bits that we shadow. */
3651 uint64_t fGst64ShadowedPdeMask;
3652 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3653 uint64_t fGst64ShadowedBigPdeMask;
3654 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3655 uint64_t fGst64ShadowedBigPde4PteMask;
3656 /** @} */
3657
3658 /** @name EPT Guest Paging.
3659 * @{ */
3660 /** The guest's page directory pointer table, R3 pointer. */
3661 R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3662 /** The guest's page directory pointer table, R0 pointer. */
3663 R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3664 /** The guest's EPT pointer (copy of virtual VMCS). */
3665 uint64_t uEptPtr;
3666 /** Mask containing the MBZ PTE bits. */
3667 uint64_t fGstEptMbzPteMask;
3668 /** Mask containing the MBZ PDE bits. */
3669 uint64_t fGstEptMbzPdeMask;
3670 /** Mask containing the MBZ big page (2M) PDE bits. */
3671 uint64_t fGstEptMbzBigPdeMask;
3672 /** Mask containing the MBZ PDPTE bits. */
3673 uint64_t fGstEptMbzPdpteMask;
3674 /** Mask containing the MBZ big page (1G) PDPTE bits. */
3675 uint64_t fGstEptMbzBigPdpteMask;
3676 /** Mask containing the MBZ PML4E bits. */
3677 uint64_t fGstEptMbzPml4eMask;
3678 /** Mask to determine whether an entry is present. */
3679 uint64_t fGstEptPresentMask;
3680 /** Mask containing the PML4E bits that we shadow. */
3681 uint64_t fGstEptShadowedPml4eMask;
3682 /** Mask containing the PDPE bits that we shadow. */
3683 uint64_t fGstEptShadowedPdpeMask;
3684 /** Mask containing the big page PDPE bits that we shadow. */
3685 uint64_t fGstEptShadowedBigPdpeMask;
3686 /** Mask containing the PDE bits that we shadow. */
3687 uint64_t fGstEptShadowedPdeMask;
3688 /** Mask containing the big page PDE bits that we shadow. */
3689 uint64_t fGstEptShadowedBigPdeMask;
3690 /** Mask containing the PTE bits that we shadow. */
3691 uint64_t fGstEptShadowedPteMask;
3692 /** @} */
3693
3694 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3695 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3696 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3697 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3698
3699 /** For saving stack space, the disassembler state is allocated here instead of
3700 * on the stack. */
3701 DISCPUSTATE DisState;
3702
3703 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
3704 uint64_t cNetwareWp0Hacks;
3705
3706 /** Count the number of pgm pool access handler calls. */
3707 uint64_t cPoolAccessHandler;
3708
3709 /** @name Release Statistics
3710 * @{ */
3711 /** The number of times the guest has switched mode since last reset or statistics reset. */
3712 STAMCOUNTER cGuestModeChanges;
3713 /** The number of times the guest has switched mode since last reset or statistics reset. */
3714 STAMCOUNTER cA20Changes;
3715 /** @} */
3716
3717#ifdef VBOX_WITH_STATISTICS
3718 /** These are statistics that used to be on the hyper heap. */
3719 PGMCPUSTATS Stats;
3720#endif
3721} PGMCPU;
3722/** Pointer to the per-cpu PGM data. */
3723typedef PGMCPU *PPGMCPU;
3724
3725
3726/** @name PGM::fSyncFlags Flags
3727 * @note Was part of saved state a long time ago.
3728 * @{
3729 */
3730/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3731/** Always sync CR3. */
3732#define PGM_SYNC_ALWAYS RT_BIT(1)
3733/** Check guest mapping in SyncCR3. */
3734#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3735/** Clear the page pool (a light weight flush). */
3736#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3737#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3738/** @} */
3739
3740
3741/**
3742 * PGM GVMCPU instance data.
3743 */
3744typedef struct PGMR0PERVCPU
3745{
3746#ifdef VBOX_WITH_STATISTICS
3747 /** R0: Which statistic this \#PF should be attributed to. */
3748 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3749#endif
3750 uint64_t u64Dummy;
3751} PGMR0PERVCPU;
3752
3753
3754/**
3755 * PGM GVM instance data.
3756 */
3757typedef struct PGMR0PERVM
3758{
3759 /** @name PGM Pool related stuff.
3760 * @{ */
3761 /** Critical section for serializing pool growth. */
3762 RTCRITSECT PoolGrowCritSect;
3763 /** The memory objects for the pool pages. */
3764 RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3765 /** The ring-3 mapping objects for the pool pages. */
3766 RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3767 /** @} */
3768} PGMR0PERVM;
3769
3770RT_C_DECLS_BEGIN
3771
3772#if defined(VBOX_STRICT)
3773int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3774# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3775# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3776#else
3777int pgmLock(PVMCC pVM, bool fVoid);
3778# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3779# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3780#endif
3781void pgmUnlock(PVMCC pVM);
3782# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3783/**
3784 * Asserts that the caller owns the PDM lock.
3785 * This is the internal variant of PGMIsLockOwner.
3786 * @param a_pVM Pointer to the VM.
3787 */
3788#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3789/**
3790 * Asserts that the caller owns the PDM lock.
3791 * This is the internal variant of PGMIsLockOwner.
3792 * @param a_pVM Pointer to the VM.
3793 * @param a_pVCpu The current CPU handle.
3794 */
3795#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3796
3797int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
3798 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
3799int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3800int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3801int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3802int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3803void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3804bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3805void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3806DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3807DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3808int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3809
3810int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3811int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3812#ifdef IN_RING0
3813int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3814#endif
3815int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3816int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3817int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3818void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3819int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3820int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3821int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3822int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3823int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3824int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3825int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3826int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3827int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3828int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3829void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3830PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3831PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3832#ifndef IN_RING3
3833DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3834DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3835DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3836DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3837#endif
3838int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3839 PGMPAGETYPE enmNewType);
3840void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3841void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3842void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3843PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3844PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3845PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3846int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3847int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3848#ifdef VBOX_WITH_NATIVE_NEM
3849void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3850#endif
3851
3852#ifdef IN_RING3
3853void pgmR3PhysRelinkRamRanges(PVM pVM);
3854int pgmR3PhysRamPreAllocate(PVM pVM);
3855int pgmR3PhysRamReset(PVM pVM);
3856int pgmR3PhysRomReset(PVM pVM);
3857int pgmR3PhysRamZeroAll(PVM pVM);
3858int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3859int pgmR3PhysRamTerm(PVM pVM);
3860void pgmR3PhysRomTerm(PVM pVM);
3861void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3862
3863int pgmR3PoolInit(PVM pVM);
3864void pgmR3PoolRelocate(PVM pVM);
3865void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3866void pgmR3PoolReset(PVM pVM);
3867void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3868DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3869void pgmR3PoolWriteProtectPages(PVM pVM);
3870
3871#endif /* IN_RING3 */
3872int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3873 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3874void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3875void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3876int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3877void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3878PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3879PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3880int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3881int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3882bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3883void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3884int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3885void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3886uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3887void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3888void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3889void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3890PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3891#ifndef IN_RING3
3892DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3893#endif
3894
3895void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3896void pgmPoolResetDirtyPages(PVMCC pVM);
3897void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3898
3899int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3900int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3901void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3902
3903int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3904int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3905int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3906
3907int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3908int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3909int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3910int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3911#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3912int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3913#endif
3914int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3915int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
3916
3917# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3918FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3919FNDBGCCMD pgmR3CmdShowSharedModules;
3920# endif
3921
3922void pgmLogState(PVM pVM);
3923
3924RT_C_DECLS_END
3925
3926/** @} */
3927
3928#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3929
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