PGMInternal.h@ 93646

Last change on this file since 93646 was 93635, checked in by vboxsync, 3 years ago
VMM/PGM,VMM/PDM,VGA: Consolidate the user parameters of the physical access handlers into a single uint64_t value that shouldn't be a pointer, at least not for ring-0 callbacks. Special hack for devices where it's translated from a ring-0 device instance index into a current context PPDMDEVINS (not really tested yet). bugref:10094
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 170.0 KB

Line
1	/* $Id: PGMInternal.h 93635 2022-02-07 10:43:45Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
19	#define VMM_INCLUDED_SRC_include_PGMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/err.h>
27	#include <VBox/dbg.h>
28	#include <VBox/vmm/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm/vmm.h>
31	#include <VBox/vmm/mm.h>
32	#include <VBox/vmm/pdmcritsect.h>
33	#include <VBox/vmm/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/vmm/gmm.h>
38	#include <VBox/vmm/hm.h>
39	#include <iprt/asm.h>
40	#include <iprt/assert.h>
41	#include <iprt/avl.h>
42	#include <iprt/critsect.h>
43	#include <iprt/list-off32.h>
44	#include <iprt/sha.h>
45
46
47
48	/** @defgroup grp_pgm_int Internals
49	* @ingroup grp_pgm
50	* @internal
51	* @{
52	*/
53
54
55	/** @name PGM Compile Time Config
56	* @{
57	*/
58
59	/**
60	* Check and skip global PDEs for non-global flushes
61	*/
62	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
63
64	/**
65	* Optimization for PAE page tables that are modified often
66	*/
67	//#if 0 /* disabled again while debugging */
68	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
69	//#endif
70
71	/**
72	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
73	*/
74	#define PGM_WITH_LARGE_PAGES
75
76	/**
77	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
78	* VMX_EXIT_EPT_MISCONFIG.
79	*/
80	#define PGM_WITH_MMIO_OPTIMIZATIONS
81
82	/**
83	* Sync N pages instead of a whole page table
84	*/
85	#define PGM_SYNC_N_PAGES
86
87	/**
88	* Number of pages to sync during a page fault
89	*
90	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
91	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
92	*
93	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
94	* world switch overhead, so let's sync more.
95	*/
96	#ifdef IN_RING0
97	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
98	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
99	* but ~5% fewer faults.
100	*/
101	# define PGM_SYNC_NR_PAGES 32
102	#else
103	# define PGM_SYNC_NR_PAGES 8
104	#endif
105
106	/**
107	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
108	*/
109	#define PGM_MAX_PHYSCACHE_ENTRIES 64
110	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
111
112
113	/** @def PGMPOOL_CFG_MAX_GROW
114	* The maximum number of pages to add to the pool in one go.
115	*/
116	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
117
118	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
119	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
120	*/
121	#ifdef VBOX_STRICT
122	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
123	#endif
124
125	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
126	* Enables the experimental lazy page allocation code. */
127	#ifdef DOXYGEN_RUNNING
128	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
129	#endif
130
131	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
132	* Enables real write monitoring of pages, i.e. mapping them read-only and
133	* only making them writable when getting a write access \#PF. */
134	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
135
136	/** @def VBOX_WITH_PGM_NEM_MODE
137	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
138	* details. */
139	#ifdef DOXYGEN_RUNNING
140	# define VBOX_WITH_PGM_NEM_MODE
141	#endif
142
143	/** @} */
144
145
146	/** @name PDPT and PML4 flags.
147	* These are placed in the three bits available for system programs in
148	* the PDPT and PML4 entries.
149	* @{ */
150	/** The entry is a permanent one and it's must always be present.
151	* Never free such an entry. */
152	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
153	/** PGM specific bits in PML4 entries. */
154	#define PGM_PML4_FLAGS 0
155	/** PGM specific bits in PDPT entries. */
156	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
157	/** @} */
158
159	/** @name Page directory flags.
160	* These are placed in the three bits available for system programs in
161	* the page directory entries.
162	* @{ */
163	/** Indicates the original entry was a big page.
164	* @remarks This is currently only used for statistics and can be recycled. */
165	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
166	/** Made read-only to facilitate dirty bit tracking. */
167	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
168	/** @} */
169
170	/** @name Page flags.
171	* These are placed in the three bits available for system programs in
172	* the page entries.
173	* @{ */
174	/** Made read-only to facilitate dirty bit tracking. */
175	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
176
177	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
178	/** Scanned and approved by CSAM (tm).
179	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
180	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
181	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
182	#endif
183
184	/** @} */
185
186	/** @name Defines used to indicate the shadow and guest paging in the templates.
187	* @{ */
188	#define PGM_TYPE_REAL 1
189	#define PGM_TYPE_PROT 2
190	#define PGM_TYPE_32BIT 3
191	#define PGM_TYPE_PAE 4
192	#define PGM_TYPE_AMD64 5
193	#define PGM_TYPE_NESTED_32BIT 6
194	#define PGM_TYPE_NESTED_PAE 7
195	#define PGM_TYPE_NESTED_AMD64 8
196	#define PGM_TYPE_EPT 9
197	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
198	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
199	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
200	/** @} */
201
202	/** @name Defines used to indicate the second-level
203	* address translation (SLAT) modes in the templates.
204	* @{ */
205	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 1)
206	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 2)
207	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 3)
208	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 4)
209	/** @} */
210
211	/** Macro for checking if the guest is using paging.
212	* @param uGstType PGM_TYPE_*
213	* @param uShwType PGM_TYPE_*
214	* @remark ASSUMES certain order of the PGM_TYPE_* values.
215	*/
216	#define PGM_WITH_PAGING(uGstType, uShwType) \
217	( (uGstType) >= PGM_TYPE_32BIT \
218	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
219
220	/** Macro for checking if the guest supports the NX bit.
221	* @param uGstType PGM_TYPE_*
222	* @param uShwType PGM_TYPE_*
223	* @remark ASSUMES certain order of the PGM_TYPE_* values.
224	*/
225	#define PGM_WITH_NX(uGstType, uShwType) \
226	( (uGstType) >= PGM_TYPE_PAE \
227	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
228
229	/** Macro for checking for nested.
230	* @param uType PGM_TYPE_*
231	*/
232	#define PGM_TYPE_IS_NESTED(uType) \
233	( (uType) == PGM_TYPE_NESTED_32BIT \
234	\|\| (uType) == PGM_TYPE_NESTED_PAE \
235	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
236
237	/** Macro for checking for nested or EPT.
238	* @param uType PGM_TYPE_*
239	*/
240	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
241	( (uType) == PGM_TYPE_NESTED_32BIT \
242	\|\| (uType) == PGM_TYPE_NESTED_PAE \
243	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
244	\|\| (uType) == PGM_TYPE_EPT)
245
246
247
248	/** @def PGM_HCPHYS_2_PTR
249	* Maps a HC physical page pool address to a virtual address.
250	*
251	* @returns VBox status code.
252	* @param pVM The cross context VM structure.
253	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
254	* @param HCPhys The HC physical address to map to a virtual one.
255	* @param ppv Where to store the virtual address. No need to cast
256	* this.
257	*
258	* @remark There is no need to assert on the result.
259	*/
260	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
261
262	/** @def PGM_GCPHYS_2_PTR_V2
263	* Maps a GC physical page address to a virtual address.
264	*
265	* @returns VBox status code.
266	* @param pVM The cross context VM structure.
267	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
268	* @param GCPhys The GC physical address to map to a virtual one.
269	* @param ppv Where to store the virtual address. No need to cast this.
270	*
271	* @remark Use with care as we don't have so much dynamic mapping space in
272	* ring-0 on 32-bit darwin and in RC.
273	* @remark There is no need to assert on the result.
274	*/
275	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
276	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
277
278	/** @def PGM_GCPHYS_2_PTR
279	* Maps a GC physical page address to a virtual address.
280	*
281	* @returns VBox status code.
282	* @param pVM The cross context VM structure.
283	* @param GCPhys The GC physical address to map to a virtual one.
284	* @param ppv Where to store the virtual address. No need to cast this.
285	*
286	* @remark Use with care as we don't have so much dynamic mapping space in
287	* ring-0 on 32-bit darwin and in RC.
288	* @remark There is no need to assert on the result.
289	*/
290	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
291
292	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
293	* Maps a GC physical page address to a virtual address.
294	*
295	* @returns VBox status code.
296	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
297	* @param GCPhys The GC physical address to map to a virtual one.
298	* @param ppv Where to store the virtual address. No need to cast this.
299	*
300	* @remark Use with care as we don't have so much dynamic mapping space in
301	* ring-0 on 32-bit darwin and in RC.
302	* @remark There is no need to assert on the result.
303	*/
304	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
305
306	/** @def PGM_GCPHYS_2_PTR_EX
307	* Maps a unaligned GC physical page address to a virtual address.
308	*
309	* @returns VBox status code.
310	* @param pVM The cross context VM structure.
311	* @param GCPhys The GC physical address to map to a virtual one.
312	* @param ppv Where to store the virtual address. No need to cast this.
313	*
314	* @remark Use with care as we don't have so much dynamic mapping space in
315	* ring-0 on 32-bit darwin and in RC.
316	* @remark There is no need to assert on the result.
317	*/
318	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
319	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
320
321	/** @def PGM_DYNMAP_UNUSED_HINT
322	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
323	* is no longer used.
324	*
325	* For best effect only apply this to the page that was mapped most recently.
326	*
327	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
328	* @param pvPage The pool page.
329	*/
330	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
331
332	/** @def PGM_DYNMAP_UNUSED_HINT_VM
333	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
334	* is no longer used.
335	*
336	* For best effect only apply this to the page that was mapped most recently.
337	*
338	* @param pVM The cross context VM structure.
339	* @param pvPage The pool page.
340	*/
341	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
342
343
344	/** @def PGM_INVL_PG
345	* Invalidates a page.
346	*
347	* @param pVCpu The cross context virtual CPU structure.
348	* @param GCVirt The virtual address of the page to invalidate.
349	*/
350	#ifdef IN_RING0
351	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
352	#elif defined(IN_RING3)
353	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
354	#else
355	# error "Not IN_RING0 or IN_RING3!"
356	#endif
357
358	/** @def PGM_INVL_PG_ALL_VCPU
359	* Invalidates a page on all VCPUs
360	*
361	* @param pVM The cross context VM structure.
362	* @param GCVirt The virtual address of the page to invalidate.
363	*/
364	#ifdef IN_RING0
365	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
366	#else
367	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
368	#endif
369
370	/** @def PGM_INVL_BIG_PG
371	* Invalidates a 4MB page directory entry.
372	*
373	* @param pVCpu The cross context virtual CPU structure.
374	* @param GCVirt The virtual address within the page directory to invalidate.
375	*/
376	#ifdef IN_RING0
377	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
378	#else
379	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
380	#endif
381
382	/** @def PGM_INVL_VCPU_TLBS()
383	* Invalidates the TLBs of the specified VCPU
384	*
385	* @param pVCpu The cross context virtual CPU structure.
386	*/
387	#ifdef IN_RING0
388	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
389	#else
390	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
391	#endif
392
393	/** @def PGM_INVL_ALL_VCPU_TLBS()
394	* Invalidates the TLBs of all VCPUs
395	*
396	* @param pVM The cross context VM structure.
397	*/
398	#ifdef IN_RING0
399	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
400	#else
401	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
402	#endif
403
404
405	/** @name Safer Shadow PAE PT/PTE
406	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
407	* present.
408	*
409	* @{
410	*/
411	#if 1
412	/**
413	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
414	* invalid entries for present.
415	* @sa X86PTEPAE.
416	*/
417	typedef union PGMSHWPTEPAE
418	{
419	/** Unsigned integer view */
420	X86PGPAEUINT uCareful;
421	/* Not other views. */
422	} PGMSHWPTEPAE;
423
424	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
425	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
426	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
427	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
428	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
429	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
430	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
431	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
432	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
433	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
434	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
435	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
436	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
437	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
438	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
439	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
440
441	/**
442	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
443	* invalid entries for present.
444	* @sa X86PTPAE.
445	*/
446	typedef struct PGMSHWPTPAE
447	{
448	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
449	} PGMSHWPTPAE;
450
451	#else
452	typedef X86PTEPAE PGMSHWPTEPAE;
453	typedef X86PTPAE PGMSHWPTPAE;
454	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
455	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
456	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
457	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
458	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
459	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
460	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
461	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
462	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
463	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
464	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
465	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
466	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
467	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
468	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
469	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
470
471	#endif
472
473	/** Pointer to a shadow PAE PTE. */
474	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
475	/** Pointer to a const shadow PAE PTE. */
476	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
477
478	/** Pointer to a shadow PAE page table. */
479	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
480	/** Pointer to a const shadow PAE page table. */
481	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
482	/** @} */
483
484
485	/**
486	* Physical page access handler type registration.
487	*/
488	typedef struct PGMPHYSHANDLERTYPEINT
489	{
490	/** Number of references. */
491	uint32_t volatile cRefs;
492	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
493	uint32_t u32Magic;
494	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
495	RTLISTOFF32NODE ListNode;
496	/** The kind of accesses we're handling. */
497	PGMPHYSHANDLERKIND enmKind;
498	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
499	uint8_t uState;
500	/** Whether to keep the PGM lock when calling the handler.
501	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
502	bool fKeepPgmLock;
503	/** Set if this is registered by a device instance and uUser should be
504	* translated from a device instance ID to a pointer.
505	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
506	bool fRing0DevInsIdx;
507	bool afPadding[1];
508	/** Pointer to R3 callback function. */
509	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
510	/** Pointer to R0 callback function. */
511	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
512	/** Pointer to R0 callback function for \#PFs. */
513	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
514	/** Description / Name. For easing debugging. */
515	R3PTRTYPE(const char *) pszDesc;
516	} PGMPHYSHANDLERTYPEINT;
517	/** Pointer to a physical access handler type registration. */
518	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
519	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
520	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
521	/** Magic value for the physical handler callbacks. */
522	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
523
524	/**
525	* Converts a handle to a pointer.
526	* @returns PPGMPHYSHANDLERTYPEINT
527	* @param a_pVM The cross context VM structure.
528	* @param a_hType Physical access handler type handle.
529	*/
530	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
531
532
533	/**
534	* Physical page access handler structure.
535	*
536	* This is used to keep track of physical address ranges
537	* which are being monitored in some kind of way.
538	*/
539	typedef struct PGMPHYSHANDLER
540	{
541	AVLROGCPHYSNODECORE Core;
542	/** Number of pages to update. */
543	uint32_t cPages;
544	/** Set if we have pages that have been aliased. */
545	uint32_t cAliasedPages;
546	/** Set if we have pages that have temporarily been disabled. */
547	uint32_t cTmpOffPages;
548	/** Registered handler type handle (heap offset). */
549	PGMPHYSHANDLERTYPE hType;
550	/** User argument for the handlers. */
551	uint64_t uUser;
552	/** Description / Name. For easing debugging. */
553	R3PTRTYPE(const char *) pszDesc;
554	#ifdef VBOX_WITH_STATISTICS
555	/** Profiling of this handler. */
556	STAMPROFILE Stat;
557	#endif
558	} PGMPHYSHANDLER;
559	/** Pointer to a physical page access handler structure. */
560	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
561
562	/**
563	* Gets the type record for a physical handler (no reference added).
564	* @returns PPGMPHYSHANDLERTYPEINT
565	* @param a_pVM The cross context VM structure.
566	* @param a_pPhysHandler Pointer to the physical handler structure
567	* (PGMPHYSHANDLER).
568	*/
569	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
570
571
572	/**
573	* A Physical Guest Page tracking structure.
574	*
575	* The format of this structure is complicated because we have to fit a lot
576	* of information into as few bits as possible. The format is also subject
577	* to change (there is one coming up soon). Which means that for we'll be
578	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
579	* accesses to the structure.
580	*/
581	typedef union PGMPAGE
582	{
583	/** Structured view. */
584	struct
585	{
586	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
587	uint64_t u2HandlerPhysStateY : 2;
588	/** 3:2 - Paging structure needed to map the page
589	* (PGM_PAGE_PDE_TYPE_). /
590	uint64_t u2PDETypeY : 2;
591	/** 4 - Unused (was used by FTE for dirty tracking). */
592	uint64_t fUnused1 : 1;
593	/** 5 - Flag indicating that a write monitored page was written to
594	* when set. */
595	uint64_t fWrittenToY : 1;
596	/** 7:6 - Unused. */
597	uint64_t u2Unused0 : 2;
598	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
599	uint64_t u2Unused1 : 2;
600	/** 11:10 - NEM state bits. */
601	uint64_t u2NemStateY : 2;
602	/** 12:48 - The host physical frame number (shift left to get the
603	* address). */
604	uint64_t HCPhysFN : 36;
605	/** 50:48 - The page state. */
606	uint64_t uStateY : 3;
607	/** 51:53 - The page type (PGMPAGETYPE). */
608	uint64_t uTypeY : 3;
609	/** 63:54 - PTE index for usage tracking (page pool). */
610	uint64_t u10PteIdx : 10;
611
612	/** The GMM page ID.
613	* @remarks In the current implementation, MMIO2 and pages aliased to
614	* MMIO2 pages will be exploiting this field to calculate the
615	* ring-3 mapping address corresponding to the page.
616	* Later we may consider including MMIO2 management into GMM. */
617	uint32_t idPage;
618	/** Usage tracking (page pool). */
619	uint16_t u16TrackingY;
620	/** The number of read locks on this page. */
621	uint8_t cReadLocksY;
622	/** The number of write locks on this page. */
623	uint8_t cWriteLocksY;
624	} s;
625
626	/** 64-bit integer view. */
627	uint64_t au64[2];
628	/** 16-bit view. */
629	uint32_t au32[4];
630	/** 16-bit view. */
631	uint16_t au16[8];
632	/** 8-bit view. */
633	uint8_t au8[16];
634	} PGMPAGE;
635	AssertCompileSize(PGMPAGE, 16);
636	/** Pointer to a physical guest page. */
637	typedef PGMPAGE *PPGMPAGE;
638	/** Pointer to a const physical guest page. */
639	typedef const PGMPAGE *PCPGMPAGE;
640	/** Pointer to a physical guest page pointer. */
641	typedef PPGMPAGE *PPPGMPAGE;
642
643
644	/**
645	* Clears the page structure.
646	* @param a_pPage Pointer to the physical guest page tracking structure.
647	*/
648	#define PGM_PAGE_CLEAR(a_pPage) \
649	do { \
650	(a_pPage)->au64[0] = 0; \
651	(a_pPage)->au64[1] = 0; \
652	} while (0)
653
654	/**
655	* Initializes the page structure.
656	* @param a_pPage Pointer to the physical guest page tracking structure.
657	* @param a_HCPhys The host physical address of the page.
658	* @param a_idPage The (GMM) page ID of the page.
659	* @param a_uType The page type (PGMPAGETYPE).
660	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
661	*/
662	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
663	do { \
664	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
665	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
666	(a_pPage)->au64[0] = SetHCPhysTmp; \
667	(a_pPage)->au64[1] = 0; \
668	(a_pPage)->s.idPage = (a_idPage); \
669	(a_pPage)->s.uStateY = (a_uState); \
670	(a_pPage)->s.uTypeY = (a_uType); \
671	} while (0)
672
673	/**
674	* Initializes the page structure of a ZERO page.
675	* @param a_pPage Pointer to the physical guest page tracking structure.
676	* @param a_pVM The VM handle (for getting the zero page address).
677	* @param a_uType The page type (PGMPAGETYPE).
678	*/
679	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
680	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
681
682
683	/** @name The Page state, PGMPAGE::uStateY.
684	* @{ */
685	/** The zero page.
686	* This is a per-VM page that's never ever mapped writable. */
687	#define PGM_PAGE_STATE_ZERO 0U
688	/** A allocated page.
689	* This is a per-VM page allocated from the page pool (or wherever
690	* we get MMIO2 pages from if the type is MMIO2).
691	*/
692	#define PGM_PAGE_STATE_ALLOCATED 1U
693	/** A allocated page that's being monitored for writes.
694	* The shadow page table mappings are read-only. When a write occurs, the
695	* fWrittenTo member is set, the page remapped as read-write and the state
696	* moved back to allocated. */
697	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
698	/** The page is shared, aka. copy-on-write.
699	* This is a page that's shared with other VMs. */
700	#define PGM_PAGE_STATE_SHARED 3U
701	/** The page is ballooned, so no longer available for this VM. */
702	#define PGM_PAGE_STATE_BALLOONED 4U
703	/** @} */
704
705
706	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
707	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
708	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
709	#else
710	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
711	#endif
712
713	/**
714	* Gets the page state.
715	* @returns page state (PGM_PAGE_STATE_*).
716	* @param a_pPage Pointer to the physical guest page tracking structure.
717	*
718	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
719	* builds.
720	*/
721	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
722	#if defined(__GNUC__) && defined(VBOX_STRICT)
723	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
724	#else
725	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
726	#endif
727
728	/**
729	* Sets the page state.
730	* @param a_pVM The VM handle, only used for lock ownership assertions.
731	* @param a_pPage Pointer to the physical guest page tracking structure.
732	* @param a_uState The new page state.
733	*/
734	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
735	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
736
737
738	/**
739	* Gets the host physical address of the guest page.
740	* @returns host physical address (RTHCPHYS).
741	* @param a_pPage Pointer to the physical guest page tracking structure.
742	*
743	* @remarks In strict builds on gcc platforms, this macro will make some ugly
744	* assumption about a valid pVM variable/parameter being in the
745	* current context. It will use this pVM variable to assert that the
746	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
747	* pVM is not around.
748	*/
749	#if 0
750	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
751	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
752	#else
753	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
754	# if defined(__GNUC__) && defined(VBOX_STRICT)
755	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
756	# else
757	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
758	# endif
759	#endif
760
761	/**
762	* Sets the host physical address of the guest page.
763	*
764	* @param a_pVM The VM handle, only used for lock ownership assertions.
765	* @param a_pPage Pointer to the physical guest page tracking structure.
766	* @param a_HCPhys The new host physical address.
767	*/
768	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
769	do { \
770	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
771	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
772	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
773	PGM_PAGE_ASSERT_LOCK(a_pVM); \
774	} while (0)
775
776	/**
777	* Get the Page ID.
778	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
779	* @param a_pPage Pointer to the physical guest page tracking structure.
780	*/
781	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
782
783	/**
784	* Sets the Page ID.
785	* @param a_pVM The VM handle, only used for lock ownership assertions.
786	* @param a_pPage Pointer to the physical guest page tracking structure.
787	* @param a_idPage The new page ID.
788	*/
789	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
790	do { \
791	(a_pPage)->s.idPage = (a_idPage); \
792	PGM_PAGE_ASSERT_LOCK(a_pVM); \
793	} while (0)
794
795	/**
796	* Get the Chunk ID.
797	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
798	* @param a_pPage Pointer to the physical guest page tracking structure.
799	*/
800	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
801
802	/**
803	* Get the index of the page within the allocation chunk.
804	* @returns The page index.
805	* @param a_pPage Pointer to the physical guest page tracking structure.
806	*/
807	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
808
809	/**
810	* Gets the page type.
811	* @returns The page type.
812	* @param a_pPage Pointer to the physical guest page tracking structure.
813	*
814	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
815	* builds.
816	*/
817	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
818	#if defined(__GNUC__) && defined(VBOX_STRICT)
819	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
820	#else
821	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
822	#endif
823
824	/**
825	* Sets the page type.
826	*
827	* @param a_pVM The VM handle, only used for lock ownership assertions.
828	* @param a_pPage Pointer to the physical guest page tracking structure.
829	* @param a_enmType The new page type (PGMPAGETYPE).
830	*/
831	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
832	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
833
834	/**
835	* Gets the page table index
836	* @returns The page table index.
837	* @param a_pPage Pointer to the physical guest page tracking structure.
838	*/
839	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
840
841	/**
842	* Sets the page table index.
843	* @param a_pVM The VM handle, only used for lock ownership assertions.
844	* @param a_pPage Pointer to the physical guest page tracking structure.
845	* @param a_iPte New page table index.
846	*/
847	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
848	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
849
850	/**
851	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
852	* @returns true/false.
853	* @param a_pPage Pointer to the physical guest page tracking structure.
854	*/
855	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
856
857	/**
858	* Checks if the page is marked for MMIO, including both aliases.
859	* @returns true/false.
860	* @param a_pPage Pointer to the physical guest page tracking structure.
861	*/
862	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
863	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
864	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
865	)
866
867	/**
868	* Checks if the page is marked for MMIO, including special aliases.
869	* @returns true/false.
870	* @param a_pPage Pointer to the physical guest page tracking structure.
871	*/
872	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
873	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
874
875	/**
876	* Checks if the page is a special aliased MMIO page.
877	* @returns true/false.
878	* @param a_pPage Pointer to the physical guest page tracking structure.
879	*/
880	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
881
882	/**
883	* Checks if the page is backed by the ZERO page.
884	* @returns true/false.
885	* @param a_pPage Pointer to the physical guest page tracking structure.
886	*/
887	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
888
889	/**
890	* Checks if the page is backed by a SHARED page.
891	* @returns true/false.
892	* @param a_pPage Pointer to the physical guest page tracking structure.
893	*/
894	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
895
896	/**
897	* Checks if the page is ballooned.
898	* @returns true/false.
899	* @param a_pPage Pointer to the physical guest page tracking structure.
900	*/
901	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
902
903	/**
904	* Checks if the page is allocated.
905	* @returns true/false.
906	* @param a_pPage Pointer to the physical guest page tracking structure.
907	*/
908	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
909
910	/**
911	* Marks the page as written to (for GMM change monitoring).
912	* @param a_pVM The VM handle, only used for lock ownership assertions.
913	* @param a_pPage Pointer to the physical guest page tracking structure.
914	*/
915	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
916	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
917
918	/**
919	* Clears the written-to indicator.
920	* @param a_pVM The VM handle, only used for lock ownership assertions.
921	* @param a_pPage Pointer to the physical guest page tracking structure.
922	*/
923	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
924	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
925
926	/**
927	* Checks if the page was marked as written-to.
928	* @returns true/false.
929	* @param a_pPage Pointer to the physical guest page tracking structure.
930	*/
931	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
932
933
934	/** @name PT usage values (PGMPAGE::u2PDEType).
935	*
936	* @{ */
937	/** Either as a PT or PDE. */
938	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
939	/** Must use a page table to map the range. */
940	#define PGM_PAGE_PDE_TYPE_PT 1
941	/** Can use a page directory entry to map the continuous range. */
942	#define PGM_PAGE_PDE_TYPE_PDE 2
943	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
944	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
945	/** @} */
946
947	/**
948	* Set the PDE type of the page
949	* @param a_pVM The VM handle, only used for lock ownership assertions.
950	* @param a_pPage Pointer to the physical guest page tracking structure.
951	* @param a_uType PGM_PAGE_PDE_TYPE_*.
952	*/
953	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
954	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
955
956	/**
957	* Checks if the page was marked being part of a large page
958	* @returns true/false.
959	* @param a_pPage Pointer to the physical guest page tracking structure.
960	*/
961	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
962
963	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
964	*
965	* @remarks The values are assigned in order of priority, so we can calculate
966	* the correct state for a page with different handlers installed.
967	* @{ */
968	/** No handler installed. */
969	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
970	/** Monitoring is temporarily disabled. */
971	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
972	/** Write access is monitored. */
973	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
974	/** All access is monitored. */
975	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
976	/** @} */
977
978	/**
979	* Gets the physical access handler state of a page.
980	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
981	* @param a_pPage Pointer to the physical guest page tracking structure.
982	*/
983	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
984
985	/**
986	* Sets the physical access handler state of a page.
987	* @param a_pPage Pointer to the physical guest page tracking structure.
988	* @param a_uState The new state value.
989	*/
990	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
991	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
992
993	/**
994	* Checks if the page has any physical access handlers, including temporarily disabled ones.
995	* @returns true/false
996	* @param a_pPage Pointer to the physical guest page tracking structure.
997	*/
998	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
999	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1000
1001	/**
1002	* Checks if the page has any active physical access handlers.
1003	* @returns true/false
1004	* @param a_pPage Pointer to the physical guest page tracking structure.
1005	*/
1006	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1007	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1008
1009	/**
1010	* Checks if the page has any access handlers, including temporarily disabled ones.
1011	* @returns true/false
1012	* @param a_pPage Pointer to the physical guest page tracking structure.
1013	*/
1014	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1015	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1016
1017	/**
1018	* Checks if the page has any active access handlers.
1019	* @returns true/false
1020	* @param a_pPage Pointer to the physical guest page tracking structure.
1021	*/
1022	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1023	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1024
1025	/**
1026	* Checks if the page has any active access handlers catching all accesses.
1027	* @returns true/false
1028	* @param a_pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1031	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1032
1033
1034	/** @def PGM_PAGE_GET_TRACKING
1035	* Gets the packed shadow page pool tracking data associated with a guest page.
1036	* @returns uint16_t containing the data.
1037	* @param a_pPage Pointer to the physical guest page tracking structure.
1038	*/
1039	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1040	#if defined(__GNUC__) && defined(VBOX_STRICT)
1041	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1042	#else
1043	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1044	#endif
1045
1046	/** @def PGM_PAGE_SET_TRACKING
1047	* Sets the packed shadow page pool tracking data associated with a guest page.
1048	* @param a_pVM The VM handle, only used for lock ownership assertions.
1049	* @param a_pPage Pointer to the physical guest page tracking structure.
1050	* @param a_u16TrackingData The tracking data to store.
1051	*/
1052	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1053	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1054
1055	/** @def PGM_PAGE_GET_TD_CREFS
1056	* Gets the @a cRefs tracking data member.
1057	* @returns cRefs.
1058	* @param a_pPage Pointer to the physical guest page tracking structure.
1059	*/
1060	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1061	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1062	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1063	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1064
1065	/** @def PGM_PAGE_GET_TD_IDX
1066	* Gets the @a idx tracking data member.
1067	* @returns idx.
1068	* @param a_pPage Pointer to the physical guest page tracking structure.
1069	*/
1070	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1071	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1072	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1073	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1074
1075
1076	/** Max number of locks on a page. */
1077	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1078
1079	/** Get the read lock count.
1080	* @returns count.
1081	* @param a_pPage Pointer to the physical guest page tracking structure.
1082	*/
1083	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1084
1085	/** Get the write lock count.
1086	* @returns count.
1087	* @param a_pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1090
1091	/** Decrement the read lock counter.
1092	* @param a_pPage Pointer to the physical guest page tracking structure.
1093	*/
1094	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1095
1096	/** Decrement the write lock counter.
1097	* @param a_pPage Pointer to the physical guest page tracking structure.
1098	*/
1099	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1100
1101	/** Increment the read lock counter.
1102	* @param a_pPage Pointer to the physical guest page tracking structure.
1103	*/
1104	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1105
1106	/** Increment the write lock counter.
1107	* @param a_pPage Pointer to the physical guest page tracking structure.
1108	*/
1109	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1110
1111
1112	/** Gets the NEM state.
1113	* @returns NEM state value (two bits).
1114	* @param a_pPage Pointer to the physical guest page tracking structure.
1115	*/
1116	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1117
1118	/** Sets the NEM state.
1119	* @param a_pPage Pointer to the physical guest page tracking structure.
1120	* @param a_u2State The NEM state value (specific to NEM impl.).
1121	*/
1122	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1123	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1124
1125
1126	#if 0
1127	/** Enables sanity checking of write monitoring using CRC-32. */
1128	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1129	#endif
1130
1131	/**
1132	* Per page live save tracking data.
1133	*/
1134	typedef struct PGMLIVESAVERAMPAGE
1135	{
1136	/** Number of times it has been dirtied. */
1137	uint32_t cDirtied : 24;
1138	/** Whether it is currently dirty. */
1139	uint32_t fDirty : 1;
1140	/** Ignore the page.
1141	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1142	* deal with these after pausing the VM and DevPCI have said it bit about
1143	* remappings. */
1144	uint32_t fIgnore : 1;
1145	/** Was a ZERO page last time around. */
1146	uint32_t fZero : 1;
1147	/** Was a SHARED page last time around. */
1148	uint32_t fShared : 1;
1149	/** Whether the page is/was write monitored in a previous pass. */
1150	uint32_t fWriteMonitored : 1;
1151	/** Whether the page is/was write monitored earlier in this pass. */
1152	uint32_t fWriteMonitoredJustNow : 1;
1153	/** Bits reserved for future use. */
1154	uint32_t u2Reserved : 2;
1155	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1156	/** CRC-32 for the page. This is for internal consistency checks. */
1157	uint32_t u32Crc;
1158	#endif
1159	} PGMLIVESAVERAMPAGE;
1160	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1161	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1162	#else
1163	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1164	#endif
1165	/** Pointer to the per page live save tracking data. */
1166	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1167
1168	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1169	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1170
1171
1172	/**
1173	* RAM range for GC Phys to HC Phys conversion.
1174	*
1175	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1176	* conversions too, but we'll let MM handle that for now.
1177	*
1178	* This structure is used by linked lists in both GC and HC.
1179	*/
1180	typedef struct PGMRAMRANGE
1181	{
1182	/** Start of the range. Page aligned. */
1183	RTGCPHYS GCPhys;
1184	/** Size of the range. (Page aligned of course). */
1185	RTGCPHYS cb;
1186	/** Pointer to the next RAM range - for R3. */
1187	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1188	/** Pointer to the next RAM range - for R0. */
1189	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1190	/** PGM_RAM_RANGE_FLAGS_* flags. */
1191	uint32_t fFlags;
1192	/** NEM specific info, UINT32_MAX if not used. */
1193	uint32_t uNemRange;
1194	/** Last address in the range (inclusive). Page aligned (-1). */
1195	RTGCPHYS GCPhysLast;
1196	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1197	R3PTRTYPE(void *) pvR3;
1198	/** Live save per page tracking data. */
1199	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1200	/** The range description. */
1201	R3PTRTYPE(const char *) pszDesc;
1202	/** Pointer to self - R0 pointer. */
1203	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1204
1205	/** Pointer to the left search three node - ring-3 context. */
1206	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1207	/** Pointer to the right search three node - ring-3 context. */
1208	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1209	/** Pointer to the left search three node - ring-0 context. */
1210	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1211	/** Pointer to the right search three node - ring-0 context. */
1212	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1213
1214	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1215	#if HC_ARCH_BITS == 32
1216	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1217	#endif
1218	/** Array of physical guest page tracking structures.
1219	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1220	PGMPAGE aPages[1];
1221	} PGMRAMRANGE;
1222	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1223	typedef PGMRAMRANGE *PPGMRAMRANGE;
1224
1225	/** @name PGMRAMRANGE::fFlags
1226	* @{ */
1227	/** The RAM range is floating around as an independent guest mapping. */
1228	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1229	/** Ad hoc RAM range for an ROM mapping. */
1230	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1231	/** Ad hoc RAM range for an MMIO mapping. */
1232	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1233	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1234	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1235	/** @} */
1236
1237	/** Tests if a RAM range is an ad hoc one or not.
1238	* @returns true/false.
1239	* @param pRam The RAM range.
1240	*/
1241	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1242	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1243
1244	/** The number of entries in the RAM range TLBs (there is one for each
1245	* context). Must be a power of two. */
1246	#define PGM_RAMRANGE_TLB_ENTRIES 8
1247
1248	/**
1249	* Calculates the RAM range TLB index for the physical address.
1250	*
1251	* @returns RAM range TLB index.
1252	* @param a_GCPhys The guest physical address.
1253	*/
1254	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1255
1256	/**
1257	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1258	* mapping address.
1259	*/
1260	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1261	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1262
1263
1264	/**
1265	* Per page tracking structure for ROM image.
1266	*
1267	* A ROM image may have a shadow page, in which case we may have two pages
1268	* backing it. This structure contains the PGMPAGE for both while
1269	* PGMRAMRANGE have a copy of the active one. It is important that these
1270	* aren't out of sync in any regard other than page pool tracking data.
1271	*/
1272	typedef struct PGMROMPAGE
1273	{
1274	/** The page structure for the virgin ROM page. */
1275	PGMPAGE Virgin;
1276	/** The page structure for the shadow RAM page. */
1277	PGMPAGE Shadow;
1278	/** The current protection setting. */
1279	PGMROMPROT enmProt;
1280	/** Live save status information. Makes use of unused alignment space. */
1281	struct
1282	{
1283	/** The previous protection value. */
1284	uint8_t u8Prot;
1285	/** Written to flag set by the handler. */
1286	bool fWrittenTo;
1287	/** Whether the shadow page is dirty or not. */
1288	bool fDirty;
1289	/** Whether it was dirtied in the recently. */
1290	bool fDirtiedRecently;
1291	} LiveSave;
1292	} PGMROMPAGE;
1293	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1294	/** Pointer to a ROM page tracking structure. */
1295	typedef PGMROMPAGE *PPGMROMPAGE;
1296
1297
1298	/**
1299	* A registered ROM image.
1300	*
1301	* This is needed to keep track of ROM image since they generally intrude
1302	* into a PGMRAMRANGE. It also keeps track of additional info like the
1303	* two page sets (read-only virgin and read-write shadow), the current
1304	* state of each page.
1305	*
1306	* Because access handlers cannot easily be executed in a different
1307	* context, the ROM ranges needs to be accessible and in all contexts.
1308	*/
1309	typedef struct PGMROMRANGE
1310	{
1311	/** Pointer to the next range - R3. */
1312	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1313	/** Pointer to the next range - R0. */
1314	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1315	/** Pointer to the this range - R0. */
1316	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1317	/** Address of the range. */
1318	RTGCPHYS GCPhys;
1319	/** Address of the last byte in the range. */
1320	RTGCPHYS GCPhysLast;
1321	/** Size of the range. */
1322	RTGCPHYS cb;
1323	/** The flags (PGMPHYS_ROM_FLAGS_). /
1324	uint8_t fFlags;
1325	/** The saved state range ID. */
1326	uint8_t idSavedState;
1327	/** Alignment padding. */
1328	uint8_t au8Alignment[2];
1329	/** The size bits pvOriginal points to. */
1330	uint32_t cbOriginal;
1331	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1332	* This is used for strictness checks. */
1333	R3PTRTYPE(const void *) pvOriginal;
1334	/** The ROM description. */
1335	R3PTRTYPE(const char *) pszDesc;
1336	#ifdef VBOX_WITH_PGM_NEM_MODE
1337	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1338	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1339	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1340	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1341	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1342	R3PTRTYPE(uint8_t *) pbR3Alternate;
1343	RTR3PTR pvAlignment2;
1344	#endif
1345	/** The per page tracking structures. */
1346	PGMROMPAGE aPages[1];
1347	} PGMROMRANGE;
1348	/** Pointer to a ROM range. */
1349	typedef PGMROMRANGE *PPGMROMRANGE;
1350
1351
1352	/**
1353	* Live save per page data for an MMIO2 page.
1354	*
1355	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1356	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1357	* CRC-32 for detecting changes as well as special handling of zero pages. This
1358	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1359	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1360	* because of speed (2.5x and 6x slower).)
1361	*
1362	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1363	* save but normally is disabled. Since we can write monitor guest
1364	* accesses on our own, we only need this for host accesses. Shouldn't be
1365	* too difficult for DevVGA, VMMDev might be doable, the planned
1366	* networking fun will be fun since it involves ring-0.
1367	*/
1368	typedef struct PGMLIVESAVEMMIO2PAGE
1369	{
1370	/** Set if the page is considered dirty. */
1371	bool fDirty;
1372	/** The number of scans this page has remained unchanged for.
1373	* Only updated for dirty pages. */
1374	uint8_t cUnchangedScans;
1375	/** Whether this page was zero at the last scan. */
1376	bool fZero;
1377	/** Alignment padding. */
1378	bool fReserved;
1379	/** CRC-32 for the first half of the page.
1380	* This is used together with u32CrcH2 to quickly detect changes in the page
1381	* during the non-final passes. */
1382	uint32_t u32CrcH1;
1383	/** CRC-32 for the second half of the page. */
1384	uint32_t u32CrcH2;
1385	/** SHA-1 for the saved page.
1386	* This is used in the final pass to skip pages without changes. */
1387	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1388	} PGMLIVESAVEMMIO2PAGE;
1389	/** Pointer to a live save status data for an MMIO2 page. */
1390	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1391
1392	/**
1393	* A registered MMIO2 (= Device RAM) range.
1394	*
1395	* There are a few reason why we need to keep track of these registrations. One
1396	* of them is the deregistration & cleanup stuff, while another is that the
1397	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1398	* range list.
1399	*
1400	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1401	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1402	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1403	* overlap we will free all the existing RAM pages and put in the ram range
1404	* pages instead.
1405	*/
1406	typedef struct PGMREGMMIO2RANGE
1407	{
1408	/** The owner of the range. (a device) */
1409	PPDMDEVINSR3 pDevInsR3;
1410	/** Pointer to the ring-3 mapping of the allocation. */
1411	RTR3PTR pvR3;
1412	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1413	/** Pointer to the ring-0 mapping of the allocation. */
1414	RTR0PTR pvR0;
1415	#endif
1416	/** Pointer to the next range - R3. */
1417	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1418	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1419	uint16_t fFlags;
1420	/** The sub device number (internal PCI config (CFGM) number). */
1421	uint8_t iSubDev;
1422	/** The PCI region number. */
1423	uint8_t iRegion;
1424	/** The saved state range ID. */
1425	uint8_t idSavedState;
1426	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1427	uint8_t idMmio2;
1428	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1429	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1430	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1431	#else
1432	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1433	#endif
1434	/** The real size.
1435	* This may be larger than indicated by RamRange.cb if the range has been
1436	* reduced during saved state loading. */
1437	RTGCPHYS cbReal;
1438	/** Pointer to the physical handler for MMIO.
1439	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1440	* will be NULL. */
1441	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1442	/** Live save per page tracking data for MMIO2. */
1443	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1444	/** The associated RAM range. */
1445	PGMRAMRANGE RamRange;
1446	} PGMREGMMIO2RANGE;
1447	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1448	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1449	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1450
1451	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1452	* @{ */
1453	/** Set if this is the first chunk in the MMIO2 range. */
1454	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1455	/** Set if this is the last chunk in the MMIO2 range. */
1456	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1457	/** Set if the whole range is mapped. */
1458	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1459	/** Set if it's overlapping, clear if not. */
1460	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1461	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1462	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1463	/** Set if the access handler is registered. */
1464	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1465	/** Set if dirty page tracking is currently enabled. */
1466	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1467	/** Set if there are dirty pages in the range. */
1468	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1469	/** @} */
1470
1471
1472	/** @name Internal MMIO2 constants.
1473	* @{ */
1474	/** The maximum number of MMIO2 ranges. */
1475	#define PGM_MMIO2_MAX_RANGES 32
1476	/** The maximum number of pages in a MMIO2 range. */
1477	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1478	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1479	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1480	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1481	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1482	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1483	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1484	/** @} */
1485
1486
1487
1488	/**
1489	* PGMPhysRead/Write cache entry
1490	*/
1491	typedef struct PGMPHYSCACHEENTRY
1492	{
1493	/** R3 pointer to physical page. */
1494	R3PTRTYPE(uint8_t *) pbR3;
1495	/** GC Physical address for cache entry */
1496	RTGCPHYS GCPhys;
1497	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1498	RTGCPHYS u32Padding0; /*< alignment padding. /
1499	#endif
1500	} PGMPHYSCACHEENTRY;
1501
1502	/**
1503	* PGMPhysRead/Write cache to reduce REM memory access overhead
1504	*/
1505	typedef struct PGMPHYSCACHE
1506	{
1507	/** Bitmap of valid cache entries */
1508	uint64_t aEntries;
1509	/** Cache entries */
1510	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1511	} PGMPHYSCACHE;
1512
1513
1514	/** @name Ring-3 page mapping TLBs
1515	* @{ */
1516
1517	/** Pointer to an allocation chunk ring-3 mapping. */
1518	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1519	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1520	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1521
1522	/**
1523	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1524	*
1525	* The primary tree (Core) uses the chunk id as key.
1526	*/
1527	typedef struct PGMCHUNKR3MAP
1528	{
1529	/** The key is the chunk id. */
1530	AVLU32NODECORE Core;
1531	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1532	* selection. */
1533	uint32_t iLastUsed;
1534	/** The current reference count. */
1535	uint32_t volatile cRefs;
1536	/** The current permanent reference count. */
1537	uint32_t volatile cPermRefs;
1538	/** The mapping address. */
1539	void *pv;
1540	} PGMCHUNKR3MAP;
1541
1542	/**
1543	* Allocation chunk ring-3 mapping TLB entry.
1544	*/
1545	typedef struct PGMCHUNKR3MAPTLBE
1546	{
1547	/** The chunk id. */
1548	uint32_t volatile idChunk;
1549	#if HC_ARCH_BITS == 64
1550	uint32_t u32Padding; /*< alignment padding. /
1551	#endif
1552	/** The chunk map. */
1553	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1554	} PGMCHUNKR3MAPTLBE;
1555	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1556	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1557
1558	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1559	* @remark Must be a power of two value. */
1560	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1561
1562	/**
1563	* Allocation chunk ring-3 mapping TLB.
1564	*
1565	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1566	* At first glance this might look kinda odd since AVL trees are
1567	* supposed to give the most optimal lookup times of all trees
1568	* due to their balancing. However, take a tree with 1023 nodes
1569	* in it, that's 10 levels, meaning that most searches has to go
1570	* down 9 levels before they find what they want. This isn't fast
1571	* compared to a TLB hit. There is the factor of cache misses,
1572	* and of course the problem with trees and branch prediction.
1573	* This is why we use TLBs in front of most of the trees.
1574	*
1575	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1576	* difficult when we switch to the new inlined AVL trees (from kStuff).
1577	*/
1578	typedef struct PGMCHUNKR3MAPTLB
1579	{
1580	/** The TLB entries. */
1581	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1582	} PGMCHUNKR3MAPTLB;
1583
1584	/**
1585	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1586	* @returns Chunk TLB index.
1587	* @param idChunk The Chunk ID.
1588	*/
1589	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1590
1591
1592	/**
1593	* Ring-3 guest page mapping TLB entry.
1594	* @remarks used in ring-0 as well at the moment.
1595	*/
1596	typedef struct PGMPAGER3MAPTLBE
1597	{
1598	/** Address of the page. */
1599	RTGCPHYS volatile GCPhys;
1600	/** The guest page. */
1601	R3PTRTYPE(PPGMPAGE) volatile pPage;
1602	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1603	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1604	/** The address */
1605	R3PTRTYPE(void *) volatile pv;
1606	#if HC_ARCH_BITS == 32
1607	uint32_t u32Padding; /*< alignment padding. /
1608	#endif
1609	} PGMPAGER3MAPTLBE;
1610	/** Pointer to an entry in the HC physical TLB. */
1611	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1612
1613
1614	/** The number of entries in the ring-3 guest page mapping TLB.
1615	* @remarks The value must be a power of two. */
1616	#define PGM_PAGER3MAPTLB_ENTRIES 256
1617
1618	/**
1619	* Ring-3 guest page mapping TLB.
1620	* @remarks used in ring-0 as well at the moment.
1621	*/
1622	typedef struct PGMPAGER3MAPTLB
1623	{
1624	/** The TLB entries. */
1625	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1626	} PGMPAGER3MAPTLB;
1627	/** Pointer to the ring-3 guest page mapping TLB. */
1628	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1629
1630	/**
1631	* Calculates the index of the TLB entry for the specified guest page.
1632	* @returns Physical TLB index.
1633	* @param GCPhys The guest physical address.
1634	*/
1635	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1636
1637	/** @} */
1638
1639
1640	/** @name Ring-0 page mapping TLB
1641	* @{ */
1642	/**
1643	* Ring-0 guest page mapping TLB entry.
1644	*/
1645	typedef struct PGMPAGER0MAPTLBE
1646	{
1647	/** Address of the page. */
1648	RTGCPHYS volatile GCPhys;
1649	/** The guest page. */
1650	R0PTRTYPE(PPGMPAGE) volatile pPage;
1651	/** The address */
1652	R0PTRTYPE(void *) volatile pv;
1653	} PGMPAGER0MAPTLBE;
1654	/** Pointer to an entry in the HC physical TLB. */
1655	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1656
1657
1658	/** The number of entries in the ring-3 guest page mapping TLB.
1659	* @remarks The value must be a power of two. */
1660	#define PGM_PAGER0MAPTLB_ENTRIES 256
1661
1662	/**
1663	* Ring-3 guest page mapping TLB.
1664	* @remarks used in ring-0 as well at the moment.
1665	*/
1666	typedef struct PGMPAGER0MAPTLB
1667	{
1668	/** The TLB entries. */
1669	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1670	} PGMPAGER0MAPTLB;
1671	/** Pointer to the ring-3 guest page mapping TLB. */
1672	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1673
1674	/**
1675	* Calculates the index of the TLB entry for the specified guest page.
1676	* @returns Physical TLB index.
1677	* @param GCPhys The guest physical address.
1678	*/
1679	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1680	/** @} */
1681
1682
1683	/** @name Context neutral page mapper TLB.
1684	*
1685	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1686	* code is writting in a kind of context neutral way. Time will show whether
1687	* this actually makes sense or not...
1688	*
1689	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1690	* context ends up using a global mapping cache on some platforms
1691	* (darwin).
1692	*
1693	* @{ */
1694	/** @typedef PPGMPAGEMAPTLB
1695	* The page mapper TLB pointer type for the current context. */
1696	/** @typedef PPGMPAGEMAPTLB
1697	* The page mapper TLB entry pointer type for the current context. */
1698	/** @typedef PPGMPAGEMAPTLB
1699	* The page mapper TLB entry pointer pointer type for the current context. */
1700	/** @def PGM_PAGEMAPTLB_ENTRIES
1701	* The number of TLB entries in the page mapper TLB for the current context. */
1702	/** @def PGM_PAGEMAPTLB_IDX
1703	* Calculate the TLB index for a guest physical address.
1704	* @returns The TLB index.
1705	* @param GCPhys The guest physical address. */
1706	/** @typedef PPGMPAGEMAP
1707	* Pointer to a page mapper unit for current context. */
1708	/** @typedef PPPGMPAGEMAP
1709	* Pointer to a page mapper unit pointer for current context. */
1710	#if defined(IN_RING0)
1711	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1712	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1713	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1714	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1715	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1716	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1717	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1718	#else
1719	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1720	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1721	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1722	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1723	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1724	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1725	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1726	#endif
1727	/** @} */
1728
1729
1730	/** @name PGM Pool Indexes.
1731	* Aka. the unique shadow page identifier.
1732	* @{ */
1733	/** NIL page pool IDX. */
1734	#define NIL_PGMPOOL_IDX 0
1735	/** The first normal index. There used to be 5 fictive pages up front, now
1736	* there is only the NIL page. */
1737	#define PGMPOOL_IDX_FIRST 1
1738	/** The last valid index. (inclusive, 14 bits) */
1739	#define PGMPOOL_IDX_LAST 0x3fff
1740	/** @} */
1741
1742	/** The NIL index for the parent chain. */
1743	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1744	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1745
1746	/**
1747	* Node in the chain linking a shadowed page to it's parent (user).
1748	*/
1749	#pragma pack(1)
1750	typedef struct PGMPOOLUSER
1751	{
1752	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1753	uint16_t iNext;
1754	/** The user page index. */
1755	uint16_t iUser;
1756	/** Index into the user table. */
1757	uint32_t iUserTable;
1758	} PGMPOOLUSER, *PPGMPOOLUSER;
1759	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1760	#pragma pack()
1761
1762
1763	/** The NIL index for the phys ext chain. */
1764	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1765	/** The NIL pte index for a phys ext chain slot. */
1766	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1767
1768	/**
1769	* Node in the chain of physical cross reference extents.
1770	* @todo Calling this an 'extent' is not quite right, find a better name.
1771	* @todo find out the optimal size of the aidx array
1772	*/
1773	#pragma pack(1)
1774	typedef struct PGMPOOLPHYSEXT
1775	{
1776	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1777	uint16_t iNext;
1778	/** Alignment. */
1779	uint16_t u16Align;
1780	/** The user page index. */
1781	uint16_t aidx[3];
1782	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1783	uint16_t apte[3];
1784	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1785	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1786	#pragma pack()
1787
1788
1789	/**
1790	* The kind of page that's being shadowed.
1791	*/
1792	typedef enum PGMPOOLKIND
1793	{
1794	/** The virtual invalid 0 entry. */
1795	PGMPOOLKIND_INVALID = 0,
1796	/** The entry is free (=unused). */
1797	PGMPOOLKIND_FREE,
1798
1799	/** Shw: 32-bit page table; Gst: no paging. */
1800	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1801	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1802	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1803	/** Shw: 32-bit page table; Gst: 4MB page. */
1804	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1805	/** Shw: PAE page table; Gst: no paging. */
1806	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1807	/** Shw: PAE page table; Gst: 32-bit page table. */
1808	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1809	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1810	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1811	/** Shw: PAE page table; Gst: PAE page table. */
1812	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1813	/** Shw: PAE page table; Gst: 2MB page. */
1814	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1815
1816	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1817	PGMPOOLKIND_32BIT_PD,
1818	/** Shw: 32-bit page directory. Gst: no paging. */
1819	PGMPOOLKIND_32BIT_PD_PHYS,
1820	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1821	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1822	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1823	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1824	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1825	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1826	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1827	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1828	/** Shw: PAE page directory; Gst: PAE page directory. */
1829	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1830	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1831	PGMPOOLKIND_PAE_PD_PHYS,
1832
1833	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1834	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1835	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1836	PGMPOOLKIND_PAE_PDPT,
1837	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1838	PGMPOOLKIND_PAE_PDPT_PHYS,
1839
1840	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1841	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1842	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1843	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1844	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1845	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1846	/** Shw: 64-bit page directory table; Gst: no paging. */
1847	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1848
1849	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1850	PGMPOOLKIND_64BIT_PML4,
1851
1852	/** Shw: EPT page directory pointer table; Gst: no paging. */
1853	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1854	/** Shw: EPT page directory table; Gst: no paging. */
1855	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1856	/** Shw: EPT page table; Gst: no paging. */
1857	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1858
1859	/** Shw: Root Nested paging table. */
1860	PGMPOOLKIND_ROOT_NESTED,
1861
1862	/** The last valid entry. */
1863	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1864	} PGMPOOLKIND;
1865
1866	/**
1867	* The access attributes of the page; only applies to big pages.
1868	*/
1869	typedef enum
1870	{
1871	PGMPOOLACCESS_DONTCARE = 0,
1872	PGMPOOLACCESS_USER_RW,
1873	PGMPOOLACCESS_USER_R,
1874	PGMPOOLACCESS_USER_RW_NX,
1875	PGMPOOLACCESS_USER_R_NX,
1876	PGMPOOLACCESS_SUPERVISOR_RW,
1877	PGMPOOLACCESS_SUPERVISOR_R,
1878	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1879	PGMPOOLACCESS_SUPERVISOR_R_NX
1880	} PGMPOOLACCESS;
1881
1882	/**
1883	* The tracking data for a page in the pool.
1884	*/
1885	typedef struct PGMPOOLPAGE
1886	{
1887	/** AVL node code with the (HC) physical address of this page. */
1888	AVLOHCPHYSNODECORE Core;
1889	/** Pointer to the R3 mapping of the page. */
1890	R3PTRTYPE(void *) pvPageR3;
1891	/** Pointer to the R0 mapping of the page. */
1892	R0PTRTYPE(void *) pvPageR0;
1893	/** The guest physical address. */
1894	RTGCPHYS GCPhys;
1895	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1896	uint8_t enmKind;
1897	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1898	uint8_t enmAccess;
1899	/** This supplements enmKind and enmAccess */
1900	bool fA20Enabled : 1;
1901
1902	/** Used to indicate that the page is zeroed. */
1903	bool fZeroed : 1;
1904	/** Used to indicate that a PT has non-global entries. */
1905	bool fSeenNonGlobal : 1;
1906	/** Used to indicate that we're monitoring writes to the guest page. */
1907	bool fMonitored : 1;
1908	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1909	* (All pages are in the age list.) */
1910	bool fCached : 1;
1911	/** This is used by the R3 access handlers when invoked by an async thread.
1912	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1913	bool volatile fReusedFlushPending : 1;
1914	/** Used to mark the page as dirty (write monitoring is temporarily
1915	* off). */
1916	bool fDirty : 1;
1917	bool fPadding1 : 1;
1918	bool fPadding2;
1919
1920	/** The index of this page. */
1921	uint16_t idx;
1922	/** The next entry in the list this page currently resides in.
1923	* It's either in the free list or in the GCPhys hash. */
1924	uint16_t iNext;
1925	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1926	uint16_t iUserHead;
1927	/** The number of present entries. */
1928	uint16_t cPresent;
1929	/** The first entry in the table which is present. */
1930	uint16_t iFirstPresent;
1931	/** The number of modifications to the monitored page. */
1932	uint16_t cModifications;
1933	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1934	uint16_t iModifiedNext;
1935	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1936	uint16_t iModifiedPrev;
1937	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1938	uint16_t iMonitoredNext;
1939	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1940	uint16_t iMonitoredPrev;
1941	/** The next page in the age list. */
1942	uint16_t iAgeNext;
1943	/** The previous page in the age list. */
1944	uint16_t iAgePrev;
1945	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
1946	uint8_t idxDirtyEntry;
1947
1948	/** @name Access handler statistics to determine whether the guest is
1949	* (re)initializing a page table.
1950	* @{ */
1951	RTGCPTR GCPtrLastAccessHandlerRip;
1952	RTGCPTR GCPtrLastAccessHandlerFault;
1953	uint64_t cLastAccessHandler;
1954	/** @} */
1955	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
1956	uint32_t volatile cLocked;
1957	#if GC_ARCH_BITS == 64
1958	uint32_t u32Alignment3;
1959	#endif
1960	# ifdef VBOX_STRICT
1961	RTGCPTR GCPtrDirtyFault;
1962	# endif
1963	} PGMPOOLPAGE;
1964	/** Pointer to a pool page. */
1965	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
1966	/** Pointer to a const pool page. */
1967	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
1968	/** Pointer to a pool page pointer. */
1969	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
1970
1971
1972	/** The hash table size. */
1973	# define PGMPOOL_HASH_SIZE 0x40
1974	/** The hash function. */
1975	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1976
1977
1978	/**
1979	* The shadow page pool instance data.
1980	*
1981	* It's all one big allocation made at init time, except for the
1982	* pages that is. The user nodes follows immediately after the
1983	* page structures.
1984	*/
1985	typedef struct PGMPOOL
1986	{
1987	/** The VM handle - R3 Ptr. */
1988	PVMR3 pVMR3;
1989	/** The VM handle - R0 Ptr. */
1990	R0PTRTYPE(PVMCC) pVMR0;
1991	/** The ring-3 pointer to this structure. */
1992	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
1993	/** The ring-0 pointer to this structure. */
1994	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
1995	/** The max pool size. This includes the special IDs. */
1996	uint16_t cMaxPages;
1997	/** The current pool size. */
1998	uint16_t cCurPages;
1999	/** The head of the free page list. */
2000	uint16_t iFreeHead;
2001	/* Padding. */
2002	uint16_t u16Padding;
2003	/** Head of the chain of free user nodes. */
2004	uint16_t iUserFreeHead;
2005	/** The number of user nodes we've allocated. */
2006	uint16_t cMaxUsers;
2007	/** The number of present page table entries in the entire pool. */
2008	uint32_t cPresent;
2009	/** Pointer to the array of user nodes - R3 pointer. */
2010	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2011	/** Pointer to the array of user nodes - R0 pointer. */
2012	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2013	/** Head of the chain of free phys ext nodes. */
2014	uint16_t iPhysExtFreeHead;
2015	/** The number of user nodes we've allocated. */
2016	uint16_t cMaxPhysExts;
2017	uint32_t u32Padding0b;
2018	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2019	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2020	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2021	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2022	/** Hash table for GCPhys addresses. */
2023	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2024	/** The head of the age list. */
2025	uint16_t iAgeHead;
2026	/** The tail of the age list. */
2027	uint16_t iAgeTail;
2028	/** Set if the cache is enabled. */
2029	bool fCacheEnabled;
2030	/** Alignment padding. */
2031	bool afPadding1[3];
2032	/** Head of the list of modified pages. */
2033	uint16_t iModifiedHead;
2034	/** The current number of modified pages. */
2035	uint16_t cModifiedPages;
2036	/** Physical access handler type registration handle. */
2037	PGMPHYSHANDLERTYPE hAccessHandlerType;
2038	/** Next available slot (in aDirtyPages). */
2039	uint32_t idxFreeDirtyPage;
2040	/** Number of active dirty pages. */
2041	uint32_t cDirtyPages;
2042	/** Array of current dirty pgm pool page indices. */
2043	uint16_t aidxDirtyPages[16];
2044	/** Array running in parallel to aidxDirtyPages with the page data. */
2045	struct
2046	{
2047	uint64_t aPage[512];
2048	} aDirtyPages[16];
2049
2050	/** The number of pages currently in use. */
2051	uint16_t cUsedPages;
2052	#ifdef VBOX_WITH_STATISTICS
2053	/** The high water mark for cUsedPages. */
2054	uint16_t cUsedPagesHigh;
2055	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2056	/** Profiling pgmPoolAlloc(). */
2057	STAMPROFILEADV StatAlloc;
2058	/** Profiling pgmR3PoolClearDoIt(). */
2059	STAMPROFILE StatClearAll;
2060	/** Profiling pgmR3PoolReset(). */
2061	STAMPROFILE StatR3Reset;
2062	/** Profiling pgmPoolFlushPage(). */
2063	STAMPROFILE StatFlushPage;
2064	/** Profiling pgmPoolFree(). */
2065	STAMPROFILE StatFree;
2066	/** Counting explicit flushes by PGMPoolFlushPage(). */
2067	STAMCOUNTER StatForceFlushPage;
2068	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2069	STAMCOUNTER StatForceFlushDirtyPage;
2070	/** Counting flushes for reused pages. */
2071	STAMCOUNTER StatForceFlushReused;
2072	/** Profiling time spent zeroing pages. */
2073	STAMPROFILE StatZeroPage;
2074	/** Profiling of pgmPoolTrackDeref. */
2075	STAMPROFILE StatTrackDeref;
2076	/** Profiling pgmTrackFlushGCPhysPT. */
2077	STAMPROFILE StatTrackFlushGCPhysPT;
2078	/** Profiling pgmTrackFlushGCPhysPTs. */
2079	STAMPROFILE StatTrackFlushGCPhysPTs;
2080	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2081	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2082	/** Number of times we've been out of user records. */
2083	STAMCOUNTER StatTrackFreeUpOneUser;
2084	/** Nr of flushed entries. */
2085	STAMCOUNTER StatTrackFlushEntry;
2086	/** Nr of updated entries. */
2087	STAMCOUNTER StatTrackFlushEntryKeep;
2088	/** Profiling deref activity related tracking GC physical pages. */
2089	STAMPROFILE StatTrackDerefGCPhys;
2090	/** Number of linear searches for a HCPhys in the ram ranges. */
2091	STAMCOUNTER StatTrackLinearRamSearches;
2092	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2093	STAMCOUNTER StamTrackPhysExtAllocFailures;
2094
2095	/** Profiling the RC/R0 \#PF access handler. */
2096	STAMPROFILE StatMonitorPfRZ;
2097	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2098	STAMPROFILE StatMonitorPfRZHandled;
2099	/** Times we've failed interpreting the instruction. */
2100	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2101	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2102	STAMPROFILE StatMonitorPfRZFlushPage;
2103	/** Times we've detected a page table reinit. */
2104	STAMCOUNTER StatMonitorPfRZFlushReinit;
2105	/** Counting flushes for pages that are modified too often. */
2106	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2107	/** Times we've detected fork(). */
2108	STAMCOUNTER StatMonitorPfRZFork;
2109	/** Times we've failed interpreting a patch code instruction. */
2110	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2111	/** Times we've failed interpreting a patch code instruction during flushing. */
2112	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2113	/** The number of times we've seen rep prefixes we can't handle. */
2114	STAMCOUNTER StatMonitorPfRZRepPrefix;
2115	/** Profiling the REP STOSD cases we've handled. */
2116	STAMPROFILE StatMonitorPfRZRepStosd;
2117
2118	/** Profiling the R0/RC regular access handler. */
2119	STAMPROFILE StatMonitorRZ;
2120	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2121	STAMPROFILE StatMonitorRZFlushPage;
2122	/** Per access size counts indexed by size minus 1, last for larger. */
2123	STAMCOUNTER aStatMonitorRZSizes[16+3];
2124	/** Missaligned access counts indexed by offset - 1. */
2125	STAMCOUNTER aStatMonitorRZMisaligned[7];
2126
2127	/** Nr of handled PT faults. */
2128	STAMCOUNTER StatMonitorRZFaultPT;
2129	/** Nr of handled PD faults. */
2130	STAMCOUNTER StatMonitorRZFaultPD;
2131	/** Nr of handled PDPT faults. */
2132	STAMCOUNTER StatMonitorRZFaultPDPT;
2133	/** Nr of handled PML4 faults. */
2134	STAMCOUNTER StatMonitorRZFaultPML4;
2135
2136	/** Profiling the R3 access handler. */
2137	STAMPROFILE StatMonitorR3;
2138	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2139	STAMPROFILE StatMonitorR3FlushPage;
2140	/** Per access size counts indexed by size minus 1, last for larger. */
2141	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2142	/** Missaligned access counts indexed by offset - 1. */
2143	STAMCOUNTER aStatMonitorR3Misaligned[7];
2144	/** Nr of handled PT faults. */
2145	STAMCOUNTER StatMonitorR3FaultPT;
2146	/** Nr of handled PD faults. */
2147	STAMCOUNTER StatMonitorR3FaultPD;
2148	/** Nr of handled PDPT faults. */
2149	STAMCOUNTER StatMonitorR3FaultPDPT;
2150	/** Nr of handled PML4 faults. */
2151	STAMCOUNTER StatMonitorR3FaultPML4;
2152
2153	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2154	STAMCOUNTER StatResetDirtyPages;
2155	/** Times we've called pgmPoolAddDirtyPage. */
2156	STAMCOUNTER StatDirtyPage;
2157	/** Times we've had to flush duplicates for dirty page management. */
2158	STAMCOUNTER StatDirtyPageDupFlush;
2159	/** Times we've had to flush because of overflow. */
2160	STAMCOUNTER StatDirtyPageOverFlowFlush;
2161
2162	/** The high water mark for cModifiedPages. */
2163	uint16_t cModifiedPagesHigh;
2164	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2165
2166	/** The number of cache hits. */
2167	STAMCOUNTER StatCacheHits;
2168	/** The number of cache misses. */
2169	STAMCOUNTER StatCacheMisses;
2170	/** The number of times we've got a conflict of 'kind' in the cache. */
2171	STAMCOUNTER StatCacheKindMismatches;
2172	/** Number of times we've been out of pages. */
2173	STAMCOUNTER StatCacheFreeUpOne;
2174	/** The number of cacheable allocations. */
2175	STAMCOUNTER StatCacheCacheable;
2176	/** The number of uncacheable allocations. */
2177	STAMCOUNTER StatCacheUncacheable;
2178	#else
2179	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2180	#endif
2181	/** Profiling PGMR0PoolGrow(). */
2182	STAMPROFILE StatGrow;
2183	/** The AVL tree for looking up a page by its HC physical address. */
2184	AVLOHCPHYSTREE HCPhysTree;
2185	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2186	/** Array of pages. (cMaxPages in length)
2187	* The Id is the index into thist array.
2188	*/
2189	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2190	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2191	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2192	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2193	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2194	#ifdef VBOX_WITH_STATISTICS
2195	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2196	#endif
2197	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2198
2199
2200	/** @def PGMPOOL_PAGE_2_PTR
2201	* Maps a pool page pool into the current context.
2202	*
2203	* @returns VBox status code.
2204	* @param a_pVM Pointer to the VM.
2205	* @param a_pPage The pool page.
2206	*
2207	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2208	* small page window employeed by that function. Be careful.
2209	* @remark There is no need to assert on the result.
2210	*/
2211	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2212	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2213	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2214	{
2215	RT_NOREF(pszCaller);
2216	AssertPtr(a_pPage);
2217	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2218	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2219	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2220	return a_pPage->CTX_SUFF(pvPage);
2221	}
2222	#else
2223	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2224	#endif
2225
2226
2227	/** @def PGMPOOL_PAGE_2_PTR_V2
2228	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2229	*
2230	* @returns VBox status code.
2231	* @param a_pVM Pointer to the VM.
2232	* @param a_pVCpu The current CPU.
2233	* @param a_pPage The pool page.
2234	*
2235	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2236	* small page window employeed by that function. Be careful.
2237	* @remark There is no need to assert on the result.
2238	*/
2239	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2240
2241
2242	/** @name Per guest page tracking data.
2243	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2244	* is to use more bits for it and split it up later on. But for now we'll play
2245	* safe and change as little as possible.
2246	*
2247	* The 16-bit word has two parts:
2248	*
2249	* The first 14-bit forms the @a idx field. It is either the index of a page in
2250	* the shadow page pool, or and index into the extent list.
2251	*
2252	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2253	* shadow page pool references to the page. If cRefs equals
2254	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2255	* (misnomer) table and not the shadow page pool.
2256	*
2257	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2258	* the 16-bit word.
2259	*
2260	* @{ */
2261	/** The shift count for getting to the cRefs part. */
2262	#define PGMPOOL_TD_CREFS_SHIFT 14
2263	/** The mask applied after shifting the tracking data down by
2264	* PGMPOOL_TD_CREFS_SHIFT. */
2265	#define PGMPOOL_TD_CREFS_MASK 0x3
2266	/** The cRefs value used to indicate that the idx is the head of a
2267	* physical cross reference list. */
2268	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2269	/** The shift used to get idx. */
2270	#define PGMPOOL_TD_IDX_SHIFT 0
2271	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2272	#define PGMPOOL_TD_IDX_MASK 0x3fff
2273	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2274	* simply too many mappings of this page. */
2275	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2276
2277	/** @def PGMPOOL_TD_MAKE
2278	* Makes a 16-bit tracking data word.
2279	*
2280	* @returns tracking data.
2281	* @param cRefs The @a cRefs field. Must be within bounds!
2282	* @param idx The @a idx field. Must also be within bounds! */
2283	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2284
2285	/** @def PGMPOOL_TD_GET_CREFS
2286	* Get the @a cRefs field from a tracking data word.
2287	*
2288	* @returns The @a cRefs field
2289	* @param u16 The tracking data word.
2290	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2291	* non-zero @a u16. */
2292	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2293
2294	/** @def PGMPOOL_TD_GET_IDX
2295	* Get the @a idx field from a tracking data word.
2296	*
2297	* @returns The @a idx field
2298	* @param u16 The tracking data word. */
2299	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2300	/** @} */
2301
2302
2303
2304	/** @name A20 gate macros
2305	* @{ */
2306	#define PGM_WITH_A20
2307	#ifdef PGM_WITH_A20
2308	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2309	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2310	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2311	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2312	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2313	#else
2314	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2315	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2316	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2317	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2318	#endif
2319	/** @} */
2320
2321
2322	/**
2323	* Roots and anchors for trees and list employing self relative offsets as
2324	* pointers.
2325	*
2326	* When using self-relative offsets instead of pointers, the offsets needs to be
2327	* the same in all offsets. Thus the roots and anchors needs to live on the
2328	* hyper heap just like the nodes.
2329	*/
2330	typedef struct PGMTREES
2331	{
2332	/** List of physical access handler types (offset pointers) of type
2333	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2334	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2335	/** Physical access handlers (AVL range+offsetptr tree). */
2336	AVLROGCPHYSTREE PhysHandlers;
2337	} PGMTREES;
2338	/** Pointer to PGM trees. */
2339	typedef PGMTREES *PPGMTREES;
2340
2341
2342	/**
2343	* Guest page table walk for the AMD64 mode.
2344	*/
2345	typedef struct PGMPTWALKGSTAMD64
2346	{
2347	PX86PML4 pPml4;
2348	PX86PML4E pPml4e;
2349	X86PML4E Pml4e;
2350
2351	PX86PDPT pPdpt;
2352	PX86PDPE pPdpe;
2353	X86PDPE Pdpe;
2354
2355	PX86PDPAE pPd;
2356	PX86PDEPAE pPde;
2357	X86PDEPAE Pde;
2358
2359	PX86PTPAE pPt;
2360	PX86PTEPAE pPte;
2361	X86PTEPAE Pte;
2362	} PGMPTWALKGSTAMD64;
2363	/** Pointer to a AMD64 guest page table walk. */
2364	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2365	/** Pointer to a const AMD64 guest page table walk. */
2366	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2367
2368	/**
2369	* Guest page table walk for the EPT mode.
2370	*/
2371	typedef struct PGMPTWALKGSTEPT
2372	{
2373	PEPTPML4 pPml4;
2374	PEPTPML4E pPml4e;
2375	EPTPML4E Pml4e;
2376
2377	PEPTPDPT pPdpt;
2378	PEPTPDPTE pPdpte;
2379	EPTPDPTE Pdpte;
2380
2381	PEPTPD pPd;
2382	PEPTPDE pPde;
2383	EPTPDE Pde;
2384
2385	PEPTPT pPt;
2386	PEPTPTE pPte;
2387	EPTPTE Pte;
2388	} PGMPTWALKGSTEPT;
2389	/** Pointer to an EPT guest page table walk. */
2390	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2391	/** Pointer to a const EPT guest page table walk. */
2392	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2393
2394	/**
2395	* Guest page table walk for the PAE mode.
2396	*/
2397	typedef struct PGMPTWALKGSTPAE
2398	{
2399	PX86PDPT pPdpt;
2400	PX86PDPE pPdpe;
2401	X86PDPE Pdpe;
2402
2403	PX86PDPAE pPd;
2404	PX86PDEPAE pPde;
2405	X86PDEPAE Pde;
2406
2407	PX86PTPAE pPt;
2408	PX86PTEPAE pPte;
2409	X86PTEPAE Pte;
2410	} PGMPTWALKGSTPAE;
2411	/** Pointer to a PAE guest page table walk. */
2412	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2413	/** Pointer to a const AMD64 guest page table walk. */
2414	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2415
2416	/**
2417	* Guest page table walk for the 32-bit mode.
2418	*/
2419	typedef struct PGMPTWALKGST32BIT
2420	{
2421	PX86PD pPd;
2422	PX86PDE pPde;
2423	X86PDE Pde;
2424
2425	PX86PT pPt;
2426	PX86PTE pPte;
2427	X86PTE Pte;
2428	} PGMPTWALKGST32BIT;
2429	/** Pointer to a 32-bit guest page table walk. */
2430	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2431	/** Pointer to a const 32-bit guest page table walk. */
2432	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2433
2434	/**
2435	* Which part of PGMPTWALKGST that is valid.
2436	*/
2437	typedef enum PGMPTWALKGSTTYPE
2438	{
2439	/** Customary invalid 0 value. */
2440	PGMPTWALKGSTTYPE_INVALID = 0,
2441	/** PGMPTWALKGST::u.Amd64 is valid. */
2442	PGMPTWALKGSTTYPE_AMD64,
2443	/** PGMPTWALKGST::u.Pae is valid. */
2444	PGMPTWALKGSTTYPE_PAE,
2445	/** PGMPTWALKGST::u.Legacy is valid. */
2446	PGMPTWALKGSTTYPE_32BIT,
2447	/** PGMPTWALKGST::u.Ept is valid. */
2448	PGMPTWALKGSTTYPE_EPT,
2449	/** Customary 32-bit type hack. */
2450	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2451	} PGMPTWALKGSTTYPE;
2452
2453	/**
2454	* Combined guest page table walk result.
2455	*/
2456	typedef struct PGMPTWALKGST
2457	{
2458	union
2459	{
2460	/** The page walker for AMD64. */
2461	PGMPTWALKGSTAMD64 Amd64;
2462	/** The page walker for PAE (32-bit). */
2463	PGMPTWALKGSTPAE Pae;
2464	/** The page walker for 32-bit paging (called legacy due to C naming
2465	* convension). */
2466	PGMPTWALKGST32BIT Legacy;
2467	/** The page walker for EPT (SLAT). */
2468	PGMPTWALKGSTEPT Ept;
2469	} u;
2470	/** Indicates which part of the union is valid. */
2471	PGMPTWALKGSTTYPE enmType;
2472	} PGMPTWALKGST;
2473	/** Pointer to a combined guest page table walk result. */
2474	typedef PGMPTWALKGST *PPGMPTWALKGST;
2475	/** Pointer to a read-only combined guest page table walk result. */
2476	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2477
2478
2479	/** @name Paging mode macros
2480	* @{
2481	*/
2482	#ifdef IN_RING3
2483	# define PGM_CTX(a,b) a##R3##b
2484	# define PGM_CTX_STR(a,b) a "R3" b
2485	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2486	#elif defined(IN_RING0)
2487	# define PGM_CTX(a,b) a##R0##b
2488	# define PGM_CTX_STR(a,b) a "R0" b
2489	# define PGM_CTX_DECL(type) VMMDECL(type)
2490	#else
2491	# error "Not IN_RING3 or IN_RING0!"
2492	#endif
2493
2494	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2495	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2496	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2497	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2498	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2499	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2500	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2501	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2502	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2503	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2504	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2505	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2506	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2507	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2508	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2509	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2510
2511	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2512	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2513	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2514	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2515
2516	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2517	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2518	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2519	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2520	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2521	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2522	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2523	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2524	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2525	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2526	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2527	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2528	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2529	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2530	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2531	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2532	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2533	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2534	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2535	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2536	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2537	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2538	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2539	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2540	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2541
2542	/* Shw_Gst */
2543	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2544	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2545	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2546	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2547	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2548	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2549	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2550	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2551	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2552	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2553	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2554	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2555	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2556	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2557	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2558	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2559	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2560	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2561	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2562	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2563	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2564	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2565	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2566	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2567	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2568	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2569	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2570	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2571	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2572	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2573	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2574	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2575	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2576	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2577
2578	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2579	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2580	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2581	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2582	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2583	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2584	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2585	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2586	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2587	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2588	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2589	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2590	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2591	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2592	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2593	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2594	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2595	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2596	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2597	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2598	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2599	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2600	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2601	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2602	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2603	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2604	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2605	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2606
2607	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2608	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2609	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2610	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2611	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2612	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2613	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2614	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2615	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2616	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2617	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2618	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2619	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2620	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2621	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2622	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2623	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2624	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2625	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2626	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2627	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2628	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2629	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2630	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2631	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2632	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2633	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2634	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2635	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2636
2637	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2638	/** @} */
2639
2640
2641	/**
2642	* Function pointers for guest paging.
2643	*/
2644	typedef struct PGMMODEDATAGST
2645	{
2646	/** The guest mode type. */
2647	uint32_t uType;
2648	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2649	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2650	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2651	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2652	#ifdef IN_RING3
2653	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2654	#endif
2655	} PGMMODEDATAGST;
2656
2657	/** The length of g_aPgmGuestModeData. */
2658	#if VBOX_WITH_64_BITS_GUESTS
2659	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2660	#else
2661	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2662	#endif
2663	/** The guest mode data array. */
2664	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2665
2666
2667	/**
2668	* Function pointers for shadow paging.
2669	*/
2670	typedef struct PGMMODEDATASHW
2671	{
2672	/** The shadow mode type. */
2673	uint32_t uType;
2674	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2675	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2676	uint64_t fMask, uint32_t fOpFlags));
2677	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, bool fIs64BitsPagingMode));
2678	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2679	#ifdef IN_RING3
2680	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2681	#endif
2682	} PGMMODEDATASHW;
2683
2684	/** The length of g_aPgmShadowModeData. */
2685	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2686	/** The shadow mode data array. */
2687	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2688
2689
2690	/**
2691	* Function pointers for guest+shadow paging.
2692	*/
2693	typedef struct PGMMODEDATABTH
2694	{
2695	/** The shadow mode type. */
2696	uint32_t uShwType;
2697	/** The guest mode type. */
2698	uint32_t uGstType;
2699
2700	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2701	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2702	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2703	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2704	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2705	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2706	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2707	#ifndef IN_RING3
2708	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2709	#endif
2710	#ifdef VBOX_STRICT
2711	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2712	#endif
2713	} PGMMODEDATABTH;
2714
2715	/** The length of g_aPgmBothModeData. */
2716	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2717	/** The guest+shadow mode data array. */
2718	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2719
2720
2721	#ifdef VBOX_WITH_STATISTICS
2722	/**
2723	* PGM statistics.
2724	*/
2725	typedef struct PGMSTATS
2726	{
2727	/* R3 only: */
2728	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2729	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2730
2731	/* R3+RZ */
2732	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2733	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2734	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2735	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2736	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2737	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2738	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2739	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2740	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2741	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2742	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2743	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2744	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2745	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2746	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2747	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2748	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2749	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2750	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2751	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2752	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2753	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2754	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2755	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2756	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2757	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2758
2759	/* RC only: */
2760	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2761	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2762
2763	STAMCOUNTER StatRZPhysRead;
2764	STAMCOUNTER StatRZPhysReadBytes;
2765	STAMCOUNTER StatRZPhysWrite;
2766	STAMCOUNTER StatRZPhysWriteBytes;
2767	STAMCOUNTER StatR3PhysRead;
2768	STAMCOUNTER StatR3PhysReadBytes;
2769	STAMCOUNTER StatR3PhysWrite;
2770	STAMCOUNTER StatR3PhysWriteBytes;
2771	STAMCOUNTER StatRCPhysRead;
2772	STAMCOUNTER StatRCPhysReadBytes;
2773	STAMCOUNTER StatRCPhysWrite;
2774	STAMCOUNTER StatRCPhysWriteBytes;
2775
2776	STAMCOUNTER StatRZPhysSimpleRead;
2777	STAMCOUNTER StatRZPhysSimpleReadBytes;
2778	STAMCOUNTER StatRZPhysSimpleWrite;
2779	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2780	STAMCOUNTER StatR3PhysSimpleRead;
2781	STAMCOUNTER StatR3PhysSimpleReadBytes;
2782	STAMCOUNTER StatR3PhysSimpleWrite;
2783	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2784	STAMCOUNTER StatRCPhysSimpleRead;
2785	STAMCOUNTER StatRCPhysSimpleReadBytes;
2786	STAMCOUNTER StatRCPhysSimpleWrite;
2787	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2788
2789	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2790	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2791	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2792	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2793	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2794	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2795	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2796
2797	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2798	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2799	/** pgmPhysIsValidLargePage profiling - R3 */
2800	STAMPROFILE StatR3IsValidLargePage;
2801	/** pgmPhysIsValidLargePage profiling - RZ*/
2802	STAMPROFILE StatRZIsValidLargePage;
2803
2804	STAMPROFILE StatChunkAging;
2805	STAMPROFILE StatChunkFindCandidate;
2806	STAMPROFILE StatChunkUnmap;
2807	STAMPROFILE StatChunkMap;
2808	} PGMSTATS;
2809	#endif /* VBOX_WITH_STATISTICS */
2810
2811
2812	/**
2813	* PGM Data (part of VM)
2814	*/
2815	typedef struct PGM
2816	{
2817	/** The zero page. */
2818	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2819	/** The MMIO placeholder page. */
2820	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2821
2822	/** @name The zero page (abPagePg).
2823	* @{ */
2824	/** The host physical address of the zero page. */
2825	RTHCPHYS HCPhysZeroPg;
2826	/** @}*/
2827
2828	/** @name The Invalid MMIO page (abMmioPg).
2829	* This page is filled with 0xfeedface.
2830	* @{ */
2831	/** The host physical address of the invalid MMIO page. */
2832	RTHCPHYS HCPhysMmioPg;
2833	/** The host pysical address of the invalid MMIO page plus all invalid
2834	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2835	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2836	RTHCPHYS HCPhysInvMmioPg;
2837	/** @} */
2838
2839	/** @cfgm{/RamPreAlloc, boolean, false}
2840	* Indicates whether the base RAM should all be allocated before starting
2841	* the VM (default), or if it should be allocated when first written to.
2842	*/
2843	bool fRamPreAlloc;
2844	#ifdef VBOX_WITH_PGM_NEM_MODE
2845	/** Set if we're operating in NEM memory mode.
2846	*
2847	* NEM mode implies that memory is allocated in big chunks for each RAM range
2848	* rather than on demand page by page. Memory is also not locked and PGM has
2849	* therefore no physical addresses for them. Page sharing is out of the
2850	* question. Ballooning depends on the native execution engine, but probably
2851	* pointless as well. */
2852	bool fNemMode;
2853	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2854	#else
2855	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2856	#endif
2857	/** Indicates whether write monitoring is currently in use.
2858	* This is used to prevent conflicts between live saving and page sharing
2859	* detection. */
2860	bool fPhysWriteMonitoringEngaged;
2861	/** Set if the CPU has less than 52-bit physical address width.
2862	* This is used */
2863	bool fLessThan52PhysicalAddressBits;
2864	/** Set when nested paging is active.
2865	* This is meant to save calls to HMIsNestedPagingActive and let the
2866	* compilers optimize the code better. Whether we use nested paging or
2867	* not is something we find out during VMM initialization and we won't
2868	* change this later on. */
2869	bool fNestedPaging;
2870	/** We're not in a state which permits writes to guest memory.
2871	* (Only used in strict builds.) */
2872	bool fNoMorePhysWrites;
2873	/** @cfgm{/PageFusionAllowed, boolean, false}
2874	* Whether page fusion is allowed. */
2875	bool fPageFusionAllowed;
2876	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2877	* Whether PCI passthrough is enabled. */
2878	bool fPciPassthrough;
2879	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2880	uint8_t cMmio2Regions;
2881	/** Restore original ROM page content when resetting after loading state.
2882	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2883	* enables the VM to start using an updated ROM without requiring powering
2884	* down the VM, just rebooting or resetting it. */
2885	bool fRestoreRomPagesOnReset;
2886	/** Whether to automatically clear all RAM pages on reset. */
2887	bool fZeroRamPagesOnReset;
2888	/** Large page enabled flag. */
2889	bool fUseLargePages;
2890	/** Alignment padding. */
2891	#ifndef VBOX_WITH_PGM_NEM_MODE
2892	bool afAlignment3[1];
2893	#endif
2894	/** The host paging mode. (This is what SUPLib reports.) */
2895	SUPPAGINGMODE enmHostMode;
2896	bool afAlignment3b[2];
2897
2898	/** Generation ID for the RAM ranges. This member is incremented everytime
2899	* a RAM range is linked or unlinked. */
2900	uint32_t volatile idRamRangesGen;
2901
2902	/** Physical access handler type for ROM protection. */
2903	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2904	/** Physical access handler type for MMIO2 dirty page tracing. */
2905	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
2906
2907	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2908	RTGCPHYS GCPhys4MBPSEMask;
2909	/** Mask containing the invalid bits of a guest physical address.
2910	* @remarks this does not stop at bit 52. */
2911	RTGCPHYS GCPhysInvAddrMask;
2912
2913
2914	/** RAM range TLB for R3. */
2915	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
2916	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2917	* This is sorted by physical address and contains no overlapping ranges. */
2918	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
2919	/** Root of the RAM range search tree for ring-3. */
2920	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
2921	/** PGM offset based trees - R3 Ptr. */
2922	R3PTRTYPE(PPGMTREES) pTreesR3;
2923	/** Caching the last physical handler we looked up in R3. */
2924	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2925	/** Shadow Page Pool - R3 Ptr. */
2926	R3PTRTYPE(PPGMPOOL) pPoolR3;
2927	/** Pointer to the list of ROM ranges - for R3.
2928	* This is sorted by physical address and contains no overlapping ranges. */
2929	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2930	/** Pointer to the list of MMIO2 ranges - for R3.
2931	* Registration order. */
2932	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
2933	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
2934	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
2935
2936	/** RAM range TLB for R0. */
2937	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
2938	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
2939	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
2940	/** Root of the RAM range search tree for ring-0. */
2941	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
2942	/** PGM offset based trees - R0 Ptr. */
2943	R0PTRTYPE(PPGMTREES) pTreesR0;
2944	/** Caching the last physical handler we looked up in R0. */
2945	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2946	/** Shadow Page Pool - R0 Ptr. */
2947	R0PTRTYPE(PPGMPOOL) pPoolR0;
2948	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2949	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2950	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
2951	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
2952
2953	/** Hack: Number of deprecated page mapping locks taken by the current lock
2954	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
2955	uint32_t cDeprecatedPageLocks;
2956	/** Alignment padding. */
2957	uint32_t au32Alignment2[1+2];
2958
2959	/** PGM critical section.
2960	* This protects the physical, ram ranges, and the page flag updating (some of
2961	* it anyway).
2962	*/
2963	PDMCRITSECT CritSectX;
2964
2965	/**
2966	* Data associated with managing the ring-3 mappings of the allocation chunks.
2967	*/
2968	struct
2969	{
2970	/** The chunk mapping TLB. */
2971	PGMCHUNKR3MAPTLB Tlb;
2972	/** The chunk tree, ordered by chunk id. */
2973	R3PTRTYPE(PAVLU32NODECORE) pTree;
2974	#if HC_ARCH_BITS == 32
2975	uint32_t u32Alignment0;
2976	#endif
2977	/** The number of mapped chunks. */
2978	uint32_t c;
2979	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
2980	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
2981	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
2982	uint32_t cMax;
2983	/** The current time. This is incremented whenever a chunk is inserted. */
2984	uint32_t iNow;
2985	/** Alignment padding. */
2986	uint32_t au32Alignment1[3];
2987	} ChunkR3Map;
2988
2989	/** The page mapping TLB for ring-3. */
2990	PGMPAGER3MAPTLB PhysTlbR3;
2991	/** The page mapping TLB for ring-0. */
2992	PGMPAGER0MAPTLB PhysTlbR0;
2993
2994	/** The number of handy pages. */
2995	uint32_t cHandyPages;
2996
2997	/** The number of large handy pages. */
2998	uint32_t cLargeHandyPages;
2999
3000	/**
3001	* Array of handy pages.
3002	*
3003	* This array is used in a two way communication between pgmPhysAllocPage
3004	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3005	* an intermediary.
3006	*
3007	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3008	* (The current size of 32 pages, means 128 KB of handy memory.)
3009	*/
3010	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3011
3012	/**
3013	* Array of large handy pages. (currently size 1)
3014	*
3015	* This array is used in a two way communication between pgmPhysAllocLargePage
3016	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3017	* an intermediary.
3018	*/
3019	GMMPAGEDESC aLargeHandyPage[1];
3020	/** When to try allocate large pages again after a failure. */
3021	uint64_t nsLargePageRetry;
3022	/** Number of repeated long allocation times. */
3023	uint32_t cLargePageLongAllocRepeats;
3024	uint32_t uPadding5;
3025
3026	/**
3027	* Live save data.
3028	*/
3029	struct
3030	{
3031	/** Per type statistics. */
3032	struct
3033	{
3034	/** The number of ready pages. */
3035	uint32_t cReadyPages;
3036	/** The number of dirty pages. */
3037	uint32_t cDirtyPages;
3038	/** The number of ready zero pages. */
3039	uint32_t cZeroPages;
3040	/** The number of write monitored pages. */
3041	uint32_t cMonitoredPages;
3042	} Rom,
3043	Mmio2,
3044	Ram;
3045	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3046	uint32_t cIgnoredPages;
3047	/** Indicates that a live save operation is active. */
3048	bool fActive;
3049	/** Padding. */
3050	bool afReserved[2];
3051	/** The next history index. */
3052	uint8_t iDirtyPagesHistory;
3053	/** History of the total amount of dirty pages. */
3054	uint32_t acDirtyPagesHistory[64];
3055	/** Short term dirty page average. */
3056	uint32_t cDirtyPagesShort;
3057	/** Long term dirty page average. */
3058	uint32_t cDirtyPagesLong;
3059	/** The number of saved pages. This is used to get some kind of estimate of the
3060	* link speed so we can decide when we're done. It is reset after the first
3061	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3062	* zero pages. */
3063	uint64_t cSavedPages;
3064	/** The nanosecond timestamp when cSavedPages was 0. */
3065	uint64_t uSaveStartNS;
3066	/** Pages per second (for statistics). */
3067	uint32_t cPagesPerSecond;
3068	uint32_t cAlignment;
3069	} LiveSave;
3070
3071	/** @name Error injection.
3072	* @{ */
3073	/** Inject handy page allocation errors pretending we're completely out of
3074	* memory. */
3075	bool volatile fErrInjHandyPages;
3076	/** Padding. */
3077	bool afReserved[3];
3078	/** @} */
3079
3080	/** @name Release Statistics
3081	* @{ */
3082	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3083	uint32_t cPrivatePages; /*< The number of private pages. /
3084	uint32_t cSharedPages; /*< The number of shared pages. /
3085	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3086	uint32_t cZeroPages; /*< The number of zero backed pages. /
3087	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3088	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3089	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3090	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3091	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3092	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3093	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3094	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3095	uint32_t cLargePages; /*< The number of large pages. /
3096	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3097	/* uint32_t aAlignment4[1]; */
3098
3099	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3100	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3101	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3102	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3103	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3104	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3105	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3106	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3107
3108	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3109
3110	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3111	/** @} */
3112
3113	#ifdef VBOX_WITH_STATISTICS
3114	/** These are optional statistics that used to be on the hyper heap. */
3115	PGMSTATS Stats;
3116	#endif
3117	} PGM;
3118	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3119	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3120	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3121	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3122	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3123	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3124	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3125	#endif /* !IN_TSTVMSTRUCTGC */
3126	/** Pointer to the PGM instance data. */
3127	typedef PGM *PPGM;
3128
3129
3130	#ifdef VBOX_WITH_STATISTICS
3131	/**
3132	* Per CPU statistis for PGM (used to be on the heap).
3133	*/
3134	typedef struct PGMCPUSTATS
3135	{
3136	/* Common */
3137	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3138	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3139
3140	/* R0 only: */
3141	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3142	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3143
3144	/* RZ only: */
3145	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3146	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3147	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3148	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3149	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3150	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3151	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3152	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3153	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3154	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3155	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3156	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3157	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3158	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3159	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3160	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3161	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3162	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3163	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3164	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3165	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3166	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3167	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3168	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3169	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3170	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3171	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3172	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3173	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3174	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3175	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3176	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3177	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3178	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3179	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3180	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3181	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3182	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3183	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3184	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3185	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3186	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3187	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3188	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3189	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3190	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3191	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3192	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3193	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3194	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3195	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3196	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3197	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3198	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3199	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3200	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3201	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3202	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3203	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3204	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3205	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3206	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3207	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3208	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3209	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3210	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3211	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3212	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3213	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3214	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3215
3216	/* HC - R3 and (maybe) R0: */
3217
3218	/* RZ & R3: */
3219	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3220	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3221	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3222	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3223	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3224	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3225	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3226	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3227	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3228	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3229	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3230	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3231	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3232	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3233	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3234	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3235	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3236	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3237	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3238	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3239	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3240	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3241	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3242	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3243	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3244	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3245	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3246	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3247	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3248	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3249	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3250	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3251	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3252	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3253	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3254	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3255	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3256	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3257	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3258	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3259	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3260	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3261	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3262	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3263	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3264	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3265	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3266
3267	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3268	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3269	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3270	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3271	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3272	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3273	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3274	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3275	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3276	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3277	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3278	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3279	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3280	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3281	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3282	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3283	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3284	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3285	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3286	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3287	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3288	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3289	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3290	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3291	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3292	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3293	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3294	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3295	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3296	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3297	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3298	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3299	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3300	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3301	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3302	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3303	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3304	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3305	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3306	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3307	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3308	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3309	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3310	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3311	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3312	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3313	} PGMCPUSTATS;
3314	#endif /* VBOX_WITH_STATISTICS */
3315
3316
3317	/**
3318	* PGMCPU Data (part of VMCPU).
3319	*/
3320	typedef struct PGMCPU
3321	{
3322	/** A20 gate mask.
3323	* Our current approach to A20 emulation is to let REM do it and don't bother
3324	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3325	* But whould need arrise, we'll subject physical addresses to this mask. */
3326	RTGCPHYS GCPhysA20Mask;
3327	/** A20 gate state - boolean! */
3328	bool fA20Enabled;
3329	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3330	bool fNoExecuteEnabled;
3331	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3332	* active. */
3333	bool fPaePdpesAndCr3MappedR3;
3334	bool fPaePdpesAndCr3MappedR0;
3335
3336	/** What needs syncing (PGM_SYNC_*).
3337	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3338	* PGMFlushTLB, and PGMR3Load. */
3339	uint32_t fSyncFlags;
3340
3341	/** The shadow paging mode. */
3342	PGMMODE enmShadowMode;
3343	/** The guest paging mode. */
3344	PGMMODE enmGuestMode;
3345	/** The guest second level address translation mode. */
3346	PGMSLAT enmGuestSlatMode;
3347	/** Guest mode data table index (PGM_TYPE_XXX). */
3348	uint8_t volatile idxGuestModeData;
3349	/** Shadow mode data table index (PGM_TYPE_XXX). */
3350	uint8_t volatile idxShadowModeData;
3351	/** Both mode data table index (complicated). */
3352	uint8_t volatile idxBothModeData;
3353	/** Alignment padding. */
3354	uint8_t abPadding[1];
3355
3356	/** The guest CR3.
3357	* When SLAT is active, this is the translated physical address.
3358	* When SLAT is inactive, this is the physical address in CR3. */
3359	RTGCPHYS GCPhysCR3;
3360
3361	/** The nested-guest CR3.
3362	* When SLAT is active, this is CR3 prior to translation.
3363	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3364	RTGCPHYS GCPhysNstGstCR3;
3365
3366	/** @name 32-bit Guest Paging.
3367	* @{ */
3368	/** The guest's page directory, R3 pointer. */
3369	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3370	/** The guest's page directory, R0 pointer. */
3371	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3372	/** Mask containing the MBZ bits of a big page PDE. */
3373	uint32_t fGst32BitMbzBigPdeMask;
3374	/** Set if the page size extension (PSE) is enabled. */
3375	bool fGst32BitPageSizeExtension;
3376	/** Alignment padding. */
3377	bool afAlignment2[3];
3378	/** @} */
3379
3380	/** @name PAE Guest Paging.
3381	* @{ */
3382	/** The guest's page directory pointer table, R3 pointer. */
3383	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3384	/** The guest's page directory pointer table, R0 pointer. */
3385	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3386
3387	/** The guest's page directories, R3 pointers.
3388	* These are individual pointers and don't have to be adjacent.
3389	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3390	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3391	/** The guest's page directories, R0 pointers.
3392	* Same restrictions as apGstPaePDsR3. */
3393	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3394	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3395	RTGCPHYS aGCPhysGstPaePDs[4];
3396	/** The physical addresses of the monitored guest page directories (PAE). */
3397	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3398	/** Mask containing the MBZ PTE bits. */
3399	uint64_t fGstPaeMbzPteMask;
3400	/** Mask containing the MBZ PDE bits. */
3401	uint64_t fGstPaeMbzPdeMask;
3402	/** Mask containing the MBZ big page PDE bits. */
3403	uint64_t fGstPaeMbzBigPdeMask;
3404	/** Mask containing the MBZ PDPE bits. */
3405	uint64_t fGstPaeMbzPdpeMask;
3406	/** @} */
3407
3408	/** @name AMD64 Guest Paging.
3409	* @{ */
3410	/** The guest's page directory pointer table, R3 pointer. */
3411	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3412	/** The guest's page directory pointer table, R0 pointer. */
3413	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3414	/** Mask containing the MBZ PTE bits. */
3415	uint64_t fGstAmd64MbzPteMask;
3416	/** Mask containing the MBZ PDE bits. */
3417	uint64_t fGstAmd64MbzPdeMask;
3418	/** Mask containing the MBZ big page PDE bits. */
3419	uint64_t fGstAmd64MbzBigPdeMask;
3420	/** Mask containing the MBZ PDPE bits. */
3421	uint64_t fGstAmd64MbzPdpeMask;
3422	/** Mask containing the MBZ big page PDPE bits. */
3423	uint64_t fGstAmd64MbzBigPdpeMask;
3424	/** Mask containing the MBZ PML4E bits. */
3425	uint64_t fGstAmd64MbzPml4eMask;
3426	/** Mask containing the PDPE bits that we shadow. */
3427	uint64_t fGstAmd64ShadowedPdpeMask;
3428	/** Mask containing the PML4E bits that we shadow. */
3429	uint64_t fGstAmd64ShadowedPml4eMask;
3430	/** @} */
3431
3432	/** @name PAE and AMD64 Guest Paging.
3433	* @{ */
3434	/** Mask containing the PTE bits that we shadow. */
3435	uint64_t fGst64ShadowedPteMask;
3436	/** Mask containing the PDE bits that we shadow. */
3437	uint64_t fGst64ShadowedPdeMask;
3438	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3439	uint64_t fGst64ShadowedBigPdeMask;
3440	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3441	uint64_t fGst64ShadowedBigPde4PteMask;
3442	/** @} */
3443
3444	/** @name EPT Guest Paging.
3445	* @{ */
3446	/** The guest's page directory pointer table, R3 pointer. */
3447	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3448	/** The guest's page directory pointer table, R0 pointer. */
3449	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3450	/** The guest's EPT pointer (copy of virtual VMCS). */
3451	uint64_t uEptPtr;
3452	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3453	* change through the lifetime of the VM. */
3454	uint64_t uEptVpidCapMsr;
3455	/** Mask containing the MBZ PTE bits. */
3456	uint64_t fGstEptMbzPteMask;
3457	/** Mask containing the MBZ PDE bits. */
3458	uint64_t fGstEptMbzPdeMask;
3459	/** Mask containing the MBZ big page (2M) PDE bits. */
3460	uint64_t fGstEptMbzBigPdeMask;
3461	/** Mask containing the MBZ PDPTE bits. */
3462	uint64_t fGstEptMbzPdpteMask;
3463	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3464	uint64_t fGstEptMbzBigPdpteMask;
3465	/** Mask containing the MBZ PML4E bits. */
3466	uint64_t fGstEptMbzPml4eMask;
3467	/** Mask to determine whether an entry is present. */
3468	uint64_t fGstEptPresentMask;
3469	/** @} */
3470
3471	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3472	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3473	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3474	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3475
3476	/** For saving stack space, the disassembler state is allocated here instead of
3477	* on the stack. */
3478	DISCPUSTATE DisState;
3479
3480	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3481	uint64_t cNetwareWp0Hacks;
3482
3483	/** Count the number of pgm pool access handler calls. */
3484	uint64_t cPoolAccessHandler;
3485
3486	/** @name Release Statistics
3487	* @{ */
3488	/** The number of times the guest has switched mode since last reset or statistics reset. */
3489	STAMCOUNTER cGuestModeChanges;
3490	/** The number of times the guest has switched mode since last reset or statistics reset. */
3491	STAMCOUNTER cA20Changes;
3492	/** @} */
3493
3494	#ifdef VBOX_WITH_STATISTICS
3495	/** These are statistics that used to be on the hyper heap. */
3496	PGMCPUSTATS Stats;
3497	#endif
3498	} PGMCPU;
3499	/** Pointer to the per-cpu PGM data. */
3500	typedef PGMCPU *PPGMCPU;
3501
3502
3503	/** @name PGM::fSyncFlags Flags
3504	* @note Was part of saved state a long time ago.
3505	* @{
3506	*/
3507	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3508	/** Always sync CR3. */
3509	#define PGM_SYNC_ALWAYS RT_BIT(1)
3510	/** Check guest mapping in SyncCR3. */
3511	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3512	/** Clear the page pool (a light weight flush). */
3513	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3514	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3515	/** @} */
3516
3517
3518	/**
3519	* PGM GVMCPU instance data.
3520	*/
3521	typedef struct PGMR0PERVCPU
3522	{
3523	#ifdef VBOX_WITH_STATISTICS
3524	/** R0: Which statistic this \#PF should be attributed to. */
3525	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3526	#endif
3527	uint64_t u64Dummy;
3528	} PGMR0PERVCPU;
3529
3530
3531	/**
3532	* PGM GVM instance data.
3533	*/
3534	typedef struct PGMR0PERVM
3535	{
3536	/** @name PGM Pool related stuff.
3537	* @{ */
3538	/** Critical section for serializing pool growth. */
3539	RTCRITSECT PoolGrowCritSect;
3540	/** The memory objects for the pool pages. */
3541	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3542	/** The ring-3 mapping objects for the pool pages. */
3543	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3544	/** @} */
3545	} PGMR0PERVM;
3546
3547	RT_C_DECLS_BEGIN
3548
3549	#if defined(VBOX_STRICT)
3550	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3551	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3552	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3553	#else
3554	int pgmLock(PVMCC pVM, bool fVoid);
3555	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3556	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3557	#endif
3558	void pgmUnlock(PVMCC pVM);
3559	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3560	/**
3561	* Asserts that the caller owns the PDM lock.
3562	* This is the internal variant of PGMIsLockOwner.
3563	* @param a_pVM Pointer to the VM.
3564	*/
3565	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3566	/**
3567	* Asserts that the caller owns the PDM lock.
3568	* This is the internal variant of PGMIsLockOwner.
3569	* @param a_pVM Pointer to the VM.
3570	* @param a_pVCpu The current CPU handle.
3571	*/
3572	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3573
3574	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3575	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3576	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3577	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3578	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3579	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3580	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3581	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3582	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3583	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3584	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3585	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3586
3587	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3588	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3589	#ifdef IN_RING0
3590	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3591	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3592	#endif
3593	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3594	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3595	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3596	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3597	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3598	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3599	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3600	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3601	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3602	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3603	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3604	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3605	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3606	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3607	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3608	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3609	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3610	#ifndef IN_RING3
3611	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
3612	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
3613	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3614	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3615	#endif
3616	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3617	PGMPAGETYPE enmNewType);
3618	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3619	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3620	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3621	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3622	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3623	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3624	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3625	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3626	#ifdef VBOX_WITH_NATIVE_NEM
3627	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3628	#endif
3629
3630	#ifdef IN_RING3
3631	void pgmR3PhysRelinkRamRanges(PVM pVM);
3632	int pgmR3PhysRamPreAllocate(PVM pVM);
3633	int pgmR3PhysRamReset(PVM pVM);
3634	int pgmR3PhysRomReset(PVM pVM);
3635	int pgmR3PhysRamZeroAll(PVM pVM);
3636	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3637	int pgmR3PhysRamTerm(PVM pVM);
3638	void pgmR3PhysRomTerm(PVM pVM);
3639	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3640
3641	int pgmR3PoolInit(PVM pVM);
3642	void pgmR3PoolRelocate(PVM pVM);
3643	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3644	void pgmR3PoolReset(PVM pVM);
3645	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3646	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3647	void pgmR3PoolWriteProtectPages(PVM pVM);
3648
3649	#endif /* IN_RING3 */
3650	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3651	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3652	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3653	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3654	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3655	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3656	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3657	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3658	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3659	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3660	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3661	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3662	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3663	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3664	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3665	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3666	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3667	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3668	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
3669	#ifndef IN_RING3
3670	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
3671	#endif
3672
3673	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3674	void pgmPoolResetDirtyPages(PVMCC pVM);
3675	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3676
3677	/** Gets the ring-0 pointer for the given pool page. */
3678	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3679	{
3680	#ifdef IN_RING3
3681	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3682	# ifdef VBOX_STRICT
3683	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3684	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3685	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3686	# endif
3687	return pPool->pPoolR0 + offPage;
3688	#else
3689	RT_NOREF(pPool);
3690	return pPage;
3691	#endif
3692	}
3693
3694	/** Gets the ring-3 pointer for the given pool page. */
3695	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3696	{
3697	#ifdef IN_RING3
3698	RT_NOREF(pPool);
3699	return pPage;
3700	#else
3701	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3702	# ifdef VBOX_STRICT
3703	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3704	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3705	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3706	# endif
3707	return pPool->pPoolR3 + offPage;
3708	#endif
3709	}
3710
3711	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3712	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3713	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3714
3715	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3716	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3717	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3718
3719	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3720	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3721	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3722	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3723	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3724	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3725	#endif
3726	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3727	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3728
3729	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3730	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3731	FNDBGCCMD pgmR3CmdShowSharedModules;
3732	# endif
3733
3734	void pgmLogState(PVM pVM);
3735
3736	RT_C_DECLS_END
3737
3738	/** @} */
3739
3740	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3741

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 93646

Download in other formats: