PGMInternal.h@ 96980

Last change on this file since 96980 was 96980, checked in by vboxsync, 2 years ago
VMM/PGM,IEM,HM: Added a PGMPHYSHANDLER_F_NOT_IN_HM flag to better deal with a nested APIC access page. [doxyfix] bugref:10092
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1	/* $Id: PGMInternal.h 96980 2022-10-04 12:51:42Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	//#if 0 /* disabled again while debugging */
79	#define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	//#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code. */
138	#ifdef DOXYGEN_RUNNING
139	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
140	#endif
141
142	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
143	* Enables real write monitoring of pages, i.e. mapping them read-only and
144	* only making them writable when getting a write access \#PF. */
145	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
146
147	/** @def VBOX_WITH_PGM_NEM_MODE
148	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
149	* details. */
150	#ifdef DOXYGEN_RUNNING
151	# define VBOX_WITH_PGM_NEM_MODE
152	#endif
153
154	/** @} */
155
156
157	/** @name PDPT and PML4 flags.
158	* These are placed in the three bits available for system programs in
159	* the PDPT and PML4 entries.
160	* @{ */
161	/** The entry is a permanent one and it's must always be present.
162	* Never free such an entry. */
163	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
164	/** PGM specific bits in PML4 entries. */
165	#define PGM_PML4_FLAGS 0
166	/** PGM specific bits in PDPT entries. */
167	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
168	/** @} */
169
170	/** @name Page directory flags.
171	* These are placed in the three bits available for system programs in
172	* the page directory entries.
173	* @{ */
174	/** Indicates the original entry was a big page.
175	* @remarks This is currently only used for statistics and can be recycled. */
176	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
177	/** Made read-only to facilitate dirty bit tracking. */
178	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
179	/** @} */
180
181	/** @name Page flags.
182	* These are placed in the three bits available for system programs in
183	* the page entries.
184	* @{ */
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
187
188	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
189	/** Scanned and approved by CSAM (tm).
190	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
191	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
192	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
193	#endif
194
195	/** @} */
196
197	/** @name Defines used to indicate the shadow and guest paging in the templates.
198	* @{ */
199	#define PGM_TYPE_REAL 1
200	#define PGM_TYPE_PROT 2
201	#define PGM_TYPE_32BIT 3
202	#define PGM_TYPE_PAE 4
203	#define PGM_TYPE_AMD64 5
204	#define PGM_TYPE_NESTED_32BIT 6
205	#define PGM_TYPE_NESTED_PAE 7
206	#define PGM_TYPE_NESTED_AMD64 8
207	#define PGM_TYPE_EPT 9
208	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
209	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
210	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
211	/** @} */
212
213	/** @name Defines used to indicate the second-level
214	* address translation (SLAT) modes in the templates.
215	* @{ */
216	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
217	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
218	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
219	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
220	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
221	/** @} */
222
223	/** Macro for checking if the guest is using paging.
224	* @param uGstType PGM_TYPE_*
225	* @param uShwType PGM_TYPE_*
226	* @remark ASSUMES certain order of the PGM_TYPE_* values.
227	*/
228	#define PGM_WITH_PAGING(uGstType, uShwType) \
229	( (uGstType) >= PGM_TYPE_32BIT \
230	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
231
232	/** Macro for checking if the guest supports the NX bit.
233	* @param uGstType PGM_TYPE_*
234	* @param uShwType PGM_TYPE_*
235	* @remark ASSUMES certain order of the PGM_TYPE_* values.
236	*/
237	#define PGM_WITH_NX(uGstType, uShwType) \
238	( (uGstType) >= PGM_TYPE_PAE \
239	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
240
241	/** Macro for checking for nested.
242	* @param uType PGM_TYPE_*
243	*/
244	#define PGM_TYPE_IS_NESTED(uType) \
245	( (uType) == PGM_TYPE_NESTED_32BIT \
246	\|\| (uType) == PGM_TYPE_NESTED_PAE \
247	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
248
249	/** Macro for checking for nested or EPT.
250	* @param uType PGM_TYPE_*
251	*/
252	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
253	( (uType) == PGM_TYPE_NESTED_32BIT \
254	\|\| (uType) == PGM_TYPE_NESTED_PAE \
255	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
256	\|\| (uType) == PGM_TYPE_EPT)
257
258
259
260	/** @def PGM_HCPHYS_2_PTR
261	* Maps a HC physical page pool address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
266	* @param HCPhys The HC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast
268	* this.
269	*
270	* @remark There is no need to assert on the result.
271	*/
272	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
273
274	/** @def PGM_GCPHYS_2_PTR_V2
275	* Maps a GC physical page address to a virtual address.
276	*
277	* @returns VBox status code.
278	* @param pVM The cross context VM structure.
279	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
280	* @param GCPhys The GC physical address to map to a virtual one.
281	* @param ppv Where to store the virtual address. No need to cast this.
282	*
283	* @remark Use with care as we don't have so much dynamic mapping space in
284	* ring-0 on 32-bit darwin and in RC.
285	* @remark There is no need to assert on the result.
286	*/
287	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
288	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
289
290	/** @def PGM_GCPHYS_2_PTR
291	* Maps a GC physical page address to a virtual address.
292	*
293	* @returns VBox status code.
294	* @param pVM The cross context VM structure.
295	* @param GCPhys The GC physical address to map to a virtual one.
296	* @param ppv Where to store the virtual address. No need to cast this.
297	*
298	* @remark Use with care as we don't have so much dynamic mapping space in
299	* ring-0 on 32-bit darwin and in RC.
300	* @remark There is no need to assert on the result.
301	*/
302	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
303
304	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
305	* Maps a GC physical page address to a virtual address.
306	*
307	* @returns VBox status code.
308	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
309	* @param GCPhys The GC physical address to map to a virtual one.
310	* @param ppv Where to store the virtual address. No need to cast this.
311	*
312	* @remark Use with care as we don't have so much dynamic mapping space in
313	* ring-0 on 32-bit darwin and in RC.
314	* @remark There is no need to assert on the result.
315	*/
316	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
317
318	/** @def PGM_GCPHYS_2_PTR_EX
319	* Maps a unaligned GC physical page address to a virtual address.
320	*
321	* @returns VBox status code.
322	* @param pVM The cross context VM structure.
323	* @param GCPhys The GC physical address to map to a virtual one.
324	* @param ppv Where to store the virtual address. No need to cast this.
325	*
326	* @remark Use with care as we don't have so much dynamic mapping space in
327	* ring-0 on 32-bit darwin and in RC.
328	* @remark There is no need to assert on the result.
329	*/
330	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
331	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
332
333	/** @def PGM_DYNMAP_UNUSED_HINT
334	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
335	* is no longer used.
336	*
337	* For best effect only apply this to the page that was mapped most recently.
338	*
339	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
340	* @param pvPage The pool page.
341	*/
342	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
343
344	/** @def PGM_DYNMAP_UNUSED_HINT_VM
345	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
346	* is no longer used.
347	*
348	* For best effect only apply this to the page that was mapped most recently.
349	*
350	* @param pVM The cross context VM structure.
351	* @param pvPage The pool page.
352	*/
353	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
354
355
356	/** @def PGM_INVL_PG
357	* Invalidates a page.
358	*
359	* @param pVCpu The cross context virtual CPU structure.
360	* @param GCVirt The virtual address of the page to invalidate.
361	*/
362	#ifdef IN_RING0
363	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
364	#elif defined(IN_RING3)
365	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
366	#else
367	# error "Not IN_RING0 or IN_RING3!"
368	#endif
369
370	/** @def PGM_INVL_PG_ALL_VCPU
371	* Invalidates a page on all VCPUs
372	*
373	* @param pVM The cross context VM structure.
374	* @param GCVirt The virtual address of the page to invalidate.
375	*/
376	#ifdef IN_RING0
377	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
378	#else
379	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
380	#endif
381
382	/** @def PGM_INVL_BIG_PG
383	* Invalidates a 4MB page directory entry.
384	*
385	* @param pVCpu The cross context virtual CPU structure.
386	* @param GCVirt The virtual address within the page directory to invalidate.
387	*/
388	#ifdef IN_RING0
389	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
390	#else
391	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
392	#endif
393
394	/** @def PGM_INVL_VCPU_TLBS()
395	* Invalidates the TLBs of the specified VCPU
396	*
397	* @param pVCpu The cross context virtual CPU structure.
398	*/
399	#ifdef IN_RING0
400	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
401	#else
402	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
403	#endif
404
405	/** @def PGM_INVL_ALL_VCPU_TLBS()
406	* Invalidates the TLBs of all VCPUs
407	*
408	* @param pVM The cross context VM structure.
409	*/
410	#ifdef IN_RING0
411	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
412	#else
413	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
414	#endif
415
416
417	/** @name Safer Shadow PAE PT/PTE
418	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419	* present.
420	*
421	* @{
422	*/
423	#if 1
424	/**
425	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
426	* invalid entries for present.
427	* @sa X86PTEPAE.
428	*/
429	typedef union PGMSHWPTEPAE
430	{
431	/** Unsigned integer view */
432	X86PGPAEUINT uCareful;
433	/* Not other views. */
434	} PGMSHWPTEPAE;
435
436	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
443	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
446	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
452
453	/**
454	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
455	* invalid entries for present.
456	* @sa X86PTPAE.
457	*/
458	typedef struct PGMSHWPTPAE
459	{
460	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461	} PGMSHWPTPAE;
462
463	#else
464	typedef X86PTEPAE PGMSHWPTEPAE;
465	typedef X86PTPAE PGMSHWPTPAE;
466	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
473	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
476	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
482
483	#endif
484
485	/** Pointer to a shadow PAE PTE. */
486	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487	/** Pointer to a const shadow PAE PTE. */
488	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490	/** Pointer to a shadow PAE page table. */
491	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492	/** Pointer to a const shadow PAE page table. */
493	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494	/** @} */
495
496
497	/** The physical access handler type handle count (power of two). */
498	#define PGMPHYSHANDLERTYPE_COUNT 0x20
499	/** Mask for getting the array index from an access handler type handle.
500	* The other handle bits are random and non-zero to avoid mixups due to zero
501	* initialized fields. */
502	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
503
504	/**
505	* Physical page access handler type registration, ring-0 part.
506	*/
507	typedef struct PGMPHYSHANDLERTYPEINTR0
508	{
509	/** The handle value for verfication. */
510	PGMPHYSHANDLERTYPE hType;
511	/** The kind of accesses we're handling. */
512	PGMPHYSHANDLERKIND enmKind;
513	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
514	uint8_t uState;
515	/** Whether to keep the PGM lock when calling the handler.
516	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
517	bool fKeepPgmLock;
518	/** Set if this is registered by a device instance and uUser should be
519	* translated from a device instance ID to a pointer.
520	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
521	bool fRing0DevInsIdx;
522	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
523	bool fNotInHm : 1;
524	/** Pointer to the ring-0 callback function. */
525	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
526	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
527	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
528	/** Description / Name. For easing debugging. */
529	R0PTRTYPE(const char *) pszDesc;
530	} PGMPHYSHANDLERTYPEINTR0;
531	/** Pointer to a physical access handler type registration. */
532	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
533
534	/**
535	* Physical page access handler type registration, shared/ring-3 part.
536	*/
537	typedef struct PGMPHYSHANDLERTYPEINTR3
538	{
539	/** The handle value for verfication. */
540	PGMPHYSHANDLERTYPE hType;
541	/** The kind of accesses we're handling. */
542	PGMPHYSHANDLERKIND enmKind;
543	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
544	uint8_t uState;
545	/** Whether to keep the PGM lock when calling the handler.
546	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
547	bool fKeepPgmLock;
548	/** Set if this is registered by a device instance and uUser should be
549	* translated from a device instance ID to a pointer.
550	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
551	bool fRing0DevInsIdx;
552	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
553	bool fRing0Enabled : 1;
554	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
555	bool fNotInHm : 1;
556	/** Pointer to the ring-3 callback function. */
557	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
558	/** Description / Name. For easing debugging. */
559	R3PTRTYPE(const char *) pszDesc;
560	} PGMPHYSHANDLERTYPEINTR3;
561	/** Pointer to a physical access handler type registration. */
562	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
563
564	/** Pointer to a physical access handler type record for the current context. */
565	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
566	/** Pointer to a const physical access handler type record for the current context. */
567	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
568	/** Dummy physical access handler type record. */
569	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
570
571
572	/**
573	* Physical page access handler structure.
574	*
575	* This is used to keep track of physical address ranges
576	* which are being monitored in some kind of way.
577	*/
578	typedef struct PGMPHYSHANDLER
579	{
580	/** @name Tree stuff.
581	* @{ */
582	/** First address. */
583	RTGCPHYS Key;
584	/** Last address. */
585	RTGCPHYS KeyLast;
586	uint32_t idxLeft;
587	uint32_t idxRight;
588	uint8_t cHeight;
589	/** @} */
590	uint8_t abPadding[3];
591	/** Number of pages to update. */
592	uint32_t cPages;
593	/** Set if we have pages that have been aliased. */
594	uint32_t cAliasedPages;
595	/** Set if we have pages that have temporarily been disabled. */
596	uint32_t cTmpOffPages;
597	/** Registered handler type handle.
598	* @note Marked volatile to prevent re-reading after validation. */
599	PGMPHYSHANDLERTYPE volatile hType;
600	/** User argument for the handlers. */
601	uint64_t uUser;
602	/** Description / Name. For easing debugging. */
603	R3PTRTYPE(const char *) pszDesc;
604	/** Profiling of this handler.
605	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
606	STAMPROFILE Stat;
607	} PGMPHYSHANDLER;
608	AssertCompileSize(PGMPHYSHANDLER, 12*8);
609	/** Pointer to a physical page access handler structure. */
610	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
611
612	/**
613	* Gets the type record for a physical handler (no reference added).
614	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
615	* @param a_pVM The cross context VM structure.
616	* @param a_pPhysHandler Pointer to the physical handler structure
617	* (PGMPHYSHANDLER).
618	*/
619	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
620	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
621
622	/**
623	* Gets the type record for a physical handler, never returns NULL.
624	*
625	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
626	* @param a_pVM The cross context VM structure.
627	* @param a_pPhysHandler Pointer to the physical handler structure
628	* (PGMPHYSHANDLER).
629	*/
630	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
631	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
632
633	/** Physical access handler allocator. */
634	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
635
636	/** Physical access handler tree. */
637	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
638	/** Pointer to a physical access handler tree. */
639	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
640
641
642	/**
643	* A Physical Guest Page tracking structure.
644	*
645	* The format of this structure is complicated because we have to fit a lot
646	* of information into as few bits as possible. The format is also subject
647	* to change (there is one coming up soon). Which means that for we'll be
648	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
649	* accesses to the structure.
650	*/
651	typedef union PGMPAGE
652	{
653	/** Structured view. */
654	struct
655	{
656	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
657	uint64_t u2HandlerPhysStateY : 2;
658	/** 3:2 - Paging structure needed to map the page
659	* (PGM_PAGE_PDE_TYPE_). /
660	uint64_t u2PDETypeY : 2;
661	/** 4 - Don't apply the physical handler in HM mode (nested APIC hack). */
662	uint64_t fHandlerPhysNotInHm : 1;
663	/** 5 - Flag indicating that a write monitored page was written to
664	* when set. */
665	uint64_t fWrittenToY : 1;
666	/** 7:6 - Unused. */
667	uint64_t u2Unused0 : 2;
668	/** 9:8 - Unused (was used by PGM_PAGE_HNDL_VIRT_STATE_). /
669	uint64_t u2Unused1 : 2;
670	/** 11:10 - NEM state bits. */
671	uint64_t u2NemStateY : 2;
672	/** 12:48 - The host physical frame number (shift left to get the
673	* address). */
674	uint64_t HCPhysFN : 36;
675	/** 50:48 - The page state. */
676	uint64_t uStateY : 3;
677	/** 51:53 - The page type (PGMPAGETYPE). */
678	uint64_t uTypeY : 3;
679	/** 63:54 - PTE index for usage tracking (page pool). */
680	uint64_t u10PteIdx : 10;
681
682	/** The GMM page ID.
683	* @remarks In the current implementation, MMIO2 and pages aliased to
684	* MMIO2 pages will be exploiting this field to calculate the
685	* ring-3 mapping address corresponding to the page.
686	* Later we may consider including MMIO2 management into GMM. */
687	uint32_t idPage;
688	/** Usage tracking (page pool). */
689	uint16_t u16TrackingY;
690	/** The number of read locks on this page. */
691	uint8_t cReadLocksY;
692	/** The number of write locks on this page. */
693	uint8_t cWriteLocksY;
694	} s;
695
696	/** 64-bit integer view. */
697	uint64_t au64[2];
698	/** 16-bit view. */
699	uint32_t au32[4];
700	/** 16-bit view. */
701	uint16_t au16[8];
702	/** 8-bit view. */
703	uint8_t au8[16];
704	} PGMPAGE;
705	AssertCompileSize(PGMPAGE, 16);
706	/** Pointer to a physical guest page. */
707	typedef PGMPAGE *PPGMPAGE;
708	/** Pointer to a const physical guest page. */
709	typedef const PGMPAGE *PCPGMPAGE;
710	/** Pointer to a physical guest page pointer. */
711	typedef PPGMPAGE *PPPGMPAGE;
712
713
714	/**
715	* Clears the page structure.
716	* @param a_pPage Pointer to the physical guest page tracking structure.
717	*/
718	#define PGM_PAGE_CLEAR(a_pPage) \
719	do { \
720	(a_pPage)->au64[0] = 0; \
721	(a_pPage)->au64[1] = 0; \
722	} while (0)
723
724	/**
725	* Initializes the page structure.
726	* @param a_pPage Pointer to the physical guest page tracking structure.
727	* @param a_HCPhys The host physical address of the page.
728	* @param a_idPage The (GMM) page ID of the page.
729	* @param a_uType The page type (PGMPAGETYPE).
730	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
731	*/
732	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
733	do { \
734	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
735	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
736	(a_pPage)->au64[0] = SetHCPhysTmp; \
737	(a_pPage)->au64[1] = 0; \
738	(a_pPage)->s.idPage = (a_idPage); \
739	(a_pPage)->s.uStateY = (a_uState); \
740	(a_pPage)->s.uTypeY = (a_uType); \
741	} while (0)
742
743	/**
744	* Initializes the page structure of a ZERO page.
745	* @param a_pPage Pointer to the physical guest page tracking structure.
746	* @param a_pVM The VM handle (for getting the zero page address).
747	* @param a_uType The page type (PGMPAGETYPE).
748	*/
749	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
750	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
751
752
753	/** @name The Page state, PGMPAGE::uStateY.
754	* @{ */
755	/** The zero page.
756	* This is a per-VM page that's never ever mapped writable. */
757	#define PGM_PAGE_STATE_ZERO 0U
758	/** A allocated page.
759	* This is a per-VM page allocated from the page pool (or wherever
760	* we get MMIO2 pages from if the type is MMIO2).
761	*/
762	#define PGM_PAGE_STATE_ALLOCATED 1U
763	/** A allocated page that's being monitored for writes.
764	* The shadow page table mappings are read-only. When a write occurs, the
765	* fWrittenTo member is set, the page remapped as read-write and the state
766	* moved back to allocated. */
767	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
768	/** The page is shared, aka. copy-on-write.
769	* This is a page that's shared with other VMs. */
770	#define PGM_PAGE_STATE_SHARED 3U
771	/** The page is ballooned, so no longer available for this VM. */
772	#define PGM_PAGE_STATE_BALLOONED 4U
773	/** @} */
774
775
776	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
777	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
778	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
779	#else
780	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
781	#endif
782
783	/**
784	* Gets the page state.
785	* @returns page state (PGM_PAGE_STATE_*).
786	* @param a_pPage Pointer to the physical guest page tracking structure.
787	*
788	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
789	* builds.
790	*/
791	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
792	#if defined(__GNUC__) && defined(VBOX_STRICT)
793	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
794	#else
795	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
796	#endif
797
798	/**
799	* Sets the page state.
800	* @param a_pVM The VM handle, only used for lock ownership assertions.
801	* @param a_pPage Pointer to the physical guest page tracking structure.
802	* @param a_uState The new page state.
803	*/
804	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
805	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
806
807
808	/**
809	* Gets the host physical address of the guest page.
810	* @returns host physical address (RTHCPHYS).
811	* @param a_pPage Pointer to the physical guest page tracking structure.
812	*
813	* @remarks In strict builds on gcc platforms, this macro will make some ugly
814	* assumption about a valid pVM variable/parameter being in the
815	* current context. It will use this pVM variable to assert that the
816	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
817	* pVM is not around.
818	*/
819	#if 0
820	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
821	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
822	#else
823	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
824	# if defined(__GNUC__) && defined(VBOX_STRICT)
825	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
826	# else
827	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
828	# endif
829	#endif
830
831	/**
832	* Sets the host physical address of the guest page.
833	*
834	* @param a_pVM The VM handle, only used for lock ownership assertions.
835	* @param a_pPage Pointer to the physical guest page tracking structure.
836	* @param a_HCPhys The new host physical address.
837	*/
838	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
839	do { \
840	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
841	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
842	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
843	PGM_PAGE_ASSERT_LOCK(a_pVM); \
844	} while (0)
845
846	/**
847	* Get the Page ID.
848	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
849	* @param a_pPage Pointer to the physical guest page tracking structure.
850	*/
851	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
852
853	/**
854	* Sets the Page ID.
855	* @param a_pVM The VM handle, only used for lock ownership assertions.
856	* @param a_pPage Pointer to the physical guest page tracking structure.
857	* @param a_idPage The new page ID.
858	*/
859	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
860	do { \
861	(a_pPage)->s.idPage = (a_idPage); \
862	PGM_PAGE_ASSERT_LOCK(a_pVM); \
863	} while (0)
864
865	/**
866	* Get the Chunk ID.
867	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
868	* @param a_pPage Pointer to the physical guest page tracking structure.
869	*/
870	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
871
872	/**
873	* Get the index of the page within the allocation chunk.
874	* @returns The page index.
875	* @param a_pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
878
879	/**
880	* Gets the page type.
881	* @returns The page type.
882	* @param a_pPage Pointer to the physical guest page tracking structure.
883	*
884	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
885	* builds.
886	*/
887	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
888	#if defined(__GNUC__) && defined(VBOX_STRICT)
889	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
890	#else
891	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
892	#endif
893
894	/**
895	* Sets the page type.
896	*
897	* @param a_pVM The VM handle, only used for lock ownership assertions.
898	* @param a_pPage Pointer to the physical guest page tracking structure.
899	* @param a_enmType The new page type (PGMPAGETYPE).
900	*/
901	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
902	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
903
904	/**
905	* Gets the page table index
906	* @returns The page table index.
907	* @param a_pPage Pointer to the physical guest page tracking structure.
908	*/
909	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
910
911	/**
912	* Sets the page table index.
913	* @param a_pVM The VM handle, only used for lock ownership assertions.
914	* @param a_pPage Pointer to the physical guest page tracking structure.
915	* @param a_iPte New page table index.
916	*/
917	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
918	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
919
920	/**
921	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
922	* @returns true/false.
923	* @param a_pPage Pointer to the physical guest page tracking structure.
924	*/
925	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
926
927	/**
928	* Checks if the page is marked for MMIO, including both aliases.
929	* @returns true/false.
930	* @param a_pPage Pointer to the physical guest page tracking structure.
931	*/
932	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
933	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
934	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
935	)
936
937	/**
938	* Checks if the page is marked for MMIO, including special aliases.
939	* @returns true/false.
940	* @param a_pPage Pointer to the physical guest page tracking structure.
941	*/
942	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
943	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
944
945	/**
946	* Checks if the page is a special aliased MMIO page.
947	* @returns true/false.
948	* @param a_pPage Pointer to the physical guest page tracking structure.
949	*/
950	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
951
952	/**
953	* Checks if the page is backed by the ZERO page.
954	* @returns true/false.
955	* @param a_pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
958
959	/**
960	* Checks if the page is backed by a SHARED page.
961	* @returns true/false.
962	* @param a_pPage Pointer to the physical guest page tracking structure.
963	*/
964	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
965
966	/**
967	* Checks if the page is ballooned.
968	* @returns true/false.
969	* @param a_pPage Pointer to the physical guest page tracking structure.
970	*/
971	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
972
973	/**
974	* Checks if the page is allocated.
975	* @returns true/false.
976	* @param a_pPage Pointer to the physical guest page tracking structure.
977	*/
978	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
979
980	/**
981	* Marks the page as written to (for GMM change monitoring).
982	* @param a_pVM The VM handle, only used for lock ownership assertions.
983	* @param a_pPage Pointer to the physical guest page tracking structure.
984	*/
985	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
986	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
987
988	/**
989	* Clears the written-to indicator.
990	* @param a_pVM The VM handle, only used for lock ownership assertions.
991	* @param a_pPage Pointer to the physical guest page tracking structure.
992	*/
993	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
994	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
995
996	/**
997	* Checks if the page was marked as written-to.
998	* @returns true/false.
999	* @param a_pPage Pointer to the physical guest page tracking structure.
1000	*/
1001	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1002
1003
1004	/** @name PT usage values (PGMPAGE::u2PDEType).
1005	*
1006	* @{ */
1007	/** Either as a PT or PDE. */
1008	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1009	/** Must use a page table to map the range. */
1010	#define PGM_PAGE_PDE_TYPE_PT 1
1011	/** Can use a page directory entry to map the continuous range. */
1012	#define PGM_PAGE_PDE_TYPE_PDE 2
1013	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1014	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1015	/** @} */
1016
1017	/**
1018	* Set the PDE type of the page
1019	* @param a_pVM The VM handle, only used for lock ownership assertions.
1020	* @param a_pPage Pointer to the physical guest page tracking structure.
1021	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1022	*/
1023	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1024	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1025
1026	/**
1027	* Checks if the page was marked being part of a large page
1028	* @returns true/false.
1029	* @param a_pPage Pointer to the physical guest page tracking structure.
1030	*/
1031	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1032
1033	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1034	*
1035	* @remarks The values are assigned in order of priority, so we can calculate
1036	* the correct state for a page with different handlers installed.
1037	* @{ */
1038	/** No handler installed. */
1039	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1040	/** Monitoring is temporarily disabled. */
1041	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1042	/** Write access is monitored. */
1043	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1044	/** All access is monitored. */
1045	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1046	/** @} */
1047
1048	/**
1049	* Gets the physical access handler state of a page.
1050	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1051	* @param a_pPage Pointer to the physical guest page tracking structure.
1052	*/
1053	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1054
1055	/**
1056	* Sets the physical access handler state of a page.
1057	* @param a_pPage Pointer to the physical guest page tracking structure.
1058	* @param a_uState The new state value.
1059	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1060	*/
1061	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1062	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1063
1064	/**
1065	* Sets the physical access handler state of a page.
1066	* @param a_pPage Pointer to the physical guest page tracking structure.
1067	* @param a_uState The new state value.
1068	*/
1069	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1070	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1071
1072	/**
1073	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1074	* @returns true/false
1075	* @param a_pPage Pointer to the physical guest page tracking structure.
1076	*/
1077	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1078	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1079
1080	/**
1081	* Checks if the page has any active physical access handlers.
1082	* @returns true/false
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1086	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1087
1088	/**
1089	* Checks if the page has any access handlers, including temporarily disabled ones.
1090	* @returns true/false
1091	* @param a_pPage Pointer to the physical guest page tracking structure.
1092	*/
1093	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1094	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1095
1096	/**
1097	* Checks if the page has any active access handlers.
1098	* @returns true/false
1099	* @param a_pPage Pointer to the physical guest page tracking structure.
1100	*/
1101	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1102	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1103
1104	/**
1105	* Checks if the page has any active access handlers catching all accesses.
1106	* @returns true/false
1107	* @param a_pPage Pointer to the physical guest page tracking structure.
1108	*/
1109	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1110	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1111
1112	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1113	* Checks if the physical handlers of the page should be ignored in shadow page
1114	* tables and such.
1115	* @returns true/false
1116	* @param a_pPage Pointer to the physical guest page tracking structure.
1117	*/
1118	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1119
1120	/** @def PGM_PAGE_GET_TRACKING
1121	* Gets the packed shadow page pool tracking data associated with a guest page.
1122	* @returns uint16_t containing the data.
1123	* @param a_pPage Pointer to the physical guest page tracking structure.
1124	*/
1125	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1126	#if defined(__GNUC__) && defined(VBOX_STRICT)
1127	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1128	#else
1129	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1130	#endif
1131
1132	/** @def PGM_PAGE_SET_TRACKING
1133	* Sets the packed shadow page pool tracking data associated with a guest page.
1134	* @param a_pVM The VM handle, only used for lock ownership assertions.
1135	* @param a_pPage Pointer to the physical guest page tracking structure.
1136	* @param a_u16TrackingData The tracking data to store.
1137	*/
1138	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1139	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1140
1141	/** @def PGM_PAGE_GET_TD_CREFS
1142	* Gets the @a cRefs tracking data member.
1143	* @returns cRefs.
1144	* @param a_pPage Pointer to the physical guest page tracking structure.
1145	*/
1146	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1147	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1148	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1149	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1150
1151	/** @def PGM_PAGE_GET_TD_IDX
1152	* Gets the @a idx tracking data member.
1153	* @returns idx.
1154	* @param a_pPage Pointer to the physical guest page tracking structure.
1155	*/
1156	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1157	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1158	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1159	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1160
1161
1162	/** Max number of locks on a page. */
1163	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1164
1165	/** Get the read lock count.
1166	* @returns count.
1167	* @param a_pPage Pointer to the physical guest page tracking structure.
1168	*/
1169	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1170
1171	/** Get the write lock count.
1172	* @returns count.
1173	* @param a_pPage Pointer to the physical guest page tracking structure.
1174	*/
1175	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1176
1177	/** Decrement the read lock counter.
1178	* @param a_pPage Pointer to the physical guest page tracking structure.
1179	*/
1180	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1181
1182	/** Decrement the write lock counter.
1183	* @param a_pPage Pointer to the physical guest page tracking structure.
1184	*/
1185	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1186
1187	/** Increment the read lock counter.
1188	* @param a_pPage Pointer to the physical guest page tracking structure.
1189	*/
1190	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1191
1192	/** Increment the write lock counter.
1193	* @param a_pPage Pointer to the physical guest page tracking structure.
1194	*/
1195	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1196
1197
1198	/** Gets the NEM state.
1199	* @returns NEM state value (two bits).
1200	* @param a_pPage Pointer to the physical guest page tracking structure.
1201	*/
1202	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1203
1204	/** Sets the NEM state.
1205	* @param a_pPage Pointer to the physical guest page tracking structure.
1206	* @param a_u2State The NEM state value (specific to NEM impl.).
1207	*/
1208	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1209	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1210
1211
1212	#if 0
1213	/** Enables sanity checking of write monitoring using CRC-32. */
1214	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1215	#endif
1216
1217	/**
1218	* Per page live save tracking data.
1219	*/
1220	typedef struct PGMLIVESAVERAMPAGE
1221	{
1222	/** Number of times it has been dirtied. */
1223	uint32_t cDirtied : 24;
1224	/** Whether it is currently dirty. */
1225	uint32_t fDirty : 1;
1226	/** Ignore the page.
1227	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1228	* deal with these after pausing the VM and DevPCI have said it bit about
1229	* remappings. */
1230	uint32_t fIgnore : 1;
1231	/** Was a ZERO page last time around. */
1232	uint32_t fZero : 1;
1233	/** Was a SHARED page last time around. */
1234	uint32_t fShared : 1;
1235	/** Whether the page is/was write monitored in a previous pass. */
1236	uint32_t fWriteMonitored : 1;
1237	/** Whether the page is/was write monitored earlier in this pass. */
1238	uint32_t fWriteMonitoredJustNow : 1;
1239	/** Bits reserved for future use. */
1240	uint32_t u2Reserved : 2;
1241	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1242	/** CRC-32 for the page. This is for internal consistency checks. */
1243	uint32_t u32Crc;
1244	#endif
1245	} PGMLIVESAVERAMPAGE;
1246	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1247	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1248	#else
1249	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1250	#endif
1251	/** Pointer to the per page live save tracking data. */
1252	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1253
1254	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1255	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1256
1257
1258	/**
1259	* RAM range for GC Phys to HC Phys conversion.
1260	*
1261	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1262	* conversions too, but we'll let MM handle that for now.
1263	*
1264	* This structure is used by linked lists in both GC and HC.
1265	*/
1266	typedef struct PGMRAMRANGE
1267	{
1268	/** Start of the range. Page aligned. */
1269	RTGCPHYS GCPhys;
1270	/** Size of the range. (Page aligned of course). */
1271	RTGCPHYS cb;
1272	/** Pointer to the next RAM range - for R3. */
1273	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1274	/** Pointer to the next RAM range - for R0. */
1275	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1276	/** PGM_RAM_RANGE_FLAGS_* flags. */
1277	uint32_t fFlags;
1278	/** NEM specific info, UINT32_MAX if not used. */
1279	uint32_t uNemRange;
1280	/** Last address in the range (inclusive). Page aligned (-1). */
1281	RTGCPHYS GCPhysLast;
1282	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1283	R3PTRTYPE(void *) pvR3;
1284	/** Live save per page tracking data. */
1285	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1286	/** The range description. */
1287	R3PTRTYPE(const char *) pszDesc;
1288	/** Pointer to self - R0 pointer. */
1289	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1290
1291	/** Pointer to the left search three node - ring-3 context. */
1292	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1293	/** Pointer to the right search three node - ring-3 context. */
1294	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1295	/** Pointer to the left search three node - ring-0 context. */
1296	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1297	/** Pointer to the right search three node - ring-0 context. */
1298	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1299
1300	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1301	#if HC_ARCH_BITS == 32
1302	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1303	#endif
1304	/** Array of physical guest page tracking structures.
1305	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1306	PGMPAGE aPages[1];
1307	} PGMRAMRANGE;
1308	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1309	typedef PGMRAMRANGE *PPGMRAMRANGE;
1310
1311	/** @name PGMRAMRANGE::fFlags
1312	* @{ */
1313	/** The RAM range is floating around as an independent guest mapping. */
1314	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1315	/** Ad hoc RAM range for an ROM mapping. */
1316	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1317	/** Ad hoc RAM range for an MMIO mapping. */
1318	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1319	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1320	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1321	/** @} */
1322
1323	/** Tests if a RAM range is an ad hoc one or not.
1324	* @returns true/false.
1325	* @param pRam The RAM range.
1326	*/
1327	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1328	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1329
1330	/** The number of entries in the RAM range TLBs (there is one for each
1331	* context). Must be a power of two. */
1332	#define PGM_RAMRANGE_TLB_ENTRIES 8
1333
1334	/**
1335	* Calculates the RAM range TLB index for the physical address.
1336	*
1337	* @returns RAM range TLB index.
1338	* @param a_GCPhys The guest physical address.
1339	*/
1340	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1341
1342	/**
1343	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1344	* mapping address.
1345	*/
1346	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1347	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1348
1349
1350	/**
1351	* Per page tracking structure for ROM image.
1352	*
1353	* A ROM image may have a shadow page, in which case we may have two pages
1354	* backing it. This structure contains the PGMPAGE for both while
1355	* PGMRAMRANGE have a copy of the active one. It is important that these
1356	* aren't out of sync in any regard other than page pool tracking data.
1357	*/
1358	typedef struct PGMROMPAGE
1359	{
1360	/** The page structure for the virgin ROM page. */
1361	PGMPAGE Virgin;
1362	/** The page structure for the shadow RAM page. */
1363	PGMPAGE Shadow;
1364	/** The current protection setting. */
1365	PGMROMPROT enmProt;
1366	/** Live save status information. Makes use of unused alignment space. */
1367	struct
1368	{
1369	/** The previous protection value. */
1370	uint8_t u8Prot;
1371	/** Written to flag set by the handler. */
1372	bool fWrittenTo;
1373	/** Whether the shadow page is dirty or not. */
1374	bool fDirty;
1375	/** Whether it was dirtied in the recently. */
1376	bool fDirtiedRecently;
1377	} LiveSave;
1378	} PGMROMPAGE;
1379	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1380	/** Pointer to a ROM page tracking structure. */
1381	typedef PGMROMPAGE *PPGMROMPAGE;
1382
1383
1384	/**
1385	* A registered ROM image.
1386	*
1387	* This is needed to keep track of ROM image since they generally intrude
1388	* into a PGMRAMRANGE. It also keeps track of additional info like the
1389	* two page sets (read-only virgin and read-write shadow), the current
1390	* state of each page.
1391	*
1392	* Because access handlers cannot easily be executed in a different
1393	* context, the ROM ranges needs to be accessible and in all contexts.
1394	*/
1395	typedef struct PGMROMRANGE
1396	{
1397	/** Pointer to the next range - R3. */
1398	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1399	/** Pointer to the next range - R0. */
1400	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1401	/** Pointer to the this range - R0. */
1402	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1403	/** Address of the range. */
1404	RTGCPHYS GCPhys;
1405	/** Address of the last byte in the range. */
1406	RTGCPHYS GCPhysLast;
1407	/** Size of the range. */
1408	RTGCPHYS cb;
1409	/** The flags (PGMPHYS_ROM_FLAGS_). /
1410	uint8_t fFlags;
1411	/** The saved state range ID. */
1412	uint8_t idSavedState;
1413	/** Alignment padding. */
1414	uint8_t au8Alignment[2];
1415	/** The size bits pvOriginal points to. */
1416	uint32_t cbOriginal;
1417	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1418	* This is used for strictness checks. */
1419	R3PTRTYPE(const void *) pvOriginal;
1420	/** The ROM description. */
1421	R3PTRTYPE(const char *) pszDesc;
1422	#ifdef VBOX_WITH_PGM_NEM_MODE
1423	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1424	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1425	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1426	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1427	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1428	R3PTRTYPE(uint8_t *) pbR3Alternate;
1429	RTR3PTR pvAlignment2;
1430	#endif
1431	/** The per page tracking structures. */
1432	PGMROMPAGE aPages[1];
1433	} PGMROMRANGE;
1434	/** Pointer to a ROM range. */
1435	typedef PGMROMRANGE *PPGMROMRANGE;
1436
1437
1438	/**
1439	* Live save per page data for an MMIO2 page.
1440	*
1441	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1442	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1443	* CRC-32 for detecting changes as well as special handling of zero pages. This
1444	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1445	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1446	* because of speed (2.5x and 6x slower).)
1447	*
1448	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1449	* save but normally is disabled. Since we can write monitor guest
1450	* accesses on our own, we only need this for host accesses. Shouldn't be
1451	* too difficult for DevVGA, VMMDev might be doable, the planned
1452	* networking fun will be fun since it involves ring-0.
1453	*/
1454	typedef struct PGMLIVESAVEMMIO2PAGE
1455	{
1456	/** Set if the page is considered dirty. */
1457	bool fDirty;
1458	/** The number of scans this page has remained unchanged for.
1459	* Only updated for dirty pages. */
1460	uint8_t cUnchangedScans;
1461	/** Whether this page was zero at the last scan. */
1462	bool fZero;
1463	/** Alignment padding. */
1464	bool fReserved;
1465	/** CRC-32 for the first half of the page.
1466	* This is used together with u32CrcH2 to quickly detect changes in the page
1467	* during the non-final passes. */
1468	uint32_t u32CrcH1;
1469	/** CRC-32 for the second half of the page. */
1470	uint32_t u32CrcH2;
1471	/** SHA-1 for the saved page.
1472	* This is used in the final pass to skip pages without changes. */
1473	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1474	} PGMLIVESAVEMMIO2PAGE;
1475	/** Pointer to a live save status data for an MMIO2 page. */
1476	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1477
1478	/**
1479	* A registered MMIO2 (= Device RAM) range.
1480	*
1481	* There are a few reason why we need to keep track of these registrations. One
1482	* of them is the deregistration & cleanup stuff, while another is that the
1483	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1484	* range list.
1485	*
1486	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1487	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1488	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1489	* overlap we will free all the existing RAM pages and put in the ram range
1490	* pages instead.
1491	*/
1492	typedef struct PGMREGMMIO2RANGE
1493	{
1494	/** The owner of the range. (a device) */
1495	PPDMDEVINSR3 pDevInsR3;
1496	/** Pointer to the ring-3 mapping of the allocation. */
1497	RTR3PTR pvR3;
1498	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1499	/** Pointer to the ring-0 mapping of the allocation. */
1500	RTR0PTR pvR0;
1501	#endif
1502	/** Pointer to the next range - R3. */
1503	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1504	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1505	uint16_t fFlags;
1506	/** The sub device number (internal PCI config (CFGM) number). */
1507	uint8_t iSubDev;
1508	/** The PCI region number. */
1509	uint8_t iRegion;
1510	/** The saved state range ID. */
1511	uint8_t idSavedState;
1512	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1513	uint8_t idMmio2;
1514	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1515	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1516	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1517	#else
1518	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1519	#endif
1520	/** The real size.
1521	* This may be larger than indicated by RamRange.cb if the range has been
1522	* reduced during saved state loading. */
1523	RTGCPHYS cbReal;
1524	/** Pointer to the physical handler for MMIO.
1525	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1526	* will be NULL. */
1527	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1528	/** Live save per page tracking data for MMIO2. */
1529	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1530	/** The associated RAM range. */
1531	PGMRAMRANGE RamRange;
1532	} PGMREGMMIO2RANGE;
1533	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1534	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1535	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1536
1537	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1538	* @{ */
1539	/** Set if this is the first chunk in the MMIO2 range. */
1540	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1541	/** Set if this is the last chunk in the MMIO2 range. */
1542	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1543	/** Set if the whole range is mapped. */
1544	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1545	/** Set if it's overlapping, clear if not. */
1546	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1547	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1548	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1549	/** Set if the access handler is registered. */
1550	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1551	/** Set if dirty page tracking is currently enabled. */
1552	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1553	/** Set if there are dirty pages in the range. */
1554	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1555	/** @} */
1556
1557
1558	/** @name Internal MMIO2 constants.
1559	* @{ */
1560	/** The maximum number of MMIO2 ranges. */
1561	#define PGM_MMIO2_MAX_RANGES 32
1562	/** The maximum number of pages in a MMIO2 range. */
1563	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1564	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1565	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1566	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1567	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1568	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1569	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1570	/** @} */
1571
1572
1573
1574	/**
1575	* PGMPhysRead/Write cache entry
1576	*/
1577	typedef struct PGMPHYSCACHEENTRY
1578	{
1579	/** R3 pointer to physical page. */
1580	R3PTRTYPE(uint8_t *) pbR3;
1581	/** GC Physical address for cache entry */
1582	RTGCPHYS GCPhys;
1583	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1584	RTGCPHYS u32Padding0; /*< alignment padding. /
1585	#endif
1586	} PGMPHYSCACHEENTRY;
1587
1588	/**
1589	* PGMPhysRead/Write cache to reduce REM memory access overhead
1590	*/
1591	typedef struct PGMPHYSCACHE
1592	{
1593	/** Bitmap of valid cache entries */
1594	uint64_t aEntries;
1595	/** Cache entries */
1596	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1597	} PGMPHYSCACHE;
1598
1599
1600	/** @name Ring-3 page mapping TLBs
1601	* @{ */
1602
1603	/** Pointer to an allocation chunk ring-3 mapping. */
1604	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1605	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1606	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1607
1608	/**
1609	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1610	*
1611	* The primary tree (Core) uses the chunk id as key.
1612	*/
1613	typedef struct PGMCHUNKR3MAP
1614	{
1615	/** The key is the chunk id. */
1616	AVLU32NODECORE Core;
1617	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1618	* selection. */
1619	uint32_t iLastUsed;
1620	/** The current reference count. */
1621	uint32_t volatile cRefs;
1622	/** The current permanent reference count. */
1623	uint32_t volatile cPermRefs;
1624	/** The mapping address. */
1625	void *pv;
1626	} PGMCHUNKR3MAP;
1627
1628	/**
1629	* Allocation chunk ring-3 mapping TLB entry.
1630	*/
1631	typedef struct PGMCHUNKR3MAPTLBE
1632	{
1633	/** The chunk id. */
1634	uint32_t volatile idChunk;
1635	#if HC_ARCH_BITS == 64
1636	uint32_t u32Padding; /*< alignment padding. /
1637	#endif
1638	/** The chunk map. */
1639	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1640	} PGMCHUNKR3MAPTLBE;
1641	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1642	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1643
1644	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1645	* @remark Must be a power of two value. */
1646	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1647
1648	/**
1649	* Allocation chunk ring-3 mapping TLB.
1650	*
1651	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1652	* At first glance this might look kinda odd since AVL trees are
1653	* supposed to give the most optimal lookup times of all trees
1654	* due to their balancing. However, take a tree with 1023 nodes
1655	* in it, that's 10 levels, meaning that most searches has to go
1656	* down 9 levels before they find what they want. This isn't fast
1657	* compared to a TLB hit. There is the factor of cache misses,
1658	* and of course the problem with trees and branch prediction.
1659	* This is why we use TLBs in front of most of the trees.
1660	*
1661	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1662	* difficult when we switch to the new inlined AVL trees (from kStuff).
1663	*/
1664	typedef struct PGMCHUNKR3MAPTLB
1665	{
1666	/** The TLB entries. */
1667	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1668	} PGMCHUNKR3MAPTLB;
1669
1670	/**
1671	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1672	* @returns Chunk TLB index.
1673	* @param idChunk The Chunk ID.
1674	*/
1675	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1676
1677
1678	/**
1679	* Ring-3 guest page mapping TLB entry.
1680	* @remarks used in ring-0 as well at the moment.
1681	*/
1682	typedef struct PGMPAGER3MAPTLBE
1683	{
1684	/** Address of the page. */
1685	RTGCPHYS volatile GCPhys;
1686	/** The guest page. */
1687	R3PTRTYPE(PPGMPAGE) volatile pPage;
1688	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1689	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1690	/** The address */
1691	R3PTRTYPE(void *) volatile pv;
1692	#if HC_ARCH_BITS == 32
1693	uint32_t u32Padding; /*< alignment padding. /
1694	#endif
1695	} PGMPAGER3MAPTLBE;
1696	/** Pointer to an entry in the HC physical TLB. */
1697	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1698
1699
1700	/** The number of entries in the ring-3 guest page mapping TLB.
1701	* @remarks The value must be a power of two. */
1702	#define PGM_PAGER3MAPTLB_ENTRIES 256
1703
1704	/**
1705	* Ring-3 guest page mapping TLB.
1706	* @remarks used in ring-0 as well at the moment.
1707	*/
1708	typedef struct PGMPAGER3MAPTLB
1709	{
1710	/** The TLB entries. */
1711	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1712	} PGMPAGER3MAPTLB;
1713	/** Pointer to the ring-3 guest page mapping TLB. */
1714	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1715
1716	/**
1717	* Calculates the index of the TLB entry for the specified guest page.
1718	* @returns Physical TLB index.
1719	* @param GCPhys The guest physical address.
1720	*/
1721	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1722
1723	/** @} */
1724
1725
1726	/** @name Ring-0 page mapping TLB
1727	* @{ */
1728	/**
1729	* Ring-0 guest page mapping TLB entry.
1730	*/
1731	typedef struct PGMPAGER0MAPTLBE
1732	{
1733	/** Address of the page. */
1734	RTGCPHYS volatile GCPhys;
1735	/** The guest page. */
1736	R0PTRTYPE(PPGMPAGE) volatile pPage;
1737	/** The address */
1738	R0PTRTYPE(void *) volatile pv;
1739	} PGMPAGER0MAPTLBE;
1740	/** Pointer to an entry in the HC physical TLB. */
1741	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1742
1743
1744	/** The number of entries in the ring-3 guest page mapping TLB.
1745	* @remarks The value must be a power of two. */
1746	#define PGM_PAGER0MAPTLB_ENTRIES 256
1747
1748	/**
1749	* Ring-3 guest page mapping TLB.
1750	* @remarks used in ring-0 as well at the moment.
1751	*/
1752	typedef struct PGMPAGER0MAPTLB
1753	{
1754	/** The TLB entries. */
1755	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1756	} PGMPAGER0MAPTLB;
1757	/** Pointer to the ring-3 guest page mapping TLB. */
1758	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1759
1760	/**
1761	* Calculates the index of the TLB entry for the specified guest page.
1762	* @returns Physical TLB index.
1763	* @param GCPhys The guest physical address.
1764	*/
1765	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1766	/** @} */
1767
1768
1769	/** @name Context neutral page mapper TLB.
1770	*
1771	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1772	* code is writting in a kind of context neutral way. Time will show whether
1773	* this actually makes sense or not...
1774	*
1775	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1776	* context ends up using a global mapping cache on some platforms
1777	* (darwin).
1778	*
1779	* @{ */
1780	/** @typedef PPGMPAGEMAPTLB
1781	* The page mapper TLB pointer type for the current context. */
1782	/** @typedef PPGMPAGEMAPTLB
1783	* The page mapper TLB entry pointer type for the current context. */
1784	/** @typedef PPGMPAGEMAPTLB
1785	* The page mapper TLB entry pointer pointer type for the current context. */
1786	/** @def PGM_PAGEMAPTLB_ENTRIES
1787	* The number of TLB entries in the page mapper TLB for the current context. */
1788	/** @def PGM_PAGEMAPTLB_IDX
1789	* Calculate the TLB index for a guest physical address.
1790	* @returns The TLB index.
1791	* @param GCPhys The guest physical address. */
1792	/** @typedef PPGMPAGEMAP
1793	* Pointer to a page mapper unit for current context. */
1794	/** @typedef PPPGMPAGEMAP
1795	* Pointer to a page mapper unit pointer for current context. */
1796	#if defined(IN_RING0)
1797	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1798	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1799	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1800	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1801	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1802	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1803	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1804	#else
1805	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1806	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1807	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1808	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1809	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1810	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1811	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1812	#endif
1813	/** @} */
1814
1815
1816	/** @name PGM Pool Indexes.
1817	* Aka. the unique shadow page identifier.
1818	* @{ */
1819	/** NIL page pool IDX. */
1820	#define NIL_PGMPOOL_IDX 0
1821	/** The first normal index. There used to be 5 fictive pages up front, now
1822	* there is only the NIL page. */
1823	#define PGMPOOL_IDX_FIRST 1
1824	/** The last valid index. (inclusive, 14 bits) */
1825	#define PGMPOOL_IDX_LAST 0x3fff
1826	/** @} */
1827
1828	/** The NIL index for the parent chain. */
1829	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1830	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1831
1832	/**
1833	* Node in the chain linking a shadowed page to it's parent (user).
1834	*/
1835	#pragma pack(1)
1836	typedef struct PGMPOOLUSER
1837	{
1838	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1839	uint16_t iNext;
1840	/** The user page index. */
1841	uint16_t iUser;
1842	/** Index into the user table. */
1843	uint32_t iUserTable;
1844	} PGMPOOLUSER, *PPGMPOOLUSER;
1845	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1846	#pragma pack()
1847
1848
1849	/** The NIL index for the phys ext chain. */
1850	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1851	/** The NIL pte index for a phys ext chain slot. */
1852	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1853
1854	/**
1855	* Node in the chain of physical cross reference extents.
1856	* @todo Calling this an 'extent' is not quite right, find a better name.
1857	* @todo find out the optimal size of the aidx array
1858	*/
1859	#pragma pack(1)
1860	typedef struct PGMPOOLPHYSEXT
1861	{
1862	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1863	uint16_t iNext;
1864	/** Alignment. */
1865	uint16_t u16Align;
1866	/** The user page index. */
1867	uint16_t aidx[3];
1868	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1869	uint16_t apte[3];
1870	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1871	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1872	#pragma pack()
1873
1874
1875	/**
1876	* The kind of page that's being shadowed.
1877	*/
1878	typedef enum PGMPOOLKIND
1879	{
1880	/** The virtual invalid 0 entry. */
1881	PGMPOOLKIND_INVALID = 0,
1882	/** The entry is free (=unused). */
1883	PGMPOOLKIND_FREE,
1884
1885	/** Shw: 32-bit page table; Gst: no paging. */
1886	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1887	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1888	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1889	/** Shw: 32-bit page table; Gst: 4MB page. */
1890	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1891	/** Shw: PAE page table; Gst: no paging. */
1892	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1893	/** Shw: PAE page table; Gst: 32-bit page table. */
1894	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1895	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1896	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1897	/** Shw: PAE page table; Gst: PAE page table. */
1898	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1899	/** Shw: PAE page table; Gst: 2MB page. */
1900	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1901
1902	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1903	PGMPOOLKIND_32BIT_PD,
1904	/** Shw: 32-bit page directory. Gst: no paging. */
1905	PGMPOOLKIND_32BIT_PD_PHYS,
1906	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1907	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1908	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1909	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1910	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1911	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1912	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1913	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1914	/** Shw: PAE page directory; Gst: PAE page directory. */
1915	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1916	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1917	PGMPOOLKIND_PAE_PD_PHYS,
1918
1919	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1920	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1921	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1922	PGMPOOLKIND_PAE_PDPT,
1923	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1924	PGMPOOLKIND_PAE_PDPT_PHYS,
1925
1926	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1927	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1928	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1929	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1930	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1931	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1932	/** Shw: 64-bit page directory table; Gst: no paging. */
1933	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1934
1935	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1936	PGMPOOLKIND_64BIT_PML4,
1937
1938	/** Shw: EPT page directory pointer table; Gst: no paging. */
1939	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1940	/** Shw: EPT page directory table; Gst: no paging. */
1941	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1942	/** Shw: EPT page table; Gst: no paging. */
1943	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1944
1945	/** Shw: Root Nested paging table. */
1946	PGMPOOLKIND_ROOT_NESTED,
1947
1948	/** Shw: EPT page table; Gst: EPT page table. */
1949	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1950	/** Shw: EPT page directory table; Gst: EPT page directory. */
1951	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1952	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1953	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1954	/** Shw: EPT PML4; Gst: EPT PML4. */
1955	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1956
1957	/** The last valid entry. */
1958	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1959	} PGMPOOLKIND;
1960
1961	/**
1962	* The access attributes of the page; only applies to big pages.
1963	*/
1964	typedef enum
1965	{
1966	PGMPOOLACCESS_DONTCARE = 0,
1967	PGMPOOLACCESS_USER_RW,
1968	PGMPOOLACCESS_USER_R,
1969	PGMPOOLACCESS_USER_RW_NX,
1970	PGMPOOLACCESS_USER_R_NX,
1971	PGMPOOLACCESS_SUPERVISOR_RW,
1972	PGMPOOLACCESS_SUPERVISOR_R,
1973	PGMPOOLACCESS_SUPERVISOR_RW_NX,
1974	PGMPOOLACCESS_SUPERVISOR_R_NX
1975	} PGMPOOLACCESS;
1976
1977	/**
1978	* The tracking data for a page in the pool.
1979	*/
1980	typedef struct PGMPOOLPAGE
1981	{
1982	/** AVL node code with the (HC) physical address of this page. */
1983	AVLOHCPHYSNODECORE Core;
1984	/** Pointer to the R3 mapping of the page. */
1985	R3PTRTYPE(void *) pvPageR3;
1986	/** Pointer to the R0 mapping of the page. */
1987	R0PTRTYPE(void *) pvPageR0;
1988	/** The guest physical address. */
1989	RTGCPHYS GCPhys;
1990	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1991	uint8_t enmKind;
1992	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
1993	uint8_t enmAccess;
1994	/** This supplements enmKind and enmAccess */
1995	bool fA20Enabled : 1;
1996
1997	/** Used to indicate that the page is zeroed. */
1998	bool fZeroed : 1;
1999	/** Used to indicate that a PT has non-global entries. */
2000	bool fSeenNonGlobal : 1;
2001	/** Used to indicate that we're monitoring writes to the guest page. */
2002	bool fMonitored : 1;
2003	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2004	* (All pages are in the age list.) */
2005	bool fCached : 1;
2006	/** This is used by the R3 access handlers when invoked by an async thread.
2007	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2008	bool volatile fReusedFlushPending : 1;
2009	/** Used to mark the page as dirty (write monitoring is temporarily
2010	* off). */
2011	bool fDirty : 1;
2012	bool fPadding1 : 1;
2013	bool fPadding2;
2014
2015	/** The index of this page. */
2016	uint16_t idx;
2017	/** The next entry in the list this page currently resides in.
2018	* It's either in the free list or in the GCPhys hash. */
2019	uint16_t iNext;
2020	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2021	uint16_t iUserHead;
2022	/** The number of present entries. */
2023	uint16_t cPresent;
2024	/** The first entry in the table which is present. */
2025	uint16_t iFirstPresent;
2026	/** The number of modifications to the monitored page. */
2027	uint16_t cModifications;
2028	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2029	uint16_t iModifiedNext;
2030	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2031	uint16_t iModifiedPrev;
2032	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2033	uint16_t iMonitoredNext;
2034	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2035	uint16_t iMonitoredPrev;
2036	/** The next page in the age list. */
2037	uint16_t iAgeNext;
2038	/** The previous page in the age list. */
2039	uint16_t iAgePrev;
2040	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2041	uint8_t idxDirtyEntry;
2042
2043	/** @name Access handler statistics to determine whether the guest is
2044	* (re)initializing a page table.
2045	* @{ */
2046	RTGCPTR GCPtrLastAccessHandlerRip;
2047	RTGCPTR GCPtrLastAccessHandlerFault;
2048	uint64_t cLastAccessHandler;
2049	/** @} */
2050	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2051	uint32_t volatile cLocked;
2052	#if GC_ARCH_BITS == 64
2053	uint32_t u32Alignment3;
2054	#endif
2055	# ifdef VBOX_STRICT
2056	RTGCPTR GCPtrDirtyFault;
2057	# endif
2058	} PGMPOOLPAGE;
2059	/** Pointer to a pool page. */
2060	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2061	/** Pointer to a const pool page. */
2062	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2063	/** Pointer to a pool page pointer. */
2064	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2065
2066
2067	/** The hash table size. */
2068	# define PGMPOOL_HASH_SIZE 0x8000
2069	/** The hash function. */
2070	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2071
2072
2073	/**
2074	* The shadow page pool instance data.
2075	*
2076	* It's all one big allocation made at init time, except for the
2077	* pages that is. The user nodes follows immediately after the
2078	* page structures.
2079	*/
2080	typedef struct PGMPOOL
2081	{
2082	/** The VM handle - R3 Ptr. */
2083	PVMR3 pVMR3;
2084	/** The VM handle - R0 Ptr. */
2085	R0PTRTYPE(PVMCC) pVMR0;
2086	/** The ring-3 pointer to this structure. */
2087	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2088	/** The ring-0 pointer to this structure. */
2089	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2090	/** The max pool size. This includes the special IDs. */
2091	uint16_t cMaxPages;
2092	/** The current pool size. */
2093	uint16_t cCurPages;
2094	/** The head of the free page list. */
2095	uint16_t iFreeHead;
2096	/* Padding. */
2097	uint16_t u16Padding;
2098	/** Head of the chain of free user nodes. */
2099	uint16_t iUserFreeHead;
2100	/** The number of user nodes we've allocated. */
2101	uint16_t cMaxUsers;
2102	/** The number of present page table entries in the entire pool. */
2103	uint32_t cPresent;
2104	/** Pointer to the array of user nodes - R3 pointer. */
2105	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2106	/** Pointer to the array of user nodes - R0 pointer. */
2107	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2108	/** Head of the chain of free phys ext nodes. */
2109	uint16_t iPhysExtFreeHead;
2110	/** The number of user nodes we've allocated. */
2111	uint16_t cMaxPhysExts;
2112	uint32_t u32Padding0b;
2113	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2114	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2115	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2116	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2117	/** Hash table for GCPhys addresses. */
2118	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2119	/** The head of the age list. */
2120	uint16_t iAgeHead;
2121	/** The tail of the age list. */
2122	uint16_t iAgeTail;
2123	/** Set if the cache is enabled. */
2124	bool fCacheEnabled;
2125	/** Alignment padding. */
2126	bool afPadding1[3];
2127	/** Head of the list of modified pages. */
2128	uint16_t iModifiedHead;
2129	/** The current number of modified pages. */
2130	uint16_t cModifiedPages;
2131	/** Alignment padding. */
2132	uint32_t u32Padding2;
2133	/** Physical access handler type registration handle. */
2134	PGMPHYSHANDLERTYPE hAccessHandlerType;
2135	/** Next available slot (in aDirtyPages). */
2136	uint32_t idxFreeDirtyPage;
2137	/** Number of active dirty pages. */
2138	uint32_t cDirtyPages;
2139	/** Array of current dirty pgm pool page indices. */
2140	uint16_t aidxDirtyPages[16];
2141	/** Array running in parallel to aidxDirtyPages with the page data. */
2142	struct
2143	{
2144	uint64_t aPage[512];
2145	} aDirtyPages[16];
2146
2147	/** The number of pages currently in use. */
2148	uint16_t cUsedPages;
2149	#ifdef VBOX_WITH_STATISTICS
2150	/** The high water mark for cUsedPages. */
2151	uint16_t cUsedPagesHigh;
2152	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2153	/** Profiling pgmPoolAlloc(). */
2154	STAMPROFILEADV StatAlloc;
2155	/** Profiling pgmR3PoolClearDoIt(). */
2156	STAMPROFILE StatClearAll;
2157	/** Profiling pgmR3PoolReset(). */
2158	STAMPROFILE StatR3Reset;
2159	/** Profiling pgmPoolFlushPage(). */
2160	STAMPROFILE StatFlushPage;
2161	/** Profiling pgmPoolFree(). */
2162	STAMPROFILE StatFree;
2163	/** Counting explicit flushes by PGMPoolFlushPage(). */
2164	STAMCOUNTER StatForceFlushPage;
2165	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2166	STAMCOUNTER StatForceFlushDirtyPage;
2167	/** Counting flushes for reused pages. */
2168	STAMCOUNTER StatForceFlushReused;
2169	/** Profiling time spent zeroing pages. */
2170	STAMPROFILE StatZeroPage;
2171	/** Profiling of pgmPoolTrackDeref. */
2172	STAMPROFILE StatTrackDeref;
2173	/** Profiling pgmTrackFlushGCPhysPT. */
2174	STAMPROFILE StatTrackFlushGCPhysPT;
2175	/** Profiling pgmTrackFlushGCPhysPTs. */
2176	STAMPROFILE StatTrackFlushGCPhysPTs;
2177	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2178	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2179	/** Number of times we've been out of user records. */
2180	STAMCOUNTER StatTrackFreeUpOneUser;
2181	/** Nr of flushed entries. */
2182	STAMCOUNTER StatTrackFlushEntry;
2183	/** Nr of updated entries. */
2184	STAMCOUNTER StatTrackFlushEntryKeep;
2185	/** Profiling deref activity related tracking GC physical pages. */
2186	STAMPROFILE StatTrackDerefGCPhys;
2187	/** Number of linear searches for a HCPhys in the ram ranges. */
2188	STAMCOUNTER StatTrackLinearRamSearches;
2189	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2190	STAMCOUNTER StamTrackPhysExtAllocFailures;
2191
2192	/** Profiling the RC/R0 \#PF access handler. */
2193	STAMPROFILE StatMonitorPfRZ;
2194	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2195	STAMPROFILE StatMonitorPfRZHandled;
2196	/** Times we've failed interpreting the instruction. */
2197	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2198	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2199	STAMPROFILE StatMonitorPfRZFlushPage;
2200	/** Times we've detected a page table reinit. */
2201	STAMCOUNTER StatMonitorPfRZFlushReinit;
2202	/** Counting flushes for pages that are modified too often. */
2203	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2204	/** Times we've detected fork(). */
2205	STAMCOUNTER StatMonitorPfRZFork;
2206	/** Times we've failed interpreting a patch code instruction. */
2207	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2208	/** Times we've failed interpreting a patch code instruction during flushing. */
2209	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2210	/** The number of times we've seen rep prefixes we can't handle. */
2211	STAMCOUNTER StatMonitorPfRZRepPrefix;
2212	/** Profiling the REP STOSD cases we've handled. */
2213	STAMPROFILE StatMonitorPfRZRepStosd;
2214
2215	/** Profiling the R0/RC regular access handler. */
2216	STAMPROFILE StatMonitorRZ;
2217	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2218	STAMPROFILE StatMonitorRZFlushPage;
2219	/** Per access size counts indexed by size minus 1, last for larger. */
2220	STAMCOUNTER aStatMonitorRZSizes[16+3];
2221	/** Missaligned access counts indexed by offset - 1. */
2222	STAMCOUNTER aStatMonitorRZMisaligned[7];
2223
2224	/** Nr of handled PT faults. */
2225	STAMCOUNTER StatMonitorRZFaultPT;
2226	/** Nr of handled PD faults. */
2227	STAMCOUNTER StatMonitorRZFaultPD;
2228	/** Nr of handled PDPT faults. */
2229	STAMCOUNTER StatMonitorRZFaultPDPT;
2230	/** Nr of handled PML4 faults. */
2231	STAMCOUNTER StatMonitorRZFaultPML4;
2232
2233	/** Profiling the R3 access handler. */
2234	STAMPROFILE StatMonitorR3;
2235	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2236	STAMPROFILE StatMonitorR3FlushPage;
2237	/** Per access size counts indexed by size minus 1, last for larger. */
2238	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2239	/** Missaligned access counts indexed by offset - 1. */
2240	STAMCOUNTER aStatMonitorR3Misaligned[7];
2241	/** Nr of handled PT faults. */
2242	STAMCOUNTER StatMonitorR3FaultPT;
2243	/** Nr of handled PD faults. */
2244	STAMCOUNTER StatMonitorR3FaultPD;
2245	/** Nr of handled PDPT faults. */
2246	STAMCOUNTER StatMonitorR3FaultPDPT;
2247	/** Nr of handled PML4 faults. */
2248	STAMCOUNTER StatMonitorR3FaultPML4;
2249
2250	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2251	STAMCOUNTER StatResetDirtyPages;
2252	/** Times we've called pgmPoolAddDirtyPage. */
2253	STAMCOUNTER StatDirtyPage;
2254	/** Times we've had to flush duplicates for dirty page management. */
2255	STAMCOUNTER StatDirtyPageDupFlush;
2256	/** Times we've had to flush because of overflow. */
2257	STAMCOUNTER StatDirtyPageOverFlowFlush;
2258
2259	/** The high water mark for cModifiedPages. */
2260	uint16_t cModifiedPagesHigh;
2261	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2262
2263	/** The number of cache hits. */
2264	STAMCOUNTER StatCacheHits;
2265	/** The number of cache misses. */
2266	STAMCOUNTER StatCacheMisses;
2267	/** The number of times we've got a conflict of 'kind' in the cache. */
2268	STAMCOUNTER StatCacheKindMismatches;
2269	/** Number of times we've been out of pages. */
2270	STAMCOUNTER StatCacheFreeUpOne;
2271	/** The number of cacheable allocations. */
2272	STAMCOUNTER StatCacheCacheable;
2273	/** The number of uncacheable allocations. */
2274	STAMCOUNTER StatCacheUncacheable;
2275	#else
2276	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2277	#endif
2278	/** Profiling PGMR0PoolGrow(). */
2279	STAMPROFILE StatGrow;
2280	/** The AVL tree for looking up a page by its HC physical address. */
2281	AVLOHCPHYSTREE HCPhysTree;
2282	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2283	/** Array of pages. (cMaxPages in length)
2284	* The Id is the index into thist array.
2285	*/
2286	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2287	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2288	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2289	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2290	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2291	#ifdef VBOX_WITH_STATISTICS
2292	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2293	#endif
2294	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2295
2296
2297	/** @def PGMPOOL_PAGE_2_PTR
2298	* Maps a pool page pool into the current context.
2299	*
2300	* @returns VBox status code.
2301	* @param a_pVM Pointer to the VM.
2302	* @param a_pPage The pool page.
2303	*
2304	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2305	* small page window employeed by that function. Be careful.
2306	* @remark There is no need to assert on the result.
2307	*/
2308	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2309	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2310	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2311	{
2312	RT_NOREF(pszCaller);
2313	AssertPtr(a_pPage);
2314	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2315	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2316	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2317	return a_pPage->CTX_SUFF(pvPage);
2318	}
2319	#else
2320	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2321	#endif
2322
2323
2324	/** @def PGMPOOL_PAGE_2_PTR_V2
2325	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2326	*
2327	* @returns VBox status code.
2328	* @param a_pVM Pointer to the VM.
2329	* @param a_pVCpu The current CPU.
2330	* @param a_pPage The pool page.
2331	*
2332	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2333	* small page window employeed by that function. Be careful.
2334	* @remark There is no need to assert on the result.
2335	*/
2336	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2337
2338
2339	/** @def PGMPOOL_PAGE_IS_NESTED
2340	* Checks whether the given pool page is a nested-guest pool page.
2341	*
2342	* @returns @c true if a nested-guest pool page, @c false otherwise.
2343	* @param a_pPage The pool page.
2344	* @todo We can optimize the conditionals later.
2345	*/
2346	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2347	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2348	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2349	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2350	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2351
2352	/** @name Per guest page tracking data.
2353	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2354	* is to use more bits for it and split it up later on. But for now we'll play
2355	* safe and change as little as possible.
2356	*
2357	* The 16-bit word has two parts:
2358	*
2359	* The first 14-bit forms the @a idx field. It is either the index of a page in
2360	* the shadow page pool, or and index into the extent list.
2361	*
2362	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2363	* shadow page pool references to the page. If cRefs equals
2364	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2365	* (misnomer) table and not the shadow page pool.
2366	*
2367	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2368	* the 16-bit word.
2369	*
2370	* @{ */
2371	/** The shift count for getting to the cRefs part. */
2372	#define PGMPOOL_TD_CREFS_SHIFT 14
2373	/** The mask applied after shifting the tracking data down by
2374	* PGMPOOL_TD_CREFS_SHIFT. */
2375	#define PGMPOOL_TD_CREFS_MASK 0x3
2376	/** The cRefs value used to indicate that the idx is the head of a
2377	* physical cross reference list. */
2378	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2379	/** The shift used to get idx. */
2380	#define PGMPOOL_TD_IDX_SHIFT 0
2381	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2382	#define PGMPOOL_TD_IDX_MASK 0x3fff
2383	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2384	* simply too many mappings of this page. */
2385	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2386
2387	/** @def PGMPOOL_TD_MAKE
2388	* Makes a 16-bit tracking data word.
2389	*
2390	* @returns tracking data.
2391	* @param cRefs The @a cRefs field. Must be within bounds!
2392	* @param idx The @a idx field. Must also be within bounds! */
2393	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2394
2395	/** @def PGMPOOL_TD_GET_CREFS
2396	* Get the @a cRefs field from a tracking data word.
2397	*
2398	* @returns The @a cRefs field
2399	* @param u16 The tracking data word.
2400	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2401	* non-zero @a u16. */
2402	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2403
2404	/** @def PGMPOOL_TD_GET_IDX
2405	* Get the @a idx field from a tracking data word.
2406	*
2407	* @returns The @a idx field
2408	* @param u16 The tracking data word. */
2409	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2410	/** @} */
2411
2412
2413
2414	/** @name A20 gate macros
2415	* @{ */
2416	#define PGM_WITH_A20
2417	#ifdef PGM_WITH_A20
2418	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2419	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2420	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2421	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2422	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2423	#else
2424	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2425	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2426	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2427	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2428	#endif
2429	/** @} */
2430
2431
2432	/**
2433	* Guest page table walk for the AMD64 mode.
2434	*/
2435	typedef struct PGMPTWALKGSTAMD64
2436	{
2437	PX86PML4 pPml4;
2438	PX86PML4E pPml4e;
2439	X86PML4E Pml4e;
2440
2441	PX86PDPT pPdpt;
2442	PX86PDPE pPdpe;
2443	X86PDPE Pdpe;
2444
2445	PX86PDPAE pPd;
2446	PX86PDEPAE pPde;
2447	X86PDEPAE Pde;
2448
2449	PX86PTPAE pPt;
2450	PX86PTEPAE pPte;
2451	X86PTEPAE Pte;
2452	} PGMPTWALKGSTAMD64;
2453	/** Pointer to a AMD64 guest page table walk. */
2454	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2455	/** Pointer to a const AMD64 guest page table walk. */
2456	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2457
2458	/**
2459	* Guest page table walk for the EPT mode.
2460	*/
2461	typedef struct PGMPTWALKGSTEPT
2462	{
2463	PEPTPML4 pPml4;
2464	PEPTPML4E pPml4e;
2465	EPTPML4E Pml4e;
2466
2467	PEPTPDPT pPdpt;
2468	PEPTPDPTE pPdpte;
2469	EPTPDPTE Pdpte;
2470
2471	PEPTPD pPd;
2472	PEPTPDE pPde;
2473	EPTPDE Pde;
2474
2475	PEPTPT pPt;
2476	PEPTPTE pPte;
2477	EPTPTE Pte;
2478	} PGMPTWALKGSTEPT;
2479	/** Pointer to an EPT guest page table walk. */
2480	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2481	/** Pointer to a const EPT guest page table walk. */
2482	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2483
2484	/**
2485	* Guest page table walk for the PAE mode.
2486	*/
2487	typedef struct PGMPTWALKGSTPAE
2488	{
2489	PX86PDPT pPdpt;
2490	PX86PDPE pPdpe;
2491	X86PDPE Pdpe;
2492
2493	PX86PDPAE pPd;
2494	PX86PDEPAE pPde;
2495	X86PDEPAE Pde;
2496
2497	PX86PTPAE pPt;
2498	PX86PTEPAE pPte;
2499	X86PTEPAE Pte;
2500	} PGMPTWALKGSTPAE;
2501	/** Pointer to a PAE guest page table walk. */
2502	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2503	/** Pointer to a const AMD64 guest page table walk. */
2504	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2505
2506	/**
2507	* Guest page table walk for the 32-bit mode.
2508	*/
2509	typedef struct PGMPTWALKGST32BIT
2510	{
2511	PX86PD pPd;
2512	PX86PDE pPde;
2513	X86PDE Pde;
2514
2515	PX86PT pPt;
2516	PX86PTE pPte;
2517	X86PTE Pte;
2518	} PGMPTWALKGST32BIT;
2519	/** Pointer to a 32-bit guest page table walk. */
2520	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2521	/** Pointer to a const 32-bit guest page table walk. */
2522	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2523
2524	/**
2525	* Which part of PGMPTWALKGST that is valid.
2526	*/
2527	typedef enum PGMPTWALKGSTTYPE
2528	{
2529	/** Customary invalid 0 value. */
2530	PGMPTWALKGSTTYPE_INVALID = 0,
2531	/** PGMPTWALKGST::u.Amd64 is valid. */
2532	PGMPTWALKGSTTYPE_AMD64,
2533	/** PGMPTWALKGST::u.Pae is valid. */
2534	PGMPTWALKGSTTYPE_PAE,
2535	/** PGMPTWALKGST::u.Legacy is valid. */
2536	PGMPTWALKGSTTYPE_32BIT,
2537	/** PGMPTWALKGST::u.Ept is valid. */
2538	PGMPTWALKGSTTYPE_EPT,
2539	/** Customary 32-bit type hack. */
2540	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2541	} PGMPTWALKGSTTYPE;
2542
2543	/**
2544	* Combined guest page table walk result.
2545	*/
2546	typedef struct PGMPTWALKGST
2547	{
2548	union
2549	{
2550	/** The page walker for AMD64. */
2551	PGMPTWALKGSTAMD64 Amd64;
2552	/** The page walker for PAE (32-bit). */
2553	PGMPTWALKGSTPAE Pae;
2554	/** The page walker for 32-bit paging (called legacy due to C naming
2555	* convension). */
2556	PGMPTWALKGST32BIT Legacy;
2557	/** The page walker for EPT (SLAT). */
2558	PGMPTWALKGSTEPT Ept;
2559	} u;
2560	/** Indicates which part of the union is valid. */
2561	PGMPTWALKGSTTYPE enmType;
2562	} PGMPTWALKGST;
2563	/** Pointer to a combined guest page table walk result. */
2564	typedef PGMPTWALKGST *PPGMPTWALKGST;
2565	/** Pointer to a read-only combined guest page table walk result. */
2566	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2567
2568
2569	/** @name Paging mode macros
2570	* @{
2571	*/
2572	#ifdef IN_RING3
2573	# define PGM_CTX(a,b) a##R3##b
2574	# define PGM_CTX_STR(a,b) a "R3" b
2575	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2576	#elif defined(IN_RING0)
2577	# define PGM_CTX(a,b) a##R0##b
2578	# define PGM_CTX_STR(a,b) a "R0" b
2579	# define PGM_CTX_DECL(type) VMMDECL(type)
2580	#else
2581	# error "Not IN_RING3 or IN_RING0!"
2582	#endif
2583
2584	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2585	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2586	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2587	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2588	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2589	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2590	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2591	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2592	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2593	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2594	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2595	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2596	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2597	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2598	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2599	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2600
2601	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2602	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2603	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2604	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2605
2606	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2607	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2608	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2609	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2610	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2611	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2612	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2613	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2614	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2615	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2616	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2617	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2618	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2619	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2620	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2621	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2622	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2623	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2624	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2625	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2626	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2627	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2628	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2629	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2630	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2631
2632	/* Shw_Gst */
2633	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2634	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2635	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2636	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2637	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2638	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2639	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2640	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2641	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2642	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2643	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2644	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2645	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2646	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2647	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2648	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2649	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2650	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2651	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2652	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2653	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2654	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2655	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2656	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2657	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2658	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2659	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2660	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2661	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2662	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2663	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2664	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2665	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2666	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2667
2668	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2669	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2670	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2671	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2672	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2673	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2674	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2675	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2676	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2677	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2678	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2679	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2680	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2681	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2682	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2683	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2684	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2685	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2686	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2687	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2688	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2689	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2690	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2691	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2692	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2693	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2694	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2695	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2696
2697	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2698	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2699	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2700	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2701	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2702	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2703	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2704	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2705	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2706	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2707	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2708	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2709	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2710	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2711	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2712	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2713	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2714	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2715	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2716	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2717	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2718	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2719	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2720	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2721	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2722	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2723	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2724	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2725	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2726
2727	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2728	/** @} */
2729
2730
2731	/**
2732	* Function pointers for guest paging.
2733	*/
2734	typedef struct PGMMODEDATAGST
2735	{
2736	/** The guest mode type. */
2737	uint32_t uType;
2738	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2739	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2740	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2741	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2742	#ifdef IN_RING3
2743	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2744	#endif
2745	} PGMMODEDATAGST;
2746
2747	/** The length of g_aPgmGuestModeData. */
2748	#if VBOX_WITH_64_BITS_GUESTS
2749	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2750	#else
2751	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2752	#endif
2753	/** The guest mode data array. */
2754	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2755
2756
2757	/**
2758	* Function pointers for shadow paging.
2759	*/
2760	typedef struct PGMMODEDATASHW
2761	{
2762	/** The shadow mode type. */
2763	uint32_t uType;
2764	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2765	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2766	uint64_t fMask, uint32_t fOpFlags));
2767	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2768	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2769	#ifdef IN_RING3
2770	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2771	#endif
2772	} PGMMODEDATASHW;
2773
2774	/** The length of g_aPgmShadowModeData. */
2775	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2776	/** The shadow mode data array. */
2777	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2778
2779
2780	/**
2781	* Function pointers for guest+shadow paging.
2782	*/
2783	typedef struct PGMMODEDATABTH
2784	{
2785	/** The shadow mode type. */
2786	uint32_t uShwType;
2787	/** The guest mode type. */
2788	uint32_t uGstType;
2789
2790	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2791	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2792	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2793	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2794	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2795	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2796	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2797	#ifndef IN_RING3
2798	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2799	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNested,
2800	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2801	bool *pfLockTaken));
2802	#endif
2803	#ifdef VBOX_STRICT
2804	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2805	#endif
2806	} PGMMODEDATABTH;
2807
2808	/** The length of g_aPgmBothModeData. */
2809	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2810	/** The guest+shadow mode data array. */
2811	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2812
2813
2814	#ifdef VBOX_WITH_STATISTICS
2815	/**
2816	* PGM statistics.
2817	*/
2818	typedef struct PGMSTATS
2819	{
2820	/* R3 only: */
2821	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2822	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2823
2824	/* R3+RZ */
2825	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2826	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2827	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2828	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2829	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2830	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2831	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2832	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2833	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2834	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2835	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2836	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2837	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2838	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2839	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2840	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2841	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2842	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2843	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2844	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2845	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2846	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2847	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2848	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2849	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2850	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2851
2852	/* RC only: */
2853	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2854	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2855
2856	STAMCOUNTER StatRZPhysRead;
2857	STAMCOUNTER StatRZPhysReadBytes;
2858	STAMCOUNTER StatRZPhysWrite;
2859	STAMCOUNTER StatRZPhysWriteBytes;
2860	STAMCOUNTER StatR3PhysRead;
2861	STAMCOUNTER StatR3PhysReadBytes;
2862	STAMCOUNTER StatR3PhysWrite;
2863	STAMCOUNTER StatR3PhysWriteBytes;
2864	STAMCOUNTER StatRCPhysRead;
2865	STAMCOUNTER StatRCPhysReadBytes;
2866	STAMCOUNTER StatRCPhysWrite;
2867	STAMCOUNTER StatRCPhysWriteBytes;
2868
2869	STAMCOUNTER StatRZPhysSimpleRead;
2870	STAMCOUNTER StatRZPhysSimpleReadBytes;
2871	STAMCOUNTER StatRZPhysSimpleWrite;
2872	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2873	STAMCOUNTER StatR3PhysSimpleRead;
2874	STAMCOUNTER StatR3PhysSimpleReadBytes;
2875	STAMCOUNTER StatR3PhysSimpleWrite;
2876	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2877	STAMCOUNTER StatRCPhysSimpleRead;
2878	STAMCOUNTER StatRCPhysSimpleReadBytes;
2879	STAMCOUNTER StatRCPhysSimpleWrite;
2880	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2881
2882	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2883	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2884	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2885	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2886	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2887	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2888	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2889
2890	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2891	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2892	/** pgmPhysIsValidLargePage profiling - R3 */
2893	STAMPROFILE StatR3IsValidLargePage;
2894	/** pgmPhysIsValidLargePage profiling - RZ*/
2895	STAMPROFILE StatRZIsValidLargePage;
2896
2897	STAMPROFILE StatChunkAging;
2898	STAMPROFILE StatChunkFindCandidate;
2899	STAMPROFILE StatChunkUnmap;
2900	STAMPROFILE StatChunkMap;
2901	} PGMSTATS;
2902	#endif /* VBOX_WITH_STATISTICS */
2903
2904
2905	/**
2906	* PGM Data (part of VM)
2907	*/
2908	typedef struct PGM
2909	{
2910	/** The zero page. */
2911	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2912	/** The MMIO placeholder page. */
2913	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2914
2915	/** @name The zero page (abPagePg).
2916	* @{ */
2917	/** The host physical address of the zero page. */
2918	RTHCPHYS HCPhysZeroPg;
2919	/** @}*/
2920
2921	/** @name The Invalid MMIO page (abMmioPg).
2922	* This page is filled with 0xfeedface.
2923	* @{ */
2924	/** The host physical address of the invalid MMIO page. */
2925	RTHCPHYS HCPhysMmioPg;
2926	/** The host pysical address of the invalid MMIO page plus all invalid
2927	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2928	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2929	RTHCPHYS HCPhysInvMmioPg;
2930	/** @} */
2931
2932	/** @cfgm{/RamPreAlloc, boolean, false}
2933	* Indicates whether the base RAM should all be allocated before starting
2934	* the VM (default), or if it should be allocated when first written to.
2935	*/
2936	bool fRamPreAlloc;
2937	#ifdef VBOX_WITH_PGM_NEM_MODE
2938	/** Set if we're operating in NEM memory mode.
2939	*
2940	* NEM mode implies that memory is allocated in big chunks for each RAM range
2941	* rather than on demand page by page. Memory is also not locked and PGM has
2942	* therefore no physical addresses for them. Page sharing is out of the
2943	* question. Ballooning depends on the native execution engine, but probably
2944	* pointless as well. */
2945	bool fNemMode;
2946	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2947	#else
2948	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2949	#endif
2950	/** Indicates whether write monitoring is currently in use.
2951	* This is used to prevent conflicts between live saving and page sharing
2952	* detection. */
2953	bool fPhysWriteMonitoringEngaged;
2954	/** Set if the CPU has less than 52-bit physical address width.
2955	* This is used */
2956	bool fLessThan52PhysicalAddressBits;
2957	/** Set when nested paging is active.
2958	* This is meant to save calls to HMIsNestedPagingActive and let the
2959	* compilers optimize the code better. Whether we use nested paging or
2960	* not is something we find out during VMM initialization and we won't
2961	* change this later on. */
2962	bool fNestedPaging;
2963	/** We're not in a state which permits writes to guest memory.
2964	* (Only used in strict builds.) */
2965	bool fNoMorePhysWrites;
2966	/** @cfgm{/PageFusionAllowed, boolean, false}
2967	* Whether page fusion is allowed. */
2968	bool fPageFusionAllowed;
2969	/** @cfgm{/PGM/PciPassThrough, boolean, false}
2970	* Whether PCI passthrough is enabled. */
2971	bool fPciPassthrough;
2972	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
2973	uint8_t cMmio2Regions;
2974	/** Restore original ROM page content when resetting after loading state.
2975	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
2976	* enables the VM to start using an updated ROM without requiring powering
2977	* down the VM, just rebooting or resetting it. */
2978	bool fRestoreRomPagesOnReset;
2979	/** Whether to automatically clear all RAM pages on reset. */
2980	bool fZeroRamPagesOnReset;
2981	/** Large page enabled flag. */
2982	bool fUseLargePages;
2983	/** Alignment padding. */
2984	#ifndef VBOX_WITH_PGM_NEM_MODE
2985	bool afAlignment3[1];
2986	#endif
2987	/** The host paging mode. (This is what SUPLib reports.) */
2988	SUPPAGINGMODE enmHostMode;
2989	bool afAlignment3b[2];
2990
2991	/** Generation ID for the RAM ranges. This member is incremented everytime
2992	* a RAM range is linked or unlinked. */
2993	uint32_t volatile idRamRangesGen;
2994
2995	/** Physical access handler type for ROM protection. */
2996	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
2997	/** Physical access handler type for MMIO2 dirty page tracing. */
2998	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
2999
3000	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3001	RTGCPHYS GCPhys4MBPSEMask;
3002	/** Mask containing the invalid bits of a guest physical address.
3003	* @remarks this does not stop at bit 52. */
3004	RTGCPHYS GCPhysInvAddrMask;
3005
3006
3007	/** RAM range TLB for R3. */
3008	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3009	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3010	* This is sorted by physical address and contains no overlapping ranges. */
3011	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3012	/** Root of the RAM range search tree for ring-3. */
3013	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3014	/** Shadow Page Pool - R3 Ptr. */
3015	R3PTRTYPE(PPGMPOOL) pPoolR3;
3016	/** Pointer to the list of ROM ranges - for R3.
3017	* This is sorted by physical address and contains no overlapping ranges. */
3018	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3019	/** Pointer to the list of MMIO2 ranges - for R3.
3020	* Registration order. */
3021	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3022	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3023	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3024
3025	/** RAM range TLB for R0. */
3026	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3027	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3028	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3029	/** Root of the RAM range search tree for ring-0. */
3030	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3031	/** Shadow Page Pool - R0 Ptr. */
3032	R0PTRTYPE(PPGMPOOL) pPoolR0;
3033	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3034	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3035	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3036	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3037
3038	/** Hack: Number of deprecated page mapping locks taken by the current lock
3039	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3040	uint32_t cDeprecatedPageLocks;
3041
3042	/** Registered physical access handler types. */
3043	uint32_t cPhysHandlerTypes;
3044	/** Physical access handler types.
3045	* Initialized to callback causing guru meditations and invalid enmKind. */
3046	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3047	/** Physical handler allocator, ring-3 edition. */
3048	#ifdef IN_RING3
3049	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3050	#else
3051	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3052	#endif
3053	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3054	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3055	/** Caching the last physical handler we looked. */
3056	uint32_t idxLastPhysHandler;
3057
3058	uint32_t au64Padding3[5];
3059
3060	/** PGM critical section.
3061	* This protects the physical, ram ranges, and the page flag updating (some of
3062	* it anyway).
3063	*/
3064	PDMCRITSECT CritSectX;
3065
3066	/**
3067	* Data associated with managing the ring-3 mappings of the allocation chunks.
3068	*/
3069	struct
3070	{
3071	/** The chunk mapping TLB. */
3072	PGMCHUNKR3MAPTLB Tlb;
3073	/** The chunk tree, ordered by chunk id. */
3074	R3PTRTYPE(PAVLU32NODECORE) pTree;
3075	#if HC_ARCH_BITS == 32
3076	uint32_t u32Alignment0;
3077	#endif
3078	/** The number of mapped chunks. */
3079	uint32_t c;
3080	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3081	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3082	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3083	uint32_t cMax;
3084	/** The current time. This is incremented whenever a chunk is inserted. */
3085	uint32_t iNow;
3086	/** Alignment padding. */
3087	uint32_t au32Alignment1[3];
3088	} ChunkR3Map;
3089
3090	/** The page mapping TLB for ring-3. */
3091	PGMPAGER3MAPTLB PhysTlbR3;
3092	/** The page mapping TLB for ring-0. */
3093	PGMPAGER0MAPTLB PhysTlbR0;
3094
3095	/** The number of handy pages. */
3096	uint32_t cHandyPages;
3097
3098	/** The number of large handy pages. */
3099	uint32_t cLargeHandyPages;
3100
3101	/**
3102	* Array of handy pages.
3103	*
3104	* This array is used in a two way communication between pgmPhysAllocPage
3105	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3106	* an intermediary.
3107	*
3108	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3109	* (The current size of 32 pages, means 128 KB of handy memory.)
3110	*/
3111	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3112
3113	/**
3114	* Array of large handy pages. (currently size 1)
3115	*
3116	* This array is used in a two way communication between pgmPhysAllocLargePage
3117	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3118	* an intermediary.
3119	*/
3120	GMMPAGEDESC aLargeHandyPage[1];
3121	/** When to try allocate large pages again after a failure. */
3122	uint64_t nsLargePageRetry;
3123	/** Number of repeated long allocation times. */
3124	uint32_t cLargePageLongAllocRepeats;
3125	uint32_t uPadding5;
3126
3127	/**
3128	* Live save data.
3129	*/
3130	struct
3131	{
3132	/** Per type statistics. */
3133	struct
3134	{
3135	/** The number of ready pages. */
3136	uint32_t cReadyPages;
3137	/** The number of dirty pages. */
3138	uint32_t cDirtyPages;
3139	/** The number of ready zero pages. */
3140	uint32_t cZeroPages;
3141	/** The number of write monitored pages. */
3142	uint32_t cMonitoredPages;
3143	} Rom,
3144	Mmio2,
3145	Ram;
3146	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3147	uint32_t cIgnoredPages;
3148	/** Indicates that a live save operation is active. */
3149	bool fActive;
3150	/** Padding. */
3151	bool afReserved[2];
3152	/** The next history index. */
3153	uint8_t iDirtyPagesHistory;
3154	/** History of the total amount of dirty pages. */
3155	uint32_t acDirtyPagesHistory[64];
3156	/** Short term dirty page average. */
3157	uint32_t cDirtyPagesShort;
3158	/** Long term dirty page average. */
3159	uint32_t cDirtyPagesLong;
3160	/** The number of saved pages. This is used to get some kind of estimate of the
3161	* link speed so we can decide when we're done. It is reset after the first
3162	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3163	* zero pages. */
3164	uint64_t cSavedPages;
3165	/** The nanosecond timestamp when cSavedPages was 0. */
3166	uint64_t uSaveStartNS;
3167	/** Pages per second (for statistics). */
3168	uint32_t cPagesPerSecond;
3169	uint32_t cAlignment;
3170	} LiveSave;
3171
3172	/** @name Error injection.
3173	* @{ */
3174	/** Inject handy page allocation errors pretending we're completely out of
3175	* memory. */
3176	bool volatile fErrInjHandyPages;
3177	/** Padding. */
3178	bool afReserved[3];
3179	/** @} */
3180
3181	/** @name Release Statistics
3182	* @{ */
3183	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3184	uint32_t cPrivatePages; /*< The number of private pages. /
3185	uint32_t cSharedPages; /*< The number of shared pages. /
3186	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3187	uint32_t cZeroPages; /*< The number of zero backed pages. /
3188	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3189	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3190	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3191	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3192	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3193	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3194	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3195	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3196	uint32_t cLargePages; /*< The number of large pages. /
3197	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3198	/* uint32_t aAlignment4[1]; */
3199
3200	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3201	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3202	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3203	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3204	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3205	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3206	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3207	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3208
3209	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3210
3211	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3212	/** @} */
3213
3214	#ifdef VBOX_WITH_STATISTICS
3215	/** These are optional statistics that used to be on the hyper heap. */
3216	PGMSTATS Stats;
3217	#endif
3218	} PGM;
3219	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3220	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3221	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3222	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3223	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3224	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3225	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3226	#endif /* !IN_TSTVMSTRUCTGC */
3227	/** Pointer to the PGM instance data. */
3228	typedef PGM *PPGM;
3229
3230
3231	#ifdef VBOX_WITH_STATISTICS
3232	/**
3233	* Per CPU statistis for PGM (used to be on the heap).
3234	*/
3235	typedef struct PGMCPUSTATS
3236	{
3237	/* Common */
3238	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3239	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3240
3241	/* R0 only: */
3242	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3243	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3244
3245	/* RZ only: */
3246	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3247	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3248	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3249	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3250	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3251	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3252	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3253	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3254	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3255	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3256	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3257	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3258	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3259	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3260	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3261	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3262	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3263	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3264	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3265	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3266	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3267	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3268	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3269	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3270	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3271	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3272	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3273	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3274	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3275	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3276	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3277	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3278	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3279	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3280	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3281	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3282	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3283	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3284	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3285	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3286	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3287	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3288	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3289	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3290	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3291	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3292	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3293	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3294	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3295	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3296	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3297	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3298	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3299	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3300	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3301	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3302	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3303	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3304	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3305	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3306	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3307	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3308	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3309	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3310	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3311	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3312	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3313	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3314	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3315	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3316
3317	/* HC - R3 and (maybe) R0: */
3318
3319	/* RZ & R3: */
3320	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3321	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3322	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3323	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3324	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3325	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3326	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3327	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3328	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3329	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3330	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3331	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3332	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3333	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3334	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3335	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3336	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3337	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3338	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3339	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3340	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3341	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3342	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3343	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3344	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3345	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3346	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3347	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3348	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3349	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3350	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3351	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3352	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3353	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3354	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3355	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3356	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3357	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3358	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3359	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3360	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3361	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3362	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3363	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3364	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3365	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3366	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3367
3368	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3369	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3370	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3371	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3372	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3373	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3374	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3375	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3376	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3377	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3378	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3379	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3380	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3381	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3382	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3383	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3384	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3385	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3386	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3387	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3388	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3389	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3390	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3391	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3392	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3393	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3394	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3395	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3396	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3397	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3398	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3399	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3400	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3401	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3402	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3403	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3404	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3405	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3406	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3407	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3408	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3409	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3410	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3411	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3412	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3413	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3414	} PGMCPUSTATS;
3415	#endif /* VBOX_WITH_STATISTICS */
3416
3417
3418	/**
3419	* PGMCPU Data (part of VMCPU).
3420	*/
3421	typedef struct PGMCPU
3422	{
3423	/** A20 gate mask.
3424	* Our current approach to A20 emulation is to let REM do it and don't bother
3425	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3426	* But whould need arrise, we'll subject physical addresses to this mask. */
3427	RTGCPHYS GCPhysA20Mask;
3428	/** A20 gate state - boolean! */
3429	bool fA20Enabled;
3430	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3431	bool fNoExecuteEnabled;
3432	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3433	* active. */
3434	bool fPaePdpesAndCr3MappedR3;
3435	bool fPaePdpesAndCr3MappedR0;
3436
3437	/** What needs syncing (PGM_SYNC_*).
3438	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3439	* PGMFlushTLB, and PGMR3Load. */
3440	uint32_t fSyncFlags;
3441
3442	/** The shadow paging mode. */
3443	PGMMODE enmShadowMode;
3444	/** The guest paging mode. */
3445	PGMMODE enmGuestMode;
3446	/** The guest second level address translation mode. */
3447	PGMSLAT enmGuestSlatMode;
3448	/** Guest mode data table index (PGM_TYPE_XXX). */
3449	uint8_t volatile idxGuestModeData;
3450	/** Shadow mode data table index (PGM_TYPE_XXX). */
3451	uint8_t volatile idxShadowModeData;
3452	/** Both mode data table index (complicated). */
3453	uint8_t volatile idxBothModeData;
3454	/** Alignment padding. */
3455	uint8_t abPadding[1];
3456
3457	/** The guest CR3.
3458	* When SLAT is active, this is the translated physical address.
3459	* When SLAT is inactive, this is the physical address in CR3. */
3460	RTGCPHYS GCPhysCR3;
3461
3462	/** The nested-guest CR3.
3463	* When SLAT is active, this is CR3 prior to translation.
3464	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3465	RTGCPHYS GCPhysNstGstCR3;
3466
3467	/** The cached guest CR3 when it has been mapped in PAE mode.
3468	* This allows us to skip remapping the CR3 and PAE PDPEs
3469	* (in PGMFlushTLB or similar) when it was already done as
3470	* part of MOV CRx instruction emulation.
3471	*/
3472	RTGCPHYS GCPhysPaeCR3;
3473
3474	/** @name 32-bit Guest Paging.
3475	* @{ */
3476	/** The guest's page directory, R3 pointer. */
3477	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3478	/** The guest's page directory, R0 pointer. */
3479	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3480	/** Mask containing the MBZ bits of a big page PDE. */
3481	uint32_t fGst32BitMbzBigPdeMask;
3482	/** Set if the page size extension (PSE) is enabled. */
3483	bool fGst32BitPageSizeExtension;
3484	/** Alignment padding. */
3485	bool afAlignment2[3];
3486	/** @} */
3487
3488	/** @name PAE Guest Paging.
3489	* @{ */
3490	/** The guest's page directory pointer table, R3 pointer. */
3491	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3492	/** The guest's page directory pointer table, R0 pointer. */
3493	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3494
3495	/** The guest's page directories, R3 pointers.
3496	* These are individual pointers and don't have to be adjacent.
3497	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3498	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3499	/** The guest's page directories, R0 pointers.
3500	* Same restrictions as apGstPaePDsR3. */
3501	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3502	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3503	RTGCPHYS aGCPhysGstPaePDs[4];
3504	/** The physical addresses of the monitored guest page directories (PAE). */
3505	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3506	/** Mask containing the MBZ PTE bits. */
3507	uint64_t fGstPaeMbzPteMask;
3508	/** Mask containing the MBZ PDE bits. */
3509	uint64_t fGstPaeMbzPdeMask;
3510	/** Mask containing the MBZ big page PDE bits. */
3511	uint64_t fGstPaeMbzBigPdeMask;
3512	/** Mask containing the MBZ PDPE bits. */
3513	uint64_t fGstPaeMbzPdpeMask;
3514	/** @} */
3515
3516	/** @name AMD64 Guest Paging.
3517	* @{ */
3518	/** The guest's page directory pointer table, R3 pointer. */
3519	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3520	/** The guest's page directory pointer table, R0 pointer. */
3521	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3522	/** Mask containing the MBZ PTE bits. */
3523	uint64_t fGstAmd64MbzPteMask;
3524	/** Mask containing the MBZ PDE bits. */
3525	uint64_t fGstAmd64MbzPdeMask;
3526	/** Mask containing the MBZ big page PDE bits. */
3527	uint64_t fGstAmd64MbzBigPdeMask;
3528	/** Mask containing the MBZ PDPE bits. */
3529	uint64_t fGstAmd64MbzPdpeMask;
3530	/** Mask containing the MBZ big page PDPE bits. */
3531	uint64_t fGstAmd64MbzBigPdpeMask;
3532	/** Mask containing the MBZ PML4E bits. */
3533	uint64_t fGstAmd64MbzPml4eMask;
3534	/** Mask containing the PDPE bits that we shadow. */
3535	uint64_t fGstAmd64ShadowedPdpeMask;
3536	/** Mask containing the PML4E bits that we shadow. */
3537	uint64_t fGstAmd64ShadowedPml4eMask;
3538	/** @} */
3539
3540	/** @name PAE and AMD64 Guest Paging.
3541	* @{ */
3542	/** Mask containing the PTE bits that we shadow. */
3543	uint64_t fGst64ShadowedPteMask;
3544	/** Mask containing the PDE bits that we shadow. */
3545	uint64_t fGst64ShadowedPdeMask;
3546	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3547	uint64_t fGst64ShadowedBigPdeMask;
3548	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3549	uint64_t fGst64ShadowedBigPde4PteMask;
3550	/** @} */
3551
3552	/** @name EPT Guest Paging.
3553	* @{ */
3554	/** The guest's EPT PML4 table, R3 pointer. */
3555	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3556	/** The guest's EPT PML4 table, R0 pointer. */
3557	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3558	/** The guest's EPT pointer (copy of virtual VMCS). */
3559	uint64_t uEptPtr;
3560	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3561	* change through the lifetime of the VM. */
3562	uint64_t uEptVpidCapMsr;
3563	/** Mask containing the MBZ PTE bits. */
3564	uint64_t fGstEptMbzPteMask;
3565	/** Mask containing the MBZ PDE bits. */
3566	uint64_t fGstEptMbzPdeMask;
3567	/** Mask containing the MBZ big page (2M) PDE bits. */
3568	uint64_t fGstEptMbzBigPdeMask;
3569	/** Mask containing the MBZ PDPTE bits. */
3570	uint64_t fGstEptMbzPdpteMask;
3571	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3572	uint64_t fGstEptMbzBigPdpteMask;
3573	/** Mask containing the MBZ PML4E bits. */
3574	uint64_t fGstEptMbzPml4eMask;
3575	/** Mask to determine whether an entry is present. */
3576	uint64_t fGstEptPresentMask;
3577
3578	/** Mask containing the EPT PTE bits we shadow. */
3579	uint64_t fGstEptShadowedPteMask;
3580	/** Mask containing the EPT PDE bits we shadow. */
3581	uint64_t fGstEptShadowedPdeMask;
3582	/** Mask containing the EPT PDPTE bits we shadow. */
3583	uint64_t fGstEptShadowedPdpteMask;
3584	/** Mask containing the EPT PML4E bits we shadow. */
3585	uint64_t fGstEptShadowedPml4eMask;
3586	/** @} */
3587
3588	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3589	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3590	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3591	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3592
3593	/** For saving stack space, the disassembler state is allocated here instead of
3594	* on the stack. */
3595	DISCPUSTATE DisState;
3596
3597	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3598	uint64_t cNetwareWp0Hacks;
3599
3600	/** Count the number of pgm pool access handler calls. */
3601	uint64_t cPoolAccessHandler;
3602
3603	/** @name Release Statistics
3604	* @{ */
3605	/** The number of times the guest has switched mode since last reset or statistics reset. */
3606	STAMCOUNTER cGuestModeChanges;
3607	/** The number of times the guest has switched mode since last reset or statistics reset. */
3608	STAMCOUNTER cA20Changes;
3609	/** @} */
3610
3611	#ifdef VBOX_WITH_STATISTICS
3612	/** These are statistics that used to be on the hyper heap. */
3613	PGMCPUSTATS Stats;
3614	#endif
3615	} PGMCPU;
3616	/** Pointer to the per-cpu PGM data. */
3617	typedef PGMCPU *PPGMCPU;
3618
3619
3620	/** @name PGM::fSyncFlags Flags
3621	* @note Was part of saved state a long time ago.
3622	* @{
3623	*/
3624	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3625	/** Always sync CR3. */
3626	#define PGM_SYNC_ALWAYS RT_BIT(1)
3627	/** Check guest mapping in SyncCR3. */
3628	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3629	/** Clear the page pool (a light weight flush). */
3630	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3631	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3632	/** @} */
3633
3634
3635	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3636
3637	/**
3638	* PGM GVMCPU instance data.
3639	*/
3640	typedef struct PGMR0PERVCPU
3641	{
3642	# ifdef VBOX_WITH_STATISTICS
3643	/** R0: Which statistic this \#PF should be attributed to. */
3644	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3645	# endif
3646	uint64_t u64Dummy;
3647	} PGMR0PERVCPU;
3648
3649
3650	/**
3651	* PGM GVM instance data.
3652	*/
3653	typedef struct PGMR0PERVM
3654	{
3655	/** @name PGM Pool related stuff.
3656	* @{ */
3657	/** Critical section for serializing pool growth. */
3658	RTCRITSECT PoolGrowCritSect;
3659	/** The memory objects for the pool pages. */
3660	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3661	/** The ring-3 mapping objects for the pool pages. */
3662	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3663	/** @} */
3664
3665	/** Physical access handler types for ring-0.
3666	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3667	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3668	/** Physical handler allocator, ring-3 edition. */
3669	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3670	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3671	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3672	/** The allocation object for the physical access handler tree. */
3673	RTR0MEMOBJ hPhysHandlerMemObj;
3674	/** The ring-3 mapping object for the physicall access handler tree. */
3675	RTR0MEMOBJ hPhysHandlerMapObj;
3676	} PGMR0PERVM;
3677
3678	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3679
3680	RT_C_DECLS_BEGIN
3681
3682	#if defined(VBOX_STRICT)
3683	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3684	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3685	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3686	#else
3687	int pgmLock(PVMCC pVM, bool fVoid);
3688	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3689	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3690	#endif
3691	void pgmUnlock(PVMCC pVM);
3692	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3693	/**
3694	* Asserts that the caller owns the PDM lock.
3695	* This is the internal variant of PGMIsLockOwner.
3696	* @param a_pVM Pointer to the VM.
3697	*/
3698	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3699	/**
3700	* Asserts that the caller owns the PDM lock.
3701	* This is the internal variant of PGMIsLockOwner.
3702	* @param a_pVM Pointer to the VM.
3703	* @param a_pVCpu The current CPU handle.
3704	*/
3705	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3706
3707	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3708	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3709	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3710	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3711	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3712	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3713	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3714	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3715	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3716	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam, bool fDoAccounting);
3717	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3718	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3719	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3720	#ifndef IN_RING3
3721	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3722	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3723	#endif
3724
3725	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3726
3727	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3728	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3729	#ifdef IN_RING0
3730	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3731	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3732	#endif
3733	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3734	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3735	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3736	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3737	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3738	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3739	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3740	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3741	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3742	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3743	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3744	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3745	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3746	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3747	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3748	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3749	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3750	#ifndef IN_RING3
3751	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3752	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3753	#endif
3754	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3755	PGMPAGETYPE enmNewType);
3756	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3757	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3758	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3759	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3760	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3761	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3762	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3763	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3764	#ifdef VBOX_WITH_NATIVE_NEM
3765	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3766	#endif
3767
3768	#ifdef IN_RING3
3769	void pgmR3PhysRelinkRamRanges(PVM pVM);
3770	int pgmR3PhysRamPreAllocate(PVM pVM);
3771	int pgmR3PhysRamReset(PVM pVM);
3772	int pgmR3PhysRomReset(PVM pVM);
3773	int pgmR3PhysRamZeroAll(PVM pVM);
3774	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3775	int pgmR3PhysRamTerm(PVM pVM);
3776	void pgmR3PhysRomTerm(PVM pVM);
3777	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3778
3779	int pgmR3PoolInit(PVM pVM);
3780	void pgmR3PoolRelocate(PVM pVM);
3781	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3782	void pgmR3PoolReset(PVM pVM);
3783	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3784	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3785	void pgmR3PoolWriteProtectPages(PVM pVM);
3786
3787	#endif /* IN_RING3 */
3788	#ifdef IN_RING0
3789	int pgmR0PoolInitVM(PGVM pGVM);
3790	#endif
3791	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3792	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3793	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3794	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3795	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3796	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3797	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3798	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3799	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3800	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3801	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3802	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3803	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3804	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3805	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3806	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3807	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3808	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3809	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3810	#ifndef IN_RING3
3811	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3812	#endif
3813
3814	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3815	void pgmPoolResetDirtyPages(PVMCC pVM);
3816	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3817
3818	/** Gets the ring-0 pointer for the given pool page. */
3819	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3820	{
3821	#ifdef IN_RING3
3822	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3823	# ifdef VBOX_STRICT
3824	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3825	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3826	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3827	# endif
3828	return pPool->pPoolR0 + offPage;
3829	#else
3830	RT_NOREF(pPool);
3831	return pPage;
3832	#endif
3833	}
3834
3835	/** Gets the ring-3 pointer for the given pool page. */
3836	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3837	{
3838	#ifdef IN_RING3
3839	RT_NOREF(pPool);
3840	return pPage;
3841	#else
3842	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3843	# ifdef VBOX_STRICT
3844	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3845	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3846	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3847	# endif
3848	return pPool->pPoolR3 + offPage;
3849	#endif
3850	}
3851
3852	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3853	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3854	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3855
3856	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3857	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3858	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3859
3860	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3861	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3862	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3863	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3864	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3865	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3866	#endif
3867	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3868	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3869
3870	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3871	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3872	FNDBGCCMD pgmR3CmdShowSharedModules;
3873	# endif
3874
3875	void pgmLogState(PVM pVM);
3876
3877	RT_C_DECLS_END
3878
3879	/** @} */
3880
3881	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3882

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 96980

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