SELMInline.h@ 60816

Last change on this file since 60816 was 58123, checked in by vboxsync, 9 years ago
VMM: Made @param pVCpu more uniform and to the point.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 10.5 KB

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1	/* $Id: SELMInline.h 58123 2015-10-08 18:09:45Z vboxsync $ */
2	/** @file
3	* SELM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___SELMInline_h
19	#define ___SELMInline_h
20
21	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
22
23	/**
24	* Checks if a shadow descriptor table entry is good for the given segment
25	* register.
26	*
27	* @returns @c true if good, @c false if not.
28	* @param pSReg The segment register.
29	* @param pShwDesc The shadow descriptor table entry.
30	* @param iSReg The segment register index (X86_SREG_XXX).
31	* @param uCpl The CPL.
32	*/
33	DECLINLINE(bool) selmIsShwDescGoodForSReg(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg, uint32_t uCpl)
34	{
35	/*
36	* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
37	*/
38
39	if (!pShwDesc->Gen.u1Present)
40	{
41	Log(("selmIsShwDescGoodForSReg: Not present\n"));
42	return false;
43	}
44
45	if (!pShwDesc->Gen.u1DescType)
46	{
47	Log(("selmIsShwDescGoodForSReg: System descriptor\n"));
48	return false;
49	}
50
51	if (iSReg == X86_SREG_SS)
52	{
53	if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
54	{
55	Log(("selmIsShwDescGoodForSReg: Stack must be writable\n"));
56	return false;
57	}
58	if (uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
59	{
60	Log(("selmIsShwDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available));
61	return false;
62	}
63	}
64	else
65	{
66	if (iSReg == X86_SREG_CS)
67	{
68	if (!(pShwDesc->Gen.u4Type & X86_SEL_TYPE_CODE))
69	{
70	Log(("selmIsShwDescGoodForSReg: CS needs code segment\n"));
71	return false;
72	}
73	}
74	else if ((pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
75	{
76	Log(("selmIsShwDescGoodForSReg: iSReg=%u execute only\n", iSReg));
77	return false;
78	}
79
80	if ( (pShwDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
81	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF)
82	&& ( ( (pSReg->Sel & X86_SEL_RPL) > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available
83	&& (pSReg->Sel & X86_SEL_RPL) != pShwDesc->Gen.u1Available )
84	\|\| uCpl > (unsigned)pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available ) )
85	{
86	Log(("selmIsShwDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u\n", iSReg,
87	pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available, uCpl, pSReg->Sel & X86_SEL_RPL));
88	return false;
89	}
90	}
91
92	return true;
93	}
94
95
96	/**
97	* Checks if a guest descriptor table entry is good for the given segment
98	* register.
99	*
100	* @returns @c true if good, @c false if not.
101	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
102	* @param pSReg The segment register.
103	* @param pGstDesc The guest descriptor table entry.
104	* @param iSReg The segment register index (X86_SREG_XXX).
105	* @param uCpl The CPL.
106	*/
107	DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl)
108	{
109	/*
110	* See iemMiscValidateNewSS, iemCImpl_LoadSReg and intel+amd manuals.
111	*/
112
113	if (!pGstDesc->Gen.u1Present)
114	{
115	Log(("selmIsGstDescGoodForSReg: Not present\n"));
116	return false;
117	}
118
119	if (!pGstDesc->Gen.u1DescType)
120	{
121	Log(("selmIsGstDescGoodForSReg: System descriptor\n"));
122	return false;
123	}
124
125	if (iSReg == X86_SREG_SS)
126	{
127	if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE)) != X86_SEL_TYPE_WRITE)
128	{
129	Log(("selmIsGstDescGoodForSReg: Stack must be writable\n"));
130	return false;
131	}
132	if (uCpl > pGstDesc->Gen.u2Dpl)
133	{
134	Log(("selmIsGstDescGoodForSReg: CPL(%d) > DPL(%d)\n", uCpl, pGstDesc->Gen.u2Dpl));
135	return false;
136	}
137	}
138	else
139	{
140	if (iSReg == X86_SREG_CS)
141	{
142	if (!(pGstDesc->Gen.u4Type & X86_SEL_TYPE_CODE))
143	{
144	Log(("selmIsGstDescGoodForSReg: CS needs code segment\n"));
145	return false;
146	}
147	}
148	else if ((pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
149	{
150	Log(("selmIsGstDescGoodForSReg: iSReg=%u execute only\n", iSReg));
151	return false;
152	}
153
154	if ( (pGstDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
155	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF)
156	&& ( ( (pSReg->Sel & X86_SEL_RPL) > pGstDesc->Gen.u2Dpl
157	&& ( (pSReg->Sel & X86_SEL_RPL) != 1
158	\|\| !CPUMIsGuestInRawMode(pVCpu) ) )
159	\|\| uCpl > (unsigned)pGstDesc->Gen.u2Dpl
160	)
161	)
162	{
163	Log(("selmIsGstDescGoodForSReg: iSReg=%u DPL=%u CPL=%u RPL=%u InRawMode=%u\n", iSReg,
164	pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu)));
165	return false;
166	}
167	}
168
169	return true;
170	}
171
172
173	/**
174	* Converts a guest GDT or LDT entry to a shadow table entry.
175	*
176	* @param pVM The cross context VM structure.
177	* @param pDesc Guest entry on input, shadow entry on return.
178	*/
179	DECL_FORCE_INLINE(void) selmGuestToShadowDesc(PVM pVM, PX86DESC pDesc)
180	{
181	/*
182	* Code and data selectors are generally 1:1, with the
183	* 'little' adjustment we do for DPL 0 selectors.
184	*/
185	if (pDesc->Gen.u1DescType)
186	{
187	/*
188	* Hack for A-bit against Trap E on read-only GDT.
189	*/
190	/** @todo Fix this by loading ds and cs before turning off WP. */
191	pDesc->Gen.u4Type \|= X86_SEL_TYPE_ACCESSED;
192
193	/*
194	* All DPL 0 code and data segments are squeezed into DPL 1.
195	*
196	* We're skipping conforming segments here because those
197	* cannot give us any trouble.
198	*/
199	if ( pDesc->Gen.u2Dpl == 0
200	&& (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
201	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
202	{
203	pDesc->Gen.u2Dpl = 1;
204	pDesc->Gen.u1Available = 1;
205	}
206	# ifdef VBOX_WITH_RAW_RING1
207	else if ( pDesc->Gen.u2Dpl == 1
208	&& EMIsRawRing1Enabled(pVM)
209	&& (pDesc->Gen.u4Type & (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF))
210	!= (X86_SEL_TYPE_CODE \| X86_SEL_TYPE_CONF) )
211	{
212	pDesc->Gen.u2Dpl = 2;
213	pDesc->Gen.u1Available = 1;
214	}
215	# endif
216	else
217	pDesc->Gen.u1Available = 0;
218	}
219	else
220	{
221	/*
222	* System type selectors are marked not present.
223	* Recompiler or special handling is required for these.
224	*/
225	/** @todo what about interrupt gates and rawr0? */
226	pDesc->Gen.u1Present = 0;
227	}
228	}
229
230
231	/**
232	* Checks if a segment register is stale given the shadow descriptor table
233	* entry.
234	*
235	* @returns @c true if stale, @c false if not.
236	* @param pSReg The segment register.
237	* @param pShwDesc The shadow descriptor entry.
238	* @param iSReg The segment register number (X86_SREG_XXX).
239	*/
240	DECLINLINE(bool) selmIsSRegStale32(PCCPUMSELREG pSReg, PCX86DESC pShwDesc, uint32_t iSReg)
241	{
242	if ( pSReg->Attr.n.u1Present != pShwDesc->Gen.u1Present
243	\|\| pSReg->Attr.n.u4Type != pShwDesc->Gen.u4Type
244	\|\| pSReg->Attr.n.u1DescType != pShwDesc->Gen.u1DescType
245	\|\| pSReg->Attr.n.u1DefBig != pShwDesc->Gen.u1DefBig
246	\|\| pSReg->Attr.n.u1Granularity != pShwDesc->Gen.u1Granularity
247	\|\| pSReg->Attr.n.u2Dpl != pShwDesc->Gen.u2Dpl - pShwDesc->Gen.u1Available)
248	{
249	Log(("selmIsSRegStale32: Attributes changed (%#x -> %#x)\n", pSReg->Attr.u, X86DESC_GET_HID_ATTR(pShwDesc)));
250	return true;
251	}
252
253	if (pSReg->u64Base != X86DESC_BASE(pShwDesc))
254	{
255	Log(("selmIsSRegStale32: base changed (%#llx -> %#x)\n", pSReg->u64Base, X86DESC_BASE(pShwDesc)));
256	return true;
257	}
258
259	if (pSReg->u32Limit != X86DESC_LIMIT_G(pShwDesc))
260	{
261	Log(("selmIsSRegStale32: limit changed (%#x -> %#x)\n", pSReg->u32Limit, X86DESC_LIMIT_G(pShwDesc)));
262	return true;
263	}
264
265	return false;
266	}
267
268
269	/**
270	* Loads the hidden bits of a selector register from a shadow descriptor table
271	* entry.
272	*
273	* @param pSReg The segment register in question.
274	* @param pShwDesc The shadow descriptor table entry.
275	*/
276	DECLINLINE(void) selmLoadHiddenSRegFromShadowDesc(PCPUMSELREG pSReg, PCX86DESC pShwDesc)
277	{
278	pSReg->Attr.u = X86DESC_GET_HID_ATTR(pShwDesc);
279	pSReg->Attr.n.u2Dpl -= pSReg->Attr.n.u1Available;
280	Assert(pSReg->Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
281	pSReg->u32Limit = X86DESC_LIMIT_G(pShwDesc);
282	pSReg->u64Base = X86DESC_BASE(pShwDesc);
283	pSReg->ValidSel = pSReg->Sel;
284	/** @todo VBOX_WITH_RAW_RING1 */
285	if (pSReg->Attr.n.u1Available)
286	pSReg->ValidSel &= ~(RTSEL)1;
287	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
288	}
289
290
291	/**
292	* Loads the hidden bits of a selector register from a guest descriptor table
293	* entry.
294	*
295	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
296	* @param pSReg The segment register in question.
297	* @param pGstDesc The guest descriptor table entry.
298	*/
299	DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc)
300	{
301	pSReg->Attr.u = X86DESC_GET_HID_ATTR(pGstDesc);
302	pSReg->Attr.n.u4Type \|= X86_SEL_TYPE_ACCESSED;
303	pSReg->u32Limit = X86DESC_LIMIT_G(pGstDesc);
304	pSReg->u64Base = X86DESC_BASE(pGstDesc);
305	pSReg->ValidSel = pSReg->Sel;
306	/** @todo VBOX_WITH_RAW_RING1 */
307	if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu))
308	pSReg->ValidSel &= ~(RTSEL)1;
309	pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
310	}
311
312	#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
313
314	/** @} */
315
316	#endif

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source: vbox/trunk/src/VBox/VMM/include/SELMInline.h@ 60816

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