InstructionTestGen.py@ 46731

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1	#!/usr/bin/env python
2	# -- coding: utf-8 --
3	# $Id: InstructionTestGen.py 46731 2013-06-22 00:34:46Z vboxsync $
4
5	"""
6	Instruction Test Generator.
7	"""
8
9	from __future__ import print_function;
10
11	__copyright__ = \
12	"""
13	Copyright (C) 2012-2013 Oracle Corporation
14
15	Oracle Corporation confidential
16	All rights reserved
17	"""
18	__version__ = "$Revision: 46731 $";
19
20
21	# Standard python imports.
22	import io;
23	import os;
24	from optparse import OptionParser
25	import random;
26	import sys;
27
28
29	## @name Exit codes
30	## @{
31	RTEXITCODE_SUCCESS = 0;
32	RTEXITCODE_SYNTAX = 2;
33	## @}
34
35	## @name Various C macros we're used to.
36	## @{
37	UINT8_MAX = 0xff
38	UINT16_MAX = 0xffff
39	UINT32_MAX = 0xffffffff
40	UINT64_MAX = 0xffffffffffffffff
41	def RT_BIT_32(iBit): # pylint: disable=C0103
42	""" 32-bit one bit mask. """
43	return 1 << iBit;
44	def RT_BIT_64(iBit): # pylint: disable=C0103
45	""" 64-bit one bit mask. """
46	return 1 << iBit;
47	## @}
48
49
50	## @name Misc
51	## @{
52
53	def convU32ToSigned(u32):
54	""" Converts a 32-bit unsigned value to 32-bit signed. """
55	if u32 < 0x80000000:
56	return u32;
57	return u32 - UINT32_MAX - 1;
58
59	## @}
60
61
62	## @name ModR/M
63	## @{
64	X86_MODRM_RM_MASK = 0x07;
65	X86_MODRM_REG_MASK = 0x38;
66	X86_MODRM_REG_SMASK = 0x07;
67	X86_MODRM_REG_SHIFT = 3;
68	X86_MODRM_MOD_MASK = 0xc0;
69	X86_MODRM_MOD_SMASK = 0x03;
70	X86_MODRM_MOD_SHIFT = 6;
71	## @}
72
73	## @name SIB
74	## @{
75	X86_SIB_BASE_MASK = 0x07;
76	X86_SIB_INDEX_MASK = 0x38;
77	X86_SIB_INDEX_SMASK = 0x07;
78	X86_SIB_INDEX_SHIFT = 3;
79	X86_SIB_SCALE_MASK = 0xc0;
80	X86_SIB_SCALE_SMASK = 0x03;
81	X86_SIB_SCALE_SHIFT = 6;
82	## @}
83
84	## @name PRefixes
85	## @
86	X86_OP_PRF_CS = 0x2e;
87	X86_OP_PRF_SS = 0x36;
88	X86_OP_PRF_DS = 0x3e;
89	X86_OP_PRF_ES = 0x26;
90	X86_OP_PRF_FS = 0x64;
91	X86_OP_PRF_GS = 0x65;
92	X86_OP_PRF_SIZE_OP = 0x66;
93	X86_OP_PRF_SIZE_ADDR = 0x67;
94	X86_OP_PRF_LOCK = 0xf0;
95	X86_OP_PRF_REPZ = 0xf2;
96	X86_OP_PRF_REPNZ = 0xf3;
97	X86_OP_REX_B = 0x41;
98	X86_OP_REX_X = 0x42;
99	X86_OP_REX_R = 0x44;
100	X86_OP_REX_W = 0x48;
101	## @}
102
103
104	## @name Register names.
105	## @{
106	g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
107	g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
108	g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',
109	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
110	g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',
111	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
112	g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',
113	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
114	g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',
115	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
116	g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ah', 'dh', 'bh');
117	g_asGRegs8_64 = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil', # pylint: disable=C0103
118	'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b');
119	## @}
120
121
122	## @name Random
123	## @{
124	g_oMyRand = random.SystemRandom()
125	def randU16():
126	""" Unsigned 16-bit random number. """
127	return g_oMyRand.getrandbits(16);
128
129	def randU32():
130	""" Unsigned 32-bit random number. """
131	return g_oMyRand.getrandbits(32);
132
133	def randU64():
134	""" Unsigned 64-bit random number. """
135	return g_oMyRand.getrandbits(64);
136
137	def randUxx(cBits):
138	""" Unsigned 8-, 16-, 32-, or 64-bit random number. """
139	return g_oMyRand.getrandbits(cBits);
140
141	def randUxxList(cBits, cElements):
142	""" List of nsigned 8-, 16-, 32-, or 64-bit random numbers. """
143	return [randUxx(cBits) for _ in range(cElements)];
144	## @}
145
146
147
148
149	## @name Instruction Emitter Helpers
150	## @{
151
152	def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):
153	"""
154	Calculates a rex prefix if neccessary given the two registers
155	and optional rex size prefixes.
156	Returns an empty array if not necessary.
157	"""
158	bRex = bOtherRexPrefixes;
159	if iReg >= 8:
160	bRex = bRex \| X86_OP_REX_R;
161	if iRm >= 8:
162	bRex = bRex \| X86_OP_REX_B;
163	if bRex == 0:
164	return [];
165	return [bRex,];
166
167	def calcModRmForTwoRegs(iReg, iRm):
168	"""
169	Calculate the RM byte for two registers.
170	Returns an array with one byte in it.
171	"""
172	bRm = (0x3 << X86_MODRM_MOD_SHIFT) \
173	\| ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \
174	\| (iRm & X86_MODRM_RM_MASK);
175	return [bRm,];
176
177	## @}
178
179
180	class TargetEnv(object):
181	"""
182	Target Runtime Environment.
183	"""
184
185	## @name CPU Modes
186	## @{
187	ksCpuMode_Real = 'real';
188	ksCpuMode_Protect = 'prot';
189	ksCpuMode_Paged = 'paged';
190	ksCpuMode_Long = 'long';
191	ksCpuMode_V86 = 'v86';
192	## @}
193
194	## @name Instruction set.
195	## @{
196	ksInstrSet_16 = '16';
197	ksInstrSet_32 = '32';
198	ksInstrSet_64 = '64';
199	## @}
200
201	def __init__(self, sName,
202	sInstrSet = ksInstrSet_32,
203	sCpuMode = ksCpuMode_Paged,
204	iRing = 3,
205	):
206	self.sName = sName;
207	self.sInstrSet = sInstrSet;
208	self.sCpuMode = sCpuMode;
209	self.iRing = iRing;
210	self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;
211	self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;
212
213	def isUsingIprt(self):
214	""" Whether it's an IPRT environment or not. """
215	return self.sName.startswith('iprt');
216
217	def is64Bit(self):
218	""" Whether it's a 64-bit environment or not. """
219	return self.sInstrSet == self.ksInstrSet_64;
220
221	def getDefOpBits(self):
222	""" Get the default operand size as a bit count. """
223	if self.sInstrSet == self.ksInstrSet_16:
224	return 16;
225	return 32;
226
227	def getDefOpBytes(self):
228	""" Get the default operand size as a byte count. """
229	return self.getDefOpBits() / 8;
230
231	def getMaxOpBits(self):
232	""" Get the max operand size as a bit count. """
233	if self.sInstrSet == self.ksInstrSet_64:
234	return 64;
235	return 32;
236
237	def getMaxOpBytes(self):
238	""" Get the max operand size as a byte count. """
239	return self.getMaxOpBits() / 8;
240
241	def getDefAddrBits(self):
242	""" Get the default address size as a bit count. """
243	if self.sInstrSet == self.ksInstrSet_16:
244	return 16;
245	if self.sInstrSet == self.ksInstrSet_32:
246	return 32;
247	return 64;
248
249	def getDefAddrBytes(self):
250	""" Get the default address size as a byte count. """
251	return self.getDefAddrBits() / 8;
252
253	def getGRegCount(self):
254	""" Get the number of general registers. """
255	if self.sInstrSet == self.ksInstrSet_64:
256	return 16;
257	return 8;
258
259	def randGRegNoSp(self):
260	""" Returns a random general register number, excluding the SP register. """
261	iReg = randU16();
262	return iReg % (16 if self.is64Bit() else 8);
263
264	def getAddrModes(self):
265	""" Gets a list of addressing mode (16, 32, or/and 64). """
266	if self.sInstrSet == self.ksInstrSet_16:
267	return [16, 32];
268	if self.sInstrSet == self.ksInstrSet_32:
269	return [32, 16];
270	return [64, 64];
271
272
273	## Target environments.
274	g_dTargetEnvs = {
275	'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),
276	'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),
277	};
278
279
280	class InstrTestBase(object):
281	"""
282	Base class for testing one instruction.
283	"""
284
285	def __init__(self, sName, sInstr = None):
286	self.sName = sName;
287	self.sInstr = sInstr if sInstr else sName.split()[0];
288
289	def isApplicable(self, oGen):
290	"""
291	Tests if the instruction test is applicable to the selected environment.
292	"""
293	_ = oGen;
294	return True;
295
296	def generateTest(self, oGen, sTestFnName):
297	"""
298	Emits the test assembly code.
299	"""
300	oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));
301	return True;
302
303	def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):
304	""" Generate a list of inputs. """
305	if fLong:
306	#
307	# Try do extremes as well as different ranges of random numbers.
308	#
309	auRet = [0, 1, ];
310	if cbMaxOp >= 1:
311	auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];
312	if cbMaxOp >= 2:
313	auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];
314	if cbMaxOp >= 4:
315	auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];
316	if cbMaxOp >= 8:
317	auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];
318
319	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
320	for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):
321	if cBits < cbMaxOp * 8:
322	auRet += randUxxList(cBits, cValues);
323	cWanted = 16;
324	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
325	for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):
326	if cBits < cbMaxOp * 8:
327	auRet += randUxxList(cBits, cValues);
328	cWanted = 64;
329	else:
330	for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):
331	if cBits < cbMaxOp * 8:
332	auRet += randUxxList(cBits, cValues);
333	cWanted = 168;
334	if len(auRet) < cWanted:
335	auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));
336	else:
337	#
338	# Short list, just do some random numbers.
339	#
340	auRet = [];
341	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
342	auRet += randUxxList(cbMaxOp, 1);
343	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
344	auRet += randUxxList(cbMaxOp, 2);
345	else:
346	auRet = [];
347	for cBits in (8, 16, 32, 64):
348	if cBits < cbMaxOp * 8:
349	auRet += randUxxList(cBits, 1);
350	return auRet;
351
352
353
354	class InstrTest_MemOrGreg_2_Greg(InstrTestBase):
355	"""
356	Instruction reading memory or general register and writing the result to a
357	general register.
358	"""
359
360	def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):
361	InstrTestBase.__init__(self, sName, sInstr);
362	self.fnCalcResult = fnCalcResult;
363	self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);
364
365	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
366	""" Writes the instruction with two general registers as operands. """
367	if cbEffOp == 8:
368	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs64[iOp2]));
369	elif cbEffOp == 4:
370	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs32[iOp1], g_asGRegs32[iOp2]));
371	elif cbEffOp == 2:
372	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs16[iOp1], g_asGRegs16[iOp2]));
373	elif cbEffOp == 1:
374	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs8[iOp1], g_asGRegs8[iOp2]));
375	else:
376	assert False;
377	return True;
378
379	def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):
380	""" Writes the instruction with two general registers as operands. """
381	if cbEffOp == 8:
382	oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
383	elif cbEffOp == 4:
384	oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
385	elif cbEffOp == 2:
386	oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
387	elif cbEffOp == 1:
388	oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs8[iOp1],));
389	else:
390	assert False;
391
392	if iOp2 == 5 and iMod == 0:
393	oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))
394	if oGen.oTarget.is64Bit():
395	oGen.write(' wrt rip');
396	else:
397	if iMod == 1:
398	oGen.write('byte %d + ' % (offDisp,));
399	elif iMod == 2:
400	oGen.write('dword %d + ' % (offDisp,));
401	else:
402	assert iMod == 0;
403
404	if cAddrBits == 64:
405	oGen.write(g_asGRegs64[iOp2]);
406	elif cAddrBits == 32:
407	oGen.write(g_asGRegs32[iOp2]);
408	elif cAddrBits == 16:
409	assert False; ## @todo implement 16-bit addressing.
410	else:
411	assert False, str(cAddrBits);
412
413	oGen.write(']\n');
414	return True;
415
416	def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
417	""" Generate one standard test. """
418	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
419	oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uInput,));
420	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
421	self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);
422	oGen.pushConst(uResult);
423	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
424	_ = cbMaxOp;
425	return True;
426
427	def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):
428	""" Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """
429	oGen.pushConst(uInput);
430	assert offDisp is None or iMod != 0;
431	if (iOp2 != 5 and iOp2 != 13) or iMod != 0:
432	oGen.write(' call VBINSTST_NAME(%s)\n'
433	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));
434	else:
435	## @todo generate REX.B=1 variant.
436	oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
437	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
438	return True;
439
440
441	def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
442	""" Generate mode 0, 1 and 2 test for the R/M=iOp2. """
443	if cAddrBits == 16:
444	_ = cbMaxOp;
445	else:
446	iMod = 0; # No disp, except for i=5.
447	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
448	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);
449	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);
450	oGen.pushConst(uResult);
451	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
452
453	iMod = 2;
454	for offDisp in (127, -128):
455	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
456	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
457	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
458	oGen.pushConst(uResult);
459	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
460
461	iMod = 2;
462	for offDisp in (2147483647, -2147483648):
463	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
464	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
465	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
466	oGen.pushConst(uResult);
467	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
468
469	return True;
470
471
472	def generateStandardTests(self, oGen):
473	""" Generate standard tests. """
474
475	# Parameters.
476	cbDefOp = oGen.oTarget.getDefOpBytes();
477	cbMaxOp = oGen.oTarget.getMaxOpBytes();
478	auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);
479	auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);
480	iLongOp1 = oGen.oTarget.randGRegNoSp();
481	iLongOp2 = oGen.oTarget.randGRegNoSp();
482	oOp2Range = range(oGen.oTarget.getGRegCount());
483	oOp1MemRange = range(oGen.oTarget.getGRegCount());
484	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
485	oOp2Range = [iLongOp2,];
486	oOp1MemRange = [iLongOp1,];
487
488	# Register tests
489	if False:
490	for cbEffOp in self.acbOpVars:
491	if cbEffOp > cbMaxOp:
492	continue;
493	for iOp1 in range(oGen.oTarget.getGRegCount()):
494	if oGen.oTarget.asGRegsNoSp[iOp1] is None:
495	continue;
496	for iOp2 in oOp2Range:
497	if oGen.oTarget.asGRegsNoSp[iOp2] is None:
498	continue;
499	for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):
500	uResult = self.fnCalcResult(cbEffOp, uInput,
501	oGen.auRegValues[iOp1] if iOp1 != iOp2 else uInput, oGen);
502	oGen.newSubTest();
503	self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult);
504
505	# Memory test.
506	for cbEffOp in self.acbOpVars:
507	if cbEffOp > cbMaxOp:
508	continue;
509	for iOp1 in oOp1MemRange:
510	if oGen.oTarget.asGRegsNoSp[iOp1] is None:
511	continue;
512	for cAddrBits in oGen.oTarget.getAddrModes():
513	for iOp2 in range(len(oGen.oTarget.asGRegs)):
514	if iOp2 != 4:
515
516	for uInput in (auLongInputs if iOp1 == iLongOp1 and False else auShortInputs):
517	oGen.newSubTest();
518	if iOp1 == iOp2 and iOp2 != 5 and iOp2 != 13 and cbEffOp != cbMaxOp:
519	continue; # Don't know the high bit of the address ending up the result - skip it.
520	uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);
521	self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,
522	iOp1, iOp2, uInput, uResult);
523	else:
524	pass; # SIB
525	break; ## remove me!
526	break; ## remove me!
527	break; ## remove me!
528
529	return True;
530
531	def generateTest(self, oGen, sTestFnName):
532	oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));
533	#oGen.write(' int3\n');
534
535	self.generateStandardTests(oGen);
536
537	#oGen.write(' int3\n');
538	oGen.write(' ret\n');
539	oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));
540	return True;
541
542
543
544	class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
545	"""
546	Tests MOV Gv,Ev.
547	"""
548	def __init__(self):
549	InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);
550
551	@staticmethod
552	def calc_mov(cbEffOp, uInput, uCur, oGen):
553	""" Calculates the result of a mov instruction."""
554	if cbEffOp == 8:
555	return uInput & UINT64_MAX;
556	if cbEffOp == 4:
557	return uInput & UINT32_MAX;
558	if cbEffOp == 2:
559	return (uCur & 0xffffffffffff0000) \| (uInput & UINT16_MAX);
560	assert cbEffOp == 1;
561	return (uCur & 0xffffffffffffff00) \| (uInput & UINT8_MAX);
562
563
564	class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
565	"""
566	Tests MOVSXD Gv,Ev.
567	"""
568	def __init__(self):
569	InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);
570
571	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
572	if cbEffOp == 8:
573	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));
574	elif cbEffOp == 4 or cbEffOp == 2:
575	abInstr = [];
576	if cbEffOp != oGen.oTarget.getDefOpBytes():
577	abInstr.append(X86_OP_PRF_SIZE_OP);
578	abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);
579	abInstr.append(0x63);
580	abInstr += calcModRmForTwoRegs(iOp1, iOp2);
581	oGen.writeInstrBytes(abInstr);
582	else:
583	assert False;
584	assert False;
585	return True;
586
587	def isApplicable(self, oGen):
588	return oGen.oTarget.is64Bit();
589
590	@staticmethod
591	def calc_movsxd(cbEffOp, uInput, uCur, oGen):
592	"""
593	Calculates the result of a movxsd instruction.
594	Returns the result value (cbMaxOp sized).
595	"""
596	_ = oGen;
597	if cbEffOp == 8 and (uInput & RT_BIT_32(31)):
598	return (UINT32_MAX << 32) \| (uInput & UINT32_MAX);
599	if cbEffOp == 2:
600	return (uCur & 0xffffffffffff0000) \| (uInput & 0xffff);
601	return uInput & UINT32_MAX;
602
603
604	## Instruction Tests.
605	g_aoInstructionTests = [
606	InstrTest_Mov_Gv_Ev(),
607	#InstrTest_MovSxD_Gv_Ev(),
608	];
609
610
611	class InstructionTestGen(object):
612	"""
613	Instruction Test Generator.
614	"""
615
616	## @name Test size
617	## @{
618	ksTestSize_Large = 'large';
619	ksTestSize_Medium = 'medium';
620	ksTestSize_Tiny = 'tiny';
621	## @}
622	kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny );
623
624
625
626	def __init__(self, oOptions):
627	self.oOptions = oOptions;
628	self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv];
629
630	# Calculate the number of output files.
631	self.cFiles = 1;
632	if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile:
633	self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile;
634	if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests):
635	self.cFiles += 1;
636
637	# Fix the known register values.
638	self.au64Regs = randUxxList(64, 16);
639	self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)];
640	self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)];
641	self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs;
642
643	# Declare state variables used while generating.
644	self.oFile = sys.stderr;
645	self.iFile = -1;
646	self.sFile = '';
647	self.dCheckFns = dict();
648	self.dMemSetupFns = dict();
649	self.d64BitConsts = dict();
650
651
652	#
653	# Methods used by instruction tests.
654	#
655
656	def write(self, sText):
657	""" Writes to the current output file. """
658	return self.oFile.write(unicode(sText));
659
660	def writeln(self, sText):
661	""" Writes a line to the current output file. """
662	self.write(sText);
663	return self.write('\n');
664
665	def writeInstrBytes(self, abInstr):
666	"""
667	Emits an instruction given as a sequence of bytes values.
668	"""
669	self.write(' db %#04x' % (abInstr[0],));
670	for i in range(1, len(abInstr)):
671	self.write(', %#04x' % (abInstr[i],));
672	return self.write('\n');
673
674	def newSubTest(self):
675	"""
676	Indicates that a new subtest has started.
677	"""
678	self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n');
679	return True;
680
681	def needGRegChecker(self, iReg1, iReg2):
682	"""
683	Records the need for a given register checker function, returning its label.
684	"""
685	assert iReg1 < 32; assert iReg2 < 32;
686	iRegs = iReg1 + iReg2 * 32;
687	if iRegs in self.dCheckFns:
688	self.dCheckFns[iRegs] += 1;
689	else:
690	self.dCheckFns[iRegs] = 1;
691	return 'Common_Check_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2]);
692
693	def needGRegMemSetup(self, cAddrBits, cbEffOp, iReg1, offDisp = None):
694	"""
695	Records the need for a given register checker function, returning its label.
696	"""
697	sName = '%ubit_U%u_%s' % (cAddrBits, cbEffOp * 8, self.oTarget.asGRegs[iReg1]);
698	if offDisp is not None:
699	sName += '_%#010x' % (offDisp & UINT32_MAX, );
700	if sName in self.dCheckFns:
701	self.dMemSetupFns[sName] += 1;
702	else:
703	self.dMemSetupFns[sName] = 1;
704	return 'Common_MemSetup_' + sName;
705
706	def need64BitConstant(self, uVal):
707	"""
708	Records the need for a 64-bit constant, returning its label.
709	These constants are pooled to attempt reduce the size of the whole thing.
710	"""
711	assert uVal >= 0 and uVal <= UINT64_MAX;
712	if uVal in self.d64BitConsts:
713	self.d64BitConsts[uVal] += 1;
714	else:
715	self.d64BitConsts[uVal] = 1;
716	return 'g_u64Const_0x%016x' % (uVal, );
717
718	def pushConst(self, uResult):
719	"""
720	Emits a push constant value, taking care of high values on 64-bit hosts.
721	"""
722	if self.oTarget.is64Bit() and uResult >= 0x80000000:
723	self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),));
724	else:
725	self.write(' push dword 0x%x\n' % (uResult,));
726	return True;
727
728
729	#
730	# Internal machinery.
731	#
732
733	def _calcTestFunctionName(self, oInstrTest, iInstrTest):
734	"""
735	Calc a test function name for the given instruction test.
736	"""
737	sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName);
738	return sName.replace(',', '_').replace(' ', '_').replace('%', '_');
739
740	def _generateFileHeader(self, ):
741	"""
742	Writes the file header.
743	Raises exception on trouble.
744	"""
745	self.write('; $Id: InstructionTestGen.py 46731 2013-06-22 00:34:46Z vboxsync $\n'
746	';; @file %s\n'
747	'; Autogenerate by %s %s. DO NOT EDIT\n'
748	';\n'
749	'\n'
750	';\n'
751	'; Headers\n'
752	';\n'
753	'%%include "env-%s.mac"\n'
754	% ( os.path.basename(self.sFile),
755	os.path.basename(__file__), __version__[11:-1],
756	self.oTarget.sName,
757	) );
758	# Target environment specific init stuff.
759
760	#
761	# Global variables.
762	#
763	self.write('\n\n'
764	';\n'
765	'; Globals\n'
766	';\n');
767	self.write('VBINSTST_BEGINDATA\n'
768	'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n'
769	' dq 0\n'
770	'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n'
771	' dq 0\n'
772	'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n'
773	' dq 0\n'
774	'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n'
775	' dd 0\n'
776	'VBINSTST_BEGINCODE\n'
777	);
778	self.write('%ifdef RT_ARCH_AMD64\n');
779	for i in range(len(g_asGRegs64)):
780	self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i]));
781	self.write('%endif\n\n')
782
783	#
784	# Common functions.
785	#
786
787	# Loading common values.
788	self.write('\n\n'
789	'VBINSTST_BEGINPROC Common_LoadKnownValues\n'
790	'%ifdef RT_ARCH_AMD64\n');
791	for i in range(len(g_asGRegs64NoSp)):
792	if g_asGRegs64NoSp[i]:
793	self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],));
794	self.write('%else\n');
795	for i in range(8):
796	if g_asGRegs32NoSp[i]:
797	self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],));
798	self.write('%endif\n'
799	' ret\n'
800	'VBINSTST_ENDPROC Common_LoadKnownValues\n'
801	'\n');
802
803	self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n'
804	'%ifdef RT_ARCH_AMD64\n');
805	for i in range(len(g_asGRegs64NoSp)):
806	if g_asGRegs64NoSp[i]:
807	self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n'
808	' je .ok_%u\n'
809	' push %u ; register number\n'
810	' push %s ; actual\n'
811	' push qword [g_u64KnownValue_%s wrt rip] ; expected\n'
812	' call VBINSTST_NAME(Common_BadValue)\n'
813	'.ok_%u:\n'
814	% ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,));
815	self.write('%else\n');
816	for i in range(8):
817	if g_asGRegs32NoSp[i]:
818	self.write(' cmp %s, 0x%x\n'
819	' je .ok_%u\n'
820	' push %u ; register number\n'
821	' push %s ; actual\n'
822	' push dword 0x%x ; expected\n'
823	' call VBINSTST_NAME(Common_BadValue)\n'
824	'.ok_%u:\n'
825	% ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,));
826	self.write('%endif\n'
827	' ret\n'
828	'VBINSTST_ENDPROC Common_CheckKnownValues\n'
829	'\n');
830
831	return True;
832
833	def _generateMemSetupFunctions(self):
834	"""
835	Generates the memory setup functions.
836	"""
837	cDefAddrBits = self.oTarget.getDefAddrBits();
838	for sName in self.dMemSetupFns:
839	# Unpack it.
840	asParams = sName.split('_');
841	cAddrBits = int(asParams[0][:-3]);
842	cEffOpBits = int(asParams[1][1:]);
843	sBaseReg = asParams[2];
844
845	if cAddrBits == 64: asAddrGRegs = g_asGRegs64;
846	elif cAddrBits == 32: asAddrGRegs = g_asGRegs32;
847	else: asAddrGRegs = g_asGRegs16;
848	iBaseReg = asAddrGRegs.index(sBaseReg);
849
850	i = 3;
851	offDisp = None;
852	if i < len(asParams) and len(asParams[i]) == 10:
853	u32Disp = long(asParams[i], 16);
854	i += 1;
855
856	sIndexReg = None;
857	iIndexReg = None;
858	if i < len(asParams):
859	sIndexReg = asParams[i];
860	iBaseReg = asAddrGRegs.index(sBaseReg);
861	i += 1;
862
863	iScale = 1;
864	if i < len(asParams):
865	iScale = int(asParams[i]); assert iScale in [2, 4, 8];
866	i += 1;
867
868	# Prologue.
869	iTmpReg1 = 0 if iBaseReg != 0 else 1;
870	self.write('\n\n'
871	'VBINSTST_BEGINPROC Common_MemSetup_%s\n'
872	' MY_PUSH_FLAGS\n'
873	' push %s\n'
874	% (sName, self.oTarget.asGRegs[iTmpReg1], ));
875
876	# Figure out what to use.
877	if cEffOpBits == 64:
878	sTmpReg1 = g_asGRegs64[iTmpReg1];
879	sDataVar = 'VBINSTST_NAME(g_u64Data)';
880	elif cEffOpBits == 32:
881	sTmpReg1 = g_asGRegs32[iTmpReg1];
882	sDataVar = 'VBINSTST_NAME(g_u32Data)';
883	elif cEffOpBits == 16:
884	sTmpReg1 = g_asGRegs16[iTmpReg1];
885	sDataVar = 'VBINSTST_NAME(g_u16Data)';
886	else:
887	assert cEffOpBits == 8;
888	sTmpReg1 = g_asGRegs8[iTmpReg1];
889	sDataVar = 'VBINSTST_NAME(g_u8Data)';
890
891	# Load the value and mem address, sorting the value there.
892	self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,));
893	if cAddrBits >= cDefAddrBits:
894	self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,));
895	self.write(' lea %s, [%s xWrtRIP]\n' % (sBaseReg, sDataVar,));
896	else:
897
898	if cAddrBits == 16:
899	self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sBaseReg,));
900	else:
901	self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sBaseReg,));
902	self.write(' add %s, %s\n' % (sBaseReg, (randU16() << cEffOpBits) & 0xfff, ));
903	self.write(' mov [%s], %s\n' % (sBaseReg, sTmpReg1, ));
904
905	# Adjust for disposition and scaling.
906	if offDisp is not None:
907	self.write(' sub %s, %d\n' % ( sBaseReg, convU32ToSigned(u32Disp), ));
908	if iIndexReg is not None:
909	uIdxRegVal = randUxx(cAddrBits);
910	self.write(' mov %s, %u\n' % ( sIndexReg, uIdxRegVal,));
911	if cAddrBits == 64:
912	self.write(' sub %s, %#06x\n' % ( sBaseReg, uIdxRegVal * iScale, ));
913	elif cAddrBits == 16:
914	self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, ));
915	else:
916	assert cAddrBits == 16;
917	self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT16_MAX, ));
918
919	# Set upper bits that's supposed to be unused.
920	if cDefAddrBits > cAddrBits or cAddrBits == 16:
921	if cDefAddrBits == 64:
922	assert cAddrBits == 32;
923	self.write(' mov %s, %#018x\n'
924	' or %s, %s\n'
925	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
926	g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],));
927	if iIndexReg is not None:
928	self.write(' mov %s, %#018x\n'
929	' or %s, %s\n'
930	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
931	g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],));
932	else:
933	assert cDefAddrBits == 32; assert cAddrBits == 16;
934	self.write(' or %s, %#010x\n'
935	% ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, ));
936	if iIndexReg is not None:
937	self.write(' or %s, %#010x\n'
938	% ( g_asGRegs32[iIndexReg], randU32() & 0xffff0000, ));
939
940	# Epilogue.
941	self.write(' pop %s\n'
942	' MY_POP_FLAGS\n'
943	' ret\n'
944	'VBINSTST_ENDPROC Common_MemSetup_%s\n'
945	% ( self.oTarget.asGRegs[iTmpReg1], sName,));
946
947
948	def _generateFileFooter(self):
949	"""
950	Generates file footer.
951	"""
952
953	# Register checking functions.
954	for iRegs in self.dCheckFns:
955	iReg1 = iRegs & 0x1f;
956	sReg1 = self.oTarget.asGRegs[iReg1];
957	iReg2 = (iRegs >> 5) & 0x1f;
958	sReg2 = self.oTarget.asGRegs[iReg2];
959	sPushSize = 'dword';
960
961	self.write('\n\n'
962	'; Checks two register values, expected values pushed on the stack.\n'
963	'; To save space, the callee cleans up the stack.'
964	'; Ref count: %u\n'
965	'VBINSTST_BEGINPROC Common_Check_%s_%s\n'
966	' MY_PUSH_FLAGS\n'
967	% ( self.dCheckFns[iRegs], sReg1, sReg2, ) );
968
969	self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB]\n'
970	' je .equal1\n'
971	' push %s %u ; register number\n'
972	' push %s ; actual\n'
973	' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB]\n'
974	' push %s ; expected\n'
975	' call VBINSTST_NAME(Common_BadValue)\n'
976	' pop %s\n'
977	' pop %s\n'
978	' pop %s\n'
979	'.equal1:\n'
980	% ( sReg1, sPushSize, iReg1, sReg1, sReg1, sReg1, sReg1, sReg1, sReg1, ) );
981	if iReg1 != iReg2: # If input and result regs are the same, only check the result.
982	self.write(' cmp %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n'
983	' je .equal2\n'
984	' push %s %u ; register number\n'
985	' push %s ; actual\n'
986	' mov %s, [xSP + sCB*3 + MY_PUSH_FLAGS_SIZE + xCB]\n'
987	' push %s ; expected\n'
988	' call VBINSTST_NAME(Common_BadValue)\n'
989	' pop %s\n'
990	' pop %s\n'
991	' pop %s\n'
992	'.equal2:\n'
993	% ( sReg2, sPushSize, iReg2, sReg2, sReg2, sReg2, sReg2, sReg2, sReg2, ) );
994
995	if self.oTarget.is64Bit():
996	self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg1, sReg1,));
997	if iReg1 != iReg2:
998	self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg2, sReg2,));
999	else:
1000	self.write(' mov %s, 0x%x\n' % (sReg1, self.au32Regs[iReg1],));
1001	if iReg1 != iReg2:
1002	self.write(' mov %s, 0x%x\n' % (sReg2, self.au32Regs[iReg2],));
1003	self.write(' MY_POP_FLAGS\n'
1004	' call VBINSTST_NAME(Common_CheckKnownValues)\n'
1005	' ret sCB*2\n'
1006	'VBINSTST_ENDPROC Common_Check_%s_%s\n'
1007	% (sReg1, sReg2,));
1008
1009	# memory setup functions
1010	self._generateMemSetupFunctions();
1011
1012	# 64-bit constants.
1013	if len(self.d64BitConsts) > 0:
1014	self.write('\n\n'
1015	';\n'
1016	'; 64-bit constants\n'
1017	';\n');
1018	for uVal in self.d64BitConsts:
1019	self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self.d64BitConsts[uVal], ) );
1020
1021	return True;
1022
1023	def _generateTests(self):
1024	"""
1025	Generate the test cases.
1026	"""
1027	for self.iFile in range(self.cFiles):
1028	if self.cFiles == 1:
1029	self.sFile = '%s.asm' % (self.oOptions.sOutputBase,)
1030	else:
1031	self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile)
1032	self.oFile = sys.stdout;
1033	if self.oOptions.sOutputBase != '-':
1034	self.oFile = io.open(self.sFile, 'w', encoding = 'utf-8');
1035
1036	self._generateFileHeader();
1037
1038	# Calc the range.
1039	iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile;
1040	iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile;
1041	if iInstrTestEnd > len(g_aoInstructionTests):
1042	iInstrTestEnd = len(g_aoInstructionTests);
1043
1044	# Generate the instruction tests.
1045	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1046	oInstrTest = g_aoInstructionTests[iInstrTest];
1047	self.write('\n'
1048	'\n'
1049	';\n'
1050	'; %s\n'
1051	';\n'
1052	% (oInstrTest.sName,));
1053	oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest));
1054
1055	# Generate the main function.
1056	self.write('\n\n'
1057	'VBINSTST_BEGINPROC TestInstrMain\n'
1058	' MY_PUSH_ALL\n'
1059	' sub xSP, 40h\n'
1060	'\n');
1061
1062	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1063	oInstrTest = g_aoInstructionTests[iInstrTest];
1064	if oInstrTest.isApplicable(self):
1065	self.write('%%ifdef ASM_CALL64_GCC\n'
1066	' lea rdi, [.szInstr%03u wrt rip]\n'
1067	'%%elifdef ASM_CALL64_MSC\n'
1068	' lea rcx, [.szInstr%03u wrt rip]\n'
1069	'%%else\n'
1070	' mov xAX, .szInstr%03u\n'
1071	' mov [xSP], xAX\n'
1072	'%%endif\n'
1073	' VBINSTST_CALL_FN_SUB_TEST\n'
1074	' call VBINSTST_NAME(%s)\n'
1075	% ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest)));
1076
1077	self.write('\n'
1078	' add xSP, 40h\n'
1079	' MY_POP_ALL\n'
1080	' ret\n\n');
1081	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1082	self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,));
1083	self.write('VBINSTST_ENDPROC TestInstrMain\n\n');
1084
1085	self._generateFileFooter();
1086	if self.oOptions.sOutputBase != '-':
1087	self.oFile.close();
1088	self.oFile = None;
1089	self.sFile = '';
1090
1091	return RTEXITCODE_SUCCESS;
1092
1093	def _runMakefileMode(self):
1094	"""
1095	Generate a list of output files on standard output.
1096	"""
1097	if self.cFiles == 1:
1098	print('%s.asm' % (self.oOptions.sOutputBase,));
1099	else:
1100	print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles)));
1101	return RTEXITCODE_SUCCESS;
1102
1103	def run(self):
1104	"""
1105	Generates the tests or whatever is required.
1106	"""
1107	if self.oOptions.fMakefileMode:
1108	return self._runMakefileMode();
1109	return self._generateTests();
1110
1111	@staticmethod
1112	def main():
1113	"""
1114	Main function a la C/C++. Returns exit code.
1115	"""
1116
1117	#
1118	# Parse the command line.
1119	#
1120	oParser = OptionParser(version = __version__[11:-1].strip());
1121	oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False,
1122	help = 'Special mode for use to output a list of output files for the benefit of '
1123	'the make program (kmk).');
1124	oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '<instr-per-file>', type = 'int', default = 9999999,
1125	help = 'Number of instruction to test per output file.');
1126	oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '<file>', default = None,
1127	help = 'The output file base name, no suffix please. Required.');
1128	oParser.add_option('--target', dest = 'sTargetEnv', metavar = '<target>',
1129	default = 'iprt-r3-32',
1130	choices = g_dTargetEnvs.keys(),
1131	help = 'The target environment. Choices: %s'
1132	% (', '.join(sorted(g_dTargetEnvs.keys())),));
1133	oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium,
1134	choices = InstructionTestGen.kasTestSizes,
1135	help = 'Selects the test size.');
1136
1137	(oOptions, asArgs) = oParser.parse_args();
1138	if len(asArgs) > 0:
1139	oParser.print_help();
1140	return RTEXITCODE_SYNTAX
1141	if oOptions.sOutputBase is None:
1142	print('syntax error: Missing required option --output-base.', file = sys.stderr);
1143	return RTEXITCODE_SYNTAX
1144
1145	#
1146	# Instantiate the program class and run it.
1147	#
1148	oProgram = InstructionTestGen(oOptions);
1149	return oProgram.run();
1150
1151
1152	if __name__ == '__main__':
1153	sys.exit(InstructionTestGen.main());
1154

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source: vbox/trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py@ 46731

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