InstructionTestGen.py@ 46856

Last change on this file since 46856 was 46856, checked in by vboxsync, 11 years ago
8-bit high register hell (reg/reg only so far).
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1	#!/usr/bin/env python
2	# -- coding: utf-8 --
3	# $Id: InstructionTestGen.py 46856 2013-06-28 03:03:19Z vboxsync $
4
5	"""
6	Instruction Test Generator.
7	"""
8
9	from __future__ import print_function;
10
11	__copyright__ = \
12	"""
13	Copyright (C) 2012-2013 Oracle Corporation
14
15	Oracle Corporation confidential
16	All rights reserved
17	"""
18	__version__ = "$Revision: 46856 $";
19
20
21	# Standard python imports.
22	import io;
23	import os;
24	from optparse import OptionParser
25	import random;
26	import sys;
27
28
29	## @name Exit codes
30	## @{
31	RTEXITCODE_SUCCESS = 0;
32	RTEXITCODE_SYNTAX = 2;
33	## @}
34
35	## @name Various C macros we're used to.
36	## @{
37	UINT8_MAX = 0xff
38	UINT16_MAX = 0xffff
39	UINT32_MAX = 0xffffffff
40	UINT64_MAX = 0xffffffffffffffff
41	def RT_BIT_32(iBit): # pylint: disable=C0103
42	""" 32-bit one bit mask. """
43	return 1 << iBit;
44	def RT_BIT_64(iBit): # pylint: disable=C0103
45	""" 64-bit one bit mask. """
46	return 1 << iBit;
47	## @}
48
49
50	## @name ModR/M
51	## @{
52	X86_MODRM_RM_MASK = 0x07;
53	X86_MODRM_REG_MASK = 0x38;
54	X86_MODRM_REG_SMASK = 0x07;
55	X86_MODRM_REG_SHIFT = 3;
56	X86_MODRM_MOD_MASK = 0xc0;
57	X86_MODRM_MOD_SMASK = 0x03;
58	X86_MODRM_MOD_SHIFT = 6;
59	## @}
60
61	## @name SIB
62	## @{
63	X86_SIB_BASE_MASK = 0x07;
64	X86_SIB_INDEX_MASK = 0x38;
65	X86_SIB_INDEX_SMASK = 0x07;
66	X86_SIB_INDEX_SHIFT = 3;
67	X86_SIB_SCALE_MASK = 0xc0;
68	X86_SIB_SCALE_SMASK = 0x03;
69	X86_SIB_SCALE_SHIFT = 6;
70	## @}
71
72	## @name Prefixes
73	## @
74	X86_OP_PRF_CS = 0x2e;
75	X86_OP_PRF_SS = 0x36;
76	X86_OP_PRF_DS = 0x3e;
77	X86_OP_PRF_ES = 0x26;
78	X86_OP_PRF_FS = 0x64;
79	X86_OP_PRF_GS = 0x65;
80	X86_OP_PRF_SIZE_OP = 0x66;
81	X86_OP_PRF_SIZE_ADDR = 0x67;
82	X86_OP_PRF_LOCK = 0xf0;
83	X86_OP_PRF_REPZ = 0xf2;
84	X86_OP_PRF_REPNZ = 0xf3;
85	X86_OP_REX_B = 0x41;
86	X86_OP_REX_X = 0x42;
87	X86_OP_REX_R = 0x44;
88	X86_OP_REX_W = 0x48;
89	## @}
90
91
92	## @name General registers
93	## @
94	X86_GREG_xAX = 0
95	X86_GREG_xCX = 1
96	X86_GREG_xDX = 2
97	X86_GREG_xBX = 3
98	X86_GREG_xSP = 4
99	X86_GREG_xBP = 5
100	X86_GREG_xSI = 6
101	X86_GREG_xDI = 7
102	X86_GREG_x8 = 8
103	X86_GREG_x9 = 9
104	X86_GREG_x10 = 10
105	X86_GREG_x11 = 11
106	X86_GREG_x12 = 12
107	X86_GREG_x13 = 13
108	X86_GREG_x14 = 14
109	X86_GREG_x15 = 15
110	## @}
111
112
113	## @name Register names.
114	## @{
115	g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
116	g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
117	g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',
118	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
119	g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',
120	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
121	g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',
122	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
123	g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',
124	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
125	g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh');
126	g_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil',
127	'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b',
128	'ah', 'ch', 'dh', 'bh');
129	## @}
130
131
132	## @name Random
133	## @{
134	g_oMyRand = random.SystemRandom()
135	def randU16():
136	""" Unsigned 16-bit random number. """
137	return g_oMyRand.getrandbits(16);
138
139	def randU32():
140	""" Unsigned 32-bit random number. """
141	return g_oMyRand.getrandbits(32);
142
143	def randU64():
144	""" Unsigned 64-bit random number. """
145	return g_oMyRand.getrandbits(64);
146
147	def randUxx(cBits):
148	""" Unsigned 8-, 16-, 32-, or 64-bit random number. """
149	return g_oMyRand.getrandbits(cBits);
150
151	def randUxxList(cBits, cElements):
152	""" List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """
153	return [randUxx(cBits) for _ in range(cElements)];
154	## @}
155
156
157
158
159	## @name Instruction Emitter Helpers
160	## @{
161
162	def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):
163	"""
164	Calculates a rex prefix if neccessary given the two registers
165	and optional rex size prefixes.
166	Returns an empty array if not necessary.
167	"""
168	bRex = bOtherRexPrefixes;
169	if iReg >= 8:
170	bRex \|= X86_OP_REX_R;
171	if iRm >= 8:
172	bRex \|= X86_OP_REX_B;
173	if bRex == 0:
174	return [];
175	return [bRex,];
176
177	def calcModRmForTwoRegs(iReg, iRm):
178	"""
179	Calculate the RM byte for two registers.
180	Returns an array with one byte in it.
181	"""
182	bRm = (0x3 << X86_MODRM_MOD_SHIFT) \
183	\| ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \
184	\| (iRm & X86_MODRM_RM_MASK);
185	return [bRm,];
186
187	## @}
188
189
190	## @name Misc
191	## @{
192
193	def convU32ToSigned(u32):
194	""" Converts a 32-bit unsigned value to 32-bit signed. """
195	if u32 < 0x80000000:
196	return u32;
197	return u32 - UINT32_MAX - 1;
198
199	def rotateLeftUxx(cBits, uVal, cShift):
200	""" Rotate a xx-bit wide unsigned number to the left. """
201	assert cShift < cBits;
202
203	if cBits == 16:
204	uMask = UINT16_MAX;
205	elif cBits == 32:
206	uMask = UINT32_MAX;
207	elif cBits == 64:
208	uMask = UINT64_MAX;
209	else:
210	assert cBits == 8;
211	uMask = UINT8_MAX;
212
213	uVal &= uMask;
214	uRet = (uVal << cShift) & uMask;
215	uRet \|= (uVal >> (cBits - cShift));
216	return uRet;
217
218	def rotateRightUxx(cBits, uVal, cShift):
219	""" Rotate a xx-bit wide unsigned number to the right. """
220	assert cShift < cBits;
221
222	if cBits == 16:
223	uMask = UINT16_MAX;
224	elif cBits == 32:
225	uMask = UINT32_MAX;
226	elif cBits == 64:
227	uMask = UINT64_MAX;
228	else:
229	assert cBits == 8;
230	uMask = UINT8_MAX;
231
232	uVal &= uMask;
233	uRet = (uVal >> cShift);
234	uRet \|= (uVal << (cBits - cShift)) & uMask;
235	return uRet;
236
237	def gregName(iReg, cBits, fRexByteRegs = True):
238	""" Gets the name of a general register by index and width. """
239	if cBits == 64:
240	return g_asGRegs64[iReg];
241	if cBits == 32:
242	return g_asGRegs32[iReg];
243	if cBits == 16:
244	return g_asGRegs16[iReg];
245	assert cBits == 8;
246	if fRexByteRegs:
247	return g_asGRegs8Rex[iReg];
248	return g_asGRegs8[iReg];
249
250	## @}
251
252
253	class TargetEnv(object):
254	"""
255	Target Runtime Environment.
256	"""
257
258	## @name CPU Modes
259	## @{
260	ksCpuMode_Real = 'real';
261	ksCpuMode_Protect = 'prot';
262	ksCpuMode_Paged = 'paged';
263	ksCpuMode_Long = 'long';
264	ksCpuMode_V86 = 'v86';
265	## @}
266
267	## @name Instruction set.
268	## @{
269	ksInstrSet_16 = '16';
270	ksInstrSet_32 = '32';
271	ksInstrSet_64 = '64';
272	## @}
273
274	def __init__(self, sName,
275	sInstrSet = ksInstrSet_32,
276	sCpuMode = ksCpuMode_Paged,
277	iRing = 3,
278	):
279	self.sName = sName;
280	self.sInstrSet = sInstrSet;
281	self.sCpuMode = sCpuMode;
282	self.iRing = iRing;
283	self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;
284	self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;
285
286	def isUsingIprt(self):
287	""" Whether it's an IPRT environment or not. """
288	return self.sName.startswith('iprt');
289
290	def is64Bit(self):
291	""" Whether it's a 64-bit environment or not. """
292	return self.sInstrSet == self.ksInstrSet_64;
293
294	def getDefOpBits(self):
295	""" Get the default operand size as a bit count. """
296	if self.sInstrSet == self.ksInstrSet_16:
297	return 16;
298	return 32;
299
300	def getDefOpBytes(self):
301	""" Get the default operand size as a byte count. """
302	return self.getDefOpBits() / 8;
303
304	def getMaxOpBits(self):
305	""" Get the max operand size as a bit count. """
306	if self.sInstrSet == self.ksInstrSet_64:
307	return 64;
308	return 32;
309
310	def getMaxOpBytes(self):
311	""" Get the max operand size as a byte count. """
312	return self.getMaxOpBits() / 8;
313
314	def getDefAddrBits(self):
315	""" Get the default address size as a bit count. """
316	if self.sInstrSet == self.ksInstrSet_16:
317	return 16;
318	if self.sInstrSet == self.ksInstrSet_32:
319	return 32;
320	return 64;
321
322	def getDefAddrBytes(self):
323	""" Get the default address size as a byte count. """
324	return self.getDefAddrBits() / 8;
325
326	def getGRegCount(self, cbEffBytes = 4):
327	""" Get the number of general registers. """
328	if self.sInstrSet == self.ksInstrSet_64:
329	if cbEffBytes == 1:
330	return 16 + 4;
331	return 16;
332	return 8;
333
334	def randGRegNoSp(self):
335	""" Returns a random general register number, excluding the SP register. """
336	iReg = randU16();
337	return iReg % (16 if self.is64Bit() else 8);
338
339	def getAddrModes(self):
340	""" Gets a list of addressing mode (16, 32, or/and 64). """
341	if self.sInstrSet == self.ksInstrSet_16:
342	return [16, 32];
343	if self.sInstrSet == self.ksInstrSet_32:
344	return [32, 16];
345	return [64, 32];
346
347	def is8BitHighGReg(self, cbEffOp, iGReg):
348	""" Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """
349	assert cbEffOp in [1, 2, 4, 8];
350	if cbEffOp == 1:
351	if iGReg >= 16:
352	return True;
353	if iGReg >= 4 and not self.is64Bit():
354	return True;
355	return False;
356
357
358
359	## Target environments.
360	g_dTargetEnvs = {
361	'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),
362	'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),
363	};
364
365
366	class InstrTestBase(object):
367	"""
368	Base class for testing one instruction.
369	"""
370
371	def __init__(self, sName, sInstr = None):
372	self.sName = sName;
373	self.sInstr = sInstr if sInstr else sName.split()[0];
374
375	def isApplicable(self, oGen):
376	"""
377	Tests if the instruction test is applicable to the selected environment.
378	"""
379	_ = oGen;
380	return True;
381
382	def generateTest(self, oGen, sTestFnName):
383	"""
384	Emits the test assembly code.
385	"""
386	oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));
387	return True;
388
389	def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):
390	""" Generate a list of inputs. """
391	if fLong:
392	#
393	# Try do extremes as well as different ranges of random numbers.
394	#
395	auRet = [0, 1, ];
396	if cbMaxOp >= 1:
397	auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];
398	if cbMaxOp >= 2:
399	auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];
400	if cbMaxOp >= 4:
401	auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];
402	if cbMaxOp >= 8:
403	auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];
404
405	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
406	for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):
407	if cBits < cbMaxOp * 8:
408	auRet += randUxxList(cBits, cValues);
409	cWanted = 16;
410	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
411	for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):
412	if cBits < cbMaxOp * 8:
413	auRet += randUxxList(cBits, cValues);
414	cWanted = 64;
415	else:
416	for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):
417	if cBits < cbMaxOp * 8:
418	auRet += randUxxList(cBits, cValues);
419	cWanted = 168;
420	if len(auRet) < cWanted:
421	auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));
422	else:
423	#
424	# Short list, just do some random numbers.
425	#
426	auRet = [];
427	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
428	auRet += randUxxList(cbMaxOp, 1);
429	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
430	auRet += randUxxList(cbMaxOp, 2);
431	else:
432	auRet = [];
433	for cBits in (8, 16, 32, 64):
434	if cBits < cbMaxOp * 8:
435	auRet += randUxxList(cBits, 1);
436	return auRet;
437
438
439	class InstrTest_MemOrGreg_2_Greg(InstrTestBase):
440	"""
441	Instruction reading memory or general register and writing the result to a
442	general register.
443	"""
444
445	def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):
446	InstrTestBase.__init__(self, sName, sInstr);
447	self.fnCalcResult = fnCalcResult;
448	self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);
449
450	## @name Test Instruction Writers
451	## @{
452
453	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
454	""" Writes the instruction with two general registers as operands. """
455	fRexByteRegs = oGen.oTarget.is64Bit();
456	oGen.write(' %s %s, %s\n'
457	% (self.sInstr, gregName(iOp1, cbEffOp * 8, fRexByteRegs), gregName(iOp2, cbEffOp * 8, fRexByteRegs),));
458	return True;
459
460	def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):
461	""" Writes the instruction with two general registers as operands. """
462	oGen.write(' ');
463	if iOp2 == 13 and iMod == 0 and cAddrBits == 64:
464	oGen.write('altrexb '); # Alternative encoding for rip relative addressing.
465	if cbEffOp == 8:
466	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
467	elif cbEffOp == 4:
468	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));
469	elif cbEffOp == 2:
470	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
471	elif cbEffOp == 1:
472	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));
473	else:
474	assert False;
475
476	if (iOp2 == 5 or iOp2 == 13) and iMod == 0:
477	oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))
478	if oGen.oTarget.is64Bit():
479	oGen.write(' wrt rip');
480	else:
481	if iMod == 1:
482	oGen.write('byte %d + ' % (offDisp,));
483	elif iMod == 2:
484	oGen.write('dword %d + ' % (offDisp,));
485	else:
486	assert iMod == 0;
487
488	if cAddrBits == 64:
489	oGen.write(g_asGRegs64[iOp2]);
490	elif cAddrBits == 32:
491	oGen.write(g_asGRegs32[iOp2]);
492	elif cAddrBits == 16:
493	assert False; ## @todo implement 16-bit addressing.
494	else:
495	assert False, str(cAddrBits);
496
497	oGen.write(']\n');
498	return True;
499
500	def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
501	""" Writes the instruction taking a register and a label (base only w/o reg), SIB form. """
502	assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16;
503	if cAddrBits == 64:
504	# Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit
505	# and we cannot (yet) make assumtions about where we're loaded.
506	## @todo Enable testing this in environments where we can make assumptions (boot sector).
507	oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
508	% ( self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
509	else:
510	oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
511	% ( iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
512	return True;
513
514	def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
515	""" Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """
516	assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16;
517	# Note! Using altsibxN to force scaled encoding. This is only really a
518	# necessity for iScale=1, but doesn't hurt for the rest.
519	oGen.write(' altsibx%u %s %s, [%s * %#x'
520	% (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iIndexReg, cAddrBits), iScale,));
521	if offDisp is not None:
522	oGen.write(' + %#x' % (offDisp,));
523	oGen.write(']\n');
524	_ = iBaseReg;
525	return True;
526
527	def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
528	""" Writes the instruction taking a register and base only (with reg), SIB form. """
529	oGen.write(' altsibx%u %s %s, [%s'
530	% (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iBaseReg, cAddrBits),));
531	if offDisp is not None:
532	oGen.write(' + %#x' % (offDisp,));
533	oGen.write(']\n');
534	_ = iIndexReg;
535	return True;
536
537	def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
538	""" Writes tinstruction taking a register and full featured SIB form address. """
539	# Note! From the looks of things, yasm will encode the following instructions the same way:
540	# mov eax, [rsi*1 + rbx]
541	# mov eax, [rbx + rsi*1]
542	# So, when there are two registers involved, the '*1' selects
543	# which is index and which is base.
544	oGen.write(' %s %s, [%s + %s * %u'
545	% ( self.sInstr, gregName(iOp1, cbEffOp * 8),
546	gregName(iBaseReg, cAddrBits), gregName(iIndexReg, cAddrBits), iScale,));
547	if offDisp is not None:
548	oGen.write(' + %#x' % (offDisp,));
549	oGen.write(']\n');
550	return True;
551
552	## @}
553
554
555	## @name Memory setups
556	## @{
557	def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput):
558	""" Sets up memory for a memory read. """
559	oGen.pushConst(uInput);
560	oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
561	return True;
562
563	def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None):
564	""" Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """
565	oGen.pushConst(uInput);
566	oGen.write(' call VBINSTST_NAME(%s)\n'
567	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),));
568	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],));
569	return True;
570
571	def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None):
572	""" Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """
573	oGen.pushConst(uInput);
574	oGen.write(' call VBINSTST_NAME(%s)\n'
575	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),));
576	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));
577	return True;
578
579	def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp):
580	""" Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """
581	oGen.pushConst(uInput);
582	oGen.write(' call VBINSTST_NAME(%s)\n'
583	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp,
584	iIndexReg = iIndexReg, iScale = iScale),));
585	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],));
586	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));
587	return True;
588
589	def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):
590	""" Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """
591	oGen.pushConst(uInput);
592	assert offDisp is None or iMod != 0;
593	if (iOp2 != 5 and iOp2 != 13) or iMod != 0:
594	oGen.write(' call VBINSTST_NAME(%s)\n'
595	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));
596	else:
597	oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
598	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
599	return True;
600
601	## @}
602
603	def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult):
604	""" Generate one standard instr greg,greg test. """
605	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
606	oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,));
607	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],));
608	self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);
609	oGen.pushConst(uResult);
610	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X),));
611	_ = cbMaxOp;
612	return True;
613
614	def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput):
615	""" High 8-bit registers are a real pain! """
616	assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2);
617	# Figure out the register indexes of the max op sized regs involved.
618	iOp1X = iOp1 & 3;
619	iOp2X = iOp2 & 3;
620	oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,));
621
622	# Calculate unshifted result.
623	if iOp1X != iOp2X:
624	uCur = oGen.auRegValues[iOp1X];
625	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
626	uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);
627	else:
628	uCur = uInput;
629	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
630	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
631	uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);
632	else:
633	uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8);
634	uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);
635
636
637	# Rotate the input and/or result to match their max-op-sized registers.
638	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
639	uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8);
640	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
641	uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8);
642
643	# Hand it over to an overridable worker method.
644	return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult);
645
646
647	def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
648	""" Generate mode 0, 1 and 2 test for the R/M=iOp2. """
649	if cAddrBits == 16:
650	_ = cbMaxOp;
651	else:
652	iMod = 0; # No disp, except for i=5.
653	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
654	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);
655	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);
656	oGen.pushConst(uResult);
657	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
658
659	if iOp2 != 5 and iOp2 != 13:
660	iMod = 1;
661	for offDisp in oGen.getDispForMod(iMod):
662	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
663	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
664	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
665	oGen.pushConst(uResult);
666	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
667
668	iMod = 2;
669	for offDisp in oGen.getDispForMod(iMod):
670	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
671	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
672	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
673	oGen.pushConst(uResult);
674	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
675
676	return True;
677
678	def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913
679	iBaseReg, iIndexReg, iScale, uInput, uResult):
680	""" Generate one SIB variations. """
681	for offDisp in oGen.getDispForMod(iMod, cbEffOp):
682	if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0):
683	if iIndexReg == 4:
684	if cAddrBits == 64:
685	continue; # skipping.
686	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
687	self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput);
688	self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
689	sChecker = oGen.needGRegChecker(iOp1);
690	else:
691	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
692	self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp);
693	self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
694	sChecker = oGen.needGRegChecker(iOp1, iIndexReg);
695	else:
696	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
697	if iIndexReg == 4:
698	self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp);
699	self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
700	sChecker = oGen.needGRegChecker(iOp1, iBaseReg);
701	else:
702	self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg,
703	iIndexReg, iScale, uInput, offDisp);
704	self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
705	sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg);
706	oGen.pushConst(uResult);
707	oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,));
708	_ = cbMaxOp;
709	return True;
710
711	def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs):
712	""" Generate all SIB variations for the given iOp1 (reg) value. """
713	assert cAddrBits in [32, 64];
714	for iBaseReg in range(len(oGen.oTarget.asGRegs)):
715	for iIndexReg in range(len(oGen.oTarget.asGRegs)):
716	if iBaseReg == 4 or iIndexReg == 4: # no RSP testing atm.
717	continue;
718	for iMod in [0, 1, 2]:
719	if iBaseReg == iOp1 and ((iBaseReg != 5 and iBaseReg != 13) or iMod != 0) and cAddrBits != cbMaxOp:
720	continue; # Don't know the high bit of the address ending up the result - skip it for now.
721	for iScale in (1, 2, 4, 8):
722	for uInput in auInputs:
723	oGen.newSubTest();
724	uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);
725	self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod,
726	iBaseReg, iIndexReg, iScale, uInput, uResult);
727
728	return True;
729
730
731	def generateStandardTests(self, oGen):
732	""" Generate standard tests. """
733
734	# Parameters.
735	cbDefOp = oGen.oTarget.getDefOpBytes();
736	cbMaxOp = oGen.oTarget.getMaxOpBytes();
737	auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);
738	auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);
739	iLongOp1 = oGen.oTarget.randGRegNoSp();
740	iLongOp2 = oGen.oTarget.randGRegNoSp();
741	oOp1MemRange = range(oGen.oTarget.getGRegCount());
742	oOp2Range = None;
743	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
744	oOp2Range = [iLongOp2,];
745	oOp1MemRange = [iLongOp1,];
746
747	# Register tests
748	if True:
749	for cbEffOp in self.acbOpVars:
750	if cbEffOp > cbMaxOp:
751	continue;
752	oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp));
753	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
754	oOp2Range = [iLongOp2,];
755	oGen.write('; cbEffOp=%u\n' % (cbEffOp,));
756
757	for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)):
758	if iOp1 == X86_GREG_xSP:
759	continue; # Cannot test xSP atm.
760	for iOp2 in oOp2Range:
761	if (iOp2 >= 16 and iOp1 in range(4, 16)) \
762	or (iOp1 >= 16 and iOp2 in range(4, 16)):
763	continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL.
764	if iOp2 == X86_GREG_xSP:
765	continue; # Cannot test xSP atm.
766
767	oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp));
768	for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):
769	oGen.newSubTest();
770	if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
771	uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput;
772	uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);
773	self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15,
774	uInput, uResult);
775	else:
776	self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput);
777
778	# Memory test.
779	if False:
780	for cbEffOp in self.acbOpVars:
781	if cbEffOp > cbMaxOp:
782	continue;
783	for iOp1 in oOp1MemRange:
784	if iOp1 == X86_GREG_xSP:
785	continue; # Cannot test xSP atm.
786	for cAddrBits in oGen.oTarget.getAddrModes():
787	auInputs = auLongInputs if iOp1 == iLongOp1 and False else auShortInputs;
788	for iOp2 in range(len(oGen.oTarget.asGRegs)):
789	if iOp2 != 4 or cAddrBits == 16:
790	for uInput in auInputs:
791	oGen.newSubTest();
792	if iOp1 == iOp2 and iOp2 != 5 and iOp2 != 13 and cbEffOp != cbMaxOp:
793	continue; # Don't know the high bit of the address ending up the result - skip it for now.
794	uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);
795	self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,
796	iOp1, iOp2, uInput, uResult);
797	else:
798	# SIB.
799	self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs);
800
801	return True;
802
803	def generateTest(self, oGen, sTestFnName):
804	oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));
805	#oGen.write(' int3\n');
806
807	self.generateStandardTests(oGen);
808
809	#oGen.write(' int3\n');
810	oGen.write(' ret\n');
811	oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));
812	return True;
813
814
815
816	class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
817	"""
818	Tests MOV Gv,Ev.
819	"""
820	def __init__(self):
821	InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);
822
823	@staticmethod
824	def calc_mov(cbEffOp, uInput, uCur, oGen):
825	""" Calculates the result of a mov instruction."""
826	if cbEffOp == 8:
827	return uInput & UINT64_MAX;
828	if cbEffOp == 4:
829	return uInput & UINT32_MAX;
830	if cbEffOp == 2:
831	return (uCur & 0xffffffffffff0000) \| (uInput & UINT16_MAX);
832	assert cbEffOp == 1; _ = oGen;
833	return (uCur & 0xffffffffffffff00) \| (uInput & UINT8_MAX);
834
835
836	class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
837	"""
838	Tests MOVSXD Gv,Ev.
839	"""
840	def __init__(self):
841	InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);
842
843	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
844	if cbEffOp == 8:
845	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));
846	elif cbEffOp == 4 or cbEffOp == 2:
847	abInstr = [];
848	if cbEffOp != oGen.oTarget.getDefOpBytes():
849	abInstr.append(X86_OP_PRF_SIZE_OP);
850	abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);
851	abInstr.append(0x63);
852	abInstr += calcModRmForTwoRegs(iOp1, iOp2);
853	oGen.writeInstrBytes(abInstr);
854	else:
855	assert False;
856	assert False;
857	return True;
858
859	def isApplicable(self, oGen):
860	return oGen.oTarget.is64Bit();
861
862	@staticmethod
863	def calc_movsxd(cbEffOp, uInput, uCur, oGen):
864	"""
865	Calculates the result of a movxsd instruction.
866	Returns the result value (cbMaxOp sized).
867	"""
868	_ = oGen;
869	if cbEffOp == 8 and (uInput & RT_BIT_32(31)):
870	return (UINT32_MAX << 32) \| (uInput & UINT32_MAX);
871	if cbEffOp == 2:
872	return (uCur & 0xffffffffffff0000) \| (uInput & 0xffff);
873	return uInput & UINT32_MAX;
874
875
876	## Instruction Tests.
877	g_aoInstructionTests = [
878	InstrTest_Mov_Gv_Ev(),
879	#InstrTest_MovSxD_Gv_Ev(),
880	];
881
882
883	class InstructionTestGen(object):
884	"""
885	Instruction Test Generator.
886	"""
887
888	## @name Test size
889	## @{
890	ksTestSize_Large = 'large';
891	ksTestSize_Medium = 'medium';
892	ksTestSize_Tiny = 'tiny';
893	## @}
894	kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny );
895
896
897
898	def __init__(self, oOptions):
899	self.oOptions = oOptions;
900	self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv];
901
902	# Calculate the number of output files.
903	self.cFiles = 1;
904	if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile:
905	self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile;
906	if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests):
907	self.cFiles += 1;
908
909	# Fix the known register values.
910	self.au64Regs = randUxxList(64, 16);
911	self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)];
912	self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)];
913	self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs;
914
915	# Declare state variables used while generating.
916	self.oFile = sys.stderr;
917	self.iFile = -1;
918	self.sFile = '';
919	self.dCheckFns = dict();
920	self.dMemSetupFns = dict();
921	self.d64BitConsts = dict();
922
923
924	#
925	# Methods used by instruction tests.
926	#
927
928	def write(self, sText):
929	""" Writes to the current output file. """
930	return self.oFile.write(unicode(sText));
931
932	def writeln(self, sText):
933	""" Writes a line to the current output file. """
934	self.write(sText);
935	return self.write('\n');
936
937	def writeInstrBytes(self, abInstr):
938	"""
939	Emits an instruction given as a sequence of bytes values.
940	"""
941	self.write(' db %#04x' % (abInstr[0],));
942	for i in range(1, len(abInstr)):
943	self.write(', %#04x' % (abInstr[i],));
944	return self.write('\n');
945
946	def newSubTest(self):
947	"""
948	Indicates that a new subtest has started.
949	"""
950	self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n');
951	return True;
952
953	def needGRegChecker(self, iReg1, iReg2 = None, iReg3 = None):
954	"""
955	Records the need for a given register checker function, returning its label.
956	"""
957	if iReg2 is not None:
958	if iReg3 is not None:
959	sName = '%s_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2], self.oTarget.asGRegs[iReg3],);
960	else:
961	sName = '%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2],);
962	else:
963	sName = '%s' % (self.oTarget.asGRegs[iReg1],);
964	assert iReg3 is None;
965
966	if sName in self.dCheckFns:
967	self.dCheckFns[sName] += 1;
968	else:
969	self.dCheckFns[sName] = 1;
970
971	return 'Common_Check_' + sName;
972
973	def needGRegMemSetup(self, cAddrBits, cbEffOp, iBaseReg = None, offDisp = None, iIndexReg = None, iScale = 1):
974	"""
975	Records the need for a given register checker function, returning its label.
976	"""
977	sName = '%ubit_U%u' % (cAddrBits, cbEffOp * 8,);
978	if iBaseReg is not None:
979	sName += '_%s' % (gregName(iBaseReg, cAddrBits),);
980	sName += '_x%u' % (iScale,);
981	if iIndexReg is not None:
982	sName += '_%s' % (gregName(iIndexReg, cAddrBits),);
983	if offDisp is not None:
984	sName += '_%#010x' % (offDisp & UINT32_MAX, );
985	if sName in self.dMemSetupFns:
986	self.dMemSetupFns[sName] += 1;
987	else:
988	self.dMemSetupFns[sName] = 1;
989	return 'Common_MemSetup_' + sName;
990
991	def need64BitConstant(self, uVal):
992	"""
993	Records the need for a 64-bit constant, returning its label.
994	These constants are pooled to attempt reduce the size of the whole thing.
995	"""
996	assert uVal >= 0 and uVal <= UINT64_MAX;
997	if uVal in self.d64BitConsts:
998	self.d64BitConsts[uVal] += 1;
999	else:
1000	self.d64BitConsts[uVal] = 1;
1001	return 'g_u64Const_0x%016x' % (uVal, );
1002
1003	def pushConst(self, uResult):
1004	"""
1005	Emits a push constant value, taking care of high values on 64-bit hosts.
1006	"""
1007	if self.oTarget.is64Bit() and uResult >= 0x80000000:
1008	self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),));
1009	else:
1010	self.write(' push dword 0x%x\n' % (uResult,));
1011	return True;
1012
1013	def getDispForMod(self, iMod, cbAlignment = 1):
1014	"""
1015	Get a set of address dispositions for a given addressing mode.
1016	The alignment restriction is for SIB scaling.
1017	"""
1018	assert cbAlignment in [1, 2, 4, 8];
1019	if iMod == 0:
1020	aoffDisp = [ None, ];
1021	elif iMod == 1:
1022	aoffDisp = [ 127 & ~cbAlignment, -128 ];
1023	elif iMod == 2:
1024	aoffDisp = [ 2147483647 & ~(cbAlignment - 1), -2147483648 ];
1025	else: assert False;
1026	return aoffDisp;
1027
1028
1029	#
1030	# Internal machinery.
1031	#
1032
1033	def _calcTestFunctionName(self, oInstrTest, iInstrTest):
1034	"""
1035	Calc a test function name for the given instruction test.
1036	"""
1037	sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName);
1038	return sName.replace(',', '_').replace(' ', '_').replace('%', '_');
1039
1040	def _generateFileHeader(self, ):
1041	"""
1042	Writes the file header.
1043	Raises exception on trouble.
1044	"""
1045	self.write('; $Id: InstructionTestGen.py 46856 2013-06-28 03:03:19Z vboxsync $\n'
1046	';; @file %s\n'
1047	'; Autogenerate by %s %s. DO NOT EDIT\n'
1048	';\n'
1049	'\n'
1050	';\n'
1051	'; Headers\n'
1052	';\n'
1053	'%%include "env-%s.mac"\n'
1054	% ( os.path.basename(self.sFile),
1055	os.path.basename(__file__), __version__[11:-1],
1056	self.oTarget.sName,
1057	) );
1058	# Target environment specific init stuff.
1059
1060	#
1061	# Global variables.
1062	#
1063	self.write('\n\n'
1064	';\n'
1065	'; Globals\n'
1066	';\n');
1067	self.write('VBINSTST_BEGINDATA\n'
1068	'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n'
1069	' dq 0\n'
1070	'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n'
1071	' dq 0\n'
1072	'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n'
1073	' dq 0\n'
1074	'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n'
1075	' dd 0\n'
1076	'VBINSTST_BEGINCODE\n'
1077	);
1078	self.write('%ifdef RT_ARCH_AMD64\n');
1079	for i in range(len(g_asGRegs64)):
1080	self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i]));
1081	self.write('%endif\n\n')
1082
1083	#
1084	# Common functions.
1085	#
1086
1087	# Loading common values.
1088	self.write('\n\n'
1089	'VBINSTST_BEGINPROC Common_LoadKnownValues\n'
1090	'%ifdef RT_ARCH_AMD64\n');
1091	for i in range(len(g_asGRegs64NoSp)):
1092	if g_asGRegs64NoSp[i]:
1093	self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],));
1094	self.write('%else\n');
1095	for i in range(8):
1096	if g_asGRegs32NoSp[i]:
1097	self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],));
1098	self.write('%endif\n'
1099	' ret\n'
1100	'VBINSTST_ENDPROC Common_LoadKnownValues\n'
1101	'\n');
1102
1103	self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n'
1104	'%ifdef RT_ARCH_AMD64\n');
1105	for i in range(len(g_asGRegs64NoSp)):
1106	if g_asGRegs64NoSp[i]:
1107	self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n'
1108	' je .ok_%u\n'
1109	' push %u ; register number\n'
1110	' push %s ; actual\n'
1111	' push qword [g_u64KnownValue_%s wrt rip] ; expected\n'
1112	' call VBINSTST_NAME(Common_BadValue)\n'
1113	'.ok_%u:\n'
1114	% ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,));
1115	self.write('%else\n');
1116	for i in range(8):
1117	if g_asGRegs32NoSp[i]:
1118	self.write(' cmp %s, 0x%x\n'
1119	' je .ok_%u\n'
1120	' push %u ; register number\n'
1121	' push %s ; actual\n'
1122	' push dword 0x%x ; expected\n'
1123	' call VBINSTST_NAME(Common_BadValue)\n'
1124	'.ok_%u:\n'
1125	% ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,));
1126	self.write('%endif\n'
1127	' ret\n'
1128	'VBINSTST_ENDPROC Common_CheckKnownValues\n'
1129	'\n');
1130
1131	return True;
1132
1133	def _generateMemSetupFunctions(self):
1134	"""
1135	Generates the memory setup functions.
1136	"""
1137	cDefAddrBits = self.oTarget.getDefAddrBits();
1138	for sName in self.dMemSetupFns:
1139	# Unpack it.
1140	asParams = sName.split('_');
1141	cAddrBits = int(asParams[0][:-3]);
1142	cEffOpBits = int(asParams[1][1:]);
1143	if cAddrBits == 64: asAddrGRegs = g_asGRegs64;
1144	elif cAddrBits == 32: asAddrGRegs = g_asGRegs32;
1145	else: asAddrGRegs = g_asGRegs16;
1146
1147	i = 2;
1148	if i < len(asParams[i]) and asParams[i]:
1149	sBaseReg = asParams[i];
1150	i += 1
1151	try:
1152	iBaseReg = asAddrGRegs.index(sBaseReg);
1153	except ValueError:
1154	assert False, 'sBaseReg=%s' % (sBaseReg,);
1155	raise;
1156
1157	u32Disp = None;
1158	if i < len(asParams) and len(asParams[i]) == 10:
1159	u32Disp = long(asParams[i], 16);
1160	i += 1;
1161
1162	sIndexReg = None;
1163	iIndexReg = None;
1164	if i < len(asParams):
1165	sIndexReg = asParams[i];
1166	iBaseReg = asAddrGRegs.index(sBaseReg);
1167	i += 1;
1168
1169	iScale = 1;
1170	if i < len(asParams):
1171	iScale = int(asParams[i]); assert iScale in [2, 4, 8];
1172	i += 1;
1173
1174	assert i == len(asParams), 'i=%d len=%d len[i]=%d (%s)' % (i, len(asParams), len(asParams[i]), asParams[i],);
1175
1176	# Prologue.
1177	iTmpReg1 = 0 if iBaseReg != 0 else 1;
1178	self.write('\n\n'
1179	'VBINSTST_BEGINPROC Common_MemSetup_%s\n'
1180	' MY_PUSH_FLAGS\n'
1181	' push %s\n'
1182	% (sName, self.oTarget.asGRegs[iTmpReg1], ));
1183	self.write('; cAddrBits=%s cEffOpBits=%s iBaseReg=%s u32Disp=%s iIndexReg=%s iScale=%s\n'
1184	% (cAddrBits, cEffOpBits, iBaseReg, u32Disp, iIndexReg, iScale,));
1185
1186	# Figure out what to use.
1187	if cEffOpBits == 64:
1188	sTmpReg1 = g_asGRegs64[iTmpReg1];
1189	sDataVar = 'VBINSTST_NAME(g_u64Data)';
1190	elif cEffOpBits == 32:
1191	sTmpReg1 = g_asGRegs32[iTmpReg1];
1192	sDataVar = 'VBINSTST_NAME(g_u32Data)';
1193	elif cEffOpBits == 16:
1194	sTmpReg1 = g_asGRegs16[iTmpReg1];
1195	sDataVar = 'VBINSTST_NAME(g_u16Data)';
1196	else:
1197	assert cEffOpBits == 8;
1198	sTmpReg1 = g_asGRegs8Rex[iTmpReg1];
1199	sDataVar = 'VBINSTST_NAME(g_u8Data)';
1200
1201	# Load the value and mem address, sorting the value there.
1202	self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,));
1203	if cAddrBits >= cDefAddrBits:
1204	self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,));
1205	self.write(' lea %s, [%s xWrtRIP]\n' % (sBaseReg, sDataVar,));
1206	else:
1207
1208	if cAddrBits == 16:
1209	self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sBaseReg,));
1210	else:
1211	self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sBaseReg,));
1212	self.write(' add %s, %s\n' % (sBaseReg, (randU16() << cEffOpBits) & 0xfff, ));
1213	self.write(' mov [%s], %s\n' % (sBaseReg, sTmpReg1, ));
1214
1215	# Adjust for disposition and scaling.
1216	if u32Disp is not None:
1217	self.write(' sub %s, %d\n' % ( sBaseReg, convU32ToSigned(u32Disp), ));
1218	if iIndexReg is not None:
1219	uIdxRegVal = randUxx(cAddrBits);
1220	self.write(' mov %s, %u\n' % ( sIndexReg, uIdxRegVal,));
1221	if cAddrBits == 64:
1222	self.write(' sub %s, %#06x\n' % ( sBaseReg, uIdxRegVal * iScale, ));
1223	elif cAddrBits == 16:
1224	self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, ));
1225	else:
1226	assert cAddrBits == 16;
1227	self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT16_MAX, ));
1228
1229	# Set upper bits that's supposed to be unused.
1230	if cDefAddrBits > cAddrBits or cAddrBits == 16:
1231	if cDefAddrBits == 64:
1232	assert cAddrBits == 32;
1233	self.write(' mov %s, %#018x\n'
1234	' or %s, %s\n'
1235	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
1236	g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],));
1237	if iIndexReg is not None:
1238	self.write(' mov %s, %#018x\n'
1239	' or %s, %s\n'
1240	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
1241	g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],));
1242	else:
1243	assert cDefAddrBits == 32; assert cAddrBits == 16;
1244	self.write(' or %s, %#010x\n'
1245	% ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, ));
1246	if iIndexReg is not None:
1247	self.write(' or %s, %#010x\n'
1248	% ( g_asGRegs32[iIndexReg], randU32() & 0xffff0000, ));
1249
1250	# Epilogue.
1251	self.write(' pop %s\n'
1252	' MY_POP_FLAGS\n'
1253	' ret sCB\n'
1254	'VBINSTST_ENDPROC Common_MemSetup_%s\n'
1255	% ( self.oTarget.asGRegs[iTmpReg1], sName,));
1256
1257
1258	def _generateFileFooter(self):
1259	"""
1260	Generates file footer.
1261	"""
1262
1263	# Register checking functions.
1264	for sName in self.dCheckFns:
1265	asRegs = sName.split('_');
1266	sPushSize = 'dword';
1267
1268	# Prologue
1269	self.write('\n\n'
1270	'; Checks 1 or more register values, expected values pushed on the stack.\n'
1271	'; To save space, the callee cleans up the stack.'
1272	'; Ref count: %u\n'
1273	'VBINSTST_BEGINPROC Common_Check_%s\n'
1274	' MY_PUSH_FLAGS\n'
1275	% ( self.dCheckFns[sName], sName, ) );
1276
1277	# Register checks.
1278	iRegPrev = -1;
1279	for i in range(len(asRegs)):
1280	sReg = asRegs[i];
1281	iReg = self.oTarget.asGRegs.index(sReg);
1282	if i == asRegs.index(sReg): # Only check once, i.e. input = output reg.
1283	self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n'
1284	' je .equal%u\n'
1285	' push %s %u ; register number\n'
1286	' push %s ; actual\n'
1287	' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB]\n'
1288	' push %s ; expected\n'
1289	' call VBINSTST_NAME(Common_BadValue)\n'
1290	' pop %s\n'
1291	' pop %s\n'
1292	' pop %s\n'
1293	'.equal%u:\n'
1294	% ( sReg, i, i, sPushSize, iReg, sReg, sReg, sReg, sReg, sReg, sReg, i, ) );
1295
1296
1297	# Restore known register values and check the other registers.
1298	for sReg in asRegs:
1299	if self.oTarget.is64Bit():
1300	self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg, sReg,));
1301	else:
1302	iReg = self.oTarget.asGRegs.index(sReg)
1303	self.write(' mov %s, 0x%x\n' % (sReg, self.au32Regs[iReg],));
1304	self.write(' MY_POP_FLAGS\n'
1305	' call VBINSTST_NAME(Common_CheckKnownValues)\n'
1306	' ret sCB*%u\n'
1307	'VBINSTST_ENDPROC Common_Check_%s\n'
1308	% (len(asRegs), sName,));
1309
1310	# memory setup functions
1311	self._generateMemSetupFunctions();
1312
1313	# 64-bit constants.
1314	if len(self.d64BitConsts) > 0:
1315	self.write('\n\n'
1316	';\n'
1317	'; 64-bit constants\n'
1318	';\n');
1319	for uVal in self.d64BitConsts:
1320	self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self.d64BitConsts[uVal], ) );
1321
1322	return True;
1323
1324	def _generateTests(self):
1325	"""
1326	Generate the test cases.
1327	"""
1328	for self.iFile in range(self.cFiles):
1329	if self.cFiles == 1:
1330	self.sFile = '%s.asm' % (self.oOptions.sOutputBase,)
1331	else:
1332	self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile)
1333	self.oFile = sys.stdout;
1334	if self.oOptions.sOutputBase != '-':
1335	self.oFile = io.open(self.sFile, 'w', encoding = 'utf-8');
1336
1337	self._generateFileHeader();
1338
1339	# Calc the range.
1340	iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile;
1341	iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile;
1342	if iInstrTestEnd > len(g_aoInstructionTests):
1343	iInstrTestEnd = len(g_aoInstructionTests);
1344
1345	# Generate the instruction tests.
1346	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1347	oInstrTest = g_aoInstructionTests[iInstrTest];
1348	self.write('\n'
1349	'\n'
1350	';\n'
1351	'; %s\n'
1352	';\n'
1353	% (oInstrTest.sName,));
1354	oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest));
1355
1356	# Generate the main function.
1357	self.write('\n\n'
1358	'VBINSTST_BEGINPROC TestInstrMain\n'
1359	' MY_PUSH_ALL\n'
1360	' sub xSP, 40h\n'
1361	'\n');
1362
1363	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1364	oInstrTest = g_aoInstructionTests[iInstrTest];
1365	if oInstrTest.isApplicable(self):
1366	self.write('%%ifdef ASM_CALL64_GCC\n'
1367	' lea rdi, [.szInstr%03u wrt rip]\n'
1368	'%%elifdef ASM_CALL64_MSC\n'
1369	' lea rcx, [.szInstr%03u wrt rip]\n'
1370	'%%else\n'
1371	' mov xAX, .szInstr%03u\n'
1372	' mov [xSP], xAX\n'
1373	'%%endif\n'
1374	' VBINSTST_CALL_FN_SUB_TEST\n'
1375	' call VBINSTST_NAME(%s)\n'
1376	% ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest)));
1377
1378	self.write('\n'
1379	' add xSP, 40h\n'
1380	' MY_POP_ALL\n'
1381	' ret\n\n');
1382	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1383	self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,));
1384	self.write('VBINSTST_ENDPROC TestInstrMain\n\n');
1385
1386	self._generateFileFooter();
1387	if self.oOptions.sOutputBase != '-':
1388	self.oFile.close();
1389	self.oFile = None;
1390	self.sFile = '';
1391
1392	return RTEXITCODE_SUCCESS;
1393
1394	def _runMakefileMode(self):
1395	"""
1396	Generate a list of output files on standard output.
1397	"""
1398	if self.cFiles == 1:
1399	print('%s.asm' % (self.oOptions.sOutputBase,));
1400	else:
1401	print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles)));
1402	return RTEXITCODE_SUCCESS;
1403
1404	def run(self):
1405	"""
1406	Generates the tests or whatever is required.
1407	"""
1408	if self.oOptions.fMakefileMode:
1409	return self._runMakefileMode();
1410	return self._generateTests();
1411
1412	@staticmethod
1413	def main():
1414	"""
1415	Main function a la C/C++. Returns exit code.
1416	"""
1417
1418	#
1419	# Parse the command line.
1420	#
1421	oParser = OptionParser(version = __version__[11:-1].strip());
1422	oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False,
1423	help = 'Special mode for use to output a list of output files for the benefit of '
1424	'the make program (kmk).');
1425	oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '<instr-per-file>', type = 'int', default = 9999999,
1426	help = 'Number of instruction to test per output file.');
1427	oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '<file>', default = None,
1428	help = 'The output file base name, no suffix please. Required.');
1429	oParser.add_option('--target', dest = 'sTargetEnv', metavar = '<target>',
1430	default = 'iprt-r3-32',
1431	choices = g_dTargetEnvs.keys(),
1432	help = 'The target environment. Choices: %s'
1433	% (', '.join(sorted(g_dTargetEnvs.keys())),));
1434	oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium,
1435	choices = InstructionTestGen.kasTestSizes,
1436	help = 'Selects the test size.');
1437
1438	(oOptions, asArgs) = oParser.parse_args();
1439	if len(asArgs) > 0:
1440	oParser.print_help();
1441	return RTEXITCODE_SYNTAX
1442	if oOptions.sOutputBase is None:
1443	print('syntax error: Missing required option --output-base.', file = sys.stderr);
1444	return RTEXITCODE_SYNTAX
1445
1446	#
1447	# Instantiate the program class and run it.
1448	#
1449	oProgram = InstructionTestGen(oOptions);
1450	return oProgram.run();
1451
1452
1453	if __name__ == '__main__':
1454	sys.exit(InstructionTestGen.main());
1455

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source: vbox/trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py@ 46856

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