InstructionTestGen.py@ 46893

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1	#!/usr/bin/env python
2	# -- coding: utf-8 --
3	# $Id: InstructionTestGen.py 46893 2013-07-01 20:38:16Z vboxsync $
4
5	"""
6	Instruction Test Generator.
7	"""
8
9	from __future__ import print_function;
10
11	__copyright__ = \
12	"""
13	Copyright (C) 2012-2013 Oracle Corporation
14
15	Oracle Corporation confidential
16	All rights reserved
17	"""
18	__version__ = "$Revision: 46893 $";
19
20
21	# Standard python imports.
22	import io;
23	import os;
24	from optparse import OptionParser
25	import random;
26	import sys;
27
28
29	## @name Exit codes
30	## @{
31	RTEXITCODE_SUCCESS = 0;
32	RTEXITCODE_SYNTAX = 2;
33	## @}
34
35	## @name Various C macros we're used to.
36	## @{
37	UINT8_MAX = 0xff
38	UINT16_MAX = 0xffff
39	UINT32_MAX = 0xffffffff
40	UINT64_MAX = 0xffffffffffffffff
41	def RT_BIT_32(iBit): # pylint: disable=C0103
42	""" 32-bit one bit mask. """
43	return 1 << iBit;
44	def RT_BIT_64(iBit): # pylint: disable=C0103
45	""" 64-bit one bit mask. """
46	return 1 << iBit;
47	## @}
48
49
50	## @name ModR/M
51	## @{
52	X86_MODRM_RM_MASK = 0x07;
53	X86_MODRM_REG_MASK = 0x38;
54	X86_MODRM_REG_SMASK = 0x07;
55	X86_MODRM_REG_SHIFT = 3;
56	X86_MODRM_MOD_MASK = 0xc0;
57	X86_MODRM_MOD_SMASK = 0x03;
58	X86_MODRM_MOD_SHIFT = 6;
59	## @}
60
61	## @name SIB
62	## @{
63	X86_SIB_BASE_MASK = 0x07;
64	X86_SIB_INDEX_MASK = 0x38;
65	X86_SIB_INDEX_SMASK = 0x07;
66	X86_SIB_INDEX_SHIFT = 3;
67	X86_SIB_SCALE_MASK = 0xc0;
68	X86_SIB_SCALE_SMASK = 0x03;
69	X86_SIB_SCALE_SHIFT = 6;
70	## @}
71
72	## @name Prefixes
73	## @
74	X86_OP_PRF_CS = 0x2e;
75	X86_OP_PRF_SS = 0x36;
76	X86_OP_PRF_DS = 0x3e;
77	X86_OP_PRF_ES = 0x26;
78	X86_OP_PRF_FS = 0x64;
79	X86_OP_PRF_GS = 0x65;
80	X86_OP_PRF_SIZE_OP = 0x66;
81	X86_OP_PRF_SIZE_ADDR = 0x67;
82	X86_OP_PRF_LOCK = 0xf0;
83	X86_OP_PRF_REPZ = 0xf2;
84	X86_OP_PRF_REPNZ = 0xf3;
85	X86_OP_REX_B = 0x41;
86	X86_OP_REX_X = 0x42;
87	X86_OP_REX_R = 0x44;
88	X86_OP_REX_W = 0x48;
89	## @}
90
91
92	## @name General registers
93	## @
94	X86_GREG_xAX = 0
95	X86_GREG_xCX = 1
96	X86_GREG_xDX = 2
97	X86_GREG_xBX = 3
98	X86_GREG_xSP = 4
99	X86_GREG_xBP = 5
100	X86_GREG_xSI = 6
101	X86_GREG_xDI = 7
102	X86_GREG_x8 = 8
103	X86_GREG_x9 = 9
104	X86_GREG_x10 = 10
105	X86_GREG_x11 = 11
106	X86_GREG_x12 = 12
107	X86_GREG_x13 = 13
108	X86_GREG_x14 = 14
109	X86_GREG_x15 = 15
110	## @}
111
112
113	## @name Register names.
114	## @{
115	g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
116	g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
117	g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',
118	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
119	g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',
120	'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
121	g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',
122	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
123	g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',
124	'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
125	g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh');
126	g_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil',
127	'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b',
128	'ah', 'ch', 'dh', 'bh');
129	## @}
130
131
132	## @name Random
133	## @{
134	g_oMyRand = random.SystemRandom()
135	def randU16():
136	""" Unsigned 16-bit random number. """
137	return g_oMyRand.getrandbits(16);
138
139	def randU32():
140	""" Unsigned 32-bit random number. """
141	return g_oMyRand.getrandbits(32);
142
143	def randU64():
144	""" Unsigned 64-bit random number. """
145	return g_oMyRand.getrandbits(64);
146
147	def randUxx(cBits):
148	""" Unsigned 8-, 16-, 32-, or 64-bit random number. """
149	return g_oMyRand.getrandbits(cBits);
150
151	def randUxxList(cBits, cElements):
152	""" List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """
153	return [randUxx(cBits) for _ in range(cElements)];
154	## @}
155
156
157
158
159	## @name Instruction Emitter Helpers
160	## @{
161
162	def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):
163	"""
164	Calculates a rex prefix if neccessary given the two registers
165	and optional rex size prefixes.
166	Returns an empty array if not necessary.
167	"""
168	bRex = bOtherRexPrefixes;
169	if iReg >= 8:
170	bRex \|= X86_OP_REX_R;
171	if iRm >= 8:
172	bRex \|= X86_OP_REX_B;
173	if bRex == 0:
174	return [];
175	return [bRex,];
176
177	def calcModRmForTwoRegs(iReg, iRm):
178	"""
179	Calculate the RM byte for two registers.
180	Returns an array with one byte in it.
181	"""
182	bRm = (0x3 << X86_MODRM_MOD_SHIFT) \
183	\| ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \
184	\| (iRm & X86_MODRM_RM_MASK);
185	return [bRm,];
186
187	## @}
188
189
190	## @name Misc
191	## @{
192
193	def convU32ToSigned(u32):
194	""" Converts a 32-bit unsigned value to 32-bit signed. """
195	if u32 < 0x80000000:
196	return u32;
197	return u32 - UINT32_MAX - 1;
198
199	def rotateLeftUxx(cBits, uVal, cShift):
200	""" Rotate a xx-bit wide unsigned number to the left. """
201	assert cShift < cBits;
202
203	if cBits == 16:
204	uMask = UINT16_MAX;
205	elif cBits == 32:
206	uMask = UINT32_MAX;
207	elif cBits == 64:
208	uMask = UINT64_MAX;
209	else:
210	assert cBits == 8;
211	uMask = UINT8_MAX;
212
213	uVal &= uMask;
214	uRet = (uVal << cShift) & uMask;
215	uRet \|= (uVal >> (cBits - cShift));
216	return uRet;
217
218	def rotateRightUxx(cBits, uVal, cShift):
219	""" Rotate a xx-bit wide unsigned number to the right. """
220	assert cShift < cBits;
221
222	if cBits == 16:
223	uMask = UINT16_MAX;
224	elif cBits == 32:
225	uMask = UINT32_MAX;
226	elif cBits == 64:
227	uMask = UINT64_MAX;
228	else:
229	assert cBits == 8;
230	uMask = UINT8_MAX;
231
232	uVal &= uMask;
233	uRet = (uVal >> cShift);
234	uRet \|= (uVal << (cBits - cShift)) & uMask;
235	return uRet;
236
237	def gregName(iReg, cBits, fRexByteRegs = True):
238	""" Gets the name of a general register by index and width. """
239	if cBits == 64:
240	return g_asGRegs64[iReg];
241	if cBits == 32:
242	return g_asGRegs32[iReg];
243	if cBits == 16:
244	return g_asGRegs16[iReg];
245	assert cBits == 8;
246	if fRexByteRegs:
247	return g_asGRegs8Rex[iReg];
248	return g_asGRegs8[iReg];
249
250	## @}
251
252
253	class TargetEnv(object):
254	"""
255	Target Runtime Environment.
256	"""
257
258	## @name CPU Modes
259	## @{
260	ksCpuMode_Real = 'real';
261	ksCpuMode_Protect = 'prot';
262	ksCpuMode_Paged = 'paged';
263	ksCpuMode_Long = 'long';
264	ksCpuMode_V86 = 'v86';
265	## @}
266
267	## @name Instruction set.
268	## @{
269	ksInstrSet_16 = '16';
270	ksInstrSet_32 = '32';
271	ksInstrSet_64 = '64';
272	## @}
273
274	def __init__(self, sName,
275	sInstrSet = ksInstrSet_32,
276	sCpuMode = ksCpuMode_Paged,
277	iRing = 3,
278	):
279	self.sName = sName;
280	self.sInstrSet = sInstrSet;
281	self.sCpuMode = sCpuMode;
282	self.iRing = iRing;
283	self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;
284	self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;
285
286	def isUsingIprt(self):
287	""" Whether it's an IPRT environment or not. """
288	return self.sName.startswith('iprt');
289
290	def is64Bit(self):
291	""" Whether it's a 64-bit environment or not. """
292	return self.sInstrSet == self.ksInstrSet_64;
293
294	def getDefOpBits(self):
295	""" Get the default operand size as a bit count. """
296	if self.sInstrSet == self.ksInstrSet_16:
297	return 16;
298	return 32;
299
300	def getDefOpBytes(self):
301	""" Get the default operand size as a byte count. """
302	return self.getDefOpBits() / 8;
303
304	def getMaxOpBits(self):
305	""" Get the max operand size as a bit count. """
306	if self.sInstrSet == self.ksInstrSet_64:
307	return 64;
308	return 32;
309
310	def getMaxOpBytes(self):
311	""" Get the max operand size as a byte count. """
312	return self.getMaxOpBits() / 8;
313
314	def getDefAddrBits(self):
315	""" Get the default address size as a bit count. """
316	if self.sInstrSet == self.ksInstrSet_16:
317	return 16;
318	if self.sInstrSet == self.ksInstrSet_32:
319	return 32;
320	return 64;
321
322	def getDefAddrBytes(self):
323	""" Get the default address size as a byte count. """
324	return self.getDefAddrBits() / 8;
325
326	def getGRegCount(self, cbEffBytes = 4):
327	""" Get the number of general registers. """
328	if self.sInstrSet == self.ksInstrSet_64:
329	if cbEffBytes == 1:
330	return 16 + 4;
331	return 16;
332	return 8;
333
334	def randGRegNoSp(self, cbEffBytes = 4):
335	""" Returns a random general register number, excluding the SP register. """
336	iReg = randU16() % self.getGRegCount(cbEffBytes);
337	while iReg == X86_GREG_xSP:
338	iReg = randU16() % self.getGRegCount(cbEffBytes);
339	return iReg;
340
341	def randGRegNoSpList(self, cItems, cbEffBytes = 4):
342	""" List of randGRegNoSp values. """
343	aiRegs = [];
344	for i in range(cItems):
345	aiRegs.append(self.randGRegNoSp(cbEffBytes));
346	return aiRegs;
347
348	def getAddrModes(self):
349	""" Gets a list of addressing mode (16, 32, or/and 64). """
350	if self.sInstrSet == self.ksInstrSet_16:
351	return [16, 32];
352	if self.sInstrSet == self.ksInstrSet_32:
353	return [32, 16];
354	return [64, 32];
355
356	def is8BitHighGReg(self, cbEffOp, iGReg):
357	""" Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """
358	assert cbEffOp in [1, 2, 4, 8];
359	if cbEffOp == 1:
360	if iGReg >= 16:
361	return True;
362	if iGReg >= 4 and not self.is64Bit():
363	return True;
364	return False;
365
366
367
368	## Target environments.
369	g_dTargetEnvs = {
370	'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),
371	'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),
372	};
373
374
375	class InstrTestBase(object):
376	"""
377	Base class for testing one instruction.
378	"""
379
380	def __init__(self, sName, sInstr = None):
381	self.sName = sName;
382	self.sInstr = sInstr if sInstr else sName.split()[0];
383
384	def isApplicable(self, oGen):
385	"""
386	Tests if the instruction test is applicable to the selected environment.
387	"""
388	_ = oGen;
389	return True;
390
391	def generateTest(self, oGen, sTestFnName):
392	"""
393	Emits the test assembly code.
394	"""
395	oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));
396	return True;
397
398	def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):
399	""" Generate a list of inputs. """
400	if fLong:
401	#
402	# Try do extremes as well as different ranges of random numbers.
403	#
404	auRet = [0, 1, ];
405	if cbMaxOp >= 1:
406	auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];
407	if cbMaxOp >= 2:
408	auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];
409	if cbMaxOp >= 4:
410	auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];
411	if cbMaxOp >= 8:
412	auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];
413
414	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
415	for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):
416	if cBits < cbMaxOp * 8:
417	auRet += randUxxList(cBits, cValues);
418	cWanted = 16;
419	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
420	for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):
421	if cBits < cbMaxOp * 8:
422	auRet += randUxxList(cBits, cValues);
423	cWanted = 64;
424	else:
425	for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):
426	if cBits < cbMaxOp * 8:
427	auRet += randUxxList(cBits, cValues);
428	cWanted = 168;
429	if len(auRet) < cWanted:
430	auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));
431	else:
432	#
433	# Short list, just do some random numbers.
434	#
435	auRet = [];
436	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
437	auRet += randUxxList(cbMaxOp, 1);
438	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
439	auRet += randUxxList(cbMaxOp, 2);
440	else:
441	auRet = [];
442	for cBits in (8, 16, 32, 64):
443	if cBits < cbMaxOp * 8:
444	auRet += randUxxList(cBits, 1);
445	return auRet;
446
447
448	class InstrTest_MemOrGreg_2_Greg(InstrTestBase):
449	"""
450	Instruction reading memory or general register and writing the result to a
451	general register.
452	"""
453
454	def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):
455	InstrTestBase.__init__(self, sName, sInstr);
456	self.fnCalcResult = fnCalcResult;
457	self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);
458
459	## @name Test Instruction Writers
460	## @{
461
462	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
463	""" Writes the instruction with two general registers as operands. """
464	fRexByteRegs = oGen.oTarget.is64Bit();
465	oGen.write(' %s %s, %s\n'
466	% (self.sInstr, gregName(iOp1, cbEffOp * 8, fRexByteRegs), gregName(iOp2, cbEffOp * 8, fRexByteRegs),));
467	return True;
468
469	def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):
470	""" Writes the instruction with two general registers as operands. """
471	oGen.write(' ');
472	if iOp2 == 13 and iMod == 0 and cAddrBits == 64:
473	oGen.write('altrexb '); # Alternative encoding for rip relative addressing.
474	if cbEffOp == 8:
475	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
476	elif cbEffOp == 4:
477	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));
478	elif cbEffOp == 2:
479	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
480	elif cbEffOp == 1:
481	oGen.write('%s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));
482	else:
483	assert False;
484
485	if (iOp2 == 5 or iOp2 == 13) and iMod == 0:
486	oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))
487	if oGen.oTarget.is64Bit():
488	oGen.write(' wrt rip');
489	else:
490	if iMod == 1:
491	oGen.write('byte %d + ' % (offDisp,));
492	elif iMod == 2:
493	oGen.write('dword %d + ' % (offDisp,));
494	else:
495	assert iMod == 0;
496
497	if cAddrBits == 64:
498	oGen.write(g_asGRegs64[iOp2]);
499	elif cAddrBits == 32:
500	oGen.write(g_asGRegs32[iOp2]);
501	elif cAddrBits == 16:
502	assert False; ## @todo implement 16-bit addressing.
503	else:
504	assert False, str(cAddrBits);
505
506	oGen.write(']\n');
507	return True;
508
509	def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
510	""" Writes the instruction taking a register and a label (base only w/o reg), SIB form. """
511	assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16;
512	if cAddrBits == 64:
513	# Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit
514	# and we cannot (yet) make assumtions about where we're loaded.
515	## @todo Enable testing this in environments where we can make assumptions (boot sector).
516	oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
517	% ( self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
518	else:
519	oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'
520	% ( iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));
521	return True;
522
523	def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
524	""" Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """
525	assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16;
526	# Note! Using altsibxN to force scaled encoding. This is only really a
527	# necessity for iScale=1, but doesn't hurt for the rest.
528	oGen.write(' altsibx%u %s %s, [%s * %#x'
529	% (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iIndexReg, cAddrBits), iScale,));
530	if offDisp is not None:
531	oGen.write(' + %#x' % (offDisp,));
532	oGen.write(']\n');
533	_ = iBaseReg;
534	return True;
535
536	def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
537	""" Writes the instruction taking a register and base only (with reg), SIB form. """
538	oGen.write(' altsibx%u %s %s, [%s'
539	% (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iBaseReg, cAddrBits),));
540	if offDisp is not None:
541	oGen.write(' + %#x' % (offDisp,));
542	oGen.write(']\n');
543	_ = iIndexReg;
544	return True;
545
546	def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):
547	""" Writes tinstruction taking a register and full featured SIB form address. """
548	# Note! From the looks of things, yasm will encode the following instructions the same way:
549	# mov eax, [rsi*1 + rbx]
550	# mov eax, [rbx + rsi*1]
551	# So, when there are two registers involved, the '*1' selects
552	# which is index and which is base.
553	oGen.write(' %s %s, [%s + %s * %u'
554	% ( self.sInstr, gregName(iOp1, cbEffOp * 8),
555	gregName(iBaseReg, cAddrBits), gregName(iIndexReg, cAddrBits), iScale,));
556	if offDisp is not None:
557	oGen.write(' + %#x' % (offDisp,));
558	oGen.write(']\n');
559	return True;
560
561	## @}
562
563
564	## @name Memory setups
565	## @{
566	def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput):
567	""" Sets up memory for a memory read. """
568	oGen.pushConst(uInput);
569	oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
570	return True;
571
572	def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None):
573	""" Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """
574	oGen.pushConst(uInput);
575	oGen.write(' call VBINSTST_NAME(%s)\n'
576	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),));
577	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],));
578	return True;
579
580	def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None):
581	""" Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """
582	oGen.pushConst(uInput);
583	oGen.write(' call VBINSTST_NAME(%s)\n'
584	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),));
585	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));
586	return True;
587
588	def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp):
589	""" Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """
590	oGen.pushConst(uInput);
591	oGen.write(' call VBINSTST_NAME(%s)\n'
592	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp,
593	iIndexReg = iIndexReg, iScale = iScale),));
594	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));
595	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],));
596	return True;
597
598	def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):
599	""" Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """
600	oGen.pushConst(uInput);
601	assert offDisp is None or iMod != 0;
602	if (iOp2 != 5 and iOp2 != 13) or iMod != 0:
603	oGen.write(' call VBINSTST_NAME(%s)\n'
604	% (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));
605	else:
606	oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
607	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
608	return True;
609
610	## @}
611
612	def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult):
613	""" Generate one standard instr greg,greg test. """
614	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
615	oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,));
616	if iOp1X != iOp2X:
617	oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],));
618	self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);
619	oGen.pushConst(uResult);
620	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X if iOp1X != iOp2X else None),));
621	_ = cbMaxOp;
622	return True;
623
624	def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput):
625	""" High 8-bit registers are a real pain! """
626	assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2);
627	# Figure out the register indexes of the max op sized regs involved.
628	iOp1X = iOp1 & 3;
629	iOp2X = iOp2 & 3;
630	oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,));
631
632	# Calculate unshifted result.
633	if iOp1X != iOp2X:
634	uCur = oGen.auRegValues[iOp1X];
635	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
636	uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);
637	else:
638	uCur = uInput;
639	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
640	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
641	uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);
642	else:
643	uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8);
644	uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);
645
646
647	# Rotate the input and/or result to match their max-op-sized registers.
648	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
649	uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8);
650	if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):
651	uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8);
652
653	# Hand it over to an overridable worker method.
654	return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult);
655
656
657	def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
658	""" Generate mode 0, 1 and 2 test for the R/M=iOp2. """
659	if cAddrBits == 16:
660	_ = cbMaxOp;
661	else:
662	iMod = 0; # No disp, except for i=5.
663	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
664	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);
665	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);
666	oGen.pushConst(uResult);
667	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
668
669	if iOp2 != 5 and iOp2 != 13:
670	iMod = 1;
671	for offDisp in oGen.getDispForMod(iMod):
672	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
673	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
674	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
675	oGen.pushConst(uResult);
676	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
677
678	iMod = 2;
679	for offDisp in oGen.getDispForMod(iMod):
680	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
681	self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
682	self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
683	oGen.pushConst(uResult);
684	oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
685
686	return True;
687
688	def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913
689	iBaseReg, iIndexReg, iScale, uInput, uResult):
690	""" Generate one SIB variations. """
691	for offDisp in oGen.getDispForMod(iMod, cbEffOp):
692	if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0):
693	if iIndexReg == 4:
694	if cAddrBits == 64:
695	continue; # skipping.
696	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
697	self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput);
698	self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
699	sChecker = oGen.needGRegChecker(iOp1);
700	else:
701	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
702	self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp);
703	self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
704	sChecker = oGen.needGRegChecker(iOp1, iIndexReg);
705	else:
706	oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
707	if iIndexReg == 4:
708	self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp);
709	self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
710	sChecker = oGen.needGRegChecker(iOp1, iBaseReg);
711	else:
712	if iIndexReg == iBaseReg and iScale == 1 and offDisp is not None and (offDisp & 1):
713	if offDisp < 0: offDisp += 1;
714	else: offDisp -= 1;
715	self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg,
716	iIndexReg, iScale, uInput, offDisp);
717	self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);
718	sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg);
719	oGen.pushConst(uResult);
720	oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,));
721	_ = cbMaxOp;
722	return True;
723
724	def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs, oBaseRegRange, oIndexRegRange):
725	""" Generate all SIB variations for the given iOp1 (reg) value. """
726	assert cAddrBits in [32, 64];
727	for iBaseReg in oBaseRegRange:
728	for iIndexReg in oIndexRegRange:
729	if iBaseReg == X86_GREG_xSP: # no RSP testing atm.
730	continue;
731
732	for iMod in [0, 1, 2]:
733	if iBaseReg == iOp1 and ((iBaseReg != 5 and iBaseReg != 13) or iMod != 0) and cAddrBits != cbMaxOp:
734	continue; # Don't know the high bit of the address ending up the result - skip it for now.
735	if iIndexReg == iOp1 and iIndexReg != 4 and cAddrBits != cbMaxOp:
736	continue; # Don't know the high bit of the address ending up the result - skip it for now.
737
738	for iScale in (1, 2, 4, 8):
739	for uInput in auInputs:
740	oGen.newSubTest();
741	uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);
742	self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod,
743	iBaseReg, iIndexReg, iScale, uInput, uResult);
744
745	return True;
746
747
748	def generateStandardTests(self, oGen):
749	""" Generate standard tests. """
750
751	# Parameters.
752	cbDefOp = oGen.oTarget.getDefOpBytes();
753	cbMaxOp = oGen.oTarget.getMaxOpBytes();
754	auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);
755	auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);
756	iLongOp1 = oGen.oTarget.randGRegNoSp();
757	iLongOp2 = oGen.oTarget.randGRegNoSp();
758	oOp2Range = None;
759	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
760	oOp2Range = [iLongOp2,];
761
762	# Register tests
763	if False:
764	for cbEffOp in self.acbOpVars:
765	if cbEffOp > cbMaxOp:
766	continue;
767	oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp));
768	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
769	oOp2Range = [iLongOp2,];
770	oGen.write('; cbEffOp=%u\n' % (cbEffOp,));
771
772	for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)):
773	if iOp1 == X86_GREG_xSP:
774	continue; # Cannot test xSP atm.
775	for iOp2 in oOp2Range:
776	if (iOp2 >= 16 and iOp1 in range(4, 16)) \
777	or (iOp1 >= 16 and iOp2 in range(4, 16)):
778	continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL.
779	if iOp2 == X86_GREG_xSP:
780	continue; # Cannot test xSP atm.
781
782	oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp));
783	for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):
784	oGen.newSubTest();
785	if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):
786	uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput;
787	uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);
788	self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15,
789	uInput, uResult);
790	else:
791	self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput);
792
793	# Memory test.
794	if True:
795	for cAddrBits in oGen.oTarget.getAddrModes():
796	for cbEffOp in self.acbOpVars:
797	if cbEffOp > cbMaxOp:
798	continue;
799
800	oOp1MemRange = range(oGen.oTarget.getGRegCount());
801	oOp2MemRange = range(oGen.oTarget.getGRegCount(cAddrBits / 8))
802	oBaseRegRange = range(oGen.oTarget.getGRegCount(cAddrBits / 8));
803	oIndexRegRange = range(oGen.oTarget.getGRegCount(cAddrBits / 8));
804	if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
805	oOp1MemRange = [iLongOp1,];
806	oOp2MemRange = [iLongOp2,];
807	oBaseRegRange = oGen.oTarget.randGRegNoSpList(2, cAddrBits / 8);
808	oIndexRegRange = oGen.oTarget.randGRegNoSpList(2, cAddrBits / 8);
809	elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
810	oOp1MemRange = oGen.oTarget.randGRegNoSpList(3 if oGen.oTarget.is64Bit() else 1, cbEffOp);
811	oOp2MemRange = oGen.oTarget.randGRegNoSpList(3 + (cAddrBits == 64) * 2, cAddrBits / 8);
812	oBaseRegRange = oGen.oTarget.randGRegNoSpList(4 + (cAddrBits == 64) * 3, cAddrBits / 8);
813	oIndexRegRange = oGen.oTarget.randGRegNoSpList(4 + (cAddrBits == 64) * 3, cAddrBits / 8);
814	if iLongOp2 not in oOp1MemRange:
815	oOp1MemRange.append(iLongOp2);
816	if cAddrBits != 16 and 4 not in oOp2MemRange:
817	oOp2MemRange.append(4)
818
819	for iOp1 in oOp1MemRange:
820	if iOp1 == X86_GREG_xSP:
821	continue; # Cannot test xSP atm.
822	if iOp1 > 15:
823	continue; ## TODO AH,CH,DH,BH
824	auInputs = auLongInputs if iOp1 == iLongOp1 and False else auShortInputs;
825
826	for iOp2 in oOp2MemRange:
827	if iOp2 != 4 or cAddrBits == 16:
828	for uInput in auInputs:
829	oGen.newSubTest();
830	if iOp1 == iOp2 and iOp2 != 5 and iOp2 != 13 and cbEffOp != cbMaxOp:
831	continue; # Don't know the high bit of the address ending up the result - skip it for now.
832	uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1 & 15], oGen);
833	self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,
834	iOp1, iOp2, uInput, uResult);
835	else:
836	# SIB.
837	self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs,
838	oBaseRegRange, oIndexRegRange);
839	break;
840	break;
841
842
843	return True;
844
845	def generateTest(self, oGen, sTestFnName):
846	oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));
847	#oGen.write(' int3\n');
848
849	self.generateStandardTests(oGen);
850
851	#oGen.write(' int3\n');
852	oGen.write(' ret\n');
853	oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));
854	return True;
855
856
857
858	class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
859	"""
860	Tests MOV Gv,Ev.
861	"""
862	def __init__(self):
863	InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);
864
865	@staticmethod
866	def calc_mov(cbEffOp, uInput, uCur, oGen):
867	""" Calculates the result of a mov instruction."""
868	if cbEffOp == 8:
869	return uInput & UINT64_MAX;
870	if cbEffOp == 4:
871	return uInput & UINT32_MAX;
872	if cbEffOp == 2:
873	return (uCur & 0xffffffffffff0000) \| (uInput & UINT16_MAX);
874	assert cbEffOp == 1; _ = oGen;
875	return (uCur & 0xffffffffffffff00) \| (uInput & UINT8_MAX);
876
877
878	class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
879	"""
880	Tests MOVSXD Gv,Ev.
881	"""
882	def __init__(self):
883	InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);
884
885	def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
886	if cbEffOp == 8:
887	oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));
888	elif cbEffOp == 4 or cbEffOp == 2:
889	abInstr = [];
890	if cbEffOp != oGen.oTarget.getDefOpBytes():
891	abInstr.append(X86_OP_PRF_SIZE_OP);
892	abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);
893	abInstr.append(0x63);
894	abInstr += calcModRmForTwoRegs(iOp1, iOp2);
895	oGen.writeInstrBytes(abInstr);
896	else:
897	assert False;
898	assert False;
899	return True;
900
901	def isApplicable(self, oGen):
902	return oGen.oTarget.is64Bit();
903
904	@staticmethod
905	def calc_movsxd(cbEffOp, uInput, uCur, oGen):
906	"""
907	Calculates the result of a movxsd instruction.
908	Returns the result value (cbMaxOp sized).
909	"""
910	_ = oGen;
911	if cbEffOp == 8 and (uInput & RT_BIT_32(31)):
912	return (UINT32_MAX << 32) \| (uInput & UINT32_MAX);
913	if cbEffOp == 2:
914	return (uCur & 0xffffffffffff0000) \| (uInput & 0xffff);
915	return uInput & UINT32_MAX;
916
917
918	## Instruction Tests.
919	g_aoInstructionTests = [
920	InstrTest_Mov_Gv_Ev(),
921	#InstrTest_MovSxD_Gv_Ev(),
922	];
923
924
925	class InstructionTestGen(object):
926	"""
927	Instruction Test Generator.
928	"""
929
930	## @name Test size
931	## @{
932	ksTestSize_Large = 'large';
933	ksTestSize_Medium = 'medium';
934	ksTestSize_Tiny = 'tiny';
935	## @}
936	kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny );
937
938
939
940	def __init__(self, oOptions):
941	self.oOptions = oOptions;
942	self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv];
943
944	# Calculate the number of output files.
945	self.cFiles = 1;
946	if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile:
947	self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile;
948	if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests):
949	self.cFiles += 1;
950
951	# Fix the known register values.
952	self.au64Regs = randUxxList(64, 16);
953	self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)];
954	self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)];
955	self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs;
956
957	# Declare state variables used while generating.
958	self.oFile = sys.stderr;
959	self.iFile = -1;
960	self.sFile = '';
961	self.dCheckFns = dict();
962	self.dMemSetupFns = dict();
963	self.d64BitConsts = dict();
964
965
966	#
967	# Methods used by instruction tests.
968	#
969
970	def write(self, sText):
971	""" Writes to the current output file. """
972	return self.oFile.write(unicode(sText));
973
974	def writeln(self, sText):
975	""" Writes a line to the current output file. """
976	self.write(sText);
977	return self.write('\n');
978
979	def writeInstrBytes(self, abInstr):
980	"""
981	Emits an instruction given as a sequence of bytes values.
982	"""
983	self.write(' db %#04x' % (abInstr[0],));
984	for i in range(1, len(abInstr)):
985	self.write(', %#04x' % (abInstr[i],));
986	return self.write('\n');
987
988	def newSubTest(self):
989	"""
990	Indicates that a new subtest has started.
991	"""
992	self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n');
993	return True;
994
995	def needGRegChecker(self, iReg1, iReg2 = None, iReg3 = None):
996	"""
997	Records the need for a given register checker function, returning its label.
998	"""
999	if iReg2 is not None:
1000	if iReg3 is not None:
1001	sName = '%s_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2], self.oTarget.asGRegs[iReg3],);
1002	else:
1003	sName = '%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2],);
1004	else:
1005	sName = '%s' % (self.oTarget.asGRegs[iReg1],);
1006	assert iReg3 is None;
1007
1008	if sName in self.dCheckFns:
1009	self.dCheckFns[sName] += 1;
1010	else:
1011	self.dCheckFns[sName] = 1;
1012
1013	return 'Common_Check_' + sName;
1014
1015	def needGRegMemSetup(self, cAddrBits, cbEffOp, iBaseReg = None, offDisp = None, iIndexReg = None, iScale = 1):
1016	"""
1017	Records the need for a given register checker function, returning its label.
1018	"""
1019	sName = '%ubit_U%u' % (cAddrBits, cbEffOp * 8,);
1020	if iBaseReg is not None:
1021	sName += '_%s' % (gregName(iBaseReg, cAddrBits),);
1022	sName += '_x%u' % (iScale,);
1023	if iIndexReg is not None:
1024	sName += '_%s' % (gregName(iIndexReg, cAddrBits),);
1025	if offDisp is not None:
1026	sName += '_%#010x' % (offDisp & UINT32_MAX, );
1027	if sName in self.dMemSetupFns:
1028	self.dMemSetupFns[sName] += 1;
1029	else:
1030	self.dMemSetupFns[sName] = 1;
1031	return 'Common_MemSetup_' + sName;
1032
1033	def need64BitConstant(self, uVal):
1034	"""
1035	Records the need for a 64-bit constant, returning its label.
1036	These constants are pooled to attempt reduce the size of the whole thing.
1037	"""
1038	assert uVal >= 0 and uVal <= UINT64_MAX;
1039	if uVal in self.d64BitConsts:
1040	self.d64BitConsts[uVal] += 1;
1041	else:
1042	self.d64BitConsts[uVal] = 1;
1043	return 'g_u64Const_0x%016x' % (uVal, );
1044
1045	def pushConst(self, uResult):
1046	"""
1047	Emits a push constant value, taking care of high values on 64-bit hosts.
1048	"""
1049	if self.oTarget.is64Bit() and uResult >= 0x80000000:
1050	self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),));
1051	else:
1052	self.write(' push dword 0x%x\n' % (uResult,));
1053	return True;
1054
1055	def getDispForMod(self, iMod, cbAlignment = 1):
1056	"""
1057	Get a set of address dispositions for a given addressing mode.
1058	The alignment restriction is for SIB scaling.
1059	"""
1060	assert cbAlignment in [1, 2, 4, 8];
1061	if iMod == 0:
1062	aoffDisp = [ None, ];
1063	elif iMod == 1:
1064	aoffDisp = [ 127 & ~(cbAlignment - 1), -128 ];
1065	elif iMod == 2:
1066	aoffDisp = [ 2147483647 & ~(cbAlignment - 1), -2147483648 ];
1067	else: assert False;
1068	return aoffDisp;
1069
1070
1071	#
1072	# Internal machinery.
1073	#
1074
1075	def _calcTestFunctionName(self, oInstrTest, iInstrTest):
1076	"""
1077	Calc a test function name for the given instruction test.
1078	"""
1079	sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName);
1080	return sName.replace(',', '_').replace(' ', '_').replace('%', '_');
1081
1082	def _generateFileHeader(self, ):
1083	"""
1084	Writes the file header.
1085	Raises exception on trouble.
1086	"""
1087	self.write('; $Id: InstructionTestGen.py 46893 2013-07-01 20:38:16Z vboxsync $\n'
1088	';; @file %s\n'
1089	'; Autogenerate by %s %s. DO NOT EDIT\n'
1090	';\n'
1091	'\n'
1092	';\n'
1093	'; Headers\n'
1094	';\n'
1095	'%%include "env-%s.mac"\n'
1096	% ( os.path.basename(self.sFile),
1097	os.path.basename(__file__), __version__[11:-1],
1098	self.oTarget.sName,
1099	) );
1100	# Target environment specific init stuff.
1101
1102	#
1103	# Global variables.
1104	#
1105	self.write('\n\n'
1106	';\n'
1107	'; Globals\n'
1108	';\n');
1109	self.write('VBINSTST_BEGINDATA\n'
1110	'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n'
1111	' dq 0\n'
1112	'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n'
1113	' dq 0\n'
1114	'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n'
1115	' dq 0\n'
1116	'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n'
1117	' dd 0\n'
1118	'VBINSTST_BEGINCODE\n'
1119	);
1120	self.write('%ifdef RT_ARCH_AMD64\n');
1121	for i in range(len(g_asGRegs64)):
1122	self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i]));
1123	self.write('%endif\n\n')
1124
1125	#
1126	# Common functions.
1127	#
1128
1129	# Loading common values.
1130	self.write('\n\n'
1131	'VBINSTST_BEGINPROC Common_LoadKnownValues\n'
1132	'%ifdef RT_ARCH_AMD64\n');
1133	for i in range(len(g_asGRegs64NoSp)):
1134	if g_asGRegs64NoSp[i]:
1135	self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],));
1136	self.write('%else\n');
1137	for i in range(8):
1138	if g_asGRegs32NoSp[i]:
1139	self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],));
1140	self.write('%endif\n'
1141	' ret\n'
1142	'VBINSTST_ENDPROC Common_LoadKnownValues\n'
1143	'\n');
1144
1145	self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n'
1146	'%ifdef RT_ARCH_AMD64\n');
1147	for i in range(len(g_asGRegs64NoSp)):
1148	if g_asGRegs64NoSp[i]:
1149	self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n'
1150	' je .ok_%u\n'
1151	' push %u ; register number\n'
1152	' push %s ; actual\n'
1153	' push qword [g_u64KnownValue_%s wrt rip] ; expected\n'
1154	' call VBINSTST_NAME(Common_BadValue)\n'
1155	'.ok_%u:\n'
1156	% ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,));
1157	self.write('%else\n');
1158	for i in range(8):
1159	if g_asGRegs32NoSp[i]:
1160	self.write(' cmp %s, 0x%x\n'
1161	' je .ok_%u\n'
1162	' push %u ; register number\n'
1163	' push %s ; actual\n'
1164	' push dword 0x%x ; expected\n'
1165	' call VBINSTST_NAME(Common_BadValue)\n'
1166	'.ok_%u:\n'
1167	% ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,));
1168	self.write('%endif\n'
1169	' ret\n'
1170	'VBINSTST_ENDPROC Common_CheckKnownValues\n'
1171	'\n');
1172
1173	return True;
1174
1175	def _generateMemSetupFunctions(self):
1176	"""
1177	Generates the memory setup functions.
1178	"""
1179	cDefAddrBits = self.oTarget.getDefAddrBits();
1180	for sName in self.dMemSetupFns:
1181	# Unpack it.
1182	asParams = sName.split('_');
1183	cAddrBits = int(asParams[0][:-3]); assert asParams[0][-3:] == 'bit';
1184	cEffOpBits = int(asParams[1][1:]); assert asParams[1][0] == 'U';
1185	if cAddrBits == 64: asAddrGRegs = g_asGRegs64;
1186	elif cAddrBits == 32: asAddrGRegs = g_asGRegs32;
1187	else: asAddrGRegs = g_asGRegs16;
1188
1189	i = 2;
1190	iBaseReg = None;
1191	sBaseReg = None;
1192	if i < len(asParams) and asParams[i] in asAddrGRegs:
1193	sBaseReg = asParams[i];
1194	iBaseReg = asAddrGRegs.index(sBaseReg);
1195	i += 1
1196
1197	assert i < len(asParams); assert asParams[i][0] == 'x';
1198	iScale = iScale = int(asParams[i][1:]); assert iScale in [1, 2, 4, 8];
1199	i += 1;
1200
1201	sIndexReg = None;
1202	iIndexReg = None;
1203	if i < len(asParams) and asParams[i] in asAddrGRegs:
1204	sIndexReg = asParams[i];
1205	iIndexReg = asAddrGRegs.index(sIndexReg);
1206	i += 1;
1207
1208	u32Disp = None;
1209	if i < len(asParams) and len(asParams[i]) == 10:
1210	u32Disp = long(asParams[i], 16);
1211	i += 1;
1212
1213	assert i == len(asParams), 'i=%d len=%d len[i]=%d (%s)' % (i, len(asParams), len(asParams[i]), asParams[i],);
1214	assert iScale == 1 or iIndexReg is not None;
1215
1216	# Find a temporary register.
1217	iTmpReg1 = X86_GREG_xCX;
1218	while iTmpReg1 in [iBaseReg, iIndexReg]:
1219	iTmpReg1 += 1;
1220
1221	# Prologue.
1222	self.write('\n\n'
1223	'; cAddrBits=%s cEffOpBits=%s iBaseReg=%s u32Disp=%s iIndexReg=%s iScale=%s\n'
1224	'VBINSTST_BEGINPROC Common_MemSetup_%s\n'
1225	' MY_PUSH_FLAGS\n'
1226	' push %s\n'
1227	% ( cAddrBits, cEffOpBits, iBaseReg, u32Disp, iIndexReg, iScale,
1228	sName, self.oTarget.asGRegs[iTmpReg1], ));
1229
1230	# Figure out what to use.
1231	if cEffOpBits == 64:
1232	sTmpReg1 = g_asGRegs64[iTmpReg1];
1233	sDataVar = 'VBINSTST_NAME(g_u64Data)';
1234	elif cEffOpBits == 32:
1235	sTmpReg1 = g_asGRegs32[iTmpReg1];
1236	sDataVar = 'VBINSTST_NAME(g_u32Data)';
1237	elif cEffOpBits == 16:
1238	sTmpReg1 = g_asGRegs16[iTmpReg1];
1239	sDataVar = 'VBINSTST_NAME(g_u16Data)';
1240	else:
1241	assert cEffOpBits == 8; assert iTmpReg1 < 4;
1242	sTmpReg1 = g_asGRegs8Rex[iTmpReg1];
1243	sDataVar = 'VBINSTST_NAME(g_u8Data)';
1244
1245	# Special case: reg + reg * [2,4,8]
1246	if iBaseReg == iIndexReg and iBaseReg is not None and iScale != 1:
1247	iTmpReg2 = X86_GREG_xBP;
1248	while iTmpReg2 in [iBaseReg, iIndexReg, iTmpReg1]:
1249	iTmpReg2 += 1;
1250	sTmpReg2 = gregName(iTmpReg2, cAddrBits);
1251	self.write(' push sAX\n'
1252	' push %s\n'
1253	' push sDX\n'
1254	% (self.oTarget.asGRegs[iTmpReg2],));
1255	if cAddrBits == 16:
1256	self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sTmpReg2,));
1257	else:
1258	self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sTmpReg2,));
1259	self.write(' add %s, 0x200\n' % (sTmpReg2,));
1260	self.write(' mov %s, %s\n' % (gregName(X86_GREG_xAX, cAddrBits), sTmpReg2,));
1261	if u32Disp is not None:
1262	self.write(' sub %s, %d\n' % ( gregName(X86_GREG_xAX, cAddrBits), convU32ToSigned(u32Disp), ));
1263	self.write(' xor edx, edx\n'
1264	'%if xCB == 2\n'
1265	' push 0\n'
1266	'%endif\n');
1267	self.write(' push %u\n' % (iScale + 1,));
1268	self.write(' div %s [xSP]\n' % ('qword' if cAddrBits == 64 else 'dword',));
1269	self.write(' sub %s, %s\n' % (sTmpReg2, gregName(X86_GREG_xDX, cAddrBits),));
1270	self.write(' pop sDX\n'
1271	' pop sDX\n'); # sTmpReg2 is eff address; sAX is sIndexReg value.
1272	# Note! sTmpReg1 can be xDX and that's no problem now.
1273	self.write(' mov %s, [xSP + sCB*3 + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,));
1274	self.write(' mov [%s], %s\n' % (sTmpReg2, sTmpReg1,)); # Value in place.
1275	self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg2],));
1276	if iBaseReg == X86_GREG_xAX:
1277	self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg1],));
1278	else:
1279	self.write(' mov %s, %s\n' % (sBaseReg, gregName(X86_GREG_xAX, cAddrBits),));
1280	self.write(' pop sAX\n');
1281
1282	else:
1283	# Load the value and mem address, storing the value there.
1284	# Note! ASSUMES that the scale and disposition works fine together.
1285	sAddrReg = sBaseReg if sBaseReg is not None else sIndexReg;
1286	self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,));
1287	if cAddrBits >= cDefAddrBits:
1288	self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,));
1289	self.write(' lea %s, [%s xWrtRIP]\n' % (sAddrReg, sDataVar,));
1290	else:
1291	if cAddrBits == 16:
1292	self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sAddrReg,));
1293	else:
1294	self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sAddrReg,));
1295	self.write(' add %s, %s\n' % (sAddrReg, (randU16() << cEffOpBits) & 0xfff, ));
1296	self.write(' mov [%s], %s\n' % (sAddrReg, sTmpReg1, ));
1297
1298	# Adjust for disposition and scaling.
1299	if u32Disp is not None:
1300	self.write(' sub %s, %d\n' % ( sAddrReg, convU32ToSigned(u32Disp), ));
1301	if iIndexReg is not None:
1302	if iBaseReg == iIndexReg:
1303	assert iScale == 1;
1304	assert u32Disp is None or (u32Disp & 1) == 0;
1305	self.write(' shr %s, 1\n' % (sIndexReg,));
1306	elif sBaseReg is not None:
1307	uIdxRegVal = randUxx(cAddrBits);
1308	if cAddrBits == 64:
1309	self.write(' mov %s, %u\n'
1310	' sub %s, %s\n'
1311	' mov %s, %u\n'
1312	% ( sIndexReg, (uIdxRegVal * iScale) & UINT64_MAX,
1313	sBaseReg, sIndexReg,
1314	sIndexReg, uIdxRegVal, ));
1315	else:
1316	assert cAddrBits == 32;
1317	self.write(' mov %s, %u\n'
1318	' sub %s, %#06x\n'
1319	% ( sIndexReg, uIdxRegVal, sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, ));
1320	elif iScale == 2:
1321	assert u32Disp is None or (u32Disp & 1) == 0;
1322	self.write(' shr %s, 1\n' % (sIndexReg,));
1323	elif iScale == 4:
1324	assert u32Disp is None or (u32Disp & 3) == 0;
1325	self.write(' shr %s, 2\n' % (sIndexReg,));
1326	elif iScale == 8:
1327	assert u32Disp is None or (u32Disp & 7) == 0;
1328	self.write(' shr %s, 3\n' % (sIndexReg,));
1329	else:
1330	assert iScale == 1;
1331
1332	# Set upper bits that's supposed to be unused.
1333	if cDefAddrBits > cAddrBits or cAddrBits == 16:
1334	if cDefAddrBits == 64:
1335	assert cAddrBits == 32;
1336	if iBaseReg is not None:
1337	self.write(' mov %s, %#018x\n'
1338	' or %s, %s\n'
1339	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
1340	g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],));
1341	if iIndexReg is not None and iIndexReg != iBaseReg:
1342	self.write(' mov %s, %#018x\n'
1343	' or %s, %s\n'
1344	% ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
1345	g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],));
1346	else:
1347	assert cDefAddrBits == 32; assert cAddrBits == 16; assert iIndexReg is None;
1348	if iBaseReg is not None:
1349	self.write(' or %s, %#010x\n'
1350	% ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, ));
1351
1352	# Epilogue.
1353	self.write(' pop %s\n'
1354	' MY_POP_FLAGS\n'
1355	' ret sCB\n'
1356	'VBINSTST_ENDPROC Common_MemSetup_%s\n'
1357	% ( self.oTarget.asGRegs[iTmpReg1], sName,));
1358
1359
1360	def _generateFileFooter(self):
1361	"""
1362	Generates file footer.
1363	"""
1364
1365	# Register checking functions.
1366	for sName in self.dCheckFns:
1367	asRegs = sName.split('_');
1368	sPushSize = 'dword';
1369
1370	# Prologue
1371	self.write('\n\n'
1372	'; Checks 1 or more register values, expected values pushed on the stack.\n'
1373	'; To save space, the callee cleans up the stack.'
1374	'; Ref count: %u\n'
1375	'VBINSTST_BEGINPROC Common_Check_%s\n'
1376	' MY_PUSH_FLAGS\n'
1377	% ( self.dCheckFns[sName], sName, ) );
1378
1379	# Register checks.
1380	for i in range(len(asRegs)):
1381	sReg = asRegs[i];
1382	iReg = self.oTarget.asGRegs.index(sReg);
1383	if i == asRegs.index(sReg): # Only check once, i.e. input = output reg.
1384	self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n'
1385	' je .equal%u\n'
1386	' push %s %u ; register number\n'
1387	' push %s ; actual\n'
1388	' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB]\n'
1389	' push %s ; expected\n'
1390	' call VBINSTST_NAME(Common_BadValue)\n'
1391	'.equal%u:\n'
1392	% ( sReg, i, i, sPushSize, iReg, sReg, sReg, sReg, i, ) );
1393
1394
1395	# Restore known register values and check the other registers.
1396	for sReg in asRegs:
1397	if self.oTarget.is64Bit():
1398	self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg, sReg,));
1399	else:
1400	iReg = self.oTarget.asGRegs.index(sReg)
1401	self.write(' mov %s, 0x%x\n' % (sReg, self.au32Regs[iReg],));
1402	self.write(' MY_POP_FLAGS\n'
1403	' call VBINSTST_NAME(Common_CheckKnownValues)\n'
1404	' ret sCB*%u\n'
1405	'VBINSTST_ENDPROC Common_Check_%s\n'
1406	% (len(asRegs), sName,));
1407
1408	# memory setup functions
1409	self._generateMemSetupFunctions();
1410
1411	# 64-bit constants.
1412	if len(self.d64BitConsts) > 0:
1413	self.write('\n\n'
1414	';\n'
1415	'; 64-bit constants\n'
1416	';\n');
1417	for uVal in self.d64BitConsts:
1418	self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self.d64BitConsts[uVal], ) );
1419
1420	return True;
1421
1422	def _generateTests(self):
1423	"""
1424	Generate the test cases.
1425	"""
1426	for self.iFile in range(self.cFiles):
1427	if self.cFiles == 1:
1428	self.sFile = '%s.asm' % (self.oOptions.sOutputBase,)
1429	else:
1430	self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile)
1431	self.oFile = sys.stdout;
1432	if self.oOptions.sOutputBase != '-':
1433	self.oFile = io.open(self.sFile, 'w', buffering = 65536, encoding = 'utf-8');
1434
1435	self._generateFileHeader();
1436
1437	# Calc the range.
1438	iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile;
1439	iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile;
1440	if iInstrTestEnd > len(g_aoInstructionTests):
1441	iInstrTestEnd = len(g_aoInstructionTests);
1442
1443	# Generate the instruction tests.
1444	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1445	oInstrTest = g_aoInstructionTests[iInstrTest];
1446	self.write('\n'
1447	'\n'
1448	';\n'
1449	'; %s\n'
1450	';\n'
1451	% (oInstrTest.sName,));
1452	oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest));
1453
1454	# Generate the main function.
1455	self.write('\n\n'
1456	'VBINSTST_BEGINPROC TestInstrMain\n'
1457	' MY_PUSH_ALL\n'
1458	' sub xSP, 40h\n'
1459	'\n');
1460
1461	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1462	oInstrTest = g_aoInstructionTests[iInstrTest];
1463	if oInstrTest.isApplicable(self):
1464	self.write('%%ifdef ASM_CALL64_GCC\n'
1465	' lea rdi, [.szInstr%03u wrt rip]\n'
1466	'%%elifdef ASM_CALL64_MSC\n'
1467	' lea rcx, [.szInstr%03u wrt rip]\n'
1468	'%%else\n'
1469	' mov xAX, .szInstr%03u\n'
1470	' mov [xSP], xAX\n'
1471	'%%endif\n'
1472	' VBINSTST_CALL_FN_SUB_TEST\n'
1473	' call VBINSTST_NAME(%s)\n'
1474	% ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest)));
1475
1476	self.write('\n'
1477	' add xSP, 40h\n'
1478	' MY_POP_ALL\n'
1479	' ret\n\n');
1480	for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1481	self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,));
1482	self.write('VBINSTST_ENDPROC TestInstrMain\n\n');
1483
1484	self._generateFileFooter();
1485	if self.oOptions.sOutputBase != '-':
1486	self.oFile.close();
1487	self.oFile = None;
1488	self.sFile = '';
1489
1490	return RTEXITCODE_SUCCESS;
1491
1492	def _runMakefileMode(self):
1493	"""
1494	Generate a list of output files on standard output.
1495	"""
1496	if self.cFiles == 1:
1497	print('%s.asm' % (self.oOptions.sOutputBase,));
1498	else:
1499	print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles)));
1500	return RTEXITCODE_SUCCESS;
1501
1502	def run(self):
1503	"""
1504	Generates the tests or whatever is required.
1505	"""
1506	if self.oOptions.fMakefileMode:
1507	return self._runMakefileMode();
1508	return self._generateTests();
1509
1510	@staticmethod
1511	def main():
1512	"""
1513	Main function a la C/C++. Returns exit code.
1514	"""
1515
1516	#
1517	# Parse the command line.
1518	#
1519	oParser = OptionParser(version = __version__[11:-1].strip());
1520	oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False,
1521	help = 'Special mode for use to output a list of output files for the benefit of '
1522	'the make program (kmk).');
1523	oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '<instr-per-file>', type = 'int', default = 9999999,
1524	help = 'Number of instruction to test per output file.');
1525	oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '<file>', default = None,
1526	help = 'The output file base name, no suffix please. Required.');
1527	oParser.add_option('--target', dest = 'sTargetEnv', metavar = '<target>',
1528	default = 'iprt-r3-32',
1529	choices = g_dTargetEnvs.keys(),
1530	help = 'The target environment. Choices: %s'
1531	% (', '.join(sorted(g_dTargetEnvs.keys())),));
1532	oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium,
1533	choices = InstructionTestGen.kasTestSizes,
1534	help = 'Selects the test size.');
1535
1536	(oOptions, asArgs) = oParser.parse_args();
1537	if len(asArgs) > 0:
1538	oParser.print_help();
1539	return RTEXITCODE_SYNTAX
1540	if oOptions.sOutputBase is None:
1541	print('syntax error: Missing required option --output-base.', file = sys.stderr);
1542	return RTEXITCODE_SYNTAX
1543
1544	#
1545	# Instantiate the program class and run it.
1546	#
1547	oProgram = InstructionTestGen(oOptions);
1548	return oProgram.run();
1549
1550
1551	if __name__ == '__main__':
1552	sys.exit(InstructionTestGen.main());
1553

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source: vbox/trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py@ 46893

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