tstIEMAImpl.cpp@ 96922

Last change on this file since 96922 was 96922, checked in by vboxsync, 2 years ago
VMM/testcase/tstIEMAImpl: Implement basic cvtpi2ps/cvtpi2pd testcases, bugref:9898
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1	/* $Id: tstIEMAImpl.cpp 96922 2022-09-28 19:23:12Z vboxsync $ */
2	/** @file
3	* IEM Assembly Instruction Helper Testcase.
4	*/
5
6	/*
7	* Copyright (C) 2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include "../include/IEMInternal.h"
33
34	#include <iprt/errcore.h>
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/ctype.h>
38	#include <iprt/getopt.h>
39	#include <iprt/initterm.h>
40	#include <iprt/message.h>
41	#include <iprt/mp.h>
42	#include <iprt/rand.h>
43	#include <iprt/stream.h>
44	#include <iprt/string.h>
45	#include <iprt/test.h>
46
47	#include "tstIEMAImpl.h"
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	#define ENTRY(a_Name) ENTRY_EX(a_Name, 0)
54	#define ENTRY_EX(a_Name, a_uExtra) \
55	{ RT_XSTR(a_Name), iemAImpl_ ## a_Name, NULL, \
56	g_aTests_ ## a_Name, &g_cTests_ ## a_Name, \
57	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_NATIVE /* means same for all here */ }
58
59	#define ENTRY_BIN(a_Name) ENTRY_EX_BIN(a_Name, 0)
60	#define ENTRY_EX_BIN(a_Name, a_uExtra) \
61	{ RT_XSTR(a_Name), iemAImpl_ ## a_Name, NULL, \
62	g_aTests_ ## a_Name, &g_cbTests_ ## a_Name, \
63	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_NATIVE /* means same for all here */ }
64
65	#define ENTRY_BIN_AVX(a_Name) ENTRY_BIN_AVX_EX(a_Name, 0)
66	#ifndef IEM_WITHOUT_ASSEMBLY
67	# define ENTRY_BIN_AVX_EX(a_Name, a_uExtra) \
68	{ RT_XSTR(a_Name), iemAImpl_ ## a_Name, NULL, \
69	g_aTests_ ## a_Name, &g_cbTests_ ## a_Name, \
70	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_NATIVE /* means same for all here */ }
71	#else
72	# define ENTRY_BIN_AVX_EX(a_Name, a_uExtra) \
73	{ RT_XSTR(a_Name), iemAImpl_ ## a_Name ## _fallback, NULL, \
74	g_aTests_ ## a_Name, &g_cbTests_ ## a_Name, \
75	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_NATIVE /* means same for all here */ }
76	#endif
77
78
79	#define ENTRY_INTEL(a_Name, a_fEflUndef) ENTRY_INTEL_EX(a_Name, a_fEflUndef, 0)
80	#define ENTRY_INTEL_EX(a_Name, a_fEflUndef, a_uExtra) \
81	{ RT_XSTR(a_Name) "_intel", iemAImpl_ ## a_Name ## _intel, iemAImpl_ ## a_Name, \
82	g_aTests_ ## a_Name ## _intel, &g_cTests_ ## a_Name ## _intel, \
83	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_INTEL }
84
85	#define ENTRY_AMD(a_Name, a_fEflUndef) ENTRY_AMD_EX(a_Name, a_fEflUndef, 0)
86	#define ENTRY_AMD_EX(a_Name, a_fEflUndef, a_uExtra) \
87	{ RT_XSTR(a_Name) "_amd", iemAImpl_ ## a_Name ## _amd, iemAImpl_ ## a_Name, \
88	g_aTests_ ## a_Name ## _amd, &g_cTests_ ## a_Name ## _amd, \
89	a_uExtra, IEMTARGETCPU_EFL_BEHAVIOR_AMD }
90
91	#define TYPEDEF_SUBTEST_TYPE(a_TypeName, a_TestType, a_FunctionPtrType) \
92	typedef struct a_TypeName \
93	{ \
94	const char *pszName; \
95	a_FunctionPtrType pfn; \
96	a_FunctionPtrType pfnNative; \
97	a_TestType const *paTests; \
98	uint32_t const *pcTests; \
99	uint32_t uExtra; \
100	uint8_t idxCpuEflFlavour; \
101	} a_TypeName
102
103	#define COUNT_VARIATIONS(a_SubTest) \
104	(1 + ((a_SubTest).idxCpuEflFlavour == g_idxCpuEflFlavour && (a_SubTest).pfnNative) )
105
106
107	/*********************************************************************************************************************************
108	* Global Variables *
109	*********************************************************************************************************************************/
110	static RTTEST g_hTest;
111	static uint8_t g_idxCpuEflFlavour = IEMTARGETCPU_EFL_BEHAVIOR_INTEL;
112	#ifdef TSTIEMAIMPL_WITH_GENERATOR
113	static uint32_t g_cZeroDstTests = 2;
114	static uint32_t g_cZeroSrcTests = 4;
115	#endif
116	static uint8_t g_pu8, g_pu8Two;
117	static uint16_t g_pu16, g_pu16Two;
118	static uint32_t g_pu32, g_pu32Two, *g_pfEfl;
119	static uint64_t g_pu64, g_pu64Two;
120	static RTUINT128U g_pu128, g_pu128Two;
121
122	static char g_aszBuf[32][256];
123	static unsigned g_idxBuf = 0;
124
125	static uint32_t g_cIncludeTestPatterns;
126	static uint32_t g_cExcludeTestPatterns;
127	static const char *g_apszIncludeTestPatterns[64];
128	static const char *g_apszExcludeTestPatterns[64];
129
130	static unsigned g_cVerbosity = 0;
131
132
133	/*********************************************************************************************************************************
134	* Internal Functions *
135	*********************************************************************************************************************************/
136	static const char *FormatR80(PCRTFLOAT80U pr80);
137	static const char *FormatR64(PCRTFLOAT64U pr64);
138	static const char *FormatR32(PCRTFLOAT32U pr32);
139
140
141	/*
142	* Random helpers.
143	*/
144
145	static uint32_t RandEFlags(void)
146	{
147	uint32_t fEfl = RTRandU32();
148	return (fEfl & X86_EFL_LIVE_MASK) \| X86_EFL_RA1_MASK;
149	}
150
151	#ifdef TSTIEMAIMPL_WITH_GENERATOR
152
153	static uint8_t RandU8(void)
154	{
155	return RTRandU32Ex(0, 0xff);
156	}
157
158
159	static uint16_t RandU16(void)
160	{
161	return RTRandU32Ex(0, 0xffff);
162	}
163
164
165	static uint32_t RandU32(void)
166	{
167	return RTRandU32();
168	}
169
170	#endif
171
172	static uint64_t RandU64(void)
173	{
174	return RTRandU64();
175	}
176
177
178	static RTUINT128U RandU128(void)
179	{
180	RTUINT128U Ret;
181	Ret.s.Hi = RTRandU64();
182	Ret.s.Lo = RTRandU64();
183	return Ret;
184	}
185
186	#ifdef TSTIEMAIMPL_WITH_GENERATOR
187
188	static uint8_t RandU8Dst(uint32_t iTest)
189	{
190	if (iTest < g_cZeroDstTests)
191	return 0;
192	return RandU8();
193	}
194
195
196	static uint8_t RandU8Src(uint32_t iTest)
197	{
198	if (iTest < g_cZeroSrcTests)
199	return 0;
200	return RandU8();
201	}
202
203
204	static uint16_t RandU16Dst(uint32_t iTest)
205	{
206	if (iTest < g_cZeroDstTests)
207	return 0;
208	return RandU16();
209	}
210
211
212	static uint16_t RandU16Src(uint32_t iTest)
213	{
214	if (iTest < g_cZeroSrcTests)
215	return 0;
216	return RandU16();
217	}
218
219
220	static uint32_t RandU32Dst(uint32_t iTest)
221	{
222	if (iTest < g_cZeroDstTests)
223	return 0;
224	return RandU32();
225	}
226
227
228	static uint32_t RandU32Src(uint32_t iTest)
229	{
230	if (iTest < g_cZeroSrcTests)
231	return 0;
232	return RandU32();
233	}
234
235
236	static uint64_t RandU64Dst(uint32_t iTest)
237	{
238	if (iTest < g_cZeroDstTests)
239	return 0;
240	return RandU64();
241	}
242
243
244	static uint64_t RandU64Src(uint32_t iTest)
245	{
246	if (iTest < g_cZeroSrcTests)
247	return 0;
248	return RandU64();
249	}
250
251
252	/** 2nd operand for and FPU instruction, pairing with RandR80Src1. */
253	static int16_t RandI16Src2(uint32_t iTest)
254	{
255	if (iTest < 18 * 4)
256	switch (iTest % 4)
257	{
258	case 0: return 0;
259	case 1: return INT16_MAX;
260	case 2: return INT16_MIN;
261	case 3: break;
262	}
263	return (int16_t)RandU16();
264	}
265
266
267	/** 2nd operand for and FPU instruction, pairing with RandR80Src1. */
268	static int32_t RandI32Src2(uint32_t iTest)
269	{
270	if (iTest < 18 * 4)
271	switch (iTest % 4)
272	{
273	case 0: return 0;
274	case 1: return INT32_MAX;
275	case 2: return INT32_MIN;
276	case 3: break;
277	}
278	return (int32_t)RandU32();
279	}
280
281
282	static int64_t RandI64Src(uint32_t iTest)
283	{
284	RT_NOREF(iTest);
285	return (int64_t)RandU64();
286	}
287
288
289	static uint16_t RandFcw(void)
290	{
291	return RandU16() & ~X86_FCW_ZERO_MASK;
292	}
293
294
295	static uint16_t RandFsw(void)
296	{
297	AssertCompile((X86_FSW_C_MASK \| X86_FSW_XCPT_ES_MASK \| X86_FSW_TOP_MASK \| X86_FSW_B) == 0xffff);
298	return RandU16();
299	}
300
301
302	static uint32_t RandMxcsr(void)
303	{
304	return RandU32() & ~X86_MXCSR_ZERO_MASK;
305	}
306
307
308	static void SafeR80FractionShift(PRTFLOAT80U pr80, uint8_t cShift)
309	{
310	if (pr80->sj64.uFraction >= RT_BIT_64(cShift))
311	pr80->sj64.uFraction >>= cShift;
312	else
313	pr80->sj64.uFraction = (cShift % 19) + 1;
314	}
315
316
317
318	static RTFLOAT80U RandR80Ex(uint8_t bType, unsigned cTarget = 80, bool fIntTarget = false)
319	{
320	Assert(cTarget == (!fIntTarget ? 80U : 16U) \|\| cTarget == 64U \|\| cTarget == 32U \|\| (cTarget == 59U && fIntTarget));
321
322	RTFLOAT80U r80;
323	r80.au64[0] = RandU64();
324	r80.au16[4] = RandU16();
325
326	/*
327	* Adjust the random stuff according to bType.
328	*/
329	bType &= 0x1f;
330	if (bType == 0 \|\| bType == 1 \|\| bType == 2 \|\| bType == 3)
331	{
332	/* Zero (0), Pseudo-Infinity (1), Infinity (2), Indefinite (3). We only keep fSign here. */
333	r80.sj64.uExponent = bType == 0 ? 0 : 0x7fff;
334	r80.sj64.uFraction = bType <= 2 ? 0 : RT_BIT_64(62);
335	r80.sj64.fInteger = bType >= 2 ? 1 : 0;
336	AssertMsg(bType != 0 \|\| RTFLOAT80U_IS_ZERO(&r80), ("%s\n", FormatR80(&r80)));
337	AssertMsg(bType != 1 \|\| RTFLOAT80U_IS_PSEUDO_INF(&r80), ("%s\n", FormatR80(&r80)));
338	Assert( bType != 1 \|\| RTFLOAT80U_IS_387_INVALID(&r80));
339	AssertMsg(bType != 2 \|\| RTFLOAT80U_IS_INF(&r80), ("%s\n", FormatR80(&r80)));
340	AssertMsg(bType != 3 \|\| RTFLOAT80U_IS_INDEFINITE(&r80), ("%s\n", FormatR80(&r80)));
341	}
342	else if (bType == 4 \|\| bType == 5 \|\| bType == 6 \|\| bType == 7)
343	{
344	/* Denormals (4,5) and Pseudo denormals (6,7) */
345	if (bType & 1)
346	SafeR80FractionShift(&r80, r80.sj64.uExponent % 62);
347	else if (r80.sj64.uFraction == 0 && bType < 6)
348	r80.sj64.uFraction = RTRandU64Ex(1, RT_BIT_64(RTFLOAT80U_FRACTION_BITS) - 1);
349	r80.sj64.uExponent = 0;
350	r80.sj64.fInteger = bType >= 6;
351	AssertMsg(bType >= 6 \|\| RTFLOAT80U_IS_DENORMAL(&r80), ("%s bType=%#x\n", FormatR80(&r80), bType));
352	AssertMsg(bType < 6 \|\| RTFLOAT80U_IS_PSEUDO_DENORMAL(&r80), ("%s bType=%#x\n", FormatR80(&r80), bType));
353	}
354	else if (bType == 8 \|\| bType == 9)
355	{
356	/* Pseudo NaN. */
357	if (bType & 1)
358	SafeR80FractionShift(&r80, r80.sj64.uExponent % 62);
359	else if (r80.sj64.uFraction == 0 && !r80.sj64.fInteger)
360	r80.sj64.uFraction = RTRandU64Ex(1, RT_BIT_64(RTFLOAT80U_FRACTION_BITS) - 1);
361	r80.sj64.uExponent = 0x7fff;
362	if (r80.sj64.fInteger)
363	r80.sj64.uFraction \|= RT_BIT_64(62);
364	else
365	r80.sj64.uFraction &= ~RT_BIT_64(62);
366	r80.sj64.fInteger = 0;
367	AssertMsg(RTFLOAT80U_IS_PSEUDO_NAN(&r80), ("%s bType=%#x\n", FormatR80(&r80), bType));
368	AssertMsg(RTFLOAT80U_IS_NAN(&r80), ("%s bType=%#x\n", FormatR80(&r80), bType));
369	Assert(RTFLOAT80U_IS_387_INVALID(&r80));
370	}
371	else if (bType == 10 \|\| bType == 11 \|\| bType == 12 \|\| bType == 13)
372	{
373	/* Quiet and signalling NaNs. */
374	if (bType & 1)
375	SafeR80FractionShift(&r80, r80.sj64.uExponent % 62);
376	else if (r80.sj64.uFraction == 0)
377	r80.sj64.uFraction = RTRandU64Ex(1, RT_BIT_64(RTFLOAT80U_FRACTION_BITS) - 1);
378	r80.sj64.uExponent = 0x7fff;
379	if (bType < 12)
380	r80.sj64.uFraction \|= RT_BIT_64(62); /* quiet */
381	else
382	r80.sj64.uFraction &= ~RT_BIT_64(62); /* signaling */
383	r80.sj64.fInteger = 1;
384	AssertMsg(bType >= 12 \|\| RTFLOAT80U_IS_QUIET_NAN(&r80), ("%s\n", FormatR80(&r80)));
385	AssertMsg(bType < 12 \|\| RTFLOAT80U_IS_SIGNALLING_NAN(&r80), ("%s\n", FormatR80(&r80)));
386	AssertMsg(RTFLOAT80U_IS_SIGNALLING_NAN(&r80) \|\| RTFLOAT80U_IS_QUIET_NAN(&r80), ("%s\n", FormatR80(&r80)));
387	AssertMsg(RTFLOAT80U_IS_QUIET_OR_SIGNALLING_NAN(&r80), ("%s\n", FormatR80(&r80)));
388	AssertMsg(RTFLOAT80U_IS_NAN(&r80), ("%s\n", FormatR80(&r80)));
389	}
390	else if (bType == 14 \|\| bType == 15)
391	{
392	/* Unnormals */
393	if (bType & 1)
394	SafeR80FractionShift(&r80, RandU8() % 62);
395	r80.sj64.fInteger = 0;
396	if (r80.sj64.uExponent == RTFLOAT80U_EXP_MAX \|\| r80.sj64.uExponent == 0)
397	r80.sj64.uExponent = (uint16_t)RTRandU32Ex(1, RTFLOAT80U_EXP_MAX - 1);
398	AssertMsg(RTFLOAT80U_IS_UNNORMAL(&r80), ("%s\n", FormatR80(&r80)));
399	Assert(RTFLOAT80U_IS_387_INVALID(&r80));
400	}
401	else if (bType < 26)
402	{
403	/* Make sure we have lots of normalized values. */
404	if (!fIntTarget)
405	{
406	const unsigned uMinExp = cTarget == 64 ? RTFLOAT80U_EXP_BIAS - RTFLOAT64U_EXP_BIAS
407	: cTarget == 32 ? RTFLOAT80U_EXP_BIAS - RTFLOAT32U_EXP_BIAS : 0;
408	const unsigned uMaxExp = cTarget == 64 ? uMinExp + RTFLOAT64U_EXP_MAX
409	: cTarget == 32 ? uMinExp + RTFLOAT32U_EXP_MAX : RTFLOAT80U_EXP_MAX;
410	r80.sj64.fInteger = 1;
411	if (r80.sj64.uExponent <= uMinExp)
412	r80.sj64.uExponent = uMinExp + 1;
413	else if (r80.sj64.uExponent >= uMaxExp)
414	r80.sj64.uExponent = uMaxExp - 1;
415
416	if (bType == 16)
417	{ /* All 1s is useful to testing rounding. Also try trigger special
418	behaviour by sometimes rounding out of range, while we're at it. */
419	r80.sj64.uFraction = RT_BIT_64(63) - 1;
420	uint8_t bExp = RandU8();
421	if ((bExp & 3) == 0)
422	r80.sj64.uExponent = uMaxExp - 1;
423	else if ((bExp & 3) == 1)
424	r80.sj64.uExponent = uMinExp + 1;
425	else if ((bExp & 3) == 2)
426	r80.sj64.uExponent = uMinExp - (bExp & 15); /* (small numbers are mapped to subnormal values) */
427	}
428	}
429	else
430	{
431	/* integer target: */
432	const unsigned uMinExp = RTFLOAT80U_EXP_BIAS;
433	const unsigned uMaxExp = RTFLOAT80U_EXP_BIAS + cTarget - 2;
434	r80.sj64.fInteger = 1;
435	if (r80.sj64.uExponent < uMinExp)
436	r80.sj64.uExponent = uMinExp;
437	else if (r80.sj64.uExponent > uMaxExp)
438	r80.sj64.uExponent = uMaxExp;
439
440	if (bType == 16)
441	{ /* All 1s is useful to testing rounding. Also try trigger special
442	behaviour by sometimes rounding out of range, while we're at it. */
443	r80.sj64.uFraction = RT_BIT_64(63) - 1;
444	uint8_t bExp = RandU8();
445	if ((bExp & 3) == 0)
446	r80.sj64.uExponent = uMaxExp;
447	else if ((bExp & 3) == 1)
448	r80.sj64.uFraction &= ~(RT_BIT_64(cTarget - 1 - r80.sj64.uExponent) - 1); /* no rounding */
449	}
450	}
451
452	AssertMsg(RTFLOAT80U_IS_NORMAL(&r80), ("%s\n", FormatR80(&r80)));
453	}
454	return r80;
455	}
456
457
458	static RTFLOAT80U RandR80(unsigned cTarget = 80, bool fIntTarget = false)
459	{
460	/*
461	* Make it more likely that we get a good selection of special values.
462	*/
463	return RandR80Ex(RandU8(), cTarget, fIntTarget);
464
465	}
466
467
468	static RTFLOAT80U RandR80Src(uint32_t iTest, unsigned cTarget = 80, bool fIntTarget = false)
469	{
470	/* Make sure we cover all the basic types first before going for random selection: */
471	if (iTest <= 18)
472	return RandR80Ex(18 - iTest, cTarget, fIntTarget); /* Starting with 3 normals. */
473	return RandR80(cTarget, fIntTarget);
474	}
475
476
477	/**
478	* Helper for RandR80Src1 and RandR80Src2 that converts bType from a 0..11 range
479	* to a 0..17, covering all basic value types.
480	*/
481	static uint8_t RandR80Src12RemapType(uint8_t bType)
482	{
483	switch (bType)
484	{
485	case 0: return 18; /* normal */
486	case 1: return 16; /* normal extreme rounding */
487	case 2: return 14; /* unnormal */
488	case 3: return 12; /* Signalling NaN */
489	case 4: return 10; /* Quiet NaN */
490	case 5: return 8; /* PseudoNaN */
491	case 6: return 6; /* Pseudo Denormal */
492	case 7: return 4; /* Denormal */
493	case 8: return 3; /* Indefinite */
494	case 9: return 2; /* Infinity */
495	case 10: return 1; /* Pseudo-Infinity */
496	case 11: return 0; /* Zero */
497	default: AssertFailedReturn(18);
498	}
499	}
500
501
502	/**
503	* This works in tandem with RandR80Src2 to make sure we cover all operand
504	* type mixes first before we venture into regular random testing.
505	*
506	* There are 11 basic variations, when we leave out the five odd ones using
507	* SafeR80FractionShift. Because of the special normalized value targetting at
508	* rounding, we make it an even 12. So 144 combinations for two operands.
509	*/
510	static RTFLOAT80U RandR80Src1(uint32_t iTest, unsigned cPartnerBits = 80, bool fPartnerInt = false)
511	{
512	if (cPartnerBits == 80)
513	{
514	Assert(!fPartnerInt);
515	if (iTest < 12 * 12)
516	return RandR80Ex(RandR80Src12RemapType(iTest / 12));
517	}
518	else if ((cPartnerBits == 64 \|\| cPartnerBits == 32) && !fPartnerInt)
519	{
520	if (iTest < 12 * 10)
521	return RandR80Ex(RandR80Src12RemapType(iTest / 10));
522	}
523	else if (iTest < 18 * 4 && fPartnerInt)
524	return RandR80Ex(iTest / 4);
525	return RandR80();
526	}
527
528
529	/** Partner to RandR80Src1. */
530	static RTFLOAT80U RandR80Src2(uint32_t iTest)
531	{
532	if (iTest < 12 * 12)
533	return RandR80Ex(RandR80Src12RemapType(iTest % 12));
534	return RandR80();
535	}
536
537
538	static void SafeR64FractionShift(PRTFLOAT64U pr64, uint8_t cShift)
539	{
540	if (pr64->s64.uFraction >= RT_BIT_64(cShift))
541	pr64->s64.uFraction >>= cShift;
542	else
543	pr64->s64.uFraction = (cShift % 19) + 1;
544	}
545
546
547	static RTFLOAT64U RandR64Ex(uint8_t bType)
548	{
549	RTFLOAT64U r64;
550	r64.u = RandU64();
551
552	/*
553	* Make it more likely that we get a good selection of special values.
554	* On average 6 out of 16 calls should return a special value.
555	*/
556	bType &= 0xf;
557	if (bType == 0 \|\| bType == 1)
558	{
559	/* 0 or Infinity. We only keep fSign here. */
560	r64.s.uExponent = bType == 0 ? 0 : 0x7ff;
561	r64.s.uFractionHigh = 0;
562	r64.s.uFractionLow = 0;
563	AssertMsg(bType != 0 \|\| RTFLOAT64U_IS_ZERO(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
564	AssertMsg(bType != 1 \|\| RTFLOAT64U_IS_INF(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
565	}
566	else if (bType == 2 \|\| bType == 3)
567	{
568	/* Subnormals */
569	if (bType == 3)
570	SafeR64FractionShift(&r64, r64.s64.uExponent % 51);
571	else if (r64.s64.uFraction == 0)
572	r64.s64.uFraction = RTRandU64Ex(1, RT_BIT_64(RTFLOAT64U_FRACTION_BITS) - 1);
573	r64.s64.uExponent = 0;
574	AssertMsg(RTFLOAT64U_IS_SUBNORMAL(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
575	}
576	else if (bType == 4 \|\| bType == 5 \|\| bType == 6 \|\| bType == 7)
577	{
578	/* NaNs */
579	if (bType & 1)
580	SafeR64FractionShift(&r64, r64.s64.uExponent % 51);
581	else if (r64.s64.uFraction == 0)
582	r64.s64.uFraction = RTRandU64Ex(1, RT_BIT_64(RTFLOAT64U_FRACTION_BITS) - 1);
583	r64.s64.uExponent = 0x7ff;
584	if (bType < 6)
585	r64.s64.uFraction \|= RT_BIT_64(RTFLOAT64U_FRACTION_BITS - 1); /* quiet */
586	else
587	r64.s64.uFraction &= ~RT_BIT_64(RTFLOAT64U_FRACTION_BITS - 1); /* signalling */
588	AssertMsg(bType >= 6 \|\| RTFLOAT64U_IS_QUIET_NAN(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
589	AssertMsg(bType < 6 \|\| RTFLOAT64U_IS_SIGNALLING_NAN(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
590	AssertMsg(RTFLOAT64U_IS_NAN(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
591	}
592	else if (bType < 12)
593	{
594	/* Make sure we have lots of normalized values. */
595	if (r64.s.uExponent == 0)
596	r64.s.uExponent = 1;
597	else if (r64.s.uExponent == 0x7ff)
598	r64.s.uExponent = 0x7fe;
599	AssertMsg(RTFLOAT64U_IS_NORMAL(&r64), ("%s bType=%#x\n", FormatR64(&r64), bType));
600	}
601	return r64;
602	}
603
604
605	static RTFLOAT64U RandR64Src(uint32_t iTest)
606	{
607	if (iTest < 16)
608	return RandR64Ex(iTest);
609	return RandR64Ex(RandU8());
610	}
611
612
613	/** Pairing with a 80-bit floating point arg. */
614	static RTFLOAT64U RandR64Src2(uint32_t iTest)
615	{
616	if (iTest < 12 * 10)
617	return RandR64Ex(9 - iTest % 10); /* start with normal values */
618	return RandR64Ex(RandU8());
619	}
620
621
622	static void SafeR32FractionShift(PRTFLOAT32U pr32, uint8_t cShift)
623	{
624	if (pr32->s.uFraction >= RT_BIT_32(cShift))
625	pr32->s.uFraction >>= cShift;
626	else
627	pr32->s.uFraction = (cShift % 19) + 1;
628	}
629
630
631	static RTFLOAT32U RandR32Ex(uint8_t bType)
632	{
633	RTFLOAT32U r32;
634	r32.u = RandU32();
635
636	/*
637	* Make it more likely that we get a good selection of special values.
638	* On average 6 out of 16 calls should return a special value.
639	*/
640	bType &= 0xf;
641	if (bType == 0 \|\| bType == 1)
642	{
643	/* 0 or Infinity. We only keep fSign here. */
644	r32.s.uExponent = bType == 0 ? 0 : 0xff;
645	r32.s.uFraction = 0;
646	AssertMsg(bType != 0 \|\| RTFLOAT32U_IS_ZERO(&r32), ("%s\n", FormatR32(&r32)));
647	AssertMsg(bType != 1 \|\| RTFLOAT32U_IS_INF(&r32), ("%s\n", FormatR32(&r32)));
648	}
649	else if (bType == 2 \|\| bType == 3)
650	{
651	/* Subnormals */
652	if (bType == 3)
653	SafeR32FractionShift(&r32, r32.s.uExponent % 22);
654	else if (r32.s.uFraction == 0)
655	r32.s.uFraction = RTRandU32Ex(1, RT_BIT_32(RTFLOAT32U_FRACTION_BITS) - 1);
656	r32.s.uExponent = 0;
657	AssertMsg(RTFLOAT32U_IS_SUBNORMAL(&r32), ("%s bType=%#x\n", FormatR32(&r32), bType));
658	}
659	else if (bType == 4 \|\| bType == 5 \|\| bType == 6 \|\| bType == 7)
660	{
661	/* NaNs */
662	if (bType & 1)
663	SafeR32FractionShift(&r32, r32.s.uExponent % 22);
664	else if (r32.s.uFraction == 0)
665	r32.s.uFraction = RTRandU32Ex(1, RT_BIT_32(RTFLOAT32U_FRACTION_BITS) - 1);
666	r32.s.uExponent = 0xff;
667	if (bType < 6)
668	r32.s.uFraction \|= RT_BIT_32(RTFLOAT32U_FRACTION_BITS - 1); /* quiet */
669	else
670	r32.s.uFraction &= ~RT_BIT_32(RTFLOAT32U_FRACTION_BITS - 1); /* signalling */
671	AssertMsg(bType >= 6 \|\| RTFLOAT32U_IS_QUIET_NAN(&r32), ("%s bType=%#x\n", FormatR32(&r32), bType));
672	AssertMsg(bType < 6 \|\| RTFLOAT32U_IS_SIGNALLING_NAN(&r32), ("%s bType=%#x\n", FormatR32(&r32), bType));
673	AssertMsg(RTFLOAT32U_IS_NAN(&r32), ("%s bType=%#x\n", FormatR32(&r32), bType));
674	}
675	else if (bType < 12)
676	{
677	/* Make sure we have lots of normalized values. */
678	if (r32.s.uExponent == 0)
679	r32.s.uExponent = 1;
680	else if (r32.s.uExponent == 0xff)
681	r32.s.uExponent = 0xfe;
682	AssertMsg(RTFLOAT32U_IS_NORMAL(&r32), ("%s bType=%#x\n", FormatR32(&r32), bType));
683	}
684	return r32;
685	}
686
687
688	static RTFLOAT32U RandR32Src(uint32_t iTest)
689	{
690	if (iTest < 16)
691	return RandR32Ex(iTest);
692	return RandR32Ex(RandU8());
693	}
694
695
696	/** Pairing with a 80-bit floating point arg. */
697	static RTFLOAT32U RandR32Src2(uint32_t iTest)
698	{
699	if (iTest < 12 * 10)
700	return RandR32Ex(9 - iTest % 10); /* start with normal values */
701	return RandR32Ex(RandU8());
702	}
703
704
705	static RTPBCD80U RandD80Src(uint32_t iTest)
706	{
707	if (iTest < 3)
708	{
709	RTPBCD80U d80Zero = RTPBCD80U_INIT_ZERO(!(iTest & 1));
710	return d80Zero;
711	}
712	if (iTest < 5)
713	{
714	RTPBCD80U d80Ind = RTPBCD80U_INIT_INDEFINITE();
715	return d80Ind;
716	}
717
718	RTPBCD80U d80;
719	uint8_t b = RandU8();
720	d80.s.fSign = b & 1;
721
722	if ((iTest & 7) >= 6)
723	{
724	/* Illegal */
725	d80.s.uPad = (iTest & 7) == 7 ? b >> 1 : 0;
726	for (size_t iPair = 0; iPair < RT_ELEMENTS(d80.s.abPairs); iPair++)
727	d80.s.abPairs[iPair] = RandU8();
728	}
729	else
730	{
731	/* Normal */
732	d80.s.uPad = 0;
733	for (size_t iPair = 0; iPair < RT_ELEMENTS(d80.s.abPairs); iPair++)
734	{
735	uint8_t const uLo = (uint8_t)RTRandU32Ex(0, 9);
736	uint8_t const uHi = (uint8_t)RTRandU32Ex(0, 9);
737	d80.s.abPairs[iPair] = RTPBCD80U_MAKE_PAIR(uHi, uLo);
738	}
739	}
740	return d80;
741	}
742
743
744	const char *GenFormatR80(PCRTFLOAT80U plrd)
745	{
746	if (RTFLOAT80U_IS_ZERO(plrd))
747	return plrd->s.fSign ? "RTFLOAT80U_INIT_ZERO(1)" : "RTFLOAT80U_INIT_ZERO(0)";
748	if (RTFLOAT80U_IS_INF(plrd))
749	return plrd->s.fSign ? "RTFLOAT80U_INIT_INF(1)" : "RTFLOAT80U_INIT_INF(0)";
750	if (RTFLOAT80U_IS_INDEFINITE(plrd))
751	return plrd->s.fSign ? "RTFLOAT80U_INIT_IND(1)" : "RTFLOAT80U_INIT_IND(0)";
752	if (RTFLOAT80U_IS_QUIET_NAN(plrd) && (plrd->s.uMantissa & (RT_BIT_64(62) - 1)) == 1)
753	return plrd->s.fSign ? "RTFLOAT80U_INIT_QNAN(1)" : "RTFLOAT80U_INIT_QNAN(0)";
754	if (RTFLOAT80U_IS_SIGNALLING_NAN(plrd) && (plrd->s.uMantissa & (RT_BIT_64(62) - 1)) == 1)
755	return plrd->s.fSign ? "RTFLOAT80U_INIT_SNAN(1)" : "RTFLOAT80U_INIT_SNAN(0)";
756
757	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
758	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "RTFLOAT80U_INIT_C(%d,%#RX64,%u)",
759	plrd->s.fSign, plrd->s.uMantissa, plrd->s.uExponent);
760	return pszBuf;
761	}
762
763	const char *GenFormatR64(PCRTFLOAT64U prd)
764	{
765	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
766	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "RTFLOAT64U_INIT_C(%d,%#RX64,%u)",
767	prd->s.fSign, RT_MAKE_U64(prd->s.uFractionLow, prd->s.uFractionHigh), prd->s.uExponent);
768	return pszBuf;
769	}
770
771
772	const char *GenFormatR32(PCRTFLOAT32U pr)
773	{
774	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
775	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "RTFLOAT32U_INIT_C(%d,%#RX32,%u)", pr->s.fSign, pr->s.uFraction, pr->s.uExponent);
776	return pszBuf;
777	}
778
779
780	const char *GenFormatD80(PCRTPBCD80U pd80)
781	{
782	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
783	size_t off;
784	if (pd80->s.uPad == 0)
785	off = RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "RTPBCD80U_INIT_C(%d", pd80->s.fSign);
786	else
787	off = RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "RTPBCD80U_INIT_EX_C(%#x,%d", pd80->s.uPad, pd80->s.fSign);
788	size_t iPair = RT_ELEMENTS(pd80->s.abPairs);
789	while (iPair-- > 0)
790	off += RTStrPrintf(&pszBuf[off], sizeof(g_aszBuf[0]) - off, ",%d,%d",
791	RTPBCD80U_HI_DIGIT(pd80->s.abPairs[iPair]),
792	RTPBCD80U_LO_DIGIT(pd80->s.abPairs[iPair]));
793	pszBuf[off++] = ')';
794	pszBuf[off++] = '\0';
795	return pszBuf;
796	}
797
798
799	const char *GenFormatI64(int64_t i64)
800	{
801	if (i64 == INT64_MIN) /* This one is problematic */
802	return "INT64_MIN";
803	if (i64 == INT64_MAX)
804	return "INT64_MAX";
805	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
806	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "INT64_C(%RI64)", i64);
807	return pszBuf;
808	}
809
810
811	const char GenFormatI64(int64_t const pi64)
812	{
813	return GenFormatI64(*pi64);
814	}
815
816
817	const char *GenFormatI32(int32_t i32)
818	{
819	if (i32 == INT32_MIN) /* This one is problematic */
820	return "INT32_MIN";
821	if (i32 == INT32_MAX)
822	return "INT32_MAX";
823	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
824	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "INT32_C(%RI32)", i32);
825	return pszBuf;
826	}
827
828
829	const char GenFormatI32(int32_t const pi32)
830	{
831	return GenFormatI32(*pi32);
832	}
833
834
835	const char *GenFormatI16(int16_t i16)
836	{
837	if (i16 == INT16_MIN) /* This one is problematic */
838	return "INT16_MIN";
839	if (i16 == INT16_MAX)
840	return "INT16_MAX";
841	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
842	RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), "INT16_C(%RI16)", i16);
843	return pszBuf;
844	}
845
846
847	const char GenFormatI16(int16_t const pi16)
848	{
849	return GenFormatI16(*pi16);
850	}
851
852
853	static void GenerateHeader(PRTSTREAM pOut, const char pszCpuDesc, const char pszCpuType)
854	{
855	/* We want to tag the generated source code with the revision that produced it. */
856	static char s_szRev[] = "$Revision$";
857	const char *pszRev = RTStrStripL(strchr(s_szRev, ':') + 1);
858	size_t cchRev = 0;
859	while (RT_C_IS_DIGIT(pszRev[cchRev]))
860	cchRev++;
861
862	RTStrmPrintf(pOut,
863	"/* $Id: tstIEMAImpl.cpp 96922 2022-09-28 19:23:12Z vboxsync $ */\n"
864	"/** @file\n"
865	" * IEM Assembly Instruction Helper Testcase Data%s%s - r%.*s on %s.\n"
866	" */\n"
867	"\n"
868	"/*\n"
869	" * Copyright (C) 2022 Oracle and/or its affiliates.\n"
870	" *\n"
871	" * This file is part of VirtualBox base platform packages, as\n"
872	" * available from https://www.virtualbox.org.\n"
873	" *\n"
874	" * This program is free software; you can redistribute it and/or\n"
875	" * modify it under the terms of the GNU General Public License\n"
876	" * as published by the Free Software Foundation, in version 3 of the\n"
877	" * License.\n"
878	" *\n"
879	" * This program is distributed in the hope that it will be useful, but\n"
880	" * WITHOUT ANY WARRANTY; without even the implied warranty of\n"
881	" * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n"
882	" * General Public License for more details.\n"
883	" *\n"
884	" * You should have received a copy of the GNU General Public License\n"
885	" * along with this program; if not, see <https://www.gnu.org/licenses>.\n"
886	" *\n"
887	" * SPDX-License-Identifier: GPL-3.0-only\n"
888	" */\n"
889	"\n"
890	"#include \"tstIEMAImpl.h\"\n"
891	"\n"
892	,
893	pszCpuType ? " " : "", pszCpuType ? pszCpuType : "", cchRev, pszRev, pszCpuDesc);
894	}
895
896
897	static PRTSTREAM GenerateOpenWithHdr(const char pszFilename, const char pszCpuDesc, const char *pszCpuType)
898	{
899	PRTSTREAM pOut = NULL;
900	int rc = RTStrmOpen(pszFilename, "w", &pOut);
901	if (RT_SUCCESS(rc))
902	{
903	GenerateHeader(pOut, pszCpuDesc, pszCpuType);
904	return pOut;
905	}
906	RTMsgError("Failed to open %s for writing: %Rrc", pszFilename, rc);
907	return NULL;
908	}
909
910
911	static RTEXITCODE GenerateFooterAndClose(PRTSTREAM pOut, const char *pszFilename, RTEXITCODE rcExit)
912	{
913	RTStrmPrintf(pOut,
914	"\n"
915	"/* end of file */\n");
916	int rc = RTStrmClose(pOut);
917	if (RT_SUCCESS(rc))
918	return rcExit;
919	return RTMsgErrorExitFailure("RTStrmClose failed on %s: %Rrc", pszFilename, rc);
920	}
921
922
923	static void GenerateArrayStart(PRTSTREAM pOut, const char pszName, const char pszType)
924	{
925	RTStrmPrintf(pOut, "%s const g_aTests_%s[] =\n{\n", pszType, pszName);
926	}
927
928
929	static void GenerateArrayEnd(PRTSTREAM pOut, const char *pszName)
930	{
931	RTStrmPrintf(pOut,
932	"};\n"
933	"uint32_t const g_cTests_%s = RT_ELEMENTS(g_aTests_%s);\n"
934	"\n",
935	pszName, pszName);
936	}
937
938	#endif /* TSTIEMAIMPL_WITH_GENERATOR */
939
940
941	/*
942	* Test helpers.
943	*/
944	static bool IsTestEnabled(const char *pszName)
945	{
946	/* Process excludes first: */
947	uint32_t i = g_cExcludeTestPatterns;
948	while (i-- > 0)
949	if (RTStrSimplePatternMultiMatch(g_apszExcludeTestPatterns[i], RTSTR_MAX, pszName, RTSTR_MAX, NULL))
950	return false;
951
952	/* If no include patterns, everything is included: */
953	i = g_cIncludeTestPatterns;
954	if (!i)
955	return true;
956
957	/* Otherwise only tests in the include patters gets tested: */
958	while (i-- > 0)
959	if (RTStrSimplePatternMultiMatch(g_apszIncludeTestPatterns[i], RTSTR_MAX, pszName, RTSTR_MAX, NULL))
960	return true;
961
962	return false;
963	}
964
965
966	static bool SubTestAndCheckIfEnabled(const char *pszName)
967	{
968	RTTestSub(g_hTest, pszName);
969	if (IsTestEnabled(pszName))
970	return true;
971	RTTestSkipped(g_hTest, g_cVerbosity > 0 ? "excluded" : NULL);
972	return false;
973	}
974
975
976	static const char *EFlagsDiff(uint32_t fActual, uint32_t fExpected)
977	{
978	if (fActual == fExpected)
979	return "";
980
981	uint32_t const fXor = fActual ^ fExpected;
982	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
983	size_t cch = RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), " - %#x", fXor);
984
985	static struct
986	{
987	const char *pszName;
988	uint32_t fFlag;
989	} const s_aFlags[] =
990	{
991	#define EFL_ENTRY(a_Flags) { #a_Flags, X86_EFL_ ## a_Flags }
992	EFL_ENTRY(CF),
993	EFL_ENTRY(PF),
994	EFL_ENTRY(AF),
995	EFL_ENTRY(ZF),
996	EFL_ENTRY(SF),
997	EFL_ENTRY(TF),
998	EFL_ENTRY(IF),
999	EFL_ENTRY(DF),
1000	EFL_ENTRY(OF),
1001	EFL_ENTRY(IOPL),
1002	EFL_ENTRY(NT),
1003	EFL_ENTRY(RF),
1004	EFL_ENTRY(VM),
1005	EFL_ENTRY(AC),
1006	EFL_ENTRY(VIF),
1007	EFL_ENTRY(VIP),
1008	EFL_ENTRY(ID),
1009	};
1010	for (size_t i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1011	if (s_aFlags[i].fFlag & fXor)
1012	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch,
1013	s_aFlags[i].fFlag & fActual ? "/%s" : "/!%s", s_aFlags[i].pszName);
1014	RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "");
1015	return pszBuf;
1016	}
1017
1018
1019	static const char *FswDiff(uint16_t fActual, uint16_t fExpected)
1020	{
1021	if (fActual == fExpected)
1022	return "";
1023
1024	uint16_t const fXor = fActual ^ fExpected;
1025	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1026	size_t cch = RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), " - %#x", fXor);
1027
1028	static struct
1029	{
1030	const char *pszName;
1031	uint32_t fFlag;
1032	} const s_aFlags[] =
1033	{
1034	#define FSW_ENTRY(a_Flags) { #a_Flags, X86_FSW_ ## a_Flags }
1035	FSW_ENTRY(IE),
1036	FSW_ENTRY(DE),
1037	FSW_ENTRY(ZE),
1038	FSW_ENTRY(OE),
1039	FSW_ENTRY(UE),
1040	FSW_ENTRY(PE),
1041	FSW_ENTRY(SF),
1042	FSW_ENTRY(ES),
1043	FSW_ENTRY(C0),
1044	FSW_ENTRY(C1),
1045	FSW_ENTRY(C2),
1046	FSW_ENTRY(C3),
1047	FSW_ENTRY(B),
1048	};
1049	for (size_t i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1050	if (s_aFlags[i].fFlag & fXor)
1051	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch,
1052	s_aFlags[i].fFlag & fActual ? "/%s" : "/!%s", s_aFlags[i].pszName);
1053	if (fXor & X86_FSW_TOP_MASK)
1054	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "/TOP%u!%u",
1055	X86_FSW_TOP_GET(fActual), X86_FSW_TOP_GET(fExpected));
1056	#if 0 /* For debugging fprem & fprem1 */
1057	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, " - Q=%d (vs %d)",
1058	X86_FSW_CX_TO_QUOTIENT(fActual), X86_FSW_CX_TO_QUOTIENT(fExpected));
1059	#endif
1060	RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "");
1061	return pszBuf;
1062	}
1063
1064
1065	static const char *MxcsrDiff(uint32_t fActual, uint32_t fExpected)
1066	{
1067	if (fActual == fExpected)
1068	return "";
1069
1070	uint16_t const fXor = fActual ^ fExpected;
1071	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1072	size_t cch = RTStrPrintf(pszBuf, sizeof(g_aszBuf[0]), " - %#x", fXor);
1073
1074	static struct
1075	{
1076	const char *pszName;
1077	uint32_t fFlag;
1078	} const s_aFlags[] =
1079	{
1080	#define MXCSR_ENTRY(a_Flags) { #a_Flags, X86_MXCSR_ ## a_Flags }
1081	MXCSR_ENTRY(IE),
1082	MXCSR_ENTRY(DE),
1083	MXCSR_ENTRY(ZE),
1084	MXCSR_ENTRY(OE),
1085	MXCSR_ENTRY(UE),
1086	MXCSR_ENTRY(PE),
1087
1088	MXCSR_ENTRY(IM),
1089	MXCSR_ENTRY(DM),
1090	MXCSR_ENTRY(ZM),
1091	MXCSR_ENTRY(OM),
1092	MXCSR_ENTRY(UM),
1093	MXCSR_ENTRY(PM),
1094
1095	MXCSR_ENTRY(DAZ),
1096	MXCSR_ENTRY(FZ),
1097	#undef MXCSR_ENTRY
1098	};
1099	for (size_t i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1100	if (s_aFlags[i].fFlag & fXor)
1101	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch,
1102	s_aFlags[i].fFlag & fActual ? "/%s" : "/!%s", s_aFlags[i].pszName);
1103	RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "");
1104	return pszBuf;
1105	}
1106
1107
1108	static const char *FormatFcw(uint16_t fFcw)
1109	{
1110	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1111
1112	const char pszPC = NULL; / (msc+gcc are too stupid) */
1113	switch (fFcw & X86_FCW_PC_MASK)
1114	{
1115	case X86_FCW_PC_24: pszPC = "PC24"; break;
1116	case X86_FCW_PC_RSVD: pszPC = "PCRSVD!"; break;
1117	case X86_FCW_PC_53: pszPC = "PC53"; break;
1118	case X86_FCW_PC_64: pszPC = "PC64"; break;
1119	}
1120
1121	const char pszRC = NULL; / (msc+gcc are too stupid) */
1122	switch (fFcw & X86_FCW_RC_MASK)
1123	{
1124	case X86_FCW_RC_NEAREST: pszRC = "NEAR"; break;
1125	case X86_FCW_RC_DOWN: pszRC = "DOWN"; break;
1126	case X86_FCW_RC_UP: pszRC = "UP"; break;
1127	case X86_FCW_RC_ZERO: pszRC = "ZERO"; break;
1128	}
1129	size_t cch = RTStrPrintf(&pszBuf[0], sizeof(g_aszBuf[0]), "%s %s", pszPC, pszRC);
1130
1131	static struct
1132	{
1133	const char *pszName;
1134	uint32_t fFlag;
1135	} const s_aFlags[] =
1136	{
1137	#define FCW_ENTRY(a_Flags) { #a_Flags, X86_FCW_ ## a_Flags }
1138	FCW_ENTRY(IM),
1139	FCW_ENTRY(DM),
1140	FCW_ENTRY(ZM),
1141	FCW_ENTRY(OM),
1142	FCW_ENTRY(UM),
1143	FCW_ENTRY(PM),
1144	{ "6M", 64 },
1145	};
1146	for (size_t i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1147	if (fFcw & s_aFlags[i].fFlag)
1148	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, " %s", s_aFlags[i].pszName);
1149
1150	RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "");
1151	return pszBuf;
1152	}
1153
1154
1155	static const char *FormatMxcsr(uint32_t fMxcsr)
1156	{
1157	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1158
1159	const char pszRC = NULL; / (msc+gcc are too stupid) */
1160	switch (fMxcsr & X86_MXCSR_RC_MASK)
1161	{
1162	case X86_MXCSR_RC_NEAREST: pszRC = "NEAR"; break;
1163	case X86_MXCSR_RC_DOWN: pszRC = "DOWN"; break;
1164	case X86_MXCSR_RC_UP: pszRC = "UP"; break;
1165	case X86_MXCSR_RC_ZERO: pszRC = "ZERO"; break;
1166	}
1167
1168	const char *pszDAZ = fMxcsr & X86_MXCSR_DAZ ? " DAZ" : "";
1169	const char *pszFZ = fMxcsr & X86_MXCSR_FZ ? " FZ" : "";
1170	size_t cch = RTStrPrintf(&pszBuf[0], sizeof(g_aszBuf[0]), "%s%s%s", pszRC, pszDAZ, pszFZ);
1171
1172	static struct
1173	{
1174	const char *pszName;
1175	uint32_t fFlag;
1176	} const s_aFlags[] =
1177	{
1178	#define MXCSR_ENTRY(a_Flags) { #a_Flags, X86_MXCSR_ ## a_Flags }
1179	MXCSR_ENTRY(IE),
1180	MXCSR_ENTRY(DE),
1181	MXCSR_ENTRY(ZE),
1182	MXCSR_ENTRY(OE),
1183	MXCSR_ENTRY(UE),
1184	MXCSR_ENTRY(PE),
1185
1186	MXCSR_ENTRY(IM),
1187	MXCSR_ENTRY(DM),
1188	MXCSR_ENTRY(ZM),
1189	MXCSR_ENTRY(OM),
1190	MXCSR_ENTRY(UM),
1191	MXCSR_ENTRY(PM),
1192	{ "6M", 64 },
1193	};
1194	for (size_t i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1195	if (fMxcsr & s_aFlags[i].fFlag)
1196	cch += RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, " %s", s_aFlags[i].pszName);
1197
1198	RTStrPrintf(&pszBuf[cch], sizeof(g_aszBuf[0]) - cch, "");
1199	return pszBuf;
1200	}
1201
1202
1203	static const char *FormatR80(PCRTFLOAT80U pr80)
1204	{
1205	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1206	RTStrFormatR80(pszBuf, sizeof(g_aszBuf[0]), pr80, 0, 0, RTSTR_F_SPECIAL);
1207	return pszBuf;
1208	}
1209
1210
1211	static const char *FormatR64(PCRTFLOAT64U pr64)
1212	{
1213	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1214	RTStrFormatR64(pszBuf, sizeof(g_aszBuf[0]), pr64, 0, 0, RTSTR_F_SPECIAL);
1215	return pszBuf;
1216	}
1217
1218
1219	static const char *FormatR32(PCRTFLOAT32U pr32)
1220	{
1221	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1222	RTStrFormatR32(pszBuf, sizeof(g_aszBuf[0]), pr32, 0, 0, RTSTR_F_SPECIAL);
1223	return pszBuf;
1224	}
1225
1226
1227	static const char *FormatD80(PCRTPBCD80U pd80)
1228	{
1229	/* There is only one indefinite endcoding (same as for 80-bit
1230	floating point), so get it out of the way first: */
1231	if (RTPBCD80U_IS_INDEFINITE(pd80))
1232	return "Ind";
1233
1234	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1235	size_t off = 0;
1236	pszBuf[off++] = pd80->s.fSign ? '-' : '+';
1237	unsigned cBadDigits = 0;
1238	size_t iPair = RT_ELEMENTS(pd80->s.abPairs);
1239	while (iPair-- > 0)
1240	{
1241	static const char s_szDigits[] = "0123456789abcdef";
1242	static const uint8_t s_bBadDigits[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 };
1243	pszBuf[off++] = s_szDigits[RTPBCD80U_HI_DIGIT(pd80->s.abPairs[iPair])];
1244	pszBuf[off++] = s_szDigits[RTPBCD80U_LO_DIGIT(pd80->s.abPairs[iPair])];
1245	cBadDigits += s_bBadDigits[RTPBCD80U_HI_DIGIT(pd80->s.abPairs[iPair])]
1246	+ s_bBadDigits[RTPBCD80U_LO_DIGIT(pd80->s.abPairs[iPair])];
1247	}
1248	if (cBadDigits \|\| pd80->s.uPad != 0)
1249	off += RTStrPrintf(&pszBuf[off], sizeof(g_aszBuf[0]) - off, "[%u,%#x]", cBadDigits, pd80->s.uPad);
1250	pszBuf[off] = '\0';
1251	return pszBuf;
1252	}
1253
1254
1255	#if 0
1256	static const char FormatI64(int64_t const piVal)
1257	{
1258	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1259	RTStrFormatU64(pszBuf, sizeof(g_aszBuf[0]), *piVal, 16, 0, 0, RTSTR_F_SPECIAL \| RTSTR_F_VALSIGNED);
1260	return pszBuf;
1261	}
1262	#endif
1263
1264
1265	static const char FormatI32(int32_t const piVal)
1266	{
1267	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1268	RTStrFormatU32(pszBuf, sizeof(g_aszBuf[0]), *piVal, 16, 0, 0, RTSTR_F_SPECIAL \| RTSTR_F_VALSIGNED);
1269	return pszBuf;
1270	}
1271
1272
1273	static const char FormatI16(int16_t const piVal)
1274	{
1275	char *pszBuf = g_aszBuf[g_idxBuf++ % RT_ELEMENTS(g_aszBuf)];
1276	RTStrFormatU16(pszBuf, sizeof(g_aszBuf[0]), *piVal, 16, 0, 0, RTSTR_F_SPECIAL \| RTSTR_F_VALSIGNED);
1277	return pszBuf;
1278	}
1279
1280
1281	/*
1282	* Binary operations.
1283	*/
1284	TYPEDEF_SUBTEST_TYPE(BINU8_T, BINU8_TEST_T, PFNIEMAIMPLBINU8);
1285	TYPEDEF_SUBTEST_TYPE(BINU16_T, BINU16_TEST_T, PFNIEMAIMPLBINU16);
1286	TYPEDEF_SUBTEST_TYPE(BINU32_T, BINU32_TEST_T, PFNIEMAIMPLBINU32);
1287	TYPEDEF_SUBTEST_TYPE(BINU64_T, BINU64_TEST_T, PFNIEMAIMPLBINU64);
1288
1289	#ifdef TSTIEMAIMPL_WITH_GENERATOR
1290	# define GEN_BINARY_TESTS(a_cBits, a_Fmt, a_TestType) \
1291	static void BinU ## a_cBits ## Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests) \
1292	{ \
1293	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aBinU ## a_cBits); iFn++) \
1294	{ \
1295	PFNIEMAIMPLBINU ## a_cBits const pfn = g_aBinU ## a_cBits[iFn].pfnNative \
1296	? g_aBinU ## a_cBits[iFn].pfnNative : g_aBinU ## a_cBits[iFn].pfn; \
1297	PRTSTREAM pOutFn = pOut; \
1298	if (g_aBinU ## a_cBits[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE) \
1299	{ \
1300	if (g_aBinU ## a_cBits[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour) \
1301	continue; \
1302	pOutFn = pOutCpu; \
1303	} \
1304	\
1305	GenerateArrayStart(pOutFn, g_aBinU ## a_cBits[iFn].pszName, #a_TestType); \
1306	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1307	{ \
1308	a_TestType Test; \
1309	Test.fEflIn = RandEFlags(); \
1310	Test.fEflOut = Test.fEflIn; \
1311	Test.uDstIn = RandU ## a_cBits ## Dst(iTest); \
1312	Test.uDstOut = Test.uDstIn; \
1313	Test.uSrcIn = RandU ## a_cBits ## Src(iTest); \
1314	if (g_aBinU ## a_cBits[iFn].uExtra) \
1315	Test.uSrcIn &= a_cBits - 1; /* Restrict bit index according to operand width */ \
1316	Test.uMisc = 0; \
1317	pfn(&Test.uDstOut, Test.uSrcIn, &Test.fEflOut); \
1318	RTStrmPrintf(pOutFn, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", " a_Fmt ", %#x }, /* #%u */\n", \
1319	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, Test.uSrcIn, Test.uMisc, iTest); \
1320	} \
1321	GenerateArrayEnd(pOutFn, g_aBinU ## a_cBits[iFn].pszName); \
1322	} \
1323	}
1324	#else
1325	# define GEN_BINARY_TESTS(a_cBits, a_Fmt, a_TestType)
1326	#endif
1327
1328	#define TEST_BINARY_OPS(a_cBits, a_uType, a_Fmt, a_TestType, a_aSubTests) \
1329	GEN_BINARY_TESTS(a_cBits, a_Fmt, a_TestType) \
1330	\
1331	static void BinU ## a_cBits ## Test(void) \
1332	{ \
1333	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
1334	{ \
1335	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
1336	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
1337	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
1338	PFNIEMAIMPLBINU ## a_cBits pfn = a_aSubTests[iFn].pfn; \
1339	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
1340	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
1341	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
1342	{ \
1343	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1344	{ \
1345	uint32_t fEfl = paTests[iTest].fEflIn; \
1346	a_uType uDst = paTests[iTest].uDstIn; \
1347	pfn(&uDst, paTests[iTest].uSrcIn, &fEfl); \
1348	if ( uDst != paTests[iTest].uDstOut \
1349	\|\| fEfl != paTests[iTest].fEflOut) \
1350	RTTestFailed(g_hTest, "#%u%s: efl=%#08x dst=" a_Fmt " src=" a_Fmt " -> efl=%#08x dst=" a_Fmt ", expected %#08x & " a_Fmt "%s - %s\n", \
1351	iTest, !iVar ? "" : "/n", paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uSrcIn, \
1352	fEfl, uDst, paTests[iTest].fEflOut, paTests[iTest].uDstOut, \
1353	EFlagsDiff(fEfl, paTests[iTest].fEflOut), \
1354	uDst == paTests[iTest].uDstOut ? "eflags" : fEfl == paTests[iTest].fEflOut ? "dst" : "both"); \
1355	else \
1356	{ \
1357	*g_pu ## a_cBits = paTests[iTest].uDstIn; \
1358	*g_pfEfl = paTests[iTest].fEflIn; \
1359	pfn(g_pu ## a_cBits, paTests[iTest].uSrcIn, g_pfEfl); \
1360	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits == paTests[iTest].uDstOut); \
1361	RTTEST_CHECK(g_hTest, *g_pfEfl == paTests[iTest].fEflOut); \
1362	} \
1363	} \
1364	pfn = a_aSubTests[iFn].pfnNative; \
1365	} \
1366	} \
1367	}
1368
1369
1370	/*
1371	* 8-bit binary operations.
1372	*/
1373	static const BINU8_T g_aBinU8[] =
1374	{
1375	ENTRY(add_u8),
1376	ENTRY(add_u8_locked),
1377	ENTRY(adc_u8),
1378	ENTRY(adc_u8_locked),
1379	ENTRY(sub_u8),
1380	ENTRY(sub_u8_locked),
1381	ENTRY(sbb_u8),
1382	ENTRY(sbb_u8_locked),
1383	ENTRY(or_u8),
1384	ENTRY(or_u8_locked),
1385	ENTRY(xor_u8),
1386	ENTRY(xor_u8_locked),
1387	ENTRY(and_u8),
1388	ENTRY(and_u8_locked),
1389	ENTRY(cmp_u8),
1390	ENTRY(test_u8),
1391	};
1392	TEST_BINARY_OPS(8, uint8_t, "%#04x", BINU8_TEST_T, g_aBinU8)
1393
1394
1395	/*
1396	* 16-bit binary operations.
1397	*/
1398	static const BINU16_T g_aBinU16[] =
1399	{
1400	ENTRY(add_u16),
1401	ENTRY(add_u16_locked),
1402	ENTRY(adc_u16),
1403	ENTRY(adc_u16_locked),
1404	ENTRY(sub_u16),
1405	ENTRY(sub_u16_locked),
1406	ENTRY(sbb_u16),
1407	ENTRY(sbb_u16_locked),
1408	ENTRY(or_u16),
1409	ENTRY(or_u16_locked),
1410	ENTRY(xor_u16),
1411	ENTRY(xor_u16_locked),
1412	ENTRY(and_u16),
1413	ENTRY(and_u16_locked),
1414	ENTRY(cmp_u16),
1415	ENTRY(test_u16),
1416	ENTRY_EX(bt_u16, 1),
1417	ENTRY_EX(btc_u16, 1),
1418	ENTRY_EX(btc_u16_locked, 1),
1419	ENTRY_EX(btr_u16, 1),
1420	ENTRY_EX(btr_u16_locked, 1),
1421	ENTRY_EX(bts_u16, 1),
1422	ENTRY_EX(bts_u16_locked, 1),
1423	ENTRY_AMD( bsf_u16, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1424	ENTRY_INTEL(bsf_u16, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1425	ENTRY_AMD( bsr_u16, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1426	ENTRY_INTEL(bsr_u16, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1427	ENTRY_AMD( imul_two_u16, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1428	ENTRY_INTEL(imul_two_u16, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1429	ENTRY(arpl),
1430	};
1431	TEST_BINARY_OPS(16, uint16_t, "%#06x", BINU16_TEST_T, g_aBinU16)
1432
1433
1434	/*
1435	* 32-bit binary operations.
1436	*/
1437	static const BINU32_T g_aBinU32[] =
1438	{
1439	ENTRY(add_u32),
1440	ENTRY(add_u32_locked),
1441	ENTRY(adc_u32),
1442	ENTRY(adc_u32_locked),
1443	ENTRY(sub_u32),
1444	ENTRY(sub_u32_locked),
1445	ENTRY(sbb_u32),
1446	ENTRY(sbb_u32_locked),
1447	ENTRY(or_u32),
1448	ENTRY(or_u32_locked),
1449	ENTRY(xor_u32),
1450	ENTRY(xor_u32_locked),
1451	ENTRY(and_u32),
1452	ENTRY(and_u32_locked),
1453	ENTRY(cmp_u32),
1454	ENTRY(test_u32),
1455	ENTRY_EX(bt_u32, 1),
1456	ENTRY_EX(btc_u32, 1),
1457	ENTRY_EX(btc_u32_locked, 1),
1458	ENTRY_EX(btr_u32, 1),
1459	ENTRY_EX(btr_u32_locked, 1),
1460	ENTRY_EX(bts_u32, 1),
1461	ENTRY_EX(bts_u32_locked, 1),
1462	ENTRY_AMD( bsf_u32, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1463	ENTRY_INTEL(bsf_u32, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1464	ENTRY_AMD( bsr_u32, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1465	ENTRY_INTEL(bsr_u32, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1466	ENTRY_AMD( imul_two_u32, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1467	ENTRY_INTEL(imul_two_u32, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1468	};
1469	TEST_BINARY_OPS(32, uint32_t, "%#010RX32", BINU32_TEST_T, g_aBinU32)
1470
1471
1472	/*
1473	* 64-bit binary operations.
1474	*/
1475	static const BINU64_T g_aBinU64[] =
1476	{
1477	ENTRY(add_u64),
1478	ENTRY(add_u64_locked),
1479	ENTRY(adc_u64),
1480	ENTRY(adc_u64_locked),
1481	ENTRY(sub_u64),
1482	ENTRY(sub_u64_locked),
1483	ENTRY(sbb_u64),
1484	ENTRY(sbb_u64_locked),
1485	ENTRY(or_u64),
1486	ENTRY(or_u64_locked),
1487	ENTRY(xor_u64),
1488	ENTRY(xor_u64_locked),
1489	ENTRY(and_u64),
1490	ENTRY(and_u64_locked),
1491	ENTRY(cmp_u64),
1492	ENTRY(test_u64),
1493	ENTRY_EX(bt_u64, 1),
1494	ENTRY_EX(btc_u64, 1),
1495	ENTRY_EX(btc_u64_locked, 1),
1496	ENTRY_EX(btr_u64, 1),
1497	ENTRY_EX(btr_u64_locked, 1),
1498	ENTRY_EX(bts_u64, 1),
1499	ENTRY_EX(bts_u64_locked, 1),
1500	ENTRY_AMD( bsf_u64, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1501	ENTRY_INTEL(bsf_u64, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1502	ENTRY_AMD( bsr_u64, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1503	ENTRY_INTEL(bsr_u64, X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_SF \| X86_EFL_OF),
1504	ENTRY_AMD( imul_two_u64, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1505	ENTRY_INTEL(imul_two_u64, X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF),
1506	};
1507	TEST_BINARY_OPS(64, uint64_t, "%#018RX64", BINU64_TEST_T, g_aBinU64)
1508
1509
1510	/*
1511	* XCHG
1512	*/
1513	static void XchgTest(void)
1514	{
1515	if (!SubTestAndCheckIfEnabled("xchg"))
1516	return;
1517	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLXCHGU8, (uint8_t pu8Mem, uint8_t pu8Reg));
1518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLXCHGU16,(uint16_t pu16Mem, uint16_t pu16Reg));
1519	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLXCHGU32,(uint32_t pu32Mem, uint32_t pu32Reg));
1520	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLXCHGU64,(uint64_t pu64Mem, uint64_t pu64Reg));
1521
1522	static struct
1523	{
1524	uint8_t cb; uint64_t fMask;
1525	union
1526	{
1527	uintptr_t pfn;
1528	FNIEMAIMPLXCHGU8 *pfnU8;
1529	FNIEMAIMPLXCHGU16 *pfnU16;
1530	FNIEMAIMPLXCHGU32 *pfnU32;
1531	FNIEMAIMPLXCHGU64 *pfnU64;
1532	} u;
1533	}
1534	s_aXchgWorkers[] =
1535	{
1536	{ 1, UINT8_MAX, { (uintptr_t)iemAImpl_xchg_u8_locked } },
1537	{ 2, UINT16_MAX, { (uintptr_t)iemAImpl_xchg_u16_locked } },
1538	{ 4, UINT32_MAX, { (uintptr_t)iemAImpl_xchg_u32_locked } },
1539	{ 8, UINT64_MAX, { (uintptr_t)iemAImpl_xchg_u64_locked } },
1540	{ 1, UINT8_MAX, { (uintptr_t)iemAImpl_xchg_u8_unlocked } },
1541	{ 2, UINT16_MAX, { (uintptr_t)iemAImpl_xchg_u16_unlocked } },
1542	{ 4, UINT32_MAX, { (uintptr_t)iemAImpl_xchg_u32_unlocked } },
1543	{ 8, UINT64_MAX, { (uintptr_t)iemAImpl_xchg_u64_unlocked } },
1544	};
1545	for (size_t i = 0; i < RT_ELEMENTS(s_aXchgWorkers); i++)
1546	{
1547	RTUINT64U uIn1, uIn2, uMem, uDst;
1548	uMem.u = uIn1.u = RTRandU64Ex(0, s_aXchgWorkers[i].fMask);
1549	uDst.u = uIn2.u = RTRandU64Ex(0, s_aXchgWorkers[i].fMask);
1550	if (uIn1.u == uIn2.u)
1551	uDst.u = uIn2.u = ~uIn2.u;
1552
1553	switch (s_aXchgWorkers[i].cb)
1554	{
1555	case 1:
1556	s_aXchgWorkers[i].u.pfnU8(g_pu8, g_pu8Two);
1557	s_aXchgWorkers[i].u.pfnU8(&uMem.au8[0], &uDst.au8[0]);
1558	break;
1559	case 2:
1560	s_aXchgWorkers[i].u.pfnU16(g_pu16, g_pu16Two);
1561	s_aXchgWorkers[i].u.pfnU16(&uMem.Words.w0, &uDst.Words.w0);
1562	break;
1563	case 4:
1564	s_aXchgWorkers[i].u.pfnU32(g_pu32, g_pu32Two);
1565	s_aXchgWorkers[i].u.pfnU32(&uMem.DWords.dw0, &uDst.DWords.dw0);
1566	break;
1567	case 8:
1568	s_aXchgWorkers[i].u.pfnU64(g_pu64, g_pu64Two);
1569	s_aXchgWorkers[i].u.pfnU64(&uMem.u, &uDst.u);
1570	break;
1571	default: RTTestFailed(g_hTest, "%d\n", s_aXchgWorkers[i].cb); break;
1572	}
1573
1574	if (uMem.u != uIn2.u \|\| uDst.u != uIn1.u)
1575	RTTestFailed(g_hTest, "i=%u: %#RX64, %#RX64 -> %#RX64, %#RX64\n", i, uIn1.u, uIn2.u, uMem.u, uDst.u);
1576	}
1577	}
1578
1579
1580	/*
1581	* XADD
1582	*/
1583	static void XaddTest(void)
1584	{
1585	#define TEST_XADD(a_cBits, a_Type, a_Fmt) do { \
1586	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLXADDU ## a_cBits, (a_Type , a_Type , uint32_t *)); \
1587	static struct \
1588	{ \
1589	const char *pszName; \
1590	FNIEMAIMPLXADDU ## a_cBits *pfn; \
1591	BINU ## a_cBits ## _TEST_T const *paTests; \
1592	uint32_t const *pcTests; \
1593	} const s_aFuncs[] = \
1594	{ \
1595	{ "xadd_u" # a_cBits, iemAImpl_xadd_u ## a_cBits, \
1596	g_aTests_add_u ## a_cBits, &g_cTests_add_u ## a_cBits }, \
1597	{ "xadd_u" # a_cBits "8_locked", iemAImpl_xadd_u ## a_cBits ## _locked, \
1598	g_aTests_add_u ## a_cBits, &g_cTests_add_u ## a_cBits }, \
1599	}; \
1600	for (size_t iFn = 0; iFn < RT_ELEMENTS(s_aFuncs); iFn++) \
1601	{ \
1602	if (!SubTestAndCheckIfEnabled(s_aFuncs[iFn].pszName)) continue; \
1603	uint32_t const cTests = *s_aFuncs[iFn].pcTests; \
1604	BINU ## a_cBits ## _TEST_T const * const paTests = s_aFuncs[iFn].paTests; \
1605	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
1606	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
1607	{ \
1608	uint32_t fEfl = paTests[iTest].fEflIn; \
1609	a_Type uSrc = paTests[iTest].uSrcIn; \
1610	*g_pu ## a_cBits = paTests[iTest].uDstIn; \
1611	s_aFuncs[iFn].pfn(g_pu ## a_cBits, &uSrc, &fEfl); \
1612	if ( fEfl != paTests[iTest].fEflOut \
1613	\|\| *g_pu ## a_cBits != paTests[iTest].uDstOut \
1614	\|\| uSrc != paTests[iTest].uDstIn) \
1615	RTTestFailed(g_hTest, "%s/#%u: efl=%#08x dst=" a_Fmt " src=" a_Fmt " -> efl=%#08x dst=" a_Fmt " src=" a_Fmt ", expected %#08x, " a_Fmt ", " a_Fmt "%s\n", \
1616	s_aFuncs[iFn].pszName, iTest, paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uSrcIn, \
1617	fEfl, *g_pu ## a_cBits, uSrc, paTests[iTest].fEflOut, paTests[iTest].uDstOut, paTests[iTest].uDstIn, \
1618	EFlagsDiff(fEfl, paTests[iTest].fEflOut)); \
1619	} \
1620	} \
1621	} while(0)
1622	TEST_XADD(8, uint8_t, "%#04x");
1623	TEST_XADD(16, uint16_t, "%#06x");
1624	TEST_XADD(32, uint32_t, "%#010RX32");
1625	TEST_XADD(64, uint64_t, "%#010RX64");
1626	}
1627
1628
1629	/*
1630	* CMPXCHG
1631	*/
1632
1633	static void CmpXchgTest(void)
1634	{
1635	#define TEST_CMPXCHG(a_cBits, a_Type, a_Fmt) do {\
1636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCMPXCHGU ## a_cBits, (a_Type , a_Type , a_Type, uint32_t *)); \
1637	static struct \
1638	{ \
1639	const char *pszName; \
1640	FNIEMAIMPLCMPXCHGU ## a_cBits *pfn; \
1641	PFNIEMAIMPLBINU ## a_cBits pfnSub; \
1642	BINU ## a_cBits ## _TEST_T const *paTests; \
1643	uint32_t const *pcTests; \
1644	} const s_aFuncs[] = \
1645	{ \
1646	{ "cmpxchg_u" # a_cBits, iemAImpl_cmpxchg_u ## a_cBits, iemAImpl_sub_u ## a_cBits, \
1647	g_aTests_cmp_u ## a_cBits, &g_cTests_cmp_u ## a_cBits }, \
1648	{ "cmpxchg_u" # a_cBits "_locked", iemAImpl_cmpxchg_u ## a_cBits ## _locked, iemAImpl_sub_u ## a_cBits, \
1649	g_aTests_cmp_u ## a_cBits, &g_cTests_cmp_u ## a_cBits }, \
1650	}; \
1651	for (size_t iFn = 0; iFn < RT_ELEMENTS(s_aFuncs); iFn++) \
1652	{ \
1653	if (!SubTestAndCheckIfEnabled(s_aFuncs[iFn].pszName)) continue; \
1654	BINU ## a_cBits ## _TEST_T const * const paTests = s_aFuncs[iFn].paTests; \
1655	uint32_t const cTests = *s_aFuncs[iFn].pcTests; \
1656	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
1657	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
1658	{ \
1659	/* as is (99% likely to be negative). */ \
1660	uint32_t fEfl = paTests[iTest].fEflIn; \
1661	a_Type const uNew = paTests[iTest].uSrcIn + 0x42; \
1662	a_Type uA = paTests[iTest].uDstIn; \
1663	*g_pu ## a_cBits = paTests[iTest].uSrcIn; \
1664	a_Type const uExpect = uA != paTests[iTest].uSrcIn ? paTests[iTest].uSrcIn : uNew; \
1665	s_aFuncs[iFn].pfn(g_pu ## a_cBits, &uA, uNew, &fEfl); \
1666	if ( fEfl != paTests[iTest].fEflOut \
1667	\|\| *g_pu ## a_cBits != uExpect \
1668	\|\| uA != paTests[iTest].uSrcIn) \
1669	RTTestFailed(g_hTest, "%s/#%ua: efl=%#08x dst=" a_Fmt " cmp=" a_Fmt " new=" a_Fmt " -> efl=%#08x dst=" a_Fmt " old=" a_Fmt ", expected %#08x, " a_Fmt ", " a_Fmt "%s\n", \
1670	s_aFuncs[iFn].pszName, iTest, paTests[iTest].fEflIn, paTests[iTest].uSrcIn, paTests[iTest].uDstIn, \
1671	uNew, fEfl, *g_pu ## a_cBits, uA, paTests[iTest].fEflOut, uExpect, paTests[iTest].uSrcIn, \
1672	EFlagsDiff(fEfl, paTests[iTest].fEflOut)); \
1673	/* positive */ \
1674	uint32_t fEflExpect = paTests[iTest].fEflIn; \
1675	uA = paTests[iTest].uDstIn; \
1676	s_aFuncs[iFn].pfnSub(&uA, uA, &fEflExpect); \
1677	fEfl = paTests[iTest].fEflIn; \
1678	uA = paTests[iTest].uDstIn; \
1679	*g_pu ## a_cBits = uA; \
1680	s_aFuncs[iFn].pfn(g_pu ## a_cBits, &uA, uNew, &fEfl); \
1681	if ( fEfl != fEflExpect \
1682	\|\| *g_pu ## a_cBits != uNew \
1683	\|\| uA != paTests[iTest].uDstIn) \
1684	RTTestFailed(g_hTest, "%s/#%ua: efl=%#08x dst=" a_Fmt " cmp=" a_Fmt " new=" a_Fmt " -> efl=%#08x dst=" a_Fmt " old=" a_Fmt ", expected %#08x, " a_Fmt ", " a_Fmt "%s\n", \
1685	s_aFuncs[iFn].pszName, iTest, paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uDstIn, \
1686	uNew, fEfl, *g_pu ## a_cBits, uA, fEflExpect, uNew, paTests[iTest].uDstIn, \
1687	EFlagsDiff(fEfl, fEflExpect)); \
1688	} \
1689	} \
1690	} while(0)
1691	TEST_CMPXCHG(8, uint8_t, "%#04RX8");
1692	TEST_CMPXCHG(16, uint16_t, "%#06x");
1693	TEST_CMPXCHG(32, uint32_t, "%#010RX32");
1694	#if ARCH_BITS != 32 /* calling convension issue, skipping as it's an unsupported host */
1695	TEST_CMPXCHG(64, uint64_t, "%#010RX64");
1696	#endif
1697	}
1698
1699	static void CmpXchg8bTest(void)
1700	{
1701	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCMPXCHG8B,(uint64_t , PRTUINT64U, PRTUINT64U, uint32_t ));
1702	static struct
1703	{
1704	const char *pszName;
1705	FNIEMAIMPLCMPXCHG8B *pfn;
1706	} const s_aFuncs[] =
1707	{
1708	{ "cmpxchg8b", iemAImpl_cmpxchg8b },
1709	{ "cmpxchg8b_locked", iemAImpl_cmpxchg8b_locked },
1710	};
1711	for (size_t iFn = 0; iFn < RT_ELEMENTS(s_aFuncs); iFn++)
1712	{
1713	if (!SubTestAndCheckIfEnabled(s_aFuncs[iFn].pszName))
1714	continue;
1715	for (uint32_t iTest = 0; iTest < 4; iTest += 2)
1716	{
1717	uint64_t const uOldValue = RandU64();
1718	uint64_t const uNewValue = RandU64();
1719
1720	/* positive test. */
1721	RTUINT64U uA, uB;
1722	uB.u = uNewValue;
1723	uA.u = uOldValue;
1724	*g_pu64 = uOldValue;
1725	uint32_t fEflIn = RandEFlags();
1726	uint32_t fEfl = fEflIn;
1727	s_aFuncs[iFn].pfn(g_pu64, &uA, &uB, &fEfl);
1728	if ( fEfl != (fEflIn \| X86_EFL_ZF)
1729	\|\| *g_pu64 != uNewValue
1730	\|\| uA.u != uOldValue)
1731	RTTestFailed(g_hTest, "#%u: efl=%#08x dst=%#018RX64 cmp=%#018RX64 new=%#018RX64\n -> efl=%#08x dst=%#018RX64 old=%#018RX64,\n wanted %#08x, %#018RX64, %#018RX64%s\n",
1732	iTest, fEflIn, uOldValue, uOldValue, uNewValue,
1733	fEfl, *g_pu64, uA.u,
1734	(fEflIn \| X86_EFL_ZF), uNewValue, uOldValue, EFlagsDiff(fEfl, fEflIn \| X86_EFL_ZF));
1735	RTTEST_CHECK(g_hTest, uB.u == uNewValue);
1736
1737	/* negative */
1738	uint64_t const uExpect = ~uOldValue;
1739	*g_pu64 = uExpect;
1740	uA.u = uOldValue;
1741	uB.u = uNewValue;
1742	fEfl = fEflIn = RandEFlags();
1743	s_aFuncs[iFn].pfn(g_pu64, &uA, &uB, &fEfl);
1744	if ( fEfl != (fEflIn & ~X86_EFL_ZF)
1745	\|\| *g_pu64 != uExpect
1746	\|\| uA.u != uExpect)
1747	RTTestFailed(g_hTest, "#%u: efl=%#08x dst=%#018RX64 cmp=%#018RX64 new=%#018RX64\n -> efl=%#08x dst=%#018RX64 old=%#018RX64,\n wanted %#08x, %#018RX64, %#018RX64%s\n",
1748	iTest + 1, fEflIn, uExpect, uOldValue, uNewValue,
1749	fEfl, *g_pu64, uA.u,
1750	(fEflIn & ~X86_EFL_ZF), uExpect, uExpect, EFlagsDiff(fEfl, fEflIn & ~X86_EFL_ZF));
1751	RTTEST_CHECK(g_hTest, uB.u == uNewValue);
1752	}
1753	}
1754	}
1755
1756	static void CmpXchg16bTest(void)
1757	{
1758	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCMPXCHG16B,(PRTUINT128U, PRTUINT128U, PRTUINT128U, uint32_t *));
1759	static struct
1760	{
1761	const char *pszName;
1762	FNIEMAIMPLCMPXCHG16B *pfn;
1763	} const s_aFuncs[] =
1764	{
1765	{ "cmpxchg16b", iemAImpl_cmpxchg16b },
1766	{ "cmpxchg16b_locked", iemAImpl_cmpxchg16b_locked },
1767	#if !defined(RT_ARCH_ARM64)
1768	{ "cmpxchg16b_fallback", iemAImpl_cmpxchg16b_fallback },
1769	#endif
1770	};
1771	for (size_t iFn = 0; iFn < RT_ELEMENTS(s_aFuncs); iFn++)
1772	{
1773	if (!SubTestAndCheckIfEnabled(s_aFuncs[iFn].pszName))
1774	continue;
1775	#if !defined(IEM_WITHOUT_ASSEMBLY) && defined(RT_ARCH_AMD64)
1776	if (!(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16))
1777	{
1778	RTTestSkipped(g_hTest, "no hardware cmpxchg16b");
1779	continue;
1780	}
1781	#endif
1782	for (uint32_t iTest = 0; iTest < 4; iTest += 2)
1783	{
1784	RTUINT128U const uOldValue = RandU128();
1785	RTUINT128U const uNewValue = RandU128();
1786
1787	/* positive test. */
1788	RTUINT128U uA, uB;
1789	uB = uNewValue;
1790	uA = uOldValue;
1791	*g_pu128 = uOldValue;
1792	uint32_t fEflIn = RandEFlags();
1793	uint32_t fEfl = fEflIn;
1794	s_aFuncs[iFn].pfn(g_pu128, &uA, &uB, &fEfl);
1795	if ( fEfl != (fEflIn \| X86_EFL_ZF)
1796	\|\| g_pu128->s.Lo != uNewValue.s.Lo
1797	\|\| g_pu128->s.Hi != uNewValue.s.Hi
1798	\|\| uA.s.Lo != uOldValue.s.Lo
1799	\|\| uA.s.Hi != uOldValue.s.Hi)
1800	RTTestFailed(g_hTest, "#%u: efl=%#08x dst=%#018RX64'%016RX64 cmp=%#018RX64'%016RX64 new=%#018RX64'%016RX64\n"
1801	" -> efl=%#08x dst=%#018RX64'%016RX64 old=%#018RX64'%016RX64,\n"
1802	" wanted %#08x, %#018RX64'%016RX64, %#018RX64'%016RX64%s\n",
1803	iTest, fEflIn, uOldValue.s.Hi, uOldValue.s.Lo, uOldValue.s.Hi, uOldValue.s.Lo, uNewValue.s.Hi, uNewValue.s.Lo,
1804	fEfl, g_pu128->s.Hi, g_pu128->s.Lo, uA.s.Hi, uA.s.Lo,
1805	(fEflIn \| X86_EFL_ZF), uNewValue.s.Hi, uNewValue.s.Lo, uOldValue.s.Hi, uOldValue.s.Lo,
1806	EFlagsDiff(fEfl, fEflIn \| X86_EFL_ZF));
1807	RTTEST_CHECK(g_hTest, uB.s.Lo == uNewValue.s.Lo && uB.s.Hi == uNewValue.s.Hi);
1808
1809	/* negative */
1810	RTUINT128U const uExpect = RTUINT128_INIT(~uOldValue.s.Hi, ~uOldValue.s.Lo);
1811	*g_pu128 = uExpect;
1812	uA = uOldValue;
1813	uB = uNewValue;
1814	fEfl = fEflIn = RandEFlags();
1815	s_aFuncs[iFn].pfn(g_pu128, &uA, &uB, &fEfl);
1816	if ( fEfl != (fEflIn & ~X86_EFL_ZF)
1817	\|\| g_pu128->s.Lo != uExpect.s.Lo
1818	\|\| g_pu128->s.Hi != uExpect.s.Hi
1819	\|\| uA.s.Lo != uExpect.s.Lo
1820	\|\| uA.s.Hi != uExpect.s.Hi)
1821	RTTestFailed(g_hTest, "#%u: efl=%#08x dst=%#018RX64'%016RX64 cmp=%#018RX64'%016RX64 new=%#018RX64'%016RX64\n"
1822	" -> efl=%#08x dst=%#018RX64'%016RX64 old=%#018RX64'%016RX64,\n"
1823	" wanted %#08x, %#018RX64'%016RX64, %#018RX64'%016RX64%s\n",
1824	iTest + 1, fEflIn, uExpect.s.Hi, uExpect.s.Lo, uOldValue.s.Hi, uOldValue.s.Lo, uNewValue.s.Hi, uNewValue.s.Lo,
1825	fEfl, g_pu128->s.Hi, g_pu128->s.Lo, uA.s.Hi, uA.s.Lo,
1826	(fEflIn & ~X86_EFL_ZF), uExpect.s.Hi, uExpect.s.Lo, uExpect.s.Hi, uExpect.s.Lo,
1827	EFlagsDiff(fEfl, fEflIn & ~X86_EFL_ZF));
1828	RTTEST_CHECK(g_hTest, uB.s.Lo == uNewValue.s.Lo && uB.s.Hi == uNewValue.s.Hi);
1829	}
1830	}
1831	}
1832
1833
1834	/*
1835	* Double shifts.
1836	*
1837	* Note! We use BINUxx_TEST_T with the shift value in the uMisc field.
1838	*/
1839	#ifdef TSTIEMAIMPL_WITH_GENERATOR
1840	# define GEN_SHIFT_DBL(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
1841	void ShiftDblU ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
1842	{ \
1843	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
1844	{ \
1845	if ( a_aSubTests[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE \
1846	&& a_aSubTests[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour) \
1847	continue; \
1848	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
1849	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1850	{ \
1851	a_TestType Test; \
1852	Test.fEflIn = RandEFlags(); \
1853	Test.fEflOut = Test.fEflIn; \
1854	Test.uDstIn = RandU ## a_cBits ## Dst(iTest); \
1855	Test.uDstOut = Test.uDstIn; \
1856	Test.uSrcIn = RandU ## a_cBits ## Src(iTest); \
1857	Test.uMisc = RandU8() & (a_cBits * 4 - 1); /* need to go way beyond the a_cBits limit */ \
1858	a_aSubTests[iFn].pfnNative(&Test.uDstOut, Test.uSrcIn, Test.uMisc, &Test.fEflOut); \
1859	RTStrmPrintf(pOut, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", " a_Fmt ", %2u }, /* #%u */\n", \
1860	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, Test.uSrcIn, Test.uMisc, iTest); \
1861	} \
1862	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
1863	} \
1864	}
1865	#else
1866	# define GEN_SHIFT_DBL(a_cBits, a_Fmt, a_TestType, a_aSubTests)
1867	#endif
1868
1869	#define TEST_SHIFT_DBL(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType, a_aSubTests) \
1870	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLSHIFTDBLU ## a_cBits); \
1871	\
1872	static a_SubTestType const a_aSubTests[] = \
1873	{ \
1874	ENTRY_AMD(shld_u ## a_cBits, X86_EFL_OF \| X86_EFL_CF), \
1875	ENTRY_INTEL(shld_u ## a_cBits, X86_EFL_OF \| X86_EFL_CF), \
1876	ENTRY_AMD(shrd_u ## a_cBits, X86_EFL_OF \| X86_EFL_CF), \
1877	ENTRY_INTEL(shrd_u ## a_cBits, X86_EFL_OF \| X86_EFL_CF), \
1878	}; \
1879	\
1880	GEN_SHIFT_DBL(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
1881	\
1882	static void ShiftDblU ## a_cBits ## Test(void) \
1883	{ \
1884	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
1885	{ \
1886	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
1887	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
1888	PFNIEMAIMPLSHIFTDBLU ## a_cBits pfn = a_aSubTests[iFn].pfn; \
1889	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
1890	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
1891	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
1892	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
1893	{ \
1894	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1895	{ \
1896	uint32_t fEfl = paTests[iTest].fEflIn; \
1897	a_Type uDst = paTests[iTest].uDstIn; \
1898	pfn(&uDst, paTests[iTest].uSrcIn, paTests[iTest].uMisc, &fEfl); \
1899	if ( uDst != paTests[iTest].uDstOut \
1900	\|\| fEfl != paTests[iTest].fEflOut) \
1901	RTTestFailed(g_hTest, "#%03u%s: efl=%#08x dst=" a_Fmt " src=" a_Fmt " shift=%-2u -> efl=%#08x dst=" a_Fmt ", expected %#08x & " a_Fmt "%s%s\n", \
1902	iTest, iVar == 0 ? "" : "/n", paTests[iTest].fEflIn, \
1903	paTests[iTest].uDstIn, paTests[iTest].uSrcIn, (unsigned)paTests[iTest].uMisc, \
1904	fEfl, uDst, paTests[iTest].fEflOut, paTests[iTest].uDstOut, \
1905	EFlagsDiff(fEfl, paTests[iTest].fEflOut), uDst == paTests[iTest].uDstOut ? "" : " dst!"); \
1906	else \
1907	{ \
1908	*g_pu ## a_cBits = paTests[iTest].uDstIn; \
1909	*g_pfEfl = paTests[iTest].fEflIn; \
1910	pfn(g_pu ## a_cBits, paTests[iTest].uSrcIn, paTests[iTest].uMisc, g_pfEfl); \
1911	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits == paTests[iTest].uDstOut); \
1912	RTTEST_CHECK(g_hTest, *g_pfEfl == paTests[iTest].fEflOut); \
1913	} \
1914	} \
1915	pfn = a_aSubTests[iFn].pfnNative; \
1916	} \
1917	} \
1918	}
1919	TEST_SHIFT_DBL(16, uint16_t, "%#06RX16", BINU16_TEST_T, SHIFT_DBL_U16_T, g_aShiftDblU16)
1920	TEST_SHIFT_DBL(32, uint32_t, "%#010RX32", BINU32_TEST_T, SHIFT_DBL_U32_T, g_aShiftDblU32)
1921	TEST_SHIFT_DBL(64, uint64_t, "%#018RX64", BINU64_TEST_T, SHIFT_DBL_U64_T, g_aShiftDblU64)
1922
1923	#ifdef TSTIEMAIMPL_WITH_GENERATOR
1924	static void ShiftDblGenerate(PRTSTREAM pOut, uint32_t cTests)
1925	{
1926	ShiftDblU16Generate(pOut, cTests);
1927	ShiftDblU32Generate(pOut, cTests);
1928	ShiftDblU64Generate(pOut, cTests);
1929	}
1930	#endif
1931
1932	static void ShiftDblTest(void)
1933	{
1934	ShiftDblU16Test();
1935	ShiftDblU32Test();
1936	ShiftDblU64Test();
1937	}
1938
1939
1940	/*
1941	* Unary operators.
1942	*
1943	* Note! We use BINUxx_TEST_T ignoreing uSrcIn and uMisc.
1944	*/
1945	#ifdef TSTIEMAIMPL_WITH_GENERATOR
1946	# define GEN_UNARY(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType) \
1947	void UnaryU ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
1948	{ \
1949	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aUnaryU ## a_cBits); iFn++) \
1950	{ \
1951	GenerateArrayStart(pOut, g_aUnaryU ## a_cBits[iFn].pszName, #a_TestType); \
1952	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1953	{ \
1954	a_TestType Test; \
1955	Test.fEflIn = RandEFlags(); \
1956	Test.fEflOut = Test.fEflIn; \
1957	Test.uDstIn = RandU ## a_cBits(); \
1958	Test.uDstOut = Test.uDstIn; \
1959	Test.uSrcIn = 0; \
1960	Test.uMisc = 0; \
1961	g_aUnaryU ## a_cBits[iFn].pfn(&Test.uDstOut, &Test.fEflOut); \
1962	RTStrmPrintf(pOut, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", 0, 0 }, /* #%u */\n", \
1963	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, iTest); \
1964	} \
1965	GenerateArrayEnd(pOut, g_aUnaryU ## a_cBits[iFn].pszName); \
1966	} \
1967	}
1968	#else
1969	# define GEN_UNARY(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType)
1970	#endif
1971
1972	#define TEST_UNARY(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType) \
1973	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLUNARYU ## a_cBits); \
1974	static a_SubTestType const g_aUnaryU ## a_cBits [] = \
1975	{ \
1976	ENTRY(inc_u ## a_cBits), \
1977	ENTRY(inc_u ## a_cBits ## _locked), \
1978	ENTRY(dec_u ## a_cBits), \
1979	ENTRY(dec_u ## a_cBits ## _locked), \
1980	ENTRY(not_u ## a_cBits), \
1981	ENTRY(not_u ## a_cBits ## _locked), \
1982	ENTRY(neg_u ## a_cBits), \
1983	ENTRY(neg_u ## a_cBits ## _locked), \
1984	}; \
1985	\
1986	GEN_UNARY(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType) \
1987	\
1988	static void UnaryU ## a_cBits ## Test(void) \
1989	{ \
1990	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aUnaryU ## a_cBits); iFn++) \
1991	{ \
1992	if (!SubTestAndCheckIfEnabled(g_aUnaryU ## a_cBits[iFn].pszName)) continue; \
1993	a_TestType const * const paTests = g_aUnaryU ## a_cBits[iFn].paTests; \
1994	uint32_t const cTests = *g_aUnaryU ## a_cBits[iFn].pcTests; \
1995	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
1996	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
1997	{ \
1998	uint32_t fEfl = paTests[iTest].fEflIn; \
1999	a_Type uDst = paTests[iTest].uDstIn; \
2000	g_aUnaryU ## a_cBits[iFn].pfn(&uDst, &fEfl); \
2001	if ( uDst != paTests[iTest].uDstOut \
2002	\|\| fEfl != paTests[iTest].fEflOut) \
2003	RTTestFailed(g_hTest, "#%u: efl=%#08x dst=" a_Fmt " -> efl=%#08x dst=" a_Fmt ", expected %#08x & " a_Fmt "%s\n", \
2004	iTest, paTests[iTest].fEflIn, paTests[iTest].uDstIn, \
2005	fEfl, uDst, paTests[iTest].fEflOut, paTests[iTest].uDstOut, \
2006	EFlagsDiff(fEfl, paTests[iTest].fEflOut)); \
2007	else \
2008	{ \
2009	*g_pu ## a_cBits = paTests[iTest].uDstIn; \
2010	*g_pfEfl = paTests[iTest].fEflIn; \
2011	g_aUnaryU ## a_cBits[iFn].pfn(g_pu ## a_cBits, g_pfEfl); \
2012	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits == paTests[iTest].uDstOut); \
2013	RTTEST_CHECK(g_hTest, *g_pfEfl == paTests[iTest].fEflOut); \
2014	} \
2015	} \
2016	} \
2017	}
2018	TEST_UNARY(8, uint8_t, "%#04RX8", BINU8_TEST_T, INT_UNARY_U8_T)
2019	TEST_UNARY(16, uint16_t, "%#06RX16", BINU16_TEST_T, INT_UNARY_U16_T)
2020	TEST_UNARY(32, uint32_t, "%#010RX32", BINU32_TEST_T, INT_UNARY_U32_T)
2021	TEST_UNARY(64, uint64_t, "%#018RX64", BINU64_TEST_T, INT_UNARY_U64_T)
2022
2023	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2024	static void UnaryGenerate(PRTSTREAM pOut, uint32_t cTests)
2025	{
2026	UnaryU8Generate(pOut, cTests);
2027	UnaryU16Generate(pOut, cTests);
2028	UnaryU32Generate(pOut, cTests);
2029	UnaryU64Generate(pOut, cTests);
2030	}
2031	#endif
2032
2033	static void UnaryTest(void)
2034	{
2035	UnaryU8Test();
2036	UnaryU16Test();
2037	UnaryU32Test();
2038	UnaryU64Test();
2039	}
2040
2041
2042	/*
2043	* Shifts.
2044	*
2045	* Note! We use BINUxx_TEST_T with the shift count in uMisc and uSrcIn unused.
2046	*/
2047	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2048	# define GEN_SHIFT(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
2049	void ShiftU ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
2050	{ \
2051	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2052	{ \
2053	if ( a_aSubTests[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE \
2054	&& a_aSubTests[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour) \
2055	continue; \
2056	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
2057	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
2058	{ \
2059	a_TestType Test; \
2060	Test.fEflIn = RandEFlags(); \
2061	Test.fEflOut = Test.fEflIn; \
2062	Test.uDstIn = RandU ## a_cBits ## Dst(iTest); \
2063	Test.uDstOut = Test.uDstIn; \
2064	Test.uSrcIn = 0; \
2065	Test.uMisc = RandU8() & (a_cBits * 4 - 1); /* need to go way beyond the a_cBits limit */ \
2066	a_aSubTests[iFn].pfnNative(&Test.uDstOut, Test.uMisc, &Test.fEflOut); \
2067	RTStrmPrintf(pOut, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", 0, %-2u }, /* #%u */\n", \
2068	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, Test.uMisc, iTest); \
2069	\
2070	Test.fEflIn = (~Test.fEflIn & X86_EFL_LIVE_MASK) \| X86_EFL_RA1_MASK; \
2071	Test.fEflOut = Test.fEflIn; \
2072	Test.uDstOut = Test.uDstIn; \
2073	a_aSubTests[iFn].pfnNative(&Test.uDstOut, Test.uMisc, &Test.fEflOut); \
2074	RTStrmPrintf(pOut, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", 0, %-2u }, /* #%u b */\n", \
2075	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, Test.uMisc, iTest); \
2076	} \
2077	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
2078	} \
2079	}
2080	#else
2081	# define GEN_SHIFT(a_cBits, a_Fmt, a_TestType, a_aSubTests)
2082	#endif
2083
2084	#define TEST_SHIFT(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType, a_aSubTests) \
2085	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLSHIFTU ## a_cBits); \
2086	static a_SubTestType const a_aSubTests[] = \
2087	{ \
2088	ENTRY_AMD( rol_u ## a_cBits, X86_EFL_OF), \
2089	ENTRY_INTEL(rol_u ## a_cBits, X86_EFL_OF), \
2090	ENTRY_AMD( ror_u ## a_cBits, X86_EFL_OF), \
2091	ENTRY_INTEL(ror_u ## a_cBits, X86_EFL_OF), \
2092	ENTRY_AMD( rcl_u ## a_cBits, X86_EFL_OF), \
2093	ENTRY_INTEL(rcl_u ## a_cBits, X86_EFL_OF), \
2094	ENTRY_AMD( rcr_u ## a_cBits, X86_EFL_OF), \
2095	ENTRY_INTEL(rcr_u ## a_cBits, X86_EFL_OF), \
2096	ENTRY_AMD( shl_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2097	ENTRY_INTEL(shl_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2098	ENTRY_AMD( shr_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2099	ENTRY_INTEL(shr_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2100	ENTRY_AMD( sar_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2101	ENTRY_INTEL(sar_u ## a_cBits, X86_EFL_OF \| X86_EFL_AF), \
2102	}; \
2103	\
2104	GEN_SHIFT(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
2105	\
2106	static void ShiftU ## a_cBits ## Test(void) \
2107	{ \
2108	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2109	{ \
2110	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
2111	PFNIEMAIMPLSHIFTU ## a_cBits pfn = a_aSubTests[iFn].pfn; \
2112	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
2113	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
2114	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
2115	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
2116	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
2117	{ \
2118	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
2119	{ \
2120	uint32_t fEfl = paTests[iTest].fEflIn; \
2121	a_Type uDst = paTests[iTest].uDstIn; \
2122	pfn(&uDst, paTests[iTest].uMisc, &fEfl); \
2123	if ( uDst != paTests[iTest].uDstOut \
2124	\|\| fEfl != paTests[iTest].fEflOut ) \
2125	RTTestFailed(g_hTest, "#%u%s: efl=%#08x dst=" a_Fmt " shift=%2u -> efl=%#08x dst=" a_Fmt ", expected %#08x & " a_Fmt "%s\n", \
2126	iTest, iVar == 0 ? "" : "/n", \
2127	paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uMisc, \
2128	fEfl, uDst, paTests[iTest].fEflOut, paTests[iTest].uDstOut, \
2129	EFlagsDiff(fEfl, paTests[iTest].fEflOut)); \
2130	else \
2131	{ \
2132	*g_pu ## a_cBits = paTests[iTest].uDstIn; \
2133	*g_pfEfl = paTests[iTest].fEflIn; \
2134	pfn(g_pu ## a_cBits, paTests[iTest].uMisc, g_pfEfl); \
2135	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits == paTests[iTest].uDstOut); \
2136	RTTEST_CHECK(g_hTest, *g_pfEfl == paTests[iTest].fEflOut); \
2137	} \
2138	} \
2139	pfn = a_aSubTests[iFn].pfnNative; \
2140	} \
2141	} \
2142	}
2143	TEST_SHIFT(8, uint8_t, "%#04RX8", BINU8_TEST_T, INT_BINARY_U8_T, g_aShiftU8)
2144	TEST_SHIFT(16, uint16_t, "%#06RX16", BINU16_TEST_T, INT_BINARY_U16_T, g_aShiftU16)
2145	TEST_SHIFT(32, uint32_t, "%#010RX32", BINU32_TEST_T, INT_BINARY_U32_T, g_aShiftU32)
2146	TEST_SHIFT(64, uint64_t, "%#018RX64", BINU64_TEST_T, INT_BINARY_U64_T, g_aShiftU64)
2147
2148	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2149	static void ShiftGenerate(PRTSTREAM pOut, uint32_t cTests)
2150	{
2151	ShiftU8Generate(pOut, cTests);
2152	ShiftU16Generate(pOut, cTests);
2153	ShiftU32Generate(pOut, cTests);
2154	ShiftU64Generate(pOut, cTests);
2155	}
2156	#endif
2157
2158	static void ShiftTest(void)
2159	{
2160	ShiftU8Test();
2161	ShiftU16Test();
2162	ShiftU32Test();
2163	ShiftU64Test();
2164	}
2165
2166
2167	/*
2168	* Multiplication and division.
2169	*
2170	* Note! The 8-bit functions has a different format, so we need to duplicate things.
2171	* Note! Currently ignoring undefined bits.
2172	*/
2173
2174	/* U8 */
2175	TYPEDEF_SUBTEST_TYPE(INT_MULDIV_U8_T, MULDIVU8_TEST_T, PFNIEMAIMPLMULDIVU8);
2176	static INT_MULDIV_U8_T const g_aMulDivU8[] =
2177	{
2178	ENTRY_AMD_EX(mul_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF,
2179	X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF),
2180	ENTRY_INTEL_EX(mul_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0),
2181	ENTRY_AMD_EX(imul_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF,
2182	X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF),
2183	ENTRY_INTEL_EX(imul_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0),
2184	ENTRY_AMD_EX(div_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0),
2185	ENTRY_INTEL_EX(div_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0),
2186	ENTRY_AMD_EX(idiv_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0),
2187	ENTRY_INTEL_EX(idiv_u8, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0),
2188	};
2189
2190	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2191	static void MulDivU8Generate(PRTSTREAM pOut, uint32_t cTests)
2192	{
2193	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aMulDivU8); iFn++)
2194	{
2195	if ( g_aMulDivU8[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE
2196	&& g_aMulDivU8[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour)
2197	continue;
2198	GenerateArrayStart(pOut, g_aMulDivU8[iFn].pszName, "MULDIVU8_TEST_T"); \
2199	for (uint32_t iTest = 0; iTest < cTests; iTest++ )
2200	{
2201	MULDIVU8_TEST_T Test;
2202	Test.fEflIn = RandEFlags();
2203	Test.fEflOut = Test.fEflIn;
2204	Test.uDstIn = RandU16Dst(iTest);
2205	Test.uDstOut = Test.uDstIn;
2206	Test.uSrcIn = RandU8Src(iTest);
2207	Test.rc = g_aMulDivU8[iFn].pfnNative(&Test.uDstOut, Test.uSrcIn, &Test.fEflOut);
2208	RTStrmPrintf(pOut, " { %#08x, %#08x, %#06RX16, %#06RX16, %#04RX8, %d }, /* #%u */\n",
2209	Test.fEflIn, Test.fEflOut, Test.uDstIn, Test.uDstOut, Test.uSrcIn, Test.rc, iTest);
2210	}
2211	GenerateArrayEnd(pOut, g_aMulDivU8[iFn].pszName);
2212	}
2213	}
2214	#endif
2215
2216	static void MulDivU8Test(void)
2217	{
2218	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aMulDivU8); iFn++)
2219	{
2220	if (!SubTestAndCheckIfEnabled(g_aMulDivU8[iFn].pszName)) continue; \
2221	MULDIVU8_TEST_T const * const paTests = g_aMulDivU8[iFn].paTests;
2222	uint32_t const cTests = *g_aMulDivU8[iFn].pcTests;
2223	uint32_t const fEflIgn = g_aMulDivU8[iFn].uExtra;
2224	PFNIEMAIMPLMULDIVU8 pfn = g_aMulDivU8[iFn].pfn;
2225	uint32_t const cVars = COUNT_VARIATIONS(g_aMulDivU8[iFn]); \
2226	if (!cTests) RTTestSkipped(g_hTest, "no tests");
2227	for (uint32_t iVar = 0; iVar < cVars; iVar++)
2228	{
2229	for (uint32_t iTest = 0; iTest < cTests; iTest++ )
2230	{
2231	uint32_t fEfl = paTests[iTest].fEflIn;
2232	uint16_t uDst = paTests[iTest].uDstIn;
2233	int rc = g_aMulDivU8[iFn].pfn(&uDst, paTests[iTest].uSrcIn, &fEfl);
2234	if ( uDst != paTests[iTest].uDstOut
2235	\|\| (fEfl \| fEflIgn) != (paTests[iTest].fEflOut \| fEflIgn)
2236	\|\| rc != paTests[iTest].rc)
2237	RTTestFailed(g_hTest, "#%02u%s: efl=%#08x dst=%#06RX16 src=%#04RX8\n"
2238	" %s-> efl=%#08x dst=%#06RX16 rc=%d\n"
2239	"%sexpected %#08x %#06RX16 %d%s\n",
2240	iTest, iVar ? "/n" : "", paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uSrcIn,
2241	iVar ? " " : "", fEfl, uDst, rc,
2242	iVar ? " " : "", paTests[iTest].fEflOut, paTests[iTest].uDstOut, paTests[iTest].rc,
2243	EFlagsDiff(fEfl \| fEflIgn, paTests[iTest].fEflOut \| fEflIgn));
2244	else
2245	{
2246	*g_pu16 = paTests[iTest].uDstIn;
2247	*g_pfEfl = paTests[iTest].fEflIn;
2248	rc = g_aMulDivU8[iFn].pfn(g_pu16, paTests[iTest].uSrcIn, g_pfEfl);
2249	RTTEST_CHECK(g_hTest, *g_pu16 == paTests[iTest].uDstOut);
2250	RTTEST_CHECK(g_hTest, (*g_pfEfl \| fEflIgn) == (paTests[iTest].fEflOut \| fEflIgn));
2251	RTTEST_CHECK(g_hTest, rc == paTests[iTest].rc);
2252	}
2253	}
2254	pfn = g_aMulDivU8[iFn].pfnNative;
2255	}
2256	}
2257	}
2258
2259	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2260	# define GEN_MULDIV(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
2261	void MulDivU ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
2262	{ \
2263	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2264	{ \
2265	if ( a_aSubTests[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE \
2266	&& a_aSubTests[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour) \
2267	continue; \
2268	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
2269	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
2270	{ \
2271	a_TestType Test; \
2272	Test.fEflIn = RandEFlags(); \
2273	Test.fEflOut = Test.fEflIn; \
2274	Test.uDst1In = RandU ## a_cBits ## Dst(iTest); \
2275	Test.uDst1Out = Test.uDst1In; \
2276	Test.uDst2In = RandU ## a_cBits ## Dst(iTest); \
2277	Test.uDst2Out = Test.uDst2In; \
2278	Test.uSrcIn = RandU ## a_cBits ## Src(iTest); \
2279	Test.rc = a_aSubTests[iFn].pfnNative(&Test.uDst1Out, &Test.uDst2Out, Test.uSrcIn, &Test.fEflOut); \
2280	RTStrmPrintf(pOut, " { %#08x, %#08x, " a_Fmt ", " a_Fmt ", " a_Fmt ", " a_Fmt ", " a_Fmt ", %d }, /* #%u */\n", \
2281	Test.fEflIn, Test.fEflOut, Test.uDst1In, Test.uDst1Out, Test.uDst2In, Test.uDst2Out, Test.uSrcIn, \
2282	Test.rc, iTest); \
2283	} \
2284	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
2285	} \
2286	}
2287	#else
2288	# define GEN_MULDIV(a_cBits, a_Fmt, a_TestType, a_aSubTests)
2289	#endif
2290
2291	#define TEST_MULDIV(a_cBits, a_Type, a_Fmt, a_TestType, a_SubTestType, a_aSubTests) \
2292	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLMULDIVU ## a_cBits); \
2293	static a_SubTestType const a_aSubTests [] = \
2294	{ \
2295	ENTRY_AMD_EX(mul_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0), \
2296	ENTRY_INTEL_EX(mul_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0), \
2297	ENTRY_AMD_EX(imul_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0), \
2298	ENTRY_INTEL_EX(imul_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF, 0), \
2299	ENTRY_AMD_EX(div_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0), \
2300	ENTRY_INTEL_EX(div_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0), \
2301	ENTRY_AMD_EX(idiv_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0), \
2302	ENTRY_INTEL_EX(idiv_u ## a_cBits, X86_EFL_SF \| X86_EFL_ZF \| X86_EFL_AF \| X86_EFL_PF \| X86_EFL_CF \| X86_EFL_OF, 0), \
2303	}; \
2304	\
2305	GEN_MULDIV(a_cBits, a_Fmt, a_TestType, a_aSubTests) \
2306	\
2307	static void MulDivU ## a_cBits ## Test(void) \
2308	{ \
2309	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2310	{ \
2311	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
2312	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
2313	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
2314	uint32_t const fEflIgn = a_aSubTests[iFn].uExtra; \
2315	PFNIEMAIMPLMULDIVU ## a_cBits pfn = a_aSubTests[iFn].pfn; \
2316	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
2317	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
2318	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
2319	{ \
2320	for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
2321	{ \
2322	uint32_t fEfl = paTests[iTest].fEflIn; \
2323	a_Type uDst1 = paTests[iTest].uDst1In; \
2324	a_Type uDst2 = paTests[iTest].uDst2In; \
2325	int rc = pfn(&uDst1, &uDst2, paTests[iTest].uSrcIn, &fEfl); \
2326	if ( uDst1 != paTests[iTest].uDst1Out \
2327	\|\| uDst2 != paTests[iTest].uDst2Out \
2328	\|\| (fEfl \| fEflIgn) != (paTests[iTest].fEflOut \| fEflIgn)\
2329	\|\| rc != paTests[iTest].rc) \
2330	RTTestFailed(g_hTest, "#%02u%s: efl=%#08x dst1=" a_Fmt " dst2=" a_Fmt " src=" a_Fmt "\n" \
2331	" -> efl=%#08x dst1=" a_Fmt " dst2=" a_Fmt " rc=%d\n" \
2332	"expected %#08x " a_Fmt " " a_Fmt " %d%s -%s%s%s\n", \
2333	iTest, iVar == 0 ? "" : "/n", \
2334	paTests[iTest].fEflIn, paTests[iTest].uDst1In, paTests[iTest].uDst2In, paTests[iTest].uSrcIn, \
2335	fEfl, uDst1, uDst2, rc, \
2336	paTests[iTest].fEflOut, paTests[iTest].uDst1Out, paTests[iTest].uDst2Out, paTests[iTest].rc, \
2337	EFlagsDiff(fEfl \| fEflIgn, paTests[iTest].fEflOut \| fEflIgn), \
2338	uDst1 != paTests[iTest].uDst1Out ? " dst1" : "", uDst2 != paTests[iTest].uDst2Out ? " dst2" : "", \
2339	(fEfl \| fEflIgn) != (paTests[iTest].fEflOut \| fEflIgn) ? " eflags" : ""); \
2340	else \
2341	{ \
2342	*g_pu ## a_cBits = paTests[iTest].uDst1In; \
2343	*g_pu ## a_cBits ## Two = paTests[iTest].uDst2In; \
2344	*g_pfEfl = paTests[iTest].fEflIn; \
2345	rc = pfn(g_pu ## a_cBits, g_pu ## a_cBits ## Two, paTests[iTest].uSrcIn, g_pfEfl); \
2346	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits == paTests[iTest].uDst1Out); \
2347	RTTEST_CHECK(g_hTest, *g_pu ## a_cBits ## Two == paTests[iTest].uDst2Out); \
2348	RTTEST_CHECK(g_hTest, (*g_pfEfl \| fEflIgn) == (paTests[iTest].fEflOut \| fEflIgn)); \
2349	RTTEST_CHECK(g_hTest, rc == paTests[iTest].rc); \
2350	} \
2351	} \
2352	pfn = a_aSubTests[iFn].pfnNative; \
2353	} \
2354	} \
2355	}
2356	TEST_MULDIV(16, uint16_t, "%#06RX16", MULDIVU16_TEST_T, INT_MULDIV_U16_T, g_aMulDivU16)
2357	TEST_MULDIV(32, uint32_t, "%#010RX32", MULDIVU32_TEST_T, INT_MULDIV_U32_T, g_aMulDivU32)
2358	TEST_MULDIV(64, uint64_t, "%#018RX64", MULDIVU64_TEST_T, INT_MULDIV_U64_T, g_aMulDivU64)
2359
2360	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2361	static void MulDivGenerate(PRTSTREAM pOut, uint32_t cTests)
2362	{
2363	MulDivU8Generate(pOut, cTests);
2364	MulDivU16Generate(pOut, cTests);
2365	MulDivU32Generate(pOut, cTests);
2366	MulDivU64Generate(pOut, cTests);
2367	}
2368	#endif
2369
2370	static void MulDivTest(void)
2371	{
2372	MulDivU8Test();
2373	MulDivU16Test();
2374	MulDivU32Test();
2375	MulDivU64Test();
2376	}
2377
2378
2379	/*
2380	* BSWAP
2381	*/
2382	static void BswapTest(void)
2383	{
2384	if (SubTestAndCheckIfEnabled("bswap_u16"))
2385	{
2386	*g_pu32 = UINT32_C(0x12345678);
2387	iemAImpl_bswap_u16(g_pu32);
2388	#if 0
2389	RTTEST_CHECK_MSG(g_hTest, g_pu32 == UINT32_C(0x12347856), (g_hTest, "g_pu32=%#RX32\n", *g_pu32));
2390	#else
2391	RTTEST_CHECK_MSG(g_hTest, g_pu32 == UINT32_C(0x12340000), (g_hTest, "g_pu32=%#RX32\n", *g_pu32));
2392	#endif
2393	*g_pu32 = UINT32_C(0xffff1122);
2394	iemAImpl_bswap_u16(g_pu32);
2395	#if 0
2396	RTTEST_CHECK_MSG(g_hTest, g_pu32 == UINT32_C(0xffff2211), (g_hTest, "g_pu32=%#RX32\n", *g_pu32));
2397	#else
2398	RTTEST_CHECK_MSG(g_hTest, g_pu32 == UINT32_C(0xffff0000), (g_hTest, "g_pu32=%#RX32\n", *g_pu32));
2399	#endif
2400	}
2401
2402	if (SubTestAndCheckIfEnabled("bswap_u32"))
2403	{
2404	*g_pu32 = UINT32_C(0x12345678);
2405	iemAImpl_bswap_u32(g_pu32);
2406	RTTEST_CHECK(g_hTest, *g_pu32 == UINT32_C(0x78563412));
2407	}
2408
2409	if (SubTestAndCheckIfEnabled("bswap_u64"))
2410	{
2411	*g_pu64 = UINT64_C(0x0123456789abcdef);
2412	iemAImpl_bswap_u64(g_pu64);
2413	RTTEST_CHECK(g_hTest, *g_pu64 == UINT64_C(0xefcdab8967452301));
2414	}
2415	}
2416
2417
2418
2419	/*********************************************************************************************************************************
2420	* Floating point (x87 style) *
2421	*********************************************************************************************************************************/
2422
2423	/*
2424	* FPU constant loading.
2425	*/
2426	TYPEDEF_SUBTEST_TYPE(FPU_LD_CONST_T, FPU_LD_CONST_TEST_T, PFNIEMAIMPLFPUR80LDCONST);
2427
2428	static const FPU_LD_CONST_T g_aFpuLdConst[] =
2429	{
2430	ENTRY(fld1),
2431	ENTRY(fldl2t),
2432	ENTRY(fldl2e),
2433	ENTRY(fldpi),
2434	ENTRY(fldlg2),
2435	ENTRY(fldln2),
2436	ENTRY(fldz),
2437	};
2438
2439	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2440	static void FpuLdConstGenerate(PRTSTREAM pOut, uint32_t cTests)
2441	{
2442	X86FXSTATE State;
2443	RT_ZERO(State);
2444	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuLdConst); iFn++)
2445	{
2446	GenerateArrayStart(pOut, g_aFpuLdConst[iFn].pszName, "FPU_LD_CONST_TEST_T");
2447	for (uint32_t iTest = 0; iTest < cTests; iTest += 4)
2448	{
2449	State.FCW = RandFcw();
2450	State.FSW = RandFsw();
2451
2452	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
2453	{
2454	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
2455	State.FCW = (State.FCW & ~X86_FCW_RC_MASK) \| (iRounding << X86_FCW_RC_SHIFT);
2456	g_aFpuLdConst[iFn].pfn(&State, &Res);
2457	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s }, /* #%u */\n",
2458	State.FCW, State.FSW, Res.FSW, GenFormatR80(&Res.r80Result), iTest + iRounding);
2459	}
2460	}
2461	GenerateArrayEnd(pOut, g_aFpuLdConst[iFn].pszName);
2462	}
2463	}
2464	#endif
2465
2466	static void FpuLoadConstTest(void)
2467	{
2468	/*
2469	* Inputs:
2470	* - FSW: C0, C1, C2, C3
2471	* - FCW: Exception masks, Precision control, Rounding control.
2472	*
2473	* C1 set to 1 on stack overflow, zero otherwise. C0, C2, and C3 are "undefined".
2474	*/
2475	X86FXSTATE State;
2476	RT_ZERO(State);
2477	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuLdConst); iFn++)
2478	{
2479	if (!SubTestAndCheckIfEnabled(g_aFpuLdConst[iFn].pszName))
2480	continue;
2481
2482	uint32_t const cTests = *g_aFpuLdConst[iFn].pcTests;
2483	FPU_LD_CONST_TEST_T const *paTests = g_aFpuLdConst[iFn].paTests;
2484	PFNIEMAIMPLFPUR80LDCONST pfn = g_aFpuLdConst[iFn].pfn;
2485	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuLdConst[iFn]); \
2486	if (!cTests) RTTestSkipped(g_hTest, "no tests");
2487	for (uint32_t iVar = 0; iVar < cVars; iVar++)
2488	{
2489	for (uint32_t iTest = 0; iTest < cTests; iTest++)
2490	{
2491	State.FCW = paTests[iTest].fFcw;
2492	State.FSW = paTests[iTest].fFswIn;
2493	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
2494	pfn(&State, &Res);
2495	if ( Res.FSW != paTests[iTest].fFswOut
2496	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult))
2497	RTTestFailed(g_hTest, "#%u%s: fcw=%#06x fsw=%#06x -> fsw=%#06x %s, expected %#06x %s%s%s (%s)\n",
2498	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
2499	Res.FSW, FormatR80(&Res.r80Result),
2500	paTests[iTest].fFswOut, FormatR80(&paTests[iTest].rdResult),
2501	FswDiff(Res.FSW, paTests[iTest].fFswOut),
2502	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult) ? " - val" : "",
2503	FormatFcw(paTests[iTest].fFcw) );
2504	}
2505	pfn = g_aFpuLdConst[iFn].pfnNative;
2506	}
2507	}
2508	}
2509
2510
2511	/*
2512	* Load floating point values from memory.
2513	*/
2514	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2515	# define GEN_FPU_LOAD(a_cBits, a_rdTypeIn, a_aSubTests, a_TestType) \
2516	static void FpuLdR ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
2517	{ \
2518	X86FXSTATE State; \
2519	RT_ZERO(State); \
2520	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2521	{ \
2522	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
2523	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
2524	{ \
2525	State.FCW = RandFcw(); \
2526	State.FSW = RandFsw(); \
2527	a_rdTypeIn InVal = RandR ## a_cBits ## Src(iTest); \
2528	\
2529	for (uint16_t iRounding = 0; iRounding < 4; iRounding++) \
2530	{ \
2531	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
2532	State.FCW = (State.FCW & ~X86_FCW_RC_MASK) \| (iRounding << X86_FCW_RC_SHIFT); \
2533	a_aSubTests[iFn].pfn(&State, &Res, &InVal); \
2534	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u */\n", \
2535	State.FCW, State.FSW, Res.FSW, GenFormatR80(&Res.r80Result), \
2536	GenFormatR ## a_cBits(&InVal), iTest, iRounding); \
2537	} \
2538	} \
2539	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
2540	} \
2541	}
2542	#else
2543	# define GEN_FPU_LOAD(a_cBits, a_rdTypeIn, a_aSubTests, a_TestType)
2544	#endif
2545
2546	#define TEST_FPU_LOAD(a_cBits, a_rdTypeIn, a_SubTestType, a_aSubTests, a_TestType) \
2547	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPULDR80FROM ## a_cBits,(PCX86FXSTATE, PIEMFPURESULT, PC ## a_rdTypeIn)); \
2548	typedef FNIEMAIMPLFPULDR80FROM ## a_cBits *PFNIEMAIMPLFPULDR80FROM ## a_cBits; \
2549	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLFPULDR80FROM ## a_cBits); \
2550	\
2551	static const a_SubTestType a_aSubTests[] = \
2552	{ \
2553	ENTRY(RT_CONCAT(fld_r80_from_r,a_cBits)) \
2554	}; \
2555	GEN_FPU_LOAD(a_cBits, a_rdTypeIn, a_aSubTests, a_TestType) \
2556	\
2557	static void FpuLdR ## a_cBits ## Test(void) \
2558	{ \
2559	X86FXSTATE State; \
2560	RT_ZERO(State); \
2561	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2562	{ \
2563	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
2564	\
2565	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
2566	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
2567	PFNIEMAIMPLFPULDR80FROM ## a_cBits pfn = a_aSubTests[iFn].pfn; \
2568	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
2569	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
2570	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
2571	{ \
2572	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
2573	{ \
2574	a_rdTypeIn const InVal = paTests[iTest].InVal; \
2575	State.FCW = paTests[iTest].fFcw; \
2576	State.FSW = paTests[iTest].fFswIn; \
2577	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
2578	pfn(&State, &Res, &InVal); \
2579	if ( Res.FSW != paTests[iTest].fFswOut \
2580	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult)) \
2581	RTTestFailed(g_hTest, "#%03u%s: fcw=%#06x fsw=%#06x in=%s\n" \
2582	"%s -> fsw=%#06x %s\n" \
2583	"%s expected %#06x %s%s%s (%s)\n", \
2584	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, \
2585	FormatR ## a_cBits(&paTests[iTest].InVal), \
2586	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result), \
2587	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].rdResult), \
2588	FswDiff(Res.FSW, paTests[iTest].fFswOut), \
2589	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult) ? " - val" : "", \
2590	FormatFcw(paTests[iTest].fFcw) ); \
2591	} \
2592	pfn = a_aSubTests[iFn].pfnNative; \
2593	} \
2594	} \
2595	}
2596
2597	TEST_FPU_LOAD(80, RTFLOAT80U, FPU_LD_R80_T, g_aFpuLdR80, FPU_R80_IN_TEST_T)
2598	TEST_FPU_LOAD(64, RTFLOAT64U, FPU_LD_R64_T, g_aFpuLdR64, FPU_R64_IN_TEST_T)
2599	TEST_FPU_LOAD(32, RTFLOAT32U, FPU_LD_R32_T, g_aFpuLdR32, FPU_R32_IN_TEST_T)
2600
2601	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2602	static void FpuLdMemGenerate(PRTSTREAM pOut, uint32_t cTests)
2603	{
2604	FpuLdR80Generate(pOut, cTests);
2605	FpuLdR64Generate(pOut, cTests);
2606	FpuLdR32Generate(pOut, cTests);
2607	}
2608	#endif
2609
2610	static void FpuLdMemTest(void)
2611	{
2612	FpuLdR80Test();
2613	FpuLdR64Test();
2614	FpuLdR32Test();
2615	}
2616
2617
2618	/*
2619	* Load integer values from memory.
2620	*/
2621	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2622	# define GEN_FPU_LOAD_INT(a_cBits, a_iTypeIn, a_szFmtIn, a_aSubTests, a_TestType) \
2623	static void FpuLdI ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
2624	{ \
2625	X86FXSTATE State; \
2626	RT_ZERO(State); \
2627	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2628	{ \
2629	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
2630	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
2631	{ \
2632	State.FCW = RandFcw(); \
2633	State.FSW = RandFsw(); \
2634	a_iTypeIn InVal = (a_iTypeIn)RandU ## a_cBits ## Src(iTest); \
2635	\
2636	for (uint16_t iRounding = 0; iRounding < 4; iRounding++) \
2637	{ \
2638	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
2639	State.FCW = (State.FCW & ~X86_FCW_RC_MASK) \| (iRounding << X86_FCW_RC_SHIFT); \
2640	a_aSubTests[iFn].pfn(&State, &Res, &InVal); \
2641	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, " a_szFmtIn " }, /* #%u/%u */\n", \
2642	State.FCW, State.FSW, Res.FSW, GenFormatR80(&Res.r80Result), InVal, iTest, iRounding); \
2643	} \
2644	} \
2645	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
2646	} \
2647	}
2648	#else
2649	# define GEN_FPU_LOAD_INT(a_cBits, a_iTypeIn, a_szFmtIn, a_aSubTests, a_TestType)
2650	#endif
2651
2652	#define TEST_FPU_LOAD_INT(a_cBits, a_iTypeIn, a_szFmtIn, a_SubTestType, a_aSubTests, a_TestType) \
2653	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPULDR80FROMI ## a_cBits,(PCX86FXSTATE, PIEMFPURESULT, a_iTypeIn const *)); \
2654	typedef FNIEMAIMPLFPULDR80FROMI ## a_cBits *PFNIEMAIMPLFPULDR80FROMI ## a_cBits; \
2655	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLFPULDR80FROMI ## a_cBits); \
2656	\
2657	static const a_SubTestType a_aSubTests[] = \
2658	{ \
2659	ENTRY(RT_CONCAT(fild_r80_from_i,a_cBits)) \
2660	}; \
2661	GEN_FPU_LOAD_INT(a_cBits, a_iTypeIn, a_szFmtIn, a_aSubTests, a_TestType) \
2662	\
2663	static void FpuLdI ## a_cBits ## Test(void) \
2664	{ \
2665	X86FXSTATE State; \
2666	RT_ZERO(State); \
2667	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2668	{ \
2669	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
2670	\
2671	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
2672	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
2673	PFNIEMAIMPLFPULDR80FROMI ## a_cBits pfn = a_aSubTests[iFn].pfn; \
2674	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
2675	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
2676	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
2677	{ \
2678	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
2679	{ \
2680	a_iTypeIn const iInVal = paTests[iTest].iInVal; \
2681	State.FCW = paTests[iTest].fFcw; \
2682	State.FSW = paTests[iTest].fFswIn; \
2683	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
2684	pfn(&State, &Res, &iInVal); \
2685	if ( Res.FSW != paTests[iTest].fFswOut \
2686	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult)) \
2687	RTTestFailed(g_hTest, "#%03u%s: fcw=%#06x fsw=%#06x in=" a_szFmtIn "\n" \
2688	"%s -> fsw=%#06x %s\n" \
2689	"%s expected %#06x %s%s%s (%s)\n", \
2690	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, paTests[iTest].iInVal, \
2691	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result), \
2692	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].rdResult), \
2693	FswDiff(Res.FSW, paTests[iTest].fFswOut), \
2694	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult) ? " - val" : "", \
2695	FormatFcw(paTests[iTest].fFcw) ); \
2696	} \
2697	pfn = a_aSubTests[iFn].pfnNative; \
2698	} \
2699	} \
2700	}
2701
2702	TEST_FPU_LOAD_INT(64, int64_t, "%RI64", FPU_LD_I64_T, g_aFpuLdU64, FPU_I64_IN_TEST_T)
2703	TEST_FPU_LOAD_INT(32, int32_t, "%RI32", FPU_LD_I32_T, g_aFpuLdU32, FPU_I32_IN_TEST_T)
2704	TEST_FPU_LOAD_INT(16, int16_t, "%RI16", FPU_LD_I16_T, g_aFpuLdU16, FPU_I16_IN_TEST_T)
2705
2706	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2707	static void FpuLdIntGenerate(PRTSTREAM pOut, uint32_t cTests)
2708	{
2709	FpuLdI64Generate(pOut, cTests);
2710	FpuLdI32Generate(pOut, cTests);
2711	FpuLdI16Generate(pOut, cTests);
2712	}
2713	#endif
2714
2715	static void FpuLdIntTest(void)
2716	{
2717	FpuLdI64Test();
2718	FpuLdI32Test();
2719	FpuLdI16Test();
2720	}
2721
2722
2723	/*
2724	* Load binary coded decimal values from memory.
2725	*/
2726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPULDR80FROMD80,(PCX86FXSTATE, PIEMFPURESULT, PCRTPBCD80U));
2727	typedef FNIEMAIMPLFPULDR80FROMD80 *PFNIEMAIMPLFPULDR80FROMD80;
2728	TYPEDEF_SUBTEST_TYPE(FPU_LD_D80_T, FPU_D80_IN_TEST_T, PFNIEMAIMPLFPULDR80FROMD80);
2729
2730	static const FPU_LD_D80_T g_aFpuLdD80[] =
2731	{
2732	ENTRY(fld_r80_from_d80)
2733	};
2734
2735	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2736	static void FpuLdD80Generate(PRTSTREAM pOut, uint32_t cTests)
2737	{
2738	X86FXSTATE State;
2739	RT_ZERO(State);
2740	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuLdD80); iFn++)
2741	{
2742	GenerateArrayStart(pOut, g_aFpuLdD80[iFn].pszName, "FPU_D80_IN_TEST_T");
2743	for (uint32_t iTest = 0; iTest < cTests; iTest++)
2744	{
2745	State.FCW = RandFcw();
2746	State.FSW = RandFsw();
2747	RTPBCD80U InVal = RandD80Src(iTest);
2748
2749	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
2750	{
2751	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
2752	State.FCW = (State.FCW & ~X86_FCW_RC_MASK) \| (iRounding << X86_FCW_RC_SHIFT);
2753	g_aFpuLdD80[iFn].pfn(&State, &Res, &InVal);
2754	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u */\n",
2755	State.FCW, State.FSW, Res.FSW, GenFormatR80(&Res.r80Result), GenFormatD80(&InVal),
2756	iTest, iRounding);
2757	}
2758	}
2759	GenerateArrayEnd(pOut, g_aFpuLdD80[iFn].pszName);
2760	}
2761	}
2762	#endif
2763
2764	static void FpuLdD80Test(void)
2765	{
2766	X86FXSTATE State;
2767	RT_ZERO(State);
2768	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuLdD80); iFn++)
2769	{
2770	if (!SubTestAndCheckIfEnabled(g_aFpuLdD80[iFn].pszName))
2771	continue;
2772
2773	uint32_t const cTests = *g_aFpuLdD80[iFn].pcTests;
2774	FPU_D80_IN_TEST_T const * const paTests = g_aFpuLdD80[iFn].paTests;
2775	PFNIEMAIMPLFPULDR80FROMD80 pfn = g_aFpuLdD80[iFn].pfn;
2776	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuLdD80[iFn]);
2777	if (!cTests) RTTestSkipped(g_hTest, "no tests");
2778	for (uint32_t iVar = 0; iVar < cVars; iVar++)
2779	{
2780	for (uint32_t iTest = 0; iTest < cTests; iTest++)
2781	{
2782	RTPBCD80U const InVal = paTests[iTest].InVal;
2783	State.FCW = paTests[iTest].fFcw;
2784	State.FSW = paTests[iTest].fFswIn;
2785	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
2786	pfn(&State, &Res, &InVal);
2787	if ( Res.FSW != paTests[iTest].fFswOut
2788	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult))
2789	RTTestFailed(g_hTest, "#%03u%s: fcw=%#06x fsw=%#06x in=%s\n"
2790	"%s -> fsw=%#06x %s\n"
2791	"%s expected %#06x %s%s%s (%s)\n",
2792	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
2793	FormatD80(&paTests[iTest].InVal),
2794	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result),
2795	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].rdResult),
2796	FswDiff(Res.FSW, paTests[iTest].fFswOut),
2797	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].rdResult) ? " - val" : "",
2798	FormatFcw(paTests[iTest].fFcw) );
2799	}
2800	pfn = g_aFpuLdD80[iFn].pfnNative;
2801	}
2802	}
2803	}
2804
2805
2806	/*
2807	* Store values floating point values to memory.
2808	*/
2809	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2810	static const RTFLOAT80U g_aFpuStR32Specials[] =
2811	{
2812	RTFLOAT80U_INIT_C(0, 0xffffff8000000000, RTFLOAT80U_EXP_BIAS), /* near rounding with carry */
2813	RTFLOAT80U_INIT_C(1, 0xffffff8000000000, RTFLOAT80U_EXP_BIAS), /* near rounding with carry */
2814	RTFLOAT80U_INIT_C(0, 0xfffffe8000000000, RTFLOAT80U_EXP_BIAS), /* near rounding */
2815	RTFLOAT80U_INIT_C(1, 0xfffffe8000000000, RTFLOAT80U_EXP_BIAS), /* near rounding */
2816	};
2817	static const RTFLOAT80U g_aFpuStR64Specials[] =
2818	{
2819	RTFLOAT80U_INIT_C(0, 0xfffffffffffffc00, RTFLOAT80U_EXP_BIAS), /* near rounding with carry */
2820	RTFLOAT80U_INIT_C(1, 0xfffffffffffffc00, RTFLOAT80U_EXP_BIAS), /* near rounding with carry */
2821	RTFLOAT80U_INIT_C(0, 0xfffffffffffff400, RTFLOAT80U_EXP_BIAS), /* near rounding */
2822	RTFLOAT80U_INIT_C(1, 0xfffffffffffff400, RTFLOAT80U_EXP_BIAS), /* near rounding */
2823	RTFLOAT80U_INIT_C(0, 0xd0b9e6fdda887400, 687 + RTFLOAT80U_EXP_BIAS), /* random example for this */
2824	};
2825	static const RTFLOAT80U g_aFpuStR80Specials[] =
2826	{
2827	RTFLOAT80U_INIT_C(0, 0x8000000000000000, RTFLOAT80U_EXP_BIAS), /* placeholder */
2828	};
2829	# define GEN_FPU_STORE(a_cBits, a_rdType, a_aSubTests, a_TestType) \
2830	static void FpuStR ## a_cBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
2831	{ \
2832	uint32_t const cTotalTests = cTests + RT_ELEMENTS(g_aFpuStR ## a_cBits ## Specials); \
2833	X86FXSTATE State; \
2834	RT_ZERO(State); \
2835	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2836	{ \
2837	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
2838	for (uint32_t iTest = 0; iTest < cTotalTests; iTest++) \
2839	{ \
2840	uint16_t const fFcw = RandFcw(); \
2841	State.FSW = RandFsw(); \
2842	RTFLOAT80U const InVal = iTest < cTests ? RandR80Src(iTest, a_cBits) \
2843	: g_aFpuStR ## a_cBits ## Specials[iTest - cTests]; \
2844	\
2845	for (uint16_t iRounding = 0; iRounding < 4; iRounding++) \
2846	{ \
2847	/* PC doesn't influence these, so leave as is. */ \
2848	AssertCompile(X86_FCW_OM_BIT + 1 == X86_FCW_UM_BIT && X86_FCW_UM_BIT + 1 == X86_FCW_PM_BIT); \
2849	for (uint16_t iMask = 0; iMask < 16; iMask += 2 /1/) \
2850	{ \
2851	uint16_t uFswOut = 0; \
2852	a_rdType OutVal; \
2853	RT_ZERO(OutVal); \
2854	memset(&OutVal, 0xfe, sizeof(OutVal)); \
2855	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_OM \| X86_FCW_UM \| X86_FCW_PM)) \
2856	\| (iRounding << X86_FCW_RC_SHIFT); \
2857	/if (iMask & 1) State.FCW ^= X86_FCW_MASK_ALL;/ \
2858	State.FCW \|= (iMask >> 1) << X86_FCW_OM_BIT; \
2859	a_aSubTests[iFn].pfn(&State, &uFswOut, &OutVal, &InVal); \
2860	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u */\n", \
2861	State.FCW, State.FSW, uFswOut, GenFormatR80(&InVal), \
2862	GenFormatR ## a_cBits(&OutVal), iTest, iRounding, iMask); \
2863	} \
2864	} \
2865	} \
2866	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
2867	} \
2868	}
2869	#else
2870	# define GEN_FPU_STORE(a_cBits, a_rdType, a_aSubTests, a_TestType)
2871	#endif
2872
2873	#define TEST_FPU_STORE(a_cBits, a_rdType, a_SubTestType, a_aSubTests, a_TestType) \
2874	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOR ## a_cBits,(PCX86FXSTATE, uint16_t *, \
2875	PRTFLOAT ## a_cBits ## U, PCRTFLOAT80U)); \
2876	typedef FNIEMAIMPLFPUSTR80TOR ## a_cBits *PFNIEMAIMPLFPUSTR80TOR ## a_cBits; \
2877	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLFPUSTR80TOR ## a_cBits); \
2878	\
2879	static const a_SubTestType a_aSubTests[] = \
2880	{ \
2881	ENTRY(RT_CONCAT(fst_r80_to_r,a_cBits)) \
2882	}; \
2883	GEN_FPU_STORE(a_cBits, a_rdType, a_aSubTests, a_TestType) \
2884	\
2885	static void FpuStR ## a_cBits ## Test(void) \
2886	{ \
2887	X86FXSTATE State; \
2888	RT_ZERO(State); \
2889	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
2890	{ \
2891	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
2892	\
2893	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
2894	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
2895	PFNIEMAIMPLFPUSTR80TOR ## a_cBits pfn = a_aSubTests[iFn].pfn; \
2896	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
2897	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
2898	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
2899	{ \
2900	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
2901	{ \
2902	RTFLOAT80U const InVal = paTests[iTest].InVal; \
2903	uint16_t uFswOut = 0; \
2904	a_rdType OutVal; \
2905	RT_ZERO(OutVal); \
2906	memset(&OutVal, 0xfe, sizeof(OutVal)); \
2907	State.FCW = paTests[iTest].fFcw; \
2908	State.FSW = paTests[iTest].fFswIn; \
2909	pfn(&State, &uFswOut, &OutVal, &InVal); \
2910	if ( uFswOut != paTests[iTest].fFswOut \
2911	\|\| !RTFLOAT ## a_cBits ## U_ARE_IDENTICAL(&OutVal, &paTests[iTest].OutVal)) \
2912	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n" \
2913	"%s -> fsw=%#06x %s\n" \
2914	"%s expected %#06x %s%s%s (%s)\n", \
2915	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, \
2916	FormatR80(&paTests[iTest].InVal), \
2917	iVar ? " " : "", uFswOut, FormatR ## a_cBits(&OutVal), \
2918	iVar ? " " : "", paTests[iTest].fFswOut, FormatR ## a_cBits(&paTests[iTest].OutVal), \
2919	FswDiff(uFswOut, paTests[iTest].fFswOut), \
2920	!RTFLOAT ## a_cBits ## U_ARE_IDENTICAL(&OutVal, &paTests[iTest].OutVal) ? " - val" : "", \
2921	FormatFcw(paTests[iTest].fFcw) ); \
2922	} \
2923	pfn = a_aSubTests[iFn].pfnNative; \
2924	} \
2925	} \
2926	}
2927
2928	TEST_FPU_STORE(80, RTFLOAT80U, FPU_ST_R80_T, g_aFpuStR80, FPU_ST_R80_TEST_T)
2929	TEST_FPU_STORE(64, RTFLOAT64U, FPU_ST_R64_T, g_aFpuStR64, FPU_ST_R64_TEST_T)
2930	TEST_FPU_STORE(32, RTFLOAT32U, FPU_ST_R32_T, g_aFpuStR32, FPU_ST_R32_TEST_T)
2931
2932	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2933	static void FpuStMemGenerate(PRTSTREAM pOut, uint32_t cTests)
2934	{
2935	FpuStR80Generate(pOut, cTests);
2936	FpuStR64Generate(pOut, cTests);
2937	FpuStR32Generate(pOut, cTests);
2938	}
2939	#endif
2940
2941	static void FpuStMemTest(void)
2942	{
2943	FpuStR80Test();
2944	FpuStR64Test();
2945	FpuStR32Test();
2946	}
2947
2948
2949	/*
2950	* Store integer values to memory or register.
2951	*/
2952	TYPEDEF_SUBTEST_TYPE(FPU_ST_I16_T, FPU_ST_I16_TEST_T, PFNIEMAIMPLFPUSTR80TOI16);
2953	TYPEDEF_SUBTEST_TYPE(FPU_ST_I32_T, FPU_ST_I32_TEST_T, PFNIEMAIMPLFPUSTR80TOI32);
2954	TYPEDEF_SUBTEST_TYPE(FPU_ST_I64_T, FPU_ST_I64_TEST_T, PFNIEMAIMPLFPUSTR80TOI64);
2955
2956	static const FPU_ST_I16_T g_aFpuStI16[] =
2957	{
2958	ENTRY(fist_r80_to_i16),
2959	ENTRY_AMD( fistt_r80_to_i16, 0),
2960	ENTRY_INTEL(fistt_r80_to_i16, 0),
2961	};
2962	static const FPU_ST_I32_T g_aFpuStI32[] =
2963	{
2964	ENTRY(fist_r80_to_i32),
2965	ENTRY(fistt_r80_to_i32),
2966	};
2967	static const FPU_ST_I64_T g_aFpuStI64[] =
2968	{
2969	ENTRY(fist_r80_to_i64),
2970	ENTRY(fistt_r80_to_i64),
2971	};
2972
2973	#ifdef TSTIEMAIMPL_WITH_GENERATOR
2974	static const RTFLOAT80U g_aFpuStI16Specials[] = /* 16-bit variant borrows properties from the 32-bit one, thus all this stuff. */
2975	{
2976	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 13 + RTFLOAT80U_EXP_BIAS),
2977	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 13 + RTFLOAT80U_EXP_BIAS),
2978	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 14 + RTFLOAT80U_EXP_BIAS),
2979	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 14 + RTFLOAT80U_EXP_BIAS),
2980	RTFLOAT80U_INIT_C(0, 0x8000080000000000, 14 + RTFLOAT80U_EXP_BIAS),
2981	RTFLOAT80U_INIT_C(1, 0x8000080000000000, 14 + RTFLOAT80U_EXP_BIAS),
2982	RTFLOAT80U_INIT_C(0, 0x8000100000000000, 14 + RTFLOAT80U_EXP_BIAS),
2983	RTFLOAT80U_INIT_C(1, 0x8000100000000000, 14 + RTFLOAT80U_EXP_BIAS),
2984	RTFLOAT80U_INIT_C(0, 0x8000200000000000, 14 + RTFLOAT80U_EXP_BIAS),
2985	RTFLOAT80U_INIT_C(1, 0x8000200000000000, 14 + RTFLOAT80U_EXP_BIAS),
2986	RTFLOAT80U_INIT_C(0, 0x8000400000000000, 14 + RTFLOAT80U_EXP_BIAS),
2987	RTFLOAT80U_INIT_C(1, 0x8000400000000000, 14 + RTFLOAT80U_EXP_BIAS),
2988	RTFLOAT80U_INIT_C(0, 0x8000800000000000, 14 + RTFLOAT80U_EXP_BIAS),
2989	RTFLOAT80U_INIT_C(1, 0x8000800000000000, 14 + RTFLOAT80U_EXP_BIAS),
2990	RTFLOAT80U_INIT_C(1, 0x8000ffffffffffff, 14 + RTFLOAT80U_EXP_BIAS),
2991	RTFLOAT80U_INIT_C(0, 0x8001000000000000, 14 + RTFLOAT80U_EXP_BIAS),
2992	RTFLOAT80U_INIT_C(1, 0x8001000000000000, 14 + RTFLOAT80U_EXP_BIAS),
2993	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 14 + RTFLOAT80U_EXP_BIAS),
2994	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 14 + RTFLOAT80U_EXP_BIAS),
2995	RTFLOAT80U_INIT_C(0, 0xffff800000000000, 14 + RTFLOAT80U_EXP_BIAS),
2996	RTFLOAT80U_INIT_C(0, 0xffff000000000000, 14 + RTFLOAT80U_EXP_BIAS), /* overflow to min/nan */
2997	RTFLOAT80U_INIT_C(0, 0xfffe000000000000, 14 + RTFLOAT80U_EXP_BIAS),
2998	RTFLOAT80U_INIT_C(1, 0xffff800000000000, 14 + RTFLOAT80U_EXP_BIAS),
2999	RTFLOAT80U_INIT_C(1, 0xffff000000000000, 14 + RTFLOAT80U_EXP_BIAS), /* min */
3000	RTFLOAT80U_INIT_C(1, 0xfffe000000000000, 14 + RTFLOAT80U_EXP_BIAS),
3001	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 15 + RTFLOAT80U_EXP_BIAS),
3002	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 15 + RTFLOAT80U_EXP_BIAS),
3003	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 16 + RTFLOAT80U_EXP_BIAS),
3004	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 17 + RTFLOAT80U_EXP_BIAS),
3005	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 20 + RTFLOAT80U_EXP_BIAS),
3006	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 24 + RTFLOAT80U_EXP_BIAS),
3007	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 28 + RTFLOAT80U_EXP_BIAS),
3008	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 30 + RTFLOAT80U_EXP_BIAS),
3009	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 30 + RTFLOAT80U_EXP_BIAS),
3010	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 30 + RTFLOAT80U_EXP_BIAS),
3011	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 30 + RTFLOAT80U_EXP_BIAS),
3012	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3013	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3014	RTFLOAT80U_INIT_C(0, 0x8000000000000001, 31 + RTFLOAT80U_EXP_BIAS),
3015	RTFLOAT80U_INIT_C(1, 0x8000000000000001, 31 + RTFLOAT80U_EXP_BIAS),
3016	RTFLOAT80U_INIT_C(0, 0x8000ffffffffffff, 31 + RTFLOAT80U_EXP_BIAS),
3017	RTFLOAT80U_INIT_C(1, 0x8000ffffffffffff, 31 + RTFLOAT80U_EXP_BIAS),
3018	RTFLOAT80U_INIT_C(0, 0x8001000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3019	RTFLOAT80U_INIT_C(1, 0x8001000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3020	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 31 + RTFLOAT80U_EXP_BIAS),
3021	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 31 + RTFLOAT80U_EXP_BIAS),
3022	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 32 + RTFLOAT80U_EXP_BIAS),
3023	};
3024	static const RTFLOAT80U g_aFpuStI32Specials[] =
3025	{
3026	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 30 + RTFLOAT80U_EXP_BIAS),
3027	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 30 + RTFLOAT80U_EXP_BIAS),
3028	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 30 + RTFLOAT80U_EXP_BIAS), /* overflow to min/nan */
3029	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 30 + RTFLOAT80U_EXP_BIAS), /* min */
3030	RTFLOAT80U_INIT_C(0, 0xffffffff80000000, 30 + RTFLOAT80U_EXP_BIAS), /* overflow to min/nan */
3031	RTFLOAT80U_INIT_C(1, 0xffffffff80000000, 30 + RTFLOAT80U_EXP_BIAS), /* min */
3032	RTFLOAT80U_INIT_C(0, 0xffffffff00000000, 30 + RTFLOAT80U_EXP_BIAS), /* overflow to min/nan */
3033	RTFLOAT80U_INIT_C(1, 0xffffffff00000000, 30 + RTFLOAT80U_EXP_BIAS), /* min */
3034	RTFLOAT80U_INIT_C(0, 0xfffffffe00000000, 30 + RTFLOAT80U_EXP_BIAS),
3035	RTFLOAT80U_INIT_C(1, 0xfffffffe00000000, 30 + RTFLOAT80U_EXP_BIAS),
3036	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3037	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 31 + RTFLOAT80U_EXP_BIAS),
3038	RTFLOAT80U_INIT_C(0, 0x8000000000000001, 31 + RTFLOAT80U_EXP_BIAS),
3039	RTFLOAT80U_INIT_C(1, 0x8000000000000001, 31 + RTFLOAT80U_EXP_BIAS),
3040	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 31 + RTFLOAT80U_EXP_BIAS),
3041	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 31 + RTFLOAT80U_EXP_BIAS),
3042	};
3043	static const RTFLOAT80U g_aFpuStI64Specials[] =
3044	{
3045	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 61 + RTFLOAT80U_EXP_BIAS),
3046	RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, 61 + RTFLOAT80U_EXP_BIAS),
3047	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 62 + RTFLOAT80U_EXP_BIAS),
3048	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 62 + RTFLOAT80U_EXP_BIAS),
3049	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 62 + RTFLOAT80U_EXP_BIAS),
3050	RTFLOAT80U_INIT_C(1, 0xfffffffffffffff0, 62 + RTFLOAT80U_EXP_BIAS),
3051	RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, 62 + RTFLOAT80U_EXP_BIAS), /* overflow to min/nan */
3052	RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, 62 + RTFLOAT80U_EXP_BIAS), /* min */
3053	RTFLOAT80U_INIT_C(0, 0xfffffffffffffffe, 62 + RTFLOAT80U_EXP_BIAS),
3054	RTFLOAT80U_INIT_C(1, 0xfffffffffffffffe, 62 + RTFLOAT80U_EXP_BIAS),
3055	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 63 + RTFLOAT80U_EXP_BIAS),
3056	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 63 + RTFLOAT80U_EXP_BIAS),
3057	RTFLOAT80U_INIT_C(0, 0x8000000000000001, 63 + RTFLOAT80U_EXP_BIAS),
3058	RTFLOAT80U_INIT_C(1, 0x8000000000000001, 63 + RTFLOAT80U_EXP_BIAS),
3059	RTFLOAT80U_INIT_C(0, 0x8000000000000002, 63 + RTFLOAT80U_EXP_BIAS),
3060	RTFLOAT80U_INIT_C(1, 0x8000000000000002, 63 + RTFLOAT80U_EXP_BIAS),
3061	RTFLOAT80U_INIT_C(0, 0xfffffffffffffff0, 63 + RTFLOAT80U_EXP_BIAS),
3062	};
3063
3064	# define GEN_FPU_STORE_INT(a_cBits, a_iType, a_szFmt, a_aSubTests, a_TestType) \
3065	static void FpuStI ## a_cBits ## Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests) \
3066	{ \
3067	X86FXSTATE State; \
3068	RT_ZERO(State); \
3069	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3070	{ \
3071	PFNIEMAIMPLFPUSTR80TOI ## a_cBits const pfn = a_aSubTests[iFn].pfnNative \
3072	? a_aSubTests[iFn].pfnNative : a_aSubTests[iFn].pfn; \
3073	PRTSTREAM pOutFn = pOut; \
3074	if (a_aSubTests[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE) \
3075	{ \
3076	if (a_aSubTests[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour) \
3077	continue; \
3078	pOutFn = pOutCpu; \
3079	} \
3080	\
3081	GenerateArrayStart(pOutFn, a_aSubTests[iFn].pszName, #a_TestType); \
3082	uint32_t const cTotalTests = cTests + RT_ELEMENTS(g_aFpuStI ## a_cBits ## Specials); \
3083	for (uint32_t iTest = 0; iTest < cTotalTests; iTest++) \
3084	{ \
3085	uint16_t const fFcw = RandFcw(); \
3086	State.FSW = RandFsw(); \
3087	RTFLOAT80U const InVal = iTest < cTests ? RandR80Src(iTest, a_cBits, true) \
3088	: g_aFpuStI ## a_cBits ## Specials[iTest - cTests]; \
3089	\
3090	for (uint16_t iRounding = 0; iRounding < 4; iRounding++) \
3091	{ \
3092	/* PC doesn't influence these, so leave as is. */ \
3093	AssertCompile(X86_FCW_OM_BIT + 1 == X86_FCW_UM_BIT && X86_FCW_UM_BIT + 1 == X86_FCW_PM_BIT); \
3094	for (uint16_t iMask = 0; iMask < 16; iMask += 2 /1/) \
3095	{ \
3096	uint16_t uFswOut = 0; \
3097	a_iType iOutVal = ~(a_iType)2; \
3098	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_OM \| X86_FCW_UM \| X86_FCW_PM)) \
3099	\| (iRounding << X86_FCW_RC_SHIFT); \
3100	/if (iMask & 1) State.FCW ^= X86_FCW_MASK_ALL;/ \
3101	State.FCW \|= (iMask >> 1) << X86_FCW_OM_BIT; \
3102	pfn(&State, &uFswOut, &iOutVal, &InVal); \
3103	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u */\n", \
3104	State.FCW, State.FSW, uFswOut, GenFormatR80(&InVal), \
3105	GenFormatI ## a_cBits(iOutVal), iTest, iRounding, iMask); \
3106	} \
3107	} \
3108	} \
3109	GenerateArrayEnd(pOutFn, a_aSubTests[iFn].pszName); \
3110	} \
3111	}
3112	#else
3113	# define GEN_FPU_STORE_INT(a_cBits, a_iType, a_szFmt, a_aSubTests, a_TestType)
3114	#endif
3115
3116	#define TEST_FPU_STORE_INT(a_cBits, a_iType, a_szFmt, a_SubTestType, a_aSubTests, a_TestType) \
3117	GEN_FPU_STORE_INT(a_cBits, a_iType, a_szFmt, a_aSubTests, a_TestType) \
3118	\
3119	static void FpuStI ## a_cBits ## Test(void) \
3120	{ \
3121	X86FXSTATE State; \
3122	RT_ZERO(State); \
3123	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3124	{ \
3125	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
3126	\
3127	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
3128	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
3129	PFNIEMAIMPLFPUSTR80TOI ## a_cBits pfn = a_aSubTests[iFn].pfn; \
3130	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
3131	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
3132	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
3133	{ \
3134	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
3135	{ \
3136	RTFLOAT80U const InVal = paTests[iTest].InVal; \
3137	uint16_t uFswOut = 0; \
3138	a_iType iOutVal = ~(a_iType)2; \
3139	State.FCW = paTests[iTest].fFcw; \
3140	State.FSW = paTests[iTest].fFswIn; \
3141	pfn(&State, &uFswOut, &iOutVal, &InVal); \
3142	if ( uFswOut != paTests[iTest].fFswOut \
3143	\|\| iOutVal != paTests[iTest].iOutVal) \
3144	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n" \
3145	"%s -> fsw=%#06x " a_szFmt "\n" \
3146	"%s expected %#06x " a_szFmt "%s%s (%s)\n", \
3147	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, \
3148	FormatR80(&paTests[iTest].InVal), \
3149	iVar ? " " : "", uFswOut, iOutVal, \
3150	iVar ? " " : "", paTests[iTest].fFswOut, paTests[iTest].iOutVal, \
3151	FswDiff(uFswOut, paTests[iTest].fFswOut), \
3152	iOutVal != paTests[iTest].iOutVal ? " - val" : "", FormatFcw(paTests[iTest].fFcw) ); \
3153	} \
3154	pfn = a_aSubTests[iFn].pfnNative; \
3155	} \
3156	} \
3157	}
3158
3159	//fistt_r80_to_i16 diffs for AMD, of course :-)
3160
3161	TEST_FPU_STORE_INT(64, int64_t, "%RI64", FPU_ST_I64_T, g_aFpuStI64, FPU_ST_I64_TEST_T)
3162	TEST_FPU_STORE_INT(32, int32_t, "%RI32", FPU_ST_I32_T, g_aFpuStI32, FPU_ST_I32_TEST_T)
3163	TEST_FPU_STORE_INT(16, int16_t, "%RI16", FPU_ST_I16_T, g_aFpuStI16, FPU_ST_I16_TEST_T)
3164
3165	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3166	static void FpuStIntGenerate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests)
3167	{
3168	FpuStI64Generate(pOut, pOutCpu, cTests);
3169	FpuStI32Generate(pOut, pOutCpu, cTests);
3170	FpuStI16Generate(pOut, pOutCpu, cTests);
3171	}
3172	#endif
3173
3174	static void FpuStIntTest(void)
3175	{
3176	FpuStI64Test();
3177	FpuStI32Test();
3178	FpuStI16Test();
3179	}
3180
3181
3182	/*
3183	* Store as packed BCD value (memory).
3184	*/
3185	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOD80,(PCX86FXSTATE, uint16_t *, PRTPBCD80U, PCRTFLOAT80U));
3186	typedef FNIEMAIMPLFPUSTR80TOD80 *PFNIEMAIMPLFPUSTR80TOD80;
3187	TYPEDEF_SUBTEST_TYPE(FPU_ST_D80_T, FPU_ST_D80_TEST_T, PFNIEMAIMPLFPUSTR80TOD80);
3188
3189	static const FPU_ST_D80_T g_aFpuStD80[] =
3190	{
3191	ENTRY(fst_r80_to_d80),
3192	};
3193
3194	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3195	static void FpuStD80Generate(PRTSTREAM pOut, uint32_t cTests)
3196	{
3197	static RTFLOAT80U const s_aSpecials[] =
3198	{
3199	RTFLOAT80U_INIT_C(0, 0xde0b6b3a763fffe0, RTFLOAT80U_EXP_BIAS + 59), /* 1 below max */
3200	RTFLOAT80U_INIT_C(1, 0xde0b6b3a763fffe0, RTFLOAT80U_EXP_BIAS + 59), /* 1 above min */
3201	RTFLOAT80U_INIT_C(0, 0xde0b6b3a763ffff0, RTFLOAT80U_EXP_BIAS + 59), /* exact max */
3202	RTFLOAT80U_INIT_C(1, 0xde0b6b3a763ffff0, RTFLOAT80U_EXP_BIAS + 59), /* exact min */
3203	RTFLOAT80U_INIT_C(0, 0xde0b6b3a763fffff, RTFLOAT80U_EXP_BIAS + 59), /* max & all rounded off bits set */
3204	RTFLOAT80U_INIT_C(1, 0xde0b6b3a763fffff, RTFLOAT80U_EXP_BIAS + 59), /* min & all rounded off bits set */
3205	RTFLOAT80U_INIT_C(0, 0xde0b6b3a763ffff8, RTFLOAT80U_EXP_BIAS + 59), /* max & some rounded off bits set */
3206	RTFLOAT80U_INIT_C(1, 0xde0b6b3a763ffff8, RTFLOAT80U_EXP_BIAS + 59), /* min & some rounded off bits set */
3207	RTFLOAT80U_INIT_C(0, 0xde0b6b3a763ffff1, RTFLOAT80U_EXP_BIAS + 59), /* max & some other rounded off bits set */
3208	RTFLOAT80U_INIT_C(1, 0xde0b6b3a763ffff1, RTFLOAT80U_EXP_BIAS + 59), /* min & some other rounded off bits set */
3209	RTFLOAT80U_INIT_C(0, 0xde0b6b3a76400000, RTFLOAT80U_EXP_BIAS + 59), /* 1 above max */
3210	RTFLOAT80U_INIT_C(1, 0xde0b6b3a76400000, RTFLOAT80U_EXP_BIAS + 59), /* 1 below min */
3211	};
3212
3213	X86FXSTATE State;
3214	RT_ZERO(State);
3215	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuStD80); iFn++)
3216	{
3217	GenerateArrayStart(pOut, g_aFpuStD80[iFn].pszName, "FPU_ST_D80_TEST_T");
3218	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
3219	{
3220	uint16_t const fFcw = RandFcw();
3221	State.FSW = RandFsw();
3222	RTFLOAT80U const InVal = iTest < cTests ? RandR80Src(iTest, 59, true) : s_aSpecials[iTest - cTests];
3223
3224	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
3225	{
3226	/* PC doesn't influence these, so leave as is. */
3227	AssertCompile(X86_FCW_OM_BIT + 1 == X86_FCW_UM_BIT && X86_FCW_UM_BIT + 1 == X86_FCW_PM_BIT);
3228	for (uint16_t iMask = 0; iMask < 16; iMask += 2 /1/)
3229	{
3230	uint16_t uFswOut = 0;
3231	RTPBCD80U OutVal = RTPBCD80U_INIT_ZERO(0);
3232	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_OM \| X86_FCW_UM \| X86_FCW_PM))
3233	\| (iRounding << X86_FCW_RC_SHIFT);
3234	/if (iMask & 1) State.FCW ^= X86_FCW_MASK_ALL;/
3235	State.FCW \|= (iMask >> 1) << X86_FCW_OM_BIT;
3236	g_aFpuStD80[iFn].pfn(&State, &uFswOut, &OutVal, &InVal);
3237	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u */\n",
3238	State.FCW, State.FSW, uFswOut, GenFormatR80(&InVal),
3239	GenFormatD80(&OutVal), iTest, iRounding, iMask);
3240	}
3241	}
3242	}
3243	GenerateArrayEnd(pOut, g_aFpuStD80[iFn].pszName);
3244	}
3245	}
3246	#endif
3247
3248
3249	static void FpuStD80Test(void)
3250	{
3251	X86FXSTATE State;
3252	RT_ZERO(State);
3253	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuStD80); iFn++)
3254	{
3255	if (!SubTestAndCheckIfEnabled(g_aFpuStD80[iFn].pszName))
3256	continue;
3257
3258	uint32_t const cTests = *g_aFpuStD80[iFn].pcTests;
3259	FPU_ST_D80_TEST_T const * const paTests = g_aFpuStD80[iFn].paTests;
3260	PFNIEMAIMPLFPUSTR80TOD80 pfn = g_aFpuStD80[iFn].pfn;
3261	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuStD80[iFn]);
3262	if (!cTests) RTTestSkipped(g_hTest, "no tests");
3263	for (uint32_t iVar = 0; iVar < cVars; iVar++)
3264	{
3265	for (uint32_t iTest = 0; iTest < cTests; iTest++)
3266	{
3267	RTFLOAT80U const InVal = paTests[iTest].InVal;
3268	uint16_t uFswOut = 0;
3269	RTPBCD80U OutVal = RTPBCD80U_INIT_ZERO(0);
3270	State.FCW = paTests[iTest].fFcw;
3271	State.FSW = paTests[iTest].fFswIn;
3272	pfn(&State, &uFswOut, &OutVal, &InVal);
3273	if ( uFswOut != paTests[iTest].fFswOut
3274	\|\| !RTPBCD80U_ARE_IDENTICAL(&OutVal, &paTests[iTest].OutVal))
3275	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n"
3276	"%s -> fsw=%#06x %s\n"
3277	"%s expected %#06x %s%s%s (%s)\n",
3278	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
3279	FormatR80(&paTests[iTest].InVal),
3280	iVar ? " " : "", uFswOut, FormatD80(&OutVal),
3281	iVar ? " " : "", paTests[iTest].fFswOut, FormatD80(&paTests[iTest].OutVal),
3282	FswDiff(uFswOut, paTests[iTest].fFswOut),
3283	RTPBCD80U_ARE_IDENTICAL(&OutVal, &paTests[iTest].OutVal) ? " - val" : "",
3284	FormatFcw(paTests[iTest].fFcw) );
3285	}
3286	pfn = g_aFpuStD80[iFn].pfnNative;
3287	}
3288	}
3289	}
3290
3291
3292
3293	/*********************************************************************************************************************************
3294	* x87 FPU Binary Operations *
3295	*********************************************************************************************************************************/
3296
3297	/*
3298	* Binary FPU operations on two 80-bit floating point values.
3299	*/
3300	TYPEDEF_SUBTEST_TYPE(FPU_BINARY_R80_T, FPU_BINARY_R80_TEST_T, PFNIEMAIMPLFPUR80);
3301	enum { kFpuBinaryHint_fprem = 1, };
3302
3303	static const FPU_BINARY_R80_T g_aFpuBinaryR80[] =
3304	{
3305	ENTRY(fadd_r80_by_r80),
3306	ENTRY(fsub_r80_by_r80),
3307	ENTRY(fsubr_r80_by_r80),
3308	ENTRY(fmul_r80_by_r80),
3309	ENTRY(fdiv_r80_by_r80),
3310	ENTRY(fdivr_r80_by_r80),
3311	ENTRY_EX(fprem_r80_by_r80, kFpuBinaryHint_fprem),
3312	ENTRY_EX(fprem1_r80_by_r80, kFpuBinaryHint_fprem),
3313	ENTRY(fscale_r80_by_r80),
3314	ENTRY_AMD( fpatan_r80_by_r80, 0), // C1 and rounding differs on AMD
3315	ENTRY_INTEL(fpatan_r80_by_r80, 0), // C1 and rounding differs on AMD
3316	ENTRY_AMD( fyl2x_r80_by_r80, 0), // C1 and rounding differs on AMD
3317	ENTRY_INTEL(fyl2x_r80_by_r80, 0), // C1 and rounding differs on AMD
3318	ENTRY_AMD( fyl2xp1_r80_by_r80, 0), // C1 and rounding differs on AMD
3319	ENTRY_INTEL(fyl2xp1_r80_by_r80, 0), // C1 and rounding differs on AMD
3320	};
3321
3322	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3323	static void FpuBinaryR80Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests)
3324	{
3325	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
3326
3327	static struct { RTFLOAT80U Val1, Val2; } const s_aSpecials[] =
3328	{
3329	{ RTFLOAT80U_INIT_C(1, 0xdd762f07f2e80eef, 30142), /* causes weird overflows with DOWN and NEAR rounding. */
3330	RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1) },
3331	{ RTFLOAT80U_INIT_ZERO(0), /* causes weird overflows with UP and NEAR rounding when precision is lower than 64. */
3332	RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1) },
3333	{ RTFLOAT80U_INIT_ZERO(0), /* minus variant */
3334	RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1) },
3335	{ RTFLOAT80U_INIT_C(0, 0xcef238bb9a0afd86, 577 + RTFLOAT80U_EXP_BIAS), /* for fprem and fprem1, max sequence length */
3336	RTFLOAT80U_INIT_C(0, 0xf11684ec0beaad94, 1 + RTFLOAT80U_EXP_BIAS) },
3337	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, -13396 + RTFLOAT80U_EXP_BIAS), /* for fdiv. We missed PE. */
3338	RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, 16383 + RTFLOAT80U_EXP_BIAS) },
3339	{ RTFLOAT80U_INIT_C(0, 0x8000000000000000, 1 + RTFLOAT80U_EXP_BIAS), /* for fprem/fprem1 */
3340	RTFLOAT80U_INIT_C(0, 0xe000000000000000, 0 + RTFLOAT80U_EXP_BIAS) },
3341	{ RTFLOAT80U_INIT_C(0, 0x8000000000000000, 1 + RTFLOAT80U_EXP_BIAS), /* for fprem/fprem1 */
3342	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 0 + RTFLOAT80U_EXP_BIAS) },
3343	/* fscale: This may seriously increase the exponent, and it turns out overflow and underflow behaviour changes
3344	once RTFLOAT80U_EXP_BIAS_ADJUST is exceeded. */
3345	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^1 */
3346	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 0 + RTFLOAT80U_EXP_BIAS) },
3347	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^64 */
3348	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 6 + RTFLOAT80U_EXP_BIAS) },
3349	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^1024 */
3350	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 10 + RTFLOAT80U_EXP_BIAS) },
3351	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^4096 */
3352	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 12 + RTFLOAT80U_EXP_BIAS) },
3353	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^16384 */
3354	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 49150 */
3355	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^24576 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3356	RTFLOAT80U_INIT_C(0, 0xc000000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 57342 - within 10980XE range */
3357	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^24577 */
3358	RTFLOAT80U_INIT_C(0, 0xc002000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 57343 - outside 10980XE range, behaviour changes! */
3359	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^32768 - result is within range on 10980XE */
3360	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 15 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 65534 */
3361	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^65536 */
3362	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 16 + RTFLOAT80U_EXP_BIAS) },
3363	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^1048576 */
3364	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 20 + RTFLOAT80U_EXP_BIAS) },
3365	{ RTFLOAT80U_INIT_C(0, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^16777216 */
3366	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 24 + RTFLOAT80U_EXP_BIAS) },
3367	{ RTFLOAT80U_INIT_C(0, 0x8000000000000000, 1), /* for fscale: min * 2^-24576 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3368	RTFLOAT80U_INIT_C(1, 0xc000000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: -24575 - within 10980XE range */
3369	{ RTFLOAT80U_INIT_C(0, 0x8000000000000000, 1), /* for fscale: max * 2^-24577 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3370	RTFLOAT80U_INIT_C(1, 0xc002000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: -24576 - outside 10980XE range, behaviour changes! */
3371	/* fscale: Negative variants for the essentials of the above. */
3372	{ RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^24576 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3373	RTFLOAT80U_INIT_C(0, 0xc000000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 57342 - within 10980XE range */
3374	{ RTFLOAT80U_INIT_C(1, 0xffffffffffffffff, RTFLOAT80U_EXP_MAX - 1), /* for fscale: max * 2^24577 */
3375	RTFLOAT80U_INIT_C(0, 0xc002000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: 57343 - outside 10980XE range, behaviour changes! */
3376	{ RTFLOAT80U_INIT_C(1, 0x8000000000000000, 1), /* for fscale: min * 2^-24576 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3377	RTFLOAT80U_INIT_C(1, 0xc000000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: -57342 - within 10980XE range */
3378	{ RTFLOAT80U_INIT_C(1, 0x8000000000000000, 1), /* for fscale: max * 2^-24576 (RTFLOAT80U_EXP_BIAS_ADJUST) */
3379	RTFLOAT80U_INIT_C(1, 0xc002000000000000, 14 + RTFLOAT80U_EXP_BIAS) }, /* resulting exponent: -57343 - outside 10980XE range, behaviour changes! */
3380	/* fscale: Some fun with denormals and pseudo-denormals. */
3381	{ RTFLOAT80U_INIT_C(0, 0x0800000000000000, 0), /* for fscale: max * 2^-4 */
3382	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 2 + RTFLOAT80U_EXP_BIAS) },
3383	{ RTFLOAT80U_INIT_C(0, 0x0800000000000000, 0), /* for fscale: max * 2^+1 */
3384	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 0 + RTFLOAT80U_EXP_BIAS) },
3385	{ RTFLOAT80U_INIT_C(0, 0x0800000000000000, 0), RTFLOAT80U_INIT_ZERO(0) }, /* for fscale: max * 2^+0 */
3386	{ RTFLOAT80U_INIT_C(0, 0x0000000000000008, 0), /* for fscale: max * 2^-4 => underflow */
3387	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 2 + RTFLOAT80U_EXP_BIAS) },
3388	{ RTFLOAT80U_INIT_C(0, 0x8005000300020001, 0), RTFLOAT80U_INIT_ZERO(0) }, /* pseudo-normal number * 2^+0. */
3389	{ RTFLOAT80U_INIT_C(1, 0x8005000300020001, 0), RTFLOAT80U_INIT_ZERO(0) }, /* pseudo-normal number * 2^+0. */
3390	{ RTFLOAT80U_INIT_C(0, 0x8005000300020001, 0), /* pseudo-normal number * 2^-4 */
3391	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 2 + RTFLOAT80U_EXP_BIAS) },
3392	{ RTFLOAT80U_INIT_C(0, 0x8005000300020001, 0), /* pseudo-normal number * 2^+0 */
3393	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 0 + RTFLOAT80U_EXP_BIAS) },
3394	{ RTFLOAT80U_INIT_C(0, 0x8005000300020001, 0), /* pseudo-normal number * 2^+1 */
3395	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 1 + RTFLOAT80U_EXP_BIAS) },
3396	};
3397
3398	X86FXSTATE State;
3399	RT_ZERO(State);
3400	uint32_t cMinNormalPairs = (cTests - 144) / 4;
3401	uint32_t cMinTargetRangeInputs = cMinNormalPairs / 2;
3402	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuBinaryR80); iFn++)
3403	{
3404	PFNIEMAIMPLFPUR80 const pfn = g_aFpuBinaryR80[iFn].pfnNative ? g_aFpuBinaryR80[iFn].pfnNative : g_aFpuBinaryR80[iFn].pfn;
3405	PRTSTREAM pOutFn = pOut;
3406	if (g_aFpuBinaryR80[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE)
3407	{
3408	if (g_aFpuBinaryR80[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour)
3409	continue;
3410	pOutFn = pOutCpu;
3411	}
3412
3413	GenerateArrayStart(pOutFn, g_aFpuBinaryR80[iFn].pszName, "FPU_BINARY_R80_TEST_T");
3414	uint32_t iTestOutput = 0;
3415	uint32_t cNormalInputPairs = 0;
3416	uint32_t cTargetRangeInputs = 0;
3417	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
3418	{
3419	RTFLOAT80U InVal1 = iTest < cTests ? RandR80Src1(iTest) : s_aSpecials[iTest - cTests].Val1;
3420	RTFLOAT80U InVal2 = iTest < cTests ? RandR80Src2(iTest) : s_aSpecials[iTest - cTests].Val2;
3421	bool fTargetRange = false;
3422	if (RTFLOAT80U_IS_NORMAL(&InVal1) && RTFLOAT80U_IS_NORMAL(&InVal2))
3423	{
3424	cNormalInputPairs++;
3425	if ( g_aFpuBinaryR80[iFn].uExtra == kFpuBinaryHint_fprem
3426	&& (uint32_t)InVal1.s.uExponent - (uint32_t)InVal2.s.uExponent - (uint32_t)64 <= (uint32_t)512)
3427	cTargetRangeInputs += fTargetRange = true;
3428	else if (cTargetRangeInputs < cMinTargetRangeInputs && iTest < cTests)
3429	if (g_aFpuBinaryR80[iFn].uExtra == kFpuBinaryHint_fprem)
3430	{ /* The aim is two values with an exponent difference between 64 and 640 so we can do the whole sequence. */
3431	InVal2.s.uExponent = RTRandU32Ex(1, RTFLOAT80U_EXP_MAX - 66);
3432	InVal1.s.uExponent = RTRandU32Ex(InVal2.s.uExponent + 64, RT_MIN(InVal2.s.uExponent + 512, RTFLOAT80U_EXP_MAX - 1));
3433	cTargetRangeInputs += fTargetRange = true;
3434	}
3435	}
3436	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
3437	{
3438	iTest -= 1;
3439	continue;
3440	}
3441
3442	uint16_t const fFcwExtra = 0;
3443	uint16_t const fFcw = RandFcw();
3444	State.FSW = RandFsw();
3445
3446	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
3447	for (uint16_t iPrecision = 0; iPrecision < 4; iPrecision++)
3448	{
3449	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_PC_MASK \| X86_FCW_MASK_ALL))
3450	\| (iRounding << X86_FCW_RC_SHIFT)
3451	\| (iPrecision << X86_FCW_PC_SHIFT)
3452	\| X86_FCW_MASK_ALL;
3453	IEMFPURESULT ResM = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3454	pfn(&State, &ResM, &InVal1, &InVal2);
3455	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/m = #%u */\n",
3456	State.FCW \| fFcwExtra, State.FSW, ResM.FSW, GenFormatR80(&InVal1), GenFormatR80(&InVal2),
3457	GenFormatR80(&ResM.r80Result), iTest, iRounding, iPrecision, iTestOutput++);
3458
3459	State.FCW = State.FCW & ~X86_FCW_MASK_ALL;
3460	IEMFPURESULT ResU = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3461	pfn(&State, &ResU, &InVal1, &InVal2);
3462	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/u = #%u */\n",
3463	State.FCW \| fFcwExtra, State.FSW, ResU.FSW, GenFormatR80(&InVal1), GenFormatR80(&InVal2),
3464	GenFormatR80(&ResU.r80Result), iTest, iRounding, iPrecision, iTestOutput++);
3465
3466	uint16_t fXcpt = (ResM.FSW \| ResU.FSW) & X86_FSW_XCPT_MASK & ~X86_FSW_SF;
3467	if (fXcpt)
3468	{
3469	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
3470	IEMFPURESULT Res1 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3471	pfn(&State, &Res1, &InVal1, &InVal2);
3472	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/%#x = #%u */\n",
3473	State.FCW \| fFcwExtra, State.FSW, Res1.FSW, GenFormatR80(&InVal1), GenFormatR80(&InVal2),
3474	GenFormatR80(&Res1.r80Result), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
3475	if (((Res1.FSW & X86_FSW_XCPT_MASK) & fXcpt) != (Res1.FSW & X86_FSW_XCPT_MASK))
3476	{
3477	fXcpt \|= Res1.FSW & X86_FSW_XCPT_MASK;
3478	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
3479	IEMFPURESULT Res2 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3480	pfn(&State, &Res2, &InVal1, &InVal2);
3481	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/%#x[!] = #%u */\n",
3482	State.FCW \| fFcwExtra, State.FSW, Res2.FSW, GenFormatR80(&InVal1), GenFormatR80(&InVal2),
3483	GenFormatR80(&Res2.r80Result), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
3484	}
3485	if (!RT_IS_POWER_OF_TWO(fXcpt))
3486	for (uint16_t fUnmasked = 1; fUnmasked <= X86_FCW_PM; fUnmasked <<= 1)
3487	if (fUnmasked & fXcpt)
3488	{
3489	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| (fXcpt & ~fUnmasked);
3490	IEMFPURESULT Res3 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3491	pfn(&State, &Res3, &InVal1, &InVal2);
3492	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/u%#x = #%u */\n",
3493	State.FCW \| fFcwExtra, State.FSW, Res3.FSW, GenFormatR80(&InVal1), GenFormatR80(&InVal2),
3494	GenFormatR80(&Res3.r80Result), iTest, iRounding, iPrecision, fUnmasked, iTestOutput++);
3495	}
3496	}
3497
3498	/* If the values are in range and caused no exceptions, do the whole series of
3499	partial reminders till we get the non-partial one or run into an exception. */
3500	if (fTargetRange && fXcpt == 0 && g_aFpuBinaryR80[iFn].uExtra == kFpuBinaryHint_fprem)
3501	{
3502	IEMFPURESULT ResPrev = ResM;
3503	for (unsigned i = 0; i < 32 && (ResPrev.FSW & (X86_FSW_C2 \| X86_FSW_XCPT_MASK)) == X86_FSW_C2; i++)
3504	{
3505	State.FCW = State.FCW \| X86_FCW_MASK_ALL;
3506	State.FSW = ResPrev.FSW;
3507	IEMFPURESULT ResSeq = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3508	pfn(&State, &ResSeq, &ResPrev.r80Result, &InVal2);
3509	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/seq%u = #%u */\n",
3510	State.FCW \| fFcwExtra, State.FSW, ResSeq.FSW, GenFormatR80(&ResPrev.r80Result),
3511	GenFormatR80(&InVal2), GenFormatR80(&ResSeq.r80Result),
3512	iTest, iRounding, iPrecision, i + 1, iTestOutput++);
3513	ResPrev = ResSeq;
3514	}
3515	}
3516	}
3517	}
3518	GenerateArrayEnd(pOutFn, g_aFpuBinaryR80[iFn].pszName);
3519	}
3520	}
3521	#endif
3522
3523
3524	static void FpuBinaryR80Test(void)
3525	{
3526	X86FXSTATE State;
3527	RT_ZERO(State);
3528	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuBinaryR80); iFn++)
3529	{
3530	if (!SubTestAndCheckIfEnabled(g_aFpuBinaryR80[iFn].pszName))
3531	continue;
3532
3533	uint32_t const cTests = *g_aFpuBinaryR80[iFn].pcTests;
3534	FPU_BINARY_R80_TEST_T const * const paTests = g_aFpuBinaryR80[iFn].paTests;
3535	PFNIEMAIMPLFPUR80 pfn = g_aFpuBinaryR80[iFn].pfn;
3536	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuBinaryR80[iFn]);
3537	if (!cTests) RTTestSkipped(g_hTest, "no tests");
3538	for (uint32_t iVar = 0; iVar < cVars; iVar++)
3539	{
3540	for (uint32_t iTest = 0; iTest < cTests; iTest++)
3541	{
3542	RTFLOAT80U const InVal1 = paTests[iTest].InVal1;
3543	RTFLOAT80U const InVal2 = paTests[iTest].InVal2;
3544	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
3545	State.FCW = paTests[iTest].fFcw;
3546	State.FSW = paTests[iTest].fFswIn;
3547	pfn(&State, &Res, &InVal1, &InVal2);
3548	if ( Res.FSW != paTests[iTest].fFswOut
3549	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].OutVal))
3550	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in1=%s in2=%s\n"
3551	"%s -> fsw=%#06x %s\n"
3552	"%s expected %#06x %s%s%s (%s)\n",
3553	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
3554	FormatR80(&paTests[iTest].InVal1), FormatR80(&paTests[iTest].InVal2),
3555	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result),
3556	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].OutVal),
3557	FswDiff(Res.FSW, paTests[iTest].fFswOut),
3558	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].OutVal) ? " - val" : "",
3559	FormatFcw(paTests[iTest].fFcw) );
3560	}
3561	pfn = g_aFpuBinaryR80[iFn].pfnNative;
3562	}
3563	}
3564	}
3565
3566
3567	/*
3568	* Binary FPU operations on one 80-bit floating point value and one 64-bit or 32-bit one.
3569	*/
3570	#define int64_t_IS_NORMAL(a) 1
3571	#define int32_t_IS_NORMAL(a) 1
3572	#define int16_t_IS_NORMAL(a) 1
3573
3574	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3575	static struct { RTFLOAT80U Val1; RTFLOAT64U Val2; } const s_aFpuBinaryR64Specials[] =
3576	{
3577	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3578	RTFLOAT64U_INIT_C(0, 0xfeeeeddddcccc, RTFLOAT64U_EXP_BIAS) }, /* whatever */
3579	};
3580	static struct { RTFLOAT80U Val1; RTFLOAT32U Val2; } const s_aFpuBinaryR32Specials[] =
3581	{
3582	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3583	RTFLOAT32U_INIT_C(0, 0x7fffee, RTFLOAT32U_EXP_BIAS) }, /* whatever */
3584	};
3585	static struct { RTFLOAT80U Val1; int32_t Val2; } const s_aFpuBinaryI32Specials[] =
3586	{
3587	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), INT32_MAX }, /* whatever */
3588	};
3589	static struct { RTFLOAT80U Val1; int16_t Val2; } const s_aFpuBinaryI16Specials[] =
3590	{
3591	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), INT16_MAX }, /* whatever */
3592	};
3593
3594	# define GEN_FPU_BINARY_SMALL(a_fIntType, a_cBits, a_LoBits, a_UpBits, a_Type2, a_aSubTests, a_TestType) \
3595	static void FpuBinary ## a_UpBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
3596	{ \
3597	cTests = RT_MAX(160, cTests); /* there are 144 standard input variations for r80 by r80 */ \
3598	\
3599	X86FXSTATE State; \
3600	RT_ZERO(State); \
3601	uint32_t cMinNormalPairs = (cTests - 144) / 4; \
3602	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3603	{ \
3604	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
3605	uint32_t cNormalInputPairs = 0; \
3606	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aFpuBinary ## a_UpBits ## Specials); iTest += 1) \
3607	{ \
3608	RTFLOAT80U const InVal1 = iTest < cTests ? RandR80Src1(iTest, a_cBits, a_fIntType) \
3609	: s_aFpuBinary ## a_UpBits ## Specials[iTest - cTests].Val1; \
3610	a_Type2 const InVal2 = iTest < cTests ? Rand ## a_UpBits ## Src2(iTest) \
3611	: s_aFpuBinary ## a_UpBits ## Specials[iTest - cTests].Val2; \
3612	if (RTFLOAT80U_IS_NORMAL(&InVal1) && a_Type2 ## _IS_NORMAL(&InVal2)) \
3613	cNormalInputPairs++; \
3614	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests) \
3615	{ \
3616	iTest -= 1; \
3617	continue; \
3618	} \
3619	\
3620	uint16_t const fFcw = RandFcw(); \
3621	State.FSW = RandFsw(); \
3622	\
3623	for (uint16_t iRounding = 0; iRounding < 4; iRounding++) \
3624	{ \
3625	for (uint16_t iPrecision = 0; iPrecision < 4; iPrecision++) \
3626	{ \
3627	for (uint16_t iMask = 0; iMask <= X86_FCW_MASK_ALL; iMask += X86_FCW_MASK_ALL) \
3628	{ \
3629	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_PC_MASK \| X86_FCW_MASK_ALL)) \
3630	\| (iRounding << X86_FCW_RC_SHIFT) \
3631	\| (iPrecision << X86_FCW_PC_SHIFT) \
3632	\| iMask; \
3633	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
3634	a_aSubTests[iFn].pfn(&State, &Res, &InVal1, &InVal2); \
3635	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/%c */\n", \
3636	State.FCW, State.FSW, Res.FSW, GenFormatR80(&InVal1), GenFormat ## a_UpBits(&InVal2), \
3637	GenFormatR80(&Res.r80Result), iTest, iRounding, iPrecision, iMask ? 'c' : 'u'); \
3638	} \
3639	} \
3640	} \
3641	} \
3642	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
3643	} \
3644	}
3645	#else
3646	# define GEN_FPU_BINARY_SMALL(a_fIntType, a_cBits, a_LoBits, a_UpBits, a_Type2, a_aSubTests, a_TestType)
3647	#endif
3648
3649	#define TEST_FPU_BINARY_SMALL(a_fIntType, a_cBits, a_LoBits, a_UpBits, a_I, a_Type2, a_SubTestType, a_aSubTests, a_TestType) \
3650	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLFPU ## a_UpBits); \
3651	\
3652	static const a_SubTestType a_aSubTests[] = \
3653	{ \
3654	ENTRY(RT_CONCAT4(f, a_I, add_r80_by_, a_LoBits)), \
3655	ENTRY(RT_CONCAT4(f, a_I, mul_r80_by_, a_LoBits)), \
3656	ENTRY(RT_CONCAT4(f, a_I, sub_r80_by_, a_LoBits)), \
3657	ENTRY(RT_CONCAT4(f, a_I, subr_r80_by_, a_LoBits)), \
3658	ENTRY(RT_CONCAT4(f, a_I, div_r80_by_, a_LoBits)), \
3659	ENTRY(RT_CONCAT4(f, a_I, divr_r80_by_, a_LoBits)), \
3660	}; \
3661	\
3662	GEN_FPU_BINARY_SMALL(a_fIntType, a_cBits, a_LoBits, a_UpBits, a_Type2, a_aSubTests, a_TestType) \
3663	\
3664	static void FpuBinary ## a_UpBits ## Test(void) \
3665	{ \
3666	X86FXSTATE State; \
3667	RT_ZERO(State); \
3668	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3669	{ \
3670	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
3671	\
3672	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
3673	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
3674	PFNIEMAIMPLFPU ## a_UpBits pfn = a_aSubTests[iFn].pfn; \
3675	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
3676	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
3677	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
3678	{ \
3679	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
3680	{ \
3681	RTFLOAT80U const InVal1 = paTests[iTest].InVal1; \
3682	a_Type2 const InVal2 = paTests[iTest].InVal2; \
3683	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 }; \
3684	State.FCW = paTests[iTest].fFcw; \
3685	State.FSW = paTests[iTest].fFswIn; \
3686	pfn(&State, &Res, &InVal1, &InVal2); \
3687	if ( Res.FSW != paTests[iTest].fFswOut \
3688	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].OutVal)) \
3689	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in1=%s in2=%s\n" \
3690	"%s -> fsw=%#06x %s\n" \
3691	"%s expected %#06x %s%s%s (%s)\n", \
3692	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, \
3693	FormatR80(&paTests[iTest].InVal1), Format ## a_UpBits(&paTests[iTest].InVal2), \
3694	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result), \
3695	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].OutVal), \
3696	FswDiff(Res.FSW, paTests[iTest].fFswOut), \
3697	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].OutVal) ? " - val" : "", \
3698	FormatFcw(paTests[iTest].fFcw) ); \
3699	} \
3700	pfn = a_aSubTests[iFn].pfnNative; \
3701	} \
3702	} \
3703	}
3704
3705	TEST_FPU_BINARY_SMALL(0, 64, r64, R64, RT_NOTHING, RTFLOAT64U, FPU_BINARY_R64_T, g_aFpuBinaryR64, FPU_BINARY_R64_TEST_T)
3706	TEST_FPU_BINARY_SMALL(0, 32, r32, R32, RT_NOTHING, RTFLOAT32U, FPU_BINARY_R32_T, g_aFpuBinaryR32, FPU_BINARY_R32_TEST_T)
3707	TEST_FPU_BINARY_SMALL(1, 32, i32, I32, i, int32_t, FPU_BINARY_I32_T, g_aFpuBinaryI32, FPU_BINARY_I32_TEST_T)
3708	TEST_FPU_BINARY_SMALL(1, 16, i16, I16, i, int16_t, FPU_BINARY_I16_T, g_aFpuBinaryI16, FPU_BINARY_I16_TEST_T)
3709
3710
3711	/*
3712	* Binary operations on 80-, 64- and 32-bit floating point only affecting FSW.
3713	*/
3714	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3715	static struct { RTFLOAT80U Val1, Val2; } const s_aFpuBinaryFswR80Specials[] =
3716	{
3717	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3718	RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS) }, /* whatever */
3719	};
3720	static struct { RTFLOAT80U Val1; RTFLOAT64U Val2; } const s_aFpuBinaryFswR64Specials[] =
3721	{
3722	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3723	RTFLOAT64U_INIT_C(0, 0xfeeeeddddcccc, RTFLOAT64U_EXP_BIAS) }, /* whatever */
3724	};
3725	static struct { RTFLOAT80U Val1; RTFLOAT32U Val2; } const s_aFpuBinaryFswR32Specials[] =
3726	{
3727	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3728	RTFLOAT32U_INIT_C(0, 0x7fffee, RTFLOAT32U_EXP_BIAS) }, /* whatever */
3729	};
3730	static struct { RTFLOAT80U Val1; int32_t Val2; } const s_aFpuBinaryFswI32Specials[] =
3731	{
3732	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), INT32_MAX }, /* whatever */
3733	};
3734	static struct { RTFLOAT80U Val1; int16_t Val2; } const s_aFpuBinaryFswI16Specials[] =
3735	{
3736	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), INT16_MAX }, /* whatever */
3737	};
3738
3739	# define GEN_FPU_BINARY_FSW(a_fIntType, a_cBits, a_UpBits, a_Type2, a_aSubTests, a_TestType) \
3740	static void FpuBinaryFsw ## a_UpBits ## Generate(PRTSTREAM pOut, uint32_t cTests) \
3741	{ \
3742	cTests = RT_MAX(160, cTests); /* there are 144 standard input variations for r80 by r80 */ \
3743	\
3744	X86FXSTATE State; \
3745	RT_ZERO(State); \
3746	uint32_t cMinNormalPairs = (cTests - 144) / 4; \
3747	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3748	{ \
3749	GenerateArrayStart(pOut, a_aSubTests[iFn].pszName, #a_TestType); \
3750	uint32_t cNormalInputPairs = 0; \
3751	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aFpuBinaryFsw ## a_UpBits ## Specials); iTest += 1) \
3752	{ \
3753	RTFLOAT80U const InVal1 = iTest < cTests ? RandR80Src1(iTest, a_cBits, a_fIntType) \
3754	: s_aFpuBinaryFsw ## a_UpBits ## Specials[iTest - cTests].Val1; \
3755	a_Type2 const InVal2 = iTest < cTests ? Rand ## a_UpBits ## Src2(iTest) \
3756	: s_aFpuBinaryFsw ## a_UpBits ## Specials[iTest - cTests].Val2; \
3757	if (RTFLOAT80U_IS_NORMAL(&InVal1) && a_Type2 ## _IS_NORMAL(&InVal2)) \
3758	cNormalInputPairs++; \
3759	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests) \
3760	{ \
3761	iTest -= 1; \
3762	continue; \
3763	} \
3764	\
3765	uint16_t const fFcw = RandFcw(); \
3766	State.FSW = RandFsw(); \
3767	\
3768	/* Guess these aren't affected by precision or rounding, so just flip the exception mask. */ \
3769	for (uint16_t iMask = 0; iMask <= X86_FCW_MASK_ALL; iMask += X86_FCW_MASK_ALL) \
3770	{ \
3771	State.FCW = (fFcw & ~(X86_FCW_MASK_ALL)) \| iMask; \
3772	uint16_t fFswOut = 0; \
3773	a_aSubTests[iFn].pfn(&State, &fFswOut, &InVal1, &InVal2); \
3774	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%c */\n", \
3775	State.FCW, State.FSW, fFswOut, GenFormatR80(&InVal1), GenFormat ## a_UpBits(&InVal2), \
3776	iTest, iMask ? 'c' : 'u'); \
3777	} \
3778	} \
3779	GenerateArrayEnd(pOut, a_aSubTests[iFn].pszName); \
3780	} \
3781	}
3782	#else
3783	# define GEN_FPU_BINARY_FSW(a_fIntType, a_cBits, a_UpBits, a_Type2, a_aSubTests, a_TestType)
3784	#endif
3785
3786	#define TEST_FPU_BINARY_FSW(a_fIntType, a_cBits, a_UpBits, a_Type2, a_SubTestType, a_aSubTests, a_TestType, ...) \
3787	TYPEDEF_SUBTEST_TYPE(a_SubTestType, a_TestType, PFNIEMAIMPLFPU ## a_UpBits ## FSW); \
3788	\
3789	static const a_SubTestType a_aSubTests[] = \
3790	{ \
3791	__VA_ARGS__ \
3792	}; \
3793	\
3794	GEN_FPU_BINARY_FSW(a_fIntType, a_cBits, a_UpBits, a_Type2, a_aSubTests, a_TestType) \
3795	\
3796	static void FpuBinaryFsw ## a_UpBits ## Test(void) \
3797	{ \
3798	X86FXSTATE State; \
3799	RT_ZERO(State); \
3800	for (size_t iFn = 0; iFn < RT_ELEMENTS(a_aSubTests); iFn++) \
3801	{ \
3802	if (!SubTestAndCheckIfEnabled(a_aSubTests[iFn].pszName)) continue; \
3803	\
3804	uint32_t const cTests = *a_aSubTests[iFn].pcTests; \
3805	a_TestType const * const paTests = a_aSubTests[iFn].paTests; \
3806	PFNIEMAIMPLFPU ## a_UpBits ## FSW pfn = a_aSubTests[iFn].pfn; \
3807	uint32_t const cVars = COUNT_VARIATIONS(a_aSubTests[iFn]); \
3808	if (!cTests) RTTestSkipped(g_hTest, "no tests"); \
3809	for (uint32_t iVar = 0; iVar < cVars; iVar++) \
3810	{ \
3811	for (uint32_t iTest = 0; iTest < cTests; iTest++) \
3812	{ \
3813	uint16_t fFswOut = 0; \
3814	RTFLOAT80U const InVal1 = paTests[iTest].InVal1; \
3815	a_Type2 const InVal2 = paTests[iTest].InVal2; \
3816	State.FCW = paTests[iTest].fFcw; \
3817	State.FSW = paTests[iTest].fFswIn; \
3818	pfn(&State, &fFswOut, &InVal1, &InVal2); \
3819	if (fFswOut != paTests[iTest].fFswOut) \
3820	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in1=%s in2=%s\n" \
3821	"%s -> fsw=%#06x\n" \
3822	"%s expected %#06x %s (%s)\n", \
3823	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn, \
3824	FormatR80(&paTests[iTest].InVal1), Format ## a_UpBits(&paTests[iTest].InVal2), \
3825	iVar ? " " : "", fFswOut, \
3826	iVar ? " " : "", paTests[iTest].fFswOut, \
3827	FswDiff(fFswOut, paTests[iTest].fFswOut), FormatFcw(paTests[iTest].fFcw) ); \
3828	} \
3829	pfn = a_aSubTests[iFn].pfnNative; \
3830	} \
3831	} \
3832	}
3833
3834	TEST_FPU_BINARY_FSW(0, 80, R80, RTFLOAT80U, FPU_BINARY_FSW_R80_T, g_aFpuBinaryFswR80, FPU_BINARY_R80_TEST_T, ENTRY(fcom_r80_by_r80), ENTRY(fucom_r80_by_r80))
3835	TEST_FPU_BINARY_FSW(0, 64, R64, RTFLOAT64U, FPU_BINARY_FSW_R64_T, g_aFpuBinaryFswR64, FPU_BINARY_R64_TEST_T, ENTRY(fcom_r80_by_r64))
3836	TEST_FPU_BINARY_FSW(0, 32, R32, RTFLOAT32U, FPU_BINARY_FSW_R32_T, g_aFpuBinaryFswR32, FPU_BINARY_R32_TEST_T, ENTRY(fcom_r80_by_r32))
3837	TEST_FPU_BINARY_FSW(1, 32, I32, int32_t, FPU_BINARY_FSW_I32_T, g_aFpuBinaryFswI32, FPU_BINARY_I32_TEST_T, ENTRY(ficom_r80_by_i32))
3838	TEST_FPU_BINARY_FSW(1, 16, I16, int16_t, FPU_BINARY_FSW_I16_T, g_aFpuBinaryFswI16, FPU_BINARY_I16_TEST_T, ENTRY(ficom_r80_by_i16))
3839
3840
3841	/*
3842	* Binary operations on 80-bit floating point that effects only EFLAGS and possibly FSW.
3843	*/
3844	TYPEDEF_SUBTEST_TYPE(FPU_BINARY_EFL_R80_T, FPU_BINARY_EFL_R80_TEST_T, PFNIEMAIMPLFPUR80EFL);
3845
3846	static const FPU_BINARY_EFL_R80_T g_aFpuBinaryEflR80[] =
3847	{
3848	ENTRY(fcomi_r80_by_r80),
3849	ENTRY(fucomi_r80_by_r80),
3850	};
3851
3852	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3853	static struct { RTFLOAT80U Val1, Val2; } const s_aFpuBinaryEflR80Specials[] =
3854	{
3855	{ RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS),
3856	RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS) }, /* whatever */
3857	};
3858
3859	static void FpuBinaryEflR80Generate(PRTSTREAM pOut, uint32_t cTests)
3860	{
3861	cTests = RT_MAX(160, cTests); /* there are 144 standard input variations */
3862
3863	X86FXSTATE State;
3864	RT_ZERO(State);
3865	uint32_t cMinNormalPairs = (cTests - 144) / 4;
3866	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuBinaryEflR80); iFn++)
3867	{
3868	GenerateArrayStart(pOut, g_aFpuBinaryEflR80[iFn].pszName, "FPU_BINARY_EFL_R80_TEST_T");
3869	uint32_t cNormalInputPairs = 0;
3870	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aFpuBinaryEflR80Specials); iTest += 1)
3871	{
3872	RTFLOAT80U const InVal1 = iTest < cTests ? RandR80Src1(iTest) : s_aFpuBinaryEflR80Specials[iTest - cTests].Val1;
3873	RTFLOAT80U const InVal2 = iTest < cTests ? RandR80Src2(iTest) : s_aFpuBinaryEflR80Specials[iTest - cTests].Val2;
3874	if (RTFLOAT80U_IS_NORMAL(&InVal1) && RTFLOAT80U_IS_NORMAL(&InVal2))
3875	cNormalInputPairs++;
3876	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
3877	{
3878	iTest -= 1;
3879	continue;
3880	}
3881
3882	uint16_t const fFcw = RandFcw();
3883	State.FSW = RandFsw();
3884
3885	/* Guess these aren't affected by precision or rounding, so just flip the exception mask. */
3886	for (uint16_t iMask = 0; iMask <= X86_FCW_MASK_ALL; iMask += X86_FCW_MASK_ALL)
3887	{
3888	State.FCW = (fFcw & ~(X86_FCW_MASK_ALL)) \| iMask;
3889	uint16_t uFswOut = 0;
3890	uint32_t fEflOut = g_aFpuBinaryEflR80[iFn].pfn(&State, &uFswOut, &InVal1, &InVal2);
3891	RTStrmPrintf(pOut, " { %#06x, %#06x, %#06x, %s, %s, %#08x }, /* #%u/%c */\n",
3892	State.FCW, State.FSW, uFswOut, GenFormatR80(&InVal1), GenFormatR80(&InVal2), fEflOut,
3893	iTest, iMask ? 'c' : 'u');
3894	}
3895	}
3896	GenerateArrayEnd(pOut, g_aFpuBinaryEflR80[iFn].pszName);
3897	}
3898	}
3899	#endif /TSTIEMAIMPL_WITH_GENERATOR/
3900
3901	static void FpuBinaryEflR80Test(void)
3902	{
3903	X86FXSTATE State;
3904	RT_ZERO(State);
3905	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuBinaryEflR80); iFn++)
3906	{
3907	if (!SubTestAndCheckIfEnabled(g_aFpuBinaryEflR80[iFn].pszName))
3908	continue;
3909
3910	uint32_t const cTests = *g_aFpuBinaryEflR80[iFn].pcTests;
3911	FPU_BINARY_EFL_R80_TEST_T const * const paTests = g_aFpuBinaryEflR80[iFn].paTests;
3912	PFNIEMAIMPLFPUR80EFL pfn = g_aFpuBinaryEflR80[iFn].pfn;
3913	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuBinaryEflR80[iFn]);
3914	if (!cTests) RTTestSkipped(g_hTest, "no tests");
3915	for (uint32_t iVar = 0; iVar < cVars; iVar++)
3916	{
3917	for (uint32_t iTest = 0; iTest < cTests; iTest++)
3918	{
3919	RTFLOAT80U const InVal1 = paTests[iTest].InVal1;
3920	RTFLOAT80U const InVal2 = paTests[iTest].InVal2;
3921	State.FCW = paTests[iTest].fFcw;
3922	State.FSW = paTests[iTest].fFswIn;
3923	uint16_t uFswOut = 0;
3924	uint32_t fEflOut = pfn(&State, &uFswOut, &InVal1, &InVal2);
3925	if ( uFswOut != paTests[iTest].fFswOut
3926	\|\| fEflOut != paTests[iTest].fEflOut)
3927	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in1=%s in2=%s\n"
3928	"%s -> fsw=%#06x efl=%#08x\n"
3929	"%s expected %#06x %#08x %s%s (%s)\n",
3930	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
3931	FormatR80(&paTests[iTest].InVal1), FormatR80(&paTests[iTest].InVal2),
3932	iVar ? " " : "", uFswOut, fEflOut,
3933	iVar ? " " : "", paTests[iTest].fFswOut, paTests[iTest].fEflOut,
3934	FswDiff(uFswOut, paTests[iTest].fFswOut), EFlagsDiff(fEflOut, paTests[iTest].fEflOut),
3935	FormatFcw(paTests[iTest].fFcw));
3936	}
3937	pfn = g_aFpuBinaryEflR80[iFn].pfnNative;
3938	}
3939	}
3940	}
3941
3942
3943	/*********************************************************************************************************************************
3944	* x87 FPU Unary Operations *
3945	*********************************************************************************************************************************/
3946
3947	/*
3948	* Unary FPU operations on one 80-bit floating point value.
3949	*
3950	* Note! The FCW reserved bit 7 is used to indicate whether a test may produce
3951	* a rounding error or not.
3952	*/
3953	TYPEDEF_SUBTEST_TYPE(FPU_UNARY_R80_T, FPU_UNARY_R80_TEST_T, PFNIEMAIMPLFPUR80UNARY);
3954
3955	enum { kUnary_Accurate = 0, kUnary_Accurate_Trigonometry /probably not accurate, but need impl to know/, kUnary_Rounding_F2xm1 };
3956	static const FPU_UNARY_R80_T g_aFpuUnaryR80[] =
3957	{
3958	ENTRY_EX( fabs_r80, kUnary_Accurate),
3959	ENTRY_EX( fchs_r80, kUnary_Accurate),
3960	ENTRY_AMD_EX( f2xm1_r80, 0, kUnary_Accurate), // C1 differs for -1m0x3fb263cc2c331e15^-2654 (different ln2 constant?)
3961	ENTRY_INTEL_EX(f2xm1_r80, 0, kUnary_Rounding_F2xm1),
3962	ENTRY_EX( fsqrt_r80, kUnary_Accurate),
3963	ENTRY_EX( frndint_r80, kUnary_Accurate),
3964	ENTRY_AMD_EX( fsin_r80, 0, kUnary_Accurate_Trigonometry), // value & C1 differences for pseudo denormals and others (e.g. -1m0x2b1e5683cbca5725^-3485)
3965	ENTRY_INTEL_EX(fsin_r80, 0, kUnary_Accurate_Trigonometry),
3966	ENTRY_AMD_EX( fcos_r80, 0, kUnary_Accurate_Trigonometry), // value & C1 differences
3967	ENTRY_INTEL_EX(fcos_r80, 0, kUnary_Accurate_Trigonometry),
3968	};
3969
3970	#ifdef TSTIEMAIMPL_WITH_GENERATOR
3971
3972	static bool FpuUnaryR80MayHaveRoundingError(PCRTFLOAT80U pr80Val, int enmKind)
3973	{
3974	if ( enmKind == kUnary_Rounding_F2xm1
3975	&& RTFLOAT80U_IS_NORMAL(pr80Val)
3976	&& pr80Val->s.uExponent < RTFLOAT80U_EXP_BIAS
3977	&& pr80Val->s.uExponent >= RTFLOAT80U_EXP_BIAS - 69)
3978	return true;
3979	return false;
3980	}
3981
3982	static void FpuUnaryR80Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests)
3983	{
3984	static RTFLOAT80U const s_aSpecials[] =
3985	{
3986	RTFLOAT80U_INIT_C(0, 0x8000000000000000, RTFLOAT80U_EXP_BIAS - 1), /* 0.5 (for f2xm1) */
3987	RTFLOAT80U_INIT_C(1, 0x8000000000000000, RTFLOAT80U_EXP_BIAS - 1), /* -0.5 (for f2xm1) */
3988	RTFLOAT80U_INIT_C(0, 0x8000000000000000, RTFLOAT80U_EXP_BIAS), /* 1.0 (for f2xm1) */
3989	RTFLOAT80U_INIT_C(1, 0x8000000000000000, RTFLOAT80U_EXP_BIAS), /* -1.0 (for f2xm1) */
3990	RTFLOAT80U_INIT_C(0, 0x8000000000000000, 0), /* +1.0^-16382 */
3991	RTFLOAT80U_INIT_C(1, 0x8000000000000000, 0), /* -1.0^-16382 */
3992	RTFLOAT80U_INIT_C(0, 0xc000000000000000, 0), /* +1.1^-16382 */
3993	RTFLOAT80U_INIT_C(1, 0xc000000000000000, 0), /* -1.1^-16382 */
3994	RTFLOAT80U_INIT_C(0, 0xc000100000000000, 0), /* +1.1xxx1^-16382 */
3995	RTFLOAT80U_INIT_C(1, 0xc000100000000000, 0), /* -1.1xxx1^-16382 */
3996	};
3997	X86FXSTATE State;
3998	RT_ZERO(State);
3999	uint32_t cMinNormals = cTests / 4;
4000	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryR80); iFn++)
4001	{
4002	PFNIEMAIMPLFPUR80UNARY const pfn = g_aFpuUnaryR80[iFn].pfnNative ? g_aFpuUnaryR80[iFn].pfnNative : g_aFpuUnaryR80[iFn].pfn;
4003	PRTSTREAM pOutFn = pOut;
4004	if (g_aFpuUnaryR80[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE)
4005	{
4006	if (g_aFpuUnaryR80[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour)
4007	continue;
4008	pOutFn = pOutCpu;
4009	}
4010
4011	GenerateArrayStart(pOutFn, g_aFpuUnaryR80[iFn].pszName, "FPU_UNARY_R80_TEST_T");
4012	uint32_t iTestOutput = 0;
4013	uint32_t cNormalInputs = 0;
4014	uint32_t cTargetRangeInputs = 0;
4015	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4016	{
4017	RTFLOAT80U InVal = iTest < cTests ? RandR80Src(iTest) : s_aSpecials[iTest - cTests];
4018	if (RTFLOAT80U_IS_NORMAL(&InVal))
4019	{
4020	if (g_aFpuUnaryR80[iFn].uExtra == kUnary_Rounding_F2xm1)
4021	{
4022	unsigned uTargetExp = g_aFpuUnaryR80[iFn].uExtra == kUnary_Rounding_F2xm1
4023	? RTFLOAT80U_EXP_BIAS /* 2^0..2^-69 / : RTFLOAT80U_EXP_BIAS + 63 + 1 / 2^64..2^-64 */;
4024	unsigned cTargetExp = g_aFpuUnaryR80[iFn].uExtra == kUnary_Rounding_F2xm1 ? 69 : 63*2 + 2;
4025	if (InVal.s.uExponent <= uTargetExp && InVal.s.uExponent >= uTargetExp - cTargetExp)
4026	cTargetRangeInputs++;
4027	else if (cTargetRangeInputs < cMinNormals / 2 && iTest + cMinNormals / 2 >= cTests && iTest < cTests)
4028	{
4029	InVal.s.uExponent = RTRandU32Ex(uTargetExp - cTargetExp, uTargetExp);
4030	cTargetRangeInputs++;
4031	}
4032	}
4033	cNormalInputs++;
4034	}
4035	else if (cNormalInputs < cMinNormals && iTest + cMinNormals >= cTests && iTest < cTests)
4036	{
4037	iTest -= 1;
4038	continue;
4039	}
4040
4041	uint16_t const fFcwExtra = FpuUnaryR80MayHaveRoundingError(&InVal, g_aFpuUnaryR80[iFn].uExtra) ? 0x80 : 0;
4042	uint16_t const fFcw = RandFcw();
4043	State.FSW = RandFsw();
4044
4045	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4046	for (uint16_t iPrecision = 0; iPrecision < 4; iPrecision++)
4047	{
4048	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_PC_MASK \| X86_FCW_MASK_ALL))
4049	\| (iRounding << X86_FCW_RC_SHIFT)
4050	\| (iPrecision << X86_FCW_PC_SHIFT)
4051	\| X86_FCW_MASK_ALL;
4052	IEMFPURESULT ResM = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4053	pfn(&State, &ResM, &InVal);
4054	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u/m = #%u */\n",
4055	State.FCW \| fFcwExtra, State.FSW, ResM.FSW, GenFormatR80(&InVal),
4056	GenFormatR80(&ResM.r80Result), iTest, iRounding, iPrecision, iTestOutput++);
4057
4058	State.FCW = State.FCW & ~X86_FCW_MASK_ALL;
4059	IEMFPURESULT ResU = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4060	pfn(&State, &ResU, &InVal);
4061	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u/u = #%u */\n",
4062	State.FCW \| fFcwExtra, State.FSW, ResU.FSW, GenFormatR80(&InVal),
4063	GenFormatR80(&ResU.r80Result), iTest, iRounding, iPrecision, iTestOutput++);
4064
4065	uint16_t fXcpt = (ResM.FSW \| ResU.FSW) & X86_FSW_XCPT_MASK & ~X86_FSW_SF;
4066	if (fXcpt)
4067	{
4068	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
4069	IEMFPURESULT Res1 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4070	pfn(&State, &Res1, &InVal);
4071	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u/%#x = #%u */\n",
4072	State.FCW \| fFcwExtra, State.FSW, Res1.FSW, GenFormatR80(&InVal),
4073	GenFormatR80(&Res1.r80Result), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
4074	if (((Res1.FSW & X86_FSW_XCPT_MASK) & fXcpt) != (Res1.FSW & X86_FSW_XCPT_MASK))
4075	{
4076	fXcpt \|= Res1.FSW & X86_FSW_XCPT_MASK;
4077	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
4078	IEMFPURESULT Res2 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4079	pfn(&State, &Res2, &InVal);
4080	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u/%#x[!] = #%u */\n",
4081	State.FCW \| fFcwExtra, State.FSW, Res2.FSW, GenFormatR80(&InVal),
4082	GenFormatR80(&Res2.r80Result), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
4083	}
4084	if (!RT_IS_POWER_OF_TWO(fXcpt))
4085	for (uint16_t fUnmasked = 1; fUnmasked <= X86_FCW_PM; fUnmasked <<= 1)
4086	if (fUnmasked & fXcpt)
4087	{
4088	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| (fXcpt & ~fUnmasked);
4089	IEMFPURESULT Res3 = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4090	pfn(&State, &Res3, &InVal);
4091	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s }, /* #%u/%u/%u/u%#x = #%u */\n",
4092	State.FCW \| fFcwExtra, State.FSW, Res3.FSW, GenFormatR80(&InVal),
4093	GenFormatR80(&Res3.r80Result), iTest, iRounding, iPrecision, fUnmasked, iTestOutput++);
4094	}
4095	}
4096	}
4097	}
4098	GenerateArrayEnd(pOutFn, g_aFpuUnaryR80[iFn].pszName);
4099	}
4100	}
4101	#endif
4102
4103	static bool FpuIsEqualFcwMaybeIgnoreRoundErr(uint16_t fFcw1, uint16_t fFcw2, bool fRndErrOk, bool *pfRndErr)
4104	{
4105	if (fFcw1 == fFcw2)
4106	return true;
4107	if (fRndErrOk && (fFcw1 & ~X86_FSW_C1) == (fFcw2 & ~X86_FSW_C1))
4108	{
4109	*pfRndErr = true;
4110	return true;
4111	}
4112	return false;
4113	}
4114
4115	static bool FpuIsEqualR80MaybeIgnoreRoundErr(PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2, bool fRndErrOk, bool *pfRndErr)
4116	{
4117	if (RTFLOAT80U_ARE_IDENTICAL(pr80Val1, pr80Val2))
4118	return true;
4119	if ( fRndErrOk
4120	&& pr80Val1->s.fSign == pr80Val2->s.fSign)
4121	{
4122	if ( ( pr80Val1->s.uExponent == pr80Val2->s.uExponent
4123	&& ( pr80Val1->s.uMantissa > pr80Val2->s.uMantissa
4124	? pr80Val1->s.uMantissa - pr80Val2->s.uMantissa == 1
4125	: pr80Val2->s.uMantissa - pr80Val1->s.uMantissa == 1))
4126	\|\|
4127	( pr80Val1->s.uExponent + 1 == pr80Val2->s.uExponent
4128	&& pr80Val1->s.uMantissa == UINT64_MAX
4129	&& pr80Val2->s.uMantissa == RT_BIT_64(63))
4130	\|\|
4131	( pr80Val1->s.uExponent == pr80Val2->s.uExponent + 1
4132	&& pr80Val2->s.uMantissa == UINT64_MAX
4133	&& pr80Val1->s.uMantissa == RT_BIT_64(63)) )
4134	{
4135	*pfRndErr = true;
4136	return true;
4137	}
4138	}
4139	return false;
4140	}
4141
4142
4143	static void FpuUnaryR80Test(void)
4144	{
4145	X86FXSTATE State;
4146	RT_ZERO(State);
4147	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryR80); iFn++)
4148	{
4149	if (!SubTestAndCheckIfEnabled(g_aFpuUnaryR80[iFn].pszName))
4150	continue;
4151
4152	uint32_t const cTests = *g_aFpuUnaryR80[iFn].pcTests;
4153	FPU_UNARY_R80_TEST_T const * const paTests = g_aFpuUnaryR80[iFn].paTests;
4154	PFNIEMAIMPLFPUR80UNARY pfn = g_aFpuUnaryR80[iFn].pfn;
4155	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuUnaryR80[iFn]);
4156	uint32_t cRndErrs = 0;
4157	uint32_t cPossibleRndErrs = 0;
4158	if (!cTests) RTTestSkipped(g_hTest, "no tests");
4159	for (uint32_t iVar = 0; iVar < cVars; iVar++)
4160	{
4161	for (uint32_t iTest = 0; iTest < cTests; iTest++)
4162	{
4163	RTFLOAT80U const InVal = paTests[iTest].InVal;
4164	IEMFPURESULT Res = { RTFLOAT80U_INIT(0, 0, 0), 0 };
4165	bool const fRndErrOk = RT_BOOL(paTests[iTest].fFcw & 0x80);
4166	State.FCW = paTests[iTest].fFcw & ~(uint16_t)0x80;
4167	State.FSW = paTests[iTest].fFswIn;
4168	pfn(&State, &Res, &InVal);
4169	bool fRndErr = false;
4170	if ( !FpuIsEqualFcwMaybeIgnoreRoundErr(Res.FSW, paTests[iTest].fFswOut, fRndErrOk, &fRndErr)
4171	\|\| !FpuIsEqualR80MaybeIgnoreRoundErr(&Res.r80Result, &paTests[iTest].OutVal, fRndErrOk, &fRndErr))
4172	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n"
4173	"%s -> fsw=%#06x %s\n"
4174	"%s expected %#06x %s%s%s%s (%s)\n",
4175	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
4176	FormatR80(&paTests[iTest].InVal),
4177	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result),
4178	iVar ? " " : "", paTests[iTest].fFswOut, FormatR80(&paTests[iTest].OutVal),
4179	FswDiff(Res.FSW, paTests[iTest].fFswOut),
4180	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result, &paTests[iTest].OutVal) ? " - val" : "",
4181	fRndErrOk ? " - rounding errors ok" : "", FormatFcw(paTests[iTest].fFcw));
4182	cRndErrs += fRndErr;
4183	cPossibleRndErrs += fRndErrOk;
4184	}
4185	pfn = g_aFpuUnaryR80[iFn].pfnNative;
4186	}
4187	if (cPossibleRndErrs > 0)
4188	RTTestPrintf(g_hTest, RTTESTLVL_ALWAYS, "rounding errors: %u out of %u\n", cRndErrs, cPossibleRndErrs);
4189	}
4190	}
4191
4192
4193	/*
4194	* Unary FPU operations on one 80-bit floating point value, but only affects the FSW.
4195	*/
4196	TYPEDEF_SUBTEST_TYPE(FPU_UNARY_FSW_R80_T, FPU_UNARY_R80_TEST_T, PFNIEMAIMPLFPUR80UNARYFSW);
4197
4198	static const FPU_UNARY_FSW_R80_T g_aFpuUnaryFswR80[] =
4199	{
4200	ENTRY(ftst_r80),
4201	ENTRY_EX(fxam_r80, 1),
4202	};
4203
4204	#ifdef TSTIEMAIMPL_WITH_GENERATOR
4205	static void FpuUnaryFswR80Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests)
4206	{
4207	static RTFLOAT80U const s_aSpecials[] =
4208	{
4209	RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), /* whatever */
4210	};
4211
4212	X86FXSTATE State;
4213	RT_ZERO(State);
4214	uint32_t cMinNormals = cTests / 4;
4215	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryFswR80); iFn++)
4216	{
4217	bool const fIsFxam = g_aFpuUnaryFswR80[iFn].uExtra == 1;
4218	PFNIEMAIMPLFPUR80UNARYFSW const pfn = g_aFpuUnaryFswR80[iFn].pfnNative ? g_aFpuUnaryFswR80[iFn].pfnNative : g_aFpuUnaryFswR80[iFn].pfn;
4219	PRTSTREAM pOutFn = pOut;
4220	if (g_aFpuUnaryFswR80[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE)
4221	{
4222	if (g_aFpuUnaryFswR80[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour)
4223	continue;
4224	pOutFn = pOutCpu;
4225	}
4226	State.FTW = 0;
4227
4228	GenerateArrayStart(pOutFn, g_aFpuUnaryFswR80[iFn].pszName, "FPU_UNARY_R80_TEST_T");
4229	uint32_t cNormalInputs = 0;
4230	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4231	{
4232	RTFLOAT80U const InVal = iTest < cTests ? RandR80Src(iTest) : s_aSpecials[iTest - cTests];
4233	if (RTFLOAT80U_IS_NORMAL(&InVal))
4234	cNormalInputs++;
4235	else if (cNormalInputs < cMinNormals && iTest + cMinNormals >= cTests && iTest < cTests)
4236	{
4237	iTest -= 1;
4238	continue;
4239	}
4240
4241	uint16_t const fFcw = RandFcw();
4242	State.FSW = RandFsw();
4243	if (!fIsFxam)
4244	{
4245	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4246	{
4247	for (uint16_t iPrecision = 0; iPrecision < 4; iPrecision++)
4248	{
4249	for (uint16_t iMask = 0; iMask <= X86_FCW_MASK_ALL; iMask += X86_FCW_MASK_ALL)
4250	{
4251	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_PC_MASK \| X86_FCW_MASK_ALL))
4252	\| (iRounding << X86_FCW_RC_SHIFT)
4253	\| (iPrecision << X86_FCW_PC_SHIFT)
4254	\| iMask;
4255	uint16_t fFswOut = 0;
4256	pfn(&State, &fFswOut, &InVal);
4257	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s }, /* #%u/%u/%u/%c */\n",
4258	State.FCW, State.FSW, fFswOut, GenFormatR80(&InVal),
4259	iTest, iRounding, iPrecision, iMask ? 'c' : 'u');
4260	}
4261	}
4262	}
4263	}
4264	else
4265	{
4266	uint16_t fFswOut = 0;
4267	uint16_t const fEmpty = RTRandU32Ex(0, 3) == 3 ? 0x80 : 0; /* Using MBZ bit 7 in FCW to indicate empty tag value. */
4268	State.FTW = !fEmpty ? 1 << X86_FSW_TOP_GET(State.FSW) : 0;
4269	State.FCW = fFcw;
4270	pfn(&State, &fFswOut, &InVal);
4271	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s }, /* #%u%s */\n",
4272	fFcw \| fEmpty, State.FSW, fFswOut, GenFormatR80(&InVal), iTest, fEmpty ? "/empty" : "");
4273	}
4274	}
4275	GenerateArrayEnd(pOutFn, g_aFpuUnaryFswR80[iFn].pszName);
4276	}
4277	}
4278	#endif
4279
4280
4281	static void FpuUnaryFswR80Test(void)
4282	{
4283	X86FXSTATE State;
4284	RT_ZERO(State);
4285	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryFswR80); iFn++)
4286	{
4287	if (!SubTestAndCheckIfEnabled(g_aFpuUnaryFswR80[iFn].pszName))
4288	continue;
4289
4290	uint32_t const cTests = *g_aFpuUnaryFswR80[iFn].pcTests;
4291	FPU_UNARY_R80_TEST_T const * const paTests = g_aFpuUnaryFswR80[iFn].paTests;
4292	PFNIEMAIMPLFPUR80UNARYFSW pfn = g_aFpuUnaryFswR80[iFn].pfn;
4293	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuUnaryFswR80[iFn]);
4294	if (!cTests) RTTestSkipped(g_hTest, "no tests");
4295	for (uint32_t iVar = 0; iVar < cVars; iVar++)
4296	{
4297	for (uint32_t iTest = 0; iTest < cTests; iTest++)
4298	{
4299	RTFLOAT80U const InVal = paTests[iTest].InVal;
4300	uint16_t fFswOut = 0;
4301	State.FSW = paTests[iTest].fFswIn;
4302	State.FCW = paTests[iTest].fFcw & ~(uint16_t)0x80; /* see generator code */
4303	State.FTW = paTests[iTest].fFcw & 0x80 ? 0 : 1 << X86_FSW_TOP_GET(paTests[iTest].fFswIn);
4304	pfn(&State, &fFswOut, &InVal);
4305	if (fFswOut != paTests[iTest].fFswOut)
4306	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n"
4307	"%s -> fsw=%#06x\n"
4308	"%s expected %#06x %s (%s%s)\n",
4309	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
4310	FormatR80(&paTests[iTest].InVal),
4311	iVar ? " " : "", fFswOut,
4312	iVar ? " " : "", paTests[iTest].fFswOut,
4313	FswDiff(fFswOut, paTests[iTest].fFswOut), FormatFcw(paTests[iTest].fFcw),
4314	paTests[iTest].fFcw & 0x80 ? " empty" : "");
4315	}
4316	pfn = g_aFpuUnaryFswR80[iFn].pfnNative;
4317	}
4318	}
4319	}
4320
4321	/*
4322	* Unary FPU operations on one 80-bit floating point value, but with two outputs.
4323	*/
4324	TYPEDEF_SUBTEST_TYPE(FPU_UNARY_TWO_R80_T, FPU_UNARY_TWO_R80_TEST_T, PFNIEMAIMPLFPUR80UNARYTWO);
4325
4326	static const FPU_UNARY_TWO_R80_T g_aFpuUnaryTwoR80[] =
4327	{
4328	ENTRY(fxtract_r80_r80),
4329	ENTRY_AMD( fptan_r80_r80, 0), // rounding differences
4330	ENTRY_INTEL(fptan_r80_r80, 0),
4331	ENTRY_AMD( fsincos_r80_r80, 0), // C1 differences & value differences (e.g. -1m0x235cf2f580244a27^-1696)
4332	ENTRY_INTEL(fsincos_r80_r80, 0),
4333	};
4334
4335	#ifdef TSTIEMAIMPL_WITH_GENERATOR
4336	static void FpuUnaryTwoR80Generate(PRTSTREAM pOut, PRTSTREAM pOutCpu, uint32_t cTests)
4337	{
4338	static RTFLOAT80U const s_aSpecials[] =
4339	{
4340	RTFLOAT80U_INIT_C(0, 0xffffeeeeddddcccc, RTFLOAT80U_EXP_BIAS), /* whatever */
4341	};
4342
4343	X86FXSTATE State;
4344	RT_ZERO(State);
4345	uint32_t cMinNormals = cTests / 4;
4346	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryTwoR80); iFn++)
4347	{
4348	PFNIEMAIMPLFPUR80UNARYTWO const pfn = g_aFpuUnaryTwoR80[iFn].pfnNative ? g_aFpuUnaryTwoR80[iFn].pfnNative : g_aFpuUnaryTwoR80[iFn].pfn;
4349	PRTSTREAM pOutFn = pOut;
4350	if (g_aFpuUnaryTwoR80[iFn].idxCpuEflFlavour != IEMTARGETCPU_EFL_BEHAVIOR_NATIVE)
4351	{
4352	if (g_aFpuUnaryTwoR80[iFn].idxCpuEflFlavour != g_idxCpuEflFlavour)
4353	continue;
4354	pOutFn = pOutCpu;
4355	}
4356
4357	GenerateArrayStart(pOutFn, g_aFpuUnaryTwoR80[iFn].pszName, "FPU_UNARY_TWO_R80_TEST_T");
4358	uint32_t iTestOutput = 0;
4359	uint32_t cNormalInputs = 0;
4360	uint32_t cTargetRangeInputs = 0;
4361	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4362	{
4363	RTFLOAT80U InVal = iTest < cTests ? RandR80Src(iTest) : s_aSpecials[iTest - cTests];
4364	if (RTFLOAT80U_IS_NORMAL(&InVal))
4365	{
4366	if (iFn != 0)
4367	{
4368	unsigned uTargetExp = RTFLOAT80U_EXP_BIAS + 63 + 1 /* 2^64..2^-64 */;
4369	unsigned cTargetExp = g_aFpuUnaryR80[iFn].uExtra == kUnary_Rounding_F2xm1 ? 69 : 63*2 + 2;
4370	if (InVal.s.uExponent <= uTargetExp && InVal.s.uExponent >= uTargetExp - cTargetExp)
4371	cTargetRangeInputs++;
4372	else if (cTargetRangeInputs < cMinNormals / 2 && iTest + cMinNormals / 2 >= cTests && iTest < cTests)
4373	{
4374	InVal.s.uExponent = RTRandU32Ex(uTargetExp - cTargetExp, uTargetExp);
4375	cTargetRangeInputs++;
4376	}
4377	}
4378	cNormalInputs++;
4379	}
4380	else if (cNormalInputs < cMinNormals && iTest + cMinNormals >= cTests && iTest < cTests)
4381	{
4382	iTest -= 1;
4383	continue;
4384	}
4385
4386	uint16_t const fFcwExtra = 0; /* for rounding error indication */
4387	uint16_t const fFcw = RandFcw();
4388	State.FSW = RandFsw();
4389
4390	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4391	for (uint16_t iPrecision = 0; iPrecision < 4; iPrecision++)
4392	{
4393	State.FCW = (fFcw & ~(X86_FCW_RC_MASK \| X86_FCW_PC_MASK \| X86_FCW_MASK_ALL))
4394	\| (iRounding << X86_FCW_RC_SHIFT)
4395	\| (iPrecision << X86_FCW_PC_SHIFT)
4396	\| X86_FCW_MASK_ALL;
4397	IEMFPURESULTTWO ResM = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4398	pfn(&State, &ResM, &InVal);
4399	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/m = #%u */\n",
4400	State.FCW \| fFcwExtra, State.FSW, ResM.FSW, GenFormatR80(&InVal), GenFormatR80(&ResM.r80Result1),
4401	GenFormatR80(&ResM.r80Result2), iTest, iRounding, iPrecision, iTestOutput++);
4402
4403	State.FCW = State.FCW & ~X86_FCW_MASK_ALL;
4404	IEMFPURESULTTWO ResU = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4405	pfn(&State, &ResU, &InVal);
4406	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/u = #%u */\n",
4407	State.FCW \| fFcwExtra, State.FSW, ResU.FSW, GenFormatR80(&InVal), GenFormatR80(&ResU.r80Result1),
4408	GenFormatR80(&ResU.r80Result2), iTest, iRounding, iPrecision, iTestOutput++);
4409
4410	uint16_t fXcpt = (ResM.FSW \| ResU.FSW) & X86_FSW_XCPT_MASK & ~X86_FSW_SF;
4411	if (fXcpt)
4412	{
4413	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
4414	IEMFPURESULTTWO Res1 = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4415	pfn(&State, &Res1, &InVal);
4416	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/%#x = #%u */\n",
4417	State.FCW \| fFcwExtra, State.FSW, Res1.FSW, GenFormatR80(&InVal), GenFormatR80(&Res1.r80Result1),
4418	GenFormatR80(&Res1.r80Result2), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
4419	if (((Res1.FSW & X86_FSW_XCPT_MASK) & fXcpt) != (Res1.FSW & X86_FSW_XCPT_MASK))
4420	{
4421	fXcpt \|= Res1.FSW & X86_FSW_XCPT_MASK;
4422	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| fXcpt;
4423	IEMFPURESULTTWO Res2 = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4424	pfn(&State, &Res2, &InVal);
4425	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/%#x[!] = #%u */\n",
4426	State.FCW \| fFcwExtra, State.FSW, Res2.FSW, GenFormatR80(&InVal), GenFormatR80(&Res2.r80Result1),
4427	GenFormatR80(&Res2.r80Result2), iTest, iRounding, iPrecision, fXcpt, iTestOutput++);
4428	}
4429	if (!RT_IS_POWER_OF_TWO(fXcpt))
4430	for (uint16_t fUnmasked = 1; fUnmasked <= X86_FCW_PM; fUnmasked <<= 1)
4431	if (fUnmasked & fXcpt)
4432	{
4433	State.FCW = (State.FCW & ~X86_FCW_MASK_ALL) \| (fXcpt & ~fUnmasked);
4434	IEMFPURESULTTWO Res3 = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4435	pfn(&State, &Res3, &InVal);
4436	RTStrmPrintf(pOutFn, " { %#06x, %#06x, %#06x, %s, %s, %s }, /* #%u/%u/%u/u%#x = #%u */\n",
4437	State.FCW \| fFcwExtra, State.FSW, Res3.FSW, GenFormatR80(&InVal), GenFormatR80(&Res3.r80Result1),
4438	GenFormatR80(&Res3.r80Result2), iTest, iRounding, iPrecision, fUnmasked, iTestOutput++);
4439	}
4440	}
4441	}
4442	}
4443	GenerateArrayEnd(pOutFn, g_aFpuUnaryTwoR80[iFn].pszName);
4444	}
4445	}
4446	#endif
4447
4448
4449	static void FpuUnaryTwoR80Test(void)
4450	{
4451	X86FXSTATE State;
4452	RT_ZERO(State);
4453	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aFpuUnaryTwoR80); iFn++)
4454	{
4455	if (!SubTestAndCheckIfEnabled(g_aFpuUnaryTwoR80[iFn].pszName))
4456	continue;
4457
4458	uint32_t const cTests = *g_aFpuUnaryTwoR80[iFn].pcTests;
4459	FPU_UNARY_TWO_R80_TEST_T const * const paTests = g_aFpuUnaryTwoR80[iFn].paTests;
4460	PFNIEMAIMPLFPUR80UNARYTWO pfn = g_aFpuUnaryTwoR80[iFn].pfn;
4461	uint32_t const cVars = COUNT_VARIATIONS(g_aFpuUnaryTwoR80[iFn]);
4462	if (!cTests) RTTestSkipped(g_hTest, "no tests");
4463	for (uint32_t iVar = 0; iVar < cVars; iVar++)
4464	{
4465	for (uint32_t iTest = 0; iTest < cTests; iTest++)
4466	{
4467	IEMFPURESULTTWO Res = { RTFLOAT80U_INIT(0, 0, 0), 0, RTFLOAT80U_INIT(0, 0, 0) };
4468	RTFLOAT80U const InVal = paTests[iTest].InVal;
4469	State.FCW = paTests[iTest].fFcw;
4470	State.FSW = paTests[iTest].fFswIn;
4471	pfn(&State, &Res, &InVal);
4472	if ( Res.FSW != paTests[iTest].fFswOut
4473	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result1, &paTests[iTest].OutVal1)
4474	\|\| !RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result2, &paTests[iTest].OutVal2) )
4475	RTTestFailed(g_hTest, "#%04u%s: fcw=%#06x fsw=%#06x in=%s\n"
4476	"%s -> fsw=%#06x %s %s\n"
4477	"%s expected %#06x %s %s %s%s%s (%s)\n",
4478	iTest, iVar ? "/n" : "", paTests[iTest].fFcw, paTests[iTest].fFswIn,
4479	FormatR80(&paTests[iTest].InVal),
4480	iVar ? " " : "", Res.FSW, FormatR80(&Res.r80Result1), FormatR80(&Res.r80Result2),
4481	iVar ? " " : "", paTests[iTest].fFswOut,
4482	FormatR80(&paTests[iTest].OutVal1), FormatR80(&paTests[iTest].OutVal2),
4483	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result1, &paTests[iTest].OutVal1) ? " - val1" : "",
4484	!RTFLOAT80U_ARE_IDENTICAL(&Res.r80Result2, &paTests[iTest].OutVal2) ? " - val2" : "",
4485	FswDiff(Res.FSW, paTests[iTest].fFswOut), FormatFcw(paTests[iTest].fFcw) );
4486	}
4487	pfn = g_aFpuUnaryTwoR80[iFn].pfnNative;
4488	}
4489	}
4490	}
4491
4492
4493	/*********************************************************************************************************************************
4494	* SSE floating point Binary Operations *
4495	*********************************************************************************************************************************/
4496
4497	/*
4498	* Binary SSE operations on packed single precision floating point values.
4499	*/
4500	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R32_T, SSE_BINARY_TEST_T, PFNIEMAIMPLFPSSEF2U128);
4501
4502	static const SSE_BINARY_R32_T g_aSseBinaryR32[] =
4503	{
4504	ENTRY_BIN(addps_u128),
4505	ENTRY_BIN(mulps_u128),
4506	ENTRY_BIN(subps_u128),
4507	ENTRY_BIN(minps_u128),
4508	ENTRY_BIN(divps_u128),
4509	ENTRY_BIN(maxps_u128),
4510	ENTRY_BIN(haddps_u128),
4511	ENTRY_BIN(hsubps_u128),
4512	ENTRY_BIN(sqrtps_u128),
4513	ENTRY_BIN(addsubps_u128),
4514	ENTRY_BIN(cvtps2pd_u128),
4515	};
4516
4517	#ifdef TSTIEMAIMPL_WITH_GENERATOR
4518	static RTEXITCODE SseBinaryR32Generate(const char *pszDataFileFmt, uint32_t cTests)
4519	{
4520	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
4521
4522	static struct { RTFLOAT32U aVal1[4], aVal2[4]; } const s_aSpecials[] =
4523	{
4524	{ { RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), },
4525	{ RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1), RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1), RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1), RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1) } },
4526	/** @todo More specials. */
4527	};
4528
4529	X86FXSTATE State;
4530	RT_ZERO(State);
4531	uint32_t cMinNormalPairs = (cTests - 144) / 4;
4532	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++)
4533	{
4534	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseBinaryR32[iFn].pfnNative ? g_aSseBinaryR32[iFn].pfnNative : g_aSseBinaryR32[iFn].pfn;
4535
4536	PRTSTREAM pStrmOut = NULL;
4537	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR32[iFn].pszName);
4538	if (RT_FAILURE(rc))
4539	{
4540	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR32[iFn].pszName, rc);
4541	return RTEXITCODE_FAILURE;
4542	}
4543
4544	uint32_t cNormalInputPairs = 0;
4545	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4546	{
4547	SSE_BINARY_TEST_T TestData; RT_ZERO(TestData);
4548
4549	TestData.InVal1.ar32[0] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
4550	TestData.InVal1.ar32[1] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
4551	TestData.InVal1.ar32[2] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[2];
4552	TestData.InVal1.ar32[3] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[3];
4553
4554	TestData.InVal2.ar32[0] = iTest < cTests ? RandR32Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[0];
4555	TestData.InVal2.ar32[1] = iTest < cTests ? RandR32Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[1];
4556	TestData.InVal2.ar32[2] = iTest < cTests ? RandR32Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[2];
4557	TestData.InVal2.ar32[3] = iTest < cTests ? RandR32Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[3];
4558
4559	if ( RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[0]) && RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[0])
4560	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[1]) && RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[1])
4561	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[2]) && RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[2])
4562	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[3]) && RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[3]))
4563	cNormalInputPairs++;
4564	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
4565	{
4566	iTest -= 1;
4567	continue;
4568	}
4569
4570	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
4571	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4572	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
4573	for (uint8_t iFz = 0; iFz < 2; iFz++)
4574	{
4575	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
4576	\| (iRounding << X86_MXCSR_RC_SHIFT)
4577	\| (iDaz ? X86_MXCSR_DAZ : 0)
4578	\| (iFz ? X86_MXCSR_FZ : 0)
4579	\| X86_MXCSR_XCPT_MASK;
4580	IEMSSERESULT ResM; RT_ZERO(ResM);
4581	pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);
4582	TestData.fMxcsrIn = State.MXCSR;
4583	TestData.fMxcsrOut = ResM.MXCSR;
4584	TestData.OutVal = ResM.uResult;
4585	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4586
4587	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
4588	IEMSSERESULT ResU; RT_ZERO(ResU);
4589	pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);
4590	TestData.fMxcsrIn = State.MXCSR;
4591	TestData.fMxcsrOut = ResU.MXCSR;
4592	TestData.OutVal = ResU.uResult;
4593	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4594
4595	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
4596	if (fXcpt)
4597	{
4598	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
4599	IEMSSERESULT Res1; RT_ZERO(Res1);
4600	pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);
4601	TestData.fMxcsrIn = State.MXCSR;
4602	TestData.fMxcsrOut = Res1.MXCSR;
4603	TestData.OutVal = Res1.uResult;
4604	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4605
4606	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
4607	{
4608	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
4609	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
4610	IEMSSERESULT Res2; RT_ZERO(Res2);
4611	pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);
4612	TestData.fMxcsrIn = State.MXCSR;
4613	TestData.fMxcsrOut = Res2.MXCSR;
4614	TestData.OutVal = Res2.uResult;
4615	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4616	}
4617	if (!RT_IS_POWER_OF_TWO(fXcpt))
4618	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
4619	if (fUnmasked & fXcpt)
4620	{
4621	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
4622	IEMSSERESULT Res3; RT_ZERO(Res3);
4623	pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);
4624	TestData.fMxcsrIn = State.MXCSR;
4625	TestData.fMxcsrOut = Res3.MXCSR;
4626	TestData.OutVal = Res3.uResult;
4627	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4628	}
4629	}
4630	}
4631	}
4632	rc = RTStrmClose(pStrmOut);
4633	if (RT_FAILURE(rc))
4634	{
4635	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR32[iFn].pszName, rc);
4636	return RTEXITCODE_FAILURE;
4637	}
4638	}
4639
4640	return RTEXITCODE_SUCCESS;
4641	}
4642	#endif
4643
4644	static void SseBinaryR32Test(void)
4645	{
4646	X86FXSTATE State;
4647	RT_ZERO(State);
4648	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++)
4649	{
4650	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR32[iFn].pszName))
4651	continue;
4652
4653	uint32_t const cTests = *g_aSseBinaryR32[iFn].pcTests;
4654	SSE_BINARY_TEST_T const * const paTests = g_aSseBinaryR32[iFn].paTests;
4655	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseBinaryR32[iFn].pfn;
4656	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR32[iFn]);
4657	if (!cTests) RTTestSkipped(g_hTest, "no tests");
4658	for (uint32_t iVar = 0; iVar < cVars; iVar++)
4659	{
4660	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_TEST_T); iTest++)
4661	{
4662	IEMSSERESULT Res; RT_ZERO(Res);
4663
4664	State.MXCSR = paTests[iTest].fMxcsrIn;
4665	pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
4666	bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
4667	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
4668	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
4669	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]);
4670	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
4671	\|\| !fValsIdentical)
4672	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s'%s'%s'%s\n"
4673	"%s -> mxcsr=%#08x %s'%s'%s'%s\n"
4674	"%s expected %#08x %s'%s'%s'%s%s%s (%s)\n",
4675	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
4676	FormatR32(&paTests[iTest].InVal1.ar32[0]), FormatR32(&paTests[iTest].InVal1.ar32[1]),
4677	FormatR32(&paTests[iTest].InVal1.ar32[2]), FormatR32(&paTests[iTest].InVal1.ar32[3]),
4678	FormatR32(&paTests[iTest].InVal2.ar32[0]), FormatR32(&paTests[iTest].InVal2.ar32[1]),
4679	FormatR32(&paTests[iTest].InVal2.ar32[2]), FormatR32(&paTests[iTest].InVal2.ar32[3]),
4680	iVar ? " " : "", Res.MXCSR,
4681	FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
4682	FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
4683	iVar ? " " : "", paTests[iTest].fMxcsrOut,
4684	FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
4685	FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
4686	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
4687	!fValsIdentical ? " - val" : "",
4688	FormatMxcsr(paTests[iTest].fMxcsrIn) );
4689	}
4690	pfn = g_aSseBinaryR32[iFn].pfnNative;
4691	}
4692	}
4693	}
4694
4695
4696	/*
4697	* Binary SSE operations on packed single precision floating point values.
4698	*/
4699	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R64_T, SSE_BINARY_TEST_T, PFNIEMAIMPLFPSSEF2U128);
4700
4701	static const SSE_BINARY_R64_T g_aSseBinaryR64[] =
4702	{
4703	ENTRY_BIN(addpd_u128),
4704	ENTRY_BIN(mulpd_u128),
4705	ENTRY_BIN(subpd_u128),
4706	ENTRY_BIN(minpd_u128),
4707	ENTRY_BIN(divpd_u128),
4708	ENTRY_BIN(maxpd_u128),
4709	ENTRY_BIN(haddpd_u128),
4710	ENTRY_BIN(hsubpd_u128),
4711	ENTRY_BIN(sqrtpd_u128),
4712	ENTRY_BIN(addsubpd_u128),
4713	ENTRY_BIN(cvtpd2ps_u128),
4714	};
4715
4716	#ifdef TSTIEMAIMPL_WITH_GENERATOR
4717	static RTEXITCODE SseBinaryR64Generate(const char *pszDataFileFmt, uint32_t cTests)
4718	{
4719	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
4720
4721	static struct { RTFLOAT64U aVal1[2], aVal2[2]; } const s_aSpecials[] =
4722	{
4723	{ { RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) },
4724	{ RTFLOAT64U_INIT_C(0, 8388607, RTFLOAT64U_EXP_MAX - 1), RTFLOAT64U_INIT_C(0, 8388607, RTFLOAT64U_EXP_MAX - 1) } },
4725	/** @todo More specials. */
4726	};
4727
4728	X86FXSTATE State;
4729	RT_ZERO(State);
4730	uint32_t cMinNormalPairs = (cTests - 144) / 4;
4731	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++)
4732	{
4733	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseBinaryR64[iFn].pfnNative ? g_aSseBinaryR64[iFn].pfnNative : g_aSseBinaryR64[iFn].pfn;
4734
4735	PRTSTREAM pStrmOut = NULL;
4736	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR64[iFn].pszName);
4737	if (RT_FAILURE(rc))
4738	{
4739	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR64[iFn].pszName, rc);
4740	return RTEXITCODE_FAILURE;
4741	}
4742
4743	uint32_t cNormalInputPairs = 0;
4744	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4745	{
4746	SSE_BINARY_TEST_T TestData; RT_ZERO(TestData);
4747
4748	TestData.InVal1.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
4749	TestData.InVal1.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
4750	TestData.InVal2.ar64[0] = iTest < cTests ? RandR64Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[0];
4751	TestData.InVal2.ar64[1] = iTest < cTests ? RandR64Src2(iTest) : s_aSpecials[iTest - cTests].aVal2[0];
4752
4753	if ( RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[0]) && RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[1])
4754	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal2.ar64[0]) && RTFLOAT64U_IS_NORMAL(&TestData.InVal2.ar64[1]))
4755	cNormalInputPairs++;
4756	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
4757	{
4758	iTest -= 1;
4759	continue;
4760	}
4761
4762	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
4763	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4764	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
4765	for (uint8_t iFz = 0; iFz < 2; iFz++)
4766	{
4767	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
4768	\| (iRounding << X86_MXCSR_RC_SHIFT)
4769	\| (iDaz ? X86_MXCSR_DAZ : 0)
4770	\| (iFz ? X86_MXCSR_FZ : 0)
4771	\| X86_MXCSR_XCPT_MASK;
4772	IEMSSERESULT ResM; RT_ZERO(ResM);
4773	pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);
4774	TestData.fMxcsrIn = State.MXCSR;
4775	TestData.fMxcsrOut = ResM.MXCSR;
4776	TestData.OutVal = ResM.uResult;
4777	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4778
4779	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
4780	IEMSSERESULT ResU; RT_ZERO(ResU);
4781	pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);
4782	TestData.fMxcsrIn = State.MXCSR;
4783	TestData.fMxcsrOut = ResU.MXCSR;
4784	TestData.OutVal = ResU.uResult;
4785	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4786
4787	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
4788	if (fXcpt)
4789	{
4790	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
4791	IEMSSERESULT Res1; RT_ZERO(Res1);
4792	pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);
4793	TestData.fMxcsrIn = State.MXCSR;
4794	TestData.fMxcsrOut = Res1.MXCSR;
4795	TestData.OutVal = Res1.uResult;
4796	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4797
4798	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
4799	{
4800	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
4801	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
4802	IEMSSERESULT Res2; RT_ZERO(Res2);
4803	pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);
4804	TestData.fMxcsrIn = State.MXCSR;
4805	TestData.fMxcsrOut = Res2.MXCSR;
4806	TestData.OutVal = Res2.uResult;
4807	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4808	}
4809	if (!RT_IS_POWER_OF_TWO(fXcpt))
4810	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
4811	if (fUnmasked & fXcpt)
4812	{
4813	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
4814	IEMSSERESULT Res3; RT_ZERO(Res3);
4815	pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);
4816	TestData.fMxcsrIn = State.MXCSR;
4817	TestData.fMxcsrOut = Res3.MXCSR;
4818	TestData.OutVal = Res3.uResult;
4819	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4820	}
4821	}
4822	}
4823	}
4824	rc = RTStrmClose(pStrmOut);
4825	if (RT_FAILURE(rc))
4826	{
4827	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR64[iFn].pszName, rc);
4828	return RTEXITCODE_FAILURE;
4829	}
4830	}
4831
4832	return RTEXITCODE_SUCCESS;
4833	}
4834	#endif
4835
4836
4837	static void SseBinaryR64Test(void)
4838	{
4839	X86FXSTATE State;
4840	RT_ZERO(State);
4841	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++)
4842	{
4843	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR64[iFn].pszName))
4844	continue;
4845
4846	uint32_t const cTests = *g_aSseBinaryR64[iFn].pcTests;
4847	SSE_BINARY_TEST_T const * const paTests = g_aSseBinaryR64[iFn].paTests;
4848	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseBinaryR64[iFn].pfn;
4849	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR64[iFn]);
4850	if (!cTests) RTTestSkipped(g_hTest, "no tests");
4851	for (uint32_t iVar = 0; iVar < cVars; iVar++)
4852	{
4853	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_TEST_T); iTest++)
4854	{
4855	IEMSSERESULT Res; RT_ZERO(Res);
4856
4857	State.MXCSR = paTests[iTest].fMxcsrIn;
4858	pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
4859	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
4860	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
4861	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
4862	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s'%s\n"
4863	"%s -> mxcsr=%#08x %s'%s\n"
4864	"%s expected %#08x %s'%s%s%s (%s)\n",
4865	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
4866	FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]),
4867	FormatR64(&paTests[iTest].InVal2.ar64[0]), FormatR64(&paTests[iTest].InVal2.ar64[1]),
4868	iVar ? " " : "", Res.MXCSR,
4869	FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
4870	iVar ? " " : "", paTests[iTest].fMxcsrOut,
4871	FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
4872	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
4873	( !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
4874	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
4875	? " - val" : "",
4876	FormatMxcsr(paTests[iTest].fMxcsrIn) );
4877	}
4878	pfn = g_aSseBinaryR64[iFn].pfnNative;
4879	}
4880	}
4881	}
4882
4883
4884	/*
4885	* Binary SSE operations on packed single precision floating point values.
4886	*/
4887	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_U128_R32_T, SSE_BINARY_U128_R32_TEST_T, PFNIEMAIMPLFPSSEF2U128R32);
4888
4889	static const SSE_BINARY_U128_R32_T g_aSseBinaryU128R32[] =
4890	{
4891	ENTRY_BIN(addss_u128_r32),
4892	ENTRY_BIN(mulss_u128_r32),
4893	ENTRY_BIN(subss_u128_r32),
4894	ENTRY_BIN(minss_u128_r32),
4895	ENTRY_BIN(divss_u128_r32),
4896	ENTRY_BIN(maxss_u128_r32),
4897	ENTRY_BIN(cvtss2sd_u128_r32),
4898	ENTRY_BIN(sqrtss_u128_r32),
4899	};
4900
4901	#ifdef TSTIEMAIMPL_WITH_GENERATOR
4902	static RTEXITCODE SseBinaryU128R32Generate(const char *pszDataFileFmt, uint32_t cTests)
4903	{
4904	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
4905
4906	static struct { RTFLOAT32U aVal1[4], Val2; } const s_aSpecials[] =
4907	{
4908	{ { RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), }, RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1) },
4909	/** @todo More specials. */
4910	};
4911
4912	X86FXSTATE State;
4913	RT_ZERO(State);
4914	uint32_t cMinNormalPairs = (cTests - 144) / 4;
4915	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++)
4916	{
4917	PFNIEMAIMPLFPSSEF2U128R32 const pfn = g_aSseBinaryU128R32[iFn].pfnNative ? g_aSseBinaryU128R32[iFn].pfnNative : g_aSseBinaryU128R32[iFn].pfn;
4918
4919	PRTSTREAM pStrmOut = NULL;
4920	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryU128R32[iFn].pszName);
4921	if (RT_FAILURE(rc))
4922	{
4923	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryU128R32[iFn].pszName, rc);
4924	return RTEXITCODE_FAILURE;
4925	}
4926
4927	uint32_t cNormalInputPairs = 0;
4928	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
4929	{
4930	SSE_BINARY_U128_R32_TEST_T TestData; RT_ZERO(TestData);
4931
4932	TestData.InVal1.ar32[0] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
4933	TestData.InVal1.ar32[1] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
4934	TestData.InVal1.ar32[2] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[2];
4935	TestData.InVal1.ar32[3] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[3];
4936
4937	TestData.r32Val2 = iTest < cTests ? RandR32Src2(iTest) : s_aSpecials[iTest - cTests].Val2;
4938
4939	if ( RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[0])
4940	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[1])
4941	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[2])
4942	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[3])
4943	&& RTFLOAT32U_IS_NORMAL(&TestData.r32Val2))
4944	cNormalInputPairs++;
4945	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
4946	{
4947	iTest -= 1;
4948	continue;
4949	}
4950
4951	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
4952	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
4953	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
4954	for (uint8_t iFz = 0; iFz < 2; iFz++)
4955	{
4956	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
4957	\| (iRounding << X86_MXCSR_RC_SHIFT)
4958	\| (iDaz ? X86_MXCSR_DAZ : 0)
4959	\| (iFz ? X86_MXCSR_FZ : 0)
4960	\| X86_MXCSR_XCPT_MASK;
4961	IEMSSERESULT ResM; RT_ZERO(ResM);
4962	pfn(&State, &ResM, &TestData.InVal1, &TestData.r32Val2);
4963	TestData.fMxcsrIn = State.MXCSR;
4964	TestData.fMxcsrOut = ResM.MXCSR;
4965	TestData.OutVal = ResM.uResult;
4966	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4967
4968	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
4969	IEMSSERESULT ResU; RT_ZERO(ResU);
4970	pfn(&State, &ResU, &TestData.InVal1, &TestData.r32Val2);
4971	TestData.fMxcsrIn = State.MXCSR;
4972	TestData.fMxcsrOut = ResU.MXCSR;
4973	TestData.OutVal = ResU.uResult;
4974	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4975
4976	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
4977	if (fXcpt)
4978	{
4979	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
4980	IEMSSERESULT Res1; RT_ZERO(Res1);
4981	pfn(&State, &Res1, &TestData.InVal1, &TestData.r32Val2);
4982	TestData.fMxcsrIn = State.MXCSR;
4983	TestData.fMxcsrOut = Res1.MXCSR;
4984	TestData.OutVal = Res1.uResult;
4985	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4986
4987	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
4988	{
4989	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
4990	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
4991	IEMSSERESULT Res2; RT_ZERO(Res2);
4992	pfn(&State, &Res2, &TestData.InVal1, &TestData.r32Val2);
4993	TestData.fMxcsrIn = State.MXCSR;
4994	TestData.fMxcsrOut = Res2.MXCSR;
4995	TestData.OutVal = Res2.uResult;
4996	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
4997	}
4998	if (!RT_IS_POWER_OF_TWO(fXcpt))
4999	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5000	if (fUnmasked & fXcpt)
5001	{
5002	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5003	IEMSSERESULT Res3; RT_ZERO(Res3);
5004	pfn(&State, &Res3, &TestData.InVal1, &TestData.r32Val2);
5005	TestData.fMxcsrIn = State.MXCSR;
5006	TestData.fMxcsrOut = Res3.MXCSR;
5007	TestData.OutVal = Res3.uResult;
5008	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5009	}
5010	}
5011	}
5012	}
5013	rc = RTStrmClose(pStrmOut);
5014	if (RT_FAILURE(rc))
5015	{
5016	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryU128R32[iFn].pszName, rc);
5017	return RTEXITCODE_FAILURE;
5018	}
5019	}
5020
5021	return RTEXITCODE_SUCCESS;
5022	}
5023	#endif
5024
5025	static void SseBinaryU128R32Test(void)
5026	{
5027	X86FXSTATE State;
5028	RT_ZERO(State);
5029	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++)
5030	{
5031	if (!SubTestAndCheckIfEnabled(g_aSseBinaryU128R32[iFn].pszName))
5032	continue;
5033
5034	uint32_t const cTests = *g_aSseBinaryU128R32[iFn].pcTests;
5035	SSE_BINARY_U128_R32_TEST_T const * const paTests = g_aSseBinaryU128R32[iFn].paTests;
5036	PFNIEMAIMPLFPSSEF2U128R32 pfn = g_aSseBinaryU128R32[iFn].pfn;
5037	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryU128R32[iFn]);
5038	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5039	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5040	{
5041	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_TEST_T); iTest++)
5042	{
5043	IEMSSERESULT Res; RT_ZERO(Res);
5044
5045	State.MXCSR = paTests[iTest].fMxcsrIn;
5046	pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r32Val2);
5047	bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
5048	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
5049	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
5050	&& RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]);
5051	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
5052	\|\| !fValsIdentical)
5053	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s\n"
5054	"%s -> mxcsr=%#08x %s'%s'%s'%s\n"
5055	"%s expected %#08x %s'%s'%s'%s%s%s (%s)\n",
5056	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5057	FormatR32(&paTests[iTest].InVal1.ar32[0]), FormatR32(&paTests[iTest].InVal1.ar32[1]),
5058	FormatR32(&paTests[iTest].InVal1.ar32[2]), FormatR32(&paTests[iTest].InVal1.ar32[3]),
5059	FormatR32(&paTests[iTest].r32Val2),
5060	iVar ? " " : "", Res.MXCSR,
5061	FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
5062	FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
5063	iVar ? " " : "", paTests[iTest].fMxcsrOut,
5064	FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
5065	FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
5066	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
5067	!fValsIdentical ? " - val" : "",
5068	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5069	}
5070	}
5071	}
5072	}
5073
5074
5075	/*
5076	* Binary SSE operations on packed single precision floating point values (xxxsd xmm1, r/m64).
5077	*/
5078	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_U128_R64_T, SSE_BINARY_U128_R64_TEST_T, PFNIEMAIMPLFPSSEF2U128R64);
5079
5080	static const SSE_BINARY_U128_R64_T g_aSseBinaryU128R64[] =
5081	{
5082	ENTRY_BIN(addsd_u128_r64),
5083	ENTRY_BIN(mulsd_u128_r64),
5084	ENTRY_BIN(subsd_u128_r64),
5085	ENTRY_BIN(minsd_u128_r64),
5086	ENTRY_BIN(divsd_u128_r64),
5087	ENTRY_BIN(maxsd_u128_r64),
5088	ENTRY_BIN(cvtsd2ss_u128_r64),
5089	ENTRY_BIN(sqrtsd_u128_r64),
5090	};
5091
5092	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5093	static RTEXITCODE SseBinaryU128R64Generate(const char *pszDataFileFmt, uint32_t cTests)
5094	{
5095	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5096
5097	static struct { RTFLOAT64U aVal1[2], Val2; } const s_aSpecials[] =
5098	{
5099	{ { RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) }, RTFLOAT64U_INIT_C(0, 8388607, RTFLOAT64U_EXP_MAX - 1) },
5100	/** @todo More specials. */
5101	};
5102
5103	X86FXSTATE State;
5104	RT_ZERO(State);
5105	uint32_t cMinNormalPairs = (cTests - 144) / 4;
5106	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++)
5107	{
5108	PFNIEMAIMPLFPSSEF2U128R64 const pfn = g_aSseBinaryU128R64[iFn].pfnNative ? g_aSseBinaryU128R64[iFn].pfnNative : g_aSseBinaryU128R64[iFn].pfn;
5109
5110	PRTSTREAM pStrmOut = NULL;
5111	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryU128R64[iFn].pszName);
5112	if (RT_FAILURE(rc))
5113	{
5114	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryU128R64[iFn].pszName, rc);
5115	return RTEXITCODE_FAILURE;
5116	}
5117
5118	uint32_t cNormalInputPairs = 0;
5119	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5120	{
5121	SSE_BINARY_U128_R64_TEST_T TestData; RT_ZERO(TestData);
5122
5123	TestData.InVal1.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
5124	TestData.InVal1.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
5125	TestData.r64Val2 = iTest < cTests ? RandR64Src2(iTest) : s_aSpecials[iTest - cTests].Val2;
5126
5127	if ( RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[0]) && RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[1])
5128	&& RTFLOAT64U_IS_NORMAL(&TestData.r64Val2))
5129	cNormalInputPairs++;
5130	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
5131	{
5132	iTest -= 1;
5133	continue;
5134	}
5135
5136	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5137	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5138	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5139	for (uint8_t iFz = 0; iFz < 2; iFz++)
5140	{
5141	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5142	\| (iRounding << X86_MXCSR_RC_SHIFT)
5143	\| (iDaz ? X86_MXCSR_DAZ : 0)
5144	\| (iFz ? X86_MXCSR_FZ : 0)
5145	\| X86_MXCSR_XCPT_MASK;
5146	IEMSSERESULT ResM; RT_ZERO(ResM);
5147	pfn(&State, &ResM, &TestData.InVal1, &TestData.r64Val2);
5148	TestData.fMxcsrIn = State.MXCSR;
5149	TestData.fMxcsrOut = ResM.MXCSR;
5150	TestData.OutVal = ResM.uResult;
5151	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5152
5153	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5154	IEMSSERESULT ResU; RT_ZERO(ResU);
5155	pfn(&State, &ResU, &TestData.InVal1, &TestData.r64Val2);
5156	TestData.fMxcsrIn = State.MXCSR;
5157	TestData.fMxcsrOut = ResU.MXCSR;
5158	TestData.OutVal = ResU.uResult;
5159	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5160
5161	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
5162	if (fXcpt)
5163	{
5164	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
5165	IEMSSERESULT Res1; RT_ZERO(Res1);
5166	pfn(&State, &Res1, &TestData.InVal1, &TestData.r64Val2);
5167	TestData.fMxcsrIn = State.MXCSR;
5168	TestData.fMxcsrOut = Res1.MXCSR;
5169	TestData.OutVal = Res1.uResult;
5170	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5171
5172	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
5173	{
5174	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
5175	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
5176	IEMSSERESULT Res2; RT_ZERO(Res2);
5177	pfn(&State, &Res2, &TestData.InVal1, &TestData.r64Val2);
5178	TestData.fMxcsrIn = State.MXCSR;
5179	TestData.fMxcsrOut = Res2.MXCSR;
5180	TestData.OutVal = Res2.uResult;
5181	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5182	}
5183	if (!RT_IS_POWER_OF_TWO(fXcpt))
5184	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5185	if (fUnmasked & fXcpt)
5186	{
5187	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5188	IEMSSERESULT Res3; RT_ZERO(Res3);
5189	pfn(&State, &Res3, &TestData.InVal1, &TestData.r64Val2);
5190	TestData.fMxcsrIn = State.MXCSR;
5191	TestData.fMxcsrOut = Res3.MXCSR;
5192	TestData.OutVal = Res3.uResult;
5193	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5194	}
5195	}
5196	}
5197	}
5198	rc = RTStrmClose(pStrmOut);
5199	if (RT_FAILURE(rc))
5200	{
5201	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryU128R64[iFn].pszName, rc);
5202	return RTEXITCODE_FAILURE;
5203	}
5204	}
5205
5206	return RTEXITCODE_SUCCESS;
5207	}
5208	#endif
5209
5210
5211	static void SseBinaryU128R64Test(void)
5212	{
5213	X86FXSTATE State;
5214	RT_ZERO(State);
5215	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++)
5216	{
5217	if (!SubTestAndCheckIfEnabled(g_aSseBinaryU128R64[iFn].pszName))
5218	continue;
5219
5220	uint32_t const cTests = *g_aSseBinaryU128R64[iFn].pcTests;
5221	SSE_BINARY_U128_R64_TEST_T const * const paTests = g_aSseBinaryU128R64[iFn].paTests;
5222	PFNIEMAIMPLFPSSEF2U128R64 pfn = g_aSseBinaryU128R64[iFn].pfn;
5223	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryU128R64[iFn]);
5224	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5225	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5226	{
5227	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_U128_R64_TEST_T); iTest++)
5228	{
5229	IEMSSERESULT Res; RT_ZERO(Res);
5230
5231	State.MXCSR = paTests[iTest].fMxcsrIn;
5232	pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r64Val2);
5233	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
5234	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
5235	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
5236	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s\n"
5237	"%s -> mxcsr=%#08x %s'%s\n"
5238	"%s expected %#08x %s'%s%s%s (%s)\n",
5239	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5240	FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]),
5241	FormatR64(&paTests[iTest].r64Val2),
5242	iVar ? " " : "", Res.MXCSR,
5243	FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
5244	iVar ? " " : "", paTests[iTest].fMxcsrOut,
5245	FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
5246	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
5247	( !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
5248	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
5249	? " - val" : "",
5250	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5251	}
5252	}
5253	}
5254	}
5255
5256
5257	/*
5258	* SSE operations converting single double-precision floating point values to signed double-word integers (cvttsd2si and friends).
5259	*/
5260	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_I32_R64_T, SSE_BINARY_I32_R64_TEST_T, PFNIEMAIMPLSSEF2I32U64);
5261
5262	static const SSE_BINARY_I32_R64_T g_aSseBinaryI32R64[] =
5263	{
5264	ENTRY_BIN(cvttsd2si_i32_r64),
5265	ENTRY_BIN(cvtsd2si_i32_r64),
5266	};
5267
5268	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5269	static RTEXITCODE SseBinaryI32R64Generate(const char *pszDataFileFmt, uint32_t cTests)
5270	{
5271	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5272
5273	static struct { RTFLOAT64U Val; } const s_aSpecials[] =
5274	{
5275	{ RTFLOAT64U_INIT_C(0, 8388607, RTFLOAT64U_EXP_MAX - 1) },
5276	/** @todo More specials. */
5277	};
5278
5279	X86FXSTATE State;
5280	RT_ZERO(State);
5281	uint32_t cMinNormalPairs = (cTests - 144) / 4;
5282	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R64); iFn++)
5283	{
5284	PFNIEMAIMPLSSEF2I32U64 const pfn = g_aSseBinaryI32R64[iFn].pfnNative ? g_aSseBinaryI32R64[iFn].pfnNative : g_aSseBinaryI32R64[iFn].pfn;
5285
5286	PRTSTREAM pStrmOut = NULL;
5287	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryI32R64[iFn].pszName);
5288	if (RT_FAILURE(rc))
5289	{
5290	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryI32R64[iFn].pszName, rc);
5291	return RTEXITCODE_FAILURE;
5292	}
5293
5294	uint32_t cNormalInputPairs = 0;
5295	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5296	{
5297	SSE_BINARY_I32_R64_TEST_T TestData; RT_ZERO(TestData);
5298
5299	TestData.r64ValIn = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val;
5300
5301	if (RTFLOAT64U_IS_NORMAL(&TestData.r64ValIn))
5302	cNormalInputPairs++;
5303	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
5304	{
5305	iTest -= 1;
5306	continue;
5307	}
5308
5309	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5310	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5311	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5312	for (uint8_t iFz = 0; iFz < 2; iFz++)
5313	{
5314	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5315	\| (iRounding << X86_MXCSR_RC_SHIFT)
5316	\| (iDaz ? X86_MXCSR_DAZ : 0)
5317	\| (iFz ? X86_MXCSR_FZ : 0)
5318	\| X86_MXCSR_XCPT_MASK;
5319	uint32_t fMxcsrM; int32_t i32OutM;
5320	pfn(&State, &fMxcsrM, &i32OutM, &TestData.r64ValIn.u);
5321	TestData.fMxcsrIn = State.MXCSR;
5322	TestData.fMxcsrOut = fMxcsrM;
5323	TestData.i32ValOut = i32OutM;
5324	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5325
5326	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5327	uint32_t fMxcsrU; int32_t i32OutU;
5328	pfn(&State, &fMxcsrU, &i32OutU, &TestData.r64ValIn.u);
5329	TestData.fMxcsrIn = State.MXCSR;
5330	TestData.fMxcsrOut = fMxcsrU;
5331	TestData.i32ValOut = i32OutU;
5332	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5333
5334	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
5335	if (fXcpt)
5336	{
5337	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
5338	uint32_t fMxcsr1; int32_t i32Out1;
5339	pfn(&State, &fMxcsr1, &i32Out1, &TestData.r64ValIn.u);
5340	TestData.fMxcsrIn = State.MXCSR;
5341	TestData.fMxcsrOut = fMxcsr1;
5342	TestData.i32ValOut = i32Out1;
5343	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5344
5345	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
5346	{
5347	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
5348	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
5349	uint32_t fMxcsr2; int32_t i32Out2;
5350	pfn(&State, &fMxcsr2, &i32Out2, &TestData.r64ValIn.u);
5351	TestData.fMxcsrIn = State.MXCSR;
5352	TestData.fMxcsrOut = fMxcsr2;
5353	TestData.i32ValOut = i32Out2;
5354	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5355	}
5356	if (!RT_IS_POWER_OF_TWO(fXcpt))
5357	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5358	if (fUnmasked & fXcpt)
5359	{
5360	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5361	uint32_t fMxcsr3; int32_t i32Out3;
5362	pfn(&State, &fMxcsr3, &i32Out3, &TestData.r64ValIn.u);
5363	TestData.fMxcsrIn = State.MXCSR;
5364	TestData.fMxcsrOut = fMxcsr3;
5365	TestData.i32ValOut = i32Out3;
5366	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5367	}
5368	}
5369	}
5370	}
5371	rc = RTStrmClose(pStrmOut);
5372	if (RT_FAILURE(rc))
5373	{
5374	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryI32R64[iFn].pszName, rc);
5375	return RTEXITCODE_FAILURE;
5376	}
5377	}
5378
5379	return RTEXITCODE_SUCCESS;
5380	}
5381	#endif
5382
5383
5384	static void SseBinaryI32R64Test(void)
5385	{
5386	X86FXSTATE State;
5387	RT_ZERO(State);
5388	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R64); iFn++)
5389	{
5390	if (!SubTestAndCheckIfEnabled(g_aSseBinaryI32R64[iFn].pszName))
5391	continue;
5392
5393	uint32_t const cTests = *g_aSseBinaryI32R64[iFn].pcTests;
5394	SSE_BINARY_I32_R64_TEST_T const * const paTests = g_aSseBinaryI32R64[iFn].paTests;
5395	PFNIEMAIMPLSSEF2I32U64 pfn = g_aSseBinaryI32R64[iFn].pfn;
5396	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryI32R64[iFn]);
5397	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5398	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5399	{
5400	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_I32_R64_TEST_T); iTest++)
5401	{
5402	uint32_t fMxcsr = 0;
5403	int32_t i32Dst = 0;
5404
5405	State.MXCSR = paTests[iTest].fMxcsrIn;
5406	pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r64ValIn.u);
5407	if ( fMxcsr != paTests[iTest].fMxcsrOut
5408	\|\| i32Dst != paTests[iTest].i32ValOut)
5409	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s\n"
5410	"%s -> mxcsr=%#08x %RI32\n"
5411	"%s expected %#08x %RI32%s%s (%s)\n",
5412	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5413	FormatR64(&paTests[iTest].r64ValIn),
5414	iVar ? " " : "", fMxcsr, i32Dst,
5415	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].i32ValOut,
5416	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
5417	i32Dst != paTests[iTest].i32ValOut
5418	? " - val" : "",
5419	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5420	}
5421	}
5422	}
5423	}
5424
5425
5426	/*
5427	* SSE operations converting single double-precision floating point values to signed quad-word integers (cvttsd2si and friends).
5428	*/
5429	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_I64_R64_T, SSE_BINARY_I64_R64_TEST_T, PFNIEMAIMPLSSEF2I64U64);
5430
5431	static const SSE_BINARY_I64_R64_T g_aSseBinaryI64R64[] =
5432	{
5433	ENTRY_BIN(cvttsd2si_i64_r64),
5434	ENTRY_BIN(cvtsd2si_i64_r64),
5435	};
5436
5437	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5438	static RTEXITCODE SseBinaryI64R64Generate(const char *pszDataFileFmt, uint32_t cTests)
5439	{
5440	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5441
5442	static struct { RTFLOAT64U Val; } const s_aSpecials[] =
5443	{
5444	{ RTFLOAT64U_INIT_C(0, 8388607, RTFLOAT64U_EXP_MAX - 1) },
5445	/** @todo More specials. */
5446	};
5447
5448	X86FXSTATE State;
5449	RT_ZERO(State);
5450	uint32_t cMinNormalPairs = (cTests - 144) / 4;
5451	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R64); iFn++)
5452	{
5453	PFNIEMAIMPLSSEF2I64U64 const pfn = g_aSseBinaryI64R64[iFn].pfnNative ? g_aSseBinaryI64R64[iFn].pfnNative : g_aSseBinaryI64R64[iFn].pfn;
5454
5455	PRTSTREAM pStrmOut = NULL;
5456	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryI64R64[iFn].pszName);
5457	if (RT_FAILURE(rc))
5458	{
5459	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryI64R64[iFn].pszName, rc);
5460	return RTEXITCODE_FAILURE;
5461	}
5462
5463	uint32_t cNormalInputPairs = 0;
5464	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5465	{
5466	SSE_BINARY_I64_R64_TEST_T TestData; RT_ZERO(TestData);
5467
5468	TestData.r64ValIn = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val;
5469
5470	if (RTFLOAT64U_IS_NORMAL(&TestData.r64ValIn))
5471	cNormalInputPairs++;
5472	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
5473	{
5474	iTest -= 1;
5475	continue;
5476	}
5477
5478	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5479	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5480	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5481	for (uint8_t iFz = 0; iFz < 2; iFz++)
5482	{
5483	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5484	\| (iRounding << X86_MXCSR_RC_SHIFT)
5485	\| (iDaz ? X86_MXCSR_DAZ : 0)
5486	\| (iFz ? X86_MXCSR_FZ : 0)
5487	\| X86_MXCSR_XCPT_MASK;
5488	uint32_t fMxcsrM; int64_t i64OutM;
5489	pfn(&State, &fMxcsrM, &i64OutM, &TestData.r64ValIn.u);
5490	TestData.fMxcsrIn = State.MXCSR;
5491	TestData.fMxcsrOut = fMxcsrM;
5492	TestData.i64ValOut = i64OutM;
5493	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5494
5495	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5496	uint32_t fMxcsrU; int64_t i64OutU;
5497	pfn(&State, &fMxcsrU, &i64OutU, &TestData.r64ValIn.u);
5498	TestData.fMxcsrIn = State.MXCSR;
5499	TestData.fMxcsrOut = fMxcsrU;
5500	TestData.i64ValOut = i64OutU;
5501	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5502
5503	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
5504	if (fXcpt)
5505	{
5506	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
5507	uint32_t fMxcsr1; int64_t i64Out1;
5508	pfn(&State, &fMxcsr1, &i64Out1, &TestData.r64ValIn.u);
5509	TestData.fMxcsrIn = State.MXCSR;
5510	TestData.fMxcsrOut = fMxcsr1;
5511	TestData.i64ValOut = i64Out1;
5512	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5513
5514	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
5515	{
5516	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
5517	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
5518	uint32_t fMxcsr2; int64_t i64Out2;
5519	pfn(&State, &fMxcsr2, &i64Out2, &TestData.r64ValIn.u);
5520	TestData.fMxcsrIn = State.MXCSR;
5521	TestData.fMxcsrOut = fMxcsr2;
5522	TestData.i64ValOut = i64Out2;
5523	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5524	}
5525	if (!RT_IS_POWER_OF_TWO(fXcpt))
5526	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5527	if (fUnmasked & fXcpt)
5528	{
5529	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5530	uint32_t fMxcsr3; int64_t i64Out3;
5531	pfn(&State, &fMxcsr3, &i64Out3, &TestData.r64ValIn.u);
5532	TestData.fMxcsrIn = State.MXCSR;
5533	TestData.fMxcsrOut = fMxcsr3;
5534	TestData.i64ValOut = i64Out3;
5535	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5536	}
5537	}
5538	}
5539	}
5540	rc = RTStrmClose(pStrmOut);
5541	if (RT_FAILURE(rc))
5542	{
5543	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryI64R64[iFn].pszName, rc);
5544	return RTEXITCODE_FAILURE;
5545	}
5546	}
5547
5548	return RTEXITCODE_SUCCESS;
5549	}
5550	#endif
5551
5552
5553	static void SseBinaryI64R64Test(void)
5554	{
5555	X86FXSTATE State;
5556	RT_ZERO(State);
5557	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R64); iFn++)
5558	{
5559	if (!SubTestAndCheckIfEnabled(g_aSseBinaryI64R64[iFn].pszName))
5560	continue;
5561
5562	uint32_t const cTests = *g_aSseBinaryI64R64[iFn].pcTests;
5563	SSE_BINARY_I64_R64_TEST_T const * const paTests = g_aSseBinaryI64R64[iFn].paTests;
5564	PFNIEMAIMPLSSEF2I64U64 pfn = g_aSseBinaryI64R64[iFn].pfn;
5565	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryI32R64[iFn]);
5566	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5567	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5568	{
5569	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_I64_R64_TEST_T); iTest++)
5570	{
5571	uint32_t fMxcsr = 0;
5572	int64_t i64Dst = 0;
5573
5574	State.MXCSR = paTests[iTest].fMxcsrIn;
5575	pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r64ValIn.u);
5576	if ( fMxcsr != paTests[iTest].fMxcsrOut
5577	\|\| i64Dst != paTests[iTest].i64ValOut)
5578	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s\n"
5579	"%s -> mxcsr=%#08x %RI64\n"
5580	"%s expected %#08x %RI64%s%s (%s)\n",
5581	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5582	FormatR64(&paTests[iTest].r64ValIn),
5583	iVar ? " " : "", fMxcsr, i64Dst,
5584	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].i64ValOut,
5585	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
5586	i64Dst != paTests[iTest].i64ValOut
5587	? " - val" : "",
5588	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5589	}
5590	}
5591	}
5592	}
5593
5594
5595	/*
5596	* SSE operations converting single single-precision floating point values to signed double-word integers (cvttss2si and friends).
5597	*/
5598	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_I32_R32_T, SSE_BINARY_I32_R32_TEST_T, PFNIEMAIMPLSSEF2I32U32);
5599
5600	static const SSE_BINARY_I32_R32_T g_aSseBinaryI32R32[] =
5601	{
5602	ENTRY_BIN(cvttss2si_i32_r32),
5603	ENTRY_BIN(cvtss2si_i32_r32),
5604	};
5605
5606	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5607	static RTEXITCODE SseBinaryI32R32Generate(const char *pszDataFileFmt, uint32_t cTests)
5608	{
5609	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5610
5611	static struct { RTFLOAT32U Val; } const s_aSpecials[] =
5612	{
5613	{ RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1) },
5614	/** @todo More specials. */
5615	};
5616
5617	X86FXSTATE State;
5618	RT_ZERO(State);
5619	uint32_t cMinNormalPairs = (cTests - 144) / 4;
5620	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R32); iFn++)
5621	{
5622	PFNIEMAIMPLSSEF2I32U32 const pfn = g_aSseBinaryI32R32[iFn].pfnNative ? g_aSseBinaryI32R32[iFn].pfnNative : g_aSseBinaryI32R32[iFn].pfn;
5623
5624	PRTSTREAM pStrmOut = NULL;
5625	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryI32R32[iFn].pszName);
5626	if (RT_FAILURE(rc))
5627	{
5628	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryI32R32[iFn].pszName, rc);
5629	return RTEXITCODE_FAILURE;
5630	}
5631
5632	uint32_t cNormalInputPairs = 0;
5633	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5634	{
5635	SSE_BINARY_I32_R32_TEST_T TestData; RT_ZERO(TestData);
5636
5637	TestData.r32ValIn = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val;
5638
5639	if (RTFLOAT32U_IS_NORMAL(&TestData.r32ValIn))
5640	cNormalInputPairs++;
5641	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
5642	{
5643	iTest -= 1;
5644	continue;
5645	}
5646
5647	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5648	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5649	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5650	for (uint8_t iFz = 0; iFz < 2; iFz++)
5651	{
5652	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5653	\| (iRounding << X86_MXCSR_RC_SHIFT)
5654	\| (iDaz ? X86_MXCSR_DAZ : 0)
5655	\| (iFz ? X86_MXCSR_FZ : 0)
5656	\| X86_MXCSR_XCPT_MASK;
5657	uint32_t fMxcsrM; int32_t i32OutM;
5658	pfn(&State, &fMxcsrM, &i32OutM, &TestData.r32ValIn.u);
5659	TestData.fMxcsrIn = State.MXCSR;
5660	TestData.fMxcsrOut = fMxcsrM;
5661	TestData.i32ValOut = i32OutM;
5662	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5663
5664	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5665	uint32_t fMxcsrU; int32_t i32OutU;
5666	pfn(&State, &fMxcsrU, &i32OutU, &TestData.r32ValIn.u);
5667	TestData.fMxcsrIn = State.MXCSR;
5668	TestData.fMxcsrOut = fMxcsrU;
5669	TestData.i32ValOut = i32OutU;
5670	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5671
5672	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
5673	if (fXcpt)
5674	{
5675	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
5676	uint32_t fMxcsr1; int32_t i32Out1;
5677	pfn(&State, &fMxcsr1, &i32Out1, &TestData.r32ValIn.u);
5678	TestData.fMxcsrIn = State.MXCSR;
5679	TestData.fMxcsrOut = fMxcsr1;
5680	TestData.i32ValOut = i32Out1;
5681	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5682
5683	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
5684	{
5685	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
5686	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
5687	uint32_t fMxcsr2; int32_t i32Out2;
5688	pfn(&State, &fMxcsr2, &i32Out2, &TestData.r32ValIn.u);
5689	TestData.fMxcsrIn = State.MXCSR;
5690	TestData.fMxcsrOut = fMxcsr2;
5691	TestData.i32ValOut = i32Out2;
5692	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5693	}
5694	if (!RT_IS_POWER_OF_TWO(fXcpt))
5695	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5696	if (fUnmasked & fXcpt)
5697	{
5698	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5699	uint32_t fMxcsr3; int32_t i32Out3;
5700	pfn(&State, &fMxcsr3, &i32Out3, &TestData.r32ValIn.u);
5701	TestData.fMxcsrIn = State.MXCSR;
5702	TestData.fMxcsrOut = fMxcsr3;
5703	TestData.i32ValOut = i32Out3;
5704	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5705	}
5706	}
5707	}
5708	}
5709	rc = RTStrmClose(pStrmOut);
5710	if (RT_FAILURE(rc))
5711	{
5712	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryI32R32[iFn].pszName, rc);
5713	return RTEXITCODE_FAILURE;
5714	}
5715	}
5716
5717	return RTEXITCODE_SUCCESS;
5718	}
5719	#endif
5720
5721
5722	static void SseBinaryI32R32Test(void)
5723	{
5724	X86FXSTATE State;
5725	RT_ZERO(State);
5726	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R32); iFn++)
5727	{
5728	if (!SubTestAndCheckIfEnabled(g_aSseBinaryI32R32[iFn].pszName))
5729	continue;
5730
5731	uint32_t const cTests = *g_aSseBinaryI32R32[iFn].pcTests;
5732	SSE_BINARY_I32_R32_TEST_T const * const paTests = g_aSseBinaryI32R32[iFn].paTests;
5733	PFNIEMAIMPLSSEF2I32U32 pfn = g_aSseBinaryI32R32[iFn].pfn;
5734	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryI32R32[iFn]);
5735	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5736	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5737	{
5738	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_I32_R32_TEST_T); iTest++)
5739	{
5740	uint32_t fMxcsr = 0;
5741	int32_t i32Dst = 0;
5742
5743	State.MXCSR = paTests[iTest].fMxcsrIn;
5744	pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r32ValIn.u);
5745	if ( fMxcsr != paTests[iTest].fMxcsrOut
5746	\|\| i32Dst != paTests[iTest].i32ValOut)
5747	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s\n"
5748	"%s -> mxcsr=%#08x %RI32\n"
5749	"%s expected %#08x %RI32%s%s (%s)\n",
5750	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5751	FormatR32(&paTests[iTest].r32ValIn),
5752	iVar ? " " : "", fMxcsr, i32Dst,
5753	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].i32ValOut,
5754	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
5755	i32Dst != paTests[iTest].i32ValOut
5756	? " - val" : "",
5757	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5758	}
5759	}
5760	}
5761	}
5762
5763
5764	/*
5765	* SSE operations converting single single-precision floating point values to signed quad-word integers (cvttss2si and friends).
5766	*/
5767	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_I64_R32_T, SSE_BINARY_I64_R32_TEST_T, PFNIEMAIMPLSSEF2I64U32);
5768
5769	static const SSE_BINARY_I64_R32_T g_aSseBinaryI64R32[] =
5770	{
5771	ENTRY_BIN(cvttss2si_i64_r32),
5772	ENTRY_BIN(cvtss2si_i64_r32),
5773	};
5774
5775	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5776	static RTEXITCODE SseBinaryI64R32Generate(const char *pszDataFileFmt, uint32_t cTests)
5777	{
5778	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5779
5780	static struct { RTFLOAT32U Val; } const s_aSpecials[] =
5781	{
5782	{ RTFLOAT32U_INIT_C(0, 8388607, RTFLOAT32U_EXP_MAX - 1) },
5783	/** @todo More specials. */
5784	};
5785
5786	X86FXSTATE State;
5787	RT_ZERO(State);
5788	uint32_t cMinNormalPairs = (cTests - 144) / 4;
5789	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R32); iFn++)
5790	{
5791	PFNIEMAIMPLSSEF2I64U32 const pfn = g_aSseBinaryI64R32[iFn].pfnNative ? g_aSseBinaryI64R32[iFn].pfnNative : g_aSseBinaryI64R32[iFn].pfn;
5792
5793	PRTSTREAM pStrmOut = NULL;
5794	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryI64R32[iFn].pszName);
5795	if (RT_FAILURE(rc))
5796	{
5797	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryI64R32[iFn].pszName, rc);
5798	return RTEXITCODE_FAILURE;
5799	}
5800
5801	uint32_t cNormalInputPairs = 0;
5802	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5803	{
5804	SSE_BINARY_I64_R32_TEST_T TestData; RT_ZERO(TestData);
5805
5806	TestData.r32ValIn = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val;
5807
5808	if (RTFLOAT32U_IS_NORMAL(&TestData.r32ValIn))
5809	cNormalInputPairs++;
5810	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
5811	{
5812	iTest -= 1;
5813	continue;
5814	}
5815
5816	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5817	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5818	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5819	for (uint8_t iFz = 0; iFz < 2; iFz++)
5820	{
5821	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5822	\| (iRounding << X86_MXCSR_RC_SHIFT)
5823	\| (iDaz ? X86_MXCSR_DAZ : 0)
5824	\| (iFz ? X86_MXCSR_FZ : 0)
5825	\| X86_MXCSR_XCPT_MASK;
5826	uint32_t fMxcsrM; int64_t i64OutM;
5827	pfn(&State, &fMxcsrM, &i64OutM, &TestData.r32ValIn.u);
5828	TestData.fMxcsrIn = State.MXCSR;
5829	TestData.fMxcsrOut = fMxcsrM;
5830	TestData.i64ValOut = i64OutM;
5831	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5832
5833	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5834	uint32_t fMxcsrU; int64_t i64OutU;
5835	pfn(&State, &fMxcsrU, &i64OutU, &TestData.r32ValIn.u);
5836	TestData.fMxcsrIn = State.MXCSR;
5837	TestData.fMxcsrOut = fMxcsrU;
5838	TestData.i64ValOut = i64OutU;
5839	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5840
5841	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
5842	if (fXcpt)
5843	{
5844	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
5845	uint32_t fMxcsr1; int64_t i64Out1;
5846	pfn(&State, &fMxcsr1, &i64Out1, &TestData.r32ValIn.u);
5847	TestData.fMxcsrIn = State.MXCSR;
5848	TestData.fMxcsrOut = fMxcsr1;
5849	TestData.i64ValOut = i64Out1;
5850	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5851
5852	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
5853	{
5854	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
5855	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
5856	uint32_t fMxcsr2; int64_t i64Out2;
5857	pfn(&State, &fMxcsr2, &i64Out2, &TestData.r32ValIn.u);
5858	TestData.fMxcsrIn = State.MXCSR;
5859	TestData.fMxcsrOut = fMxcsr2;
5860	TestData.i64ValOut = i64Out2;
5861	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5862	}
5863	if (!RT_IS_POWER_OF_TWO(fXcpt))
5864	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
5865	if (fUnmasked & fXcpt)
5866	{
5867	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
5868	uint32_t fMxcsr3; int64_t i64Out3;
5869	pfn(&State, &fMxcsr3, &i64Out3, &TestData.r32ValIn.u);
5870	TestData.fMxcsrIn = State.MXCSR;
5871	TestData.fMxcsrOut = fMxcsr3;
5872	TestData.i64ValOut = i64Out3;
5873	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5874	}
5875	}
5876	}
5877	}
5878	rc = RTStrmClose(pStrmOut);
5879	if (RT_FAILURE(rc))
5880	{
5881	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryI64R32[iFn].pszName, rc);
5882	return RTEXITCODE_FAILURE;
5883	}
5884	}
5885
5886	return RTEXITCODE_SUCCESS;
5887	}
5888	#endif
5889
5890
5891	static void SseBinaryI64R32Test(void)
5892	{
5893	X86FXSTATE State;
5894	RT_ZERO(State);
5895	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R32); iFn++)
5896	{
5897	if (!SubTestAndCheckIfEnabled(g_aSseBinaryI64R32[iFn].pszName))
5898	continue;
5899
5900	uint32_t const cTests = *g_aSseBinaryI64R32[iFn].pcTests;
5901	SSE_BINARY_I64_R32_TEST_T const * const paTests = g_aSseBinaryI64R32[iFn].paTests;
5902	PFNIEMAIMPLSSEF2I64U32 pfn = g_aSseBinaryI64R32[iFn].pfn;
5903	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryI64R32[iFn]);
5904	if (!cTests) RTTestSkipped(g_hTest, "no tests");
5905	for (uint32_t iVar = 0; iVar < cVars; iVar++)
5906	{
5907	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_I64_R32_TEST_T); iTest++)
5908	{
5909	uint32_t fMxcsr = 0;
5910	int64_t i64Dst = 0;
5911
5912	State.MXCSR = paTests[iTest].fMxcsrIn;
5913	pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r32ValIn.u);
5914	if ( fMxcsr != paTests[iTest].fMxcsrOut
5915	\|\| i64Dst != paTests[iTest].i64ValOut)
5916	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s\n"
5917	"%s -> mxcsr=%#08x %RI64\n"
5918	"%s expected %#08x %RI64%s%s (%s)\n",
5919	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
5920	FormatR32(&paTests[iTest].r32ValIn),
5921	iVar ? " " : "", fMxcsr, i64Dst,
5922	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].i64ValOut,
5923	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
5924	i64Dst != paTests[iTest].i64ValOut
5925	? " - val" : "",
5926	FormatMxcsr(paTests[iTest].fMxcsrIn) );
5927	}
5928	}
5929	}
5930	}
5931
5932
5933	/*
5934	* SSE operations converting single signed double-word integers to double-precision floating point values (probably only cvtsi2sd).
5935	*/
5936	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R64_I32_T, SSE_BINARY_R64_I32_TEST_T, PFNIEMAIMPLSSEF2R64I32);
5937
5938	static const SSE_BINARY_R64_I32_T g_aSseBinaryR64I32[] =
5939	{
5940	ENTRY_BIN(cvtsi2sd_r64_i32)
5941	};
5942
5943	#ifdef TSTIEMAIMPL_WITH_GENERATOR
5944	static RTEXITCODE SseBinaryR64I32Generate(const char *pszDataFileFmt, uint32_t cTests)
5945	{
5946	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
5947
5948	static int32_t const s_aSpecials[] =
5949	{
5950	INT32_MIN,
5951	INT32_MAX,
5952	/** @todo More specials. */
5953	};
5954
5955	X86FXSTATE State;
5956	RT_ZERO(State);
5957	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++)
5958	{
5959	PFNIEMAIMPLSSEF2R64I32 const pfn = g_aSseBinaryR64I32[iFn].pfnNative ? g_aSseBinaryR64I32[iFn].pfnNative : g_aSseBinaryR64I32[iFn].pfn;
5960
5961	PRTSTREAM pStrmOut = NULL;
5962	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR64I32[iFn].pszName);
5963	if (RT_FAILURE(rc))
5964	{
5965	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR64I32[iFn].pszName, rc);
5966	return RTEXITCODE_FAILURE;
5967	}
5968
5969	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
5970	{
5971	SSE_BINARY_R64_I32_TEST_T TestData; RT_ZERO(TestData);
5972
5973	TestData.i32ValIn = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
5974
5975	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
5976	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
5977	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
5978	for (uint8_t iFz = 0; iFz < 2; iFz++)
5979	{
5980	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
5981	\| (iRounding << X86_MXCSR_RC_SHIFT)
5982	\| (iDaz ? X86_MXCSR_DAZ : 0)
5983	\| (iFz ? X86_MXCSR_FZ : 0)
5984	\| X86_MXCSR_XCPT_MASK;
5985	uint32_t fMxcsrM; RTFLOAT64U r64OutM;
5986	pfn(&State, &fMxcsrM, &r64OutM, &TestData.i32ValIn);
5987	TestData.fMxcsrIn = State.MXCSR;
5988	TestData.fMxcsrOut = fMxcsrM;
5989	TestData.r64ValOut = r64OutM;
5990	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5991
5992	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
5993	uint32_t fMxcsrU; RTFLOAT64U r64OutU;
5994	pfn(&State, &fMxcsrU, &r64OutU, &TestData.i32ValIn);
5995	TestData.fMxcsrIn = State.MXCSR;
5996	TestData.fMxcsrOut = fMxcsrU;
5997	TestData.r64ValOut = r64OutU;
5998	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
5999
6000	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6001	if (fXcpt)
6002	{
6003	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6004	uint32_t fMxcsr1; RTFLOAT64U r64Out1;
6005	pfn(&State, &fMxcsr1, &r64Out1, &TestData.i32ValIn);
6006	TestData.fMxcsrIn = State.MXCSR;
6007	TestData.fMxcsrOut = fMxcsr1;
6008	TestData.r64ValOut = r64Out1;
6009	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6010
6011	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6012	{
6013	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6014	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6015	uint32_t fMxcsr2; RTFLOAT64U r64Out2;
6016	pfn(&State, &fMxcsr2, &r64Out2, &TestData.i32ValIn);
6017	TestData.fMxcsrIn = State.MXCSR;
6018	TestData.fMxcsrOut = fMxcsr2;
6019	TestData.r64ValOut = r64Out2;
6020	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6021	}
6022	if (!RT_IS_POWER_OF_TWO(fXcpt))
6023	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6024	if (fUnmasked & fXcpt)
6025	{
6026	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6027	uint32_t fMxcsr3; RTFLOAT64U r64Out3;
6028	pfn(&State, &fMxcsr3, &r64Out3, &TestData.i32ValIn);
6029	TestData.fMxcsrIn = State.MXCSR;
6030	TestData.fMxcsrOut = fMxcsr3;
6031	TestData.r64ValOut = r64Out3;
6032	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6033	}
6034	}
6035	}
6036	}
6037	rc = RTStrmClose(pStrmOut);
6038	if (RT_FAILURE(rc))
6039	{
6040	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR64I32[iFn].pszName, rc);
6041	return RTEXITCODE_FAILURE;
6042	}
6043	}
6044
6045	return RTEXITCODE_SUCCESS;
6046	}
6047	#endif
6048
6049
6050	static void SseBinaryR64I32Test(void)
6051	{
6052	X86FXSTATE State;
6053	RT_ZERO(State);
6054	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++)
6055	{
6056	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR64I32[iFn].pszName))
6057	continue;
6058
6059	uint32_t const cTests = *g_aSseBinaryR64I32[iFn].pcTests;
6060	SSE_BINARY_R64_I32_TEST_T const * const paTests = g_aSseBinaryR64I32[iFn].paTests;
6061	PFNIEMAIMPLSSEF2R64I32 pfn = g_aSseBinaryR64I32[iFn].pfn;
6062	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR64I32[iFn]);
6063	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6064	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6065	{
6066	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_R64_I32_TEST_T); iTest++)
6067	{
6068	uint32_t fMxcsr = 0;
6069	RTFLOAT64U r64Dst; RT_ZERO(r64Dst);
6070
6071	State.MXCSR = paTests[iTest].fMxcsrIn;
6072	pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i32ValIn);
6073	if ( fMxcsr != paTests[iTest].fMxcsrOut
6074	\|\| !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut))
6075	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32\n"
6076	"%s -> mxcsr=%#08x %s\n"
6077	"%s expected %#08x %s%s%s (%s)\n",
6078	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
6079	&paTests[iTest].i32ValIn,
6080	iVar ? " " : "", fMxcsr, FormatR64(&r64Dst),
6081	iVar ? " " : "", paTests[iTest].fMxcsrOut, FormatR64(&paTests[iTest].r64ValOut),
6082	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6083	!RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut)
6084	? " - val" : "",
6085	FormatMxcsr(paTests[iTest].fMxcsrIn) );
6086	}
6087	}
6088	}
6089	}
6090
6091
6092	/*
6093	* SSE operations converting single signed quad-word integers to double-precision floating point values (probably only cvtsi2sd).
6094	*/
6095	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R64_I64_T, SSE_BINARY_R64_I64_TEST_T, PFNIEMAIMPLSSEF2R64I64);
6096
6097	static const SSE_BINARY_R64_I64_T g_aSseBinaryR64I64[] =
6098	{
6099	ENTRY_BIN(cvtsi2sd_r64_i64),
6100	};
6101
6102	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6103	static RTEXITCODE SseBinaryR64I64Generate(const char *pszDataFileFmt, uint32_t cTests)
6104	{
6105	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6106
6107	static int64_t const s_aSpecials[] =
6108	{
6109	INT64_MIN,
6110	INT64_MAX
6111	/** @todo More specials. */
6112	};
6113
6114	X86FXSTATE State;
6115	RT_ZERO(State);
6116	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++)
6117	{
6118	PFNIEMAIMPLSSEF2R64I64 const pfn = g_aSseBinaryR64I64[iFn].pfnNative ? g_aSseBinaryR64I64[iFn].pfnNative : g_aSseBinaryR64I64[iFn].pfn;
6119
6120	PRTSTREAM pStrmOut = NULL;
6121	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR64I64[iFn].pszName);
6122	if (RT_FAILURE(rc))
6123	{
6124	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR64I64[iFn].pszName, rc);
6125	return RTEXITCODE_FAILURE;
6126	}
6127
6128	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
6129	{
6130	SSE_BINARY_R64_I64_TEST_T TestData; RT_ZERO(TestData);
6131
6132	TestData.i64ValIn = iTest < cTests ? RandI64Src(iTest) : s_aSpecials[iTest - cTests];
6133
6134	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
6135	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
6136	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
6137	for (uint8_t iFz = 0; iFz < 2; iFz++)
6138	{
6139	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
6140	\| (iRounding << X86_MXCSR_RC_SHIFT)
6141	\| (iDaz ? X86_MXCSR_DAZ : 0)
6142	\| (iFz ? X86_MXCSR_FZ : 0)
6143	\| X86_MXCSR_XCPT_MASK;
6144	uint32_t fMxcsrM; RTFLOAT64U r64OutM;
6145	pfn(&State, &fMxcsrM, &r64OutM, &TestData.i64ValIn);
6146	TestData.fMxcsrIn = State.MXCSR;
6147	TestData.fMxcsrOut = fMxcsrM;
6148	TestData.r64ValOut = r64OutM;
6149	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6150
6151	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
6152	uint32_t fMxcsrU; RTFLOAT64U r64OutU;
6153	pfn(&State, &fMxcsrU, &r64OutU, &TestData.i64ValIn);
6154	TestData.fMxcsrIn = State.MXCSR;
6155	TestData.fMxcsrOut = fMxcsrU;
6156	TestData.r64ValOut = r64OutU;
6157	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6158
6159	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6160	if (fXcpt)
6161	{
6162	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6163	uint32_t fMxcsr1; RTFLOAT64U r64Out1;
6164	pfn(&State, &fMxcsr1, &r64Out1, &TestData.i64ValIn);
6165	TestData.fMxcsrIn = State.MXCSR;
6166	TestData.fMxcsrOut = fMxcsr1;
6167	TestData.r64ValOut = r64Out1;
6168	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6169
6170	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6171	{
6172	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6173	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6174	uint32_t fMxcsr2; RTFLOAT64U r64Out2;
6175	pfn(&State, &fMxcsr2, &r64Out2, &TestData.i64ValIn);
6176	TestData.fMxcsrIn = State.MXCSR;
6177	TestData.fMxcsrOut = fMxcsr2;
6178	TestData.r64ValOut = r64Out2;
6179	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6180	}
6181	if (!RT_IS_POWER_OF_TWO(fXcpt))
6182	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6183	if (fUnmasked & fXcpt)
6184	{
6185	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6186	uint32_t fMxcsr3; RTFLOAT64U r64Out3;
6187	pfn(&State, &fMxcsr3, &r64Out3, &TestData.i64ValIn);
6188	TestData.fMxcsrIn = State.MXCSR;
6189	TestData.fMxcsrOut = fMxcsr3;
6190	TestData.r64ValOut = r64Out3;
6191	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6192	}
6193	}
6194	}
6195	}
6196	rc = RTStrmClose(pStrmOut);
6197	if (RT_FAILURE(rc))
6198	{
6199	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR64I64[iFn].pszName, rc);
6200	return RTEXITCODE_FAILURE;
6201	}
6202	}
6203
6204	return RTEXITCODE_SUCCESS;
6205	}
6206	#endif
6207
6208
6209	static void SseBinaryR64I64Test(void)
6210	{
6211	X86FXSTATE State;
6212	RT_ZERO(State);
6213	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++)
6214	{
6215	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR64I64[iFn].pszName))
6216	continue;
6217
6218	uint32_t const cTests = *g_aSseBinaryR64I64[iFn].pcTests;
6219	SSE_BINARY_R64_I64_TEST_T const * const paTests = g_aSseBinaryR64I64[iFn].paTests;
6220	PFNIEMAIMPLSSEF2R64I64 pfn = g_aSseBinaryR64I64[iFn].pfn;
6221	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR64I64[iFn]);
6222	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6223	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6224	{
6225	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_R64_I64_TEST_T); iTest++)
6226	{
6227	uint32_t fMxcsr = 0;
6228	RTFLOAT64U r64Dst; RT_ZERO(r64Dst);
6229
6230	State.MXCSR = paTests[iTest].fMxcsrIn;
6231	pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i64ValIn);
6232	if ( fMxcsr != paTests[iTest].fMxcsrOut
6233	\|\| !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut))
6234	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI64\n"
6235	"%s -> mxcsr=%#08x %s\n"
6236	"%s expected %#08x %s%s%s (%s)\n",
6237	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
6238	&paTests[iTest].i64ValIn,
6239	iVar ? " " : "", fMxcsr, FormatR64(&r64Dst),
6240	iVar ? " " : "", paTests[iTest].fMxcsrOut, FormatR64(&paTests[iTest].r64ValOut),
6241	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6242	!RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut)
6243	? " - val" : "",
6244	FormatMxcsr(paTests[iTest].fMxcsrIn) );
6245	}
6246	}
6247	}
6248	}
6249
6250
6251	/*
6252	* SSE operations converting single signed double-word integers to single-precision floating point values (probably only cvtsi2ss).
6253	*/
6254	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R32_I32_T, SSE_BINARY_R32_I32_TEST_T, PFNIEMAIMPLSSEF2R32I32);
6255
6256	static const SSE_BINARY_R32_I32_T g_aSseBinaryR32I32[] =
6257	{
6258	ENTRY_BIN(cvtsi2ss_r32_i32),
6259	};
6260
6261	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6262	static RTEXITCODE SseBinaryR32I32Generate(const char *pszDataFileFmt, uint32_t cTests)
6263	{
6264	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6265
6266	static int32_t const s_aSpecials[] =
6267	{
6268	INT32_MIN,
6269	INT32_MAX,
6270	/** @todo More specials. */
6271	};
6272
6273	X86FXSTATE State;
6274	RT_ZERO(State);
6275	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++)
6276	{
6277	PFNIEMAIMPLSSEF2R32I32 const pfn = g_aSseBinaryR32I32[iFn].pfnNative ? g_aSseBinaryR32I32[iFn].pfnNative : g_aSseBinaryR32I32[iFn].pfn;
6278
6279	PRTSTREAM pStrmOut = NULL;
6280	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR32I32[iFn].pszName);
6281	if (RT_FAILURE(rc))
6282	{
6283	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR32I32[iFn].pszName, rc);
6284	return RTEXITCODE_FAILURE;
6285	}
6286
6287	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
6288	{
6289	SSE_BINARY_R32_I32_TEST_T TestData; RT_ZERO(TestData);
6290
6291	TestData.i32ValIn = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
6292
6293	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
6294	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
6295	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
6296	for (uint8_t iFz = 0; iFz < 2; iFz++)
6297	{
6298	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
6299	\| (iRounding << X86_MXCSR_RC_SHIFT)
6300	\| (iDaz ? X86_MXCSR_DAZ : 0)
6301	\| (iFz ? X86_MXCSR_FZ : 0)
6302	\| X86_MXCSR_XCPT_MASK;
6303	uint32_t fMxcsrM; RTFLOAT32U r32OutM;
6304	pfn(&State, &fMxcsrM, &r32OutM, &TestData.i32ValIn);
6305	TestData.fMxcsrIn = State.MXCSR;
6306	TestData.fMxcsrOut = fMxcsrM;
6307	TestData.r32ValOut = r32OutM;
6308	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6309
6310	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
6311	uint32_t fMxcsrU; RTFLOAT32U r32OutU;
6312	pfn(&State, &fMxcsrU, &r32OutU, &TestData.i32ValIn);
6313	TestData.fMxcsrIn = State.MXCSR;
6314	TestData.fMxcsrOut = fMxcsrU;
6315	TestData.r32ValOut = r32OutU;
6316	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6317
6318	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6319	if (fXcpt)
6320	{
6321	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6322	uint32_t fMxcsr1; RTFLOAT32U r32Out1;
6323	pfn(&State, &fMxcsr1, &r32Out1, &TestData.i32ValIn);
6324	TestData.fMxcsrIn = State.MXCSR;
6325	TestData.fMxcsrOut = fMxcsr1;
6326	TestData.r32ValOut = r32Out1;
6327	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6328
6329	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6330	{
6331	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6332	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6333	uint32_t fMxcsr2; RTFLOAT32U r32Out2;
6334	pfn(&State, &fMxcsr2, &r32Out2, &TestData.i32ValIn);
6335	TestData.fMxcsrIn = State.MXCSR;
6336	TestData.fMxcsrOut = fMxcsr2;
6337	TestData.r32ValOut = r32Out2;
6338	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6339	}
6340	if (!RT_IS_POWER_OF_TWO(fXcpt))
6341	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6342	if (fUnmasked & fXcpt)
6343	{
6344	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6345	uint32_t fMxcsr3; RTFLOAT32U r32Out3;
6346	pfn(&State, &fMxcsr3, &r32Out3, &TestData.i32ValIn);
6347	TestData.fMxcsrIn = State.MXCSR;
6348	TestData.fMxcsrOut = fMxcsr3;
6349	TestData.r32ValOut = r32Out3;
6350	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6351	}
6352	}
6353	}
6354	}
6355	rc = RTStrmClose(pStrmOut);
6356	if (RT_FAILURE(rc))
6357	{
6358	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR32I32[iFn].pszName, rc);
6359	return RTEXITCODE_FAILURE;
6360	}
6361	}
6362
6363	return RTEXITCODE_SUCCESS;
6364	}
6365	#endif
6366
6367
6368	static void SseBinaryR32I32Test(void)
6369	{
6370	X86FXSTATE State;
6371	RT_ZERO(State);
6372	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++)
6373	{
6374	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR32I32[iFn].pszName))
6375	continue;
6376
6377	uint32_t const cTests = *g_aSseBinaryR32I32[iFn].pcTests;
6378	SSE_BINARY_R32_I32_TEST_T const * const paTests = g_aSseBinaryR32I32[iFn].paTests;
6379	PFNIEMAIMPLSSEF2R32I32 pfn = g_aSseBinaryR32I32[iFn].pfn;
6380	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR32I32[iFn]);
6381	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6382	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6383	{
6384	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_R32_I32_TEST_T); iTest++)
6385	{
6386	uint32_t fMxcsr = 0;
6387	RTFLOAT32U r32Dst; RT_ZERO(r32Dst);
6388
6389	State.MXCSR = paTests[iTest].fMxcsrIn;
6390	pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i32ValIn);
6391	if ( fMxcsr != paTests[iTest].fMxcsrOut
6392	\|\| !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut))
6393	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32\n"
6394	"%s -> mxcsr=%#08x %RI32\n"
6395	"%s expected %#08x %RI32%s%s (%s)\n",
6396	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
6397	&paTests[iTest].i32ValIn,
6398	iVar ? " " : "", fMxcsr, FormatR32(&r32Dst),
6399	iVar ? " " : "", paTests[iTest].fMxcsrOut, FormatR32(&paTests[iTest].r32ValOut),
6400	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6401	!RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut)
6402	? " - val" : "",
6403	FormatMxcsr(paTests[iTest].fMxcsrIn) );
6404	}
6405	}
6406	}
6407	}
6408
6409
6410	/*
6411	* SSE operations converting single signed quad-word integers to single-precision floating point values (probably only cvtsi2ss).
6412	*/
6413	TYPEDEF_SUBTEST_TYPE(SSE_BINARY_R32_I64_T, SSE_BINARY_R32_I64_TEST_T, PFNIEMAIMPLSSEF2R32I64);
6414
6415	static const SSE_BINARY_R32_I64_T g_aSseBinaryR32I64[] =
6416	{
6417	ENTRY_BIN(cvtsi2ss_r32_i64),
6418	};
6419
6420	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6421	static RTEXITCODE SseBinaryR32I64Generate(const char *pszDataFileFmt, uint32_t cTests)
6422	{
6423	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6424
6425	static int64_t const s_aSpecials[] =
6426	{
6427	INT64_MIN,
6428	INT64_MAX
6429	/** @todo More specials. */
6430	};
6431
6432	X86FXSTATE State;
6433	RT_ZERO(State);
6434	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++)
6435	{
6436	PFNIEMAIMPLSSEF2R32I64 const pfn = g_aSseBinaryR32I64[iFn].pfnNative ? g_aSseBinaryR32I64[iFn].pfnNative : g_aSseBinaryR32I64[iFn].pfn;
6437
6438	PRTSTREAM pStrmOut = NULL;
6439	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseBinaryR32I64[iFn].pszName);
6440	if (RT_FAILURE(rc))
6441	{
6442	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseBinaryR32I64[iFn].pszName, rc);
6443	return RTEXITCODE_FAILURE;
6444	}
6445
6446	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
6447	{
6448	SSE_BINARY_R32_I64_TEST_T TestData; RT_ZERO(TestData);
6449
6450	TestData.i64ValIn = iTest < cTests ? RandI64Src(iTest) : s_aSpecials[iTest - cTests];
6451
6452	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
6453	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
6454	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
6455	for (uint8_t iFz = 0; iFz < 2; iFz++)
6456	{
6457	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
6458	\| (iRounding << X86_MXCSR_RC_SHIFT)
6459	\| (iDaz ? X86_MXCSR_DAZ : 0)
6460	\| (iFz ? X86_MXCSR_FZ : 0)
6461	\| X86_MXCSR_XCPT_MASK;
6462	uint32_t fMxcsrM; RTFLOAT32U r32OutM;
6463	pfn(&State, &fMxcsrM, &r32OutM, &TestData.i64ValIn);
6464	TestData.fMxcsrIn = State.MXCSR;
6465	TestData.fMxcsrOut = fMxcsrM;
6466	TestData.r32ValOut = r32OutM;
6467	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6468
6469	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
6470	uint32_t fMxcsrU; RTFLOAT32U r32OutU;
6471	pfn(&State, &fMxcsrU, &r32OutU, &TestData.i64ValIn);
6472	TestData.fMxcsrIn = State.MXCSR;
6473	TestData.fMxcsrOut = fMxcsrU;
6474	TestData.r32ValOut = r32OutU;
6475	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6476
6477	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6478	if (fXcpt)
6479	{
6480	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6481	uint32_t fMxcsr1; RTFLOAT32U r32Out1;
6482	pfn(&State, &fMxcsr1, &r32Out1, &TestData.i64ValIn);
6483	TestData.fMxcsrIn = State.MXCSR;
6484	TestData.fMxcsrOut = fMxcsr1;
6485	TestData.r32ValOut = r32Out1;
6486	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6487
6488	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6489	{
6490	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6491	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6492	uint32_t fMxcsr2; RTFLOAT32U r32Out2;
6493	pfn(&State, &fMxcsr2, &r32Out2, &TestData.i64ValIn);
6494	TestData.fMxcsrIn = State.MXCSR;
6495	TestData.fMxcsrOut = fMxcsr2;
6496	TestData.r32ValOut = r32Out2;
6497	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6498	}
6499	if (!RT_IS_POWER_OF_TWO(fXcpt))
6500	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6501	if (fUnmasked & fXcpt)
6502	{
6503	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6504	uint32_t fMxcsr3; RTFLOAT32U r32Out3;
6505	pfn(&State, &fMxcsr3, &r32Out3, &TestData.i64ValIn);
6506	TestData.fMxcsrIn = State.MXCSR;
6507	TestData.fMxcsrOut = fMxcsr3;
6508	TestData.r32ValOut = r32Out3;
6509	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6510	}
6511	}
6512	}
6513	}
6514	rc = RTStrmClose(pStrmOut);
6515	if (RT_FAILURE(rc))
6516	{
6517	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseBinaryR32I64[iFn].pszName, rc);
6518	return RTEXITCODE_FAILURE;
6519	}
6520	}
6521
6522	return RTEXITCODE_SUCCESS;
6523	}
6524	#endif
6525
6526
6527	static void SseBinaryR32I64Test(void)
6528	{
6529	X86FXSTATE State;
6530	RT_ZERO(State);
6531	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++)
6532	{
6533	if (!SubTestAndCheckIfEnabled(g_aSseBinaryR32I64[iFn].pszName))
6534	continue;
6535
6536	uint32_t const cTests = *g_aSseBinaryR32I64[iFn].pcTests;
6537	SSE_BINARY_R32_I64_TEST_T const * const paTests = g_aSseBinaryR32I64[iFn].paTests;
6538	PFNIEMAIMPLSSEF2R32I64 pfn = g_aSseBinaryR32I64[iFn].pfn;
6539	uint32_t const cVars = COUNT_VARIATIONS(g_aSseBinaryR32I64[iFn]);
6540	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6541	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6542	{
6543	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_BINARY_R32_I64_TEST_T); iTest++)
6544	{
6545	uint32_t fMxcsr = 0;
6546	RTFLOAT32U r32Dst; RT_ZERO(r32Dst);
6547
6548	State.MXCSR = paTests[iTest].fMxcsrIn;
6549	pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i64ValIn);
6550	if ( fMxcsr != paTests[iTest].fMxcsrOut
6551	\|\| !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut))
6552	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI64\n"
6553	"%s -> mxcsr=%#08x %RI32\n"
6554	"%s expected %#08x %RI32%s%s (%s)\n",
6555	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
6556	&paTests[iTest].i64ValIn,
6557	iVar ? " " : "", fMxcsr, FormatR32(&r32Dst),
6558	iVar ? " " : "", paTests[iTest].fMxcsrOut, FormatR32(&paTests[iTest].r32ValOut),
6559	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6560	!RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut)
6561	? " - val" : "",
6562	FormatMxcsr(paTests[iTest].fMxcsrIn) );
6563	}
6564	}
6565	}
6566	}
6567
6568
6569	/*
6570	* Compare SSE operations on single single-precision floating point values - outputting only EFLAGS.
6571	*/
6572	TYPEDEF_SUBTEST_TYPE(SSE_COMPARE_EFL_R32_R32_T, SSE_COMPARE_EFL_R32_R32_TEST_T, PFNIEMAIMPLF2EFLMXCSR128);
6573
6574	static const SSE_COMPARE_EFL_R32_R32_T g_aSseCompareEflR32R32[] =
6575	{
6576	ENTRY_BIN(ucomiss_u128),
6577	ENTRY_BIN(comiss_u128),
6578	ENTRY_BIN_AVX(vucomiss_u128),
6579	ENTRY_BIN_AVX(vcomiss_u128),
6580	};
6581
6582	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6583	static RTEXITCODE SseCompareEflR32R32Generate(const char *pszDataFileFmt, uint32_t cTests)
6584	{
6585	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6586
6587	static struct { RTFLOAT32U Val1, Val2; } const s_aSpecials[] =
6588	{
6589	{ RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0) },
6590	{ RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(1) },
6591	{ RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(0) },
6592	{ RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(1) },
6593	{ RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(0) },
6594	{ RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(1) },
6595	{ RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(0) },
6596	{ RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(1) },
6597	/** @todo More specials. */
6598	};
6599
6600	uint32_t cMinNormalPairs = (cTests - 144) / 4;
6601	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareEflR32R32); iFn++)
6602	{
6603	PFNIEMAIMPLF2EFLMXCSR128 const pfn = g_aSseCompareEflR32R32[iFn].pfnNative ? g_aSseCompareEflR32R32[iFn].pfnNative : g_aSseCompareEflR32R32[iFn].pfn;
6604
6605	PRTSTREAM pStrmOut = NULL;
6606	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseCompareEflR32R32[iFn].pszName);
6607	if (RT_FAILURE(rc))
6608	{
6609	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseCompareEflR32R32[iFn].pszName, rc);
6610	return RTEXITCODE_FAILURE;
6611	}
6612
6613	uint32_t cNormalInputPairs = 0;
6614	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
6615	{
6616	SSE_COMPARE_EFL_R32_R32_TEST_T TestData; RT_ZERO(TestData);
6617	X86XMMREG ValIn1; RT_ZERO(ValIn1);
6618	X86XMMREG ValIn2; RT_ZERO(ValIn2);
6619
6620	TestData.r32ValIn1 = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val1;
6621	TestData.r32ValIn2 = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val2;
6622
6623	ValIn1.ar32[0] = TestData.r32ValIn1;
6624	ValIn2.ar32[0] = TestData.r32ValIn2;
6625
6626	if ( RTFLOAT32U_IS_NORMAL(&TestData.r32ValIn1)
6627	&& RTFLOAT32U_IS_NORMAL(&TestData.r32ValIn2))
6628	cNormalInputPairs++;
6629	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
6630	{
6631	iTest -= 1;
6632	continue;
6633	}
6634
6635	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
6636	uint32_t const fEFlags = RandEFlags();
6637	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
6638	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
6639	for (uint8_t iFz = 0; iFz < 2; iFz++)
6640	{
6641	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
6642	\| (iRounding << X86_MXCSR_RC_SHIFT)
6643	\| (iDaz ? X86_MXCSR_DAZ : 0)
6644	\| (iFz ? X86_MXCSR_FZ : 0)
6645	\| X86_MXCSR_XCPT_MASK;
6646	uint32_t fMxcsrM = fMxcsrIn;
6647	uint32_t fEFlagsM = fEFlags;
6648	pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);
6649	TestData.fMxcsrIn = fMxcsrIn;
6650	TestData.fMxcsrOut = fMxcsrM;
6651	TestData.fEflIn = fEFlags;
6652	TestData.fEflOut = fEFlagsM;
6653	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6654
6655	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
6656	uint32_t fMxcsrU = fMxcsrIn;
6657	uint32_t fEFlagsU = fEFlags;
6658	pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);
6659	TestData.fMxcsrIn = fMxcsrIn;
6660	TestData.fMxcsrOut = fMxcsrU;
6661	TestData.fEflIn = fEFlags;
6662	TestData.fEflOut = fEFlagsU;
6663	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6664
6665	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6666	if (fXcpt)
6667	{
6668	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6669	uint32_t fMxcsr1 = fMxcsrIn;
6670	uint32_t fEFlags1 = fEFlags;
6671	pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);
6672	TestData.fMxcsrIn = fMxcsrIn;
6673	TestData.fMxcsrOut = fMxcsr1;
6674	TestData.fEflIn = fEFlags;
6675	TestData.fEflOut = fEFlags1;
6676	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6677
6678	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6679	{
6680	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6681	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6682	uint32_t fMxcsr2 = fMxcsrIn;
6683	uint32_t fEFlags2 = fEFlags;
6684	pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);
6685	TestData.fMxcsrIn = fMxcsrIn;
6686	TestData.fMxcsrOut = fMxcsr2;
6687	TestData.fEflIn = fEFlags;
6688	TestData.fEflOut = fEFlags2;
6689	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6690	}
6691	if (!RT_IS_POWER_OF_TWO(fXcpt))
6692	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6693	if (fUnmasked & fXcpt)
6694	{
6695	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6696	uint32_t fMxcsr3 = fMxcsrIn;
6697	uint32_t fEFlags3 = fEFlags;
6698	pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);
6699	TestData.fMxcsrIn = fMxcsrIn;
6700	TestData.fMxcsrOut = fMxcsr3;
6701	TestData.fEflIn = fEFlags;
6702	TestData.fEflOut = fEFlags3;
6703	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6704	}
6705	}
6706	}
6707	}
6708	rc = RTStrmClose(pStrmOut);
6709	if (RT_FAILURE(rc))
6710	{
6711	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseCompareEflR32R32[iFn].pszName, rc);
6712	return RTEXITCODE_FAILURE;
6713	}
6714	}
6715
6716	return RTEXITCODE_SUCCESS;
6717	}
6718	#endif
6719
6720	static void SseCompareEflR32R32Test(void)
6721	{
6722	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareEflR32R32); iFn++)
6723	{
6724	if (!SubTestAndCheckIfEnabled(g_aSseCompareEflR32R32[iFn].pszName))
6725	continue;
6726
6727	uint32_t const cTests = *g_aSseCompareEflR32R32[iFn].pcTests;
6728	SSE_COMPARE_EFL_R32_R32_TEST_T const * const paTests = g_aSseCompareEflR32R32[iFn].paTests;
6729	PFNIEMAIMPLF2EFLMXCSR128 pfn = g_aSseCompareEflR32R32[iFn].pfn;
6730	uint32_t const cVars = COUNT_VARIATIONS(g_aSseCompareEflR32R32[iFn]);
6731	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6732	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6733	{
6734	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_COMPARE_EFL_R32_R32_TEST_T); iTest++)
6735	{
6736	X86XMMREG ValIn1; RT_ZERO(ValIn1);
6737	X86XMMREG ValIn2; RT_ZERO(ValIn2);
6738
6739	ValIn1.ar32[0] = paTests[iTest].r32ValIn1;
6740	ValIn2.ar32[0] = paTests[iTest].r32ValIn2;
6741	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
6742	uint32_t fEFlags = paTests[iTest].fEflIn;
6743	pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);
6744	if ( fMxcsr != paTests[iTest].fMxcsrOut
6745	\|\| fEFlags != paTests[iTest].fEflOut)
6746	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x efl=%#08x in1=%s in2=%s\n"
6747	"%s -> mxcsr=%#08x %#08x\n"
6748	"%s expected %#08x %#08x%s (%s) (EFL: %s)\n",
6749	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn, paTests[iTest].fEflIn,
6750	FormatR32(&paTests[iTest].r32ValIn1), FormatR32(&paTests[iTest].r32ValIn2),
6751	iVar ? " " : "", fMxcsr, fEFlags,
6752	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].fEflOut,
6753	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6754	FormatMxcsr(paTests[iTest].fMxcsrIn),
6755	EFlagsDiff(fEFlags, paTests[iTest].fEflOut));
6756	}
6757	}
6758	}
6759	}
6760
6761
6762	/*
6763	* Compare SSE operations on single single-precision floating point values - outputting only EFLAGS.
6764	*/
6765	TYPEDEF_SUBTEST_TYPE(SSE_COMPARE_EFL_R64_R64_T, SSE_COMPARE_EFL_R64_R64_TEST_T, PFNIEMAIMPLF2EFLMXCSR128);
6766
6767	static const SSE_COMPARE_EFL_R64_R64_T g_aSseCompareEflR64R64[] =
6768	{
6769	ENTRY_BIN(ucomisd_u128),
6770	ENTRY_BIN(comisd_u128),
6771	ENTRY_BIN_AVX(vucomisd_u128),
6772	ENTRY_BIN_AVX(vcomisd_u128)
6773	};
6774
6775	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6776	static RTEXITCODE SseCompareEflR64R64Generate(const char *pszDataFileFmt, uint32_t cTests)
6777	{
6778	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6779
6780	static struct { RTFLOAT64U Val1, Val2; } const s_aSpecials[] =
6781	{
6782	{ RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) },
6783	{ RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(1) },
6784	{ RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(0) },
6785	{ RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(1) },
6786	{ RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(0) },
6787	{ RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(1) },
6788	{ RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(0) },
6789	{ RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(1) },
6790	/** @todo More specials. */
6791	};
6792
6793	uint32_t cMinNormalPairs = (cTests - 144) / 4;
6794	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareEflR64R64); iFn++)
6795	{
6796	PFNIEMAIMPLF2EFLMXCSR128 const pfn = g_aSseCompareEflR64R64[iFn].pfnNative ? g_aSseCompareEflR64R64[iFn].pfnNative : g_aSseCompareEflR64R64[iFn].pfn;
6797
6798	PRTSTREAM pStrmOut = NULL;
6799	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseCompareEflR64R64[iFn].pszName);
6800	if (RT_FAILURE(rc))
6801	{
6802	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseCompareEflR64R64[iFn].pszName, rc);
6803	return RTEXITCODE_FAILURE;
6804	}
6805
6806	uint32_t cNormalInputPairs = 0;
6807	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
6808	{
6809	SSE_COMPARE_EFL_R64_R64_TEST_T TestData; RT_ZERO(TestData);
6810	X86XMMREG ValIn1; RT_ZERO(ValIn1);
6811	X86XMMREG ValIn2; RT_ZERO(ValIn2);
6812
6813	TestData.r64ValIn1 = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val1;
6814	TestData.r64ValIn2 = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val2;
6815
6816	ValIn1.ar64[0] = TestData.r64ValIn1;
6817	ValIn2.ar64[0] = TestData.r64ValIn2;
6818
6819	if ( RTFLOAT64U_IS_NORMAL(&TestData.r64ValIn1)
6820	&& RTFLOAT64U_IS_NORMAL(&TestData.r64ValIn2))
6821	cNormalInputPairs++;
6822	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
6823	{
6824	iTest -= 1;
6825	continue;
6826	}
6827
6828	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
6829	uint32_t const fEFlags = RandEFlags();
6830	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
6831	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
6832	for (uint8_t iFz = 0; iFz < 2; iFz++)
6833	{
6834	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
6835	\| (iRounding << X86_MXCSR_RC_SHIFT)
6836	\| (iDaz ? X86_MXCSR_DAZ : 0)
6837	\| (iFz ? X86_MXCSR_FZ : 0)
6838	\| X86_MXCSR_XCPT_MASK;
6839	uint32_t fMxcsrM = fMxcsrIn;
6840	uint32_t fEFlagsM = fEFlags;
6841	pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);
6842	TestData.fMxcsrIn = fMxcsrIn;
6843	TestData.fMxcsrOut = fMxcsrM;
6844	TestData.fEflIn = fEFlags;
6845	TestData.fEflOut = fEFlagsM;
6846	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6847
6848	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
6849	uint32_t fMxcsrU = fMxcsrIn;
6850	uint32_t fEFlagsU = fEFlags;
6851	pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);
6852	TestData.fMxcsrIn = fMxcsrIn;
6853	TestData.fMxcsrOut = fMxcsrU;
6854	TestData.fEflIn = fEFlags;
6855	TestData.fEflOut = fEFlagsU;
6856	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6857
6858	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
6859	if (fXcpt)
6860	{
6861	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
6862	uint32_t fMxcsr1 = fMxcsrIn;
6863	uint32_t fEFlags1 = fEFlags;
6864	pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);
6865	TestData.fMxcsrIn = fMxcsrIn;
6866	TestData.fMxcsrOut = fMxcsr1;
6867	TestData.fEflIn = fEFlags;
6868	TestData.fEflOut = fEFlags1;
6869	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6870
6871	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
6872	{
6873	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
6874	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
6875	uint32_t fMxcsr2 = fMxcsrIn;
6876	uint32_t fEFlags2 = fEFlags;
6877	pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);
6878	TestData.fMxcsrIn = fMxcsrIn;
6879	TestData.fMxcsrOut = fMxcsr2;
6880	TestData.fEflIn = fEFlags;
6881	TestData.fEflOut = fEFlags2;
6882	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6883	}
6884	if (!RT_IS_POWER_OF_TWO(fXcpt))
6885	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
6886	if (fUnmasked & fXcpt)
6887	{
6888	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
6889	uint32_t fMxcsr3 = fMxcsrIn;
6890	uint32_t fEFlags3 = fEFlags;
6891	pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);
6892	TestData.fMxcsrIn = fMxcsrIn;
6893	TestData.fMxcsrOut = fMxcsr3;
6894	TestData.fEflIn = fEFlags;
6895	TestData.fEflOut = fEFlags3;
6896	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
6897	}
6898	}
6899	}
6900	}
6901	rc = RTStrmClose(pStrmOut);
6902	if (RT_FAILURE(rc))
6903	{
6904	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseCompareEflR64R64[iFn].pszName, rc);
6905	return RTEXITCODE_FAILURE;
6906	}
6907	}
6908
6909	return RTEXITCODE_SUCCESS;
6910	}
6911	#endif
6912
6913	static void SseCompareEflR64R64Test(void)
6914	{
6915	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareEflR64R64); iFn++)
6916	{
6917	if (!SubTestAndCheckIfEnabled(g_aSseCompareEflR64R64[iFn].pszName))
6918	continue;
6919
6920	uint32_t const cTests = *g_aSseCompareEflR64R64[iFn].pcTests;
6921	SSE_COMPARE_EFL_R64_R64_TEST_T const * const paTests = g_aSseCompareEflR64R64[iFn].paTests;
6922	PFNIEMAIMPLF2EFLMXCSR128 pfn = g_aSseCompareEflR64R64[iFn].pfn;
6923	uint32_t const cVars = COUNT_VARIATIONS(g_aSseCompareEflR64R64[iFn]);
6924	if (!cTests) RTTestSkipped(g_hTest, "no tests");
6925	for (uint32_t iVar = 0; iVar < cVars; iVar++)
6926	{
6927	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_COMPARE_EFL_R64_R64_TEST_T); iTest++)
6928	{
6929	X86XMMREG ValIn1; RT_ZERO(ValIn1);
6930	X86XMMREG ValIn2; RT_ZERO(ValIn2);
6931
6932	ValIn1.ar64[0] = paTests[iTest].r64ValIn1;
6933	ValIn2.ar64[0] = paTests[iTest].r64ValIn2;
6934	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
6935	uint32_t fEFlags = paTests[iTest].fEflIn;
6936	pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);
6937	if ( fMxcsr != paTests[iTest].fMxcsrOut
6938	\|\| fEFlags != paTests[iTest].fEflOut)
6939	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x efl=%#08x in1=%s in2=%s\n"
6940	"%s -> mxcsr=%#08x %#08x\n"
6941	"%s expected %#08x %#08x%s (%s) (EFL: %s)\n",
6942	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn, paTests[iTest].fEflIn,
6943	FormatR64(&paTests[iTest].r64ValIn1), FormatR64(&paTests[iTest].r64ValIn2),
6944	iVar ? " " : "", fMxcsr, fEFlags,
6945	iVar ? " " : "", paTests[iTest].fMxcsrOut, paTests[iTest].fEflOut,
6946	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
6947	FormatMxcsr(paTests[iTest].fMxcsrIn),
6948	EFlagsDiff(fEFlags, paTests[iTest].fEflOut));
6949	}
6950	}
6951	}
6952	}
6953
6954
6955	/*
6956	* Compare SSE operations on packed and single single-precision floating point values - outputting a mask.
6957	*/
6958	/** Maximum immediate to try to keep the testdata size under control (at least a little bit)- */
6959	#define SSE_COMPARE_F2_XMM_IMM8_MAX 0x1f
6960
6961	TYPEDEF_SUBTEST_TYPE(SSE_COMPARE_F2_XMM_IMM8_T, SSE_COMPARE_F2_XMM_IMM8_TEST_T, PFNIEMAIMPLMXCSRF2XMMIMM8);
6962
6963	static const SSE_COMPARE_F2_XMM_IMM8_T g_aSseCompareF2XmmR32Imm8[] =
6964	{
6965	ENTRY_BIN(cmpps_u128),
6966	ENTRY_BIN(cmpss_u128)
6967	};
6968
6969	#ifdef TSTIEMAIMPL_WITH_GENERATOR
6970	static RTEXITCODE SseCompareF2XmmR32Imm8Generate(const char *pszDataFileFmt, uint32_t cTests)
6971	{
6972	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
6973
6974	static struct { RTFLOAT32U Val1, Val2; } const s_aSpecials[] =
6975	{
6976	{ RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0) },
6977	{ RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(1) },
6978	{ RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(0) },
6979	{ RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(1) },
6980	{ RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(0) },
6981	{ RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(1) },
6982	{ RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(0) },
6983	{ RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(1) },
6984	/** @todo More specials. */
6985	};
6986
6987	uint32_t cMinNormalPairs = (cTests - 144) / 4;
6988	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareF2XmmR32Imm8); iFn++)
6989	{
6990	PFNIEMAIMPLMXCSRF2XMMIMM8 const pfn = g_aSseCompareF2XmmR32Imm8[iFn].pfnNative ? g_aSseCompareF2XmmR32Imm8[iFn].pfnNative : g_aSseCompareF2XmmR32Imm8[iFn].pfn;
6991
6992	PRTSTREAM pStrmOut = NULL;
6993	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseCompareF2XmmR32Imm8[iFn].pszName);
6994	if (RT_FAILURE(rc))
6995	{
6996	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseCompareF2XmmR32Imm8[iFn].pszName, rc);
6997	return RTEXITCODE_FAILURE;
6998	}
6999
7000	uint32_t cNormalInputPairs = 0;
7001	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7002	{
7003	SSE_COMPARE_F2_XMM_IMM8_TEST_T TestData; RT_ZERO(TestData);
7004
7005	TestData.InVal1.ar32[0] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7006	TestData.InVal1.ar32[1] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7007	TestData.InVal1.ar32[2] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7008	TestData.InVal1.ar32[3] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7009
7010	TestData.InVal2.ar32[0] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7011	TestData.InVal2.ar32[1] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7012	TestData.InVal2.ar32[2] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7013	TestData.InVal2.ar32[3] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7014
7015	if ( RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[0])
7016	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[1])
7017	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[2])
7018	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal1.ar32[3])
7019	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[0])
7020	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[1])
7021	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[2])
7022	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal2.ar32[3]))
7023	cNormalInputPairs++;
7024	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
7025	{
7026	iTest -= 1;
7027	continue;
7028	}
7029
7030	IEMMEDIAF2XMMSRC Src;
7031	Src.uSrc1 = TestData.InVal1;
7032	Src.uSrc2 = TestData.InVal2;
7033	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7034	for (uint8_t bImm = 0; bImm <= SSE_COMPARE_F2_XMM_IMM8_MAX; bImm++)
7035	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7036	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7037	for (uint8_t iFz = 0; iFz < 2; iFz++)
7038	{
7039	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
7040	\| (iRounding << X86_MXCSR_RC_SHIFT)
7041	\| (iDaz ? X86_MXCSR_DAZ : 0)
7042	\| (iFz ? X86_MXCSR_FZ : 0)
7043	\| X86_MXCSR_XCPT_MASK;
7044	uint32_t fMxcsrM = fMxcsrIn;
7045	X86XMMREG ResM;
7046	pfn(&fMxcsrM, &ResM, &Src, bImm);
7047	TestData.fMxcsrIn = fMxcsrIn;
7048	TestData.fMxcsrOut = fMxcsrM;
7049	TestData.bImm = bImm;
7050	TestData.OutVal = ResM;
7051	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7052
7053	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
7054	uint32_t fMxcsrU = fMxcsrIn;
7055	X86XMMREG ResU;
7056	pfn(&fMxcsrU, &ResU, &Src, bImm);
7057	TestData.fMxcsrIn = fMxcsrIn;
7058	TestData.fMxcsrOut = fMxcsrU;
7059	TestData.bImm = bImm;
7060	TestData.OutVal = ResU;
7061	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7062
7063	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
7064	if (fXcpt)
7065	{
7066	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7067	uint32_t fMxcsr1 = fMxcsrIn;
7068	X86XMMREG Res1;
7069	pfn(&fMxcsr1, &Res1, &Src, bImm);
7070	TestData.fMxcsrIn = fMxcsrIn;
7071	TestData.fMxcsrOut = fMxcsr1;
7072	TestData.bImm = bImm;
7073	TestData.OutVal = Res1;
7074	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7075
7076	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
7077	{
7078	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
7079	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7080	uint32_t fMxcsr2 = fMxcsrIn;
7081	X86XMMREG Res2;
7082	pfn(&fMxcsr2, &Res2, &Src, bImm);
7083	TestData.fMxcsrIn = fMxcsrIn;
7084	TestData.fMxcsrOut = fMxcsr2;
7085	TestData.bImm = bImm;
7086	TestData.OutVal = Res2;
7087	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7088	}
7089	if (!RT_IS_POWER_OF_TWO(fXcpt))
7090	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
7091	if (fUnmasked & fXcpt)
7092	{
7093	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
7094	uint32_t fMxcsr3 = fMxcsrIn;
7095	X86XMMREG Res3;
7096	pfn(&fMxcsr3, &Res3, &Src, bImm);
7097	TestData.fMxcsrIn = fMxcsrIn;
7098	TestData.fMxcsrOut = fMxcsr3;
7099	TestData.bImm = bImm;
7100	TestData.OutVal = Res3;
7101	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7102	}
7103	}
7104	}
7105	}
7106	rc = RTStrmClose(pStrmOut);
7107	if (RT_FAILURE(rc))
7108	{
7109	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseCompareF2XmmR32Imm8[iFn].pszName, rc);
7110	return RTEXITCODE_FAILURE;
7111	}
7112	}
7113
7114	return RTEXITCODE_SUCCESS;
7115	}
7116	#endif
7117
7118	static void SseCompareF2XmmR32Imm8Test(void)
7119	{
7120	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareF2XmmR32Imm8); iFn++)
7121	{
7122	if (!SubTestAndCheckIfEnabled(g_aSseCompareF2XmmR32Imm8[iFn].pszName))
7123	continue;
7124
7125	uint32_t const cTests = *g_aSseCompareF2XmmR32Imm8[iFn].pcTests;
7126	SSE_COMPARE_F2_XMM_IMM8_TEST_T const * const paTests = g_aSseCompareF2XmmR32Imm8[iFn].paTests;
7127	PFNIEMAIMPLMXCSRF2XMMIMM8 pfn = g_aSseCompareF2XmmR32Imm8[iFn].pfn;
7128	uint32_t const cVars = COUNT_VARIATIONS(g_aSseCompareF2XmmR32Imm8[iFn]);
7129	if (!cTests) RTTestSkipped(g_hTest, "no tests");
7130	for (uint32_t iVar = 0; iVar < cVars; iVar++)
7131	{
7132	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_COMPARE_F2_XMM_IMM8_TEST_T); iTest++)
7133	{
7134	IEMMEDIAF2XMMSRC Src;
7135	X86XMMREG ValOut;
7136
7137	Src.uSrc1 = paTests[iTest].InVal1;
7138	Src.uSrc2 = paTests[iTest].InVal2;
7139	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
7140	pfn(&fMxcsr, &ValOut, &Src, paTests[iTest].bImm);
7141	if ( fMxcsr != paTests[iTest].fMxcsrOut
7142	\|\| ValOut.au32[0] != paTests[iTest].OutVal.au32[0]
7143	\|\| ValOut.au32[1] != paTests[iTest].OutVal.au32[1]
7144	\|\| ValOut.au32[2] != paTests[iTest].OutVal.au32[2]
7145	\|\| ValOut.au32[3] != paTests[iTest].OutVal.au32[3])
7146	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s'%s'%s'%s imm8=%x\n"
7147	"%s -> mxcsr=%#08x %RX32'%RX32'%RX32'%RX32\n"
7148	"%s expected %#08x %RX32'%RX32'%RX32'%RX32%s%s (%s)\n",
7149	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
7150	FormatR32(&paTests[iTest].InVal1.ar32[0]), FormatR32(&paTests[iTest].InVal1.ar32[1]),
7151	FormatR32(&paTests[iTest].InVal1.ar32[2]), FormatR32(&paTests[iTest].InVal1.ar32[3]),
7152	FormatR32(&paTests[iTest].InVal2.ar32[0]), FormatR32(&paTests[iTest].InVal2.ar32[1]),
7153	FormatR32(&paTests[iTest].InVal2.ar32[2]), FormatR32(&paTests[iTest].InVal2.ar32[3]),
7154	paTests[iTest].bImm,
7155	iVar ? " " : "", fMxcsr, ValOut.au32[0], ValOut.au32[1], ValOut.au32[2], ValOut.au32[3],
7156	iVar ? " " : "", paTests[iTest].fMxcsrOut,
7157	paTests[iTest].OutVal.au32[0], paTests[iTest].OutVal.au32[1],
7158	paTests[iTest].OutVal.au32[2], paTests[iTest].OutVal.au32[3],
7159	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
7160	( ValOut.au32[0] != paTests[iTest].OutVal.au32[0]
7161	\|\| ValOut.au32[1] != paTests[iTest].OutVal.au32[1]
7162	\|\| ValOut.au32[2] != paTests[iTest].OutVal.au32[2]
7163	\|\| ValOut.au32[3] != paTests[iTest].OutVal.au32[3])
7164	? " - val" : "",
7165	FormatMxcsr(paTests[iTest].fMxcsrIn));
7166	}
7167	}
7168	}
7169	}
7170
7171
7172	/*
7173	* Compare SSE operations on packed and single double-precision floating point values - outputting a mask.
7174	*/
7175	static const SSE_COMPARE_F2_XMM_IMM8_T g_aSseCompareF2XmmR64Imm8[] =
7176	{
7177	ENTRY_BIN(cmppd_u128),
7178	ENTRY_BIN(cmpsd_u128)
7179	};
7180
7181	#ifdef TSTIEMAIMPL_WITH_GENERATOR
7182	static RTEXITCODE SseCompareF2XmmR64Imm8Generate(const char *pszDataFileFmt, uint32_t cTests)
7183	{
7184	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
7185
7186	static struct { RTFLOAT64U Val1, Val2; } const s_aSpecials[] =
7187	{
7188	{ RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) },
7189	{ RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(1) },
7190	{ RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(0) },
7191	{ RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(1) },
7192	{ RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(0) },
7193	{ RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(1) },
7194	{ RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(0) },
7195	{ RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(1) },
7196	/** @todo More specials. */
7197	};
7198
7199	uint32_t cMinNormalPairs = (cTests - 144) / 4;
7200	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareF2XmmR64Imm8); iFn++)
7201	{
7202	PFNIEMAIMPLMXCSRF2XMMIMM8 const pfn = g_aSseCompareF2XmmR64Imm8[iFn].pfnNative ? g_aSseCompareF2XmmR64Imm8[iFn].pfnNative : g_aSseCompareF2XmmR64Imm8[iFn].pfn;
7203
7204	PRTSTREAM pStrmOut = NULL;
7205	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseCompareF2XmmR64Imm8[iFn].pszName);
7206	if (RT_FAILURE(rc))
7207	{
7208	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseCompareF2XmmR64Imm8[iFn].pszName, rc);
7209	return RTEXITCODE_FAILURE;
7210	}
7211
7212	uint32_t cNormalInputPairs = 0;
7213	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7214	{
7215	SSE_COMPARE_F2_XMM_IMM8_TEST_T TestData; RT_ZERO(TestData);
7216
7217	TestData.InVal1.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7218	TestData.InVal1.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val1;
7219
7220	TestData.InVal2.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7221	TestData.InVal2.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].Val2;
7222
7223	if ( RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[0])
7224	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal1.ar64[1])
7225	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal2.ar64[0])
7226	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal2.ar64[1]))
7227	cNormalInputPairs++;
7228	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
7229	{
7230	iTest -= 1;
7231	continue;
7232	}
7233
7234	IEMMEDIAF2XMMSRC Src;
7235	Src.uSrc1 = TestData.InVal1;
7236	Src.uSrc2 = TestData.InVal2;
7237	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7238	for (uint8_t bImm = 0; bImm <= SSE_COMPARE_F2_XMM_IMM8_MAX; bImm++)
7239	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7240	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7241	for (uint8_t iFz = 0; iFz < 2; iFz++)
7242	{
7243	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
7244	\| (iRounding << X86_MXCSR_RC_SHIFT)
7245	\| (iDaz ? X86_MXCSR_DAZ : 0)
7246	\| (iFz ? X86_MXCSR_FZ : 0)
7247	\| X86_MXCSR_XCPT_MASK;
7248	uint32_t fMxcsrM = fMxcsrIn;
7249	X86XMMREG ResM;
7250	pfn(&fMxcsrM, &ResM, &Src, bImm);
7251	TestData.fMxcsrIn = fMxcsrIn;
7252	TestData.fMxcsrOut = fMxcsrM;
7253	TestData.bImm = bImm;
7254	TestData.OutVal = ResM;
7255	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7256
7257	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
7258	uint32_t fMxcsrU = fMxcsrIn;
7259	X86XMMREG ResU;
7260	pfn(&fMxcsrU, &ResU, &Src, bImm);
7261	TestData.fMxcsrIn = fMxcsrIn;
7262	TestData.fMxcsrOut = fMxcsrU;
7263	TestData.bImm = bImm;
7264	TestData.OutVal = ResU;
7265	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7266
7267	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
7268	if (fXcpt)
7269	{
7270	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7271	uint32_t fMxcsr1 = fMxcsrIn;
7272	X86XMMREG Res1;
7273	pfn(&fMxcsr1, &Res1, &Src, bImm);
7274	TestData.fMxcsrIn = fMxcsrIn;
7275	TestData.fMxcsrOut = fMxcsr1;
7276	TestData.bImm = bImm;
7277	TestData.OutVal = Res1;
7278	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7279
7280	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
7281	{
7282	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
7283	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7284	uint32_t fMxcsr2 = fMxcsrIn;
7285	X86XMMREG Res2;
7286	pfn(&fMxcsr2, &Res2, &Src, bImm);
7287	TestData.fMxcsrIn = fMxcsrIn;
7288	TestData.fMxcsrOut = fMxcsr2;
7289	TestData.bImm = bImm;
7290	TestData.OutVal = Res2;
7291	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7292	}
7293	if (!RT_IS_POWER_OF_TWO(fXcpt))
7294	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
7295	if (fUnmasked & fXcpt)
7296	{
7297	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
7298	uint32_t fMxcsr3 = fMxcsrIn;
7299	X86XMMREG Res3;
7300	pfn(&fMxcsr3, &Res3, &Src, bImm);
7301	TestData.fMxcsrIn = fMxcsrIn;
7302	TestData.fMxcsrOut = fMxcsr3;
7303	TestData.bImm = bImm;
7304	TestData.OutVal = Res3;
7305	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7306	}
7307	}
7308	}
7309	}
7310	rc = RTStrmClose(pStrmOut);
7311	if (RT_FAILURE(rc))
7312	{
7313	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseCompareF2XmmR64Imm8[iFn].pszName, rc);
7314	return RTEXITCODE_FAILURE;
7315	}
7316	}
7317
7318	return RTEXITCODE_SUCCESS;
7319	}
7320	#endif
7321
7322	static void SseCompareF2XmmR64Imm8Test(void)
7323	{
7324	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseCompareF2XmmR64Imm8); iFn++)
7325	{
7326	if (!SubTestAndCheckIfEnabled(g_aSseCompareF2XmmR64Imm8[iFn].pszName))
7327	continue;
7328
7329	uint32_t const cTests = *g_aSseCompareF2XmmR64Imm8[iFn].pcTests;
7330	SSE_COMPARE_F2_XMM_IMM8_TEST_T const * const paTests = g_aSseCompareF2XmmR64Imm8[iFn].paTests;
7331	PFNIEMAIMPLMXCSRF2XMMIMM8 pfn = g_aSseCompareF2XmmR64Imm8[iFn].pfn;
7332	uint32_t const cVars = COUNT_VARIATIONS(g_aSseCompareF2XmmR64Imm8[iFn]);
7333	if (!cTests) RTTestSkipped(g_hTest, "no tests");
7334	for (uint32_t iVar = 0; iVar < cVars; iVar++)
7335	{
7336	for (uint32_t iTest = 0; iTest < cTests / sizeof(SSE_COMPARE_F2_XMM_IMM8_TEST_T); iTest++)
7337	{
7338	IEMMEDIAF2XMMSRC Src;
7339	X86XMMREG ValOut;
7340
7341	Src.uSrc1 = paTests[iTest].InVal1;
7342	Src.uSrc2 = paTests[iTest].InVal2;
7343	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
7344	pfn(&fMxcsr, &ValOut, &Src, paTests[iTest].bImm);
7345	if ( fMxcsr != paTests[iTest].fMxcsrOut
7346	\|\| ValOut.au64[0] != paTests[iTest].OutVal.au64[0]
7347	\|\| ValOut.au64[1] != paTests[iTest].OutVal.au64[1])
7348	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s'%s imm8=%x\n"
7349	"%s -> mxcsr=%#08x %RX64'%RX64\n"
7350	"%s expected %#08x %RX64'%RX64%s%s (%s)\n",
7351	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
7352	FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]),
7353	FormatR64(&paTests[iTest].InVal2.ar64[0]), FormatR64(&paTests[iTest].InVal2.ar64[1]),
7354	paTests[iTest].bImm,
7355	iVar ? " " : "", fMxcsr, ValOut.au64[0], ValOut.au64[1],
7356	iVar ? " " : "", paTests[iTest].fMxcsrOut,
7357	paTests[iTest].OutVal.au64[0], paTests[iTest].OutVal.au64[1],
7358	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
7359	( ValOut.au64[0] != paTests[iTest].OutVal.au64[0]
7360	\|\| ValOut.au64[1] != paTests[iTest].OutVal.au64[1])
7361	? " - val" : "",
7362	FormatMxcsr(paTests[iTest].fMxcsrIn));
7363	}
7364	}
7365	}
7366	}
7367
7368
7369	/*
7370	* Convert SSE operations converting signed double-words to single-precision floating point values.
7371	*/
7372	TYPEDEF_SUBTEST_TYPE(SSE_CONVERT_XMM_T, SSE_CONVERT_XMM_TEST_T, PFNIEMAIMPLFPSSEF2U128);
7373
7374	static const SSE_CONVERT_XMM_T g_aSseConvertXmmI32R32[] =
7375	{
7376	ENTRY_BIN(cvtdq2ps_u128)
7377	};
7378
7379	#ifdef TSTIEMAIMPL_WITH_GENERATOR
7380	static RTEXITCODE SseConvertXmmI32R32Generate(const char *pszDataFileFmt, uint32_t cTests)
7381	{
7382	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
7383
7384	static int32_t const s_aSpecials[] =
7385	{
7386	INT32_MIN,
7387	INT32_MIN / 2,
7388	0,
7389	INT32_MAX / 2,
7390	INT32_MAX,
7391	(int32_t)0x80000000
7392	/** @todo More specials. */
7393	};
7394
7395	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R32); iFn++)
7396	{
7397	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseConvertXmmI32R32[iFn].pfnNative ? g_aSseConvertXmmI32R32[iFn].pfnNative : g_aSseConvertXmmI32R32[iFn].pfn;
7398
7399	PRTSTREAM pStrmOut = NULL;
7400	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmI32R32[iFn].pszName);
7401	if (RT_FAILURE(rc))
7402	{
7403	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmI32R32[iFn].pszName, rc);
7404	return RTEXITCODE_FAILURE;
7405	}
7406
7407	X86FXSTATE State;
7408	RT_ZERO(State);
7409	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7410	{
7411	SSE_CONVERT_XMM_TEST_T TestData; RT_ZERO(TestData);
7412
7413	TestData.InVal.ai32[0] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7414	TestData.InVal.ai32[1] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7415	TestData.InVal.ai32[2] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7416	TestData.InVal.ai32[3] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7417
7418	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7419	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7420	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7421	for (uint8_t iFz = 0; iFz < 2; iFz++)
7422	{
7423	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
7424	\| (iRounding << X86_MXCSR_RC_SHIFT)
7425	\| (iDaz ? X86_MXCSR_DAZ : 0)
7426	\| (iFz ? X86_MXCSR_FZ : 0)
7427	\| X86_MXCSR_XCPT_MASK;
7428	IEMSSERESULT ResM; RT_ZERO(ResM);
7429	pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
7430	TestData.fMxcsrIn = State.MXCSR;
7431	TestData.fMxcsrOut = ResM.MXCSR;
7432	TestData.OutVal = ResM.uResult;
7433	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7434
7435	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
7436	IEMSSERESULT ResU; RT_ZERO(ResU);
7437	pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
7438	TestData.fMxcsrIn = State.MXCSR;
7439	TestData.fMxcsrOut = ResU.MXCSR;
7440	TestData.OutVal = ResU.uResult;
7441	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7442
7443	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
7444	if (fXcpt)
7445	{
7446	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7447	IEMSSERESULT Res1; RT_ZERO(Res1);
7448	pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
7449	TestData.fMxcsrIn = State.MXCSR;
7450	TestData.fMxcsrOut = Res1.MXCSR;
7451	TestData.OutVal = Res1.uResult;
7452	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7453
7454	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
7455	{
7456	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
7457	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7458	IEMSSERESULT Res2; RT_ZERO(Res2);
7459	pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
7460	TestData.fMxcsrIn = State.MXCSR;
7461	TestData.fMxcsrOut = Res2.MXCSR;
7462	TestData.OutVal = Res2.uResult;
7463	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7464	}
7465	if (!RT_IS_POWER_OF_TWO(fXcpt))
7466	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
7467	if (fUnmasked & fXcpt)
7468	{
7469	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
7470	IEMSSERESULT Res3; RT_ZERO(Res3);
7471	pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
7472	TestData.fMxcsrIn = State.MXCSR;
7473	TestData.fMxcsrOut = Res3.MXCSR;
7474	TestData.OutVal = Res3.uResult;
7475	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7476	}
7477	}
7478	}
7479	}
7480	rc = RTStrmClose(pStrmOut);
7481	if (RT_FAILURE(rc))
7482	{
7483	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmI32R32[iFn].pszName, rc);
7484	return RTEXITCODE_FAILURE;
7485	}
7486	}
7487
7488	return RTEXITCODE_SUCCESS;
7489	}
7490	#endif
7491
7492	static void SseConvertXmmI32R32Test(void)
7493	{
7494	X86FXSTATE State;
7495	RT_ZERO(State);
7496
7497	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R32); iFn++)
7498	{
7499	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmI32R32[iFn].pszName))
7500	continue;
7501
7502	uint32_t const cTests = *g_aSseConvertXmmI32R32[iFn].pcTests;
7503	SSE_CONVERT_XMM_TEST_T const * const paTests = g_aSseConvertXmmI32R32[iFn].paTests;
7504	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseConvertXmmI32R32[iFn].pfn;
7505	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmI32R32[iFn]);
7506	if (!cTests) RTTestSkipped(g_hTest, "no tests");
7507	for (uint32_t iVar = 0; iVar < cVars; iVar++)
7508	{
7509	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
7510	{
7511	IEMSSERESULT Res; RT_ZERO(Res);
7512
7513	State.MXCSR = paTests[iTest].fMxcsrIn;
7514	pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
7515	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
7516	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
7517	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
7518	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
7519	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]))
7520	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n"
7521	"%s -> mxcsr=%#08x %s'%s'%s'%s\n"
7522	"%s expected %#08x %s'%s'%s'%s%s%s (%s)\n",
7523	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
7524	paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
7525	paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3],
7526	iVar ? " " : "", Res.MXCSR,
7527	FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
7528	FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
7529	iVar ? " " : "", paTests[iTest].fMxcsrOut,
7530	FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
7531	FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
7532	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
7533	( !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
7534	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
7535	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
7536	\|\| !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]))
7537	? " - val" : "",
7538	FormatMxcsr(paTests[iTest].fMxcsrIn));
7539	}
7540	}
7541	}
7542	}
7543
7544
7545	/*
7546	* Convert SSE operations converting signed double-words to single-precision floating point values.
7547	*/
7548	static const SSE_CONVERT_XMM_T g_aSseConvertXmmR32I32[] =
7549	{
7550	ENTRY_BIN(cvtps2dq_u128),
7551	ENTRY_BIN(cvttps2dq_u128)
7552	};
7553
7554	#ifdef TSTIEMAIMPL_WITH_GENERATOR
7555	static RTEXITCODE SseConvertXmmR32I32Generate(const char *pszDataFileFmt, uint32_t cTests)
7556	{
7557	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
7558
7559	static struct { RTFLOAT32U aVal1[4]; } const s_aSpecials[] =
7560	{
7561	{ { RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0), RTFLOAT32U_INIT_ZERO(0) } },
7562	{ { RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(1), RTFLOAT32U_INIT_ZERO(1) } },
7563	{ { RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(0) } },
7564	{ { RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(1), RTFLOAT32U_INIT_INF(1) } }
7565	/** @todo More specials. */
7566	};
7567
7568	X86FXSTATE State;
7569	RT_ZERO(State);
7570	uint32_t cMinNormalPairs = (cTests - 144) / 4;
7571	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++)
7572	{
7573	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseConvertXmmR32I32[iFn].pfnNative ? g_aSseConvertXmmR32I32[iFn].pfnNative : g_aSseConvertXmmR32I32[iFn].pfn;
7574
7575	PRTSTREAM pStrmOut = NULL;
7576	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmR32I32[iFn].pszName);
7577	if (RT_FAILURE(rc))
7578	{
7579	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmR32I32[iFn].pszName, rc);
7580	return RTEXITCODE_FAILURE;
7581	}
7582
7583	uint32_t cNormalInputPairs = 0;
7584	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7585	{
7586	SSE_CONVERT_XMM_TEST_T TestData; RT_ZERO(TestData);
7587
7588	TestData.InVal.ar32[0] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
7589	TestData.InVal.ar32[1] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
7590	TestData.InVal.ar32[2] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[2];
7591	TestData.InVal.ar32[3] = iTest < cTests ? RandR32Src(iTest) : s_aSpecials[iTest - cTests].aVal1[3];
7592
7593	if ( RTFLOAT32U_IS_NORMAL(&TestData.InVal.ar32[0])
7594	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal.ar32[1])
7595	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal.ar32[2])
7596	&& RTFLOAT32U_IS_NORMAL(&TestData.InVal.ar32[3]))
7597	cNormalInputPairs++;
7598	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
7599	{
7600	iTest -= 1;
7601	continue;
7602	}
7603
7604	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7605	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7606	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7607	for (uint8_t iFz = 0; iFz < 2; iFz++)
7608	{
7609	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
7610	\| (iRounding << X86_MXCSR_RC_SHIFT)
7611	\| (iDaz ? X86_MXCSR_DAZ : 0)
7612	\| (iFz ? X86_MXCSR_FZ : 0)
7613	\| X86_MXCSR_XCPT_MASK;
7614	IEMSSERESULT ResM; RT_ZERO(ResM);
7615	pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
7616	TestData.fMxcsrIn = State.MXCSR;
7617	TestData.fMxcsrOut = ResM.MXCSR;
7618	TestData.OutVal = ResM.uResult;
7619	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7620
7621	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
7622	IEMSSERESULT ResU; RT_ZERO(ResU);
7623	pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
7624	TestData.fMxcsrIn = State.MXCSR;
7625	TestData.fMxcsrOut = ResU.MXCSR;
7626	TestData.OutVal = ResU.uResult;
7627	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7628
7629	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
7630	if (fXcpt)
7631	{
7632	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7633	IEMSSERESULT Res1; RT_ZERO(Res1);
7634	pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
7635	TestData.fMxcsrIn = State.MXCSR;
7636	TestData.fMxcsrOut = Res1.MXCSR;
7637	TestData.OutVal = Res1.uResult;
7638	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7639
7640	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
7641	{
7642	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
7643	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7644	IEMSSERESULT Res2; RT_ZERO(Res2);
7645	pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
7646	TestData.fMxcsrIn = State.MXCSR;
7647	TestData.fMxcsrOut = Res2.MXCSR;
7648	TestData.OutVal = Res2.uResult;
7649	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7650	}
7651	if (!RT_IS_POWER_OF_TWO(fXcpt))
7652	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
7653	if (fUnmasked & fXcpt)
7654	{
7655	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
7656	IEMSSERESULT Res3; RT_ZERO(Res3);
7657	pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
7658	TestData.fMxcsrIn = State.MXCSR;
7659	TestData.fMxcsrOut = Res3.MXCSR;
7660	TestData.OutVal = Res3.uResult;
7661	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7662	}
7663	}
7664	}
7665	}
7666	rc = RTStrmClose(pStrmOut);
7667	if (RT_FAILURE(rc))
7668	{
7669	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmR32I32[iFn].pszName, rc);
7670	return RTEXITCODE_FAILURE;
7671	}
7672	}
7673
7674	return RTEXITCODE_SUCCESS;
7675	}
7676	#endif
7677
7678	static void SseConvertXmmR32I32Test(void)
7679	{
7680	X86FXSTATE State;
7681	RT_ZERO(State);
7682
7683	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++)
7684	{
7685	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmR32I32[iFn].pszName))
7686	continue;
7687
7688	uint32_t const cTests = *g_aSseConvertXmmR32I32[iFn].pcTests;
7689	SSE_CONVERT_XMM_TEST_T const * const paTests = g_aSseConvertXmmR32I32[iFn].paTests;
7690	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseConvertXmmR32I32[iFn].pfn;
7691	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmR32I32[iFn]);
7692	if (!cTests) RTTestSkipped(g_hTest, "no tests");
7693	for (uint32_t iVar = 0; iVar < cVars; iVar++)
7694	{
7695	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
7696	{
7697	IEMSSERESULT Res; RT_ZERO(Res);
7698
7699	State.MXCSR = paTests[iTest].fMxcsrIn;
7700	pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
7701	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
7702	\|\| Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
7703	\|\| Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
7704	\|\| Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
7705	\|\| Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
7706	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s \n"
7707	"%s -> mxcsr=%#08x %RI32'%RI32'%RI32'%RI32\n"
7708	"%s expected %#08x %RI32'%RI32'%RI32'%RI32%s%s (%s)\n",
7709	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
7710	FormatR32(&paTests[iTest].InVal.ar32[0]), FormatR32(&paTests[iTest].InVal.ar32[1]),
7711	FormatR32(&paTests[iTest].InVal.ar32[2]), FormatR32(&paTests[iTest].InVal.ar32[3]),
7712	iVar ? " " : "", Res.MXCSR,
7713	Res.uResult.ai32[0], Res.uResult.ai32[1],
7714	Res.uResult.ai32[2], Res.uResult.ai32[3],
7715	iVar ? " " : "", paTests[iTest].fMxcsrOut,
7716	paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1],
7717	paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3],
7718	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
7719	( Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
7720	\|\| Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
7721	\|\| Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
7722	\|\| Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
7723	? " - val" : "",
7724	FormatMxcsr(paTests[iTest].fMxcsrIn));
7725	}
7726	}
7727	}
7728	}
7729
7730
7731	/*
7732	* Convert SSE operations converting signed double-words to double-precision floating point values.
7733	*/
7734	static const SSE_CONVERT_XMM_T g_aSseConvertXmmI32R64[] =
7735	{
7736	ENTRY_BIN(cvtdq2pd_u128)
7737	};
7738
7739	#ifdef TSTIEMAIMPL_WITH_GENERATOR
7740	static RTEXITCODE SseConvertXmmI32R64Generate(const char *pszDataFileFmt, uint32_t cTests)
7741	{
7742	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
7743
7744	static int32_t const s_aSpecials[] =
7745	{
7746	INT32_MIN,
7747	INT32_MIN / 2,
7748	0,
7749	INT32_MAX / 2,
7750	INT32_MAX,
7751	(int32_t)0x80000000
7752	/** @todo More specials. */
7753	};
7754
7755	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R64); iFn++)
7756	{
7757	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseConvertXmmI32R64[iFn].pfnNative ? g_aSseConvertXmmI32R64[iFn].pfnNative : g_aSseConvertXmmI32R64[iFn].pfn;
7758
7759	PRTSTREAM pStrmOut = NULL;
7760	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmI32R64[iFn].pszName);
7761	if (RT_FAILURE(rc))
7762	{
7763	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmI32R64[iFn].pszName, rc);
7764	return RTEXITCODE_FAILURE;
7765	}
7766
7767	X86FXSTATE State;
7768	RT_ZERO(State);
7769	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7770	{
7771	SSE_CONVERT_XMM_TEST_T TestData; RT_ZERO(TestData);
7772
7773	TestData.InVal.ai32[0] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7774	TestData.InVal.ai32[1] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7775	TestData.InVal.ai32[2] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7776	TestData.InVal.ai32[3] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests];
7777
7778	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7779	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7780	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7781	for (uint8_t iFz = 0; iFz < 2; iFz++)
7782	{
7783	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
7784	\| (iRounding << X86_MXCSR_RC_SHIFT)
7785	\| (iDaz ? X86_MXCSR_DAZ : 0)
7786	\| (iFz ? X86_MXCSR_FZ : 0)
7787	\| X86_MXCSR_XCPT_MASK;
7788	IEMSSERESULT ResM; RT_ZERO(ResM);
7789	pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
7790	TestData.fMxcsrIn = State.MXCSR;
7791	TestData.fMxcsrOut = ResM.MXCSR;
7792	TestData.OutVal = ResM.uResult;
7793	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7794
7795	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
7796	IEMSSERESULT ResU; RT_ZERO(ResU);
7797	pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
7798	TestData.fMxcsrIn = State.MXCSR;
7799	TestData.fMxcsrOut = ResU.MXCSR;
7800	TestData.OutVal = ResU.uResult;
7801	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7802
7803	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
7804	if (fXcpt)
7805	{
7806	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7807	IEMSSERESULT Res1; RT_ZERO(Res1);
7808	pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
7809	TestData.fMxcsrIn = State.MXCSR;
7810	TestData.fMxcsrOut = Res1.MXCSR;
7811	TestData.OutVal = Res1.uResult;
7812	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7813
7814	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
7815	{
7816	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
7817	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7818	IEMSSERESULT Res2; RT_ZERO(Res2);
7819	pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
7820	TestData.fMxcsrIn = State.MXCSR;
7821	TestData.fMxcsrOut = Res2.MXCSR;
7822	TestData.OutVal = Res2.uResult;
7823	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7824	}
7825	if (!RT_IS_POWER_OF_TWO(fXcpt))
7826	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
7827	if (fUnmasked & fXcpt)
7828	{
7829	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
7830	IEMSSERESULT Res3; RT_ZERO(Res3);
7831	pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
7832	TestData.fMxcsrIn = State.MXCSR;
7833	TestData.fMxcsrOut = Res3.MXCSR;
7834	TestData.OutVal = Res3.uResult;
7835	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7836	}
7837	}
7838	}
7839	}
7840	rc = RTStrmClose(pStrmOut);
7841	if (RT_FAILURE(rc))
7842	{
7843	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmI32R64[iFn].pszName, rc);
7844	return RTEXITCODE_FAILURE;
7845	}
7846	}
7847
7848	return RTEXITCODE_SUCCESS;
7849	}
7850	#endif
7851
7852	static void SseConvertXmmI32R64Test(void)
7853	{
7854	X86FXSTATE State;
7855	RT_ZERO(State);
7856
7857	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R64); iFn++)
7858	{
7859	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmI32R64[iFn].pszName))
7860	continue;
7861
7862	uint32_t const cTests = *g_aSseConvertXmmI32R64[iFn].pcTests;
7863	SSE_CONVERT_XMM_TEST_T const * const paTests = g_aSseConvertXmmI32R64[iFn].paTests;
7864	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseConvertXmmI32R64[iFn].pfn;
7865	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmI32R64[iFn]);
7866	if (!cTests) RTTestSkipped(g_hTest, "no tests");
7867	for (uint32_t iVar = 0; iVar < cVars; iVar++)
7868	{
7869	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
7870	{
7871	IEMSSERESULT Res; RT_ZERO(Res);
7872
7873	State.MXCSR = paTests[iTest].fMxcsrIn;
7874	pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
7875	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
7876	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
7877	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
7878	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n"
7879	"%s -> mxcsr=%#08x %s'%s\n"
7880	"%s expected %#08x %s'%s%s%s (%s)\n",
7881	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
7882	paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
7883	paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3],
7884	iVar ? " " : "", Res.MXCSR,
7885	FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
7886	iVar ? " " : "", paTests[iTest].fMxcsrOut,
7887	FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
7888	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
7889	( !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
7890	\|\| !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
7891	? " - val" : "",
7892	FormatMxcsr(paTests[iTest].fMxcsrIn));
7893	}
7894	}
7895	}
7896	}
7897
7898
7899	/*
7900	* Convert SSE operations converting signed double-words to double-precision floating point values.
7901	*/
7902	static const SSE_CONVERT_XMM_T g_aSseConvertXmmR64I32[] =
7903	{
7904	ENTRY_BIN(cvtpd2dq_u128),
7905	ENTRY_BIN(cvttpd2dq_u128)
7906	};
7907
7908	#ifdef TSTIEMAIMPL_WITH_GENERATOR
7909	static RTEXITCODE SseConvertXmmR64I32Generate(const char *pszDataFileFmt, uint32_t cTests)
7910	{
7911	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
7912
7913	static struct { RTFLOAT64U aVal1[2]; } const s_aSpecials[] =
7914	{
7915	{ { RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) } },
7916	{ { RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(1) } },
7917	{ { RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(0) } },
7918	{ { RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(1) } }
7919	/** @todo More specials. */
7920	};
7921
7922	X86FXSTATE State;
7923	RT_ZERO(State);
7924	uint32_t cMinNormalPairs = (cTests - 144) / 4;
7925	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++)
7926	{
7927	PFNIEMAIMPLFPSSEF2U128 const pfn = g_aSseConvertXmmR64I32[iFn].pfnNative ? g_aSseConvertXmmR64I32[iFn].pfnNative : g_aSseConvertXmmR64I32[iFn].pfn;
7928
7929	PRTSTREAM pStrmOut = NULL;
7930	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmR64I32[iFn].pszName);
7931	if (RT_FAILURE(rc))
7932	{
7933	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmR64I32[iFn].pszName, rc);
7934	return RTEXITCODE_FAILURE;
7935	}
7936
7937	uint32_t cNormalInputPairs = 0;
7938	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
7939	{
7940	SSE_CONVERT_XMM_TEST_T TestData; RT_ZERO(TestData);
7941
7942	TestData.InVal.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
7943	TestData.InVal.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
7944
7945	if ( RTFLOAT64U_IS_NORMAL(&TestData.InVal.ar64[0])
7946	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal.ar64[1]))
7947	cNormalInputPairs++;
7948	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
7949	{
7950	iTest -= 1;
7951	continue;
7952	}
7953
7954	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
7955	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
7956	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
7957	for (uint8_t iFz = 0; iFz < 2; iFz++)
7958	{
7959	State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
7960	\| (iRounding << X86_MXCSR_RC_SHIFT)
7961	\| (iDaz ? X86_MXCSR_DAZ : 0)
7962	\| (iFz ? X86_MXCSR_FZ : 0)
7963	\| X86_MXCSR_XCPT_MASK;
7964	IEMSSERESULT ResM; RT_ZERO(ResM);
7965	pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
7966	TestData.fMxcsrIn = State.MXCSR;
7967	TestData.fMxcsrOut = ResM.MXCSR;
7968	TestData.OutVal = ResM.uResult;
7969	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7970
7971	State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
7972	IEMSSERESULT ResU; RT_ZERO(ResU);
7973	pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
7974	TestData.fMxcsrIn = State.MXCSR;
7975	TestData.fMxcsrOut = ResU.MXCSR;
7976	TestData.OutVal = ResU.uResult;
7977	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7978
7979	uint16_t fXcpt = (ResM.MXCSR \| ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
7980	if (fXcpt)
7981	{
7982	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
7983	IEMSSERESULT Res1; RT_ZERO(Res1);
7984	pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
7985	TestData.fMxcsrIn = State.MXCSR;
7986	TestData.fMxcsrOut = Res1.MXCSR;
7987	TestData.OutVal = Res1.uResult;
7988	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
7989
7990	if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
7991	{
7992	fXcpt \|= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
7993	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
7994	IEMSSERESULT Res2; RT_ZERO(Res2);
7995	pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
7996	TestData.fMxcsrIn = State.MXCSR;
7997	TestData.fMxcsrOut = Res2.MXCSR;
7998	TestData.OutVal = Res2.uResult;
7999	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8000	}
8001	if (!RT_IS_POWER_OF_TWO(fXcpt))
8002	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
8003	if (fUnmasked & fXcpt)
8004	{
8005	State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
8006	IEMSSERESULT Res3; RT_ZERO(Res3);
8007	pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
8008	TestData.fMxcsrIn = State.MXCSR;
8009	TestData.fMxcsrOut = Res3.MXCSR;
8010	TestData.OutVal = Res3.uResult;
8011	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8012	}
8013	}
8014	}
8015	}
8016	rc = RTStrmClose(pStrmOut);
8017	if (RT_FAILURE(rc))
8018	{
8019	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmR64I32[iFn].pszName, rc);
8020	return RTEXITCODE_FAILURE;
8021	}
8022	}
8023
8024	return RTEXITCODE_SUCCESS;
8025	}
8026	#endif
8027
8028	static void SseConvertXmmR64I32Test(void)
8029	{
8030	X86FXSTATE State;
8031	RT_ZERO(State);
8032
8033	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++)
8034	{
8035	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmR64I32[iFn].pszName))
8036	continue;
8037
8038	uint32_t const cTests = *g_aSseConvertXmmR64I32[iFn].pcTests;
8039	SSE_CONVERT_XMM_TEST_T const * const paTests = g_aSseConvertXmmR64I32[iFn].paTests;
8040	PFNIEMAIMPLFPSSEF2U128 pfn = g_aSseConvertXmmR64I32[iFn].pfn;
8041	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmR64I32[iFn]);
8042	if (!cTests) RTTestSkipped(g_hTest, "no tests");
8043	for (uint32_t iVar = 0; iVar < cVars; iVar++)
8044	{
8045	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
8046	{
8047	IEMSSERESULT Res; RT_ZERO(Res);
8048
8049	State.MXCSR = paTests[iTest].fMxcsrIn;
8050	pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
8051	if ( Res.MXCSR != paTests[iTest].fMxcsrOut
8052	\|\| Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
8053	\|\| Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
8054	\|\| Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
8055	\|\| Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
8056	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s \n"
8057	"%s -> mxcsr=%#08x %RI32'%RI32'%RI32'%RI32\n"
8058	"%s expected %#08x %RI32'%RI32'%RI32'%RI32%s%s (%s)\n",
8059	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
8060	FormatR64(&paTests[iTest].InVal.ar64[0]), FormatR64(&paTests[iTest].InVal.ar64[1]),
8061	iVar ? " " : "", Res.MXCSR,
8062	Res.uResult.ai32[0], Res.uResult.ai32[1],
8063	Res.uResult.ai32[2], Res.uResult.ai32[3],
8064	iVar ? " " : "", paTests[iTest].fMxcsrOut,
8065	paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1],
8066	paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3],
8067	MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
8068	( Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
8069	\|\| Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
8070	\|\| Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
8071	\|\| Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
8072	? " - val" : "",
8073	FormatMxcsr(paTests[iTest].fMxcsrIn));
8074	}
8075	}
8076	}
8077	}
8078
8079
8080	/*
8081	* Convert SSE operations converting double-precision floating point values to signed double-word values.
8082	*/
8083	TYPEDEF_SUBTEST_TYPE(SSE_CONVERT_MM_XMM_T, SSE_CONVERT_MM_XMM_TEST_T, PFNIEMAIMPLMXCSRU64U128);
8084
8085	static const SSE_CONVERT_MM_XMM_T g_aSseConvertMmXmm[] =
8086	{
8087	ENTRY_BIN(cvtpd2pi_u128),
8088	ENTRY_BIN(cvttpd2pi_u128)
8089	};
8090
8091	#ifdef TSTIEMAIMPL_WITH_GENERATOR
8092	static RTEXITCODE SseConvertMmXmmGenerate(const char *pszDataFileFmt, uint32_t cTests)
8093	{
8094	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
8095
8096	static struct { RTFLOAT64U aVal1[2]; } const s_aSpecials[] =
8097	{
8098	{ { RTFLOAT64U_INIT_ZERO(0), RTFLOAT64U_INIT_ZERO(0) } },
8099	{ { RTFLOAT64U_INIT_ZERO(1), RTFLOAT64U_INIT_ZERO(1) } },
8100	{ { RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(0) } },
8101	{ { RTFLOAT64U_INIT_INF(1), RTFLOAT64U_INIT_INF(1) } }
8102	/** @todo More specials. */
8103	};
8104
8105	uint32_t cMinNormalPairs = (cTests - 144) / 4;
8106	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertMmXmm); iFn++)
8107	{
8108	PFNIEMAIMPLMXCSRU64U128 const pfn = g_aSseConvertMmXmm[iFn].pfnNative ? g_aSseConvertMmXmm[iFn].pfnNative : g_aSseConvertMmXmm[iFn].pfn;
8109
8110	PRTSTREAM pStrmOut = NULL;
8111	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertMmXmm[iFn].pszName);
8112	if (RT_FAILURE(rc))
8113	{
8114	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertMmXmm[iFn].pszName, rc);
8115	return RTEXITCODE_FAILURE;
8116	}
8117
8118	uint32_t cNormalInputPairs = 0;
8119	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
8120	{
8121	SSE_CONVERT_MM_XMM_TEST_T TestData; RT_ZERO(TestData);
8122
8123	TestData.InVal.ar64[0] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[0];
8124	TestData.InVal.ar64[1] = iTest < cTests ? RandR64Src(iTest) : s_aSpecials[iTest - cTests].aVal1[1];
8125
8126	if ( RTFLOAT64U_IS_NORMAL(&TestData.InVal.ar64[0])
8127	&& RTFLOAT64U_IS_NORMAL(&TestData.InVal.ar64[1]))
8128	cNormalInputPairs++;
8129	else if (cNormalInputPairs < cMinNormalPairs && iTest + cMinNormalPairs >= cTests && iTest < cTests)
8130	{
8131	iTest -= 1;
8132	continue;
8133	}
8134
8135	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
8136	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
8137	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
8138	for (uint8_t iFz = 0; iFz < 2; iFz++)
8139	{
8140	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
8141	\| (iRounding << X86_MXCSR_RC_SHIFT)
8142	\| (iDaz ? X86_MXCSR_DAZ : 0)
8143	\| (iFz ? X86_MXCSR_FZ : 0)
8144	\| X86_MXCSR_XCPT_MASK;
8145	uint32_t fMxcsrM = fMxcsrIn;
8146	uint64_t u64ResM;
8147	pfn(&fMxcsrM, &u64ResM, &TestData.InVal);
8148	TestData.fMxcsrIn = fMxcsrIn;
8149	TestData.fMxcsrOut = fMxcsrM;
8150	TestData.OutVal.u = u64ResM;
8151	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8152
8153	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
8154	uint32_t fMxcsrU = fMxcsrIn;
8155	uint64_t u64ResU;
8156	pfn(&fMxcsrU, &u64ResU, &TestData.InVal);
8157	TestData.fMxcsrIn = fMxcsrIn;
8158	TestData.fMxcsrOut = fMxcsrU;
8159	TestData.OutVal.u = u64ResU;
8160	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8161
8162	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
8163	if (fXcpt)
8164	{
8165	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
8166	uint32_t fMxcsr1 = fMxcsrIn;
8167	uint64_t u64Res1;
8168	pfn(&fMxcsr1, &u64Res1, &TestData.InVal);
8169	TestData.fMxcsrIn = fMxcsrIn;
8170	TestData.fMxcsrOut = fMxcsr1;
8171	TestData.OutVal.u = u64Res1;
8172	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8173
8174	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
8175	{
8176	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
8177	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
8178	uint32_t fMxcsr2 = fMxcsrIn;
8179	uint64_t u64Res2;
8180	pfn(&fMxcsr2, &u64Res2, &TestData.InVal);
8181	TestData.fMxcsrIn = fMxcsrIn;
8182	TestData.fMxcsrOut = fMxcsr2;
8183	TestData.OutVal.u = u64Res2;
8184	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8185	}
8186	if (!RT_IS_POWER_OF_TWO(fXcpt))
8187	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
8188	if (fUnmasked & fXcpt)
8189	{
8190	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
8191	uint32_t fMxcsr3 = fMxcsrIn;
8192	uint64_t u64Res3;
8193	pfn(&fMxcsr3, &u64Res3, &TestData.InVal);
8194	TestData.fMxcsrIn = fMxcsrIn;
8195	TestData.fMxcsrOut = fMxcsr3;
8196	TestData.OutVal.u = u64Res3;
8197	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8198	}
8199	}
8200	}
8201	}
8202	rc = RTStrmClose(pStrmOut);
8203	if (RT_FAILURE(rc))
8204	{
8205	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertMmXmm[iFn].pszName, rc);
8206	return RTEXITCODE_FAILURE;
8207	}
8208	}
8209
8210	return RTEXITCODE_SUCCESS;
8211	}
8212	#endif
8213
8214	static void SseConvertMmXmmTest(void)
8215	{
8216	X86FXSTATE State;
8217	RT_ZERO(State);
8218
8219	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertMmXmm); iFn++)
8220	{
8221	if (!SubTestAndCheckIfEnabled(g_aSseConvertMmXmm[iFn].pszName))
8222	continue;
8223
8224	uint32_t const cTests = *g_aSseConvertMmXmm[iFn].pcTests;
8225	SSE_CONVERT_MM_XMM_TEST_T const * const paTests = g_aSseConvertMmXmm[iFn].paTests;
8226	PFNIEMAIMPLMXCSRU64U128 pfn = g_aSseConvertMmXmm[iFn].pfn;
8227	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertMmXmm[iFn]);
8228	if (!cTests) RTTestSkipped(g_hTest, "no tests");
8229	for (uint32_t iVar = 0; iVar < cVars; iVar++)
8230	{
8231	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
8232	{
8233	RTUINT64U ValOut;
8234	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
8235	pfn(&fMxcsr, &ValOut.u, &paTests[iTest].InVal);
8236	if ( fMxcsr != paTests[iTest].fMxcsrOut
8237	\|\| ValOut.ai32[0] != paTests[iTest].OutVal.ai32[0]
8238	\|\| ValOut.ai32[1] != paTests[iTest].OutVal.ai32[1])
8239	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s\n"
8240	"%s -> mxcsr=%#08x %RI32'%RI32\n"
8241	"%s expected %#08x %RI32'%RI32%s%s (%s)\n",
8242	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
8243	FormatR64(&paTests[iTest].InVal.ar64[0]), FormatR64(&paTests[iTest].InVal.ar64[1]),
8244	iVar ? " " : "", fMxcsr, ValOut.ai32[0], ValOut.ai32[1],
8245	iVar ? " " : "", paTests[iTest].fMxcsrOut,
8246	paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1],
8247	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
8248	( ValOut.ai32[0] != paTests[iTest].OutVal.ai32[0]
8249	\|\| ValOut.ai32[1] != paTests[iTest].OutVal.ai32[1])
8250	? " - val" : "",
8251	FormatMxcsr(paTests[iTest].fMxcsrIn));
8252	}
8253	}
8254	}
8255	}
8256
8257
8258	/*
8259	* Convert SSE operations converting signed double-word values to double precision floating-point values (probably only cvtpi2pd).
8260	*/
8261	TYPEDEF_SUBTEST_TYPE(SSE_CONVERT_XMM_R64_MM_T, SSE_CONVERT_XMM_MM_TEST_T, PFNIEMAIMPLMXCSRU128U64);
8262
8263	static const SSE_CONVERT_XMM_R64_MM_T g_aSseConvertXmmR64Mm[] =
8264	{
8265	ENTRY_BIN(cvtpi2pd_u128)
8266	};
8267
8268	#ifdef TSTIEMAIMPL_WITH_GENERATOR
8269	static RTEXITCODE SseConvertXmmR64MmGenerate(const char *pszDataFileFmt, uint32_t cTests)
8270	{
8271	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
8272
8273	static struct { int32_t aVal[2]; } const s_aSpecials[] =
8274	{
8275	{ { INT32_MIN, INT32_MIN } },
8276	{ { INT32_MAX, INT32_MAX } }
8277	/** @todo More specials. */
8278	};
8279
8280	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64Mm); iFn++)
8281	{
8282	PFNIEMAIMPLMXCSRU128U64 const pfn = g_aSseConvertXmmR64Mm[iFn].pfnNative ? g_aSseConvertXmmR64Mm[iFn].pfnNative : g_aSseConvertXmmR64Mm[iFn].pfn;
8283
8284	PRTSTREAM pStrmOut = NULL;
8285	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmR64Mm[iFn].pszName);
8286	if (RT_FAILURE(rc))
8287	{
8288	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmR64Mm[iFn].pszName, rc);
8289	return RTEXITCODE_FAILURE;
8290	}
8291
8292	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
8293	{
8294	SSE_CONVERT_XMM_MM_TEST_T TestData; RT_ZERO(TestData);
8295
8296	TestData.InVal.ai32[0] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests].aVal[0];
8297	TestData.InVal.ai32[1] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests].aVal[1];
8298
8299	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
8300	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
8301	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
8302	for (uint8_t iFz = 0; iFz < 2; iFz++)
8303	{
8304	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
8305	\| (iRounding << X86_MXCSR_RC_SHIFT)
8306	\| (iDaz ? X86_MXCSR_DAZ : 0)
8307	\| (iFz ? X86_MXCSR_FZ : 0)
8308	\| X86_MXCSR_XCPT_MASK;
8309	uint32_t fMxcsrM = fMxcsrIn;
8310	pfn(&fMxcsrM, &TestData.OutVal, TestData.InVal.u);
8311	TestData.fMxcsrIn = fMxcsrIn;
8312	TestData.fMxcsrOut = fMxcsrM;
8313	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8314
8315	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
8316	uint32_t fMxcsrU = fMxcsrIn;
8317	pfn(&fMxcsrU, &TestData.OutVal, TestData.InVal.u);
8318	TestData.fMxcsrIn = fMxcsrIn;
8319	TestData.fMxcsrOut = fMxcsrU;
8320	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8321
8322	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
8323	if (fXcpt)
8324	{
8325	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
8326	uint32_t fMxcsr1 = fMxcsrIn;
8327	pfn(&fMxcsr1, &TestData.OutVal, TestData.InVal.u);
8328	TestData.fMxcsrIn = fMxcsrIn;
8329	TestData.fMxcsrOut = fMxcsr1;
8330	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8331
8332	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
8333	{
8334	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
8335	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
8336	uint32_t fMxcsr2 = fMxcsrIn;
8337	pfn(&fMxcsr2, &TestData.OutVal, TestData.InVal.u);
8338	TestData.fMxcsrIn = fMxcsrIn;
8339	TestData.fMxcsrOut = fMxcsr2;
8340	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8341	}
8342	if (!RT_IS_POWER_OF_TWO(fXcpt))
8343	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
8344	if (fUnmasked & fXcpt)
8345	{
8346	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
8347	uint32_t fMxcsr3 = fMxcsrIn;
8348	pfn(&fMxcsr3, &TestData.OutVal, TestData.InVal.u);
8349	TestData.fMxcsrIn = fMxcsrIn;
8350	TestData.fMxcsrOut = fMxcsr3;
8351	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8352	}
8353	}
8354	}
8355	}
8356	rc = RTStrmClose(pStrmOut);
8357	if (RT_FAILURE(rc))
8358	{
8359	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmR64Mm[iFn].pszName, rc);
8360	return RTEXITCODE_FAILURE;
8361	}
8362	}
8363
8364	return RTEXITCODE_SUCCESS;
8365	}
8366	#endif
8367
8368	static void SseConvertXmmR64MmTest(void)
8369	{
8370	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64Mm); iFn++)
8371	{
8372	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmR64Mm[iFn].pszName))
8373	continue;
8374
8375	uint32_t const cTests = *g_aSseConvertXmmR64Mm[iFn].pcTests;
8376	SSE_CONVERT_XMM_MM_TEST_T const * const paTests = g_aSseConvertXmmR64Mm[iFn].paTests;
8377	PFNIEMAIMPLMXCSRU128U64 pfn = g_aSseConvertXmmR64Mm[iFn].pfn;
8378	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmR64Mm[iFn]);
8379	if (!cTests) RTTestSkipped(g_hTest, "no tests");
8380	for (uint32_t iVar = 0; iVar < cVars; iVar++)
8381	{
8382	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
8383	{
8384	X86XMMREG ValOut;
8385	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
8386	pfn(&fMxcsr, &ValOut, paTests[iTest].InVal.u);
8387	if ( fMxcsr != paTests[iTest].fMxcsrOut
8388	\|\| !RTFLOAT64U_ARE_IDENTICAL(&ValOut.ar64[0], &paTests[iTest].OutVal.ar64[0])
8389	\|\| !RTFLOAT64U_ARE_IDENTICAL(&ValOut.ar64[1], &paTests[iTest].OutVal.ar64[1]))
8390	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32\n"
8391	"%s -> mxcsr=%#08x %s'%s\n"
8392	"%s expected %#08x %s'%s%s%s (%s)\n",
8393	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
8394	paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
8395	iVar ? " " : "", fMxcsr,
8396	FormatR64(&ValOut.ar64[0]), FormatR64(&ValOut.ar64[1]),
8397	iVar ? " " : "", paTests[iTest].fMxcsrOut,
8398	FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
8399	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
8400	( !RTFLOAT64U_ARE_IDENTICAL(&ValOut.ar64[0], &paTests[iTest].OutVal.ar64[0])
8401	\|\| !RTFLOAT64U_ARE_IDENTICAL(&ValOut.ar64[1], &paTests[iTest].OutVal.ar64[1]))
8402	? " - val" : "",
8403	FormatMxcsr(paTests[iTest].fMxcsrIn));
8404	}
8405	}
8406	}
8407	}
8408
8409
8410	/*
8411	* Convert SSE operations converting signed double-word values to double precision floating-point values (probably only cvtpi2pd).
8412	*/
8413	TYPEDEF_SUBTEST_TYPE(SSE_CONVERT_XMM_R32_MM_T, SSE_CONVERT_XMM_MM_TEST_T, PFNIEMAIMPLMXCSRU128U64);
8414
8415	static const SSE_CONVERT_XMM_R32_MM_T g_aSseConvertXmmR32Mm[] =
8416	{
8417	ENTRY_BIN(cvtpi2ps_u128)
8418	};
8419
8420	#ifdef TSTIEMAIMPL_WITH_GENERATOR
8421	static RTEXITCODE SseConvertXmmR32MmGenerate(const char *pszDataFileFmt, uint32_t cTests)
8422	{
8423	cTests = RT_MAX(192, cTests); /* there are 144 standard input variations */
8424
8425	static struct { int32_t aVal[2]; } const s_aSpecials[] =
8426	{
8427	{ { INT32_MIN, INT32_MIN } },
8428	{ { INT32_MAX, INT32_MAX } }
8429	/** @todo More specials. */
8430	};
8431
8432	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32Mm); iFn++)
8433	{
8434	PFNIEMAIMPLMXCSRU128U64 const pfn = g_aSseConvertXmmR32Mm[iFn].pfnNative ? g_aSseConvertXmmR32Mm[iFn].pfnNative : g_aSseConvertXmmR32Mm[iFn].pfn;
8435
8436	PRTSTREAM pStrmOut = NULL;
8437	int rc = RTStrmOpenF("wb", &pStrmOut, pszDataFileFmt, g_aSseConvertXmmR32Mm[iFn].pszName);
8438	if (RT_FAILURE(rc))
8439	{
8440	RTMsgError("Failed to open data file for %s for writing: %Rrc", g_aSseConvertXmmR32Mm[iFn].pszName, rc);
8441	return RTEXITCODE_FAILURE;
8442	}
8443
8444	for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
8445	{
8446	SSE_CONVERT_XMM_MM_TEST_T TestData; RT_ZERO(TestData);
8447
8448	TestData.InVal.ai32[0] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests].aVal[0];
8449	TestData.InVal.ai32[1] = iTest < cTests ? RandI32Src2(iTest) : s_aSpecials[iTest - cTests].aVal[1];
8450
8451	uint32_t const fMxcsr = RandMxcsr() & X86_MXCSR_XCPT_FLAGS;
8452	for (uint16_t iRounding = 0; iRounding < 4; iRounding++)
8453	for (uint8_t iDaz = 0; iDaz < 2; iDaz++)
8454	for (uint8_t iFz = 0; iFz < 2; iFz++)
8455	{
8456	uint32_t fMxcsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
8457	\| (iRounding << X86_MXCSR_RC_SHIFT)
8458	\| (iDaz ? X86_MXCSR_DAZ : 0)
8459	\| (iFz ? X86_MXCSR_FZ : 0)
8460	\| X86_MXCSR_XCPT_MASK;
8461	uint32_t fMxcsrM = fMxcsrIn;
8462	pfn(&fMxcsrM, &TestData.OutVal, TestData.InVal.u);
8463	TestData.fMxcsrIn = fMxcsrIn;
8464	TestData.fMxcsrOut = fMxcsrM;
8465	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8466
8467	fMxcsrIn &= ~X86_MXCSR_XCPT_MASK;
8468	uint32_t fMxcsrU = fMxcsrIn;
8469	pfn(&fMxcsrU, &TestData.OutVal, TestData.InVal.u);
8470	TestData.fMxcsrIn = fMxcsrIn;
8471	TestData.fMxcsrOut = fMxcsrU;
8472	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8473
8474	uint16_t fXcpt = (fMxcsrM \| fMxcsrU) & X86_MXCSR_XCPT_FLAGS;
8475	if (fXcpt)
8476	{
8477	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| fXcpt;
8478	uint32_t fMxcsr1 = fMxcsrIn;
8479	pfn(&fMxcsr1, &TestData.OutVal, TestData.InVal.u);
8480	TestData.fMxcsrIn = fMxcsrIn;
8481	TestData.fMxcsrOut = fMxcsr1;
8482	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8483
8484	if (((fMxcsr1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (fMxcsr1 & X86_MXCSR_XCPT_FLAGS))
8485	{
8486	fXcpt \|= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
8487	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
8488	uint32_t fMxcsr2 = fMxcsrIn;
8489	pfn(&fMxcsr2, &TestData.OutVal, TestData.InVal.u);
8490	TestData.fMxcsrIn = fMxcsrIn;
8491	TestData.fMxcsrOut = fMxcsr2;
8492	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8493	}
8494	if (!RT_IS_POWER_OF_TWO(fXcpt))
8495	for (uint16_t fUnmasked = 1; fUnmasked <= X86_MXCSR_PE; fUnmasked <<= 1)
8496	if (fUnmasked & fXcpt)
8497	{
8498	fMxcsrIn = (fMxcsrIn & ~X86_MXCSR_XCPT_MASK) \| ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
8499	uint32_t fMxcsr3 = fMxcsrIn;
8500	pfn(&fMxcsr3, &TestData.OutVal, TestData.InVal.u);
8501	TestData.fMxcsrIn = fMxcsrIn;
8502	TestData.fMxcsrOut = fMxcsr3;
8503	RTStrmWrite(pStrmOut, &TestData, sizeof(TestData));
8504	}
8505	}
8506	}
8507	}
8508	rc = RTStrmClose(pStrmOut);
8509	if (RT_FAILURE(rc))
8510	{
8511	RTMsgError("Failed to close data file for %s: %Rrc", g_aSseConvertXmmR32Mm[iFn].pszName, rc);
8512	return RTEXITCODE_FAILURE;
8513	}
8514	}
8515
8516	return RTEXITCODE_SUCCESS;
8517	}
8518	#endif
8519
8520	static void SseConvertXmmR32MmTest(void)
8521	{
8522	for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32Mm); iFn++)
8523	{
8524	if (!SubTestAndCheckIfEnabled(g_aSseConvertXmmR32Mm[iFn].pszName))
8525	continue;
8526
8527	uint32_t const cTests = *g_aSseConvertXmmR32Mm[iFn].pcTests;
8528	SSE_CONVERT_XMM_MM_TEST_T const * const paTests = g_aSseConvertXmmR32Mm[iFn].paTests;
8529	PFNIEMAIMPLMXCSRU128U64 pfn = g_aSseConvertXmmR32Mm[iFn].pfn;
8530	uint32_t const cVars = COUNT_VARIATIONS(g_aSseConvertXmmR32Mm[iFn]);
8531	if (!cTests) RTTestSkipped(g_hTest, "no tests");
8532	for (uint32_t iVar = 0; iVar < cVars; iVar++)
8533	{
8534	for (uint32_t iTest = 0; iTest < cTests / sizeof(*paTests); iTest++)
8535	{
8536	X86XMMREG ValOut;
8537	uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
8538	pfn(&fMxcsr, &ValOut, paTests[iTest].InVal.u);
8539	if ( fMxcsr != paTests[iTest].fMxcsrOut
8540	\|\| !RTFLOAT32U_ARE_IDENTICAL(&ValOut.ar32[0], &paTests[iTest].OutVal.ar32[0])
8541	\|\| !RTFLOAT32U_ARE_IDENTICAL(&ValOut.ar32[1], &paTests[iTest].OutVal.ar32[1]))
8542	RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32\n"
8543	"%s -> mxcsr=%#08x %s'%s\n"
8544	"%s expected %#08x %s'%s%s%s (%s)\n",
8545	iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
8546	paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
8547	iVar ? " " : "", fMxcsr,
8548	FormatR32(&ValOut.ar32[0]), FormatR32(&ValOut.ar32[1]),
8549	iVar ? " " : "", paTests[iTest].fMxcsrOut,
8550	FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
8551	MxcsrDiff(fMxcsr, paTests[iTest].fMxcsrOut),
8552	( !RTFLOAT32U_ARE_IDENTICAL(&ValOut.ar32[0], &paTests[iTest].OutVal.ar32[0])
8553	\|\| !RTFLOAT32U_ARE_IDENTICAL(&ValOut.ar32[1], &paTests[iTest].OutVal.ar32[1]))
8554	? " - val" : "",
8555	FormatMxcsr(paTests[iTest].fMxcsrIn));
8556	}
8557	}
8558	}
8559	}
8560
8561
8562
8563	int main(int argc, char **argv)
8564	{
8565	int rc = RTR3InitExe(argc, &argv, 0);
8566	if (RT_FAILURE(rc))
8567	return RTMsgInitFailure(rc);
8568
8569	/*
8570	* Determin the host CPU.
8571	* If not using the IEMAllAImpl.asm code, this will be set to Intel.
8572	*/
8573	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
8574	g_idxCpuEflFlavour = ASMIsAmdCpu() \|\| ASMIsHygonCpu()
8575	? IEMTARGETCPU_EFL_BEHAVIOR_AMD
8576	: IEMTARGETCPU_EFL_BEHAVIOR_INTEL;
8577	#else
8578	g_idxCpuEflFlavour = IEMTARGETCPU_EFL_BEHAVIOR_INTEL;
8579	#endif
8580
8581	/*
8582	* Parse arguments.
8583	*/
8584	enum { kModeNotSet, kModeTest, kModeGenerate }
8585	enmMode = kModeNotSet;
8586	bool fInt = true;
8587	bool fFpuLdSt = true;
8588	bool fFpuBinary1 = true;
8589	bool fFpuBinary2 = true;
8590	bool fFpuOther = true;
8591	bool fCpuData = true;
8592	bool fCommonData = true;
8593	bool fSseFpBinary = true;
8594	bool fSseFpOther = true;
8595	uint32_t const cDefaultTests = 96;
8596	uint32_t cTests = cDefaultTests;
8597	RTGETOPTDEF const s_aOptions[] =
8598	{
8599	// mode:
8600	{ "--generate", 'g', RTGETOPT_REQ_NOTHING },
8601	{ "--test", 't', RTGETOPT_REQ_NOTHING },
8602	// test selection (both)
8603	{ "--all", 'a', RTGETOPT_REQ_NOTHING },
8604	{ "--none", 'z', RTGETOPT_REQ_NOTHING },
8605	{ "--zap", 'z', RTGETOPT_REQ_NOTHING },
8606	{ "--fpu-ld-st", 'F', RTGETOPT_REQ_NOTHING }, /* FPU stuff is upper case */
8607	{ "--fpu-load-store", 'F', RTGETOPT_REQ_NOTHING },
8608	{ "--fpu-binary-1", 'B', RTGETOPT_REQ_NOTHING },
8609	{ "--fpu-binary-2", 'P', RTGETOPT_REQ_NOTHING },
8610	{ "--fpu-other", 'O', RTGETOPT_REQ_NOTHING },
8611	{ "--sse-fp-binary", 'S', RTGETOPT_REQ_NOTHING },
8612	{ "--sse-fp-other", 'T', RTGETOPT_REQ_NOTHING },
8613	{ "--int", 'i', RTGETOPT_REQ_NOTHING },
8614	{ "--include", 'I', RTGETOPT_REQ_STRING },
8615	{ "--exclude", 'X', RTGETOPT_REQ_STRING },
8616	// generation parameters
8617	{ "--common", 'm', RTGETOPT_REQ_NOTHING },
8618	{ "--cpu", 'c', RTGETOPT_REQ_NOTHING },
8619	{ "--number-of-tests", 'n', RTGETOPT_REQ_UINT32 },
8620	{ "--verbose", 'v', RTGETOPT_REQ_NOTHING },
8621	{ "--quiet", 'q', RTGETOPT_REQ_NOTHING },
8622	};
8623
8624	RTGETOPTSTATE State;
8625	rc = RTGetOptInit(&State, argc, argv, s_aOptions, RT_ELEMENTS(s_aOptions), 1, 0);
8626	AssertRCReturn(rc, RTEXITCODE_FAILURE);
8627
8628	RTGETOPTUNION ValueUnion;
8629	while ((rc = RTGetOpt(&State, &ValueUnion)))
8630	{
8631	switch (rc)
8632	{
8633	case 'g':
8634	enmMode = kModeGenerate;
8635	break;
8636	case 't':
8637	enmMode = kModeTest;
8638	break;
8639
8640	case 'a':
8641	fCpuData = true;
8642	fCommonData = true;
8643	fInt = true;
8644	fFpuLdSt = true;
8645	fFpuBinary1 = true;
8646	fFpuBinary2 = true;
8647	fFpuOther = true;
8648	fSseFpBinary = true;
8649	fSseFpOther = true;
8650	break;
8651	case 'z':
8652	fCpuData = false;
8653	fCommonData = false;
8654	fInt = false;
8655	fFpuLdSt = false;
8656	fFpuBinary1 = false;
8657	fFpuBinary2 = false;
8658	fFpuOther = false;
8659	fSseFpBinary = false;
8660	fSseFpOther = false;
8661	break;
8662
8663	case 'F':
8664	fFpuLdSt = true;
8665	break;
8666	case 'O':
8667	fFpuOther = true;
8668	break;
8669	case 'B':
8670	fFpuBinary1 = true;
8671	break;
8672	case 'P':
8673	fFpuBinary2 = true;
8674	break;
8675	case 'S':
8676	fSseFpBinary = true;
8677	break;
8678	case 'T':
8679	fSseFpOther = true;
8680	break;
8681	case 'i':
8682	fInt = true;
8683	break;
8684
8685	case 'I':
8686	if (g_cIncludeTestPatterns >= RT_ELEMENTS(g_apszIncludeTestPatterns))
8687	return RTMsgErrorExit(RTEXITCODE_SYNTAX, "Too many include patterns (max %zu)",
8688	RT_ELEMENTS(g_apszIncludeTestPatterns));
8689	g_apszIncludeTestPatterns[g_cIncludeTestPatterns++] = ValueUnion.psz;
8690	break;
8691	case 'X':
8692	if (g_cExcludeTestPatterns >= RT_ELEMENTS(g_apszExcludeTestPatterns))
8693	return RTMsgErrorExit(RTEXITCODE_SYNTAX, "Too many exclude patterns (max %zu)",
8694	RT_ELEMENTS(g_apszExcludeTestPatterns));
8695	g_apszExcludeTestPatterns[g_cExcludeTestPatterns++] = ValueUnion.psz;
8696	break;
8697
8698	case 'm':
8699	fCommonData = true;
8700	break;
8701	case 'c':
8702	fCpuData = true;
8703	break;
8704	case 'n':
8705	cTests = ValueUnion.u32;
8706	break;
8707
8708	case 'q':
8709	g_cVerbosity = 0;
8710	break;
8711	case 'v':
8712	g_cVerbosity++;
8713	break;
8714
8715	case 'h':
8716	RTPrintf("usage: %s <-g\|-t> [options]\n"
8717	"\n"
8718	"Mode:\n"
8719	" -g, --generate\n"
8720	" Generate test data.\n"
8721	" -t, --test\n"
8722	" Execute tests.\n"
8723	"\n"
8724	"Test selection (both modes):\n"
8725	" -a, --all\n"
8726	" Enable all tests and generated test data. (default)\n"
8727	" -z, --zap, --none\n"
8728	" Disable all tests and test data types.\n"
8729	" -i, --int\n"
8730	" Enable non-FPU tests.\n"
8731	" -F, --fpu-ld-st\n"
8732	" Enable FPU load and store tests.\n"
8733	" -B, --fpu-binary-1\n"
8734	" Enable FPU binary 80-bit FP tests.\n"
8735	" -P, --fpu-binary-2\n"
8736	" Enable FPU binary 64- and 32-bit FP tests.\n"
8737	" -O, --fpu-other\n"
8738	" Enable FPU binary 64- and 32-bit FP tests.\n"
8739	" -S, --sse-fp-binary\n"
8740	" Enable SSE binary 64- and 32-bit FP tests.\n"
8741	" -T, --sse-fp-other\n"
8742	" Enable misc SSE 64- and 32-bit FP tests.\n"
8743	" -I,--include=<test-patter>\n"
8744	" Enable tests matching the given pattern.\n"
8745	" -X,--exclude=<test-patter>\n"
8746	" Skip tests matching the given pattern (overrides --include).\n"
8747	"\n"
8748	"Generation:\n"
8749	" -m, --common\n"
8750	" Enable generating common test data.\n"
8751	" -c, --only-cpu\n"
8752	" Enable generating CPU specific test data.\n"
8753	" -n, --number-of-test <count>\n"
8754	" Number of tests to generate. Default: %u\n"
8755	"\n"
8756	"Other:\n"
8757	" -v, --verbose\n"
8758	" -q, --quiet\n"
8759	" Noise level. Default: --quiet\n"
8760	, argv[0], cDefaultTests);
8761	return RTEXITCODE_SUCCESS;
8762	default:
8763	return RTGetOptPrintError(rc, &ValueUnion);
8764	}
8765	}
8766
8767	/*
8768	* Generate data?
8769	*/
8770	if (enmMode == kModeGenerate)
8771	{
8772	#ifdef TSTIEMAIMPL_WITH_GENERATOR
8773	char szCpuDesc[256] = {0};
8774	RTMpGetDescription(NIL_RTCPUID, szCpuDesc, sizeof(szCpuDesc));
8775	const char * const pszCpuType = g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD ? "Amd" : "Intel";
8776	# if defined(RT_OS_WINDOWS) \|\| defined(RT_OS_OS2)
8777	const char * const pszBitBucket = "NUL";
8778	# else
8779	const char * const pszBitBucket = "/dev/null";
8780	# endif
8781
8782	if (cTests == 0)
8783	cTests = cDefaultTests;
8784	g_cZeroDstTests = RT_MIN(cTests / 16, 32);
8785	g_cZeroSrcTests = g_cZeroDstTests * 2;
8786
8787	if (fInt)
8788	{
8789	const char *pszDataFile = fCommonData ? "tstIEMAImplDataInt.cpp" : pszBitBucket;
8790	PRTSTREAM pStrmData = GenerateOpenWithHdr(pszDataFile, szCpuDesc, NULL);
8791	const char *pszDataCpuFile = !fCpuData ? pszBitBucket : g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD
8792	? "tstIEMAImplDataInt-Amd.cpp" : "tstIEMAImplDataInt-Intel.cpp";
8793	PRTSTREAM pStrmDataCpu = GenerateOpenWithHdr(pszDataCpuFile, szCpuDesc, pszCpuType);
8794	if (!pStrmData \|\| !pStrmDataCpu)
8795	return RTEXITCODE_FAILURE;
8796
8797	BinU8Generate( pStrmData, pStrmDataCpu, cTests);
8798	BinU16Generate(pStrmData, pStrmDataCpu, cTests);
8799	BinU32Generate(pStrmData, pStrmDataCpu, cTests);
8800	BinU64Generate(pStrmData, pStrmDataCpu, cTests);
8801	ShiftDblGenerate(pStrmDataCpu, RT_MAX(cTests, 128));
8802	UnaryGenerate(pStrmData, cTests);
8803	ShiftGenerate(pStrmDataCpu, cTests);
8804	MulDivGenerate(pStrmDataCpu, cTests);
8805
8806	RTEXITCODE rcExit = GenerateFooterAndClose(pStrmDataCpu, pszDataCpuFile,
8807	GenerateFooterAndClose(pStrmData, pszDataFile, RTEXITCODE_SUCCESS));
8808	if (rcExit != RTEXITCODE_SUCCESS)
8809	return rcExit;
8810	}
8811
8812	if (fFpuLdSt)
8813	{
8814	const char *pszDataFile = fCommonData ? "tstIEMAImplDataFpuLdSt.cpp" : pszBitBucket;
8815	PRTSTREAM pStrmData = GenerateOpenWithHdr(pszDataFile, szCpuDesc, NULL);
8816	const char *pszDataCpuFile = !fCpuData ? pszBitBucket : g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD
8817	? "tstIEMAImplDataFpuLdSt-Amd.cpp" : "tstIEMAImplDataFpuLdSt-Intel.cpp";
8818	PRTSTREAM pStrmDataCpu = GenerateOpenWithHdr(pszDataCpuFile, szCpuDesc, pszCpuType);
8819	if (!pStrmData \|\| !pStrmDataCpu)
8820	return RTEXITCODE_FAILURE;
8821
8822	FpuLdConstGenerate(pStrmData, cTests);
8823	FpuLdIntGenerate(pStrmData, cTests);
8824	FpuLdD80Generate(pStrmData, cTests);
8825	FpuStIntGenerate(pStrmData, pStrmDataCpu, cTests);
8826	FpuStD80Generate(pStrmData, cTests);
8827	uint32_t const cTests2 = RT_MAX(cTests, 384); /* need better coverage for the next ones. */
8828	FpuLdMemGenerate(pStrmData, cTests2);
8829	FpuStMemGenerate(pStrmData, cTests2);
8830
8831	RTEXITCODE rcExit = GenerateFooterAndClose(pStrmDataCpu, pszDataCpuFile,
8832	GenerateFooterAndClose(pStrmData, pszDataFile, RTEXITCODE_SUCCESS));
8833	if (rcExit != RTEXITCODE_SUCCESS)
8834	return rcExit;
8835	}
8836
8837	if (fFpuBinary1)
8838	{
8839	const char *pszDataFile = fCommonData ? "tstIEMAImplDataFpuBinary1.cpp" : pszBitBucket;
8840	PRTSTREAM pStrmData = GenerateOpenWithHdr(pszDataFile, szCpuDesc, NULL);
8841	const char *pszDataCpuFile = !fCpuData ? pszBitBucket : g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD
8842	? "tstIEMAImplDataFpuBinary1-Amd.cpp" : "tstIEMAImplDataFpuBinary1-Intel.cpp";
8843	PRTSTREAM pStrmDataCpu = GenerateOpenWithHdr(pszDataCpuFile, szCpuDesc, pszCpuType);
8844	if (!pStrmData \|\| !pStrmDataCpu)
8845	return RTEXITCODE_FAILURE;
8846
8847	FpuBinaryR80Generate(pStrmData, pStrmDataCpu, cTests);
8848	FpuBinaryFswR80Generate(pStrmData, cTests);
8849	FpuBinaryEflR80Generate(pStrmData, cTests);
8850
8851	RTEXITCODE rcExit = GenerateFooterAndClose(pStrmDataCpu, pszDataCpuFile,
8852	GenerateFooterAndClose(pStrmData, pszDataFile, RTEXITCODE_SUCCESS));
8853	if (rcExit != RTEXITCODE_SUCCESS)
8854	return rcExit;
8855	}
8856
8857	if (fFpuBinary2)
8858	{
8859	const char *pszDataFile = fCommonData ? "tstIEMAImplDataFpuBinary2.cpp" : pszBitBucket;
8860	PRTSTREAM pStrmData = GenerateOpenWithHdr(pszDataFile, szCpuDesc, NULL);
8861	const char pszDataCpuFile = pszBitBucket; /!fCpuData ? pszBitBucket : g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD
8862	? "tstIEMAImplDataFpuBinary2-Amd.cpp" : "tstIEMAImplDataFpuBinary2-Intel.cpp"; */
8863	PRTSTREAM pStrmDataCpu = GenerateOpenWithHdr(pszDataCpuFile, szCpuDesc, pszCpuType);
8864	if (!pStrmData \|\| !pStrmDataCpu)
8865	return RTEXITCODE_FAILURE;
8866
8867	FpuBinaryR64Generate(pStrmData, cTests);
8868	FpuBinaryR32Generate(pStrmData, cTests);
8869	FpuBinaryI32Generate(pStrmData, cTests);
8870	FpuBinaryI16Generate(pStrmData, cTests);
8871	FpuBinaryFswR64Generate(pStrmData, cTests);
8872	FpuBinaryFswR32Generate(pStrmData, cTests);
8873	FpuBinaryFswI32Generate(pStrmData, cTests);
8874	FpuBinaryFswI16Generate(pStrmData, cTests);
8875
8876	RTEXITCODE rcExit = GenerateFooterAndClose(pStrmDataCpu, pszDataCpuFile,
8877	GenerateFooterAndClose(pStrmData, pszDataFile, RTEXITCODE_SUCCESS));
8878	if (rcExit != RTEXITCODE_SUCCESS)
8879	return rcExit;
8880	}
8881
8882	if (fFpuOther)
8883	{
8884	const char *pszDataFile = fCommonData ? "tstIEMAImplDataFpuOther.cpp" : pszBitBucket;
8885	PRTSTREAM pStrmData = GenerateOpenWithHdr(pszDataFile, szCpuDesc, NULL);
8886	const char *pszDataCpuFile = !fCpuData ? pszBitBucket : g_idxCpuEflFlavour == IEMTARGETCPU_EFL_BEHAVIOR_AMD
8887	? "tstIEMAImplDataFpuOther-Amd.cpp" : "tstIEMAImplDataFpuOther-Intel.cpp";
8888	PRTSTREAM pStrmDataCpu = GenerateOpenWithHdr(pszDataCpuFile, szCpuDesc, pszCpuType);
8889	if (!pStrmData \|\| !pStrmDataCpu)
8890	return RTEXITCODE_FAILURE;
8891
8892	FpuUnaryR80Generate(pStrmData, pStrmDataCpu, cTests);
8893	FpuUnaryFswR80Generate(pStrmData, pStrmDataCpu, cTests);
8894	FpuUnaryTwoR80Generate(pStrmData, pStrmDataCpu, cTests);
8895
8896	RTEXITCODE rcExit = GenerateFooterAndClose(pStrmDataCpu, pszDataCpuFile,
8897	GenerateFooterAndClose(pStrmData, pszDataFile, RTEXITCODE_SUCCESS));
8898	if (rcExit != RTEXITCODE_SUCCESS)
8899	return rcExit;
8900	}
8901
8902	if (fSseFpBinary)
8903	{
8904	const char *pszDataFileFmt = fCommonData ? "tstIEMAImplDataSseBinary-%s.bin" : pszBitBucket;
8905
8906	RTEXITCODE rcExit = SseBinaryR32Generate(pszDataFileFmt, cTests);
8907	if (rcExit == RTEXITCODE_SUCCESS)
8908	rcExit = SseBinaryR64Generate(pszDataFileFmt, cTests);
8909	if (rcExit == RTEXITCODE_SUCCESS)
8910	rcExit = SseBinaryU128R32Generate(pszDataFileFmt, cTests);
8911	if (rcExit == RTEXITCODE_SUCCESS)
8912	rcExit = SseBinaryU128R64Generate(pszDataFileFmt, cTests);
8913
8914	if (rcExit == RTEXITCODE_SUCCESS)
8915	rcExit = SseBinaryI32R64Generate(pszDataFileFmt, cTests);
8916	if (rcExit == RTEXITCODE_SUCCESS)
8917	rcExit = SseBinaryI64R64Generate(pszDataFileFmt, cTests);
8918	if (rcExit == RTEXITCODE_SUCCESS)
8919	rcExit = SseBinaryI32R32Generate(pszDataFileFmt, cTests);
8920	if (rcExit == RTEXITCODE_SUCCESS)
8921	rcExit = SseBinaryI64R32Generate(pszDataFileFmt, cTests);
8922
8923	if (rcExit == RTEXITCODE_SUCCESS)
8924	rcExit = SseBinaryR64I32Generate(pszDataFileFmt, cTests);
8925	if (rcExit == RTEXITCODE_SUCCESS)
8926	rcExit = SseBinaryR64I64Generate(pszDataFileFmt, cTests);
8927	if (rcExit == RTEXITCODE_SUCCESS)
8928	rcExit = SseBinaryR32I32Generate(pszDataFileFmt, cTests);
8929	if (rcExit == RTEXITCODE_SUCCESS)
8930	rcExit = SseBinaryR32I64Generate(pszDataFileFmt, cTests);
8931	if (rcExit != RTEXITCODE_SUCCESS)
8932	return rcExit;
8933	}
8934
8935	if (fSseFpOther)
8936	{
8937	const char *pszDataFileFmtCmp = fCommonData ? "tstIEMAImplDataSseCompare-%s.bin" : pszBitBucket;
8938	const char *pszDataFileFmtConv = fCommonData ? "tstIEMAImplDataSseConvert-%s.bin" : pszBitBucket;
8939
8940	RTEXITCODE rcExit = SseCompareEflR32R32Generate(pszDataFileFmtCmp, cTests);
8941	if (rcExit == RTEXITCODE_SUCCESS)
8942	rcExit = SseCompareEflR64R64Generate(pszDataFileFmtCmp, cTests);
8943	if (rcExit == RTEXITCODE_SUCCESS)
8944	rcExit = SseCompareF2XmmR32Imm8Generate(pszDataFileFmtCmp, cTests);
8945	if (rcExit == RTEXITCODE_SUCCESS)
8946	rcExit = SseCompareF2XmmR64Imm8Generate(pszDataFileFmtCmp, cTests);
8947	if (rcExit == RTEXITCODE_SUCCESS)
8948	rcExit = SseConvertXmmI32R32Generate(pszDataFileFmtConv, cTests);
8949	if (rcExit == RTEXITCODE_SUCCESS)
8950	rcExit = SseConvertXmmR32I32Generate(pszDataFileFmtConv, cTests);
8951	if (rcExit == RTEXITCODE_SUCCESS)
8952	rcExit = SseConvertXmmI32R64Generate(pszDataFileFmtConv, cTests);
8953	if (rcExit == RTEXITCODE_SUCCESS)
8954	rcExit = SseConvertXmmR64I32Generate(pszDataFileFmtConv, cTests);
8955	if (rcExit == RTEXITCODE_SUCCESS)
8956	rcExit = SseConvertMmXmmGenerate(pszDataFileFmtConv, cTests);
8957	if (rcExit == RTEXITCODE_SUCCESS)
8958	rcExit = SseConvertXmmR32MmGenerate(pszDataFileFmtConv, cTests);
8959	if (rcExit == RTEXITCODE_SUCCESS)
8960	rcExit = SseConvertXmmR64MmGenerate(pszDataFileFmtConv, cTests);
8961	if (rcExit != RTEXITCODE_SUCCESS)
8962	return rcExit;
8963	}
8964
8965	return RTEXITCODE_SUCCESS;
8966	#else
8967	return RTMsgErrorExitFailure("Test data generator not compiled in!");
8968	#endif
8969	}
8970
8971	/*
8972	* Do testing. Currrently disabled by default as data needs to be checked
8973	* on both intel and AMD systems first.
8974	*/
8975	rc = RTTestCreate("tstIEMAimpl", &g_hTest);
8976	AssertRCReturn(rc, RTEXITCODE_FAILURE);
8977	if (enmMode == kModeTest)
8978	{
8979	RTTestBanner(g_hTest);
8980
8981	/* Allocate guarded memory for use in the tests. */
8982	#define ALLOC_GUARDED_VAR(a_puVar) do { \
8983	rc = RTTestGuardedAlloc(g_hTest, sizeof(a_puVar), sizeof(a_puVar), false /fHead/, (void **)&a_puVar); \
8984	if (RT_FAILURE(rc)) RTTestFailed(g_hTest, "Failed to allocate guarded mem: " #a_puVar); \
8985	} while (0)
8986	ALLOC_GUARDED_VAR(g_pu8);
8987	ALLOC_GUARDED_VAR(g_pu16);
8988	ALLOC_GUARDED_VAR(g_pu32);
8989	ALLOC_GUARDED_VAR(g_pu64);
8990	ALLOC_GUARDED_VAR(g_pu128);
8991	ALLOC_GUARDED_VAR(g_pu8Two);
8992	ALLOC_GUARDED_VAR(g_pu16Two);
8993	ALLOC_GUARDED_VAR(g_pu32Two);
8994	ALLOC_GUARDED_VAR(g_pu64Two);
8995	ALLOC_GUARDED_VAR(g_pu128Two);
8996	ALLOC_GUARDED_VAR(g_pfEfl);
8997	if (RTTestErrorCount(g_hTest) == 0)
8998	{
8999	if (fInt)
9000	{
9001	BinU8Test();
9002	BinU16Test();
9003	BinU32Test();
9004	BinU64Test();
9005	XchgTest();
9006	XaddTest();
9007	CmpXchgTest();
9008	CmpXchg8bTest();
9009	CmpXchg16bTest();
9010	ShiftDblTest();
9011	UnaryTest();
9012	ShiftTest();
9013	MulDivTest();
9014	BswapTest();
9015	}
9016
9017	if (fFpuLdSt)
9018	{
9019	FpuLoadConstTest();
9020	FpuLdMemTest();
9021	FpuLdIntTest();
9022	FpuLdD80Test();
9023	FpuStMemTest();
9024	FpuStIntTest();
9025	FpuStD80Test();
9026	}
9027
9028	if (fFpuBinary1)
9029	{
9030	FpuBinaryR80Test();
9031	FpuBinaryFswR80Test();
9032	FpuBinaryEflR80Test();
9033	}
9034
9035	if (fFpuBinary2)
9036	{
9037	FpuBinaryR64Test();
9038	FpuBinaryR32Test();
9039	FpuBinaryI32Test();
9040	FpuBinaryI16Test();
9041	FpuBinaryFswR64Test();
9042	FpuBinaryFswR32Test();
9043	FpuBinaryFswI32Test();
9044	FpuBinaryFswI16Test();
9045	}
9046
9047	if (fFpuOther)
9048	{
9049	FpuUnaryR80Test();
9050	FpuUnaryFswR80Test();
9051	FpuUnaryTwoR80Test();
9052	}
9053
9054	if (fSseFpBinary)
9055	{
9056	SseBinaryR32Test();
9057	SseBinaryR64Test();
9058	SseBinaryU128R32Test();
9059	SseBinaryU128R64Test();
9060
9061	SseBinaryI32R64Test();
9062	SseBinaryI64R64Test();
9063	SseBinaryI32R32Test();
9064	SseBinaryI64R32Test();
9065
9066	SseBinaryR64I32Test();
9067	SseBinaryR64I64Test();
9068	SseBinaryR32I32Test();
9069	SseBinaryR32I64Test();
9070	}
9071
9072	if (fSseFpOther)
9073	{
9074	SseCompareEflR32R32Test();
9075	SseCompareEflR64R64Test();
9076	SseCompareEflR64R64Test();
9077	SseCompareF2XmmR32Imm8Test();
9078	SseCompareF2XmmR64Imm8Test();
9079	SseConvertXmmI32R32Test();
9080	SseConvertXmmR32I32Test();
9081	SseConvertXmmI32R64Test();
9082	SseConvertXmmR64I32Test();
9083	SseConvertMmXmmTest();
9084	SseConvertXmmR32MmTest();
9085	SseConvertXmmR64MmTest();
9086	}
9087	}
9088	return RTTestSummaryAndDestroy(g_hTest);
9089	}
9090	return RTTestSkipAndDestroy(g_hTest, "unfinished testcase");
9091	}
9092

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source: vbox/trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp@ 96922

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