tstIEMCheckMc.cpp@ 100696

Last change on this file since 100696 was 100591, checked in by vboxsync, 17 months ago
VMM/IEM: Must pass the FPU opcode word to the various MCs updating FOP as IEMCPU::uFpuOpcode isn't available during recompiled code execution. bugref:10369
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File size: 85.8 KB

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1	/* $Id: tstIEMCheckMc.cpp 100591 2023-07-15 01:20:13Z vboxsync $ */
2	/** @file
3	* IEM Testcase - Check the "Microcode".
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define VMCPU_INCL_CPUM_GST_CTX
33	#include <iprt/assert.h>
34	#include <iprt/rand.h>
35	#include <iprt/test.h>
36
37	#include <VBox/types.h>
38	#include <VBox/err.h>
39	#include <VBox/log.h>
40	#define TST_IEM_CHECK_MC /*< For hacks. /
41	#define IN_TSTVMSTRUCT 1 /*< Ditto. /
42	#include "../include/IEMInternal.h"
43	#include <VBox/vmm/vm.h>
44
45
46	/*********************************************************************************************************************************
47	* Global Variables *
48	*********************************************************************************************************************************/
49	bool volatile g_fRandom;
50	uint8_t volatile g_bRandom;
51	RTUINT128U g_u128Zero;
52	X86XMMREG g_XmmZero;
53
54
55
56	#define CHK_TYPE(a_ExpectedType, a_Param) \
57	do { a_ExpectedType const * pCheckType = &(a_Param); NOREF(pCheckType); } while (0)
58	#define CHK_PTYPE(a_ExpectedType, a_Param) \
59	do { a_ExpectedType pCheckType = (a_Param); NOREF(pCheckType); } while (0)
60
61	#define CHK_CONST(a_ExpectedType, a_Const) \
62	do { \
63	AssertCompile(((a_Const) >> 1) == ((a_Const) >> 1)); \
64	AssertCompile((a_ExpectedType)(a_Const) == (a_Const)); \
65	} while (0)
66
67	#define CHK_SINGLE_BIT(a_ExpectedType, a_fBitMask) \
68	do { \
69	CHK_CONST(a_ExpectedType, a_fBitMask); \
70	AssertCompile(RT_IS_POWER_OF_TWO(a_fBitMask)); \
71	} while (0)
72
73	#define CHK_GCPTR(a_EffAddr) \
74	CHK_TYPE(RTGCPTR, a_EffAddr)
75
76	#define CHK_SEG_IDX(a_iSeg) \
77	do { \
78	uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \
79	} while (0)
80
81	#define CHK_GREG_IDX(a_iGReg) \
82	do { \
83	uint8_t const iMyGReg = (a_iGReg); NOREF(iMyGReg); \
84	} while (0)
85
86	#define CHK_MREG_IDX(a_iMReg) \
87	do { \
88	uint8_t const iMyMReg = (a_iMReg); NOREF(iMyMReg); \
89	} while (0)
90
91	#define CHK_XREG_IDX(a_iXReg) \
92	do { \
93	uint8_t const iMyXReg = (a_iXReg); NOREF(iMyXReg); \
94	} while (0)
95
96	#define CHK_YREG_IDX(a_iYReg) \
97	do { \
98	uint8_t const iMyYReg = (a_iYReg); NOREF(iMyYReg); \
99	} while (0)
100
101	#define CHK_CALL_ARG(a_Name, a_iArg) \
102	do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0)
103
104
105	/** @name Other stubs.
106	* @{ */
107
108	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPU pVCpu);
109	#undef FNIEMOP_DEF
110	#define FNIEMOP_DEF(a_Name) \
111	static VBOXSTRICTRC a_Name(PVMCPU pVCpu) RT_NO_THROW_DEF
112	#undef FNIEMOP_DEF_1
113	#define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
114	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
115	#undef FNIEMOP_DEF_2
116	#define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
117	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
118
119	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPU pVCpu, uint8_t bRm);
120	#undef FNIEMOPRM_DEF
121	#define FNIEMOPRM_DEF(a_Name) \
122	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint8_t bRm) RT_NO_THROW_DEF
123
124	#undef IEM_NOT_REACHED_DEFAULT_CASE_RET
125	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: return VERR_IPE_NOT_REACHED_DEFAULT_CASE
126	#undef IEM_RETURN_ASPECT_NOT_IMPLEMENTED
127	#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
128	#undef IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG
129	#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
130
131
132	#define IEM_OPCODE_GET_NEXT_U8(a_pu8) do { (a_pu8) = g_bRandom; CHK_PTYPE(uint8_t , a_pu8); } while (0)
133	#define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { (a_pi8) = g_bRandom; CHK_PTYPE(int8_t , a_pi8); } while (0)
134	#define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) do { (a_pu16) = g_bRandom; CHK_PTYPE(uint16_t , a_pu16); } while (0)
135	#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
136	#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
137	#define IEM_OPCODE_GET_NEXT_U16(a_pu16) do { (a_pu16) = g_bRandom; CHK_PTYPE(uint16_t , a_pu16); } while (0)
138	#define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
139	#define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
140	#define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { (a_pi16) = g_bRandom; CHK_PTYPE(int16_t , a_pi16); } while (0)
141	#define IEM_OPCODE_GET_NEXT_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
142	#define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
143	#define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { (a_pi32) = g_bRandom; CHK_PTYPE(int32_t , a_pi32); } while (0)
144	#define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
145	#define IEM_OPCODE_GET_NEXT_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
146	#define IEMOP_HLP_MIN_186() do { } while (0)
147	#define IEMOP_HLP_MIN_286() do { } while (0)
148	#define IEMOP_HLP_MIN_386() do { } while (0)
149	#define IEMOP_HLP_MIN_386_EX(a_fTrue) do { } while (0)
150	#define IEMOP_HLP_MIN_486() do { } while (0)
151	#define IEMOP_HLP_MIN_586() do { } while (0)
152	#define IEMOP_HLP_MIN_686() do { } while (0)
153	#define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0)
154	#define IEMOP_HLP_NO_64BIT() do { } while (0)
155	#define IEMOP_HLP_ONLY_64BIT() do { } while (0)
156	#define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0)
157	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0)
158	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX() do { } while (0)
159	#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0)
160	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0)
161	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(a_fFeature) do { } while (0)
162	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(a_fFeature1, a_fFeature2) do { } while (0)
163	#define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0)
164	#define IEMOP_HLP_DONE_VEX_DECODING_EX(a_fFeature) do { } while (0)
165	#define IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeature) do { } while (0)
166	#define IEMOP_HLP_DONE_VEX_DECODING_L1_EX(a_fFeature) do { } while (0)
167	#define IEMOP_HLP_DONE_VEX_DECODING_L0() do { } while (0)
168	#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV() do { } while (0)
169	#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(a_fFeature) do { } while (0)
170	#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV() do { } while (0)
171	#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(a_fFeature) do { } while (0)
172	#define IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(a_fFeature) do { } while (0)
173	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() do { } while (0)
174	#define IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES() do { } while (0)
175	#define IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE(pVCpu, a_fFeature) do { } while (0)
176	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
177	# define IEMOP_HLP_VMX_INSTR(a_szInstr, a_InsDiagPrefix) do { } while (0)
178	# define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) do { } while (0)
179	#endif
180
181
182	#define IEMOP_HLP_DONE_DECODING() do { } while (0)
183
184	#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) do { } while (0)
185	#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) do { } while (0)
186	#undef IEMOP_RAISE_DIVIDE_ERROR_RET
187	#define IEMOP_RAISE_DIVIDE_ERROR_RET() return VERR_TRPM_ACTIVE_TRAP
188	#undef IEMOP_RAISE_INVALID_OPCODE_RET
189	#define IEMOP_RAISE_INVALID_OPCODE_RET() return VERR_TRPM_ACTIVE_TRAP
190	#undef IEMOP_RAISE_INVALID_LOCK_PREFIX_RET
191	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() return VERR_TRPM_ACTIVE_TRAP
192	#define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) do { } while (0)
193	#define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
194	#define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
195	#define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
196	#define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
197	#define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) do { } while (0)
198	#define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
199	#define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
200	#define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
201	#define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
202	#define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) do { } while (0)
203	#define IEMOP_BITCH_ABOUT_STUB() do { } while (0)
204	#define FNIEMOP_STUB(a_Name) \
205	FNIEMOP_DEF(a_Name) { return VERR_NOT_IMPLEMENTED; } \
206	typedef int ignore_semicolon
207	#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
208	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return VERR_NOT_IMPLEMENTED; } \
209	typedef int ignore_semicolon
210
211	#define FNIEMOP_UD_STUB(a_Name) \
212	FNIEMOP_DEF(a_Name) { IEMOP_RAISE_INVALID_OPCODE_RET(); } \
213	typedef int ignore_semicolon
214	#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
215	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { IEMOP_RAISE_INVALID_OPCODE_RET(); } \
216	typedef int ignore_semicolon
217
218
219	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
220	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
221	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
222
223	#undef IEM_IS_REAL_OR_V86_MODE
224	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (g_fRandom)
225	#undef IEM_IS_LONG_MODE
226	#define IEM_IS_LONG_MODE(a_pVCpu) (g_fRandom)
227	#undef IEM_IS_REAL_MODE
228	#define IEM_IS_REAL_MODE(a_pVCpu) (g_fRandom)
229	#undef IEM_IS_GUEST_CPU_AMD
230	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) (g_fRandom)
231	#undef IEM_IS_GUEST_CPU_INTEL
232	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) (g_fRandom)
233	#undef IEM_GET_GUEST_CPU_FEATURES
234	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)42)
235	#undef IEM_GET_HOST_CPU_FEATURES
236	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)88)
237
238	#define iemRecalEffOpSize(a_pVCpu) do { } while (0)
239
240	#undef IEMTARGETCPU_EFL_BEHAVIOR_SELECT
241	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) NULL
242	#undef IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE
243	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) NULL
244	#undef IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
245	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) NULL
246
247	#undef IEM_SELECT_HOST_OR_FALLBACK
248	#define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) NULL
249
250	#define iemAImpl_fpu_r32_to_r80 NULL
251	#define iemAImpl_fcom_r80_by_r32 NULL
252	#define iemAImpl_fadd_r80_by_r32 NULL
253	#define iemAImpl_fmul_r80_by_r32 NULL
254	#define iemAImpl_fsub_r80_by_r32 NULL
255	#define iemAImpl_fsubr_r80_by_r32 NULL
256	#define iemAImpl_fdiv_r80_by_r32 NULL
257	#define iemAImpl_fdivr_r80_by_r32 NULL
258
259	#define iemAImpl_fpu_r64_to_r80 NULL
260	#define iemAImpl_fadd_r80_by_r64 NULL
261	#define iemAImpl_fmul_r80_by_r64 NULL
262	#define iemAImpl_fcom_r80_by_r64 NULL
263	#define iemAImpl_fsub_r80_by_r64 NULL
264	#define iemAImpl_fsubr_r80_by_r64 NULL
265	#define iemAImpl_fdiv_r80_by_r64 NULL
266	#define iemAImpl_fdivr_r80_by_r64 NULL
267
268	#define iemAImpl_fadd_r80_by_r80 NULL
269	#define iemAImpl_fmul_r80_by_r80 NULL
270	#define iemAImpl_fsub_r80_by_r80 NULL
271	#define iemAImpl_fsubr_r80_by_r80 NULL
272	#define iemAImpl_fdiv_r80_by_r80 NULL
273	#define iemAImpl_fdivr_r80_by_r80 NULL
274	#define iemAImpl_fprem_r80_by_r80 NULL
275	#define iemAImpl_fprem1_r80_by_r80 NULL
276	#define iemAImpl_fscale_r80_by_r80 NULL
277
278	#define iemAImpl_fpatan_r80_by_r80 NULL
279	#define iemAImpl_fyl2x_r80_by_r80 NULL
280	#define iemAImpl_fyl2xp1_r80_by_r80 NULL
281
282	#define iemAImpl_fcom_r80_by_r80 NULL
283	#define iemAImpl_fucom_r80_by_r80 NULL
284	#define iemAImpl_fabs_r80 NULL
285	#define iemAImpl_fchs_r80 NULL
286	#define iemAImpl_ftst_r80 NULL
287	#define iemAImpl_fxam_r80 NULL
288	#define iemAImpl_f2xm1_r80 NULL
289	#define iemAImpl_fsqrt_r80 NULL
290	#define iemAImpl_frndint_r80 NULL
291	#define iemAImpl_fsin_r80 NULL
292	#define iemAImpl_fcos_r80 NULL
293
294	#define iemAImpl_fld1 NULL
295	#define iemAImpl_fldl2t NULL
296	#define iemAImpl_fldl2e NULL
297	#define iemAImpl_fldpi NULL
298	#define iemAImpl_fldlg2 NULL
299	#define iemAImpl_fldln2 NULL
300	#define iemAImpl_fldz NULL
301
302	#define iemAImpl_fptan_r80_r80 NULL
303	#define iemAImpl_fxtract_r80_r80 NULL
304	#define iemAImpl_fsincos_r80_r80 NULL
305
306	#define iemAImpl_fiadd_r80_by_i16 NULL
307	#define iemAImpl_fimul_r80_by_i16 NULL
308	#define iemAImpl_fisub_r80_by_i16 NULL
309	#define iemAImpl_fisubr_r80_by_i16 NULL
310	#define iemAImpl_fidiv_r80_by_i16 NULL
311	#define iemAImpl_fidivr_r80_by_i16 NULL
312
313	#define iemAImpl_fiadd_r80_by_i32 NULL
314	#define iemAImpl_fimul_r80_by_i32 NULL
315	#define iemAImpl_fisub_r80_by_i32 NULL
316	#define iemAImpl_fisubr_r80_by_i32 NULL
317	#define iemAImpl_fidiv_r80_by_i32 NULL
318	#define iemAImpl_fidivr_r80_by_i32 NULL
319
320	#define iemCImpl_callf NULL
321	#define iemCImpl_FarJmp NULL
322
323	#define iemAImpl_pshufhw_u128 NULL
324	#define iemAImpl_pshuflw_u128 NULL
325	#define iemAImpl_pshufd_u128 NULL
326	#define iemAImpl_punpcklbw_u64 NULL
327	#define iemAImpl_punpcklwd_u64 NULL
328	#define iemAImpl_punpckldq_u64 NULL
329	#define iemAImpl_punpckhbw_u64 NULL
330	#define iemAImpl_punpckhwd_u64 NULL
331	#define iemAImpl_punpckhdq_u64 NULL
332	#define iemAImpl_packsswb_u64 NULL
333	#define iemAImpl_packssdw_u64 NULL
334	#define iemAImpl_packuswb_u64 NULL
335
336	#define iemAImpl_punpcklbw_u128 NULL
337	#define iemAImpl_punpcklwd_u128 NULL
338	#define iemAImpl_punpckldq_u128 NULL
339	#define iemAImpl_punpcklqdq_u128 NULL
340	#define iemAImpl_punpckhbw_u128 NULL
341	#define iemAImpl_punpckhwd_u128 NULL
342	#define iemAImpl_punpckhdq_u128 NULL
343	#define iemAImpl_punpckhqdq_u128 NULL
344	#define iemAImpl_packsswb_u128 NULL
345	#define iemAImpl_packssdw_u128 NULL
346	#define iemAImpl_packuswb_u128 NULL
347	#define iemAImpl_packusdw_u128 NULL
348
349
350	#define iemAImpl_pand_u64 NULL
351	#define iemAImpl_pandn_u64 NULL
352	#define iemAImpl_por_u64 NULL
353	#define iemAImpl_pxor_u64 NULL
354	#define iemAImpl_pcmpeqb_u64 NULL
355	#define iemAImpl_pcmpeqw_u64 NULL
356	#define iemAImpl_pcmpeqd_u64 NULL
357	#define iemAImpl_pcmpgtb_u64 NULL
358	#define iemAImpl_pcmpgtw_u64 NULL
359	#define iemAImpl_pcmpgtd_u64 NULL
360	#define iemAImpl_paddb_u64 NULL
361	#define iemAImpl_paddw_u64 NULL
362	#define iemAImpl_paddd_u64 NULL
363	#define iemAImpl_paddq_u64 NULL
364	#define iemAImpl_psubb_u64 NULL
365	#define iemAImpl_psubw_u64 NULL
366	#define iemAImpl_psubd_u64 NULL
367	#define iemAImpl_psubq_u64 NULL
368
369	#define iemAImpl_pand_u128 NULL
370	#define iemAImpl_pandn_u128 NULL
371	#define iemAImpl_por_u128 NULL
372	#define iemAImpl_pxor_u128 NULL
373	#define iemAImpl_pcmpeqb_u128 NULL
374	#define iemAImpl_pcmpeqw_u128 NULL
375	#define iemAImpl_pcmpeqd_u128 NULL
376	#define iemAImpl_pcmpgtb_u128 NULL
377	#define iemAImpl_pcmpgtw_u128 NULL
378	#define iemAImpl_pcmpgtd_u128 NULL
379	#define iemAImpl_paddb_u128 NULL
380	#define iemAImpl_paddw_u128 NULL
381	#define iemAImpl_paddd_u128 NULL
382	#define iemAImpl_paddq_u128 NULL
383	#define iemAImpl_psubb_u128 NULL
384	#define iemAImpl_psubw_u128 NULL
385	#define iemAImpl_psubd_u128 NULL
386	#define iemAImpl_psubq_u128 NULL
387
388	#define iemAImpl_psllw_u64 NULL
389	#define iemAImpl_psrlw_u64 NULL
390	#define iemAImpl_psraw_u64 NULL
391	#define iemAImpl_pslld_u64 NULL
392	#define iemAImpl_psrld_u64 NULL
393	#define iemAImpl_psrad_u64 NULL
394	#define iemAImpl_psllq_u64 NULL
395	#define iemAImpl_psrlq_u64 NULL
396	#define iemAImpl_psraq_u64 NULL
397
398	#define iemAImpl_psllw_u128 NULL
399	#define iemAImpl_psrlw_u128 NULL
400	#define iemAImpl_psraw_u128 NULL
401	#define iemAImpl_pslld_u128 NULL
402	#define iemAImpl_psrld_u128 NULL
403	#define iemAImpl_psrad_u128 NULL
404	#define iemAImpl_psllq_u128 NULL
405	#define iemAImpl_psrlq_u128 NULL
406	#define iemAImpl_psraq_u128 NULL
407
408	#define iemAImpl_psllw_imm_u64 NULL
409	#define iemAImpl_psrlw_imm_u64 NULL
410	#define iemAImpl_psraw_imm_u64 NULL
411	#define iemAImpl_pslld_imm_u64 NULL
412	#define iemAImpl_psrld_imm_u64 NULL
413	#define iemAImpl_psrad_imm_u64 NULL
414	#define iemAImpl_psllq_imm_u64 NULL
415	#define iemAImpl_psrlq_imm_u64 NULL
416	#define iemAImpl_psraq_imm_u64 NULL
417
418	#define iemAImpl_psllw_imm_u128 NULL
419	#define iemAImpl_psrlw_imm_u128 NULL
420	#define iemAImpl_psraw_imm_u128 NULL
421	#define iemAImpl_pslld_imm_u128 NULL
422	#define iemAImpl_psrld_imm_u128 NULL
423	#define iemAImpl_psrad_imm_u128 NULL
424	#define iemAImpl_psllq_imm_u128 NULL
425	#define iemAImpl_psrlq_imm_u128 NULL
426	#define iemAImpl_psraq_imm_u128 NULL
427
428	#define iemAImpl_pslldq_imm_u128 NULL
429	#define iemAImpl_psrldq_imm_u128 NULL
430
431	#define iemAImpl_paddsb_u64 NULL
432	#define iemAImpl_paddusb_u64 NULL
433	#define iemAImpl_paddsw_u64 NULL
434	#define iemAImpl_paddusw_u64 NULL
435	#define iemAImpl_psubsb_u64 NULL
436	#define iemAImpl_psubusb_u64 NULL
437	#define iemAImpl_psubsw_u64 NULL
438	#define iemAImpl_psubusw_u64 NULL
439
440	#define iemAImpl_paddsb_u128 NULL
441	#define iemAImpl_paddusb_u128 NULL
442	#define iemAImpl_paddsw_u128 NULL
443	#define iemAImpl_paddusw_u128 NULL
444	#define iemAImpl_psubsb_u128 NULL
445	#define iemAImpl_psubusb_u128 NULL
446	#define iemAImpl_psubsw_u128 NULL
447	#define iemAImpl_psubusw_u128 NULL
448
449	#define iemAImpl_pmullw_u64 NULL
450	#define iemAImpl_pmulhw_u64 NULL
451	#define iemAImpl_pmulhuw_u64 NULL
452	#define iemAImpl_pmaddwd_u64 NULL
453
454	#define iemAImpl_pmullw_u128 NULL
455	#define iemAImpl_pmulhw_u128 NULL
456	#define iemAImpl_pmulhuw_u128 NULL
457	#define iemAImpl_pmaddwd_u128 NULL
458
459	#define iemAImpl_pmaxub_u64 NULL
460	#define iemAImpl_pmaxsw_u64 NULL
461	#define iemAImpl_pminub_u64 NULL
462	#define iemAImpl_pminsw_u64 NULL
463	#define iemAImpl_pavgb_u64 NULL
464	#define iemAImpl_pavgw_u64 NULL
465	#define iemAImpl_psadbw_u64 NULL
466	#define iemAImpl_pmuludq_u64 NULL
467
468	#define iemAImpl_pmaxub_u128 NULL
469	#define iemAImpl_pmaxsw_u128 NULL
470	#define iemAImpl_pminub_u128 NULL
471	#define iemAImpl_pminsw_u128 NULL
472	#define iemAImpl_pavgb_u128 NULL
473	#define iemAImpl_pavgw_u128 NULL
474	#define iemAImpl_psadbw_u128 NULL
475	#define iemAImpl_pmuludq_u128 NULL
476	#define iemAImpl_unpcklps_u128 NULL
477	#define iemAImpl_unpcklpd_u128 NULL
478	#define iemAImpl_unpckhps_u128 NULL
479	#define iemAImpl_unpckhpd_u128 NULL
480
481	#define iemAImpl_addps_u128 NULL
482	#define iemAImpl_addpd_u128 NULL
483	#define iemAImpl_mulps_u128 NULL
484	#define iemAImpl_mulpd_u128 NULL
485	#define iemAImpl_subps_u128 NULL
486	#define iemAImpl_subpd_u128 NULL
487	#define iemAImpl_minps_u128 NULL
488	#define iemAImpl_minpd_u128 NULL
489	#define iemAImpl_divps_u128 NULL
490	#define iemAImpl_divpd_u128 NULL
491	#define iemAImpl_maxps_u128 NULL
492	#define iemAImpl_maxpd_u128 NULL
493	#define iemAImpl_haddps_u128 NULL
494	#define iemAImpl_haddpd_u128 NULL
495	#define iemAImpl_hsubps_u128 NULL
496	#define iemAImpl_hsubpd_u128 NULL
497	#define iemAImpl_sqrtps_u128 NULL
498	#define iemAImpl_sqrtpd_u128 NULL
499	#define iemAImpl_rsqrtps_u128 NULL
500	#define iemAImpl_addsubps_u128 NULL
501	#define iemAImpl_addsubpd_u128 NULL
502	#define iemAImpl_cvtpd2ps_u128 NULL
503	#define iemAImpl_cvtps2pd_u128 NULL
504	#define iemAImpl_shufpd_u128 NULL
505	#define iemAImpl_shufps_u128 NULL
506	#define iemAImpl_roundps_u128 NULL
507	#define iemAImpl_roundpd_u128 NULL
508
509	#define iemAImpl_cvtdq2ps_u128 NULL
510	#define iemAImpl_cvtps2dq_u128 NULL
511	#define iemAImpl_cvttps2dq_u128 NULL
512	#define iemAImpl_cvttpd2dq_u128 NULL
513	#define iemAImpl_cvtdq2pd_u128 NULL
514	#define iemAImpl_cvtpd2dq_u128 NULL
515
516	#define iemAImpl_addss_u128_r32 NULL
517	#define iemAImpl_addsd_u128_r64 NULL
518	#define iemAImpl_mulss_u128_r32 NULL
519	#define iemAImpl_mulsd_u128_r64 NULL
520	#define iemAImpl_subss_u128_r32 NULL
521	#define iemAImpl_subsd_u128_r64 NULL
522	#define iemAImpl_minss_u128_r32 NULL
523	#define iemAImpl_minsd_u128_r64 NULL
524	#define iemAImpl_divss_u128_r32 NULL
525	#define iemAImpl_divsd_u128_r64 NULL
526	#define iemAImpl_maxss_u128_r32 NULL
527	#define iemAImpl_maxsd_u128_r64 NULL
528	#define iemAImpl_sqrtss_u128_r32 NULL
529	#define iemAImpl_sqrtsd_u128_r64 NULL
530	#define iemAImpl_roundss_u128_r32 NULL
531	#define iemAImpl_roundsd_u128_r64 NULL
532	#define iemAImpl_rsqrtss_u128_r32 NULL
533
534	#define iemAImpl_cvtss2sd_u128_r32 NULL
535	#define iemAImpl_cvtsd2ss_u128_r64 NULL
536
537	/** @} */
538
539
540	#define IEM_REPEAT_0(a_Callback, a_User) do { } while (0)
541	#define IEM_REPEAT_1(a_Callback, a_User) a_Callback##_CALLBACK(0, a_User)
542	#define IEM_REPEAT_2(a_Callback, a_User) IEM_REPEAT_1(a_Callback, a_User); a_Callback##_CALLBACK(1, a_User)
543	#define IEM_REPEAT_3(a_Callback, a_User) IEM_REPEAT_2(a_Callback, a_User); a_Callback##_CALLBACK(2, a_User)
544	#define IEM_REPEAT_4(a_Callback, a_User) IEM_REPEAT_3(a_Callback, a_User); a_Callback##_CALLBACK(3, a_User)
545	#define IEM_REPEAT_5(a_Callback, a_User) IEM_REPEAT_4(a_Callback, a_User); a_Callback##_CALLBACK(4, a_User)
546	#define IEM_REPEAT_6(a_Callback, a_User) IEM_REPEAT_5(a_Callback, a_User); a_Callback##_CALLBACK(5, a_User)
547	#define IEM_REPEAT_7(a_Callback, a_User) IEM_REPEAT_6(a_Callback, a_User); a_Callback##_CALLBACK(6, a_User)
548	#define IEM_REPEAT_8(a_Callback, a_User) IEM_REPEAT_7(a_Callback, a_User); a_Callback##_CALLBACK(7, a_User)
549	#define IEM_REPEAT_9(a_Callback, a_User) IEM_REPEAT_8(a_Callback, a_User); a_Callback##_CALLBACK(8, a_User)
550	#define IEM_REPEAT(a_cTimes, a_Callback, a_User) RT_CONCAT(IEM_REPEAT_,a_cTimes)(a_Callback, a_User)
551
552
553
554	/** @name Microcode test stubs
555	* @{ */
556
557	#define IEM_ARG_CHECK_CALLBACK(a_idx, a_User) int RT_CONCAT(iArgCheck_,a_idx); NOREF(RT_CONCAT(iArgCheck_,a_idx))
558	#define IEM_MC_BEGIN(a_cArgs, a_cLocals) \
559	{ \
560	const uint8_t cArgs = (a_cArgs); NOREF(cArgs); \
561	const uint8_t cLocals = (a_cLocals); NOREF(cLocals); \
562	const uint8_t fMcBegin = (a_cArgs) + (a_cLocals); \
563	IEM_REPEAT(a_cArgs, IEM_ARG_CHECK, 0); \
564
565	#define IEM_MC_END() \
566	}
567
568	#define IEM_MC_ADVANCE_RIP_AND_FINISH() do { (void)fMcBegin; return VINF_SUCCESS; } while (0)
569	#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) do { (void)fMcBegin; CHK_TYPE(int8_t, a_i8); return VINF_SUCCESS; } while (0)
570	#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) do { (void)fMcBegin; CHK_TYPE(int16_t, a_i16); return VINF_SUCCESS; } while (0)
571	#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) do { (void)fMcBegin; CHK_TYPE(int32_t, a_i32); return VINF_SUCCESS; } while (0)
572	#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) do { (void)fMcBegin; CHK_TYPE(uint16_t, a_u16NewIP); return VINF_SUCCESS; } while (0)
573	#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) do { (void)fMcBegin; CHK_TYPE(uint32_t, a_u32NewIP); return VINF_SUCCESS; } while (0)
574	#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) do { (void)fMcBegin; CHK_TYPE(uint64_t, a_u64NewIP); return VINF_SUCCESS; } while (0)
575	#define IEM_MC_RAISE_DIVIDE_ERROR() do { (void)fMcBegin; return VERR_TRPM_ACTIVE_TRAP; } while (0)
576	#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do { (void)fMcBegin; } while (0)
577	#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() do { (void)fMcBegin; } while (0)
578	#define IEM_MC_MAYBE_RAISE_FPU_XCPT() do { (void)fMcBegin; } while (0)
579	#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do { (void)fMcBegin; } while (0)
580	#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() do { (void)fMcBegin; } while (0)
581	#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() do { (void)fMcBegin; } while (0)
582	#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do { (void)fMcBegin; } while (0)
583	#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
584	do { (void)fMcBegin; AssertCompile(RT_IS_POWER_OF_TWO(a_cbAlign)); CHK_TYPE(RTGCPTR, a_EffAddr); } while (0)
585	#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() do { (void)fMcBegin; } while (0)
586	#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) do { (void)fMcBegin; } while (0)
587	#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() do { (void)fMcBegin; } while (0)
588	#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() do { (void)fMcBegin; } while (0)
589
590	#define IEM_MC_LOCAL(a_Type, a_Name) (void)fMcBegin; \
591	a_Type a_Name; NOREF(a_Name); (void)fMcBegin
592	#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) (void)fMcBegin; \
593	a_Type const a_Name = (a_Value); \
594	NOREF(a_Name)
595	#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (void)fMcBegin; \
596	(a_pRefArg) = &(a_Local)
597
598	#define IEM_MC_ARG(a_Type, a_Name, a_iArg) (void)fMcBegin; \
599	RT_CONCAT(iArgCheck_,a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
600	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
601	AssertCompile((a_iArg) < cArgs); \
602	a_Type a_Name; \
603	NOREF(a_Name)
604	#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) (void)fMcBegin; \
605	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
606	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
607	AssertCompile((a_iArg) < cArgs); \
608	a_Type const a_Name = (a_Value); \
609	NOREF(a_Name)
610	#define IEM_MC_ARG_XSTATE(a_Name, a_iArg) \
611	IEM_MC_ARG_CONST(PX86XSAVEAREA, a_Name, NULL, a_iArg)
612
613	#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) (void)fMcBegin; \
614	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
615	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
616	AssertCompile((a_iArg) < cArgs); \
617	a_Type const a_Name = &(a_Local); \
618	NOREF(a_Name)
619	#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) (void)fMcBegin; \
620	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
621	int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \
622	AssertCompile((a_iArg) < cArgs); \
623	uint32_t a_Name; \
624	uint32_t *a_pName = &a_Name; \
625	NOREF(a_pName)
626
627	#define IEM_MC_COMMIT_EFLAGS(a_EFlags) do { CHK_TYPE(uint32_t, a_EFlags); (void)fMcBegin; } while (0)
628	#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) do { (a_VarOrArg) = (0); (void)fMcBegin; } while (0)
629	#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
630	#define IEM_MC_ASSIGN_U8_SX_U64 IEM_MC_ASSIGN
631	#define IEM_MC_ASSIGN_U32_SX_U64 IEM_MC_ASSIGN
632
633	#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) do { (a_u8Dst) = 0; CHK_TYPE(uint8_t, a_u8Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
634	#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
635	#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
636	#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
637	#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
638	#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
639	#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
640	#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
641	#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
642	#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
643	#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
644	#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
645	#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
646	#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
647	#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
648	#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
649	#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
650	#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
651	#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
652	#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
653	#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
654	#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
655	#define IEM_MC_FETCH_EFLAGS(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint32_t, a_EFlags); (void)fMcBegin; } while (0)
656	#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint8_t, a_EFlags); (void)fMcBegin; } while (0)
657	#define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); (void)fFpuRead; (void)fMcBegin; } while (0)
658	#define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); (void)fFpuRead; (void)fMcBegin; } while (0)
659	#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) do { CHK_GREG_IDX(a_iGReg); CHK_TYPE(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
660	#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) do { CHK_GREG_IDX(a_iGReg); CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
661	#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) do { CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
662	#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) do { CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
663	#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) do { CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
664	#define IEM_MC_STORE_GREG_U8_CONST(a_iGReg, a_u8C) do { CHK_GREG_IDX(a_iGReg); AssertCompile((uint8_t )(a_u8C) == (a_u8C) ); (void)fMcBegin; } while (0)
665	#define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16C) do { CHK_GREG_IDX(a_iGReg); AssertCompile((uint16_t)(a_u16C) == (a_u16C)); (void)fMcBegin; } while (0)
666	#define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32C) do { CHK_GREG_IDX(a_iGReg); AssertCompile((uint32_t)(a_u32C) == (a_u32C)); (void)fMcBegin; } while (0)
667	#define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u64C) do { CHK_GREG_IDX(a_iGReg); AssertCompile((uint64_t)(a_u64C) == (a_u64C)); (void)fMcBegin; } while (0)
668	#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) do { CHK_PTYPE(PCRTFLOAT80U, a_pr80Src); Assert((a_iSt) < 8); (void)fMcBegin; } while (0)
669	#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) do { CHK_GREG_IDX(a_iGReg); (void)fMcBegin; } while (0)
670	#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { CHK_PTYPE(uint32_t *, a_pu32Dst); (void)fMcBegin; } while (0)
671	#define IEM_MC_STORE_SREG_BASE_U64(a_iSeg, a_u64Value) do { (void)fMcBegin; CHK_SEG_IDX(a_iSeg); } while (0)
672	#define IEM_MC_STORE_SREG_BASE_U32(a_iSeg, a_u32Value) do { (void)fMcBegin; CHK_SEG_IDX(a_iSeg); } while (0)
673	#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu8Dst) = (uint8_t )((uintptr_t)0); CHK_PTYPE(uint8_t , a_pu8Dst); (void)fMcBegin; } while (0)
674	#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu16Dst) = (uint16_t )((uintptr_t)0); CHK_PTYPE(uint16_t , a_pu16Dst); (void)fMcBegin; } while (0)
675	#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu32Dst) = (uint32_t )((uintptr_t)0); CHK_PTYPE(uint32_t , a_pu32Dst); (void)fMcBegin; } while (0)
676	#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi32Dst) = (int32_t )((uintptr_t)0); CHK_PTYPE(int32_t , a_pi32Dst); (void)fMcBegin; } while (0)
677	#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi32Dst) = (int32_t const )((uintptr_t)0); CHK_PTYPE(int32_t const , a_pi32Dst); (void)fMcBegin; } while (0)
678	#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pu64Dst) = (uint64_t )((uintptr_t)0); CHK_PTYPE(uint64_t , a_pu64Dst); (void)fMcBegin; } while (0)
679	#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi64Dst) = (int64_t )((uintptr_t)0); CHK_PTYPE(int64_t , a_pi64Dst); (void)fMcBegin; } while (0)
680	#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_pi64Dst) = (int64_t const )((uintptr_t)0); CHK_PTYPE(int64_t const , a_pi64Dst); (void)fMcBegin; } while (0)
681	#define IEM_MC_REF_EFLAGS(a_pEFlags) do { (a_pEFlags) = (uint32_t )((uintptr_t)0); CHK_PTYPE(uint32_t , a_pEFlags); (void)fMcBegin; } while (0)
682	#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) do { (a_pr80Dst) = (PRTFLOAT80U)((uintptr_t)0); CHK_PTYPE(PCRTFLOAT80U, a_pr80Dst); AssertCompile((a_iSt) < 8); (void)fMcBegin; } while (0)
683	#define IEM_MC_REF_MXCSR(a_pfMxcsr) do { (a_pfMxcsr) = (uint32_t )((uintptr_t)0); CHK_PTYPE(uint32_t , a_pfMxcsr); (void)fMcBegin; (void)fSseRead; } while (0)
684
685	#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
686	#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
687	#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
688	#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
689	#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
690	#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
691	#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
692	#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
693	#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { CHK_CONST(uint16_t, a_u16Const); (void)fMcBegin; } while (0)
694
695	#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
696	#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
697	#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
698	#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
699	#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
700	#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
701	#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
702	#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) do { CHK_GREG_IDX(a_iGReg); CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
703
704	#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u16Value, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_u8Value) += 1; CHK_TYPE(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
705	#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_u16Value) += 1; CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
706	#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_u32Value) += 1; CHK_TYPE(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
707	#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { CHK_GREG_IDX(a_iGReg); (a_u64Value) += 1; CHK_TYPE(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
708	#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
709	#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
710	#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
711	#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); (void)fMcBegin; } while (0)
712	#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
713	#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
714	#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Local); CHK_CONST(uint64_t, a_u64Mask); (void)fMcBegin; } while (0)
715	#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Arg); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
716	#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Arg); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
717	#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Arg); CHK_CONST(uint64_t, a_u64Mask); (void)fMcBegin; } while (0)
718	#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) \|= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); (void)fMcBegin; } while (0)
719	#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) \|= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
720	#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
721	#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
722	#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
723	#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
724	#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
725	#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
726	#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
727	#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
728	#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); (void)fMcBegin; } while (0)
729	#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); (void)fMcBegin; } while (0)
730	#define IEM_MC_SET_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
731	#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
732	#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
733	#define IEM_MC_CLEAR_FSW_EX() do { (void)fMcBegin; } while (0)
734	#define IEM_MC_FPU_TO_MMX_MODE() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
735	#define IEM_MC_FPU_FROM_MMX_MODE() do { (void)fMcBegin; } while (0)
736
737	#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) do { CHK_TYPE(uint16_t, a_u16Local); (void)fMcBegin; } while (0)
738	#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) do { CHK_TYPE(uint32_t, a_u32Local);( void)fMcBegin; } while (0)
739	#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) do { CHK_TYPE(uint64_t, a_u64Local); (void)fMcBegin; } while (0)
740
741	#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { CHK_MREG_IDX(a_iMReg); (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fFpuRead; (void)fMcBegin; } while (0)
742	#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { CHK_MREG_IDX(a_iMReg); (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fFpuRead; (void)fMcBegin; } while (0)
743	#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_MREG_IDX(a_iMReg); CHK_TYPE(uint64_t, a_u64Value); (void)fFpuWrite; (void)fMcBegin; } while (0)
744	#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_MREG_IDX(a_iMReg); CHK_TYPE(uint32_t, a_u32Value); (void)fFpuWrite; (void)fMcBegin; } while (0)
745	#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { CHK_MREG_IDX(a_iMReg); (a_pu64Dst) = (uint64_t )((uintptr_t)0); CHK_PTYPE(uint64_t , a_pu64Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
746	#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { CHK_MREG_IDX(a_iMReg); (a_pu64Dst) = (uint64_t const )((uintptr_t)0); CHK_PTYPE(uint64_t const , a_pu64Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
747	#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { CHK_MREG_IDX(a_iMReg); (a_pu32Dst) = (uint32_t const )((uintptr_t)0); CHK_PTYPE(uint32_t const , a_pu32Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
748	#define IEM_MC_MODIFIED_MREG(a_iMReg) do { CHK_MREG_IDX(a_iMReg); (void)fFpuWrite; (void)fMcBegin; } while (0)
749	#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) do { AssertCompile(sizeof(*a_pu64Dst) <= sizeof(uint64_t)); (void)fFpuWrite; (void)fMcBegin; } while (0)
750
751	#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint8_t, a_bMask); (void)fSseRead; (void)fMcBegin; } while (0)
752	#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_u128Value) = g_u128Zero; CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseRead; (void)fMcBegin; } while (0)
753	#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_XmmValue) = g_XmmZero; CHK_TYPE(X86XMMREG, a_XmmValue); (void)fSseRead; (void)fMcBegin; } while (0)
754	#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) do { CHK_XREG_IDX(a_iXReg); (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; (void)fMcBegin; } while (0)
755	#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) do { CHK_XREG_IDX(a_iXReg); (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fSseRead; (void)fMcBegin; } while (0)
756	#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord ) do { CHK_XREG_IDX(a_iXReg); (a_u16Value) = 0; CHK_TYPE(uint16_t, a_u16Value); (void)fSseRead; (void)fMcBegin; } while (0)
757	#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) do { CHK_XREG_IDX(a_iXReg); (a_u8Value) = 0; CHK_TYPE(uint8_t, a_u8Value); (void)fSseRead; (void)fMcBegin; } while (0)
758	#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(RTUINT128U, a_u128Value); AssertCompile((a_iDwDst) < RT_ELEMENTS((a_u128Value).au32)); AssertCompile((a_iDwSrc) < RT_ELEMENTS((a_u128Value).au32)); (void)fSseWrite; (void)fMcBegin; } while (0)
759	#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseWrite; (void)fMcBegin; } while (0)
760	#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) do { CHK_TYPE(X86XMMREG, a_XmmValue); (void)fSseWrite; (void)fMcBegin; } while (0)
761	#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(X86XMMREG, a_XmmValue); AssertCompile((a_iDword) < RT_ELEMENTS((a_XmmValue).au32)); (void)fSseWrite; (void)fMcBegin; } while (0)
762	#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(X86XMMREG, a_XmmValue); AssertCompile((a_iQword) < RT_ELEMENTS((a_XmmValue).au64)); (void)fSseWrite; (void)fMcBegin; } while (0)
763	#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
764	#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
765	#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; (void)fMcBegin; } while (0)
766	#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint16_t, a_u16Value); (void)fSseWrite; (void)fMcBegin; } while (0)
767	#define IEM_MC_STORE_XREG_U8( a_iXReg, a_iByte, a_u8Value ) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint8_t, a_u8Value ); (void)fSseWrite; (void)fMcBegin; } while (0)
768	#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; (void)fMcBegin; } while (0)
769	#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
770	#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(RTFLOAT32U, a_r32Value); (void)fSseWrite; (void)fMcBegin; } while (0)
771	#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) do { CHK_XREG_IDX(a_iXReg); CHK_TYPE(RTFLOAT64U, a_r64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
772	#define IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(a_iXRegDst, a_u8Value) do { CHK_XREG_IDX(a_iXRegDst); CHK_TYPE(uint8_t, a_u8Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
773	#define IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(a_iXRegDst, a_u16Value) do { CHK_XREG_IDX(a_iXRegDst); CHK_TYPE(uint16_t, a_u16Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
774	#define IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(a_iXRegDst, a_u32Value) do { CHK_XREG_IDX(a_iXRegDst); CHK_TYPE(uint32_t, a_u32Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
775	#define IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(a_iXRegDst, a_u64Value) do { CHK_XREG_IDX(a_iXRegDst); CHK_TYPE(uint64_t, a_u64Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
776	#define IEM_MC_BROADCAST_XREG_U128_ZX_VLMAX(a_iXRegDst, a_u128Value) do { CHK_XREG_IDX(a_iXRegDst); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
777	#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
778	#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
779	#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pu32Dst) = (uint32_t const )((uintptr_t)0); CHK_PTYPE(uint32_t const , a_pu32Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
780	#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pu64Dst) = (uint64_t const )((uintptr_t)0); CHK_PTYPE(uint64_t const , a_pu64Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
781	#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pr32Dst) = (RTFLOAT32U const )((uintptr_t)0); CHK_PTYPE(RTFLOAT32U const , a_pr32Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
782	#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pr64Dst) = (RTFLOAT64U const )((uintptr_t)0); CHK_PTYPE(RTFLOAT64U const , a_pr64Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
783	#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) do { CHK_XREG_IDX(a_iXReg); (a_pXmmDst) = (PCX86XMMREG)((uintptr_t)0); CHK_PTYPE(PCX86XMMREG, a_pXmmDst); (void)fSseWrite; (void)fMcBegin; } while (0)
784	#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) do { CHK_XREG_IDX(a_iXRegDst); CHK_XREG_IDX(a_iXRegSrc); (void)fSseWrite; (void)fMcBegin; } while (0)
785
786	#define IEM_MC_FETCH_YREG_U256(a_u256Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); (a_u256Value).au64[0] = (a_u256Value).au64[1] = (a_u256Value).au64[2] = (a_u256Value).au64[3] = 0; CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxRead; (void)fMcBegin; } while (0)
787	#define IEM_MC_FETCH_YREG_U128(a_u128Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); (a_u128Value).au64[0] = (a_u128Value).au64[1] = 0; CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxRead; (void)fMcBegin; } while (0)
788	#define IEM_MC_FETCH_YREG_U64(a_u64Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); (a_u64Value) = UINT64_MAX; CHK_TYPE(uint64_t, a_u64Value); (void)fAvxRead; (void)fMcBegin; } while (0)
789	#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); (a_u64Value) = UINT64_MAX; CHK_TYPE(uint64_t, a_u64Value); (void)fAvxRead; (void)fMcBegin; } while (0)
790	#define IEM_MC_FETCH_YREG_U32(a_u32Value, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegSrc); (a_u32Value) = UINT32_MAX; CHK_TYPE(uint32_t, a_u32Value); (void)fAvxRead; (void)fMcBegin; } while (0)
791	#define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
792	#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint32_t, a_u32Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
793	#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint64_t, a_u64Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
794	#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
795	#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
796	#define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint8_t, a_u8Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
797	#define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint16_t, a_u16Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
798	#define IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint32_t, a_u32Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
799	#define IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(uint64_t, a_u64Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
800	#define IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Value) do { CHK_YREG_IDX(a_iYRegDst); CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
801	#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) do { CHK_YREG_IDX(a_iYReg); (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
802	#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) do { CHK_YREG_IDX(a_iYReg); (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
803	#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) do { CHK_YREG_IDX(a_iYReg); (a_pu64Dst) = (uint64_t const )((uintptr_t)0); CHK_PTYPE(uint64_t const , a_pu64Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
804	#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) do { CHK_YREG_IDX(a_iYReg); (void)fAvxWrite; (void)fMcBegin; } while (0)
805	#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrc); (void)fAvxWrite; (void)fMcBegin; } while (0)
806	#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrc); (void)fAvxWrite; (void)fMcBegin; } while (0)
807	#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrc); (void)fAvxWrite; (void)fMcBegin; } while (0)
808	#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); CHK_YREG_IDX(a_iYRegSrc32); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
809	#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); CHK_YREG_IDX(a_iYRegSrc64); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
810	#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); CHK_YREG_IDX(a_iYRegSrc64); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
811	#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); CHK_YREG_IDX(a_iYRegSrc64); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
812	#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
813	#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { CHK_YREG_IDX(a_iYRegDst); CHK_YREG_IDX(a_iYRegSrcHx); (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
814
815	#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u8Dst) == (sizeof(uint8_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
816	#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); AssertCompile(sizeof(a_u8Dst) == (sizeof(uint8_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
817	#define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); AssertCompile(sizeof(a_u8Dst) == (sizeof(uint8_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
818	#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u16Dst) == (sizeof(uint16_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
819	#define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int16_t, a_i16Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
820	#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u32Dst) == (sizeof(uint32_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
821	#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
822	#define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
823	#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
824	#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
825	#define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int64_t, a_i64Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
826
827	#define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
828	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
829	#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
830	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint16_t, a_u16Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
831	#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
832	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint32_t, a_u32Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
833	#define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
834	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
835
836	#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u16Dst) == (sizeof(uint16_t))); (void)fMcBegin; } while (0)
837	#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u32Dst) == (sizeof(uint32_t))); (void)fMcBegin; } while (0)
838	#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
839	#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u32Dst) == (sizeof(uint32_t))); (void)fMcBegin; } while (0)
840	#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
841	#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
842	#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u16Dst) == (sizeof(uint16_t))); (void)fMcBegin; } while (0)
843	#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u32Dst) == (sizeof(uint32_t))); (void)fMcBegin; } while (0)
844	#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
845	#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u32Dst) == (sizeof(uint32_t))); (void)fMcBegin; } while (0)
846	#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
847	#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); AssertCompile(sizeof(a_u64Dst) == (sizeof(uint64_t))); (void)fMcBegin; } while (0)
848	#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst); (void)fMcBegin; } while (0)
849	#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst); (void)fMcBegin; } while (0)
850	#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst); (void)fMcBegin; } while (0)
851	#define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTPBCD80U, a_d80Dst); (void)fMcBegin; } while (0)
852	#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); (void)fMcBegin; } while (0)
853	#define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); (void)fMcBegin; } while (0)
854	#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); (void)fMcBegin; } while (0)
855	#define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(X86XMMREG, a_XmmDst); (void)fMcBegin; } while (0)
856	#define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(X86XMMREG, a_XmmDst); (void)fMcBegin; } while (0)
857	#define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(X86XMMREG, a_XmmDst); (void)fMcBegin; } while (0)
858	#define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(X86XMMREG, a_XmmDst); AssertCompile((a_iDWord) < RT_ELEMENTS((a_XmmDst).au32)); (void)fMcBegin; } while (0)
859	#define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(X86XMMREG, a_XmmDst); AssertCompile((a_iQWord) < RT_ELEMENTS((a_XmmDst).au64)); (void)fMcBegin; } while (0)
860	#define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0)
861	#define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0)
862	#define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0)
863
864	#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
865	#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
866	#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
867	#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
868	#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); (void)fMcBegin; } while (0)
869	#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint16_t, a_u16C); (void)fMcBegin; } while (0)
870	#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint32_t, a_u32C); (void)fMcBegin; } while (0)
871	#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint64_t, a_u64C); (void)fMcBegin; } while (0)
872	#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) do { CHK_TYPE(int8_t *, a_pi8Dst); CHK_CONST(int8_t, a_i8C); (void)fMcBegin; } while (0)
873	#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) do { CHK_TYPE(int16_t *, a_pi16Dst); CHK_CONST(int16_t, a_i16C); (void)fMcBegin; } while (0)
874	#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) do { CHK_TYPE(int32_t *, a_pi32Dst); CHK_CONST(int32_t, a_i32C); (void)fMcBegin; } while (0)
875	#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) do { CHK_TYPE(int64_t *, a_pi64Dst); CHK_CONST(int64_t, a_i64C); (void)fMcBegin; } while (0)
876	#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); (void)fMcBegin; } while (0)
877	#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); (void)fMcBegin; } while (0)
878	#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); (void)fMcBegin; } while (0)
879	#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) do { CHK_TYPE(PRTPBCD80U, a_pd80Dst); (void)fMcBegin; } while (0)
880	#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Src) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Src); (void)fMcBegin; } while (0)
881	#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Src) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Src); (void)fMcBegin; } while (0)
882	#define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Src) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Src); (void)fMcBegin; } while (0)
883	#define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Src) do { CHK_SEG_IDX(a_iSeg); CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Src); (void)fMcBegin; } while (0)
884
885	#define IEM_MC_PUSH_U16(a_u16Value) do { (void)fMcBegin; } while (0)
886	#define IEM_MC_PUSH_U32(a_u32Value) do { (void)fMcBegin; } while (0)
887	#define IEM_MC_PUSH_U32_SREG(a_u32Value) do { (void)fMcBegin; } while (0)
888	#define IEM_MC_PUSH_U64(a_u64Value) do { (void)fMcBegin; } while (0)
889	#define IEM_MC_POP_U16(a_pu16Value) do { (void)fMcBegin; } while (0)
890	#define IEM_MC_POP_U32(a_pu32Value) do { (void)fMcBegin; } while (0)
891	#define IEM_MC_POP_U64(a_pu64Value) do { (void)fMcBegin; } while (0)
892	#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) do { CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
893	#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) do { CHK_SEG_IDX(a_iSeg); (void)fMcBegin; AssertCompile((a_cbAlign) <= (a_cbMem)); } while (0)
894	#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do { (void)fMcBegin; } while (0)
895	#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do { (void)fMcBegin; } while (0)
896	#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); (void)fMcBegin; } while (0)
897	#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) do { (void)fMcBegin; } while (0)
898	#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \
899	do { CHK_CALL_ARG(a0, 0); (void)fMcBegin; } while (0)
900	#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \
901	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
902	#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \
903	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
904	#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \
905	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
906	#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
907	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
908	#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
909	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
910	#define IEM_MC_CALL_CIMPL_0(a_fFlags, a_pfnCImpl) do { (void)fMcBegin; } while (0)
911	#define IEM_MC_CALL_CIMPL_1(a_fFlags, a_pfnCImpl, a0) \
912	do { CHK_CALL_ARG(a0, 0); (void)fMcBegin; return VINF_SUCCESS; } while (0)
913	#define IEM_MC_CALL_CIMPL_2(a_fFlags, a_pfnCImpl, a0, a1) \
914	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; return VINF_SUCCESS; } while (0)
915	#define IEM_MC_CALL_CIMPL_3(a_fFlags, a_pfnCImpl, a0, a1, a2) \
916	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; return VINF_SUCCESS; } while (0)
917	#define IEM_MC_CALL_CIMPL_4(a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
918	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; return VINF_SUCCESS; } while (0)
919	#define IEM_MC_CALL_CIMPL_5(a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
920	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; return VINF_SUCCESS; } while (0)
921	#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) return VINF_SUCCESS
922	#define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_pfnCImpl, a0) return VINF_SUCCESS
923	#define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_pfnCImpl, a0, a1) return VINF_SUCCESS
924	#define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_pfnCImpl, a0, a1, a2) return VINF_SUCCESS
925
926	#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
927	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); (void)fMcBegin; } while (0)
928	#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
929	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
930	#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
931	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
932	#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
933	#define IEM_MC_PUSH_FPU_RESULT(a_FpuData, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
934	#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
935	#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
936	#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
937	#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
938	#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do {(void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
939	#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
940	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
941	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
942	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do{(void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
943	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
944	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW(a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
945	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
946	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW(a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
947	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
948	#define IEM_MC_UPDATE_FPU_OPCODE_IP(a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
949	#define IEM_MC_FPU_STACK_DEC_TOP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
950	#define IEM_MC_FPU_STACK_INC_TOP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
951	#define IEM_MC_FPU_STACK_FREE(a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
952	#define IEM_MC_UPDATE_FSW(a_u16FSW, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
953	#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
954	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
955	#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
956	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
957	#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW, a_uFpuOpcode) do { (void)fFpuWrite; (void)fMcBegin; (void)a_uFpuOpcode; } while (0)
958	#define IEM_MC_PREPARE_FPU_USAGE() (void)fMcBegin; \
959	const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1, fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1
960	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() (void)fMcBegin; const int fFpuRead = 1, fSseRead = 1
961	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() (void)fMcBegin; const int fFpuRead = 1, fFpuWrite = 1, fSseRead = 1, fSseWrite = 1
962	#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) do { (void)fSseWrite; (void)fMcBegin; } while (0)
963	#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) do { (void)fSseWrite; (void)fMcBegin; } while (0)
964	#define IEM_MC_PREPARE_SSE_USAGE() (void)fMcBegin; const int fSseRead = 1, fSseWrite = 1, fSseHost = 1
965	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() (void)fMcBegin; const int fSseRead = 1
966	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() (void)fMcBegin; const int fSseRead = 1, fSseWrite = 1
967	#define IEM_MC_PREPARE_AVX_USAGE() (void)fMcBegin; const int fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1
968	#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() (void)fMcBegin; const int fAvxRead = 1, fSseRead = 1
969	#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() (void)fMcBegin; const int fAvxRead = 1, fAvxWrite = 1, fSseRead = 1, fSseWrite = 1
970
971	#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
972	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
973	#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
974	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
975	#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
976	do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
977	#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
978	do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
979	#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() do { IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0); (void)fMcBegin; } while (0)
980	#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
981	do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
982	#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
983	do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
984	#define IEM_MC_CALL_AVX_AIMPL_4(a_pfnAImpl, a1, a2, a3, a4) \
985	do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; } while (0)
986
987	#define IEM_MC_IF_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
988	#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
989	#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) {
990	#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) {
991	#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
992	#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
993	#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
994	#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
995	#define IEM_MC_IF_CX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
996	#define IEM_MC_IF_ECX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
997	#define IEM_MC_IF_RCX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
998	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
999	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
1000	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
1001	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
1002	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
1003	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
1004	#define IEM_MC_IF_LOCAL_IS_Z(a_Local) (void)fMcBegin; if ((a_Local) == 0) {
1005	#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) (void)fMcBegin; CHK_GREG_IDX(a_iGReg); if (g_fRandom) {
1006	#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) (void)fMcBegin; if (g_fRandom != fFpuRead) {
1007	#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) (void)fMcBegin; if (g_fRandom != fFpuRead) {
1008	#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) (void)fMcBegin; \
1009	a_pr80Dst = NULL; \
1010	if (g_fRandom != fFpuRead) {
1011	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(p0, i0, p1, i1) (void)fMcBegin; \
1012	p0 = NULL; \
1013	p1 = NULL; \
1014	if (g_fRandom != fFpuRead) {
1015	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(p0, i0, i1) (void)fMcBegin; \
1016	p0 = NULL; \
1017	if (g_fRandom != fFpuRead) {
1018	#define IEM_MC_IF_FCW_IM() (void)fMcBegin; if (g_fRandom != fFpuRead) {
1019	#define IEM_MC_IF_MXCSR_XCPT_PENDING() (void)fMcBegin; if (g_fRandom != fSseRead) {
1020	#define IEM_MC_ELSE() } else {
1021	#define IEM_MC_ENDIF() } do { (void)fMcBegin; } while (0)
1022
1023	/** @} */
1024
1025	#include "../VMMAll/IEMAllInstructionsInterpretOnly.cpp"
1026
1027
1028
1029	/**
1030	* Formalities...
1031	*/
1032	int main()
1033	{
1034	RTTEST hTest;
1035	RTEXITCODE rcExit = RTTestInitAndCreate("tstIEMCheckMc", &hTest);
1036	if (rcExit == RTEXITCODE_SUCCESS)
1037	{
1038	RTTestBanner(hTest);
1039	RTTestPrintf(hTest, RTTESTLVL_ALWAYS, "(this is only a compile test.)");
1040	rcExit = RTTestSummaryAndDestroy(hTest);
1041	}
1042	return rcExit;
1043	}

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source: vbox/trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp@ 100696

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