tstIEMCheckMc.cpp@ 66745

Last change on this file since 66745 was 66581, checked in by vboxsync, 8 years ago
VMM: Nested Hw.virt: Implemented various SVM intercepts in IEM, addressed some todos.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 51.6 KB

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1	/* $Id: tstIEMCheckMc.cpp 66581 2017-04-17 03:00:00Z vboxsync $ */
2	/** @file
3	* IEM Testcase - Check the "Microcode".
4	*/
5
6	/*
7	* Copyright (C) 2011-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#include <iprt/assert.h>
23	#include <iprt/rand.h>
24	#include <iprt/test.h>
25
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#define IN_TSTVMSTRUCT 1
30	#include "../include/IEMInternal.h"
31	#include <VBox/vmm/vm.h>
32
33
34	/*********************************************************************************************************************************
35	* Global Variables *
36	*********************************************************************************************************************************/
37	bool volatile g_fRandom;
38	uint8_t volatile g_bRandom;
39	RTUINT128U g_u128Zero;
40
41
42	/** For hacks. */
43	#define TST_IEM_CHECK_MC
44
45	#define CHK_TYPE(a_ExpectedType, a_Param) \
46	do { a_ExpectedType const * pCheckType = &(a_Param); NOREF(pCheckType); } while (0)
47	#define CHK_PTYPE(a_ExpectedType, a_Param) \
48	do { a_ExpectedType pCheckType = (a_Param); NOREF(pCheckType); } while (0)
49
50	#define CHK_CONST(a_ExpectedType, a_Const) \
51	do { \
52	AssertCompile(((a_Const) >> 1) == ((a_Const) >> 1)); \
53	AssertCompile((a_ExpectedType)(a_Const) == (a_Const)); \
54	} while (0)
55
56	#define CHK_SINGLE_BIT(a_ExpectedType, a_fBitMask) \
57	do { \
58	CHK_CONST(a_ExpectedType, a_fBitMask); \
59	AssertCompile(RT_IS_POWER_OF_TWO(a_fBitMask)); \
60	} while (0)
61
62	#define CHK_GCPTR(a_EffAddr) \
63	CHK_TYPE(RTGCPTR, a_EffAddr)
64
65	#define CHK_SEG_IDX(a_iSeg) \
66	do { \
67	uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \
68	} while (0)
69
70	#define CHK_CALL_ARG(a_Name, a_iArg) \
71	do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0)
72
73
74	/** @name Other stubs.
75	* @{ */
76
77	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPU pVCpu);
78	#define FNIEMOP_DEF(a_Name) \
79	static VBOXSTRICTRC a_Name(PVMCPU pVCpu) RT_NO_THROW_DEF
80	#define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
81	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
82	#define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
83	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
84
85	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPU pVCpu, uint8_t bRm);
86	#define FNIEMOPRM_DEF(a_Name) \
87	static VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint8_t bRm) RT_NO_THROW_DEF
88
89	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: return VERR_IPE_NOT_REACHED_DEFAULT_CASE
90	#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
91	#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
92
93
94	#define IEM_OPCODE_GET_NEXT_U8(a_pu8) do { (a_pu8) = g_bRandom; CHK_PTYPE(uint8_t , a_pu8); } while (0)
95	#define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { (a_pi8) = g_bRandom; CHK_PTYPE(int8_t , a_pi8); } while (0)
96	#define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) do { (a_pu16) = g_bRandom; CHK_PTYPE(uint16_t , a_pu16); } while (0)
97	#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
98	#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
99	#define IEM_OPCODE_GET_NEXT_U16(a_pu16) do { (a_pu16) = g_bRandom; CHK_PTYPE(uint16_t , a_pu16); } while (0)
100	#define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
101	#define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
102	#define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { (a_pi16) = g_bRandom; CHK_PTYPE(int16_t , a_pi16); } while (0)
103	#define IEM_OPCODE_GET_NEXT_U32(a_pu32) do { (a_pu32) = g_bRandom; CHK_PTYPE(uint32_t , a_pu32); } while (0)
104	#define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
105	#define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { (a_pi32) = g_bRandom; CHK_PTYPE(int32_t , a_pi32); } while (0)
106	#define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
107	#define IEM_OPCODE_GET_NEXT_U64(a_pu64) do { (a_pu64) = g_bRandom; CHK_PTYPE(uint64_t , a_pu64); } while (0)
108	#define IEMOP_HLP_MIN_186() do { } while (0)
109	#define IEMOP_HLP_MIN_286() do { } while (0)
110	#define IEMOP_HLP_MIN_386() do { } while (0)
111	#define IEMOP_HLP_MIN_386_EX(a_fTrue) do { } while (0)
112	#define IEMOP_HLP_MIN_486() do { } while (0)
113	#define IEMOP_HLP_MIN_586() do { } while (0)
114	#define IEMOP_HLP_MIN_686() do { } while (0)
115	#define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0)
116	#define IEMOP_HLP_NO_64BIT() do { } while (0)
117	#define IEMOP_HLP_ONLY_64BIT() do { } while (0)
118	#define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0)
119	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0)
120	#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0)
121	#define IEMOP_HLP_DONE_VEX_DECODING_L_ZERO_NO_VVV() do { } while (0)
122	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0)
123	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() do { } while (0)
124	#define IEMOP_HLP_DONE_DECODING() do { } while (0)
125	#define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0)
126
127	#define IEMOP_HLP_SVM_CTRL_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
128	#define IEMOP_HLP_SVM_READ_CR_INTERCEPT(a_pVCpu, a_uCr, a_uExitInfo1, a_uExitInfo2) do { } while (0)
129
130	#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) do { } while (0)
131	#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) do { } while (0)
132	#define IEMOP_RAISE_DIVIDE_ERROR() VERR_TRPM_ACTIVE_TRAP
133	#define IEMOP_RAISE_INVALID_OPCODE() VERR_TRPM_ACTIVE_TRAP
134	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() VERR_TRPM_ACTIVE_TRAP
135	#define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) do { } while (0)
136	#define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
137	#define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
138	#define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
139	#define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
140	#define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) do { } while (0)
141	#define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
142	#define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
143	#define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
144	#define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
145	#define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
146	#define IEMOP_BITCH_ABOUT_STUB() do { } while (0)
147	#define FNIEMOP_STUB(a_Name) \
148	FNIEMOP_DEF(a_Name) { return VERR_NOT_IMPLEMENTED; } \
149	typedef int ignore_semicolon
150	#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
151	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return VERR_NOT_IMPLEMENTED; } \
152	typedef int ignore_semicolon
153
154	#define FNIEMOP_UD_STUB(a_Name) \
155	FNIEMOP_DEF(a_Name) { return IEMOP_RAISE_INVALID_OPCODE(); } \
156	typedef int ignore_semicolon
157	#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
158	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return IEMOP_RAISE_INVALID_OPCODE(); } \
159	typedef int ignore_semicolon
160
161
162	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
163	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
164	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
165
166	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (g_fRandom)
167	#define IEM_IS_LONG_MODE(a_pVCpu) (g_fRandom)
168	#define IEM_IS_REAL_MODE(a_pVCpu) (g_fRandom)
169	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) (g_fRandom)
170	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) (g_fRandom)
171	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)42)
172	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)88)
173
174	#define iemRecalEffOpSize(a_pVCpu) do { } while (0)
175
176	IEMOPBINSIZES g_iemAImpl_add;
177	IEMOPBINSIZES g_iemAImpl_adc;
178	IEMOPBINSIZES g_iemAImpl_sub;
179	IEMOPBINSIZES g_iemAImpl_sbb;
180	IEMOPBINSIZES g_iemAImpl_or;
181	IEMOPBINSIZES g_iemAImpl_xor;
182	IEMOPBINSIZES g_iemAImpl_and;
183	IEMOPBINSIZES g_iemAImpl_cmp;
184	IEMOPBINSIZES g_iemAImpl_test;
185	IEMOPBINSIZES g_iemAImpl_bt;
186	IEMOPBINSIZES g_iemAImpl_btc;
187	IEMOPBINSIZES g_iemAImpl_btr;
188	IEMOPBINSIZES g_iemAImpl_bts;
189	IEMOPBINSIZES g_iemAImpl_bsf;
190	IEMOPBINSIZES g_iemAImpl_bsr;
191	IEMOPBINSIZES g_iemAImpl_imul_two;
192	PCIEMOPBINSIZES g_apIemImplGrp1[8];
193	IEMOPUNARYSIZES g_iemAImpl_inc;
194	IEMOPUNARYSIZES g_iemAImpl_dec;
195	IEMOPUNARYSIZES g_iemAImpl_neg;
196	IEMOPUNARYSIZES g_iemAImpl_not;
197	IEMOPSHIFTSIZES g_iemAImpl_rol;
198	IEMOPSHIFTSIZES g_iemAImpl_ror;
199	IEMOPSHIFTSIZES g_iemAImpl_rcl;
200	IEMOPSHIFTSIZES g_iemAImpl_rcr;
201	IEMOPSHIFTSIZES g_iemAImpl_shl;
202	IEMOPSHIFTSIZES g_iemAImpl_shr;
203	IEMOPSHIFTSIZES g_iemAImpl_sar;
204	IEMOPMULDIVSIZES g_iemAImpl_mul;
205	IEMOPMULDIVSIZES g_iemAImpl_imul;
206	IEMOPMULDIVSIZES g_iemAImpl_div;
207	IEMOPMULDIVSIZES g_iemAImpl_idiv;
208	IEMOPSHIFTDBLSIZES g_iemAImpl_shld;
209	IEMOPSHIFTDBLSIZES g_iemAImpl_shrd;
210	IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw;
211	IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd;
212	IEMOPMEDIAF1L1 g_iemAImpl_punpckldq;
213	IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq;
214	IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw;
215	IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd;
216	IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq;
217	IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq;
218	IEMOPMEDIAF2 g_iemAImpl_pxor;
219	IEMOPMEDIAF2 g_iemAImpl_pcmpeqb;
220	IEMOPMEDIAF2 g_iemAImpl_pcmpeqw;
221	IEMOPMEDIAF2 g_iemAImpl_pcmpeqd;
222
223
224	#define iemAImpl_idiv_u8 ((PFNIEMAIMPLMULDIVU8)0)
225	#define iemAImpl_div_u8 ((PFNIEMAIMPLMULDIVU8)0)
226	#define iemAImpl_imul_u8 ((PFNIEMAIMPLMULDIVU8)0)
227	#define iemAImpl_mul_u8 ((PFNIEMAIMPLMULDIVU8)0)
228
229	#define iemAImpl_fpu_r32_to_r80 NULL
230	#define iemAImpl_fcom_r80_by_r32 NULL
231	#define iemAImpl_fadd_r80_by_r32 NULL
232	#define iemAImpl_fmul_r80_by_r32 NULL
233	#define iemAImpl_fsub_r80_by_r32 NULL
234	#define iemAImpl_fsubr_r80_by_r32 NULL
235	#define iemAImpl_fdiv_r80_by_r32 NULL
236	#define iemAImpl_fdivr_r80_by_r32 NULL
237
238	#define iemAImpl_fpu_r64_to_r80 NULL
239	#define iemAImpl_fadd_r80_by_r64 NULL
240	#define iemAImpl_fmul_r80_by_r64 NULL
241	#define iemAImpl_fcom_r80_by_r64 NULL
242	#define iemAImpl_fsub_r80_by_r64 NULL
243	#define iemAImpl_fsubr_r80_by_r64 NULL
244	#define iemAImpl_fdiv_r80_by_r64 NULL
245	#define iemAImpl_fdivr_r80_by_r64 NULL
246
247	#define iemAImpl_fadd_r80_by_r80 NULL
248	#define iemAImpl_fmul_r80_by_r80 NULL
249	#define iemAImpl_fsub_r80_by_r80 NULL
250	#define iemAImpl_fsubr_r80_by_r80 NULL
251	#define iemAImpl_fdiv_r80_by_r80 NULL
252	#define iemAImpl_fdivr_r80_by_r80 NULL
253	#define iemAImpl_fprem_r80_by_r80 NULL
254	#define iemAImpl_fprem1_r80_by_r80 NULL
255	#define iemAImpl_fscale_r80_by_r80 NULL
256
257	#define iemAImpl_fpatan_r80_by_r80 NULL
258	#define iemAImpl_fyl2x_r80_by_r80 NULL
259	#define iemAImpl_fyl2xp1_r80_by_r80 NULL
260
261	#define iemAImpl_fcom_r80_by_r80 NULL
262	#define iemAImpl_fucom_r80_by_r80 NULL
263	#define iemAImpl_fabs_r80 NULL
264	#define iemAImpl_fchs_r80 NULL
265	#define iemAImpl_ftst_r80 NULL
266	#define iemAImpl_fxam_r80 NULL
267	#define iemAImpl_f2xm1_r80 NULL
268	#define iemAImpl_fsqrt_r80 NULL
269	#define iemAImpl_frndint_r80 NULL
270	#define iemAImpl_fsin_r80 NULL
271	#define iemAImpl_fcos_r80 NULL
272
273	#define iemAImpl_fld1 NULL
274	#define iemAImpl_fldl2t NULL
275	#define iemAImpl_fldl2e NULL
276	#define iemAImpl_fldpi NULL
277	#define iemAImpl_fldlg2 NULL
278	#define iemAImpl_fldln2 NULL
279	#define iemAImpl_fldz NULL
280
281	#define iemAImpl_fptan_r80_r80 NULL
282	#define iemAImpl_fxtract_r80_r80 NULL
283	#define iemAImpl_fsincos_r80_r80 NULL
284
285	#define iemAImpl_fiadd_r80_by_i16 NULL
286	#define iemAImpl_fimul_r80_by_i16 NULL
287	#define iemAImpl_fisub_r80_by_i16 NULL
288	#define iemAImpl_fisubr_r80_by_i16 NULL
289	#define iemAImpl_fidiv_r80_by_i16 NULL
290	#define iemAImpl_fidivr_r80_by_i16 NULL
291
292	#define iemAImpl_fiadd_r80_by_i32 NULL
293	#define iemAImpl_fimul_r80_by_i32 NULL
294	#define iemAImpl_fisub_r80_by_i32 NULL
295	#define iemAImpl_fisubr_r80_by_i32 NULL
296	#define iemAImpl_fidiv_r80_by_i32 NULL
297	#define iemAImpl_fidivr_r80_by_i32 NULL
298
299	#define iemCImpl_callf NULL
300	#define iemCImpl_FarJmp NULL
301
302	#define iemAImpl_pshufhw NULL
303	#define iemAImpl_pshuflw NULL
304	#define iemAImpl_pshufd NULL
305
306	/** @} */
307
308
309	#define IEM_REPEAT_0(a_Callback, a_User) do { } while (0)
310	#define IEM_REPEAT_1(a_Callback, a_User) a_Callback##_CALLBACK(0, a_User)
311	#define IEM_REPEAT_2(a_Callback, a_User) IEM_REPEAT_1(a_Callback, a_User); a_Callback##_CALLBACK(1, a_User)
312	#define IEM_REPEAT_3(a_Callback, a_User) IEM_REPEAT_2(a_Callback, a_User); a_Callback##_CALLBACK(2, a_User)
313	#define IEM_REPEAT_4(a_Callback, a_User) IEM_REPEAT_3(a_Callback, a_User); a_Callback##_CALLBACK(3, a_User)
314	#define IEM_REPEAT_5(a_Callback, a_User) IEM_REPEAT_4(a_Callback, a_User); a_Callback##_CALLBACK(4, a_User)
315	#define IEM_REPEAT_6(a_Callback, a_User) IEM_REPEAT_5(a_Callback, a_User); a_Callback##_CALLBACK(5, a_User)
316	#define IEM_REPEAT_7(a_Callback, a_User) IEM_REPEAT_6(a_Callback, a_User); a_Callback##_CALLBACK(6, a_User)
317	#define IEM_REPEAT_8(a_Callback, a_User) IEM_REPEAT_7(a_Callback, a_User); a_Callback##_CALLBACK(7, a_User)
318	#define IEM_REPEAT_9(a_Callback, a_User) IEM_REPEAT_8(a_Callback, a_User); a_Callback##_CALLBACK(8, a_User)
319	#define IEM_REPEAT(a_cTimes, a_Callback, a_User) RT_CONCAT(IEM_REPEAT_,a_cTimes)(a_Callback, a_User)
320
321
322
323	/** @name Microcode test stubs
324	* @{ */
325
326	#define IEM_ARG_CHECK_CALLBACK(a_idx, a_User) int RT_CONCAT(iArgCheck_,a_idx); NOREF(RT_CONCAT(iArgCheck_,a_idx))
327	#define IEM_MC_BEGIN(a_cArgs, a_cLocals) \
328	{ \
329	const uint8_t cArgs = (a_cArgs); NOREF(cArgs); \
330	const uint8_t cLocals = (a_cArgs); NOREF(cLocals); \
331	IEM_REPEAT(a_cArgs, IEM_ARG_CHECK, 0); \
332
333	#define IEM_MC_END() \
334	}
335
336	#define IEM_MC_PAUSE() do {} while (0)
337	#define IEM_MC_CONTINUE() do {} while (0)
338	#define IEM_MC_ADVANCE_RIP() do {} while (0)
339	#define IEM_MC_REL_JMP_S8(a_i8) CHK_TYPE(int8_t, a_i8)
340	#define IEM_MC_REL_JMP_S16(a_i16) CHK_TYPE(int16_t, a_i16)
341	#define IEM_MC_REL_JMP_S32(a_i32) CHK_TYPE(int32_t, a_i32)
342	#define IEM_MC_SET_RIP_U16(a_u16NewIP) CHK_TYPE(uint16_t, a_u16NewIP)
343	#define IEM_MC_SET_RIP_U32(a_u32NewIP) CHK_TYPE(uint32_t, a_u32NewIP)
344	#define IEM_MC_SET_RIP_U64(a_u64NewIP) CHK_TYPE(uint64_t, a_u64NewIP)
345	#define IEM_MC_RAISE_DIVIDE_ERROR() return VERR_TRPM_ACTIVE_TRAP
346	#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do {} while (0)
347	#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() do {} while (0)
348	#define IEM_MC_MAYBE_RAISE_FPU_XCPT() do {} while (0)
349	#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do {} while (0)
350	#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() do {} while (0)
351	#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() do {} while (0)
352	#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() do {} while (0)
353	#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() do {} while (0)
354	#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do {} while (0)
355	#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
356	do { AssertCompile(RT_IS_POWER_OF_TWO(a_cbAlign)); CHK_TYPE(RTGCPTR, a_EffAddr); } while (0)
357
358	#define IEM_MC_LOCAL(a_Type, a_Name) \
359	a_Type a_Name; NOREF(a_Name)
360	#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) \
361	a_Type const a_Name = (a_Value); \
362	NOREF(a_Name)
363	#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) \
364	(a_pRefArg) = &(a_Local)
365
366	#define IEM_MC_ARG(a_Type, a_Name, a_iArg) \
367	RT_CONCAT(iArgCheck_,a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
368	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
369	AssertCompile((a_iArg) < cArgs); \
370	a_Type a_Name; \
371	NOREF(a_Name)
372	#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) \
373	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
374	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
375	AssertCompile((a_iArg) < cArgs); \
376	a_Type const a_Name = (a_Value); \
377	NOREF(a_Name)
378	#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) \
379	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
380	int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
381	AssertCompile((a_iArg) < cArgs); \
382	a_Type const a_Name = &(a_Local); \
383	NOREF(a_Name)
384	#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
385	RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
386	int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \
387	AssertCompile((a_iArg) < cArgs); \
388	uint32_t a_Name; \
389	uint32_t *a_pName = &a_Name; \
390	NOREF(a_pName)
391
392	#define IEM_MC_COMMIT_EFLAGS(a_EFlags) CHK_TYPE(uint32_t, a_EFlags)
393	#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (0)
394	#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
395
396	#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) do { (a_u8Dst) = 0; CHK_TYPE(uint8_t, a_u8Dst); } while (0)
397	#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
398	#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
399	#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
400	#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
401	#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
402	#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
403	#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
404	#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
405	#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
406	#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
407	#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
408	#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
409	#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
410	#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
411	#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
412	#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
413	#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
414	#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
415	#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
416	#define IEM_MC_FETCH_CR0_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
417	#define IEM_MC_FETCH_CR0_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
418	#define IEM_MC_FETCH_CR0_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
419	#define IEM_MC_FETCH_LDTR_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
420	#define IEM_MC_FETCH_LDTR_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
421	#define IEM_MC_FETCH_LDTR_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
422	#define IEM_MC_FETCH_TR_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
423	#define IEM_MC_FETCH_TR_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
424	#define IEM_MC_FETCH_TR_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
425	#define IEM_MC_FETCH_EFLAGS(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint32_t, a_EFlags); } while (0)
426	#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint8_t, a_EFlags); } while (0)
427	#define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); (void)fFpuRead; } while (0)
428	#define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); (void)fFpuRead; } while (0)
429	#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) do { CHK_TYPE(uint8_t, a_u8Value); } while (0)
430	#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) do { CHK_TYPE(uint16_t, a_u16Value); } while (0)
431	#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) do { } while (0)
432	#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) do { } while (0)
433	#define IEM_MC_STORE_GREG_U8_CONST(a_iGReg, a_u8C) do { AssertCompile((uint8_t )(a_u8C) == (a_u8C) ); } while (0)
434	#define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16C) do { AssertCompile((uint16_t)(a_u16C) == (a_u16C)); } while (0)
435	#define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32C) do { AssertCompile((uint32_t)(a_u32C) == (a_u32C)); } while (0)
436	#define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u64C) do { AssertCompile((uint64_t)(a_u64C) == (a_u64C)); } while (0)
437	#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) do { CHK_PTYPE(PCRTFLOAT80U, a_pr80Src); Assert((a_iSt) < 8); } while (0)
438	#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) do { } while (0)
439	#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { CHK_PTYPE(uint32_t *, a_pu32Dst); } while (0)
440	#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) do { (a_pu8Dst) = (uint8_t )((uintptr_t)0); CHK_PTYPE(uint8_t , a_pu8Dst); } while (0)
441	#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) do { (a_pu16Dst) = (uint16_t )((uintptr_t)0); CHK_PTYPE(uint16_t , a_pu16Dst); } while (0)
442	#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) do { (a_pu32Dst) = (uint32_t )((uintptr_t)0); CHK_PTYPE(uint32_t , a_pu32Dst); } while (0)
443	#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { (a_pu64Dst) = (uint64_t )((uintptr_t)0); CHK_PTYPE(uint64_t , a_pu64Dst); } while (0)
444	#define IEM_MC_REF_EFLAGS(a_pEFlags) do { (a_pEFlags) = (uint32_t )((uintptr_t)0); CHK_PTYPE(uint32_t , a_pEFlags); } while (0)
445
446	#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
447	#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
448	#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
449	#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
450	#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
451	#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
452	#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
453	#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
454	#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { CHK_CONST(uint16_t, a_u16Const); } while (0)
455
456	#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
457	#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
458	#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
459	#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
460	#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
461	#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
462	#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
463	#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
464
465	#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u8Value) += 1; CHK_TYPE(uint8_t, a_u8Value); } while (0)
466	#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += 1; CHK_TYPE(uint16_t, a_u16Value); } while (0)
467	#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += 1; CHK_TYPE(uint32_t, a_u32Value); } while (0)
468	#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += 1; CHK_TYPE(uint64_t, a_u64Value); } while (0)
469	#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); CHK_GCPTR(a_EffAddr); } while (0)
470	#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); CHK_GCPTR(a_EffAddr); } while (0)
471	#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); CHK_GCPTR(a_EffAddr); } while (0)
472	#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); } while (0)
473	#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); } while (0)
474	#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); } while (0)
475	#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Local); CHK_CONST(uint64_t, a_u64Mask); } while (0)
476	#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Arg); CHK_CONST(uint16_t, a_u16Mask); } while (0)
477	#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Arg); CHK_CONST(uint32_t, a_u32Mask); } while (0)
478	#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Arg); CHK_CONST(uint64_t, a_u64Mask); } while (0)
479	#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) \|= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); } while (0)
480	#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) \|= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); } while (0)
481	#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); } while (0)
482	#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); } while (0)
483	#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); } while (0)
484	#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); } while (0)
485	#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); } while (0)
486	#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); } while (0)
487	#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); } while (0)
488	#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); } while (0)
489	#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) \|= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); } while (0)
490	#define IEM_MC_SET_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
491	#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
492	#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
493	#define IEM_MC_CLEAR_FSW_EX() do { } while (0)
494
495
496	#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fFpuRead; } while (0)
497	#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fFpuRead; } while (0)
498	#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fFpuWrite; } while (0)
499	#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fFpuWrite; } while (0)
500	#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t )((uintptr_t)0); CHK_PTYPE(uint64_t , a_pu64Dst); (void)fFpuWrite; } while (0)
501	#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const )((uintptr_t)0); CHK_PTYPE(uint64_t const , a_pu64Dst); (void)fFpuWrite; } while (0)
502	#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const )((uintptr_t)0); CHK_PTYPE(uint32_t const , a_pu32Dst); (void)fFpuWrite; } while (0)
503
504	#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseRead; } while (0)
505	#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; } while (0)
506	#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fSseRead; } while (0)
507	#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; } while (0)
508	#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseWrite; } while (0)
509	#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; } while (0)
510	#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; } while (0)
511	#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; } while (0)
512	#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; } while (0)
513	#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fSseWrite; } while (0)
514	#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fSseWrite; } while (0)
515	#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const )((uintptr_t)0); CHK_PTYPE(uint64_t const , a_pu64Dst); (void)fSseWrite; } while (0)
516	#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) do { (void)fSseWrite; } while (0)
517
518	#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
519	#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); } while (0)
520	#define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); } while (0)
521	#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
522	#define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int16_t, a_i16Dst); } while (0)
523	#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
524	#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); } while (0)
525	#define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
526	#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
527	#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
528	#define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int64_t, a_i64Dst); } while (0)
529
530	#define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
531	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); } while (0)
532	#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
533	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint16_t, a_u16Dst); } while (0)
534	#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
535	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint32_t, a_u32Dst); } while (0)
536	#define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
537	do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); } while (0)
538
539	#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
540	#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
541	#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
542	#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
543	#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
544	#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
545	#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
546	#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
547	#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
548	#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
549	#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
550	#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
551	#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0)
552	#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0)
553	#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0)
554	#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst);} while (0)
555	#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst);} while (0)
556
557	#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0)
558	#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0)
559	#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0)
560	#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0)
561	#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); } while (0)
562	#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint16_t, a_u16C); } while (0)
563	#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint32_t, a_u32C); } while (0)
564	#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint64_t, a_u64C); } while (0)
565	#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) do { CHK_TYPE(int8_t *, a_pi8Dst); CHK_CONST(int8_t, a_i8C); } while (0)
566	#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) do { CHK_TYPE(int16_t *, a_pi16Dst); CHK_CONST(int16_t, a_i16C); } while (0)
567	#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) do { CHK_TYPE(int32_t *, a_pi32Dst); CHK_CONST(int32_t, a_i32C); } while (0)
568	#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) do { CHK_TYPE(int64_t *, a_pi64Dst); CHK_CONST(int64_t, a_i64C); } while (0)
569	#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); } while (0)
570	#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); } while (0)
571	#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); } while (0)
572	#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0)
573	#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0)
574
575	#define IEM_MC_PUSH_U16(a_u16Value) do {} while (0)
576	#define IEM_MC_PUSH_U32(a_u32Value) do {} while (0)
577	#define IEM_MC_PUSH_U32_SREG(a_u32Value) do {} while (0)
578	#define IEM_MC_PUSH_U64(a_u64Value) do {} while (0)
579	#define IEM_MC_POP_U16(a_pu16Value) do {} while (0)
580	#define IEM_MC_POP_U32(a_pu32Value) do {} while (0)
581	#define IEM_MC_POP_U64(a_pu64Value) do {} while (0)
582	#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0)
583	#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0)
584	#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0)
585	#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do {} while (0)
586	#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0)
587	#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) do {} while (0)
588	#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \
589	do { CHK_CALL_ARG(a0, 0); } while (0)
590	#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \
591	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)
592	#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \
593	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0)
594	#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \
595	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0)
596	#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
597	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (a_rc) = VINF_SUCCESS; } while (0)
598	#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
599	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (a_rc) = VINF_SUCCESS; } while (0)
600	#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) do { } while (0)
601	#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) \
602	do { CHK_CALL_ARG(a0, 0); } while (0)
603	#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) \
604	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)
605	#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) \
606	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0)
607	#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) \
608	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0)
609	#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) \
610	do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); } while (0)
611	#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (VINF_SUCCESS)
612	#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (VINF_SUCCESS)
613	#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (VINF_SUCCESS)
614	#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (VINF_SUCCESS)
615
616	#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
617	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); } while (0)
618	#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
619	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)
620	#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
621	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0)
622	#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { (void)fFpuWrite; } while (0)
623	#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { (void)fFpuWrite; } while (0)
624	#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
625	#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) do { (void)fFpuWrite; } while (0)
626	#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) do { (void)fFpuWrite; } while (0)
627	#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) do { (void)fFpuWrite; } while (0)
628	#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
629	#define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
630	#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg) do { (void)fFpuWrite; } while (0)
631	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
632	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg) do { (void)fFpuWrite; } while (0)
633	#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
634	#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() do { (void)fFpuWrite; } while (0)
635	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() do { (void)fFpuWrite; } while (0)
636	#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() do { (void)fFpuWrite; } while (0)
637	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() do { (void)fFpuWrite; } while (0)
638	#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
639	#define IEM_MC_UPDATE_FPU_OPCODE_IP() do { (void)fFpuWrite; } while (0)
640	#define IEM_MC_FPU_STACK_DEC_TOP() do { (void)fFpuWrite; } while (0)
641	#define IEM_MC_FPU_STACK_INC_TOP() do { (void)fFpuWrite; } while (0)
642	#define IEM_MC_FPU_STACK_FREE(a_iStReg) do { (void)fFpuWrite; } while (0)
643	#define IEM_MC_UPDATE_FSW(a_u16FSW) do { (void)fFpuWrite; } while (0)
644	#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) do { (void)fFpuWrite; } while (0)
645	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
646	#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) do { (void)fFpuWrite; } while (0)
647	#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; } while (0)
648	#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { (void)fFpuWrite; } while (0)
649	#define IEM_MC_PREPARE_FPU_USAGE() \
650	const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1
651	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() const int fFpuRead = 1, fSseRead = 1
652	#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() const int fFpuRead = 1, fFpuWrite = 1, fSseRead = 1, fSseWrite = 1
653	#define IEM_MC_PREPARE_SSE_USAGE() const int fSseRead = 1, fSseWrite = 1, fSseHost = 1
654	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() const int fSseRead = 1
655	#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() const int fSseRead = 1, fSseWrite = 1
656
657	#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
658	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)
659	#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
660	do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0)
661	#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
662	do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0)
663	#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
664	do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0)
665
666	#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (g_fRandom) {
667	#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
668	#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (g_fRandom) {
669	#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (g_fRandom) {
670	#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) if (g_fRandom) {
671	#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) if (g_fRandom) {
672	#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) if (g_fRandom) {
673	#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) if (g_fRandom) {
674	#define IEM_MC_IF_CX_IS_NZ() if (g_fRandom) {
675	#define IEM_MC_IF_ECX_IS_NZ() if (g_fRandom) {
676	#define IEM_MC_IF_RCX_IS_NZ() if (g_fRandom) {
677	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
678	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
679	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
680	#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
681	#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
682	#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
683	#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
684	#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (g_fRandom) {
685	#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) if (g_fRandom != fFpuRead) {
686	#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) if (g_fRandom != fFpuRead) {
687	#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
688	a_pr80Dst = NULL; \
689	if (g_fRandom != fFpuRead) {
690	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(p0, i0, p1, i1) \
691	p0 = NULL; \
692	p1 = NULL; \
693	if (g_fRandom != fFpuRead) {
694	#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(p0, i0, i1) \
695	p0 = NULL; \
696	if (g_fRandom != fFpuRead) {
697	#define IEM_MC_IF_FCW_IM() if (g_fRandom != fFpuRead) {
698	#define IEM_MC_ELSE() } else {
699	#define IEM_MC_ENDIF() } do {} while (0)
700
701	/** @} */
702
703	#include "../VMMAll/IEMAllInstructions.cpp.h"
704
705
706
707	/**
708	* Formalities...
709	*/
710	int main()
711	{
712	RTTEST hTest;
713	RTEXITCODE rcExit = RTTestInitAndCreate("tstIEMCheckMc", &hTest);
714	if (rcExit == RTEXITCODE_SUCCESS)
715	{
716	RTTestBanner(hTest);
717	RTTestPrintf(hTest, RTTESTLVL_ALWAYS, "(this is only a compile test.)");
718	rcExit = RTTestSummaryAndDestroy(hTest);
719	}
720	return rcExit;
721	}

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source: vbox/trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp@ 66745

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