| 1 | /* $Id: tstIEMCheckMc.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM Testcase - Check the "Microcode".
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2011-2019 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 |
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| 19 | /*********************************************************************************************************************************
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| 20 | * Header Files *
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| 21 | *********************************************************************************************************************************/
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| 22 | #define VMCPU_INCL_CPUM_GST_CTX
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| 23 | #include <iprt/assert.h>
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| 24 | #include <iprt/rand.h>
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| 25 | #include <iprt/test.h>
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| 26 |
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| 27 | #include <VBox/types.h>
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| 28 | #include <VBox/err.h>
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| 29 | #include <VBox/log.h>
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| 30 | #define IN_TSTVMSTRUCT 1
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| 31 | #include "../include/IEMInternal.h"
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| 32 | #include <VBox/vmm/vm.h>
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| 33 |
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| 34 |
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| 35 | /*********************************************************************************************************************************
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| 36 | * Global Variables *
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| 37 | *********************************************************************************************************************************/
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| 38 | bool volatile g_fRandom;
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| 39 | uint8_t volatile g_bRandom;
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| 40 | RTUINT128U g_u128Zero;
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| 41 |
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| 42 |
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| 43 | /** For hacks. */
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| 44 | #define TST_IEM_CHECK_MC
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| 45 |
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| 46 | #define CHK_TYPE(a_ExpectedType, a_Param) \
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| 47 | do { a_ExpectedType const * pCheckType = &(a_Param); NOREF(pCheckType); } while (0)
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| 48 | #define CHK_PTYPE(a_ExpectedType, a_Param) \
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| 49 | do { a_ExpectedType pCheckType = (a_Param); NOREF(pCheckType); } while (0)
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| 50 |
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| 51 | #define CHK_CONST(a_ExpectedType, a_Const) \
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| 52 | do { \
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| 53 | AssertCompile(((a_Const) >> 1) == ((a_Const) >> 1)); \
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| 54 | AssertCompile((a_ExpectedType)(a_Const) == (a_Const)); \
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| 55 | } while (0)
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| 56 |
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| 57 | #define CHK_SINGLE_BIT(a_ExpectedType, a_fBitMask) \
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| 58 | do { \
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| 59 | CHK_CONST(a_ExpectedType, a_fBitMask); \
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| 60 | AssertCompile(RT_IS_POWER_OF_TWO(a_fBitMask)); \
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| 61 | } while (0)
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| 62 |
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| 63 | #define CHK_GCPTR(a_EffAddr) \
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| 64 | CHK_TYPE(RTGCPTR, a_EffAddr)
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| 65 |
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| 66 | #define CHK_SEG_IDX(a_iSeg) \
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| 67 | do { \
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| 68 | uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \
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| 69 | } while (0)
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| 70 |
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| 71 | #define CHK_CALL_ARG(a_Name, a_iArg) \
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| 72 | do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0)
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| 73 |
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| 74 |
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| 75 | /** @name Other stubs.
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| 76 | * @{ */
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| 77 |
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| 78 | typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPU pVCpu);
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| 79 | #define FNIEMOP_DEF(a_Name) \
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| 80 | static VBOXSTRICTRC a_Name(PVMCPU pVCpu) RT_NO_THROW_DEF
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| 81 | #define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
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| 82 | static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
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| 83 | #define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
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| 84 | static VBOXSTRICTRC a_Name(PVMCPU pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
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| 85 |
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| 86 | typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPU pVCpu, uint8_t bRm);
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| 87 | #define FNIEMOPRM_DEF(a_Name) \
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| 88 | static VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint8_t bRm) RT_NO_THROW_DEF
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| 89 |
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| 90 | #define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: return VERR_IPE_NOT_REACHED_DEFAULT_CASE
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| 91 | #define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
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| 92 | #define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
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| 93 |
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| 94 |
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| 95 | #define IEM_OPCODE_GET_NEXT_RM(a_pu8) do { *(a_pu8) = g_bRandom; CHK_PTYPE(uint8_t *, a_pu8); } while (0)
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| 96 | #define IEM_OPCODE_GET_NEXT_U8(a_pu8) do { *(a_pu8) = g_bRandom; CHK_PTYPE(uint8_t *, a_pu8); } while (0)
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| 97 | #define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { *(a_pi8) = g_bRandom; CHK_PTYPE(int8_t *, a_pi8); } while (0)
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| 98 | #define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0)
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| 99 | #define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
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| 100 | #define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
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| 101 | #define IEM_OPCODE_GET_NEXT_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0)
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| 102 | #define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
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| 103 | #define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
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| 104 | #define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { *(a_pi16) = g_bRandom; CHK_PTYPE(int16_t *, a_pi16); } while (0)
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| 105 | #define IEM_OPCODE_GET_NEXT_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
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| 106 | #define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
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| 107 | #define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { *(a_pi32) = g_bRandom; CHK_PTYPE(int32_t *, a_pi32); } while (0)
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| 108 | #define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
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| 109 | #define IEM_OPCODE_GET_NEXT_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
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| 110 | #define IEMOP_HLP_MIN_186() do { } while (0)
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| 111 | #define IEMOP_HLP_MIN_286() do { } while (0)
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| 112 | #define IEMOP_HLP_MIN_386() do { } while (0)
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| 113 | #define IEMOP_HLP_MIN_386_EX(a_fTrue) do { } while (0)
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| 114 | #define IEMOP_HLP_MIN_486() do { } while (0)
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| 115 | #define IEMOP_HLP_MIN_586() do { } while (0)
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| 116 | #define IEMOP_HLP_MIN_686() do { } while (0)
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| 117 | #define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0)
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| 118 | #define IEMOP_HLP_NO_64BIT() do { } while (0)
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| 119 | #define IEMOP_HLP_ONLY_64BIT() do { } while (0)
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| 120 | #define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0)
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| 121 | #define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0)
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| 122 | #define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0)
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| 123 | #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0)
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| 124 | #define IEMOP_HLP_DONE_VEX_DECODING() do { } while (0)
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| 125 | #define IEMOP_HLP_DONE_VEX_DECODING_L0() do { } while (0)
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| 126 | #define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV() do { } while (0)
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| 127 | #define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV() do { } while (0)
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| 128 | #define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() do { } while (0)
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| 129 | #define IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES() do { } while (0)
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| 130 | #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
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| 131 | # define IEMOP_HLP_VMX_INSTR(a_szInstr, a_InsDiagPrefix) do { } while (0)
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| 132 | # define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) do { } while (0)
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| 133 | #endif
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| 134 |
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| 135 |
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| 136 | #define IEMOP_HLP_DONE_DECODING() do { } while (0)
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| 137 |
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| 138 | #define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) do { } while (0)
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| 139 | #define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) do { } while (0)
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| 140 | #define IEMOP_RAISE_DIVIDE_ERROR() VERR_TRPM_ACTIVE_TRAP
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| 141 | #define IEMOP_RAISE_INVALID_OPCODE() VERR_TRPM_ACTIVE_TRAP
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| 142 | #define IEMOP_RAISE_INVALID_LOCK_PREFIX() VERR_TRPM_ACTIVE_TRAP
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| 143 | #define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) do { } while (0)
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| 144 | #define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
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| 145 | #define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
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| 146 | #define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
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| 147 | #define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
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| 148 | #define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) do { } while (0)
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| 149 | #define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) do { } while (0)
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| 150 | #define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) do { } while (0)
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| 151 | #define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) do { } while (0)
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| 152 | #define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
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| 153 | #define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) do { } while (0)
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| 154 | #define IEMOP_BITCH_ABOUT_STUB() do { } while (0)
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| 155 | #define FNIEMOP_STUB(a_Name) \
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| 156 | FNIEMOP_DEF(a_Name) { return VERR_NOT_IMPLEMENTED; } \
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| 157 | typedef int ignore_semicolon
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| 158 | #define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
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| 159 | FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return VERR_NOT_IMPLEMENTED; } \
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| 160 | typedef int ignore_semicolon
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| 161 |
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| 162 | #define FNIEMOP_UD_STUB(a_Name) \
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| 163 | FNIEMOP_DEF(a_Name) { return IEMOP_RAISE_INVALID_OPCODE(); } \
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| 164 | typedef int ignore_semicolon
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| 165 | #define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
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| 166 | FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return IEMOP_RAISE_INVALID_OPCODE(); } \
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| 167 | typedef int ignore_semicolon
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| 168 |
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| 169 |
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| 170 | #define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
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| 171 | #define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
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| 172 | #define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
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| 173 |
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| 174 | #define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (g_fRandom)
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| 175 | #define IEM_IS_LONG_MODE(a_pVCpu) (g_fRandom)
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| 176 | #define IEM_IS_REAL_MODE(a_pVCpu) (g_fRandom)
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| 177 | #define IEM_IS_GUEST_CPU_AMD(a_pVCpu) (g_fRandom)
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| 178 | #define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) (g_fRandom)
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| 179 | #define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)42)
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| 180 | #define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) ((PCCPUMFEATURES)(uintptr_t)88)
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| 181 |
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| 182 | #define iemRecalEffOpSize(a_pVCpu) do { } while (0)
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| 183 |
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| 184 | IEMOPBINSIZES g_iemAImpl_add;
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| 185 | IEMOPBINSIZES g_iemAImpl_adc;
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| 186 | IEMOPBINSIZES g_iemAImpl_sub;
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| 187 | IEMOPBINSIZES g_iemAImpl_sbb;
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| 188 | IEMOPBINSIZES g_iemAImpl_or;
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| 189 | IEMOPBINSIZES g_iemAImpl_xor;
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| 190 | IEMOPBINSIZES g_iemAImpl_and;
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| 191 | IEMOPBINSIZES g_iemAImpl_cmp;
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| 192 | IEMOPBINSIZES g_iemAImpl_test;
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| 193 | IEMOPBINSIZES g_iemAImpl_bt;
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| 194 | IEMOPBINSIZES g_iemAImpl_btc;
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| 195 | IEMOPBINSIZES g_iemAImpl_btr;
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| 196 | IEMOPBINSIZES g_iemAImpl_bts;
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| 197 | IEMOPBINSIZES g_iemAImpl_bsf;
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| 198 | IEMOPBINSIZES g_iemAImpl_bsr;
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| 199 | IEMOPBINSIZES g_iemAImpl_imul_two;
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| 200 | PCIEMOPBINSIZES g_apIemImplGrp1[8];
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| 201 | IEMOPUNARYSIZES g_iemAImpl_inc;
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| 202 | IEMOPUNARYSIZES g_iemAImpl_dec;
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| 203 | IEMOPUNARYSIZES g_iemAImpl_neg;
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| 204 | IEMOPUNARYSIZES g_iemAImpl_not;
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| 205 | IEMOPSHIFTSIZES g_iemAImpl_rol;
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| 206 | IEMOPSHIFTSIZES g_iemAImpl_ror;
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| 207 | IEMOPSHIFTSIZES g_iemAImpl_rcl;
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| 208 | IEMOPSHIFTSIZES g_iemAImpl_rcr;
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| 209 | IEMOPSHIFTSIZES g_iemAImpl_shl;
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| 210 | IEMOPSHIFTSIZES g_iemAImpl_shr;
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| 211 | IEMOPSHIFTSIZES g_iemAImpl_sar;
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| 212 | IEMOPMULDIVSIZES g_iemAImpl_mul;
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| 213 | IEMOPMULDIVSIZES g_iemAImpl_imul;
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| 214 | IEMOPMULDIVSIZES g_iemAImpl_div;
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| 215 | IEMOPMULDIVSIZES g_iemAImpl_idiv;
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| 216 | IEMOPSHIFTDBLSIZES g_iemAImpl_shld;
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| 217 | IEMOPSHIFTDBLSIZES g_iemAImpl_shrd;
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| 218 | IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw;
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| 219 | IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd;
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| 220 | IEMOPMEDIAF1L1 g_iemAImpl_punpckldq;
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| 221 | IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq;
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| 222 | IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw;
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| 223 | IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd;
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| 224 | IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq;
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| 225 | IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq;
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| 226 | IEMOPMEDIAF2 g_iemAImpl_pxor;
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| 227 | IEMOPMEDIAF2 g_iemAImpl_pcmpeqb;
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| 228 | IEMOPMEDIAF2 g_iemAImpl_pcmpeqw;
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| 229 | IEMOPMEDIAF2 g_iemAImpl_pcmpeqd;
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| 230 |
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| 231 |
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| 232 | #define iemAImpl_idiv_u8 ((PFNIEMAIMPLMULDIVU8)0)
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| 233 | #define iemAImpl_div_u8 ((PFNIEMAIMPLMULDIVU8)0)
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| 234 | #define iemAImpl_imul_u8 ((PFNIEMAIMPLMULDIVU8)0)
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| 235 | #define iemAImpl_mul_u8 ((PFNIEMAIMPLMULDIVU8)0)
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| 236 |
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| 237 | #define iemAImpl_fpu_r32_to_r80 NULL
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| 238 | #define iemAImpl_fcom_r80_by_r32 NULL
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| 239 | #define iemAImpl_fadd_r80_by_r32 NULL
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| 240 | #define iemAImpl_fmul_r80_by_r32 NULL
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| 241 | #define iemAImpl_fsub_r80_by_r32 NULL
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| 242 | #define iemAImpl_fsubr_r80_by_r32 NULL
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| 243 | #define iemAImpl_fdiv_r80_by_r32 NULL
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| 244 | #define iemAImpl_fdivr_r80_by_r32 NULL
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| 245 |
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| 246 | #define iemAImpl_fpu_r64_to_r80 NULL
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| 247 | #define iemAImpl_fadd_r80_by_r64 NULL
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| 248 | #define iemAImpl_fmul_r80_by_r64 NULL
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| 249 | #define iemAImpl_fcom_r80_by_r64 NULL
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| 250 | #define iemAImpl_fsub_r80_by_r64 NULL
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| 251 | #define iemAImpl_fsubr_r80_by_r64 NULL
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| 252 | #define iemAImpl_fdiv_r80_by_r64 NULL
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| 253 | #define iemAImpl_fdivr_r80_by_r64 NULL
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| 254 |
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| 255 | #define iemAImpl_fadd_r80_by_r80 NULL
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| 256 | #define iemAImpl_fmul_r80_by_r80 NULL
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| 257 | #define iemAImpl_fsub_r80_by_r80 NULL
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| 258 | #define iemAImpl_fsubr_r80_by_r80 NULL
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| 259 | #define iemAImpl_fdiv_r80_by_r80 NULL
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| 260 | #define iemAImpl_fdivr_r80_by_r80 NULL
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| 261 | #define iemAImpl_fprem_r80_by_r80 NULL
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| 262 | #define iemAImpl_fprem1_r80_by_r80 NULL
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| 263 | #define iemAImpl_fscale_r80_by_r80 NULL
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| 264 |
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| 265 | #define iemAImpl_fpatan_r80_by_r80 NULL
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| 266 | #define iemAImpl_fyl2x_r80_by_r80 NULL
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| 267 | #define iemAImpl_fyl2xp1_r80_by_r80 NULL
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| 268 |
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| 269 | #define iemAImpl_fcom_r80_by_r80 NULL
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| 270 | #define iemAImpl_fucom_r80_by_r80 NULL
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| 271 | #define iemAImpl_fabs_r80 NULL
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| 272 | #define iemAImpl_fchs_r80 NULL
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| 273 | #define iemAImpl_ftst_r80 NULL
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| 274 | #define iemAImpl_fxam_r80 NULL
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| 275 | #define iemAImpl_f2xm1_r80 NULL
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| 276 | #define iemAImpl_fsqrt_r80 NULL
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| 277 | #define iemAImpl_frndint_r80 NULL
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| 278 | #define iemAImpl_fsin_r80 NULL
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| 279 | #define iemAImpl_fcos_r80 NULL
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| 280 |
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| 281 | #define iemAImpl_fld1 NULL
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| 282 | #define iemAImpl_fldl2t NULL
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| 283 | #define iemAImpl_fldl2e NULL
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| 284 | #define iemAImpl_fldpi NULL
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| 285 | #define iemAImpl_fldlg2 NULL
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| 286 | #define iemAImpl_fldln2 NULL
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| 287 | #define iemAImpl_fldz NULL
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| 288 |
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| 289 | #define iemAImpl_fptan_r80_r80 NULL
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| 290 | #define iemAImpl_fxtract_r80_r80 NULL
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| 291 | #define iemAImpl_fsincos_r80_r80 NULL
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| 292 |
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| 293 | #define iemAImpl_fiadd_r80_by_i16 NULL
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| 294 | #define iemAImpl_fimul_r80_by_i16 NULL
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| 295 | #define iemAImpl_fisub_r80_by_i16 NULL
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| 296 | #define iemAImpl_fisubr_r80_by_i16 NULL
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| 297 | #define iemAImpl_fidiv_r80_by_i16 NULL
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| 298 | #define iemAImpl_fidivr_r80_by_i16 NULL
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| 299 |
|
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| 300 | #define iemAImpl_fiadd_r80_by_i32 NULL
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| 301 | #define iemAImpl_fimul_r80_by_i32 NULL
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| 302 | #define iemAImpl_fisub_r80_by_i32 NULL
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| 303 | #define iemAImpl_fisubr_r80_by_i32 NULL
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| 304 | #define iemAImpl_fidiv_r80_by_i32 NULL
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| 305 | #define iemAImpl_fidivr_r80_by_i32 NULL
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| 306 |
|
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| 307 | #define iemCImpl_callf NULL
|
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| 308 | #define iemCImpl_FarJmp NULL
|
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| 309 |
|
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| 310 | #define iemAImpl_pshufhw NULL
|
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| 311 | #define iemAImpl_pshuflw NULL
|
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| 312 | #define iemAImpl_pshufd NULL
|
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| 313 |
|
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| 314 | /** @} */
|
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| 315 |
|
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| 316 |
|
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| 317 | #define IEM_REPEAT_0(a_Callback, a_User) do { } while (0)
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| 318 | #define IEM_REPEAT_1(a_Callback, a_User) a_Callback##_CALLBACK(0, a_User)
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| 319 | #define IEM_REPEAT_2(a_Callback, a_User) IEM_REPEAT_1(a_Callback, a_User); a_Callback##_CALLBACK(1, a_User)
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| 320 | #define IEM_REPEAT_3(a_Callback, a_User) IEM_REPEAT_2(a_Callback, a_User); a_Callback##_CALLBACK(2, a_User)
|
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| 321 | #define IEM_REPEAT_4(a_Callback, a_User) IEM_REPEAT_3(a_Callback, a_User); a_Callback##_CALLBACK(3, a_User)
|
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| 322 | #define IEM_REPEAT_5(a_Callback, a_User) IEM_REPEAT_4(a_Callback, a_User); a_Callback##_CALLBACK(4, a_User)
|
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| 323 | #define IEM_REPEAT_6(a_Callback, a_User) IEM_REPEAT_5(a_Callback, a_User); a_Callback##_CALLBACK(5, a_User)
|
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| 324 | #define IEM_REPEAT_7(a_Callback, a_User) IEM_REPEAT_6(a_Callback, a_User); a_Callback##_CALLBACK(6, a_User)
|
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| 325 | #define IEM_REPEAT_8(a_Callback, a_User) IEM_REPEAT_7(a_Callback, a_User); a_Callback##_CALLBACK(7, a_User)
|
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| 326 | #define IEM_REPEAT_9(a_Callback, a_User) IEM_REPEAT_8(a_Callback, a_User); a_Callback##_CALLBACK(8, a_User)
|
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| 327 | #define IEM_REPEAT(a_cTimes, a_Callback, a_User) RT_CONCAT(IEM_REPEAT_,a_cTimes)(a_Callback, a_User)
|
|---|
| 328 |
|
|---|
| 329 |
|
|---|
| 330 |
|
|---|
| 331 | /** @name Microcode test stubs
|
|---|
| 332 | * @{ */
|
|---|
| 333 |
|
|---|
| 334 | #define IEM_ARG_CHECK_CALLBACK(a_idx, a_User) int RT_CONCAT(iArgCheck_,a_idx); NOREF(RT_CONCAT(iArgCheck_,a_idx))
|
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| 335 | #define IEM_MC_BEGIN(a_cArgs, a_cLocals) \
|
|---|
| 336 | { \
|
|---|
| 337 | const uint8_t cArgs = (a_cArgs); NOREF(cArgs); \
|
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| 338 | const uint8_t cLocals = (a_cLocals); NOREF(cLocals); \
|
|---|
| 339 | const uint8_t fMcBegin = (a_cArgs) + (a_cLocals); \
|
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| 340 | IEM_REPEAT(a_cArgs, IEM_ARG_CHECK, 0); \
|
|---|
| 341 |
|
|---|
| 342 | #define IEM_MC_END() \
|
|---|
| 343 | }
|
|---|
| 344 |
|
|---|
| 345 | #define IEM_MC_PAUSE() do { (void)fMcBegin; } while (0)
|
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| 346 | #define IEM_MC_CONTINUE() do { (void)fMcBegin; } while (0)
|
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| 347 | #define IEM_MC_ADVANCE_RIP() do { (void)fMcBegin; } while (0)
|
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| 348 | #define IEM_MC_REL_JMP_S8(a_i8) do { (void)fMcBegin; CHK_TYPE(int8_t, a_i8); } while (0)
|
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| 349 | #define IEM_MC_REL_JMP_S16(a_i16) do { (void)fMcBegin; CHK_TYPE(int16_t, a_i16); } while (0)
|
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| 350 | #define IEM_MC_REL_JMP_S32(a_i32) do { (void)fMcBegin; CHK_TYPE(int32_t, a_i32); } while (0)
|
|---|
| 351 | #define IEM_MC_SET_RIP_U16(a_u16NewIP) do { (void)fMcBegin; CHK_TYPE(uint16_t, a_u16NewIP); } while (0)
|
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| 352 | #define IEM_MC_SET_RIP_U32(a_u32NewIP) do { (void)fMcBegin; CHK_TYPE(uint32_t, a_u32NewIP); } while (0)
|
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| 353 | #define IEM_MC_SET_RIP_U64(a_u64NewIP) do { (void)fMcBegin; CHK_TYPE(uint64_t, a_u64NewIP); } while (0)
|
|---|
| 354 | #define IEM_MC_RAISE_DIVIDE_ERROR() do { (void)fMcBegin; return VERR_TRPM_ACTIVE_TRAP; } while (0)
|
|---|
| 355 | #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do { (void)fMcBegin; } while (0)
|
|---|
| 356 | #define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() do { (void)fMcBegin; } while (0)
|
|---|
| 357 | #define IEM_MC_MAYBE_RAISE_FPU_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 358 | #define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
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| 359 | #define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() do { (void)fMcBegin; } while (0)
|
|---|
| 360 | #define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
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| 361 | #define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 362 | #define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 363 | #define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 364 | #define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 365 | #define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 366 | #define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do { (void)fMcBegin; } while (0)
|
|---|
| 367 | #define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
|
|---|
| 368 | do { (void)fMcBegin; AssertCompile(RT_IS_POWER_OF_TWO(a_cbAlign)); CHK_TYPE(RTGCPTR, a_EffAddr); } while (0)
|
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| 369 | #define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() do { (void)fMcBegin; } while (0)
|
|---|
| 370 | #define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) do { (void)fMcBegin; } while (0)
|
|---|
| 371 |
|
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| 372 | #define IEM_MC_LOCAL(a_Type, a_Name) (void)fMcBegin; \
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| 373 | a_Type a_Name; NOREF(a_Name); (void)fMcBegin
|
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| 374 | #define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) (void)fMcBegin; \
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| 375 | a_Type const a_Name = (a_Value); \
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| 376 | NOREF(a_Name)
|
|---|
| 377 | #define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (void)fMcBegin; \
|
|---|
| 378 | (a_pRefArg) = &(a_Local)
|
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| 379 |
|
|---|
| 380 | #define IEM_MC_ARG(a_Type, a_Name, a_iArg) (void)fMcBegin; \
|
|---|
| 381 | RT_CONCAT(iArgCheck_,a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
|
|---|
| 382 | int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
|
|---|
| 383 | AssertCompile((a_iArg) < cArgs); \
|
|---|
| 384 | a_Type a_Name; \
|
|---|
| 385 | NOREF(a_Name)
|
|---|
| 386 | #define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) (void)fMcBegin; \
|
|---|
| 387 | RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
|
|---|
| 388 | int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
|
|---|
| 389 | AssertCompile((a_iArg) < cArgs); \
|
|---|
| 390 | a_Type const a_Name = (a_Value); \
|
|---|
| 391 | NOREF(a_Name)
|
|---|
| 392 | #define IEM_MC_ARG_XSTATE(a_Name, a_iArg) \
|
|---|
| 393 | IEM_MC_ARG_CONST(PX86XSAVEAREA, a_Name, NULL, a_iArg)
|
|---|
| 394 |
|
|---|
| 395 | #define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) (void)fMcBegin; \
|
|---|
| 396 | RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
|
|---|
| 397 | int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
|
|---|
| 398 | AssertCompile((a_iArg) < cArgs); \
|
|---|
| 399 | a_Type const a_Name = &(a_Local); \
|
|---|
| 400 | NOREF(a_Name)
|
|---|
| 401 | #define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) (void)fMcBegin; \
|
|---|
| 402 | RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
|
|---|
| 403 | int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \
|
|---|
| 404 | AssertCompile((a_iArg) < cArgs); \
|
|---|
| 405 | uint32_t a_Name; \
|
|---|
| 406 | uint32_t *a_pName = &a_Name; \
|
|---|
| 407 | NOREF(a_pName)
|
|---|
| 408 |
|
|---|
| 409 | #define IEM_MC_COMMIT_EFLAGS(a_EFlags) do { CHK_TYPE(uint32_t, a_EFlags); (void)fMcBegin; } while (0)
|
|---|
| 410 | #define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) do { (a_VarOrArg) = (0); (void)fMcBegin; } while (0)
|
|---|
| 411 | #define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
|
|---|
| 412 |
|
|---|
| 413 | #define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) do { (a_u8Dst) = 0; CHK_TYPE(uint8_t, a_u8Dst); (void)fMcBegin; } while (0)
|
|---|
| 414 | #define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
|
|---|
| 415 | #define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 416 | #define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 417 | #define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
|
|---|
| 418 | #define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 419 | #define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 420 | #define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
|
|---|
| 421 | #define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 422 | #define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 423 | #define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 424 | #define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 425 | #define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 426 | #define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 427 | #define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 428 | #define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 429 | #define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
|
|---|
| 430 | #define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
|
|---|
| 431 | #define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 432 | #define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 433 | #define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 434 | #define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 435 | #define IEM_MC_FETCH_EFLAGS(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint32_t, a_EFlags); (void)fMcBegin; } while (0)
|
|---|
| 436 | #define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint8_t, a_EFlags); (void)fMcBegin; } while (0)
|
|---|
| 437 | #define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); (void)fFpuRead; (void)fMcBegin; } while (0)
|
|---|
| 438 | #define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); (void)fFpuRead; (void)fMcBegin; } while (0)
|
|---|
| 439 | #define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) do { CHK_TYPE(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
|
|---|
| 440 | #define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) do { CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
|
|---|
| 441 | #define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) do { (void)fMcBegin; } while (0)
|
|---|
| 442 | #define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) do { (void)fMcBegin; } while (0)
|
|---|
| 443 | #define IEM_MC_STORE_GREG_U8_CONST(a_iGReg, a_u8C) do { AssertCompile((uint8_t )(a_u8C) == (a_u8C) ); (void)fMcBegin; } while (0)
|
|---|
| 444 | #define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16C) do { AssertCompile((uint16_t)(a_u16C) == (a_u16C)); (void)fMcBegin; } while (0)
|
|---|
| 445 | #define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32C) do { AssertCompile((uint32_t)(a_u32C) == (a_u32C)); (void)fMcBegin; } while (0)
|
|---|
| 446 | #define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u64C) do { AssertCompile((uint64_t)(a_u64C) == (a_u64C)); (void)fMcBegin; } while (0)
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| 447 | #define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) do { CHK_PTYPE(PCRTFLOAT80U, a_pr80Src); Assert((a_iSt) < 8); (void)fMcBegin; } while (0)
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| 448 | #define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) do { (void)fMcBegin; } while (0)
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| 449 | #define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { CHK_PTYPE(uint32_t *, a_pu32Dst); (void)fMcBegin; } while (0)
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| 450 | #define IEM_MC_STORE_SREG_BASE_U64(a_iSeg, a_u64Value) do { (void)fMcBegin; } while (0)
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| 451 | #define IEM_MC_STORE_SREG_BASE_U32(a_iSeg, a_u32Value) do { (void)fMcBegin; } while (0)
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| 452 | #define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) do { (a_pu8Dst) = (uint8_t *)((uintptr_t)0); CHK_PTYPE(uint8_t *, a_pu8Dst); (void)fMcBegin; } while (0)
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| 453 | #define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) do { (a_pu16Dst) = (uint16_t *)((uintptr_t)0); CHK_PTYPE(uint16_t *, a_pu16Dst); (void)fMcBegin; } while (0)
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| 454 | #define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) do { (a_pu32Dst) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pu32Dst); (void)fMcBegin; } while (0)
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| 455 | #define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); (void)fMcBegin; } while (0)
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| 456 | #define IEM_MC_REF_EFLAGS(a_pEFlags) do { (a_pEFlags) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pEFlags); (void)fMcBegin; } while (0)
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| 457 |
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| 458 | #define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
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| 459 | #define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
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| 460 | #define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
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| 461 | #define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
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| 462 | #define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
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| 463 | #define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
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| 464 | #define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
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| 465 | #define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
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| 466 | #define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { CHK_CONST(uint16_t, a_u16Const); (void)fMcBegin; } while (0)
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| 467 |
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| 468 | #define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
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| 469 | #define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
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| 470 | #define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
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| 471 | #define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
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| 472 | #define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
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| 473 | #define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
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| 474 | #define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
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| 475 | #define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
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| 476 |
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| 477 | #define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u8Value) += 1; CHK_TYPE(uint8_t, a_u8Value); (void)fMcBegin; } while (0)
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| 478 | #define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += 1; CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
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| 479 | #define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += 1; CHK_TYPE(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
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| 480 | #define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += 1; CHK_TYPE(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
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| 481 | #define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
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| 482 | #define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
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| 483 | #define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); CHK_GCPTR(a_EffAddr); (void)fMcBegin; } while (0)
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| 484 | #define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); (void)fMcBegin; } while (0)
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| 485 | #define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
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| 486 | #define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
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| 487 | #define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Local); CHK_CONST(uint64_t, a_u64Mask); (void)fMcBegin; } while (0)
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| 488 | #define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Arg); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
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| 489 | #define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Arg); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
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| 490 | #define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Arg); CHK_CONST(uint64_t, a_u64Mask); (void)fMcBegin; } while (0)
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| 491 | #define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); (void)fMcBegin; } while (0)
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| 492 | #define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); (void)fMcBegin; } while (0)
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| 493 | #define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); (void)fMcBegin; } while (0)
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| 494 | #define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 495 | #define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 496 | #define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 497 | #define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 498 | #define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 499 | #define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); (void)fMcBegin; } while (0)
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| 500 | #define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); (void)fMcBegin; } while (0)
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| 501 | #define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); (void)fMcBegin; } while (0)
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| 502 | #define IEM_MC_SET_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
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| 503 | #define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
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| 504 | #define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); (void)fMcBegin; } while (0)
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| 505 | #define IEM_MC_CLEAR_FSW_EX() do { (void)fMcBegin; } while (0)
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| 506 | #define IEM_MC_FPU_TO_MMX_MODE() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 507 | #define IEM_MC_FPU_FROM_MMX_MODE() do { (void)fMcBegin; } while (0)
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| 508 |
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| 509 | #define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fFpuRead; (void)fMcBegin; } while (0)
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| 510 | #define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fFpuRead; (void)fMcBegin; } while (0)
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| 511 | #define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 512 | #define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 513 | #define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 514 | #define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 515 | #define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 516 |
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| 517 | #define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseRead; (void)fMcBegin; } while (0)
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| 518 | #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; (void)fMcBegin; } while (0)
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| 519 | #define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fSseRead; (void)fMcBegin; } while (0)
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| 520 | #define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; (void)fMcBegin; } while (0)
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| 521 | #define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 522 | #define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 523 | #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 524 | #define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 525 | #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 526 | #define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 527 | #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 528 | #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 529 | #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fSseWrite; (void)fMcBegin; } while (0)
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| 530 | #define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) do { (void)fSseWrite; (void)fMcBegin; } while (0)
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| 531 |
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| 532 | #define IEM_MC_FETCH_YREG_U256(a_u256Value, a_iYRegSrc) do { (a_u256Value).au64[0] = (a_u256Value).au64[1] = (a_u256Value).au64[2] = (a_u256Value).au64[3] = 0; CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxRead; (void)fMcBegin; } while (0)
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| 533 | #define IEM_MC_FETCH_YREG_U128(a_u128Value, a_iYRegSrc) do { (a_u128Value).au64[0] = (a_u128Value).au64[1] = 0; CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxRead; (void)fMcBegin; } while (0)
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| 534 | #define IEM_MC_FETCH_YREG_U64(a_u64Value, a_iYRegSrc) do { (a_u64Value) = UINT64_MAX; CHK_TYPE(uint64_t, a_u64Value); (void)fAvxRead; (void)fMcBegin; } while (0)
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| 535 | #define IEM_MC_FETCH_YREG_U32(a_u32Value, a_iYRegSrc) do { (a_u32Value) = UINT32_MAX; CHK_TYPE(uint32_t, a_u32Value); (void)fAvxRead; (void)fMcBegin; } while (0)
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| 536 | #define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 537 | #define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 538 | #define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Value) do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 539 | #define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Value) do { CHK_TYPE(RTUINT256U, a_u256Value); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 540 | #define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) do { (a_pu128Dst) = (PRTUINT128U)((uintptr_t)0); CHK_PTYPE(PRTUINT128U, a_pu128Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 541 | #define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) do { (a_pu128Dst) = (PCRTUINT128U)((uintptr_t)0); CHK_PTYPE(PCRTUINT128U, a_pu128Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 542 | #define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 543 | #define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) do { (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 544 | #define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 545 | #define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 546 | #define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; (void)fMcBegin; } while (0)
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| 547 | #define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
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| 548 | #define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
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| 549 | #define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
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|---|
| 550 | #define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { (void)fAvxWrite; (void)fAvxRead; (void)fMcBegin; } while (0)
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|---|
| 551 |
|
|---|
| 552 | #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 553 | #define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); (void)fMcBegin; } while (0)
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|---|
| 554 | #define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); (void)fMcBegin; } while (0)
|
|---|
| 555 | #define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 556 | #define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int16_t, a_i16Dst); (void)fMcBegin; } while (0)
|
|---|
| 557 | #define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 558 | #define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); (void)fMcBegin; } while (0)
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|---|
| 559 | #define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 560 | #define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 561 | #define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
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|---|
| 562 | #define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int64_t, a_i64Dst); (void)fMcBegin; } while (0)
|
|---|
| 563 |
|
|---|
| 564 | #define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
|
|---|
| 565 | do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); (void)fMcBegin; } while (0)
|
|---|
| 566 | #define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
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|---|
| 567 | do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint16_t, a_u16Dst); (void)fMcBegin; } while (0)
|
|---|
| 568 | #define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
|
|---|
| 569 | do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint32_t, a_u32Dst); (void)fMcBegin; } while (0)
|
|---|
| 570 | #define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
|
|---|
| 571 | do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); (void)fMcBegin; } while (0)
|
|---|
| 572 |
|
|---|
| 573 | #define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 574 | #define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 575 | #define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 576 | #define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 577 | #define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 578 | #define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 579 | #define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 580 | #define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 581 | #define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 582 | #define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 583 | #define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 584 | #define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); (void)fMcBegin; } while (0)
|
|---|
| 585 | #define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst); (void)fMcBegin; } while (0)
|
|---|
| 586 | #define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst); (void)fMcBegin; } while (0)
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|---|
| 587 | #define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst); (void)fMcBegin; } while (0)
|
|---|
| 588 | #define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); (void)fMcBegin; } while (0)
|
|---|
| 589 | #define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Dst); (void)fMcBegin; } while (0)
|
|---|
| 590 | #define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0)
|
|---|
| 591 | #define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Dst); (void)fMcBegin; } while (0)
|
|---|
| 592 |
|
|---|
| 593 | #define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
|
|---|
| 594 | #define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); (void)fMcBegin; } while (0)
|
|---|
| 595 | #define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); (void)fMcBegin; } while (0)
|
|---|
| 596 | #define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); (void)fMcBegin; } while (0)
|
|---|
| 597 | #define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); (void)fMcBegin; } while (0)
|
|---|
| 598 | #define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint16_t, a_u16C); (void)fMcBegin; } while (0)
|
|---|
| 599 | #define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint32_t, a_u32C); (void)fMcBegin; } while (0)
|
|---|
| 600 | #define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint64_t, a_u64C); (void)fMcBegin; } while (0)
|
|---|
| 601 | #define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) do { CHK_TYPE(int8_t *, a_pi8Dst); CHK_CONST(int8_t, a_i8C); (void)fMcBegin; } while (0)
|
|---|
| 602 | #define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) do { CHK_TYPE(int16_t *, a_pi16Dst); CHK_CONST(int16_t, a_i16C); (void)fMcBegin; } while (0)
|
|---|
| 603 | #define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) do { CHK_TYPE(int32_t *, a_pi32Dst); CHK_CONST(int32_t, a_i32C); (void)fMcBegin; } while (0)
|
|---|
| 604 | #define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) do { CHK_TYPE(int64_t *, a_pi64Dst); CHK_CONST(int64_t, a_i64C); (void)fMcBegin; } while (0)
|
|---|
| 605 | #define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); (void)fMcBegin; } while (0)
|
|---|
| 606 | #define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); (void)fMcBegin; } while (0)
|
|---|
| 607 | #define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); (void)fMcBegin; } while (0)
|
|---|
| 608 | #define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Src) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Src); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
|
|---|
| 609 | #define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Src) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT128U, a_u128Src); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
|
|---|
| 610 | #define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Src) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Src); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
|
|---|
| 611 | #define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Src) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTUINT256U, a_u256Src); CHK_SEG_IDX(a_iSeg); (void)fMcBegin; } while (0)
|
|---|
| 612 |
|
|---|
| 613 | #define IEM_MC_PUSH_U16(a_u16Value) do { (void)fMcBegin; } while (0)
|
|---|
| 614 | #define IEM_MC_PUSH_U32(a_u32Value) do { (void)fMcBegin; } while (0)
|
|---|
| 615 | #define IEM_MC_PUSH_U32_SREG(a_u32Value) do { (void)fMcBegin; } while (0)
|
|---|
| 616 | #define IEM_MC_PUSH_U64(a_u64Value) do { (void)fMcBegin; } while (0)
|
|---|
| 617 | #define IEM_MC_POP_U16(a_pu16Value) do { (void)fMcBegin; } while (0)
|
|---|
| 618 | #define IEM_MC_POP_U32(a_pu32Value) do { (void)fMcBegin; } while (0)
|
|---|
| 619 | #define IEM_MC_POP_U64(a_pu64Value) do { (void)fMcBegin; } while (0)
|
|---|
| 620 | #define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) do { (void)fMcBegin; } while (0)
|
|---|
| 621 | #define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do { (void)fMcBegin; } while (0)
|
|---|
| 622 | #define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do { (void)fMcBegin; } while (0)
|
|---|
| 623 | #define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do { (void)fMcBegin; } while (0)
|
|---|
| 624 | #define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); (void)fMcBegin; } while (0)
|
|---|
| 625 | #define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) do { (void)fMcBegin; } while (0)
|
|---|
| 626 | #define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \
|
|---|
| 627 | do { CHK_CALL_ARG(a0, 0); (void)fMcBegin; } while (0)
|
|---|
| 628 | #define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \
|
|---|
| 629 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
|
|---|
| 630 | #define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \
|
|---|
| 631 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 632 | #define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \
|
|---|
| 633 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
|
|---|
| 634 | #define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
|
|---|
| 635 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
|
|---|
| 636 | #define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
|
|---|
| 637 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
|
|---|
| 638 | #define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) do { (void)fMcBegin; } while (0)
|
|---|
| 639 | #define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) \
|
|---|
| 640 | do { CHK_CALL_ARG(a0, 0); (void)fMcBegin; } while (0)
|
|---|
| 641 | #define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) \
|
|---|
| 642 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
|
|---|
| 643 | #define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) \
|
|---|
| 644 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 645 | #define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) \
|
|---|
| 646 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
|
|---|
| 647 | #define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) \
|
|---|
| 648 | do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; } while (0)
|
|---|
| 649 | #define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (VINF_SUCCESS)
|
|---|
| 650 | #define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (VINF_SUCCESS)
|
|---|
| 651 | #define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (VINF_SUCCESS)
|
|---|
| 652 | #define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (VINF_SUCCESS)
|
|---|
| 653 |
|
|---|
| 654 | #define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
|
|---|
| 655 | do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); (void)fMcBegin; } while (0)
|
|---|
| 656 | #define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
|
|---|
| 657 | do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
|
|---|
| 658 | #define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
|
|---|
| 659 | do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 660 | #define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 661 | #define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 662 | #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 663 | #define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 664 | #define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 665 | #define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 666 | #define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 667 | #define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 668 | #define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 669 | #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 670 | #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 671 | #define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 672 | #define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 673 | #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 674 | #define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 675 | #define IEM_MC_FPU_STACK_PUSH_OVERFLOW() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 676 | #define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 677 | #define IEM_MC_UPDATE_FPU_OPCODE_IP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 678 | #define IEM_MC_FPU_STACK_DEC_TOP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 679 | #define IEM_MC_FPU_STACK_INC_TOP() do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 680 | #define IEM_MC_FPU_STACK_FREE(a_iStReg) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 681 | #define IEM_MC_UPDATE_FSW(a_u16FSW) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 682 | #define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 683 | #define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 684 | #define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
|---|
| 685 | #define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
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| 686 | #define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { (void)fFpuWrite; (void)fMcBegin; } while (0)
|
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| 687 | #define IEM_MC_PREPARE_FPU_USAGE() (void)fMcBegin; \
|
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| 688 | const int fFpuRead = 1, fFpuWrite = 1, fFpuHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1, fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1
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| 689 | #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() (void)fMcBegin; const int fFpuRead = 1, fSseRead = 1
|
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| 690 | #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() (void)fMcBegin; const int fFpuRead = 1, fFpuWrite = 1, fSseRead = 1, fSseWrite = 1
|
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| 691 | #define IEM_MC_PREPARE_SSE_USAGE() (void)fMcBegin; const int fSseRead = 1, fSseWrite = 1, fSseHost = 1
|
|---|
| 692 | #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() (void)fMcBegin; const int fSseRead = 1
|
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| 693 | #define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() (void)fMcBegin; const int fSseRead = 1, fSseWrite = 1
|
|---|
| 694 | #define IEM_MC_PREPARE_AVX_USAGE() (void)fMcBegin; const int fAvxRead = 1, fAvxWrite = 1, fAvxHost = 1, fSseRead = 1, fSseWrite = 1, fSseHost = 1
|
|---|
| 695 | #define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() (void)fMcBegin; const int fAvxRead = 1, fSseRead = 1
|
|---|
| 696 | #define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() (void)fMcBegin; const int fAvxRead = 1, fAvxWrite = 1, fSseRead = 1, fSseWrite = 1
|
|---|
| 697 |
|
|---|
| 698 | #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
|
|---|
| 699 | do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
|
|---|
| 700 | #define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
|
|---|
| 701 | do { (void)fFpuHost; (void)fFpuWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 702 | #define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
|
|---|
| 703 | do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); (void)fMcBegin; } while (0)
|
|---|
| 704 | #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
|
|---|
| 705 | do { (void)fSseHost; (void)fSseWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 706 | #define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() do { IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, pVCpu->cpum.GstCtx.CTX_SUFF(pXState), 0); (void)fMcBegin; } while (0)
|
|---|
| 707 | #define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
|
|---|
| 708 | do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
|
|---|
| 709 | #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
|
|---|
| 710 | do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
|
|---|
| 711 | #define IEM_MC_CALL_AVX_AIMPL_4(a_pfnAImpl, a1, a2, a3, a4) \
|
|---|
| 712 | do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); (void)fMcBegin; } while (0)
|
|---|
| 713 |
|
|---|
| 714 | #define IEM_MC_IF_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 715 | #define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 716 | #define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 717 | #define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 718 | #define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 719 | #define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 720 | #define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 721 | #define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 722 | #define IEM_MC_IF_CX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
|
|---|
| 723 | #define IEM_MC_IF_ECX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
|
|---|
| 724 | #define IEM_MC_IF_RCX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
|
|---|
| 725 | #define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 726 | #define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 727 | #define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 728 | #define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 729 | #define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 730 | #define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 731 | #define IEM_MC_IF_LOCAL_IS_Z(a_Local) (void)fMcBegin; if ((a_Local) == 0) {
|
|---|
| 732 | #define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) (void)fMcBegin; if (g_fRandom) {
|
|---|
| 733 | #define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) (void)fMcBegin; if (g_fRandom != fFpuRead) {
|
|---|
| 734 | #define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) (void)fMcBegin; if (g_fRandom != fFpuRead) {
|
|---|
| 735 | #define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) (void)fMcBegin; \
|
|---|
| 736 | a_pr80Dst = NULL; \
|
|---|
| 737 | if (g_fRandom != fFpuRead) {
|
|---|
| 738 | #define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(p0, i0, p1, i1) (void)fMcBegin; \
|
|---|
| 739 | p0 = NULL; \
|
|---|
| 740 | p1 = NULL; \
|
|---|
| 741 | if (g_fRandom != fFpuRead) {
|
|---|
| 742 | #define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(p0, i0, i1) (void)fMcBegin; \
|
|---|
| 743 | p0 = NULL; \
|
|---|
| 744 | if (g_fRandom != fFpuRead) {
|
|---|
| 745 | #define IEM_MC_IF_FCW_IM() (void)fMcBegin; if (g_fRandom != fFpuRead) {
|
|---|
| 746 | #define IEM_MC_ELSE() } else {
|
|---|
| 747 | #define IEM_MC_ENDIF() } do { (void)fMcBegin; } while (0)
|
|---|
| 748 |
|
|---|
| 749 | /** @} */
|
|---|
| 750 |
|
|---|
| 751 | #include "../VMMAll/IEMAllInstructions.cpp.h"
|
|---|
| 752 |
|
|---|
| 753 |
|
|---|
| 754 |
|
|---|
| 755 | /**
|
|---|
| 756 | * Formalities...
|
|---|
| 757 | */
|
|---|
| 758 | int main()
|
|---|
| 759 | {
|
|---|
| 760 | RTTEST hTest;
|
|---|
| 761 | RTEXITCODE rcExit = RTTestInitAndCreate("tstIEMCheckMc", &hTest);
|
|---|
| 762 | if (rcExit == RTEXITCODE_SUCCESS)
|
|---|
| 763 | {
|
|---|
| 764 | RTTestBanner(hTest);
|
|---|
| 765 | RTTestPrintf(hTest, RTTESTLVL_ALWAYS, "(this is only a compile test.)");
|
|---|
| 766 | rcExit = RTTestSummaryAndDestroy(hTest);
|
|---|
| 767 | }
|
|---|
| 768 | return rcExit;
|
|---|
| 769 | }
|
|---|
