VirtualBox

source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport-arm.cpp

Last change on this file was 109166, checked in by vboxsync, 7 days ago

VBoxCpuReporter: Took a shot at getting the info using hv_vcpu_get_sys_reg & hv_vcpu_config_get_feature_reg. jiraref:VBP-1653
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1/* $Id: VBoxCpuReport-arm.cpp 109166 2025-05-05 23:50:35Z vboxsync $ */
2/** @file
3 * VBoxCpuReport - Produces the basis for a CPU DB entry, x86 specifics.
4 */
5
6/*
7 * Copyright (C) 2013-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#include <iprt/ctype.h>
33#include <iprt/message.h>
34#include <iprt/mem.h>
35#include <iprt/string.h>
36#include <iprt/sort.h>
37
38#include <VBox/err.h>
39#include <VBox/vmm/cpum.h>
40#include <VBox/sup.h>
41
42#ifdef RT_OS_DARWIN
43# include <Hypervisor/Hypervisor.h>
44#endif
45
46#include "VBoxCpuReport.h"
47
48
49/*********************************************************************************************************************************
50* Structures and Typedefs *
51*********************************************************************************************************************************/
52typedef struct PARTNUMINFO
53{
54 uint32_t uPartNum;
55 CPUMMICROARCH enmMicroarch;
56 const char *pszName;
57 const char *pszFullName;
58 CPUMCORETYPE enmCoreType;
59} PARTNUMINFO;
60
61
62/*********************************************************************************************************************************
63* Global Variables *
64*********************************************************************************************************************************/
65static struct CPUCOREVARIATION
66{
67 /** @name Set by populateSystemRegisters().
68 * @{ */
69 RTCPUSET bmMembers;
70 uint32_t cCores;
71 uint32_t cSysRegVals;
72 SUPARMSYSREGVAL aSysRegVals[256];
73 /** @} */
74
75 /** @name Set later by produceCpuReport().
76 * @{ */
77 uint64_t uMIdReg;
78 CPUMCPUVENDOR enmVendor;
79 CPUMCORETYPE enmCoreType;
80 CPUMMICROARCH enmMicroarch;
81 const char *pszName;
82 const char *pszFullName;
83 /** @} */
84} g_aVariations[RTCPUSET_MAX_CPUS];
85static uint32_t g_cVariations = 0;
86static uint32_t g_cCores = 0;
87
88static uint32_t g_cCmnSysRegVals = 0;
89static SUPARMSYSREGVAL g_aCmnSysRegVals[256];
90
91static bool g_fOtherSysRegSource = false;
92
93
94/** ARM CPU info by part number. */
95static PARTNUMINFO const g_aPartNumDbArm[] =
96{
97 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
98};
99
100/** Broadcom CPU info by part number. */
101static PARTNUMINFO const g_aPartNumDbBroadcom[] =
102{
103 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
104};
105
106/** Qualcomm CPU info by part number. */
107static PARTNUMINFO const g_aPartNumDbQualcomm[] =
108{
109 { 0x0d4b, kCpumMicroarch_Qualcomm_Kyro, "Qualcomm Snapdragon 8cx Gen 3", "Qualcomm Snapdragon 8cx Gen 3 (Kryo Prime)", kCpumCoreType_Efficiency }, /* Guessing which part */ /*MIDR_EL1=0x410FD4B0*/
110 { 0x0d4c, kCpumMicroarch_Qualcomm_Kyro, "Qualcomm Snapdragon 8cx Gen 3", "Qualcomm Snapdragon 8cx Gen 3 (Kryo Gold)", kCpumCoreType_Performance }, /* is for which core... */ /*MIDR_EL1=0x410FD4C0*/
111 { 0x1001, kCpumMicroarch_Qualcomm_Oryon, "Qualcomm Snapdragon X", "Qualcomm Snapdragon X (Oryon var 1)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x511f0011 (perf?)*/
112 { 0x2001, kCpumMicroarch_Qualcomm_Oryon, "Qualcomm Snapdragon X", "Qualcomm Snapdragon X (Oryon var 2)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x512f0011 (eff?)*/
113};
114
115/** Apple CPU info by part number. */
116static PARTNUMINFO const g_aPartNumDbApple[] =
117{
118 { 0x022, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Icestorm)", kCpumCoreType_Efficiency },
119 { 0x023, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Firestorm)", kCpumCoreType_Performance },
120 { 0x024, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Icestorm)", kCpumCoreType_Efficiency },
121 { 0x025, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Firestorm)", kCpumCoreType_Performance },
122 { 0x028, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Icestorm)", kCpumCoreType_Efficiency },
123 { 0x029, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Firestorm)", kCpumCoreType_Performance },
124 /** @todo some sources lists 0x30/31 as plain m2... */
125 { 0x032, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Blizzard)", kCpumCoreType_Efficiency },
126 { 0x033, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Avalanche)", kCpumCoreType_Performance },
127 { 0x034, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Blizzard)", kCpumCoreType_Efficiency },
128 { 0x035, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Avalanche)", kCpumCoreType_Performance },
129 { 0x038, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Blizzard)", kCpumCoreType_Efficiency },
130 { 0x039, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Avalanche)", kCpumCoreType_Performance },
131 { 0x048, kCpumMicroarch_Apple_M3, "Apple M3 Max", "Apple M3 Max (Sawtooth)", kCpumCoreType_Efficiency }, /** @todo code names */
132 { 0x049, kCpumMicroarch_Apple_M3, "Apple M3 Max", "Apple M3 Max (Everest)", kCpumCoreType_Performance }, /** @todo code names */
133};
134
135/** Ampere CPU info by part number. */
136static PARTNUMINFO const g_aPartNumDbAmpere[] =
137{
138 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
139};
140
141
142/** @callback_impl{FNRTSORTCMP} */
143static DECLCALLBACK(int) variationSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
144{
145 RT_NOREF(pvUser);
146 struct CPUCOREVARIATION const * const pElm1 = (struct CPUCOREVARIATION const *)pvElement1;
147 struct CPUCOREVARIATION const * const pElm2 = (struct CPUCOREVARIATION const *)pvElement2;
148
149 /* Sort by core type, putting the efficiency cores before performance and performance before unknown ones. */
150 AssertCompile(kCpumCoreType_Efficiency < kCpumCoreType_Performance && kCpumCoreType_Performance < kCpumCoreType_Unknown);
151 return (int)pElm1->enmCoreType < (int)pElm2->enmCoreType ? -1
152 : (int)pElm1->enmCoreType > (int)pElm2->enmCoreType ? 1
153 : 0;
154}
155
156
157/** Looks up a register entry in an array. */
158static SUPARMSYSREGVAL *lookupSysReg(SUPARMSYSREGVAL *paSysRegVals, uint32_t const cSysRegVals, uint32_t const idReg)
159{
160 for (uint32_t i = 0; i < cSysRegVals; i++)
161 if (paSysRegVals[i].idReg == idReg)
162 return &paSysRegVals[i];
163 return NULL;
164}
165
166
167/** Looks up a register value in g_aSysRegVals. */
168static uint64_t getSysRegVal(uint32_t idReg, uint32_t iVar, uint64_t uNotFoundValue = 0)
169{
170 SUPARMSYSREGVAL const *pVal = lookupSysReg(g_aCmnSysRegVals, g_cCmnSysRegVals, idReg);
171 if (!pVal && iVar < g_cVariations)
172 pVal = lookupSysReg(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals, idReg);
173 return pVal ? pVal->uValue : uNotFoundValue;
174}
175
176
177/**
178 * Translates system register ID to a string, returning NULL if we can't.
179 */
180static const char *sysRegNoToName(uint32_t idReg)
181{
182 switch (idReg)
183 {
184 /* The stuff here is copied from SUPDrv.cpp and trimmed down to the reads: */
185#define READ_SYS_REG_NAMED(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
186 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
187#define READ_SYS_REG__TODO(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
188 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
189#define READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
190 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return NULL
191
192 READ_SYS_REG_NAMED(3, 0, 0, 0, 0, MIDR_EL1);
193 READ_SYS_REG_NAMED(3, 0, 0, 0, 5, MPIDR_EL1);
194 READ_SYS_REG_NAMED(3, 0, 0, 0, 6, REVIDR_EL1);
195 READ_SYS_REG__TODO(3, 1, 0, 0, 0, CCSIDR_EL1);
196 READ_SYS_REG__TODO(3, 1, 0, 0, 1, CLIDR_EL1);
197 READ_SYS_REG__TODO(3, 1, 0, 0, 7, AIDR_EL1);
198 READ_SYS_REG_NAMED(3, 3, 0, 0, 1, CTR_EL0);
199 READ_SYS_REG_NAMED(3, 3, 0, 0, 7, DCZID_EL0);
200 READ_SYS_REG_NAMED(3, 3,14, 0, 0, CNTFRQ_EL0);
201
202 READ_SYS_REG_NAMED(3, 0, 0, 4, 0, ID_AA64PFR0_EL1);
203 READ_SYS_REG_NAMED(3, 0, 0, 4, 1, ID_AA64PFR1_EL1);
204 READ_SYS_REG_UNDEF(3, 0, 0, 4, 2);
205 READ_SYS_REG_UNDEF(3, 0, 0, 4, 3);
206 READ_SYS_REG_NAMED(3, 0, 0, 4, 4, ID_AA64ZFR0_EL1);
207 READ_SYS_REG_NAMED(3, 0, 0, 4, 5, ID_AA64SMFR0_EL1);
208 READ_SYS_REG_UNDEF(3, 0, 0, 4, 6);
209 READ_SYS_REG_UNDEF(3, 0, 0, 4, 7);
210
211 READ_SYS_REG_NAMED(3, 0, 0, 5, 0, ID_AA64DFR0_EL1);
212 READ_SYS_REG_NAMED(3, 0, 0, 5, 1, ID_AA64DFR1_EL1);
213 READ_SYS_REG_UNDEF(3, 0, 0, 5, 2);
214 READ_SYS_REG_UNDEF(3, 0, 0, 5, 3);
215 READ_SYS_REG_NAMED(3, 0, 0, 5, 4, ID_AA64AFR0_EL1);
216 READ_SYS_REG_NAMED(3, 0, 0, 5, 5, ID_AA64AFR1_EL1);
217 READ_SYS_REG_UNDEF(3, 0, 0, 5, 6);
218 READ_SYS_REG_UNDEF(3, 0, 0, 5, 7);
219
220 READ_SYS_REG_NAMED(3, 0, 0, 6, 0, ID_AA64ISAR0_EL1);
221 READ_SYS_REG_NAMED(3, 0, 0, 6, 1, ID_AA64ISAR1_EL1);
222 READ_SYS_REG_NAMED(3, 0, 0, 6, 2, ID_AA64ISAR2_EL1);
223 READ_SYS_REG__TODO(3, 0, 0, 6, 3, ID_AA64ISAR3_EL1);
224 READ_SYS_REG_UNDEF(3, 0, 0, 6, 4);
225 READ_SYS_REG_UNDEF(3, 0, 0, 6, 5);
226 READ_SYS_REG_UNDEF(3, 0, 0, 6, 6);
227 READ_SYS_REG_UNDEF(3, 0, 0, 6, 7);
228
229 READ_SYS_REG_NAMED(3, 0, 0, 7, 0, ID_AA64MMFR0_EL1);
230 READ_SYS_REG_NAMED(3, 0, 0, 7, 1, ID_AA64MMFR1_EL1);
231 READ_SYS_REG_NAMED(3, 0, 0, 7, 2, ID_AA64MMFR2_EL1);
232 READ_SYS_REG__TODO(3, 0, 0, 7, 3, ID_AA64MMFR3_EL1);
233 READ_SYS_REG__TODO(3, 0, 0, 7, 4, ID_AA64MMFR4_EL1);
234 READ_SYS_REG_UNDEF(3, 0, 0, 7, 5);
235 READ_SYS_REG_UNDEF(3, 0, 0, 7, 6);
236 READ_SYS_REG_UNDEF(3, 0, 0, 7, 7);
237
238 READ_SYS_REG_NAMED(3, 0, 0, 1, 0, ID_PFR0_EL1);
239 READ_SYS_REG_NAMED(3, 0, 0, 1, 1, ID_PFR1_EL1);
240
241 READ_SYS_REG_NAMED(3, 0, 0, 1, 2, ID_DFR0_EL1);
242
243 READ_SYS_REG_NAMED(3, 0, 0, 1, 3, ID_AFR0_EL1);
244
245 READ_SYS_REG_NAMED(3, 0, 0, 1, 4, ID_MMFR0_EL1);
246 READ_SYS_REG_NAMED(3, 0, 0, 1, 5, ID_MMFR1_EL1);
247 READ_SYS_REG_NAMED(3, 0, 0, 1, 6, ID_MMFR2_EL1);
248 READ_SYS_REG_NAMED(3, 0, 0, 1, 7, ID_MMFR3_EL1);
249
250 READ_SYS_REG_NAMED(3, 0, 0, 2, 0, ID_ISAR0_EL1);
251 READ_SYS_REG_NAMED(3, 0, 0, 2, 1, ID_ISAR1_EL1);
252 READ_SYS_REG_NAMED(3, 0, 0, 2, 2, ID_ISAR2_EL1);
253 READ_SYS_REG_NAMED(3, 0, 0, 2, 3, ID_ISAR3_EL1);
254 READ_SYS_REG_NAMED(3, 0, 0, 2, 4, ID_ISAR4_EL1);
255 READ_SYS_REG_NAMED(3, 0, 0, 2, 5, ID_ISAR5_EL1);
256
257 READ_SYS_REG_NAMED(3, 0, 0, 2, 6, ID_MMFR4_EL1);
258
259 READ_SYS_REG_NAMED(3, 0, 0, 2, 7, ID_ISAR6_EL1);
260
261 READ_SYS_REG_NAMED(3, 0, 0, 3, 0, MVFR0_EL1);
262 READ_SYS_REG_NAMED(3, 0, 0, 3, 1, MVFR1_EL1);
263 READ_SYS_REG_NAMED(3, 0, 0, 3, 2, MVFR2_EL1);
264
265 READ_SYS_REG_NAMED(3, 0, 0, 3, 4, ID_PFR2_EL1);
266
267 READ_SYS_REG_NAMED(3, 0, 0, 3, 5, ID_DFR1_EL1);
268
269 READ_SYS_REG_NAMED(3, 0, 0, 3, 6, ID_MMFR5_EL1);
270
271 READ_SYS_REG__TODO(3, 1, 0, 0, 2, CCSIDR2_EL1); /*?*/
272
273 READ_SYS_REG_NAMED(3, 0, 5, 3, 0, ERRIDR_EL1);
274
275 READ_SYS_REG__TODO(3, 1, 0, 0, 4, GMID_EL1);
276
277 READ_SYS_REG__TODO(3, 0, 10, 4, 4, MPAMIDR_EL1);
278 READ_SYS_REG__TODO(3, 0, 10, 4, 5, MPAMBWIDR_EL1);
279
280 READ_SYS_REG__TODO(3, 0, 9, 10, 7, PMBIDR_EL1);
281 READ_SYS_REG__TODO(3, 0, 9, 8, 7, PMSIDR_EL1);
282
283 READ_SYS_REG__TODO(3, 0, 9, 11, 7, TRBIDR_EL1);
284
285 READ_SYS_REG__TODO(2, 1, 0, 8, 7, TRCIDR0); /*?*/
286 READ_SYS_REG__TODO(2, 1, 0, 9, 7, TRCIDR1);
287 READ_SYS_REG__TODO(2, 1, 0,10, 7, TRCIDR2);
288 READ_SYS_REG__TODO(2, 1, 0,11, 7, TRCIDR3);
289 READ_SYS_REG__TODO(2, 1, 0,12, 7, TRCIDR4);
290 READ_SYS_REG__TODO(2, 1, 0,13, 7, TRCIDR5);
291 READ_SYS_REG__TODO(2, 1, 0,14, 7, TRCIDR6);
292 READ_SYS_REG__TODO(2, 1, 0,15, 7, TRCIDR7);
293 READ_SYS_REG__TODO(2, 1, 0, 0, 6, TRCIDR8);
294 READ_SYS_REG__TODO(2, 1, 0, 1, 6, TRCIDR9);
295 READ_SYS_REG__TODO(2, 1, 0, 2, 6, TRCIDR10);
296 READ_SYS_REG__TODO(2, 1, 0, 3, 6, TRCIDR11);
297 READ_SYS_REG__TODO(2, 1, 0, 4, 6, TRCIDR12);
298 READ_SYS_REG__TODO(2, 1, 0, 5, 6, TRCIDR13);
299
300#undef READ_SYS_REG_NAMED
301#undef READ_SYS_REG__TODO
302#undef READ_SYS_REG_UNDEF
303 }
304 return NULL;
305}
306
307
308/** @callback_impl{FNRTSORTCMP} */
309static DECLCALLBACK(int) sysRegValSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
310{
311 RT_NOREF(pvUser);
312 PCSUPARMSYSREGVAL const pElm1 = (PCSUPARMSYSREGVAL)pvElement1;
313 PCSUPARMSYSREGVAL const pElm2 = (PCSUPARMSYSREGVAL)pvElement2;
314 return pElm1->idReg < pElm2->idReg ? -1 : pElm1->idReg > pElm2->idReg ? 1 : 0;
315}
316
317
318static int populateSystemRegistersComplete(void)
319{
320 vbCpuRepDebug("Detected %u variants across %u online CPUs\n", g_cVariations, g_cCores);
321
322 /*
323 * Now, destill similar register values and unique ones.
324 * This isn't too complicated since the arrays have been sorted.
325 */
326 g_cCmnSysRegVals = 0;
327
328 uint32_t cMaxRegs = g_aVariations[0].cSysRegVals;
329 for (unsigned i = 0; i < g_cVariations; i++)
330 cMaxRegs = RT_MAX(cMaxRegs, g_aVariations[i].cSysRegVals);
331
332 struct
333 {
334 unsigned idxSrc;
335 unsigned idxDst;
336 } aState[RTCPUSET_MAX_CPUS] = { {0, 0} };
337
338 for (;;)
339 {
340 /* Find the min & max register value. */
341 uint32_t idRegMax = 0;
342 uint32_t idRegMin = UINT32_MAX;
343 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
344 {
345 unsigned const idxSrc = aState[iVar].idxSrc;
346
347 uint32_t const idReg = idxSrc < g_aVariations[iVar].cSysRegVals
348 ? g_aVariations[iVar].aSysRegVals[idxSrc].idReg : UINT32_MAX;
349 idRegMax = RT_MAX(idRegMax, idReg);
350 idRegMin = RT_MIN(idRegMin, idReg);
351 }
352 if (idRegMin == UINT32_MAX)
353 break;
354
355 /* Advance all arrays till we've reached idRegMax. */
356 unsigned cMatchedMax = 0;
357 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
358 {
359 unsigned idxSrc = aState[iVar].idxSrc;
360 unsigned idxDst = aState[iVar].idxDst;
361 while ( idxSrc < g_aVariations[iVar].cSysRegVals
362 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg < idRegMax)
363 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
364 cMatchedMax += idxSrc < g_aVariations[iVar].cSysRegVals
365 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax;
366 aState[iVar].idxSrc = idxSrc;
367 aState[iVar].idxDst = idxDst;
368 }
369 if (idRegMax == UINT32_MAX)
370 break;
371
372 if (cMatchedMax == g_cVariations)
373 {
374 /* Check if all the values match. */
375 uint64_t const uValue0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].uValue;
376 uint32_t const fFlags0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].fFlags;
377 unsigned cMatches = 1;
378 for (unsigned iVar = 1; iVar < g_cVariations; iVar++)
379 {
380 unsigned const idxSrc = aState[iVar].idxSrc;
381 Assert(idxSrc < g_aVariations[iVar].cSysRegVals);
382 Assert(g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax);
383 cMatches += g_aVariations[iVar].aSysRegVals[idxSrc].uValue == uValue0
384 && g_aVariations[iVar].aSysRegVals[idxSrc].fFlags == fFlags0;
385 }
386 if (cMatches == g_cVariations)
387 {
388 g_aCmnSysRegVals[g_cCmnSysRegVals++] = g_aVariations[0].aSysRegVals[aState[0].idxSrc];
389 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
390 aState[iVar].idxSrc += 1;
391 continue;
392 }
393 vbCpuRepDebug("%#x: missed #2\n", idRegMax);
394 }
395 else
396 vbCpuRepDebug("%#x: missed #1\n", idRegMax);
397
398 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
399 {
400 Assert(aState[iVar].idxSrc < g_aVariations[iVar].cSysRegVals);
401 g_aVariations[iVar].aSysRegVals[aState[iVar].idxDst++]
402 = g_aVariations[iVar].aSysRegVals[aState[iVar].idxSrc++];
403 }
404 }
405 vbCpuRepDebug("Common register values: %u\n", g_cCmnSysRegVals);
406
407 /* Anything left in any of the arrays are considered unique and needs to be moved up. */
408 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
409 {
410 unsigned idxSrc = aState[iVar].idxSrc;
411 unsigned idxDst = aState[iVar].idxDst;
412 Assert(idxDst <= idxSrc);
413 Assert(idxSrc == g_aVariations[iVar].cSysRegVals);
414 while (idxSrc < g_aVariations[iVar].cSysRegVals)
415 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
416 g_aVariations[iVar].cSysRegVals = idxDst;
417 vbCpuRepDebug("Var #%u register values: %u\n", iVar, idxDst);
418 }
419 return VINF_SUCCESS;
420}
421
422
423/**
424 * Populates g_aSysRegVals and g_cSysRegVals
425 */
426static int populateSystemRegisters(void)
427{
428 /*
429 * First try using the support driver.
430 */
431 int rc = SUPR3Init(NULL);
432 if (RT_SUCCESS(rc))
433 {
434 /*
435 * Get the registers for online each CPU in the system, sorting them.
436 */
437 vbCpuRepDebug("Gathering CPU info via the support driver...\n");
438 for (int idxCpu = 0, iVar = 0; idxCpu < RTCPUSET_MAX_CPUS; idxCpu++)
439 if (RTMpIsCpuOnline(idxCpu))
440 {
441 RTCPUID const idCpu = RTMpCpuIdFromSetIndex(idxCpu);
442 uint32_t cTries = 0; /* Kludge for M3 Max / 14.7.5. Takes anywhere from 44 to at least 144 tries. */
443 uint32_t cRegAvailable;
444 do
445 {
446 cRegAvailable = 0;
447 g_aVariations[iVar].cSysRegVals = 0;
448 rc = SUPR3ArmQuerySysRegs(idCpu,
449 SUP_ARM_SYS_REG_F_INC_ZERO_REG_VAL | SUP_ARM_SYS_REG_F_EXTENDED,
450 RT_ELEMENTS(g_aVariations[iVar].aSysRegVals),
451 &g_aVariations[iVar].cSysRegVals,
452 &cRegAvailable,
453 g_aVariations[iVar].aSysRegVals);
454 } while (rc == VERR_CPU_OFFLINE && ++cTries < 512);
455 vbCpuRepDebug("SUPR3ArmQuerySysRegs(%u/%u) -> %Rrc (%u/%u regs - %u retries)\n",
456 idCpu, idxCpu, rc, g_aVariations[iVar].cSysRegVals, cRegAvailable, cTries);
457 if (rc == VERR_CPU_OFFLINE)
458 continue;
459 if (RT_FAILURE(rc))
460 return RTMsgErrorRc(rc, "SUPR3ArmQuerySysRegs failed: %Rrc", rc);
461 if (cRegAvailable > g_aVariations[iVar].cSysRegVals)
462 return RTMsgErrorRc(rc,
463 "SUPR3ArmQuerySysRegs claims there are %u more registers availble.\n"
464 "Increase size of g_aSysRegVals to at least %u entries and retry!",
465 cRegAvailable - g_aVariations[iVar].cSysRegVals, cRegAvailable);
466 /* Sort it. */
467 RTSortShell(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
468 sizeof(g_aVariations[iVar].aSysRegVals[0]), sysRegValSortCmp, NULL);
469
470 /* Sanitize the MP affinity register. */
471 SUPARMSYSREGVAL *pReg = lookupSysReg(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
472 ARMV8_AARCH64_SYSREG_MPIDR_EL1);
473 if (pReg)
474 {
475 pReg->uValue &= ~UINT64_C(0xff00ffffff); /* Zero the Aff3, Aff2, Aff1 & Aff0 fields. */
476 pReg->fFlags = 1;
477 }
478
479 /* Check if it's the same as an existing variation. */
480 int iVarMatch;
481 for (iVarMatch = iVar - 1; iVarMatch >= 0; iVarMatch--)
482 if ( g_aVariations[iVarMatch].cSysRegVals == g_aVariations[iVar].cSysRegVals
483 && memcmp(&g_aVariations[iVarMatch].aSysRegVals,
484 &g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals) == 0)
485 break;
486 if (iVarMatch >= 0)
487 {
488 /* Add to existing */
489 vbCpuRepDebug("CPU %u/%u is same as variant #%u\n", idCpu, idxCpu, iVarMatch);
490 g_aVariations[iVarMatch].cCores += 1;
491 RTCpuSetAddByIndex(&g_aVariations[iVarMatch].bmMembers, idxCpu);
492 }
493 else
494 {
495 vbCpuRepDebug("CPU %u/%u is a new variant #%u\n", idCpu, idxCpu, iVar);
496 g_aVariations[iVar].cCores = 1;
497 RTCpuSetEmpty(&g_aVariations[iVar].bmMembers);
498 RTCpuSetAddByIndex(&g_aVariations[iVar].bmMembers, idxCpu);
499
500 /* Set remaining entries to 0xffff to guard against trouble below when
501 finding common register values. */
502 for (uint32_t i = g_aVariations[iVar].cSysRegVals; i < RT_ELEMENTS(g_aVariations[iVar].aSysRegVals); i++)
503 {
504 g_aVariations[iVar].aSysRegVals[i].idReg = UINT32_MAX;
505 g_aVariations[iVar].aSysRegVals[i].uValue = 0;
506 g_aVariations[iVar].aSysRegVals[i].fFlags = 0;
507 }
508
509 g_cVariations = ++iVar;
510 }
511 g_cCores += 1;
512 }
513
514 return populateSystemRegistersComplete();
515 }
516 RTMsgErrorRc(rc, "Unable to initialize the support library (%Rrc).", rc);
517
518#ifdef RT_OS_DARWIN
519 /*
520 * Create a VM and gather the information from it.
521 *
522 * As it turns out, this isn't much better than nemR3DarwinNativeInitVCpuOnEmt(),
523 * but it's something...
524 */
525 hv_return_t rcHv = hv_vm_create(NULL);
526 if (rcHv == HV_SUCCESS)
527 {
528 /* Create a configuration so we can query . */
529 hv_vcpu_config_t hVCpuCfg = hv_vcpu_config_create();
530 if (hVCpuCfg == NULL)
531 vbCpuRepDebug("Warning! hv_vcpu_config_create failed\n");
532
533 hv_vcpu_t hVCpu = UINT64_MAX / 2;
534 hv_vcpu_exit_t *pExitInfo = NULL;
535 rcHv = hv_vcpu_create(&hVCpu, &pExitInfo, NULL /*hConfig*/);
536 if (rcHv == HV_SUCCESS)
537 {
538 vbCpuRepDebug("Gathering (guest) CPU info via hv_vm_create...\n");
539 unsigned const iVar = 0;
540 g_cCores = g_aVariations[iVar].cCores = RTCpuSetCount(RTMpGetOnlineSet(&g_aVariations[iVar].bmMembers));
541 g_cVariations = 1;
542 unsigned iReg = 0;
543# define ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_uValue) do { \
544 g_aVariations[iVar].aSysRegVals[iReg].fFlags = 0; \
545 g_aVariations[iVar].aSysRegVals[iReg].idReg = ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \
546 g_aVariations[iVar].aSysRegVals[iReg].uValue = a_uValue; \
547 g_aVariations[iVar].cSysRegVals = ++iReg; \
548 } while (0)
549
550# define READ_SYS_REG_UNDEF_U(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) do { \
551 uint64_t uValue = 0; \
552 hv_sys_reg_t const enmSysReg = (hv_sys_reg_t)ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \
553 hv_return_t const rcHvGet = hv_vcpu_get_sys_reg(hVCpu, enmSysReg, &uValue); \
554 if (rcHvGet == HV_SUCCESS) ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, uValue); \
555 else vbCpuRepDebug("Warning! hv_vcpu_get_sys_reg(%u,%u,%u,%u,%u) failed on line %u: %#x (%d)\n", \
556 a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, __LINE__, rcHvGet, rcHvGet); \
557 } while (0)
558
559# define READ_SYS_REG__TODO_U(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
560 uint64_t uValue = 0; \
561 hv_sys_reg_t const enmSysReg = (hv_sys_reg_t)ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \
562 hv_return_t const rcHvGet = hv_vcpu_get_sys_reg(hVCpu, enmSysReg, &uValue); \
563 if (rcHvGet == HV_SUCCESS) ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, uValue); \
564 else vbCpuRepDebug("Warning! hv_vcpu_get_sys_reg(" #a_SysRegName ") failed: %#x (%d)\n", rcHvGet, rcHvGet); \
565 } while (0)
566
567# define READ_SYS_REG__TODO_F(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
568 uint64_t uValue = 0; \
569 hv_return_t const rcHvGet = hv_vcpu_config_get_feature_reg(hVCpuCfg, RT_CONCAT(HV_FEATURE_REG_,a_SysRegName), &uValue); \
570 if (rcHvGet == HV_SUCCESS) ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, uValue); \
571 else vbCpuRepDebug("Warning! hv_vcpu_get_sys_reg(" #a_SysRegName ") failed: %#x (%d)\n", rcHvGet, rcHvGet); \
572 } while (0)
573
574# define READ_SYS_REG_NAMED_U(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
575 AssertCompile( ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
576 == RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName)); \
577 READ_SYS_REG__TODO_U(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName); \
578 } while (0)
579
580# define READ_SYS_REG_NAMED_F(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
581 AssertCompile( ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
582 == RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName)); \
583 READ_SYS_REG__TODO_F(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName); \
584 } while (0)
585
586# define READ_SYS_REG_NAMED_B(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
587 AssertCompile( ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
588 == RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName)); \
589 /* 1. sys_reg */ \
590 uint64_t uValueSys = 0; \
591 hv_sys_reg_t const enmSysReg = (hv_sys_reg_t)ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \
592 hv_return_t const rcHvSys = hv_vcpu_get_sys_reg(hVCpu, enmSysReg, &uValueSys); \
593 if (rcHvSys == HV_SUCCESS) ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, uValueSys); \
594 else vbCpuRepDebug("Warning! hv_vcpu_get_sys_reg(" #a_SysRegName ") failed: %#x (%d)\n", rcHvSys, rcHvSys); \
595 /* 2. feature: */ \
596 uint64_t uValueFeature = 0; \
597 hv_return_t const rcHvFeat = hv_vcpu_config_get_feature_reg(hVCpuCfg, RT_CONCAT(HV_FEATURE_REG_,a_SysRegName), &uValueFeature); \
598 if (rcHvFeat != HV_SUCCESS) vbCpuRepDebug("Warning! hv_vcpu_config_get_feature_reg(" #a_SysRegName ") failed: %#x (%d)\n", rcHvFeat, rcHvFeat); \
599 else if (rcHvSys != HV_SUCCESS) ADD_REG(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, uValueFeature); \
600 else if (uValueFeature != uValueSys) \
601 vbCpuRepDebug("Warning! ARMV8_AARCH64_SYSREG_" #a_SysRegName "=%#RX64 while HV_FEATURE_REG_" #a_SysRegName "=%#RX64, diff: %#RX64\n", \
602 uValueSys, uValueFeature, uValueSys ^ uValueFeature); \
603 } while (0)
604
605# define READ_SYS_REG_NAMED_S(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \
606 AssertCompile( ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
607 == (uint32_t)RT_CONCAT(HV_SYS_REG_,a_SysRegName)); \
608 READ_SYS_REG_NAMED_U(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName); \
609 } while (0)
610
611 READ_SYS_REG_NAMED_S(3, 0, 0, 0, 0, MIDR_EL1);
612 READ_SYS_REG_NAMED_S(3, 0, 0, 0, 5, MPIDR_EL1);
613 READ_SYS_REG_NAMED_U(3, 0, 0, 0, 6, REVIDR_EL1);
614 READ_SYS_REG__TODO_U(3, 1, 0, 0, 0, CCSIDR_EL1);
615 READ_SYS_REG__TODO_F(3, 1, 0, 0, 1, CLIDR_EL1);
616 READ_SYS_REG__TODO_U(3, 1, 0, 0, 7, AIDR_EL1);
617 READ_SYS_REG_NAMED_F(3, 3, 0, 0, 1, CTR_EL0); /** @todo */
618 READ_SYS_REG_NAMED_F(3, 3, 0, 0, 7, DCZID_EL0);
619 READ_SYS_REG_NAMED_U(3, 3,14, 0, 0, CNTFRQ_EL0);
620
621 READ_SYS_REG_NAMED_B(3, 0, 0, 4, 0, ID_AA64PFR0_EL1);
622 READ_SYS_REG_NAMED_B(3, 0, 0, 4, 1, ID_AA64PFR1_EL1);
623 READ_SYS_REG_UNDEF_U(3, 0, 0, 4, 2);
624 READ_SYS_REG_UNDEF_U(3, 0, 0, 4, 3);
625 READ_SYS_REG_NAMED_U(3, 0, 0, 4, 4, ID_AA64ZFR0_EL1); // undefined in older SDKs.
626 READ_SYS_REG_NAMED_U(3, 0, 0, 4, 5, ID_AA64SMFR0_EL1); // undefined in older SDKs.
627 READ_SYS_REG_UNDEF_U(3, 0, 0, 4, 6);
628 READ_SYS_REG_UNDEF_U(3, 0, 0, 4, 7);
629
630 READ_SYS_REG_NAMED_B(3, 0, 0, 5, 0, ID_AA64DFR0_EL1);
631 READ_SYS_REG_NAMED_B(3, 0, 0, 5, 1, ID_AA64DFR1_EL1);
632 READ_SYS_REG_UNDEF_U(3, 0, 0, 5, 2);
633 READ_SYS_REG_UNDEF_U(3, 0, 0, 5, 3);
634 READ_SYS_REG_NAMED_U(3, 0, 0, 5, 4, ID_AA64AFR0_EL1);
635 READ_SYS_REG_NAMED_U(3, 0, 0, 5, 5, ID_AA64AFR1_EL1);
636 READ_SYS_REG_UNDEF_U(3, 0, 0, 5, 6);
637 READ_SYS_REG_UNDEF_U(3, 0, 0, 5, 7);
638
639 READ_SYS_REG_NAMED_B(3, 0, 0, 6, 0, ID_AA64ISAR0_EL1);
640 READ_SYS_REG_NAMED_B(3, 0, 0, 6, 1, ID_AA64ISAR1_EL1);
641 READ_SYS_REG_NAMED_U(3, 0, 0, 6, 2, ID_AA64ISAR2_EL1);
642 READ_SYS_REG__TODO_U(3, 0, 0, 6, 3, ID_AA64ISAR3_EL1);
643 READ_SYS_REG_UNDEF_U(3, 0, 0, 6, 4);
644 READ_SYS_REG_UNDEF_U(3, 0, 0, 6, 5);
645 READ_SYS_REG_UNDEF_U(3, 0, 0, 6, 6);
646 READ_SYS_REG_UNDEF_U(3, 0, 0, 6, 7);
647
648 READ_SYS_REG_NAMED_B(3, 0, 0, 7, 0, ID_AA64MMFR0_EL1);
649 READ_SYS_REG_NAMED_B(3, 0, 0, 7, 1, ID_AA64MMFR1_EL1);
650 READ_SYS_REG_NAMED_B(3, 0, 0, 7, 2, ID_AA64MMFR2_EL1);
651 READ_SYS_REG__TODO_U(3, 0, 0, 7, 3, ID_AA64MMFR3_EL1);
652 READ_SYS_REG__TODO_U(3, 0, 0, 7, 4, ID_AA64MMFR4_EL1);
653 READ_SYS_REG_UNDEF_U(3, 0, 0, 7, 5);
654 READ_SYS_REG_UNDEF_U(3, 0, 0, 7, 6);
655 READ_SYS_REG_UNDEF_U(3, 0, 0, 7, 7);
656
657 READ_SYS_REG__TODO_U(3, 1, 0, 0, 2, CCSIDR2_EL1);
658 READ_SYS_REG_NAMED_U(3, 0, 5, 3, 0, ERRIDR_EL1);
659 READ_SYS_REG__TODO_U(3, 1, 0, 0, 4, GMID_EL1);
660
661 READ_SYS_REG__TODO_U(3, 0, 10, 4, 4, MPAMIDR_EL1);
662 READ_SYS_REG__TODO_U(3, 0, 10, 4, 5, MPAMBWIDR_EL1);
663
664 READ_SYS_REG__TODO_U(3, 0, 9, 10, 7, PMBIDR_EL1);
665 READ_SYS_REG__TODO_U(3, 0, 9, 8, 7, PMSIDR_EL1);
666
667 READ_SYS_REG__TODO_U(3, 0, 9, 11, 7, TRBIDR_EL1);
668
669 /* Sort it. */
670 RTSortShell(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
671 sizeof(g_aVariations[iVar].aSysRegVals[0]), sysRegValSortCmp, NULL);
672
673# undef ADD_REG
674# undef READ_SYS_REG_UNDEF_U
675# undef READ_SYS_REG__TODO_U
676# undef READ_SYS_REG__TODO_F
677# undef READ_SYS_REG_NAMED_U
678# undef READ_SYS_REG_NAMED_F
679# undef READ_SYS_REG_NAMED_B
680# undef READ_SYS_REG_NAMED_S
681 hv_vcpu_destroy(hVCpu);
682 }
683 if (hVCpuCfg)
684 os_release(hVCpuCfg);
685 hv_vm_destroy();
686 if (rcHv == HV_SUCCESS) /* from hv_vcpu_create */
687 {
688 g_fOtherSysRegSource = true;
689 return populateSystemRegistersComplete();
690 }
691 return RTMsgErrorRc(rc, "hv_vcpu_create failed: %#x", rcHv);
692 }
693 return RTMsgErrorRc(rc, "hv_vm_create failed: %#x", rcHv);
694
695#elif defined(RT_OS_LINUX)
696 /** @todo On Linux we can query the registers exposed to ring-3... */
697 return rc;
698
699#else
700 return rc;
701#endif
702}
703
704
705static void printSysRegArray(const char *pszNameC, uint32_t cSysRegVals, SUPARMSYSREGVAL const *paSysRegVals,
706 const char *pszCpuDesc, uint32_t iVariation = UINT32_MAX)
707{
708 if (!cSysRegVals)
709 return;
710
711 vbCpuRepPrintf("\n"
712 "/**\n");
713 if (iVariation == UINT32_MAX)
714 vbCpuRepPrintf(" * Common system register values for %s.\n"
715 " */\n"
716 "static SUPARMSYSREGVAL const g_aCmnSysRegVals_%s[] =\n"
717 "{\n",
718 pszCpuDesc, pszNameC);
719 else
720 {
721 vbCpuRepPrintf(" * System register values for %s, variation #%u.\n"
722 " * %u CPUs shares this variant: ",
723 pszCpuDesc, iVariation,
724 g_aVariations[iVariation].cCores);
725 int iLast = RTCpuSetLastIndex(&g_aVariations[iVariation].bmMembers);
726 for (int i = 0, cPrinted = 0; i <= iLast; i++)
727 if (RTCpuSetIsMemberByIndex(&g_aVariations[iVariation].bmMembers, i))
728 vbCpuRepPrintf(cPrinted++ == 0 ? "%u" : ", %u", i);
729 vbCpuRepPrintf("\n"
730 " */\n"
731 "static SUPARMSYSREGVAL const g_aVar%uSysRegVals_%s[] =\n"
732 "{\n",
733 iVariation, pszNameC);
734 }
735 for (uint32_t i = 0; i < cSysRegVals; i++)
736 {
737 uint32_t const idReg = paSysRegVals[i].idReg;
738 uint32_t const uOp0 = ARMV8_AARCH64_SYSREG_ID_GET_OP0(idReg);
739 uint32_t const uOp1 = ARMV8_AARCH64_SYSREG_ID_GET_OP1(idReg);
740 uint32_t const uCRn = ARMV8_AARCH64_SYSREG_ID_GET_CRN(idReg);
741 uint32_t const uCRm = ARMV8_AARCH64_SYSREG_ID_GET_CRM(idReg);
742 uint32_t const uOp2 = ARMV8_AARCH64_SYSREG_ID_GET_OP2(idReg);
743 const char * const pszNm = sysRegNoToName(idReg);
744
745 vbCpuRepPrintf(" { UINT64_C(%#018RX64), ARMV8_AARCH64_SYSREG_ID_CREATE(%u, %u,%2u,%2u, %u), %#x },%s%s%s\n",
746 paSysRegVals[i].uValue, uOp0, uOp1, uCRn, uCRm, uOp2, paSysRegVals[i].fFlags,
747 pszNm ? " /* " : "", pszNm ? pszNm : "", pszNm ? " */" : "");
748 }
749 vbCpuRepPrintf("};\n"
750 "\n");
751}
752
753
754/**
755 * Populate the system register array and output it.
756 */
757static int produceSysRegArray(const char *pszNameC, const char *pszCpuDesc)
758{
759 printSysRegArray(pszNameC, g_cCmnSysRegVals, g_aCmnSysRegVals, pszCpuDesc);
760 for (uint32_t iVar = 0; iVar < g_cVariations; iVar++)
761 printSysRegArray(pszNameC, g_aVariations[iVar].cSysRegVals, g_aVariations[iVar].aSysRegVals,
762 g_aVariations[iVar].pszFullName, iVar);
763 return VINF_SUCCESS;
764}
765
766
767int produceCpuReport(void)
768{
769 /*
770 * Figure out the processor name via the host OS and command line first...
771 */
772 /** @todo HKLM/Hardware/... */
773 char szDetectedCpuName[256] = {0};
774 int rc = RTMpGetDescription(NIL_RTCPUID, szDetectedCpuName, sizeof(szDetectedCpuName));
775 if (RT_SUCCESS(rc))
776 vbCpuRepDebug("szDetectedCpuName: %s\n", szDetectedCpuName);
777 if (RT_FAILURE(rc) || strcmp(szDetectedCpuName, "Unknown") == 0)
778 szDetectedCpuName[0] = '\0';
779
780 const char *pszCpuName = g_pszCpuNameOverride ? g_pszCpuNameOverride : RTStrStrip(szDetectedCpuName);
781 if (strlen(pszCpuName) >= sizeof(szDetectedCpuName))
782 return RTMsgErrorRc(VERR_FILENAME_TOO_LONG, "CPU name is too long: %zu chars, max %zu: %s",
783 strlen(pszCpuName), sizeof(szDetectedCpuName) - 1, pszCpuName);
784
785 /*
786 * Get the system registers first so we can try identify the CPU.
787 */
788 rc = populateSystemRegisters();
789 if (RT_FAILURE(rc))
790 return rc;
791
792 /*
793 * Identify each of the CPU variations we've detected.
794 */
795 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
796 {
797 /*
798 * Now that we've got the ID register values, figure out the vendor,
799 * microarch, cpu name and description..
800 */
801 uint64_t const uMIdReg = getSysRegVal(ARMV8_AARCH64_SYSREG_MIDR_EL1, iVar);
802 g_aVariations[iVar].uMIdReg = uMIdReg;
803
804 uint8_t const bImplementer = (uint8_t )((uMIdReg >> 24) & 0xff);
805 uint8_t const bVariant = (uint8_t )((uMIdReg >> 20) & 0xf);
806 uint16_t const uPartNum = (uint16_t)((uMIdReg >> 4) & 0xfff);
807 //uint8_t const bRevision = (uint8_t )( uMIdReg & 0x7);
808 uint16_t const uPartNumEx = uPartNum | ((uint16_t)bVariant << 12);
809
810 /** @todo move this to CPUM or IPRT... */
811 PARTNUMINFO const *paPartNums;
812 size_t cPartNums;
813 uint32_t uPartNumSearch = uPartNum;
814 switch (bImplementer)
815 {
816 case 0x41:
817 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_ARM;
818 paPartNums = g_aPartNumDbArm;
819 cPartNums = RT_ELEMENTS(g_aPartNumDbArm);
820 break;
821
822 case 0x42:
823 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_BROADCOM;
824 paPartNums = g_aPartNumDbBroadcom;
825 cPartNums = RT_ELEMENTS(g_aPartNumDbBroadcom);
826 break;
827
828 case 0x51:
829 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_QUALCOMM;
830 paPartNums = g_aPartNumDbQualcomm;
831 cPartNums = RT_ELEMENTS(g_aPartNumDbQualcomm);
832 uPartNumSearch = uPartNumEx; /* include the variant in the search */
833 break;
834
835 case 0x61:
836 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_APPLE;
837 paPartNums = g_aPartNumDbApple;
838 cPartNums = RT_ELEMENTS(g_aPartNumDbApple);
839 break;
840
841 case 0xc0:
842 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_AMPERE;
843 paPartNums = g_aPartNumDbAmpere;
844 cPartNums = RT_ELEMENTS(g_aPartNumDbAmpere);
845 break;
846
847 default:
848 return RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "Unknown ARM implementer: %#x (%s)", bImplementer, pszCpuName);
849 }
850
851 /* Look up the part number in the vendor table: */
852 g_aVariations[iVar].enmCoreType = kCpumCoreType_Invalid;
853 g_aVariations[iVar].enmMicroarch = kCpumMicroarch_Invalid;
854 g_aVariations[iVar].pszName = NULL;
855 g_aVariations[iVar].pszFullName = NULL;
856 for (size_t i = 0; i < cPartNums; i++)
857 if (paPartNums[i].uPartNum == uPartNumSearch)
858 {
859 g_aVariations[iVar].enmCoreType = paPartNums[i].enmCoreType;
860 g_aVariations[iVar].enmMicroarch = paPartNums[i].enmMicroarch;
861 g_aVariations[iVar].pszName = paPartNums[i].pszName;
862 g_aVariations[iVar].pszFullName = paPartNums[i].pszFullName;
863 break;
864 }
865 if (g_aVariations[iVar].enmMicroarch == kCpumMicroarch_Invalid)
866 {
867 rc = RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "%s part number not found: %#x (MIDR_EL1=%#x%s%s)",
868 CPUMCpuVendorName(g_aVariations[iVar].enmVendor), uPartNum, uMIdReg,
869 *pszCpuName ? " " : "", pszCpuName);
870#ifdef RT_OS_DARWIN
871 /* Search by CPU name. */
872 if (pszCpuName && g_fOtherSysRegSource)
873 for (size_t i = 0; i < cPartNums; i++)
874 if ( strcmp(paPartNums[i].pszName, pszCpuName) == 0
875 || strcmp(paPartNums[i].pszFullName, pszCpuName) == 0)
876 {
877 g_aVariations[iVar].enmCoreType = kCpumCoreType_Unknown;
878 g_aVariations[iVar].enmMicroarch = paPartNums[i].enmMicroarch;
879 g_aVariations[iVar].pszName = paPartNums[i].pszName;
880 g_aVariations[iVar].pszFullName = paPartNums[i].pszName;
881 break;
882 }
883 if (g_aVariations[iVar].enmMicroarch == kCpumMicroarch_Invalid)
884#endif
885 return rc;
886 }
887 }
888
889 /*
890 * Sort the variations by core type.
891 */
892 AssertCompile(sizeof(g_aVariations[0]) < _32K); /* Stack allocation in RTSortShell. */
893 if (g_cVariations > 1)
894 RTSortShell(g_aVariations, g_cVariations, sizeof(g_aVariations[0]), variationSortCmp, NULL);
895
896 /*
897 * Take the CPU name and description from the first variation,
898 * unless something better is provided on the command line.
899 */
900 if (!g_pszCpuNameOverride)
901 pszCpuName = g_aVariations[0].pszName;
902 const char * const pszCpuDesc = strlen(szDetectedCpuName) > strlen(pszCpuName) ? RTStrStrip(szDetectedCpuName)
903 : g_cVariations == 1 ? g_aVariations[0].pszFullName : pszCpuName;
904
905 /*
906 * Sanitize the name.
907 */
908 char szName[sizeof(szDetectedCpuName)];
909 size_t offSrc = 0;
910 size_t offDst = 0;
911 for (;;)
912 {
913 char ch = pszCpuName[offSrc++];
914 if (!RT_C_IS_SPACE(ch))
915 szName[offDst++] = ch;
916 else
917 {
918 while (RT_C_IS_SPACE((ch = pszCpuName[offSrc])))
919 offSrc++;
920 if (offDst > 0 && ch != '\0')
921 szName[offDst++] = ' ';
922 }
923 if (!ch)
924 break;
925 }
926 RTStrPurgeEncoding(szName);
927 pszCpuName = szName;
928 vbCpuRepDebug("Name: %s\n", pszCpuName);
929
930 /*
931 * Make it C/C++ acceptable.
932 */
933 static const char s_szNamePrefix[] = "ARM_";
934 char szNameC[sizeof(s_szNamePrefix) + sizeof(szDetectedCpuName)];
935 strcpy(szNameC, s_szNamePrefix);
936 /** @todo Move to common function... */
937 offDst = sizeof(s_szNamePrefix) - 1;
938 offSrc = 0;
939 for (;;)
940 {
941 char ch = pszCpuName[offSrc++];
942 if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
943 ch = '_';
944 if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
945 offDst--;
946 szNameC[offDst++] = ch;
947 if (!ch)
948 break;
949 }
950 while (offDst > 1 && szNameC[offDst - 1] == '_')
951 szNameC[--offDst] = '\0';
952
953 vbCpuRepDebug("NameC: %s\n", szNameC);
954
955 /*
956 * Print a file header, if we're not outputting to stdout (assumption being
957 * that stdout is used while hacking the reporter and too much output is
958 * unwanted).
959 */
960 if (g_pReportOut)
961 vbCpuRepFileHdr(pszCpuName, szNameC);
962
963 /*
964 * Produce the array of system (id) register values.
965 */
966 rc = produceSysRegArray(szNameC, pszCpuDesc);
967 if (RT_FAILURE(rc))
968 return rc;
969
970 /*
971 * Emit the database entry.
972 */
973 vbCpuRepPrintf("\n"
974 "/**\n"
975 " * Database entry for %s.\n"
976 " */\n"
977 "static CPUMDBENTRYARM const g_Entry_%s =\n"
978 "{\n"
979 " {\n"
980 " /*.pszName = */ \"%s\",\n"
981 " /*.pszFullName = */ \"%s\",\n"
982 " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
983 " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
984 " /*.fFlags = */ %s,\n"
985 " },\n"
986 " /*.paSysRegCmnVals = */ NULL_ALONE(g_aCmnSysRegVals_%s),\n"
987 " /*.cSysRegCmnVals = */ ZERO_ALONE(RT_ELEMENTS(g_aCmnSysRegVals_%s)),\n"
988 " /*.cVariants = */ %u,\n"
989 " /*.aVariants = */\n"
990 " {\n"
991 ,
992 pszCpuDesc,
993 szNameC,
994 pszCpuName,
995 pszCpuDesc,
996 vbCpuVendorToString(g_aVariations[0].enmVendor),
997 CPUMMicroarchName(g_aVariations[0].enmMicroarch),
998 !g_fOtherSysRegSource ? "0" : "CPUMDB_F_UNRELIABLE_INFO",
999 szNameC,
1000 szNameC,
1001 g_cVariations);
1002 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
1003 {
1004 vbCpuRepPrintf(" /*.Variants[%u] = */\n"
1005 " {\n"
1006 " /*.pszName = */ \"%s\",\n"
1007 " /*.Midr = */\n"
1008 " {\n"
1009 " /*Midr.s = */\n"
1010 " {\n"
1011 " /*.u4Revision = */ %#03x,\n"
1012 " /*.u12PartNum = */ %#05x,\n"
1013 " /*.u4Arch = */ %#03x,\n"
1014 " /*.u4Variant = */ %#03x,\n"
1015 " /*.u4Implementer = */ %#04x,\n"
1016 " }\n"
1017 " },\n"
1018 " /*.enmCoreType = */ kCpumCoreType_%s,\n"
1019 ,
1020 iVar,
1021 g_aVariations[iVar].pszFullName,
1022 (unsigned)( g_aVariations[iVar].uMIdReg & 0xf),
1023 (unsigned)((g_aVariations[iVar].uMIdReg >> 4) & 0xfff),
1024 (unsigned)((g_aVariations[iVar].uMIdReg >> 16) & 0xf),
1025 (unsigned)((g_aVariations[iVar].uMIdReg >> 20) & 0xf),
1026 (unsigned)((g_aVariations[iVar].uMIdReg >> 24) & 0xff),
1027 vbGetCoreTypeToString(g_aVariations[iVar].enmCoreType));
1028 if (g_aVariations[iVar].cSysRegVals == 0)
1029 vbCpuRepPrintf(" /*.cSysRegVals = */ 0,\n"
1030 " /*.paSysRegVals = */ NULL\n");
1031 else
1032 vbCpuRepPrintf(" /*.cSysRegVals = */ ZERO_ALONE(RT_ELEMENTS(g_aVar%uSysRegVals_%s)),\n"
1033 " /*.paSysRegVals = */ NULL_ALONE(g_aVar%uSysRegVals_%s)\n",
1034 iVar, szNameC, iVar, szNameC);
1035 vbCpuRepPrintf(" },\n");
1036 }
1037 vbCpuRepPrintf(" }\n"
1038 "};\n"
1039 "\n"
1040 "#endif /* !VBOX_CPUDB_%s_h */\n"
1041 "\n",
1042 szNameC);
1043
1044 return VINF_SUCCESS;
1045}
1046
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