VirtualBox

source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport-arm.cpp@ 109029

Last change on this file since 109029 was 109029, checked in by vboxsync, 3 weeks ago

SUP,VBoxCpuReport,VMM/CPUM: Deal with core variations on arm CPUs when generating reports for them. jiraref:VBP-1598
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1/* $Id: VBoxCpuReport-arm.cpp 109029 2025-04-20 02:48:56Z vboxsync $ */
2/** @file
3 * VBoxCpuReport - Produces the basis for a CPU DB entry, x86 specifics.
4 */
5
6/*
7 * Copyright (C) 2013-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#include <iprt/ctype.h>
33#include <iprt/message.h>
34#include <iprt/mem.h>
35#include <iprt/string.h>
36#include <iprt/sort.h>
37
38#include <VBox/err.h>
39#include <VBox/vmm/cpum.h>
40#include <VBox/sup.h>
41
42#include "VBoxCpuReport.h"
43
44
45/*********************************************************************************************************************************
46* Structures and Typedefs *
47*********************************************************************************************************************************/
48typedef struct PARTNUMINFO
49{
50 uint32_t uPartNum;
51 CPUMMICROARCH enmMicroarch;
52 const char *pszName;
53 const char *pszFullName;
54 CPUMCORETYPE enmCoreType;
55} PARTNUMINFO;
56
57
58/*********************************************************************************************************************************
59* Global Variables *
60*********************************************************************************************************************************/
61static struct
62{
63 RTCPUSET bmMembers;
64 uint32_t cCores;
65 uint32_t cSysRegVals;
66 SUPARMSYSREGVAL aSysRegVals[256];
67} g_aVariations[RTCPUSET_MAX_CPUS];
68static uint32_t g_cVariations = 0;
69static uint32_t g_cCores = 0;
70
71static uint32_t g_cCmnSysRegVals = 0;
72static SUPARMSYSREGVAL g_aCmnSysRegVals[256];
73
74
75/** ARM CPU info by part number. */
76static PARTNUMINFO const g_aPartNumDbArm[] =
77{
78 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
79};
80
81/** Broadcom CPU info by part number. */
82static PARTNUMINFO const g_aPartNumDbBroadcom[] =
83{
84 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
85};
86
87/** Qualcomm CPU info by part number. */
88static PARTNUMINFO const g_aPartNumDbQualcomm[] =
89{
90 { 0x0d4b, kCpumMicroarch_Qualcomm_Kyro, "Snapdragon 8cx Gen 3", "Snapdragon 8cx Gen 3 (Kryo Prime)", kCpumCoreType_Efficiency }, /* Guessing which part */ /*MIDR_EL1=0x410FD4B0*/
91 { 0x0d4c, kCpumMicroarch_Qualcomm_Kyro, "Snapdragon 8cx Gen 3", "Snapdragon 8cx Gen 3 (Kryo Gold)", kCpumCoreType_Performance }, /* is for which core... */ /*MIDR_EL1=0x410FD4C0*/
92 { 0x1001, kCpumMicroarch_Qualcomm_Oryon, "Snapdragon X", "Snapdragon X (Oryon var 1)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x511f0011 (perf?)*/
93 { 0x2001, kCpumMicroarch_Qualcomm_Oryon, "Snapdragon X", "Snapdragon X (Oryon var 2)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x512f0011 (eff?)*/
94};
95
96/** Apple CPU info by part number. */
97static PARTNUMINFO const g_aPartNumDbApple[] =
98{
99 { 0x022, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Icestorm)", kCpumCoreType_Efficiency },
100 { 0x023, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Firestorm)", kCpumCoreType_Performance },
101 { 0x024, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Icestorm)", kCpumCoreType_Efficiency },
102 { 0x025, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Firestorm)", kCpumCoreType_Performance },
103 { 0x028, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Icestorm)", kCpumCoreType_Efficiency },
104 { 0x029, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Firestorm)", kCpumCoreType_Performance },
105 { 0x032, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Blizzard)", kCpumCoreType_Efficiency },
106 { 0x033, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Avalanche)", kCpumCoreType_Performance },
107 { 0x034, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Blizzard)", kCpumCoreType_Efficiency },
108 { 0x035, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Avalanche)", kCpumCoreType_Performance },
109 { 0x038, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Blizzard)", kCpumCoreType_Efficiency },
110 { 0x039, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Avalanche)", kCpumCoreType_Performance },
111};
112
113/** Ampere CPU info by part number. */
114static PARTNUMINFO const g_aPartNumDbAmpere[] =
115{
116 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
117};
118
119
120/** Looks up a register entry in an array. */
121static SUPARMSYSREGVAL *lookupSysReg(SUPARMSYSREGVAL *paSysRegVals, uint32_t const cSysRegVals, uint32_t const idReg)
122{
123 for (uint32_t i = 0; i < cSysRegVals; i++)
124 if (paSysRegVals[i].idReg == idReg)
125 return &paSysRegVals[i];
126 return NULL;
127}
128
129
130/** Looks up a register value in g_aSysRegVals. */
131static uint64_t getSysRegVal(uint32_t idReg, uint64_t uNotFoundValue = 0, uint32_t iVar = 0)
132{
133 for (uint32_t i = 0; i < g_cCmnSysRegVals; i++)
134 if (g_aCmnSysRegVals[i].idReg == idReg)
135 return g_aCmnSysRegVals[i].uValue;
136
137 if (iVar < g_cVariations)
138 for (uint32_t i = 0; i < g_aVariations[iVar].cSysRegVals; i++)
139 if (g_aVariations[iVar].aSysRegVals[i].idReg == idReg)
140 return g_aVariations[iVar].aSysRegVals[i].uValue;
141
142 return uNotFoundValue;
143}
144
145
146/**
147 * Translates system register ID to a string, returning NULL if we can't.
148 */
149static const char *sysRegNoToName(uint32_t idReg)
150{
151 switch (idReg)
152 {
153 /* The stuff here is copied from SUPDrv.cpp and trimmed down to the reads: */
154#define READ_SYS_REG_NAMED(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
155 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
156#define READ_SYS_REG__TODO(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
157 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
158#define READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
159 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return NULL
160
161 READ_SYS_REG_NAMED(3, 0, 0, 0, 0, MIDR_EL1);
162 READ_SYS_REG_NAMED(3, 0, 0, 0, 5, MPIDR_EL1);
163 READ_SYS_REG_NAMED(3, 0, 0, 0, 6, REVIDR_EL1);
164 READ_SYS_REG__TODO(3, 1, 0, 0, 0, CCSIDR_EL1);
165 READ_SYS_REG__TODO(3, 1, 0, 0, 1, CLIDR_EL1);
166 READ_SYS_REG__TODO(3, 1, 0, 0, 7, AIDR_EL1);
167 READ_SYS_REG_NAMED(3, 3, 0, 0, 7, DCZID_EL0);
168 READ_SYS_REG_NAMED(3, 3,14, 0, 0, CNTFRQ_EL0);
169
170
171 READ_SYS_REG_NAMED(3, 0, 0, 4, 0, ID_AA64PFR0_EL1);
172 READ_SYS_REG_NAMED(3, 0, 0, 4, 1, ID_AA64PFR1_EL1);
173 READ_SYS_REG_UNDEF(3, 0, 0, 4, 2);
174 READ_SYS_REG_UNDEF(3, 0, 0, 4, 3);
175 READ_SYS_REG_NAMED(3, 0, 0, 4, 4, ID_AA64ZFR0_EL1);
176 READ_SYS_REG_NAMED(3, 0, 0, 4, 5, ID_AA64SMFR0_EL1);
177 READ_SYS_REG_UNDEF(3, 0, 0, 4, 6);
178 READ_SYS_REG_UNDEF(3, 0, 0, 4, 7);
179
180 READ_SYS_REG_NAMED(3, 0, 0, 5, 0, ID_AA64DFR0_EL1);
181 READ_SYS_REG_NAMED(3, 0, 0, 5, 1, ID_AA64DFR1_EL1);
182 READ_SYS_REG_UNDEF(3, 0, 0, 5, 2);
183 READ_SYS_REG_UNDEF(3, 0, 0, 5, 3);
184 READ_SYS_REG_NAMED(3, 0, 0, 5, 4, ID_AA64AFR0_EL1);
185 READ_SYS_REG_NAMED(3, 0, 0, 5, 5, ID_AA64AFR1_EL1);
186 READ_SYS_REG_UNDEF(3, 0, 0, 5, 6);
187 READ_SYS_REG_UNDEF(3, 0, 0, 5, 7);
188
189 READ_SYS_REG_NAMED(3, 0, 0, 6, 0, ID_AA64ISAR0_EL1);
190 READ_SYS_REG_NAMED(3, 0, 0, 6, 1, ID_AA64ISAR1_EL1);
191 READ_SYS_REG_NAMED(3, 0, 0, 6, 2, ID_AA64ISAR2_EL1);
192 READ_SYS_REG__TODO(3, 0, 0, 6, 3, ID_AA64ISAR3_EL1);
193 READ_SYS_REG_UNDEF(3, 0, 0, 6, 4);
194 READ_SYS_REG_UNDEF(3, 0, 0, 6, 5);
195 READ_SYS_REG_UNDEF(3, 0, 0, 6, 6);
196 READ_SYS_REG_UNDEF(3, 0, 0, 6, 7);
197
198 READ_SYS_REG_NAMED(3, 0, 0, 7, 0, ID_AA64MMFR0_EL1);
199 READ_SYS_REG_NAMED(3, 0, 0, 7, 1, ID_AA64MMFR1_EL1);
200 READ_SYS_REG_NAMED(3, 0, 0, 7, 2, ID_AA64MMFR2_EL1);
201 READ_SYS_REG__TODO(3, 0, 0, 7, 3, ID_AA64MMFR3_EL1);
202 READ_SYS_REG__TODO(3, 0, 0, 7, 4, ID_AA64MMFR4_EL1);
203 READ_SYS_REG_UNDEF(3, 0, 0, 7, 5);
204 READ_SYS_REG_UNDEF(3, 0, 0, 7, 6);
205 READ_SYS_REG_UNDEF(3, 0, 0, 7, 7);
206
207 READ_SYS_REG_NAMED(3, 0, 0, 1, 0, ID_PFR0_EL1);
208 READ_SYS_REG_NAMED(3, 0, 0, 1, 1, ID_PFR1_EL1);
209
210 READ_SYS_REG_NAMED(3, 0, 0, 1, 2, ID_DFR0_EL1);
211
212 READ_SYS_REG_NAMED(3, 0, 0, 1, 3, ID_AFR0_EL1);
213
214 READ_SYS_REG_NAMED(3, 0, 0, 1, 4, ID_MMFR0_EL1);
215 READ_SYS_REG_NAMED(3, 0, 0, 1, 5, ID_MMFR1_EL1);
216 READ_SYS_REG_NAMED(3, 0, 0, 1, 6, ID_MMFR2_EL1);
217 READ_SYS_REG_NAMED(3, 0, 0, 1, 7, ID_MMFR3_EL1);
218
219 READ_SYS_REG_NAMED(3, 0, 0, 2, 0, ID_ISAR0_EL1);
220 READ_SYS_REG_NAMED(3, 0, 0, 2, 1, ID_ISAR1_EL1);
221 READ_SYS_REG_NAMED(3, 0, 0, 2, 2, ID_ISAR2_EL1);
222 READ_SYS_REG_NAMED(3, 0, 0, 2, 3, ID_ISAR3_EL1);
223 READ_SYS_REG_NAMED(3, 0, 0, 2, 4, ID_ISAR4_EL1);
224 READ_SYS_REG_NAMED(3, 0, 0, 2, 5, ID_ISAR5_EL1);
225
226 READ_SYS_REG_NAMED(3, 0, 0, 2, 6, ID_MMFR4_EL1);
227
228 READ_SYS_REG_NAMED(3, 0, 0, 2, 7, ID_ISAR6_EL1);
229
230 READ_SYS_REG_NAMED(3, 0, 0, 3, 0, MVFR0_EL1);
231 READ_SYS_REG_NAMED(3, 0, 0, 3, 1, MVFR1_EL1);
232 READ_SYS_REG_NAMED(3, 0, 0, 3, 2, MVFR2_EL1);
233
234 READ_SYS_REG_NAMED(3, 0, 0, 3, 4, ID_PFR2_EL1);
235
236 READ_SYS_REG_NAMED(3, 0, 0, 3, 5, ID_DFR1_EL1);
237
238 READ_SYS_REG_NAMED(3, 0, 0, 3, 6, ID_MMFR5_EL1);
239
240 READ_SYS_REG__TODO(3, 1, 0, 0, 2, CCSIDR2_EL1); /*?*/
241
242 READ_SYS_REG_NAMED(3, 0, 5, 3, 0, ERRIDR_EL1);
243
244 READ_SYS_REG__TODO(3, 1, 0, 0, 4, GMID_EL1);
245
246 READ_SYS_REG__TODO(3, 0, 10, 4, 4, MPAMIDR_EL1);
247 READ_SYS_REG__TODO(3, 0, 10, 4, 5, MPAMBWIDR_EL1);
248
249 READ_SYS_REG__TODO(3, 0, 9, 10, 7, PMBIDR_EL1);
250 READ_SYS_REG__TODO(3, 0, 9, 8, 7, PMSIDR_EL1);
251
252 READ_SYS_REG__TODO(3, 0, 9, 11, 7, TRBIDR_EL1);
253
254 READ_SYS_REG__TODO(2, 1, 0, 8, 7, TRCIDR0); /*?*/
255 READ_SYS_REG__TODO(2, 1, 0, 9, 7, TRCIDR1);
256 READ_SYS_REG__TODO(2, 1, 0,10, 7, TRCIDR2);
257 READ_SYS_REG__TODO(2, 1, 0,11, 7, TRCIDR3);
258 READ_SYS_REG__TODO(2, 1, 0,12, 7, TRCIDR4);
259 READ_SYS_REG__TODO(2, 1, 0,13, 7, TRCIDR5);
260 READ_SYS_REG__TODO(2, 1, 0,14, 7, TRCIDR6);
261 READ_SYS_REG__TODO(2, 1, 0,15, 7, TRCIDR7);
262 READ_SYS_REG__TODO(2, 1, 0, 0, 6, TRCIDR8);
263 READ_SYS_REG__TODO(2, 1, 0, 1, 6, TRCIDR9);
264 READ_SYS_REG__TODO(2, 1, 0, 2, 6, TRCIDR10);
265 READ_SYS_REG__TODO(2, 1, 0, 3, 6, TRCIDR11);
266 READ_SYS_REG__TODO(2, 1, 0, 4, 6, TRCIDR12);
267 READ_SYS_REG__TODO(2, 1, 0, 5, 6, TRCIDR13);
268
269#undef READ_SYS_REG_NAMED
270#undef READ_SYS_REG__TODO
271#undef READ_SYS_REG_UNDEF
272 }
273 return NULL;
274}
275
276
277/** @callback_impl{FNRTSORTCMP} */
278static DECLCALLBACK(int) sysRegValSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
279{
280 RT_NOREF(pvUser);
281 PCSUPARMSYSREGVAL const pElm1 = (PCSUPARMSYSREGVAL)pvElement1;
282 PCSUPARMSYSREGVAL const pElm2 = (PCSUPARMSYSREGVAL)pvElement2;
283 return pElm1->idReg < pElm2->idReg ? -1 : pElm1->idReg > pElm2->idReg ? 1 : 0;
284}
285
286
287/**
288 * Populates g_aSysRegVals and g_cSysRegVals
289 */
290static int populateSystemRegisters(void)
291{
292 /*
293 * First try using the support driver.
294 */
295 int rc = SUPR3Init(NULL);
296 if (RT_SUCCESS(rc))
297 {
298 /*
299 * Get the registers for online each CPU in the system, sorting them.
300 */
301 RTCPUSET OnlineSet;
302 int const idxLast = RTCpuLastIndex(RTMpGetOnlineSet(&OnlineSet));
303 for (int idxCpu = 0, iVar = 0; idxCpu <= idxLast; idxCpu++)
304 if (RTCpuSetIsMemberByIndex(&OnlineSet, idxCpu))
305 {
306 RTCPUID const idCpu = RTMpCpuIdFromSetIndex(idxCpu);
307 uint32_t cRegAvailable = 0;
308 g_aVariations[iVar].cSysRegVals = 0;
309 rc = SUPR3ArmQuerySysRegs(idCpu,
310 SUP_ARM_SYS_REG_F_INC_ZERO_REG_VAL | SUP_ARM_SYS_REG_F_EXTENDED,
311 RT_ELEMENTS(g_aVariations[iVar].aSysRegVals),
312 &g_aVariations[iVar].cSysRegVals,
313 &cRegAvailable,
314 g_aVariations[iVar].aSysRegVals);
315 vbCpuRepDebug("SUPR3ArmQuerySysRegs(%u/%u) -> %Rrc (%u/%u regs)\n",
316 idCpu, idxCpu, rc, g_aVariations[iVar].cSysRegVals, cRegAvailable);
317 if (RT_FAILURE(rc))
318 return RTMsgErrorRc(rc, "SUPR3ArmQuerySysRegs failed: %Rrc", rc);
319 if (cRegAvailable > g_aVariations[iVar].cSysRegVals)
320 return RTMsgErrorRc(rc,
321 "SUPR3ArmQuerySysRegs claims there are %u more registers availble.\n"
322 "Increase size of g_aSysRegVals to at least %u entries and retry!",
323 cRegAvailable - g_aVariations[iVar].cSysRegVals, cRegAvailable);
324 /* Sort it. */
325 RTSortShell(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
326 sizeof(g_aVariations[iVar].aSysRegVals[0]), sysRegValSortCmp, NULL);
327
328 /* Sanitize the MP affinity register. */
329 SUPARMSYSREGVAL *pReg = lookupSysReg(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
330 ARMV8_AARCH64_SYSREG_MPIDR_EL1);
331 if (pReg)
332 {
333 pReg->uValue &= ~UINT64_C(0xff00ffffff); /* Zero the Aff3, Aff2, Aff1 & Aff0 fields. */
334 pReg->fFlags = 1;
335 }
336
337 /* Check if it's the same as an existing variation. */
338 int iVarMatch;
339 for (iVarMatch = iVar - 1; iVarMatch >= 0; iVarMatch--)
340 if ( g_aVariations[iVarMatch].cSysRegVals == g_aVariations[iVar].cSysRegVals
341 && memcmp(&g_aVariations[iVarMatch].aSysRegVals,
342 &g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals) == 0)
343 break;
344 if (iVarMatch >= 0)
345 {
346 /* Add to existing */
347 vbCpuRepDebug("CPU %u/%u is same as variant #%u\n", idCpu, idxCpu, iVarMatch);
348 g_aVariations[iVarMatch].cCores += 1;
349 RTCpuSetAddByIndex(&g_aVariations[iVarMatch].bmMembers, idxCpu);
350 }
351 else
352 {
353 vbCpuRepDebug("CPU %u/%u is a new variant #%u\n", idCpu, idxCpu, iVar);
354 g_aVariations[iVar].cCores = 1;
355 RTCpuSetEmpty(&g_aVariations[iVar].bmMembers);
356 RTCpuSetAddByIndex(&g_aVariations[iVar].bmMembers, idxCpu);
357
358 /* Set remaining entries to 0xffff to guard against trouble below when
359 finding common register values. */
360 for (uint32_t i = g_aVariations[iVar].cSysRegVals; i < RT_ELEMENTS(g_aVariations[iVar].aSysRegVals); i++)
361 {
362 g_aVariations[iVar].aSysRegVals[i].idReg = UINT32_MAX;
363 g_aVariations[iVar].aSysRegVals[i].uValue = 0;
364 g_aVariations[iVar].aSysRegVals[i].fFlags = 0;
365 }
366
367 g_cVariations = ++iVar;
368 }
369 g_cCores += 1;
370 }
371 vbCpuRepDebug("Detected %u variants across %u online CPUs\n", g_cVariations, g_cCores);
372
373 /*
374 * Now, destill similar register values and unique ones.
375 * This isn't too complicated since the arrays have been sorted.
376 */
377 g_cCmnSysRegVals = 0;
378
379 uint32_t cMaxRegs = g_aVariations[0].cSysRegVals;
380 for (unsigned i = 0; i < g_cVariations; i++)
381 cMaxRegs = RT_MAX(cMaxRegs, g_aVariations[i].cSysRegVals);
382
383 struct
384 {
385 unsigned idxSrc;
386 unsigned idxDst;
387 } aState[RTCPUSET_MAX_CPUS] = { {0, 0} };
388
389 for (;;)
390 {
391 /* Find the min & max register value. */
392 uint32_t idRegMax = 0;
393 uint32_t idRegMin = UINT32_MAX;
394 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
395 {
396 unsigned const idxSrc = aState[iVar].idxSrc;
397
398 uint32_t const idReg = idxSrc < g_aVariations[iVar].cSysRegVals
399 ? g_aVariations[iVar].aSysRegVals[idxSrc].idReg : UINT32_MAX;
400 idRegMax = RT_MAX(idRegMax, idReg);
401 idRegMin = RT_MIN(idRegMin, idReg);
402 }
403 if (idRegMin == UINT32_MAX)
404 break;
405
406 /* Advance all arrays till we've reached idRegMax. */
407 unsigned cMatchedMax = 0;
408 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
409 {
410 unsigned idxSrc = aState[iVar].idxSrc;
411 unsigned idxDst = aState[iVar].idxDst;
412 while ( idxSrc < g_aVariations[iVar].cSysRegVals
413 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg < idRegMax)
414 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
415 cMatchedMax += idxSrc < g_aVariations[iVar].cSysRegVals
416 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax;
417 aState[iVar].idxSrc = idxSrc;
418 aState[iVar].idxDst = idxDst;
419 }
420 if (idRegMax == UINT32_MAX)
421 break;
422
423 if (cMatchedMax == g_cVariations)
424 {
425 /* Check if all the values match. */
426 uint64_t const uValue0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].uValue;
427 uint32_t const fFlags0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].fFlags;
428 unsigned cMatches = 1;
429 for (unsigned iVar = 1; iVar < g_cVariations; iVar++)
430 {
431 unsigned const idxSrc = aState[iVar].idxSrc;
432 Assert(idxSrc < g_aVariations[iVar].cSysRegVals);
433 Assert(g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax);
434 cMatches += g_aVariations[iVar].aSysRegVals[idxSrc].uValue == uValue0
435 && g_aVariations[iVar].aSysRegVals[idxSrc].fFlags == fFlags0;
436 }
437 if (cMatches == g_cVariations)
438 {
439 g_aCmnSysRegVals[g_cCmnSysRegVals++] = g_aVariations[0].aSysRegVals[aState[0].idxSrc];
440 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
441 aState[iVar].idxSrc += 1;
442 continue;
443 }
444 vbCpuRepDebug("%#x: missed #2\n", idRegMax);
445 }
446 else
447 vbCpuRepDebug("%#x: missed #1\n", idRegMax);
448
449 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
450 {
451 Assert(aState[iVar].idxSrc < g_aVariations[iVar].cSysRegVals);
452 g_aVariations[iVar].aSysRegVals[aState[iVar].idxDst++]
453 = g_aVariations[iVar].aSysRegVals[aState[iVar].idxSrc++];
454 }
455 }
456 vbCpuRepDebug("Common register values: %u\n", g_cCmnSysRegVals);
457
458 /* Anything left in any of the arrays are considered unique and needs to be moved up. */
459 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
460 {
461 unsigned idxSrc = aState[iVar].idxSrc;
462 unsigned idxDst = aState[iVar].idxDst;
463 Assert(idxDst <= idxSrc);
464 Assert(idxSrc == g_aVariations[iVar].cSysRegVals);
465 while (idxSrc < g_aVariations[iVar].cSysRegVals)
466 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
467 g_aVariations[iVar].cSysRegVals = idxDst;
468 vbCpuRepDebug("Var #%u register values: %u\n", iVar, idxDst);
469 }
470 return rc;
471 }
472 return RTMsgErrorRc(rc, "Unable to initialize the support library (%Rrc).", rc);
473 //vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc).\n", rc);
474 /** @todo On Linux we can query the registers exposed to ring-3... */
475}
476
477
478static void printSysRegArray(const char *pszNameC, uint32_t cSysRegVals, SUPARMSYSREGVAL const *paSysRegVals,
479 const char *pszCpuDesc, uint32_t iVariation = UINT32_MAX)
480{
481 if (!g_cCmnSysRegVals)
482 return;
483
484 vbCpuRepPrintf("\n"
485 "/*\n");
486 if (iVariation == UINT32_MAX)
487 vbCpuRepPrintf(" * Common system register values for %s.\n"
488 " */\n"
489 "static SUPARMSYSREGVAL const g_aCmnSysRegVals_%s[] =\n"
490 "{\n",
491 pszCpuDesc, pszNameC);
492 else
493 {
494 vbCpuRepPrintf(" * System register values for %s, variation #%u.\n"
495 " * %u CPUs shares this variant: ",
496 pszCpuDesc, iVariation,
497 g_aVariations[iVariation].cCores);
498 int iLast = RTCpuLastIndex(&g_aVariations[iVariation].bmMembers);
499 for (int i = 0, cPrinted = 0; i <= iLast; i++)
500 if (RTCpuSetIsMemberByIndex(&g_aVariations[iVariation].bmMembers, i))
501 vbCpuRepPrintf(cPrinted++ == 0 ? "%u" : ", %u", i);
502 vbCpuRepPrintf("\n"
503 " */\n"
504 "static SUPARMSYSREGVAL const g_aVar%uSysRegVals_%s[] =\n"
505 "{\n",
506 iVariation, pszNameC);
507 }
508 for (uint32_t i = 0; i < cSysRegVals; i++)
509 {
510 uint32_t const idReg = paSysRegVals[i].idReg;
511 uint32_t const uOp0 = ARMV8_AARCH64_SYSREG_OP0_GET(idReg);
512 uint32_t const uOp1 = ARMV8_AARCH64_SYSREG_OP1_GET(idReg);
513 uint32_t const uCRn = ARMV8_AARCH64_SYSREG_CRN_GET(idReg);
514 uint32_t const uCRm = ARMV8_AARCH64_SYSREG_CRM_GET(idReg);
515 uint32_t const uOp2 = ARMV8_AARCH64_SYSREG_OP2_GET(idReg);
516 const char * const pszNm = sysRegNoToName(idReg);
517
518 vbCpuRepPrintf(" { UINT64_C(%#018RX64), ARMV8_AARCH64_SYSREG_ID_CREATE(%u, %u,%2u,%2u, %u), %#x },%s%s%s\n",
519 paSysRegVals[i].uValue, uOp0, uOp1, uCRn, uCRm, uOp2, paSysRegVals[i].fFlags,
520 pszNm ? " /* " : "", pszNm, pszNm ? " */" : "");
521 }
522 vbCpuRepPrintf("};\n"
523 "\n");
524}
525
526
527/**
528 * Populate the system register array and output it.
529 */
530static int produceSysRegArray(const char *pszNameC, const char *pszCpuDesc)
531{
532 printSysRegArray(pszNameC, g_cCmnSysRegVals, g_aCmnSysRegVals, pszCpuDesc);
533 for (uint32_t iVar = 0; iVar < g_cVariations; iVar++)
534 printSysRegArray(pszNameC, g_aVariations[iVar].cSysRegVals, g_aVariations[iVar].aSysRegVals, pszCpuDesc, iVar);
535 return VINF_SUCCESS;
536}
537
538
539int produceCpuReport(void)
540{
541 /*
542 * Figure out the processor name via the host OS and command line first...
543 */
544 /** @todo HKLM/Hardware/... */
545 char szDetectedCpuName[256] = {0};
546 int rc = RTMpGetDescription(NIL_RTCPUID, szDetectedCpuName, sizeof(szDetectedCpuName));
547 if (RT_SUCCESS(rc))
548 vbCpuRepDebug("szDetectedCpuName: %s\n", szDetectedCpuName);
549 if (RT_FAILURE(rc) || strcmp(szDetectedCpuName, "Unknown") == 0)
550 szDetectedCpuName[0] = '\0';
551
552 const char *pszCpuName = g_pszCpuNameOverride ? g_pszCpuNameOverride : RTStrStrip(szDetectedCpuName);
553 if (strlen(pszCpuName) >= sizeof(szDetectedCpuName))
554 return RTMsgErrorRc(VERR_FILENAME_TOO_LONG, "CPU name is too long: %zu chars, max %zu: %s",
555 strlen(pszCpuName), sizeof(szDetectedCpuName) - 1, pszCpuName);
556
557 /*
558 * Get the system registers first so we can try identify the CPU.
559 */
560 rc = populateSystemRegisters();
561 if (RT_FAILURE(rc))
562 return rc;
563
564 /** @todo update the remainder of the file to the variation scheme... */
565
566 /*
567 * Now that we've got the ID register values, figure out the vendor,
568 * microarch, cpu name and description..
569 */
570 uint64_t const uMIdReg = getSysRegVal(ARMV8_AARCH64_SYSREG_MIDR_EL1);
571
572 uint8_t const bImplementer = (uint8_t )((uMIdReg >> 24) & 0xff);
573 uint8_t const bVariant = (uint8_t )((uMIdReg >> 20) & 0xf);
574 uint16_t const uPartNum = (uint16_t)((uMIdReg >> 4) & 0xfff);
575 uint8_t const bRevision = (uint8_t )( uMIdReg & 0x7);
576 uint16_t const uPartNumEx = uPartNum | ((uint16_t)bVariant << 12);
577
578 /** @todo move this to CPUM or IPRT... */
579 CPUMCPUVENDOR enmVendor;
580 const char *pszVendor;
581 PARTNUMINFO const *paPartNums;
582 size_t cPartNums;
583 uint32_t uPartNumSearch = uPartNum;
584 switch (bImplementer)
585 {
586 case 0x41:
587 enmVendor = CPUMCPUVENDOR_ARM;
588 pszVendor = "ARM";
589 paPartNums = g_aPartNumDbArm;
590 cPartNums = RT_ELEMENTS(g_aPartNumDbArm);
591 break;
592
593 case 0x42:
594 enmVendor = CPUMCPUVENDOR_BROADCOM;
595 pszVendor = "Broadcom";
596 paPartNums = g_aPartNumDbBroadcom;
597 cPartNums = RT_ELEMENTS(g_aPartNumDbBroadcom);
598 break;
599
600 case 0x51:
601 enmVendor = CPUMCPUVENDOR_QUALCOMM;
602 pszVendor = "Qualcomm";
603 paPartNums = g_aPartNumDbQualcomm;
604 cPartNums = RT_ELEMENTS(g_aPartNumDbQualcomm);
605 uPartNumSearch = uPartNumEx; /* include the variant in the search */
606 break;
607
608 case 0x61:
609 enmVendor = CPUMCPUVENDOR_APPLE;
610 pszVendor = "Apple";
611 paPartNums = g_aPartNumDbApple;
612 cPartNums = RT_ELEMENTS(g_aPartNumDbApple);
613 break;
614
615 case 0xc0:
616 enmVendor = CPUMCPUVENDOR_AMPERE;
617 pszVendor = "Ampere";
618 paPartNums = g_aPartNumDbAmpere;
619 cPartNums = RT_ELEMENTS(g_aPartNumDbAmpere);
620 break;
621
622 default:
623 return RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "Unknown ARM implementer: %#x (%s)", bImplementer, pszCpuName);
624 }
625
626 /* Look up the part number in the vendor table: */
627 const char *pszCpuDesc = NULL;
628 CPUMMICROARCH enmMicroarch = kCpumMicroarch_Invalid;
629 for (size_t i = 0; i < cPartNums; i++)
630 if (paPartNums[i].uPartNum == uPartNumSearch)
631 {
632 enmMicroarch = paPartNums[i].enmMicroarch;
633 pszCpuDesc = paPartNums[i].pszFullName;
634 if (!g_pszCpuNameOverride)
635 pszCpuName = paPartNums[i].pszName;
636 break;
637 }
638 if (enmMicroarch == kCpumMicroarch_Invalid)
639 return RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "%s part number not found: %#x (MIDR_EL1=%#x%s%s)",
640 pszVendor, uPartNum, uMIdReg, *pszCpuName ? " " : "", pszCpuName);
641
642 /*
643 * Sanitize the name.
644 */
645 char szName[sizeof(szDetectedCpuName)];
646 size_t offSrc = 0;
647 size_t offDst = 0;
648 for (;;)
649 {
650 char ch = pszCpuName[offSrc++];
651 if (!RT_C_IS_SPACE(ch))
652 szName[offDst++] = ch;
653 else
654 {
655 while (RT_C_IS_SPACE((ch = pszCpuName[offSrc])))
656 offSrc++;
657 if (offDst > 0 && ch != '\0')
658 szName[offDst++] = ' ';
659 }
660 if (!ch)
661 break;
662 }
663 RTStrPurgeEncoding(szName);
664 pszCpuName = szName;
665 vbCpuRepDebug("Name: %s\n", pszCpuName);
666
667 /*
668 * Make it C/C++ acceptable.
669 */
670 static const char s_szNamePrefix[] = "ARM_";
671 char szNameC[sizeof(s_szNamePrefix) + sizeof(szDetectedCpuName)];
672 strcpy(szNameC, s_szNamePrefix);
673 /** @todo Move to common function... */
674 offDst = sizeof(s_szNamePrefix) - 1;
675 offSrc = 0;
676 for (;;)
677 {
678 char ch = pszCpuName[offSrc++];
679 if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
680 ch = '_';
681 if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
682 offDst--;
683 szNameC[offDst++] = ch;
684 if (!ch)
685 break;
686 }
687 while (offDst > 1 && szNameC[offDst - 1] == '_')
688 szNameC[--offDst] = '\0';
689
690 vbCpuRepDebug("NameC: %s\n", szNameC);
691
692 /*
693 * Print a file header, if we're not outputting to stdout (assumption being
694 * that stdout is used while hacking the reporter and too much output is
695 * unwanted).
696 */
697 if (g_pReportOut)
698 vbCpuRepFileHdr(pszCpuName, szNameC);
699
700 /*
701 * Produce the array of system (id) register values.
702 */
703 rc = produceSysRegArray(szNameC, pszCpuDesc);
704 if (RT_FAILURE(rc))
705 return rc;
706
707 /*
708 * Emit the database entry.
709 */
710 vbCpuRepPrintf("\n"
711 "/**\n"
712 " * Database entry for %s.\n"
713 " */\n"
714 "static CPUMDBENTRYARM const g_Entry_%s = \n"
715 "{\n"
716 " {\n"
717 " /*.pszName = */ \"%s\",\n"
718 " /*.pszFullName = */ \"%s\",\n"
719 " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
720 " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
721 " /*.fFlags = */ 0,\n"
722 " },\n"
723 " /*.bImplementer = */ %#04x,\n"
724 " /*.bRevision = */ %#04x,\n"
725 " /*.uPartNum = */ %#04x,\n"
726 " /*.cSysRegVals = */ ZERO_ALONE(RT_ELEMENTS(g_aSysRegVals_%s)),\n"
727 " /*.paSysRegVals = */ NULL_ALONE(g_aSysRegVals_%s),\n"
728 "};\n"
729 "\n"
730 "#endif /* !VBOX_CPUDB_%s_h */\n"
731 "\n",
732 pszCpuDesc,
733 szNameC,
734 pszCpuName,
735 pszCpuDesc,
736 CPUMCpuVendorName(enmVendor),
737 CPUMMicroarchName(enmMicroarch),
738 bImplementer,
739 bRevision,
740 uPartNum,
741 szNameC,
742 szNameC,
743 szNameC);
744
745 return VINF_SUCCESS;
746}
747
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