VirtualBox

source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport-arm.cpp@ 109151

Last change on this file since 109151 was 109139, checked in by vboxsync, 10 days ago

VBoxCpuReport,RTSSortShell: M3 Max adjustments; shutting up assertion. jiraref:VBP-1653
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1/* $Id: VBoxCpuReport-arm.cpp 109139 2025-05-02 20:25:17Z vboxsync $ */
2/** @file
3 * VBoxCpuReport - Produces the basis for a CPU DB entry, x86 specifics.
4 */
5
6/*
7 * Copyright (C) 2013-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#include <iprt/ctype.h>
33#include <iprt/message.h>
34#include <iprt/mem.h>
35#include <iprt/string.h>
36#include <iprt/sort.h>
37
38#include <VBox/err.h>
39#include <VBox/vmm/cpum.h>
40#include <VBox/sup.h>
41
42#include "VBoxCpuReport.h"
43
44
45/*********************************************************************************************************************************
46* Structures and Typedefs *
47*********************************************************************************************************************************/
48typedef struct PARTNUMINFO
49{
50 uint32_t uPartNum;
51 CPUMMICROARCH enmMicroarch;
52 const char *pszName;
53 const char *pszFullName;
54 CPUMCORETYPE enmCoreType;
55} PARTNUMINFO;
56
57
58/*********************************************************************************************************************************
59* Global Variables *
60*********************************************************************************************************************************/
61static struct CPUCOREVARIATION
62{
63 /** @name Set by populateSystemRegisters().
64 * @{ */
65 RTCPUSET bmMembers;
66 uint32_t cCores;
67 uint32_t cSysRegVals;
68 SUPARMSYSREGVAL aSysRegVals[256];
69 /** @} */
70
71 /** @name Set later by produceCpuReport().
72 * @{ */
73 uint64_t uMIdReg;
74 CPUMCPUVENDOR enmVendor;
75 CPUMCORETYPE enmCoreType;
76 CPUMMICROARCH enmMicroarch;
77 const char *pszName;
78 const char *pszFullName;
79 /** @} */
80} g_aVariations[RTCPUSET_MAX_CPUS];
81static uint32_t g_cVariations = 0;
82static uint32_t g_cCores = 0;
83
84static uint32_t g_cCmnSysRegVals = 0;
85static SUPARMSYSREGVAL g_aCmnSysRegVals[256];
86
87
88/** ARM CPU info by part number. */
89static PARTNUMINFO const g_aPartNumDbArm[] =
90{
91 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
92};
93
94/** Broadcom CPU info by part number. */
95static PARTNUMINFO const g_aPartNumDbBroadcom[] =
96{
97 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
98};
99
100/** Qualcomm CPU info by part number. */
101static PARTNUMINFO const g_aPartNumDbQualcomm[] =
102{
103 { 0x0d4b, kCpumMicroarch_Qualcomm_Kyro, "Qualcomm Snapdragon 8cx Gen 3", "Qualcomm Snapdragon 8cx Gen 3 (Kryo Prime)", kCpumCoreType_Efficiency }, /* Guessing which part */ /*MIDR_EL1=0x410FD4B0*/
104 { 0x0d4c, kCpumMicroarch_Qualcomm_Kyro, "Qualcomm Snapdragon 8cx Gen 3", "Qualcomm Snapdragon 8cx Gen 3 (Kryo Gold)", kCpumCoreType_Performance }, /* is for which core... */ /*MIDR_EL1=0x410FD4C0*/
105 { 0x1001, kCpumMicroarch_Qualcomm_Oryon, "Qualcomm Snapdragon X", "Qualcomm Snapdragon X (Oryon var 1)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x511f0011 (perf?)*/
106 { 0x2001, kCpumMicroarch_Qualcomm_Oryon, "Qualcomm Snapdragon X", "Qualcomm Snapdragon X (Oryon var 2)", kCpumCoreType_Unknown }, /*MIDR_EL1=0x512f0011 (eff?)*/
107};
108
109/** Apple CPU info by part number. */
110static PARTNUMINFO const g_aPartNumDbApple[] =
111{
112 { 0x022, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Icestorm)", kCpumCoreType_Efficiency },
113 { 0x023, kCpumMicroarch_Apple_M1, "Apple M1", "Apple M1 (Firestorm)", kCpumCoreType_Performance },
114 { 0x024, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Icestorm)", kCpumCoreType_Efficiency },
115 { 0x025, kCpumMicroarch_Apple_M1, "Apple M1 Pro", "Apple M1 Pro (Firestorm)", kCpumCoreType_Performance },
116 { 0x028, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Icestorm)", kCpumCoreType_Efficiency },
117 { 0x029, kCpumMicroarch_Apple_M1, "Apple M1 Max", "Apple M1 Max (Firestorm)", kCpumCoreType_Performance },
118 /** @todo some sources lists 0x30/31 as plain m2... */
119 { 0x032, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Blizzard)", kCpumCoreType_Efficiency },
120 { 0x033, kCpumMicroarch_Apple_M2, "Apple M2", "Apple M2 (Avalanche)", kCpumCoreType_Performance },
121 { 0x034, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Blizzard)", kCpumCoreType_Efficiency },
122 { 0x035, kCpumMicroarch_Apple_M2, "Apple M2 Pro", "Apple M2 Pro (Avalanche)", kCpumCoreType_Performance },
123 { 0x038, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Blizzard)", kCpumCoreType_Efficiency },
124 { 0x039, kCpumMicroarch_Apple_M2, "Apple M2 Max", "Apple M2 Max (Avalanche)", kCpumCoreType_Performance },
125 { 0x048, kCpumMicroarch_Apple_M3, "Apple M3 Max", "Apple M3 Max (Sawtooth)", kCpumCoreType_Efficiency }, /** @todo code names */
126 { 0x049, kCpumMicroarch_Apple_M3, "Apple M3 Max", "Apple M3 Max (Everest)", kCpumCoreType_Performance }, /** @todo code names */
127};
128
129/** Ampere CPU info by part number. */
130static PARTNUMINFO const g_aPartNumDbAmpere[] =
131{
132 { 0xfff, kCpumMicroarch_Unknown, "TODO", "TODO" },
133};
134
135
136/** @callback_impl{FNRTSORTCMP} */
137static DECLCALLBACK(int) variationSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
138{
139 RT_NOREF(pvUser);
140 struct CPUCOREVARIATION const * const pElm1 = (struct CPUCOREVARIATION const *)pvElement1;
141 struct CPUCOREVARIATION const * const pElm2 = (struct CPUCOREVARIATION const *)pvElement2;
142
143 /* Sort by core type, putting the efficiency cores before performance and performance before unknown ones. */
144 AssertCompile(kCpumCoreType_Efficiency < kCpumCoreType_Performance && kCpumCoreType_Performance < kCpumCoreType_Unknown);
145 return (int)pElm1->enmCoreType < (int)pElm2->enmCoreType ? -1
146 : (int)pElm1->enmCoreType > (int)pElm2->enmCoreType ? 1
147 : 0;
148}
149
150
151/** Looks up a register entry in an array. */
152static SUPARMSYSREGVAL *lookupSysReg(SUPARMSYSREGVAL *paSysRegVals, uint32_t const cSysRegVals, uint32_t const idReg)
153{
154 for (uint32_t i = 0; i < cSysRegVals; i++)
155 if (paSysRegVals[i].idReg == idReg)
156 return &paSysRegVals[i];
157 return NULL;
158}
159
160
161/** Looks up a register value in g_aSysRegVals. */
162static uint64_t getSysRegVal(uint32_t idReg, uint32_t iVar, uint64_t uNotFoundValue = 0)
163{
164 SUPARMSYSREGVAL const *pVal = lookupSysReg(g_aCmnSysRegVals, g_cCmnSysRegVals, idReg);
165 if (!pVal && iVar < g_cVariations)
166 pVal = lookupSysReg(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals, idReg);
167 return pVal ? pVal->uValue : uNotFoundValue;
168}
169
170
171/**
172 * Translates system register ID to a string, returning NULL if we can't.
173 */
174static const char *sysRegNoToName(uint32_t idReg)
175{
176 switch (idReg)
177 {
178 /* The stuff here is copied from SUPDrv.cpp and trimmed down to the reads: */
179#define READ_SYS_REG_NAMED(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
180 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
181#define READ_SYS_REG__TODO(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) \
182 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return #a_SysRegName
183#define READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
184 case ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2): return NULL
185
186 READ_SYS_REG_NAMED(3, 0, 0, 0, 0, MIDR_EL1);
187 READ_SYS_REG_NAMED(3, 0, 0, 0, 5, MPIDR_EL1);
188 READ_SYS_REG_NAMED(3, 0, 0, 0, 6, REVIDR_EL1);
189 READ_SYS_REG__TODO(3, 1, 0, 0, 0, CCSIDR_EL1);
190 READ_SYS_REG__TODO(3, 1, 0, 0, 1, CLIDR_EL1);
191 READ_SYS_REG__TODO(3, 1, 0, 0, 7, AIDR_EL1);
192 READ_SYS_REG_NAMED(3, 3, 0, 0, 7, DCZID_EL0);
193 READ_SYS_REG_NAMED(3, 3,14, 0, 0, CNTFRQ_EL0);
194
195
196 READ_SYS_REG_NAMED(3, 0, 0, 4, 0, ID_AA64PFR0_EL1);
197 READ_SYS_REG_NAMED(3, 0, 0, 4, 1, ID_AA64PFR1_EL1);
198 READ_SYS_REG_UNDEF(3, 0, 0, 4, 2);
199 READ_SYS_REG_UNDEF(3, 0, 0, 4, 3);
200 READ_SYS_REG_NAMED(3, 0, 0, 4, 4, ID_AA64ZFR0_EL1);
201 READ_SYS_REG_NAMED(3, 0, 0, 4, 5, ID_AA64SMFR0_EL1);
202 READ_SYS_REG_UNDEF(3, 0, 0, 4, 6);
203 READ_SYS_REG_UNDEF(3, 0, 0, 4, 7);
204
205 READ_SYS_REG_NAMED(3, 0, 0, 5, 0, ID_AA64DFR0_EL1);
206 READ_SYS_REG_NAMED(3, 0, 0, 5, 1, ID_AA64DFR1_EL1);
207 READ_SYS_REG_UNDEF(3, 0, 0, 5, 2);
208 READ_SYS_REG_UNDEF(3, 0, 0, 5, 3);
209 READ_SYS_REG_NAMED(3, 0, 0, 5, 4, ID_AA64AFR0_EL1);
210 READ_SYS_REG_NAMED(3, 0, 0, 5, 5, ID_AA64AFR1_EL1);
211 READ_SYS_REG_UNDEF(3, 0, 0, 5, 6);
212 READ_SYS_REG_UNDEF(3, 0, 0, 5, 7);
213
214 READ_SYS_REG_NAMED(3, 0, 0, 6, 0, ID_AA64ISAR0_EL1);
215 READ_SYS_REG_NAMED(3, 0, 0, 6, 1, ID_AA64ISAR1_EL1);
216 READ_SYS_REG_NAMED(3, 0, 0, 6, 2, ID_AA64ISAR2_EL1);
217 READ_SYS_REG__TODO(3, 0, 0, 6, 3, ID_AA64ISAR3_EL1);
218 READ_SYS_REG_UNDEF(3, 0, 0, 6, 4);
219 READ_SYS_REG_UNDEF(3, 0, 0, 6, 5);
220 READ_SYS_REG_UNDEF(3, 0, 0, 6, 6);
221 READ_SYS_REG_UNDEF(3, 0, 0, 6, 7);
222
223 READ_SYS_REG_NAMED(3, 0, 0, 7, 0, ID_AA64MMFR0_EL1);
224 READ_SYS_REG_NAMED(3, 0, 0, 7, 1, ID_AA64MMFR1_EL1);
225 READ_SYS_REG_NAMED(3, 0, 0, 7, 2, ID_AA64MMFR2_EL1);
226 READ_SYS_REG__TODO(3, 0, 0, 7, 3, ID_AA64MMFR3_EL1);
227 READ_SYS_REG__TODO(3, 0, 0, 7, 4, ID_AA64MMFR4_EL1);
228 READ_SYS_REG_UNDEF(3, 0, 0, 7, 5);
229 READ_SYS_REG_UNDEF(3, 0, 0, 7, 6);
230 READ_SYS_REG_UNDEF(3, 0, 0, 7, 7);
231
232 READ_SYS_REG_NAMED(3, 0, 0, 1, 0, ID_PFR0_EL1);
233 READ_SYS_REG_NAMED(3, 0, 0, 1, 1, ID_PFR1_EL1);
234
235 READ_SYS_REG_NAMED(3, 0, 0, 1, 2, ID_DFR0_EL1);
236
237 READ_SYS_REG_NAMED(3, 0, 0, 1, 3, ID_AFR0_EL1);
238
239 READ_SYS_REG_NAMED(3, 0, 0, 1, 4, ID_MMFR0_EL1);
240 READ_SYS_REG_NAMED(3, 0, 0, 1, 5, ID_MMFR1_EL1);
241 READ_SYS_REG_NAMED(3, 0, 0, 1, 6, ID_MMFR2_EL1);
242 READ_SYS_REG_NAMED(3, 0, 0, 1, 7, ID_MMFR3_EL1);
243
244 READ_SYS_REG_NAMED(3, 0, 0, 2, 0, ID_ISAR0_EL1);
245 READ_SYS_REG_NAMED(3, 0, 0, 2, 1, ID_ISAR1_EL1);
246 READ_SYS_REG_NAMED(3, 0, 0, 2, 2, ID_ISAR2_EL1);
247 READ_SYS_REG_NAMED(3, 0, 0, 2, 3, ID_ISAR3_EL1);
248 READ_SYS_REG_NAMED(3, 0, 0, 2, 4, ID_ISAR4_EL1);
249 READ_SYS_REG_NAMED(3, 0, 0, 2, 5, ID_ISAR5_EL1);
250
251 READ_SYS_REG_NAMED(3, 0, 0, 2, 6, ID_MMFR4_EL1);
252
253 READ_SYS_REG_NAMED(3, 0, 0, 2, 7, ID_ISAR6_EL1);
254
255 READ_SYS_REG_NAMED(3, 0, 0, 3, 0, MVFR0_EL1);
256 READ_SYS_REG_NAMED(3, 0, 0, 3, 1, MVFR1_EL1);
257 READ_SYS_REG_NAMED(3, 0, 0, 3, 2, MVFR2_EL1);
258
259 READ_SYS_REG_NAMED(3, 0, 0, 3, 4, ID_PFR2_EL1);
260
261 READ_SYS_REG_NAMED(3, 0, 0, 3, 5, ID_DFR1_EL1);
262
263 READ_SYS_REG_NAMED(3, 0, 0, 3, 6, ID_MMFR5_EL1);
264
265 READ_SYS_REG__TODO(3, 1, 0, 0, 2, CCSIDR2_EL1); /*?*/
266
267 READ_SYS_REG_NAMED(3, 0, 5, 3, 0, ERRIDR_EL1);
268
269 READ_SYS_REG__TODO(3, 1, 0, 0, 4, GMID_EL1);
270
271 READ_SYS_REG__TODO(3, 0, 10, 4, 4, MPAMIDR_EL1);
272 READ_SYS_REG__TODO(3, 0, 10, 4, 5, MPAMBWIDR_EL1);
273
274 READ_SYS_REG__TODO(3, 0, 9, 10, 7, PMBIDR_EL1);
275 READ_SYS_REG__TODO(3, 0, 9, 8, 7, PMSIDR_EL1);
276
277 READ_SYS_REG__TODO(3, 0, 9, 11, 7, TRBIDR_EL1);
278
279 READ_SYS_REG__TODO(2, 1, 0, 8, 7, TRCIDR0); /*?*/
280 READ_SYS_REG__TODO(2, 1, 0, 9, 7, TRCIDR1);
281 READ_SYS_REG__TODO(2, 1, 0,10, 7, TRCIDR2);
282 READ_SYS_REG__TODO(2, 1, 0,11, 7, TRCIDR3);
283 READ_SYS_REG__TODO(2, 1, 0,12, 7, TRCIDR4);
284 READ_SYS_REG__TODO(2, 1, 0,13, 7, TRCIDR5);
285 READ_SYS_REG__TODO(2, 1, 0,14, 7, TRCIDR6);
286 READ_SYS_REG__TODO(2, 1, 0,15, 7, TRCIDR7);
287 READ_SYS_REG__TODO(2, 1, 0, 0, 6, TRCIDR8);
288 READ_SYS_REG__TODO(2, 1, 0, 1, 6, TRCIDR9);
289 READ_SYS_REG__TODO(2, 1, 0, 2, 6, TRCIDR10);
290 READ_SYS_REG__TODO(2, 1, 0, 3, 6, TRCIDR11);
291 READ_SYS_REG__TODO(2, 1, 0, 4, 6, TRCIDR12);
292 READ_SYS_REG__TODO(2, 1, 0, 5, 6, TRCIDR13);
293
294#undef READ_SYS_REG_NAMED
295#undef READ_SYS_REG__TODO
296#undef READ_SYS_REG_UNDEF
297 }
298 return NULL;
299}
300
301
302/** @callback_impl{FNRTSORTCMP} */
303static DECLCALLBACK(int) sysRegValSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
304{
305 RT_NOREF(pvUser);
306 PCSUPARMSYSREGVAL const pElm1 = (PCSUPARMSYSREGVAL)pvElement1;
307 PCSUPARMSYSREGVAL const pElm2 = (PCSUPARMSYSREGVAL)pvElement2;
308 return pElm1->idReg < pElm2->idReg ? -1 : pElm1->idReg > pElm2->idReg ? 1 : 0;
309}
310
311
312/**
313 * Populates g_aSysRegVals and g_cSysRegVals
314 */
315static int populateSystemRegisters(void)
316{
317 /*
318 * First try using the support driver.
319 */
320 int rc = SUPR3Init(NULL);
321 if (RT_SUCCESS(rc))
322 {
323 /*
324 * Get the registers for online each CPU in the system, sorting them.
325 */
326 for (int idxCpu = 0, iVar = 0; idxCpu < RTCPUSET_MAX_CPUS; idxCpu++)
327 if (RTMpIsCpuOnline(idxCpu))
328 {
329 RTCPUID const idCpu = RTMpCpuIdFromSetIndex(idxCpu);
330 uint32_t cTries = 0; /* Kludge for M3 Max / 14.7.5. Takes anywhere from 44 to at least 144 tries. */
331 uint32_t cRegAvailable;
332 do
333 {
334 cRegAvailable = 0;
335 g_aVariations[iVar].cSysRegVals = 0;
336 rc = SUPR3ArmQuerySysRegs(idCpu,
337 SUP_ARM_SYS_REG_F_INC_ZERO_REG_VAL | SUP_ARM_SYS_REG_F_EXTENDED,
338 RT_ELEMENTS(g_aVariations[iVar].aSysRegVals),
339 &g_aVariations[iVar].cSysRegVals,
340 &cRegAvailable,
341 g_aVariations[iVar].aSysRegVals);
342 } while (rc == VERR_CPU_OFFLINE && ++cTries < 512);
343 vbCpuRepDebug("SUPR3ArmQuerySysRegs(%u/%u) -> %Rrc (%u/%u regs - %u retries)\n",
344 idCpu, idxCpu, rc, g_aVariations[iVar].cSysRegVals, cRegAvailable, cTries);
345 if (rc == VERR_CPU_OFFLINE)
346 continue;
347 if (RT_FAILURE(rc))
348 return RTMsgErrorRc(rc, "SUPR3ArmQuerySysRegs failed: %Rrc", rc);
349 if (cRegAvailable > g_aVariations[iVar].cSysRegVals)
350 return RTMsgErrorRc(rc,
351 "SUPR3ArmQuerySysRegs claims there are %u more registers availble.\n"
352 "Increase size of g_aSysRegVals to at least %u entries and retry!",
353 cRegAvailable - g_aVariations[iVar].cSysRegVals, cRegAvailable);
354 /* Sort it. */
355 RTSortShell(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
356 sizeof(g_aVariations[iVar].aSysRegVals[0]), sysRegValSortCmp, NULL);
357
358 /* Sanitize the MP affinity register. */
359 SUPARMSYSREGVAL *pReg = lookupSysReg(g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals,
360 ARMV8_AARCH64_SYSREG_MPIDR_EL1);
361 if (pReg)
362 {
363 pReg->uValue &= ~UINT64_C(0xff00ffffff); /* Zero the Aff3, Aff2, Aff1 & Aff0 fields. */
364 pReg->fFlags = 1;
365 }
366
367 /* Check if it's the same as an existing variation. */
368 int iVarMatch;
369 for (iVarMatch = iVar - 1; iVarMatch >= 0; iVarMatch--)
370 if ( g_aVariations[iVarMatch].cSysRegVals == g_aVariations[iVar].cSysRegVals
371 && memcmp(&g_aVariations[iVarMatch].aSysRegVals,
372 &g_aVariations[iVar].aSysRegVals, g_aVariations[iVar].cSysRegVals) == 0)
373 break;
374 if (iVarMatch >= 0)
375 {
376 /* Add to existing */
377 vbCpuRepDebug("CPU %u/%u is same as variant #%u\n", idCpu, idxCpu, iVarMatch);
378 g_aVariations[iVarMatch].cCores += 1;
379 RTCpuSetAddByIndex(&g_aVariations[iVarMatch].bmMembers, idxCpu);
380 }
381 else
382 {
383 vbCpuRepDebug("CPU %u/%u is a new variant #%u\n", idCpu, idxCpu, iVar);
384 g_aVariations[iVar].cCores = 1;
385 RTCpuSetEmpty(&g_aVariations[iVar].bmMembers);
386 RTCpuSetAddByIndex(&g_aVariations[iVar].bmMembers, idxCpu);
387
388 /* Set remaining entries to 0xffff to guard against trouble below when
389 finding common register values. */
390 for (uint32_t i = g_aVariations[iVar].cSysRegVals; i < RT_ELEMENTS(g_aVariations[iVar].aSysRegVals); i++)
391 {
392 g_aVariations[iVar].aSysRegVals[i].idReg = UINT32_MAX;
393 g_aVariations[iVar].aSysRegVals[i].uValue = 0;
394 g_aVariations[iVar].aSysRegVals[i].fFlags = 0;
395 }
396
397 g_cVariations = ++iVar;
398 }
399 g_cCores += 1;
400 }
401
402 vbCpuRepDebug("Detected %u variants across %u online CPUs\n", g_cVariations, g_cCores);
403
404 /*
405 * Now, destill similar register values and unique ones.
406 * This isn't too complicated since the arrays have been sorted.
407 */
408 g_cCmnSysRegVals = 0;
409
410 uint32_t cMaxRegs = g_aVariations[0].cSysRegVals;
411 for (unsigned i = 0; i < g_cVariations; i++)
412 cMaxRegs = RT_MAX(cMaxRegs, g_aVariations[i].cSysRegVals);
413
414 struct
415 {
416 unsigned idxSrc;
417 unsigned idxDst;
418 } aState[RTCPUSET_MAX_CPUS] = { {0, 0} };
419
420 for (;;)
421 {
422 /* Find the min & max register value. */
423 uint32_t idRegMax = 0;
424 uint32_t idRegMin = UINT32_MAX;
425 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
426 {
427 unsigned const idxSrc = aState[iVar].idxSrc;
428
429 uint32_t const idReg = idxSrc < g_aVariations[iVar].cSysRegVals
430 ? g_aVariations[iVar].aSysRegVals[idxSrc].idReg : UINT32_MAX;
431 idRegMax = RT_MAX(idRegMax, idReg);
432 idRegMin = RT_MIN(idRegMin, idReg);
433 }
434 if (idRegMin == UINT32_MAX)
435 break;
436
437 /* Advance all arrays till we've reached idRegMax. */
438 unsigned cMatchedMax = 0;
439 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
440 {
441 unsigned idxSrc = aState[iVar].idxSrc;
442 unsigned idxDst = aState[iVar].idxDst;
443 while ( idxSrc < g_aVariations[iVar].cSysRegVals
444 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg < idRegMax)
445 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
446 cMatchedMax += idxSrc < g_aVariations[iVar].cSysRegVals
447 && g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax;
448 aState[iVar].idxSrc = idxSrc;
449 aState[iVar].idxDst = idxDst;
450 }
451 if (idRegMax == UINT32_MAX)
452 break;
453
454 if (cMatchedMax == g_cVariations)
455 {
456 /* Check if all the values match. */
457 uint64_t const uValue0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].uValue;
458 uint32_t const fFlags0 = g_aVariations[0].aSysRegVals[aState[0].idxSrc].fFlags;
459 unsigned cMatches = 1;
460 for (unsigned iVar = 1; iVar < g_cVariations; iVar++)
461 {
462 unsigned const idxSrc = aState[iVar].idxSrc;
463 Assert(idxSrc < g_aVariations[iVar].cSysRegVals);
464 Assert(g_aVariations[iVar].aSysRegVals[idxSrc].idReg == idRegMax);
465 cMatches += g_aVariations[iVar].aSysRegVals[idxSrc].uValue == uValue0
466 && g_aVariations[iVar].aSysRegVals[idxSrc].fFlags == fFlags0;
467 }
468 if (cMatches == g_cVariations)
469 {
470 g_aCmnSysRegVals[g_cCmnSysRegVals++] = g_aVariations[0].aSysRegVals[aState[0].idxSrc];
471 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
472 aState[iVar].idxSrc += 1;
473 continue;
474 }
475 vbCpuRepDebug("%#x: missed #2\n", idRegMax);
476 }
477 else
478 vbCpuRepDebug("%#x: missed #1\n", idRegMax);
479
480 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
481 {
482 Assert(aState[iVar].idxSrc < g_aVariations[iVar].cSysRegVals);
483 g_aVariations[iVar].aSysRegVals[aState[iVar].idxDst++]
484 = g_aVariations[iVar].aSysRegVals[aState[iVar].idxSrc++];
485 }
486 }
487 vbCpuRepDebug("Common register values: %u\n", g_cCmnSysRegVals);
488
489 /* Anything left in any of the arrays are considered unique and needs to be moved up. */
490 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
491 {
492 unsigned idxSrc = aState[iVar].idxSrc;
493 unsigned idxDst = aState[iVar].idxDst;
494 Assert(idxDst <= idxSrc);
495 Assert(idxSrc == g_aVariations[iVar].cSysRegVals);
496 while (idxSrc < g_aVariations[iVar].cSysRegVals)
497 g_aVariations[iVar].aSysRegVals[idxDst++] = g_aVariations[iVar].aSysRegVals[idxSrc++];
498 g_aVariations[iVar].cSysRegVals = idxDst;
499 vbCpuRepDebug("Var #%u register values: %u\n", iVar, idxDst);
500 }
501 return rc;
502 }
503 return RTMsgErrorRc(rc, "Unable to initialize the support library (%Rrc).", rc);
504 //vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc).\n", rc);
505 /** @todo On Linux we can query the registers exposed to ring-3... */
506}
507
508
509static void printSysRegArray(const char *pszNameC, uint32_t cSysRegVals, SUPARMSYSREGVAL const *paSysRegVals,
510 const char *pszCpuDesc, uint32_t iVariation = UINT32_MAX)
511{
512 if (!g_cCmnSysRegVals)
513 return;
514
515 vbCpuRepPrintf("\n"
516 "/**\n");
517 if (iVariation == UINT32_MAX)
518 vbCpuRepPrintf(" * Common system register values for %s.\n"
519 " */\n"
520 "static SUPARMSYSREGVAL const g_aCmnSysRegVals_%s[] =\n"
521 "{\n",
522 pszCpuDesc, pszNameC);
523 else
524 {
525 vbCpuRepPrintf(" * System register values for %s, variation #%u.\n"
526 " * %u CPUs shares this variant: ",
527 pszCpuDesc, iVariation,
528 g_aVariations[iVariation].cCores);
529 int iLast = RTCpuSetLastIndex(&g_aVariations[iVariation].bmMembers);
530 for (int i = 0, cPrinted = 0; i <= iLast; i++)
531 if (RTCpuSetIsMemberByIndex(&g_aVariations[iVariation].bmMembers, i))
532 vbCpuRepPrintf(cPrinted++ == 0 ? "%u" : ", %u", i);
533 vbCpuRepPrintf("\n"
534 " */\n"
535 "static SUPARMSYSREGVAL const g_aVar%uSysRegVals_%s[] =\n"
536 "{\n",
537 iVariation, pszNameC);
538 }
539 for (uint32_t i = 0; i < cSysRegVals; i++)
540 {
541 uint32_t const idReg = paSysRegVals[i].idReg;
542 uint32_t const uOp0 = ARMV8_AARCH64_SYSREG_ID_GET_OP0(idReg);
543 uint32_t const uOp1 = ARMV8_AARCH64_SYSREG_ID_GET_OP1(idReg);
544 uint32_t const uCRn = ARMV8_AARCH64_SYSREG_ID_GET_CRN(idReg);
545 uint32_t const uCRm = ARMV8_AARCH64_SYSREG_ID_GET_CRM(idReg);
546 uint32_t const uOp2 = ARMV8_AARCH64_SYSREG_ID_GET_OP2(idReg);
547 const char * const pszNm = sysRegNoToName(idReg);
548
549 vbCpuRepPrintf(" { UINT64_C(%#018RX64), ARMV8_AARCH64_SYSREG_ID_CREATE(%u, %u,%2u,%2u, %u), %#x },%s%s%s\n",
550 paSysRegVals[i].uValue, uOp0, uOp1, uCRn, uCRm, uOp2, paSysRegVals[i].fFlags,
551 pszNm ? " /* " : "", pszNm ? pszNm : "", pszNm ? " */" : "");
552 }
553 vbCpuRepPrintf("};\n"
554 "\n");
555}
556
557
558/**
559 * Populate the system register array and output it.
560 */
561static int produceSysRegArray(const char *pszNameC, const char *pszCpuDesc)
562{
563 printSysRegArray(pszNameC, g_cCmnSysRegVals, g_aCmnSysRegVals, pszCpuDesc);
564 for (uint32_t iVar = 0; iVar < g_cVariations; iVar++)
565 printSysRegArray(pszNameC, g_aVariations[iVar].cSysRegVals, g_aVariations[iVar].aSysRegVals,
566 g_aVariations[iVar].pszFullName, iVar);
567 return VINF_SUCCESS;
568}
569
570
571int produceCpuReport(void)
572{
573 /*
574 * Figure out the processor name via the host OS and command line first...
575 */
576 /** @todo HKLM/Hardware/... */
577 char szDetectedCpuName[256] = {0};
578 int rc = RTMpGetDescription(NIL_RTCPUID, szDetectedCpuName, sizeof(szDetectedCpuName));
579 if (RT_SUCCESS(rc))
580 vbCpuRepDebug("szDetectedCpuName: %s\n", szDetectedCpuName);
581 if (RT_FAILURE(rc) || strcmp(szDetectedCpuName, "Unknown") == 0)
582 szDetectedCpuName[0] = '\0';
583
584 const char *pszCpuName = g_pszCpuNameOverride ? g_pszCpuNameOverride : RTStrStrip(szDetectedCpuName);
585 if (strlen(pszCpuName) >= sizeof(szDetectedCpuName))
586 return RTMsgErrorRc(VERR_FILENAME_TOO_LONG, "CPU name is too long: %zu chars, max %zu: %s",
587 strlen(pszCpuName), sizeof(szDetectedCpuName) - 1, pszCpuName);
588
589 /*
590 * Get the system registers first so we can try identify the CPU.
591 */
592 rc = populateSystemRegisters();
593 if (RT_FAILURE(rc))
594 return rc;
595
596 /*
597 * Identify each of the CPU variations we've detected.
598 */
599 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
600 {
601 /*
602 * Now that we've got the ID register values, figure out the vendor,
603 * microarch, cpu name and description..
604 */
605 uint64_t const uMIdReg = getSysRegVal(ARMV8_AARCH64_SYSREG_MIDR_EL1, iVar);
606 g_aVariations[iVar].uMIdReg = uMIdReg;
607
608 uint8_t const bImplementer = (uint8_t )((uMIdReg >> 24) & 0xff);
609 uint8_t const bVariant = (uint8_t )((uMIdReg >> 20) & 0xf);
610 uint16_t const uPartNum = (uint16_t)((uMIdReg >> 4) & 0xfff);
611 //uint8_t const bRevision = (uint8_t )( uMIdReg & 0x7);
612 uint16_t const uPartNumEx = uPartNum | ((uint16_t)bVariant << 12);
613
614 /** @todo move this to CPUM or IPRT... */
615 PARTNUMINFO const *paPartNums;
616 size_t cPartNums;
617 uint32_t uPartNumSearch = uPartNum;
618 switch (bImplementer)
619 {
620 case 0x41:
621 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_ARM;
622 paPartNums = g_aPartNumDbArm;
623 cPartNums = RT_ELEMENTS(g_aPartNumDbArm);
624 break;
625
626 case 0x42:
627 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_BROADCOM;
628 paPartNums = g_aPartNumDbBroadcom;
629 cPartNums = RT_ELEMENTS(g_aPartNumDbBroadcom);
630 break;
631
632 case 0x51:
633 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_QUALCOMM;
634 paPartNums = g_aPartNumDbQualcomm;
635 cPartNums = RT_ELEMENTS(g_aPartNumDbQualcomm);
636 uPartNumSearch = uPartNumEx; /* include the variant in the search */
637 break;
638
639 case 0x61:
640 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_APPLE;
641 paPartNums = g_aPartNumDbApple;
642 cPartNums = RT_ELEMENTS(g_aPartNumDbApple);
643 break;
644
645 case 0xc0:
646 g_aVariations[iVar].enmVendor = CPUMCPUVENDOR_AMPERE;
647 paPartNums = g_aPartNumDbAmpere;
648 cPartNums = RT_ELEMENTS(g_aPartNumDbAmpere);
649 break;
650
651 default:
652 return RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "Unknown ARM implementer: %#x (%s)", bImplementer, pszCpuName);
653 }
654
655 /* Look up the part number in the vendor table: */
656 g_aVariations[iVar].enmCoreType = kCpumCoreType_Invalid;
657 g_aVariations[iVar].enmMicroarch = kCpumMicroarch_Invalid;
658 g_aVariations[iVar].pszName = NULL;
659 g_aVariations[iVar].pszFullName = NULL;
660 for (size_t i = 0; i < cPartNums; i++)
661 if (paPartNums[i].uPartNum == uPartNumSearch)
662 {
663 g_aVariations[iVar].enmCoreType = paPartNums[i].enmCoreType;
664 g_aVariations[iVar].enmMicroarch = paPartNums[i].enmMicroarch;
665 g_aVariations[iVar].pszName = paPartNums[i].pszName;
666 g_aVariations[iVar].pszFullName = paPartNums[i].pszFullName;
667 break;
668 }
669 if (g_aVariations[iVar].enmMicroarch == kCpumMicroarch_Invalid)
670 return RTMsgErrorRc(VERR_UNSUPPORTED_CPU, "%s part number not found: %#x (MIDR_EL1=%#x%s%s)",
671 CPUMCpuVendorName(g_aVariations[iVar].enmVendor), uPartNum, uMIdReg,
672 *pszCpuName ? " " : "", pszCpuName);
673 }
674
675 /*
676 * Sort the variations by core type.
677 */
678 AssertCompile(sizeof(g_aVariations[0]) < _32K); /* Stack allocation in RTSortShell. */
679 if (g_cVariations > 1)
680 RTSortShell(g_aVariations, g_cVariations, sizeof(g_aVariations[0]), variationSortCmp, NULL);
681
682 /*
683 * Take the CPU name and description from the first variation,
684 * unless something better is provided on the command line.
685 */
686 if (!g_pszCpuNameOverride)
687 pszCpuName = g_aVariations[0].pszName;
688 const char * const pszCpuDesc = strlen(szDetectedCpuName) > strlen(pszCpuName) ? RTStrStrip(szDetectedCpuName)
689 : g_cVariations == 1 ? g_aVariations[0].pszFullName : pszCpuName;
690
691 /*
692 * Sanitize the name.
693 */
694 char szName[sizeof(szDetectedCpuName)];
695 size_t offSrc = 0;
696 size_t offDst = 0;
697 for (;;)
698 {
699 char ch = pszCpuName[offSrc++];
700 if (!RT_C_IS_SPACE(ch))
701 szName[offDst++] = ch;
702 else
703 {
704 while (RT_C_IS_SPACE((ch = pszCpuName[offSrc])))
705 offSrc++;
706 if (offDst > 0 && ch != '\0')
707 szName[offDst++] = ' ';
708 }
709 if (!ch)
710 break;
711 }
712 RTStrPurgeEncoding(szName);
713 pszCpuName = szName;
714 vbCpuRepDebug("Name: %s\n", pszCpuName);
715
716 /*
717 * Make it C/C++ acceptable.
718 */
719 static const char s_szNamePrefix[] = "ARM_";
720 char szNameC[sizeof(s_szNamePrefix) + sizeof(szDetectedCpuName)];
721 strcpy(szNameC, s_szNamePrefix);
722 /** @todo Move to common function... */
723 offDst = sizeof(s_szNamePrefix) - 1;
724 offSrc = 0;
725 for (;;)
726 {
727 char ch = pszCpuName[offSrc++];
728 if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
729 ch = '_';
730 if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
731 offDst--;
732 szNameC[offDst++] = ch;
733 if (!ch)
734 break;
735 }
736 while (offDst > 1 && szNameC[offDst - 1] == '_')
737 szNameC[--offDst] = '\0';
738
739 vbCpuRepDebug("NameC: %s\n", szNameC);
740
741 /*
742 * Print a file header, if we're not outputting to stdout (assumption being
743 * that stdout is used while hacking the reporter and too much output is
744 * unwanted).
745 */
746 if (g_pReportOut)
747 vbCpuRepFileHdr(pszCpuName, szNameC);
748
749 /*
750 * Produce the array of system (id) register values.
751 */
752 rc = produceSysRegArray(szNameC, pszCpuDesc);
753 if (RT_FAILURE(rc))
754 return rc;
755
756 /*
757 * Emit the database entry.
758 */
759 vbCpuRepPrintf("\n"
760 "/**\n"
761 " * Database entry for %s.\n"
762 " */\n"
763 "static CPUMDBENTRYARM const g_Entry_%s =\n"
764 "{\n"
765 " {\n"
766 " /*.pszName = */ \"%s\",\n"
767 " /*.pszFullName = */ \"%s\",\n"
768 " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
769 " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
770 " /*.fFlags = */ 0,\n"
771 " },\n"
772 " /*.paSysRegCmnVals = */ NULL_ALONE(g_aCmnSysRegVals_%s),\n"
773 " /*.cSysRegCmnVals = */ ZERO_ALONE(RT_ELEMENTS(g_aCmnSysRegVals_%s)),\n"
774 " /*.cVariants = */ %u,\n"
775 " /*.aVariants = */\n"
776 " {\n"
777 ,
778 pszCpuDesc,
779 szNameC,
780 pszCpuName,
781 pszCpuDesc,
782 vbCpuVendorToString(g_aVariations[0].enmVendor),
783 CPUMMicroarchName(g_aVariations[0].enmMicroarch),
784 szNameC,
785 szNameC,
786 g_cVariations);
787 for (unsigned iVar = 0; iVar < g_cVariations; iVar++)
788 {
789 vbCpuRepPrintf(" /*.Variants[%u] = */\n"
790 " {\n"
791 " /*.pszName = */ \"%s\",\n"
792 " /*.Midr = */\n"
793 " {\n"
794 " /*Midr.s = */\n"
795 " {\n"
796 " /*.u4Revision = */ %#03x,\n"
797 " /*.u12PartNum = */ %#05x,\n"
798 " /*.u4Arch = */ %#03x,\n"
799 " /*.u4Variant = */ %#03x,\n"
800 " /*.u4Implementer = */ %#04x,\n"
801 " }\n"
802 " },\n"
803 " /*.enmCoreType = */ kCpumCoreType_%s,\n"
804 ,
805 iVar,
806 g_aVariations[iVar].pszFullName,
807 (unsigned)( g_aVariations[iVar].uMIdReg & 0xf),
808 (unsigned)((g_aVariations[iVar].uMIdReg >> 4) & 0xfff),
809 (unsigned)((g_aVariations[iVar].uMIdReg >> 16) & 0xf),
810 (unsigned)((g_aVariations[iVar].uMIdReg >> 20) & 0xf),
811 (unsigned)((g_aVariations[iVar].uMIdReg >> 24) & 0xff),
812 vbGetCoreTypeToString(g_aVariations[iVar].enmCoreType));
813 if (g_aVariations[iVar].cSysRegVals == 0)
814 vbCpuRepPrintf(" /*.cSysRegVals = */ 0,\n"
815 " /*.paSysRegVals = */ NULL\n");
816 else
817 vbCpuRepPrintf(" /*.cSysRegVals = */ ZERO_ALONE(RT_ELEMENTS(g_aVar%uSysRegVals_%s)),\n"
818 " /*.paSysRegVals = */ NULL_ALONE(g_aVar%uSysRegVals_%s)\n",
819 iVar, szNameC, iVar, szNameC);
820 vbCpuRepPrintf(" },\n");
821 }
822 vbCpuRepPrintf(" }\n"
823 "};\n"
824 "\n"
825 "#endif /* !VBOX_CPUDB_%s_h */\n"
826 "\n",
827 szNameC);
828
829 return VINF_SUCCESS;
830}
831
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