VirtualBox

source: vbox/trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp@ 65801

Last change on this file since 65801 was 62869, checked in by vboxsync, 8 years ago

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1/* $Id: VBoxCpuReport.cpp 62869 2016-08-02 12:01:23Z vboxsync $ */
2/** @file
3 * VBoxCpuReport - Produces the basis for a CPU DB entry.
4 */
5
6/*
7 * Copyright (C) 2013-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#include <iprt/asm.h>
23#include <iprt/asm-amd64-x86.h>
24#include <iprt/buildconfig.h>
25#include <iprt/ctype.h>
26#include <iprt/file.h>
27#include <iprt/getopt.h>
28#include <iprt/initterm.h>
29#include <iprt/message.h>
30#include <iprt/mem.h>
31#include <iprt/path.h>
32#include <iprt/string.h>
33#include <iprt/stream.h>
34#include <iprt/symlink.h>
35#include <iprt/thread.h>
36#include <iprt/time.h>
37
38#include <VBox/err.h>
39#include <VBox/vmm/cpum.h>
40#include <VBox/sup.h>
41
42
43/*******************************************************************************
44* Structures and Typedefs *
45*******************************************************************************/
46/** Write only register. */
47#define VBCPUREPMSR_F_WRITE_ONLY RT_BIT(0)
48
49typedef struct VBCPUREPMSR
50{
51 /** The first MSR register number. */
52 uint32_t uMsr;
53 /** Flags (MSRREPORT_F_XXX). */
54 uint32_t fFlags;
55 /** The value we read, unless write-only. */
56 uint64_t uValue;
57} VBCPUREPMSR;
58
59
60/*******************************************************************************
61* Global Variables *
62*******************************************************************************/
63/** The CPU vendor. Used by the MSR code. */
64static CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
65/** The CPU microarchitecture. Used by the MSR code. */
66static CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
67/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
68static bool g_fIntelNetBurst = false;
69/** The alternative report stream. */
70static PRTSTREAM g_pReportOut;
71/** The alternative debug stream. */
72static PRTSTREAM g_pDebugOut;
73
74/** Snooping info storage for vbCpuRepGuessScalableBusFrequencyName. */
75static uint64_t g_uMsrIntelP6FsbFrequency = UINT64_MAX;
76
77
78static void vbCpuRepDebug(const char *pszMsg, ...)
79{
80 va_list va;
81
82 /* Always print a copy of the report to standard error. */
83 va_start(va, pszMsg);
84 RTStrmPrintfV(g_pStdErr, pszMsg, va);
85 va_end(va);
86 RTStrmFlush(g_pStdErr);
87
88 /* Alternatively, also print to a log file. */
89 if (g_pDebugOut)
90 {
91 va_start(va, pszMsg);
92 RTStrmPrintfV(g_pDebugOut, pszMsg, va);
93 va_end(va);
94 RTStrmFlush(g_pDebugOut);
95 }
96
97 /* Give the output device a chance to write / display it. */
98 RTThreadSleep(1);
99}
100
101
102static void vbCpuRepPrintf(const char *pszMsg, ...)
103{
104 va_list va;
105
106 /* Output to report file, if requested. */
107 if (g_pReportOut)
108 {
109 va_start(va, pszMsg);
110 RTStrmPrintfV(g_pReportOut, pszMsg, va);
111 va_end(va);
112 RTStrmFlush(g_pReportOut);
113 }
114
115 /* Always print a copy of the report to standard out. */
116 va_start(va, pszMsg);
117 RTStrmPrintfV(g_pStdOut, pszMsg, va);
118 va_end(va);
119 RTStrmFlush(g_pStdOut);
120}
121
122
123
124static int vbCpuRepMsrsAddOne(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs,
125 uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
126{
127 /*
128 * Grow the array?
129 */
130 uint32_t cMsrs = *pcMsrs;
131 if ((cMsrs % 64) == 0)
132 {
133 void *pvNew = RTMemRealloc(*ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
134 if (!pvNew)
135 {
136 RTMemFree(*ppaMsrs);
137 *ppaMsrs = NULL;
138 *pcMsrs = 0;
139 return VERR_NO_MEMORY;
140 }
141 *ppaMsrs = (VBCPUREPMSR *)pvNew;
142 }
143
144 /*
145 * Add it.
146 */
147 VBCPUREPMSR *pEntry = *ppaMsrs + cMsrs;
148 pEntry->uMsr = uMsr;
149 pEntry->fFlags = fFlags;
150 pEntry->uValue = uValue;
151 *pcMsrs = cMsrs + 1;
152
153 return VINF_SUCCESS;
154}
155
156
157/**
158 * Returns the max physical address width as a number of bits.
159 *
160 * @returns Bit count.
161 */
162static uint8_t vbCpuRepGetPhysAddrWidth(void)
163{
164 uint8_t cMaxWidth;
165 uint32_t cMaxExt = ASMCpuId_EAX(0x80000000);
166 if (!ASMHasCpuId())
167 cMaxWidth = 32;
168 else if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
169 cMaxWidth = ASMCpuId_EAX(0x80000008) & 0xff;
170 else if ( ASMIsValidStdRange(ASMCpuId_EAX(0))
171 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
172 cMaxWidth = 36;
173 else
174 cMaxWidth = 32;
175 return cMaxWidth;
176}
177
178
179static bool vbCpuRepSupportsPae(void)
180{
181 return ASMHasCpuId()
182 && ASMIsValidStdRange(ASMCpuId_EAX(0))
183 && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE);
184}
185
186
187static bool vbCpuRepSupportsLongMode(void)
188{
189 return ASMHasCpuId()
190 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
191 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
192}
193
194
195static bool vbCpuRepSupportsNX(void)
196{
197 return ASMHasCpuId()
198 && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
199 && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
200}
201
202
203static bool vbCpuRepSupportsX2Apic(void)
204{
205 return ASMHasCpuId()
206 && ASMIsValidStdRange(ASMCpuId_EAX(0))
207 && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
208}
209
210
211
212#if 0 /* unused */
213static bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
214{
215 bool fGp;
216 int rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
217 AssertRC(rc);
218 return RT_SUCCESS(rc) && !fGp;
219}
220#endif
221
222
223static bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
224{
225 *puValue = 0;
226 bool fGp;
227 int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
228 AssertRC(rc);
229 return RT_SUCCESS(rc) && !fGp;
230}
231
232
233/** Tries to modify the register by writing the original value to it. */
234static bool msrProberModifyNoChange(uint32_t uMsr)
235{
236 SUPMSRPROBERMODIFYRESULT Result;
237 int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
238 return RT_SUCCESS(rc)
239 && !Result.fBeforeGp
240 && !Result.fModifyGp
241 && !Result.fAfterGp
242 && !Result.fRestoreGp;
243}
244
245
246/** Tries to modify the register by writing zero to it. */
247static bool msrProberModifyZero(uint32_t uMsr)
248{
249 SUPMSRPROBERMODIFYRESULT Result;
250 int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
251 return RT_SUCCESS(rc)
252 && !Result.fBeforeGp
253 && !Result.fModifyGp
254 && !Result.fAfterGp
255 && !Result.fRestoreGp;
256}
257
258
259/**
260 * Tries to modify each bit in the MSR and see if we can make it change.
261 *
262 * @returns VBox status code.
263 * @param uMsr The MSR.
264 * @param pfIgnMask The ignore mask to update.
265 * @param pfGpMask The GP mask to update.
266 * @param fSkipMask Mask of bits to skip.
267 */
268static int msrProberModifyBitChanges(uint32_t uMsr, uint64_t *pfIgnMask, uint64_t *pfGpMask, uint64_t fSkipMask)
269{
270 for (unsigned iBit = 0; iBit < 64; iBit++)
271 {
272 uint64_t fBitMask = RT_BIT_64(iBit);
273 if (fBitMask & fSkipMask)
274 continue;
275
276 /* Set it. */
277 SUPMSRPROBERMODIFYRESULT ResultSet;
278 int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
279 if (RT_FAILURE(rc))
280 return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
281
282 /* Clear it. */
283 SUPMSRPROBERMODIFYRESULT ResultClear;
284 rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
285 if (RT_FAILURE(rc))
286 return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
287
288 if (ResultSet.fModifyGp || ResultClear.fModifyGp)
289 *pfGpMask |= fBitMask;
290 else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
291 && !ResultSet.fBeforeGp
292 && !ResultSet.fAfterGp)
293 && ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
294 && !ResultClear.fBeforeGp
295 && !ResultClear.fAfterGp) )
296 *pfIgnMask |= fBitMask;
297 }
298
299 return VINF_SUCCESS;
300}
301
302
303#if 0 /* currently unused */
304/**
305 * Tries to modify one bit.
306 *
307 * @retval -2 on API error.
308 * @retval -1 on \#GP.
309 * @retval 0 if ignored.
310 * @retval 1 if it changed.
311 *
312 * @param uMsr The MSR.
313 * @param iBit The bit to try modify.
314 */
315static int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
316{
317 uint64_t fBitMask = RT_BIT_64(iBit);
318
319 /* Set it. */
320 SUPMSRPROBERMODIFYRESULT ResultSet;
321 int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
322 if (RT_FAILURE(rc))
323 return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
324
325 /* Clear it. */
326 SUPMSRPROBERMODIFYRESULT ResultClear;
327 rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
328 if (RT_FAILURE(rc))
329 return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
330
331 if (ResultSet.fModifyGp || ResultClear.fModifyGp)
332 return -1;
333
334 if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
335 && !ResultSet.fBeforeGp
336 && !ResultSet.fAfterGp)
337 || ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
338 && !ResultClear.fBeforeGp
339 && !ResultClear.fAfterGp) )
340 return 1;
341
342 return 0;
343}
344#endif
345
346
347/**
348 * Tries to do a simple AND+OR change and see if we \#GP or not.
349 *
350 * @retval @c true if successfully modified.
351 * @retval @c false if \#GP or other error.
352 *
353 * @param uMsr The MSR.
354 * @param fAndMask The AND mask.
355 * @param fOrMask The OR mask.
356 */
357static bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
358{
359 SUPMSRPROBERMODIFYRESULT Result;
360 int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
361 if (RT_FAILURE(rc))
362 {
363 RTMsgError("SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
364 return false;
365 }
366 return !Result.fBeforeGp
367 && !Result.fModifyGp
368 && !Result.fAfterGp
369 && !Result.fRestoreGp;
370}
371
372
373
374
375/**
376 * Combination of the basic tests.
377 *
378 * @returns VBox status code.
379 * @param uMsr The MSR.
380 * @param fSkipMask Mask of bits to skip.
381 * @param pfReadOnly Where to return read-only status.
382 * @param pfIgnMask Where to return the write ignore mask. Need not
383 * be initialized.
384 * @param pfGpMask Where to return the write GP mask. Need not
385 * be initialized.
386 */
387static int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool *pfReadOnly, uint64_t *pfIgnMask, uint64_t *pfGpMask)
388{
389 if (msrProberModifyNoChange(uMsr))
390 {
391 *pfReadOnly = false;
392 *pfIgnMask = 0;
393 *pfGpMask = 0;
394 return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
395 }
396
397 *pfReadOnly = true;
398 *pfIgnMask = 0;
399 *pfGpMask = UINT64_MAX;
400 return VINF_SUCCESS;
401}
402
403
404
405/**
406 * Determines for the MSR AND mask.
407 *
408 * Older CPUs doesn't necessiarly implement all bits of the MSR register number.
409 * So, we have to approximate how many are used so we don't get an overly large
410 * and confusing set of MSRs when probing.
411 *
412 * @returns The mask.
413 */
414static uint32_t determineMsrAndMask(void)
415{
416#define VBCPUREP_MASK_TEST_MSRS 7
417 static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
418 {
419 /* Try a bunch of mostly read only registers: */
420 MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
421 /* Then some which aren't supposed to be present on any CPU: */
422 0x00000015, 0x00000019,
423 };
424
425 /* Get the base values. */
426 uint64_t auBaseValues[VBCPUREP_MASK_TEST_MSRS];
427 for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
428 {
429 if (!msrProberRead(s_aMsrs[i], &auBaseValues[i]))
430 auBaseValues[i] = UINT64_MAX;
431 //vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
432 }
433
434 /* Do the probing. */
435 unsigned iBit;
436 for (iBit = 31; iBit > 8; iBit--)
437 {
438 uint64_t fMsrOrMask = RT_BIT_64(iBit);
439 for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
440 {
441 for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
442 {
443 uint64_t uValue;
444 if (!msrProberRead(s_aMsrs[i] | fMsrOrMask, &uValue))
445 uValue = UINT64_MAX;
446 if (uValue != auBaseValues[i])
447 {
448 uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
449 vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
450 iBit, s_aMsrs[i] | (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
451 return fMsrMask;
452 }
453 }
454
455 /* Advance. */
456 if (iBit <= 6)
457 fMsrOrMask += RT_BIT_64(iBit);
458 else if (iBit <= 11)
459 fMsrOrMask += RT_BIT_64(iBit) * 33;
460 else if (iBit <= 16)
461 fMsrOrMask += RT_BIT_64(iBit) * 1025;
462 else if (iBit <= 22)
463 fMsrOrMask += RT_BIT_64(iBit) * 65537;
464 else
465 fMsrOrMask += RT_BIT_64(iBit) * 262145;
466 }
467 }
468
469 uint32_t fMsrMask = RT_BIT_32(iBit + 1) - 1;
470 vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
471 return fMsrMask;
472}
473
474
475static int findMsrs(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs, uint32_t fMsrMask)
476{
477 /*
478 * Gather them.
479 */
480 static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
481 {
482 { 0x00000000, 0x00042000 },
483 { 0x10000000, 0x00001000 },
484 { 0x20000000, 0x00001000 },
485 { 0x40000000, 0x00012000 },
486 { 0x80000000, 0x00012000 },
487 { 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
488 };
489
490 *pcMsrs = 0;
491 *ppaMsrs = NULL;
492
493 for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
494 {
495 uint32_t uMsr = s_aRanges[i].uFirst;
496 if ((uMsr & fMsrMask) != uMsr)
497 continue;
498 uint32_t cLeft = s_aRanges[i].cMsrs;
499 while (cLeft-- > 0 && (uMsr & fMsrMask) == uMsr)
500 {
501 if ((uMsr & 0xfff) == 0)
502 {
503 vbCpuRepDebug("testing %#x...\n", uMsr);
504 RTThreadSleep(22);
505 }
506#if 0
507 else if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
508 {
509 vbCpuRepDebug("testing %#x...\n", uMsr);
510 RTThreadSleep(250);
511 }
512#endif
513 /* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
514 /* Ditto for 0x0000002a (EBL_CR_POWERON) and 0x00000277 (MSR_IA32_CR_PAT) on Intel (Atom 330). */
515 /* And more of the same for 0x280 on Intel Pentium III. */
516 if ( ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && g_enmVendor == CPUMCPUVENDOR_AMD)
517 || ( (uMsr == 0x2a || uMsr == 0x277)
518 && g_enmVendor == CPUMCPUVENDOR_INTEL
519 && g_enmMicroarch == kCpumMicroarch_Intel_Atom_Bonnell)
520 || ( (uMsr == 0x280)
521 && g_enmMicroarch == kCpumMicroarch_Intel_P6_III))
522 vbCpuRepDebug("Skipping %#x\n", uMsr);
523 else
524 {
525 /* Read probing normally does it. */
526 uint64_t uValue = 0;
527 bool fGp = true;
528 int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
529 if (RT_FAILURE(rc))
530 {
531 RTMemFree(*ppaMsrs);
532 *ppaMsrs = NULL;
533 return RTMsgErrorRc(rc, "SUPR3MsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
534 }
535
536 uint32_t fFlags;
537 if (!fGp)
538 fFlags = 0;
539 /* VIA HACK - writing to 0x0000317e on a quad core make the core unresponsive. */
540 else if (uMsr == 0x0000317e && g_enmVendor == CPUMCPUVENDOR_VIA)
541 {
542 uValue = 0;
543 fFlags = VBCPUREPMSR_F_WRITE_ONLY;
544 fGp = *pcMsrs == 0
545 || (*ppaMsrs)[*pcMsrs - 1].uMsr != 0x0000317d
546 || (*ppaMsrs)[*pcMsrs - 1].fFlags != VBCPUREPMSR_F_WRITE_ONLY;
547 }
548 else
549 {
550 /* Is it a write only register? */
551#if 0
552 if (uMsr >= 0x00003170 && uMsr <= 0xc0000090)
553 {
554 vbCpuRepDebug("test writing %#x...\n", uMsr);
555 RTThreadSleep(250);
556 }
557#endif
558 fGp = true;
559 rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
560 if (RT_FAILURE(rc))
561 {
562 RTMemFree(*ppaMsrs);
563 *ppaMsrs = NULL;
564 return RTMsgErrorRc(rc, "SUPR3MsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
565 }
566 uValue = 0;
567 fFlags = VBCPUREPMSR_F_WRITE_ONLY;
568
569 /*
570 * Tweaks. On Intel CPUs we've got trouble detecting
571 * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
572 * Ditto on AMD with PATCH_LOADER (0xc0010020).
573 */
574 if ( uMsr == 0x00000079
575 && fGp
576 && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
577 && g_enmMicroarch <= kCpumMicroarch_Intel_End)
578 fGp = false;
579 if ( uMsr == 0xc0010020
580 && fGp
581 && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First
582 && g_enmMicroarch <= kCpumMicroarch_AMD_End)
583 fGp = false;
584 }
585
586 if (!fGp)
587 {
588 /* Add it. */
589 rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
590 if (RT_FAILURE(rc))
591 return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
592 if ( g_enmVendor != CPUMCPUVENDOR_VIA
593 || uValue
594 || fFlags)
595 vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
596 }
597 }
598
599 uMsr++;
600 }
601 }
602
603 return VINF_SUCCESS;
604}
605
606/**
607 * Get the name of the specified MSR, if we know it and can handle it.
608 *
609 * Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
610 * is handled correctly by the PROBING CODE and REPORTED correctly!!
611 *
612 * @returns Pointer to name if handled, NULL if not yet explored.
613 * @param uMsr The MSR in question.
614 */
615static const char *getMsrNameHandled(uint32_t uMsr)
616{
617 /** @todo figure out where NCU_EVENT_CORE_MASK might be... */
618 switch (uMsr)
619 {
620 case 0x00000000: return "IA32_P5_MC_ADDR";
621 case 0x00000001: return "IA32_P5_MC_TYPE";
622 case 0x00000006:
623 if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
624 return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
625 return "IA32_MONITOR_FILTER_LINE_SIZE";
626 //case 0x0000000e: return "P?_TR12"; /* K6-III docs */
627 case 0x00000010: return "IA32_TIME_STAMP_COUNTER";
628 case 0x00000017: return "IA32_PLATFORM_ID";
629 case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
630 case 0x0000001b: return "IA32_APIC_BASE";
631 case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
632 case 0x0000002a: return g_fIntelNetBurst ? "P4_EBC_HARD_POWERON" : "EBL_CR_POWERON";
633 case 0x0000002b: return g_fIntelNetBurst ? "P4_EBC_SOFT_POWERON" : NULL;
634 case 0x0000002c: return g_fIntelNetBurst ? "P4_EBC_FREQUENCY_ID" : NULL;
635 case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
636 case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
637 case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
638 case 0x00000033: return "TEST_CTL";
639 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch)
640 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch)
641 ? "MSR_SMI_COUNT" : "P6_UNK_0000_0034"; /* P6_M_Dothan. */
642 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_CORE_THREAD_COUNT" : "P6_UNK_0000_0035"; /* P6_M_Dothan. */
643 case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
644 case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
645 case 0x0000003a: return "IA32_FEATURE_CONTROL";
646 case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
647 case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
648 case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
649 case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
650 case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
651 case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
652 case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
653 case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
654 case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
655 case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
656 case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
657 case 0x00000048: return "MSR_LASTBRANCH_8"; /*??*/
658 case 0x00000049: return "MSR_LASTBRANCH_9"; /*??*/
659 case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
660 case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
661 case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
662 case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
663 case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
664 case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
665 case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
666 case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
667 case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
668 case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
669 case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
670 case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
671 case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
672 case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
673 case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
674 case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
675 case 0x00000065: return "MSR_LASTBRANCH_5_TO_IP";
676 case 0x00000066: return "MSR_LASTBRANCH_6_TO_IP";
677 case 0x00000067: return "MSR_LASTBRANCH_7_TO_IP";
678 case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
679 case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
680 case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
681 case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
682 case 0x00000079: return "IA32_BIOS_UPDT_TRIG";
683 case 0x00000080: return "P4_UNK_0000_0080";
684 case 0x00000088: return "BBL_CR_D0";
685 case 0x00000089: return "BBL_CR_D1";
686 case 0x0000008a: return "BBL_CR_D2";
687 case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AMD_K8_PATCH_LEVEL"
688 : g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3|BIOS_SIGN";
689 case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
690 case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
691 case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
692 case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
693 case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
694 case 0x0000009b: return "IA32_SMM_MONITOR_CTL";
695 case 0x000000a8: return "C2_EMTTM_CR_TABLES_0";
696 case 0x000000a9: return "C2_EMTTM_CR_TABLES_1";
697 case 0x000000aa: return "C2_EMTTM_CR_TABLES_2";
698 case 0x000000ab: return "C2_EMTTM_CR_TABLES_3";
699 case 0x000000ac: return "C2_EMTTM_CR_TABLES_4";
700 case 0x000000ad: return "C2_EMTTM_CR_TABLES_5";
701 case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
702 case 0x000000c1: return "IA32_PMC0";
703 case 0x000000c2: return "IA32_PMC1";
704 case 0x000000c3: return "IA32_PMC2";
705 case 0x000000c4: return "IA32_PMC3";
706 /* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
707 on the safe side as we must avoid P6_M_Dothan and possibly others. */
708 case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
709 case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
710 case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
711 case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
712 case 0x000000cd: return "MSR_FSB_FREQ"; /* P6_M_Dothan. */
713 case 0x000000ce: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PLATFORM_INFO" : "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
714 case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
715 case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
716 case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
717 case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
718 case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
719 case 0x000000e4: return "MSR_PMG_IO_CAPTURE_BASE";
720 case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
721 case 0x000000e7: return "IA32_MPERF";
722 case 0x000000e8: return "IA32_APERF";
723 case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
724 case 0x000000fe: return "IA32_MTRRCAP";
725 case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
726 case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
727 case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
728 case 0x00000116: return "BBL_CR_ADDR";
729 case 0x00000118: return "BBL_CR_DECC";
730 case 0x00000119: return "BBL_CR_CTL";
731 case 0x0000011a: return "BBL_CR_TRIG";
732 case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
733 case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
734 case 0x0000011e: return "BBL_CR_CTL3";
735 case 0x00000120: return "SILV_UNK_0000_0120"; /* Silvermont */
736 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
737 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
738 ? "CPUID1_FEATURE_MASK" : NULL;
739 case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
740 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
741 ? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
742 case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
743 ? "CPUID1_FEATURE_MASK" : NULL;
744 case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
745 ? "CPUIDD_01_FEATURE_MASK" : NULL;
746 case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
747 ? "CPUID80000001_FEATURE_MASK" : NULL;
748 case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
749 case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
750 case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
751 case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
752 case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
753 case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
754 case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
755 case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
756 case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
757 case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
758 case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
759 case 0x00000174: return "IA32_SYSENTER_CS";
760 case 0x00000175: return "IA32_SYSENTER_ESP";
761 case 0x00000176: return "IA32_SYSENTER_EIP";
762 case 0x00000179: return "IA32_MCG_CAP";
763 case 0x0000017a: return "IA32_MCG_STATUS";
764 case 0x0000017b: return "IA32_MCG_CTL";
765 case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
766 case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
767 case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
768 case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
769 case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
770 case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
771 case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
772 case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
773 case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
774 case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
775 case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
776 case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
777 case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
778 case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
779 case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
780 case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
781 case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
782 case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
783 case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
784 case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
785 case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
786 case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
787 case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
788 case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
789 case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
790 case 0x00000198: return "IA32_PERF_STATUS";
791 case 0x00000199: return "IA32_PERF_CTL";
792 case 0x0000019a: return "IA32_CLOCK_MODULATION";
793 case 0x0000019b: return "IA32_THERM_INTERRUPT";
794 case 0x0000019c: return "IA32_THERM_STATUS";
795 case 0x0000019d: return "IA32_THERM2_CTL";
796 case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
797 case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
798 case 0x000001a0: return "IA32_MISC_ENABLE";
799 case 0x000001a1: return g_fIntelNetBurst ? "MSR_PLATFORM_BRV" : "P6_UNK_0000_01a1" /* P6_M_Dothan. */;
800 case 0x000001a2: return g_fIntelNetBurst ? "P4_UNK_0000_01a2" : "I7_MSR_TEMPERATURE_TARGET" /* SandyBridge, IvyBridge. */;
801 case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
802 case 0x000001a6: return "I7_MSR_OFFCORE_RSP_0";
803 case 0x000001a7: return "I7_MSR_OFFCORE_RSP_1";
804 case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
805 case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
806 case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
807 case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
808 case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
809 case 0x000001b0: return "IA32_ENERGY_PERF_BIAS";
810 case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
811 case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
812 case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
813 case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
814 case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
815 case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
816 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
817 ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
818 case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
819 case 0x000001d7: return g_fIntelNetBurst ? "MSR_LER_FROM_LIP" : NULL;
820 case 0x000001d8: return g_fIntelNetBurst ? "MSR_LER_TO_LIP" : NULL;
821 case 0x000001d9: return "IA32_DEBUGCTL";
822 case 0x000001da: return g_fIntelNetBurst ? "MSR_LASTBRANCH_TOS" : NULL;
823 case 0x000001db: return g_fIntelNetBurst ? "P6_LASTBRANCH_0" : "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
824 case 0x000001dc: return g_fIntelNetBurst ? "P6_LASTBRANCH_1" : "P6_LAST_BRANCH_TO_IP";
825 case 0x000001dd: return g_fIntelNetBurst ? "P6_LASTBRANCH_2" : "P6_LAST_INT_FROM_IP";
826 case 0x000001de: return g_fIntelNetBurst ? "P6_LASTBRANCH_3" : "P6_LAST_INT_TO_IP";
827 case 0x000001e0: return "MSR_ROB_CR_BKUPTMPDR6";
828 case 0x000001e1: return "I7_SB_UNK_0000_01e1";
829 case 0x000001ef: return "I7_SB_UNK_0000_01ef";
830 case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
831 case 0x000001f2: return "IA32_SMRR_PHYSBASE";
832 case 0x000001f3: return "IA32_SMRR_PHYSMASK";
833 case 0x000001f8: return "IA32_PLATFORM_DCA_CAP";
834 case 0x000001f9: return "IA32_CPU_DCA_CAP";
835 case 0x000001fa: return "IA32_DCA_0_CAP";
836 case 0x000001fc: return "I7_MSR_POWER_CTL";
837
838 case 0x00000200: return "IA32_MTRR_PHYS_BASE0";
839 case 0x00000202: return "IA32_MTRR_PHYS_BASE1";
840 case 0x00000204: return "IA32_MTRR_PHYS_BASE2";
841 case 0x00000206: return "IA32_MTRR_PHYS_BASE3";
842 case 0x00000208: return "IA32_MTRR_PHYS_BASE4";
843 case 0x0000020a: return "IA32_MTRR_PHYS_BASE5";
844 case 0x0000020c: return "IA32_MTRR_PHYS_BASE6";
845 case 0x0000020e: return "IA32_MTRR_PHYS_BASE7";
846 case 0x00000210: return "IA32_MTRR_PHYS_BASE8";
847 case 0x00000212: return "IA32_MTRR_PHYS_BASE9";
848 case 0x00000214: return "IA32_MTRR_PHYS_BASE10";
849 case 0x00000216: return "IA32_MTRR_PHYS_BASE11";
850 case 0x00000218: return "IA32_MTRR_PHYS_BASE12";
851 case 0x0000021a: return "IA32_MTRR_PHYS_BASE13";
852 case 0x0000021c: return "IA32_MTRR_PHYS_BASE14";
853 case 0x0000021e: return "IA32_MTRR_PHYS_BASE15";
854
855 case 0x00000201: return "IA32_MTRR_PHYS_MASK0";
856 case 0x00000203: return "IA32_MTRR_PHYS_MASK1";
857 case 0x00000205: return "IA32_MTRR_PHYS_MASK2";
858 case 0x00000207: return "IA32_MTRR_PHYS_MASK3";
859 case 0x00000209: return "IA32_MTRR_PHYS_MASK4";
860 case 0x0000020b: return "IA32_MTRR_PHYS_MASK5";
861 case 0x0000020d: return "IA32_MTRR_PHYS_MASK6";
862 case 0x0000020f: return "IA32_MTRR_PHYS_MASK7";
863 case 0x00000211: return "IA32_MTRR_PHYS_MASK8";
864 case 0x00000213: return "IA32_MTRR_PHYS_MASK9";
865 case 0x00000215: return "IA32_MTRR_PHYS_MASK10";
866 case 0x00000217: return "IA32_MTRR_PHYS_MASK11";
867 case 0x00000219: return "IA32_MTRR_PHYS_MASK12";
868 case 0x0000021b: return "IA32_MTRR_PHYS_MASK13";
869 case 0x0000021d: return "IA32_MTRR_PHYS_MASK14";
870 case 0x0000021f: return "IA32_MTRR_PHYS_MASK15";
871
872 case 0x00000250: return "IA32_MTRR_FIX64K_00000";
873 case 0x00000258: return "IA32_MTRR_FIX16K_80000";
874 case 0x00000259: return "IA32_MTRR_FIX16K_A0000";
875 case 0x00000268: return "IA32_MTRR_FIX4K_C0000";
876 case 0x00000269: return "IA32_MTRR_FIX4K_C8000";
877 case 0x0000026a: return "IA32_MTRR_FIX4K_D0000";
878 case 0x0000026b: return "IA32_MTRR_FIX4K_D8000";
879 case 0x0000026c: return "IA32_MTRR_FIX4K_E0000";
880 case 0x0000026d: return "IA32_MTRR_FIX4K_E8000";
881 case 0x0000026e: return "IA32_MTRR_FIX4K_F0000";
882 case 0x0000026f: return "IA32_MTRR_FIX4K_F8000";
883 case 0x00000277: return "IA32_PAT";
884 case 0x00000280: return "IA32_MC0_CTL2";
885 case 0x00000281: return "IA32_MC1_CTL2";
886 case 0x00000282: return "IA32_MC2_CTL2";
887 case 0x00000283: return "IA32_MC3_CTL2";
888 case 0x00000284: return "IA32_MC4_CTL2";
889 case 0x00000285: return "IA32_MC5_CTL2";
890 case 0x00000286: return "IA32_MC6_CTL2";
891 case 0x00000287: return "IA32_MC7_CTL2";
892 case 0x00000288: return "IA32_MC8_CTL2";
893 case 0x00000289: return "IA32_MC9_CTL2";
894 case 0x0000028a: return "IA32_MC10_CTL2";
895 case 0x0000028b: return "IA32_MC11_CTL2";
896 case 0x0000028c: return "IA32_MC12_CTL2";
897 case 0x0000028d: return "IA32_MC13_CTL2";
898 case 0x0000028e: return "IA32_MC14_CTL2";
899 case 0x0000028f: return "IA32_MC15_CTL2";
900 case 0x00000290: return "IA32_MC16_CTL2";
901 case 0x00000291: return "IA32_MC17_CTL2";
902 case 0x00000292: return "IA32_MC18_CTL2";
903 case 0x00000293: return "IA32_MC19_CTL2";
904 case 0x00000294: return "IA32_MC20_CTL2";
905 case 0x00000295: return "IA32_MC21_CTL2";
906 //case 0x00000296: return "IA32_MC22_CTL2";
907 //case 0x00000297: return "IA32_MC23_CTL2";
908 //case 0x00000298: return "IA32_MC24_CTL2";
909 //case 0x00000299: return "IA32_MC25_CTL2";
910 //case 0x0000029a: return "IA32_MC26_CTL2";
911 //case 0x0000029b: return "IA32_MC27_CTL2";
912 //case 0x0000029c: return "IA32_MC28_CTL2";
913 //case 0x0000029d: return "IA32_MC29_CTL2";
914 //case 0x0000029e: return "IA32_MC30_CTL2";
915 //case 0x0000029f: return "IA32_MC31_CTL2";
916 case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
917 case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
918 case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
919 case 0x000002ff: return "IA32_MTRR_DEF_TYPE";
920 case 0x00000300: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
921 case 0x00000301: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER1" : NULL;
922 case 0x00000302: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER2" : NULL;
923 case 0x00000303: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER3" : NULL;
924 case 0x00000304: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER0" : NULL;
925 case 0x00000305: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
926 case 0x00000306: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER2" : NULL;
927 case 0x00000307: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER3" : NULL;
928 case 0x00000308: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER0" : NULL;
929 case 0x00000309: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
930 case 0x0000030a: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
931 case 0x0000030b: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
932 case 0x0000030c: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER0" : NULL;
933 case 0x0000030d: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER1" : NULL;
934 case 0x0000030e: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER2" : NULL;
935 case 0x0000030f: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER3" : NULL;
936 case 0x00000310: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER4" : NULL;
937 case 0x00000311: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER5" : NULL;
938 case 0x00000345: return "IA32_PERF_CAPABILITIES";
939 case 0x00000360: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR0" : NULL;
940 case 0x00000361: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR1" : NULL;
941 case 0x00000362: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR2" : NULL;
942 case 0x00000363: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR3" : NULL;
943 case 0x00000364: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR0" : NULL;
944 case 0x00000365: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR1" : NULL;
945 case 0x00000366: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR2" : NULL;
946 case 0x00000367: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR3" : NULL;
947 case 0x00000368: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR0" : NULL;
948 case 0x00000369: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR1" : NULL;
949 case 0x0000036a: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR2" : NULL;
950 case 0x0000036b: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR3" : NULL;
951 case 0x0000036c: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR0" : NULL;
952 case 0x0000036d: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR1" : NULL;
953 case 0x0000036e: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR2" : NULL;
954 case 0x0000036f: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR3" : NULL;
955 case 0x00000370: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR4" : NULL;
956 case 0x00000371: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR5" : NULL;
957 case 0x0000038d: return "IA32_FIXED_CTR_CTRL";
958 case 0x0000038e: return "IA32_PERF_GLOBAL_STATUS";
959 case 0x0000038f: return "IA32_PERF_GLOBAL_CTRL";
960 case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
961 case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
962 case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
963 case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
964 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */
965 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */
966 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */
967 case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? NULL : "I7_SB_UNK_0000_0397";
968 case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT";
969 case 0x000003a0: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR0" : NULL;
970 case 0x000003a1: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR1" : NULL;
971 case 0x000003a2: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR0" : NULL;
972 case 0x000003a3: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR1" : NULL;
973 case 0x000003a4: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR0" : NULL;
974 case 0x000003a5: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR1" : NULL;
975 case 0x000003a6: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR0" : NULL;
976 case 0x000003a7: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR1" : NULL;
977 case 0x000003a8: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR0" : NULL;
978 case 0x000003a9: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR1" : NULL;
979 case 0x000003aa: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR0" : NULL;
980 case 0x000003ab: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR1" : NULL;
981 case 0x000003ac: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR0" : NULL;
982 case 0x000003ad: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR1" : NULL;
983 case 0x000003ae: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR0" : NULL;
984 case 0x000003af: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR1" : NULL;
985 case 0x000003b0: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */
986 case 0x000003b1: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */ : "I7_UNC_ARB_PERF_CTR1"; /* >= S,H */
987 case 0x000003b2: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL0"; /* >= S,H */
988 case 0x000003b3: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL1"; /* >= S,H */
989 case 0x000003b4: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR0" : "I7_UNC_PMC4";
990 case 0x000003b5: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR1" : "I7_UNC_PMC5";
991 case 0x000003b6: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR0" : "I7_UNC_PMC6";
992 case 0x000003b7: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR1" : "I7_UNC_PMC7";
993 case 0x000003b8: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR0" : NULL;
994 case 0x000003b9: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR1" : NULL;
995 case 0x000003ba: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR0" : NULL;
996 case 0x000003bb: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR1" : NULL;
997 case 0x000003bc: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR0" : NULL;
998 case 0x000003bd: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR1" : NULL;
999 case 0x000003be: return g_fIntelNetBurst ? "P4_MSR_SSU_ESCR0" : NULL;
1000 case 0x000003c0: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR0" : "I7_UNC_PERF_EVT_SEL0";
1001 case 0x000003c1: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR1" : "I7_UNC_PERF_EVT_SEL1";
1002 case 0x000003c2: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR0" : "I7_UNC_PERF_EVT_SEL2";
1003 case 0x000003c3: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR1" : "I7_UNC_PERF_EVT_SEL3";
1004 case 0x000003c4: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR0" : "I7_UNC_PERF_EVT_SEL4";
1005 case 0x000003c5: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR1" : "I7_UNC_PERF_EVT_SEL5";
1006 case 0x000003c6: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL6";
1007 case 0x000003c7: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL7";
1008 case 0x000003c8: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
1009 case 0x000003c9: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
1010 case 0x000003ca: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR0" : NULL;
1011 case 0x000003cb: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR1" : NULL;
1012 case 0x000003cc: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR2" : NULL;
1013 case 0x000003cd: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR3" : NULL;
1014 case 0x000003e0: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR4" : NULL;
1015 case 0x000003e1: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR5" : NULL;
1016 case 0x000003f0: return g_fIntelNetBurst ? "P4_MSR_TC_PRECISE_EVENT" : NULL;
1017 case 0x000003f1: return "IA32_PEBS_ENABLE";
1018 case 0x000003f2: return g_fIntelNetBurst ? "P4_MSR_PEBS_MATRIX_VERT" : "IA32_PEBS_ENABLE";
1019 case 0x000003f3: return g_fIntelNetBurst ? "P4_UNK_0000_03f3" : NULL;
1020 case 0x000003f4: return g_fIntelNetBurst ? "P4_UNK_0000_03f4" : NULL;
1021 case 0x000003f5: return g_fIntelNetBurst ? "P4_UNK_0000_03f5" : NULL;
1022 case 0x000003f6: return g_fIntelNetBurst ? "P4_UNK_0000_03f6" : "I7_MSR_PEBS_LD_LAT";
1023 case 0x000003f7: return g_fIntelNetBurst ? "P4_UNK_0000_03f7" : "I7_MSR_PEBS_LD_LAT";
1024 case 0x000003f8: return g_fIntelNetBurst ? "P4_UNK_0000_03f8" : "I7_MSR_PKG_C3_RESIDENCY";
1025 case 0x000003f9: return "I7_MSR_PKG_C6_RESIDENCY";
1026 case 0x000003fa: return "I7_MSR_PKG_C7_RESIDENCY";
1027 case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
1028 case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
1029 case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
1030 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
1031 case 0x00000480: return "IA32_VMX_BASIC";
1032 case 0x00000481: return "IA32_VMX_PINBASED_CTLS";
1033 case 0x00000482: return "IA32_VMX_PROCBASED_CTLS";
1034 case 0x00000483: return "IA32_VMX_EXIT_CTLS";
1035 case 0x00000484: return "IA32_VMX_ENTRY_CTLS";
1036 case 0x00000485: return "IA32_VMX_MISC";
1037 case 0x00000486: return "IA32_VMX_CR0_FIXED0";
1038 case 0x00000487: return "IA32_VMX_CR0_FIXED1";
1039 case 0x00000488: return "IA32_VMX_CR4_FIXED0";
1040 case 0x00000489: return "IA32_VMX_CR4_FIXED1";
1041 case 0x0000048a: return "IA32_VMX_VMCS_ENUM";
1042 case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
1043 case 0x0000048c: return "IA32_VMX_EPT_VPID_CAP";
1044 case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
1045 case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
1046 case 0x0000048f: return "IA32_VMX_TRUE_EXIT_CTLS";
1047 case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
1048 case 0x00000491: return "IA32_VMX_VMFUNC";
1049 case 0x000004c1: return "IA32_A_PMC0";
1050 case 0x000004c2: return "IA32_A_PMC1";
1051 case 0x000004c3: return "IA32_A_PMC2";
1052 case 0x000004c4: return "IA32_A_PMC3";
1053 case 0x000004c5: return "IA32_A_PMC4";
1054 case 0x000004c6: return "IA32_A_PMC5";
1055 case 0x000004c7: return "IA32_A_PMC6";
1056 case 0x000004c8: return "IA32_A_PMC7";
1057 case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
1058 case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
1059 case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
1060 case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
1061 case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
1062 case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
1063 case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
1064 case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
1065 case 0x00000502: return "I7_SB_UNK_0000_0502";
1066 case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
1067 case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
1068 case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
1069 case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
1070 case 0x00000600: return "IA32_DS_AREA";
1071 case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
1072 case 0x00000602: return "I7_IB_UNK_0000_0602";
1073 case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
1074 case 0x00000604: return "I7_IB_UNK_0000_0602";
1075 case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
1076 case 0x00000609: return "I7_SB_UNK_0000_0609"; /* SandyBridge (non EP). */
1077 case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
1078 case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
1079 case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
1080 case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
1081 case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
1082 case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
1083 case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
1084 case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
1085 case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
1086 case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
1087 case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
1088 case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
1089 case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
1090 case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
1091 case 0x0000063a: return "I7_SB_MSR_PP0_POLICY";
1092 case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
1093 case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
1094 case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
1095 case 0x00000642: return "I7_HW_MSR_PP0_POLICY";
1096 case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
1097 case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
1098 case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
1099 case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
1100 case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
1101 case 0x00000660: return "SILV_CORE_C1_RESIDENCY";
1102 case 0x00000661: return "SILV_UNK_0000_0661";
1103 case 0x00000662: return "SILV_UNK_0000_0662";
1104 case 0x00000663: return "SILV_UNK_0000_0663";
1105 case 0x00000664: return "SILV_UNK_0000_0664";
1106 case 0x00000665: return "SILV_UNK_0000_0665";
1107 case 0x00000666: return "SILV_UNK_0000_0666";
1108 case 0x00000667: return "SILV_UNK_0000_0667";
1109 case 0x00000668: return "SILV_UNK_0000_0668";
1110 case 0x00000669: return "SILV_UNK_0000_0669";
1111 case 0x0000066a: return "SILV_UNK_0000_066a";
1112 case 0x0000066b: return "SILV_UNK_0000_066b";
1113 case 0x0000066c: return "SILV_UNK_0000_066c";
1114 case 0x0000066d: return "SILV_UNK_0000_066d";
1115 case 0x0000066e: return "SILV_UNK_0000_066e";
1116 case 0x0000066f: return "SILV_UNK_0000_066f";
1117 case 0x00000670: return "SILV_UNK_0000_0670";
1118 case 0x00000671: return "SILV_UNK_0000_0671";
1119 case 0x00000672: return "SILV_UNK_0000_0672";
1120 case 0x00000673: return "SILV_UNK_0000_0673";
1121 case 0x00000674: return "SILV_UNK_0000_0674";
1122 case 0x00000675: return "SILV_UNK_0000_0675";
1123 case 0x00000676: return "SILV_UNK_0000_0676";
1124 case 0x00000677: return "SILV_UNK_0000_0677";
1125
1126 case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
1127 case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
1128 case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
1129 case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
1130 case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
1131 case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
1132 case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
1133 case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
1134 case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
1135 case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
1136 case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
1137 case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
1138 case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
1139 case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
1140 case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
1141 case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
1142 case 0x000006c0: return "MSR_LASTBRANCH_0_TO_IP";
1143 case 0x000006c1: return "MSR_LASTBRANCH_1_TO_IP";
1144 case 0x000006c2: return "MSR_LASTBRANCH_2_TO_IP";
1145 case 0x000006c3: return "MSR_LASTBRANCH_3_TO_IP";
1146 case 0x000006c4: return "MSR_LASTBRANCH_4_TO_IP";
1147 case 0x000006c5: return "MSR_LASTBRANCH_5_TO_IP";
1148 case 0x000006c6: return "MSR_LASTBRANCH_6_TO_IP";
1149 case 0x000006c7: return "MSR_LASTBRANCH_7_TO_IP";
1150 case 0x000006c8: return "MSR_LASTBRANCH_8_TO_IP";
1151 case 0x000006c9: return "MSR_LASTBRANCH_9_TO_IP";
1152 case 0x000006ca: return "MSR_LASTBRANCH_10_TO_IP";
1153 case 0x000006cb: return "MSR_LASTBRANCH_11_TO_IP";
1154 case 0x000006cc: return "MSR_LASTBRANCH_12_TO_IP";
1155 case 0x000006cd: return "MSR_LASTBRANCH_13_TO_IP";
1156 case 0x000006ce: return "MSR_LASTBRANCH_14_TO_IP";
1157 case 0x000006cf: return "MSR_LASTBRANCH_15_TO_IP";
1158 case 0x000006e0: return "IA32_TSC_DEADLINE";
1159
1160 case 0x00000768: return "SILV_UNK_0000_0768";
1161 case 0x00000769: return "SILV_UNK_0000_0769";
1162 case 0x0000076a: return "SILV_UNK_0000_076a";
1163 case 0x0000076b: return "SILV_UNK_0000_076b";
1164 case 0x0000076c: return "SILV_UNK_0000_076c";
1165 case 0x0000076d: return "SILV_UNK_0000_076d";
1166 case 0x0000076e: return "SILV_UNK_0000_076e";
1167
1168 case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
1169 case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1170 case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1171 case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
1172
1173 /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
1174 case 0x00001000: return "P6_DEBUG_REGISTER_0";
1175 case 0x00001001: return "P6_DEBUG_REGISTER_1";
1176 case 0x00001002: return "P6_DEBUG_REGISTER_2";
1177 case 0x00001003: return "P6_DEBUG_REGISTER_3";
1178 case 0x00001004: return "P6_DEBUG_REGISTER_4";
1179 case 0x00001005: return "P6_DEBUG_REGISTER_5";
1180 case 0x00001006: return "P6_DEBUG_REGISTER_6";
1181 case 0x00001007: return "P6_DEBUG_REGISTER_7";
1182 case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
1183 case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
1184
1185 case 0x00001107: return "VIA_UNK_0000_1107";
1186 case 0x0000110f: return "VIA_UNK_0000_110f";
1187 case 0x00001153: return "VIA_UNK_0000_1153";
1188 case 0x00001200: return "VIA_UNK_0000_1200";
1189 case 0x00001201: return "VIA_UNK_0000_1201";
1190 case 0x00001202: return "VIA_UNK_0000_1202";
1191 case 0x00001203: return "VIA_UNK_0000_1203";
1192 case 0x00001204: return "VIA_UNK_0000_1204";
1193 case 0x00001205: return "VIA_UNK_0000_1205";
1194 case 0x00001206: return "VIA_ALT_VENDOR_EBX";
1195 case 0x00001207: return "VIA_ALT_VENDOR_ECDX";
1196 case 0x00001208: return "VIA_UNK_0000_1208";
1197 case 0x00001209: return "VIA_UNK_0000_1209";
1198 case 0x0000120a: return "VIA_UNK_0000_120a";
1199 case 0x0000120b: return "VIA_UNK_0000_120b";
1200 case 0x0000120c: return "VIA_UNK_0000_120c";
1201 case 0x0000120d: return "VIA_UNK_0000_120d";
1202 case 0x0000120e: return "VIA_UNK_0000_120e";
1203 case 0x0000120f: return "VIA_UNK_0000_120f";
1204 case 0x00001210: return "VIA_UNK_0000_1210";
1205 case 0x00001211: return "VIA_UNK_0000_1211";
1206 case 0x00001212: return "VIA_UNK_0000_1212";
1207 case 0x00001213: return "VIA_UNK_0000_1213";
1208 case 0x00001214: return "VIA_UNK_0000_1214";
1209 case 0x00001220: return "VIA_UNK_0000_1220";
1210 case 0x00001221: return "VIA_UNK_0000_1221";
1211 case 0x00001230: return "VIA_UNK_0000_1230";
1212 case 0x00001231: return "VIA_UNK_0000_1231";
1213 case 0x00001232: return "VIA_UNK_0000_1232";
1214 case 0x00001233: return "VIA_UNK_0000_1233";
1215 case 0x00001234: return "VIA_UNK_0000_1234";
1216 case 0x00001235: return "VIA_UNK_0000_1235";
1217 case 0x00001236: return "VIA_UNK_0000_1236";
1218 case 0x00001237: return "VIA_UNK_0000_1237";
1219 case 0x00001238: return "VIA_UNK_0000_1238";
1220 case 0x00001239: return "VIA_UNK_0000_1239";
1221 case 0x00001240: return "VIA_UNK_0000_1240";
1222 case 0x00001241: return "VIA_UNK_0000_1241";
1223 case 0x00001243: return "VIA_UNK_0000_1243";
1224 case 0x00001245: return "VIA_UNK_0000_1245";
1225 case 0x00001246: return "VIA_UNK_0000_1246";
1226 case 0x00001247: return "VIA_UNK_0000_1247";
1227 case 0x00001248: return "VIA_UNK_0000_1248";
1228 case 0x00001249: return "VIA_UNK_0000_1249";
1229 case 0x0000124a: return "VIA_UNK_0000_124a";
1230
1231 case 0x00001301: return "VIA_UNK_0000_1301";
1232 case 0x00001302: return "VIA_UNK_0000_1302";
1233 case 0x00001303: return "VIA_UNK_0000_1303";
1234 case 0x00001304: return "VIA_UNK_0000_1304";
1235 case 0x00001305: return "VIA_UNK_0000_1305";
1236 case 0x00001306: return "VIA_UNK_0000_1306";
1237 case 0x00001307: return "VIA_UNK_0000_1307";
1238 case 0x00001308: return "VIA_UNK_0000_1308";
1239 case 0x00001309: return "VIA_UNK_0000_1309";
1240 case 0x0000130d: return "VIA_UNK_0000_130d";
1241 case 0x0000130e: return "VIA_UNK_0000_130e";
1242 case 0x00001312: return "VIA_UNK_0000_1312";
1243 case 0x00001315: return "VIA_UNK_0000_1315";
1244 case 0x00001317: return "VIA_UNK_0000_1317";
1245 case 0x00001318: return "VIA_UNK_0000_1318";
1246 case 0x0000131a: return "VIA_UNK_0000_131a";
1247 case 0x0000131b: return "VIA_UNK_0000_131b";
1248 case 0x00001402: return "VIA_UNK_0000_1402";
1249 case 0x00001403: return "VIA_UNK_0000_1403";
1250 case 0x00001404: return "VIA_UNK_0000_1404";
1251 case 0x00001405: return "VIA_UNK_0000_1405";
1252 case 0x00001406: return "VIA_UNK_0000_1406";
1253 case 0x00001407: return "VIA_UNK_0000_1407";
1254 case 0x00001410: return "VIA_UNK_0000_1410";
1255 case 0x00001411: return "VIA_UNK_0000_1411";
1256 case 0x00001412: return "VIA_UNK_0000_1412";
1257 case 0x00001413: return "VIA_UNK_0000_1413";
1258 case 0x00001414: return "VIA_UNK_0000_1414";
1259 case 0x00001415: return "VIA_UNK_0000_1415";
1260 case 0x00001416: return "VIA_UNK_0000_1416";
1261 case 0x00001417: return "VIA_UNK_0000_1417";
1262 case 0x00001418: return "VIA_UNK_0000_1418";
1263 case 0x00001419: return "VIA_UNK_0000_1419";
1264 case 0x0000141a: return "VIA_UNK_0000_141a";
1265 case 0x0000141b: return "VIA_UNK_0000_141b";
1266 case 0x0000141c: return "VIA_UNK_0000_141c";
1267 case 0x0000141d: return "VIA_UNK_0000_141d";
1268 case 0x0000141e: return "VIA_UNK_0000_141e";
1269 case 0x0000141f: return "VIA_UNK_0000_141f";
1270 case 0x00001420: return "VIA_UNK_0000_1420";
1271 case 0x00001421: return "VIA_UNK_0000_1421";
1272 case 0x00001422: return "VIA_UNK_0000_1422";
1273 case 0x00001423: return "VIA_UNK_0000_1423";
1274 case 0x00001424: return "VIA_UNK_0000_1424";
1275 case 0x00001425: return "VIA_UNK_0000_1425";
1276 case 0x00001426: return "VIA_UNK_0000_1426";
1277 case 0x00001427: return "VIA_UNK_0000_1427";
1278 case 0x00001428: return "VIA_UNK_0000_1428";
1279 case 0x00001429: return "VIA_UNK_0000_1429";
1280 case 0x0000142a: return "VIA_UNK_0000_142a";
1281 case 0x0000142b: return "VIA_UNK_0000_142b";
1282 case 0x0000142c: return "VIA_UNK_0000_142c";
1283 case 0x0000142d: return "VIA_UNK_0000_142d";
1284 case 0x0000142e: return "VIA_UNK_0000_142e";
1285 case 0x0000142f: return "VIA_UNK_0000_142f";
1286 case 0x00001434: return "VIA_UNK_0000_1434";
1287 case 0x00001435: return "VIA_UNK_0000_1435";
1288 case 0x00001436: return "VIA_UNK_0000_1436";
1289 case 0x00001437: return "VIA_UNK_0000_1437";
1290 case 0x00001438: return "VIA_UNK_0000_1438";
1291 case 0x0000143a: return "VIA_UNK_0000_143a";
1292 case 0x0000143c: return "VIA_UNK_0000_143c";
1293 case 0x0000143d: return "VIA_UNK_0000_143d";
1294 case 0x00001440: return "VIA_UNK_0000_1440";
1295 case 0x00001441: return "VIA_UNK_0000_1441";
1296 case 0x00001442: return "VIA_UNK_0000_1442";
1297 case 0x00001449: return "VIA_UNK_0000_1449";
1298 case 0x00001450: return "VIA_UNK_0000_1450";
1299 case 0x00001451: return "VIA_UNK_0000_1451";
1300 case 0x00001452: return "VIA_UNK_0000_1452";
1301 case 0x00001453: return "VIA_UNK_0000_1453";
1302 case 0x00001460: return "VIA_UNK_0000_1460";
1303 case 0x00001461: return "VIA_UNK_0000_1461";
1304 case 0x00001462: return "VIA_UNK_0000_1462";
1305 case 0x00001463: return "VIA_UNK_0000_1463";
1306 case 0x00001465: return "VIA_UNK_0000_1465";
1307 case 0x00001466: return "VIA_UNK_0000_1466";
1308 case 0x00001470: return "VIA_UNK_0000_1470";
1309 case 0x00001471: return "VIA_UNK_0000_1471";
1310 case 0x00001480: return "VIA_UNK_0000_1480";
1311 case 0x00001481: return "VIA_UNK_0000_1481";
1312 case 0x00001482: return "VIA_UNK_0000_1482";
1313 case 0x00001483: return "VIA_UNK_0000_1483";
1314 case 0x00001484: return "VIA_UNK_0000_1484";
1315 case 0x00001485: return "VIA_UNK_0000_1485";
1316 case 0x00001486: return "VIA_UNK_0000_1486";
1317 case 0x00001490: return "VIA_UNK_0000_1490";
1318 case 0x00001491: return "VIA_UNK_0000_1491";
1319 case 0x00001492: return "VIA_UNK_0000_1492";
1320 case 0x00001493: return "VIA_UNK_0000_1493";
1321 case 0x00001494: return "VIA_UNK_0000_1494";
1322 case 0x00001495: return "VIA_UNK_0000_1495";
1323 case 0x00001496: return "VIA_UNK_0000_1496";
1324 case 0x00001497: return "VIA_UNK_0000_1497";
1325 case 0x00001498: return "VIA_UNK_0000_1498";
1326 case 0x00001499: return "VIA_UNK_0000_1499";
1327 case 0x0000149a: return "VIA_UNK_0000_149a";
1328 case 0x0000149b: return "VIA_UNK_0000_149b";
1329 case 0x0000149c: return "VIA_UNK_0000_149c";
1330 case 0x0000149f: return "VIA_UNK_0000_149f";
1331 case 0x00001523: return "VIA_UNK_0000_1523";
1332
1333 case 0x00002000: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR0" : NULL;
1334 case 0x00002002: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR2" : NULL;
1335 case 0x00002003: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR3" : NULL;
1336 case 0x00002004: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR4" : NULL;
1337 case 0x0000203f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_203f" /* P6_M_Dothan. */ : NULL;
1338 case 0x000020cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_20cd" /* P6_M_Dothan. */ : NULL;
1339 case 0x0000303f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_303f" /* P6_M_Dothan. */ : NULL;
1340 case 0x000030cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_30cd" /* P6_M_Dothan. */ : NULL;
1341
1342 case 0x0000317a: return "VIA_UNK_0000_317a";
1343 case 0x0000317b: return "VIA_UNK_0000_317b";
1344 case 0x0000317d: return "VIA_UNK_0000_317d";
1345 case 0x0000317e: return "VIA_UNK_0000_317e";
1346 case 0x0000317f: return "VIA_UNK_0000_317f";
1347 case 0x80000198: return "VIA_UNK_8000_0198";
1348
1349 case 0xc0000080: return "AMD64_EFER";
1350 case 0xc0000081: return "AMD64_STAR";
1351 case 0xc0000082: return "AMD64_STAR64";
1352 case 0xc0000083: return "AMD64_STARCOMPAT";
1353 case 0xc0000084: return "AMD64_SYSCALL_FLAG_MASK";
1354 case 0xc0000100: return "AMD64_FS_BASE";
1355 case 0xc0000101: return "AMD64_GS_BASE";
1356 case 0xc0000102: return "AMD64_KERNEL_GS_BASE";
1357 case 0xc0000103: return "AMD64_TSC_AUX";
1358 case 0xc0000104: return "AMD_15H_TSC_RATE";
1359 case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
1360 case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
1361 case 0xc0000408: return "AMD_10H_MC4_MISC1";
1362 case 0xc0000409: return "AMD_10H_MC4_MISC2";
1363 case 0xc000040a: return "AMD_10H_MC4_MISC3";
1364 case 0xc000040b: return "AMD_10H_MC4_MISC4";
1365 case 0xc000040c: return "AMD_10H_MC4_MISC5";
1366 case 0xc000040d: return "AMD_10H_MC4_MISC6";
1367 case 0xc000040e: return "AMD_10H_MC4_MISC7";
1368 case 0xc000040f: return "AMD_10H_MC4_MISC8";
1369 case 0xc0010000: return "AMD_K8_PERF_CTL_0";
1370 case 0xc0010001: return "AMD_K8_PERF_CTL_1";
1371 case 0xc0010002: return "AMD_K8_PERF_CTL_2";
1372 case 0xc0010003: return "AMD_K8_PERF_CTL_3";
1373 case 0xc0010004: return "AMD_K8_PERF_CTR_0";
1374 case 0xc0010005: return "AMD_K8_PERF_CTR_1";
1375 case 0xc0010006: return "AMD_K8_PERF_CTR_2";
1376 case 0xc0010007: return "AMD_K8_PERF_CTR_3";
1377 case 0xc0010010: return "AMD_K8_SYS_CFG";
1378 case 0xc0010015: return "AMD_K8_HW_CFG";
1379 case 0xc0010016: return "AMD_K8_IORR_BASE_0";
1380 case 0xc0010017: return "AMD_K8_IORR_MASK_0";
1381 case 0xc0010018: return "AMD_K8_IORR_BASE_1";
1382 case 0xc0010019: return "AMD_K8_IORR_MASK_1";
1383 case 0xc001001a: return "AMD_K8_TOP_MEM";
1384 case 0xc001001d: return "AMD_K8_TOP_MEM2";
1385 case 0xc001001e: return "AMD_K8_MANID";
1386 case 0xc001001f: return "AMD_K8_NB_CFG1";
1387 case 0xc0010020: return "AMD_K8_PATCH_LOADER";
1388 case 0xc0010021: return "AMD_K8_UNK_c001_0021";
1389 case 0xc0010022: return "AMD_K8_MC_XCPT_REDIR";
1390 case 0xc0010028: return "AMD_K8_UNK_c001_0028";
1391 case 0xc0010029: return "AMD_K8_UNK_c001_0029";
1392 case 0xc001002a: return "AMD_K8_UNK_c001_002a";
1393 case 0xc001002b: return "AMD_K8_UNK_c001_002b";
1394 case 0xc001002c: return "AMD_K8_UNK_c001_002c";
1395 case 0xc001002d: return "AMD_K8_UNK_c001_002d";
1396 case 0xc0010030: return "AMD_K8_CPU_NAME_0";
1397 case 0xc0010031: return "AMD_K8_CPU_NAME_1";
1398 case 0xc0010032: return "AMD_K8_CPU_NAME_2";
1399 case 0xc0010033: return "AMD_K8_CPU_NAME_3";
1400 case 0xc0010034: return "AMD_K8_CPU_NAME_4";
1401 case 0xc0010035: return "AMD_K8_CPU_NAME_5";
1402 case 0xc001003e: return "AMD_K8_HTC";
1403 case 0xc001003f: return "AMD_K8_STC";
1404 case 0xc0010041: return "AMD_K8_FIDVID_CTL";
1405 case 0xc0010042: return "AMD_K8_FIDVID_STATUS";
1406 case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
1407 case 0xc0010044: return "AMD_K8_MC_CTL_MASK_0";
1408 case 0xc0010045: return "AMD_K8_MC_CTL_MASK_1";
1409 case 0xc0010046: return "AMD_K8_MC_CTL_MASK_2";
1410 case 0xc0010047: return "AMD_K8_MC_CTL_MASK_3";
1411 case 0xc0010048: return "AMD_K8_MC_CTL_MASK_4";
1412 case 0xc0010049: return "AMD_K8_MC_CTL_MASK_5";
1413 case 0xc001004a: return "AMD_K8_MC_CTL_MASK_6";
1414 //case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
1415 case 0xc0010050: return "AMD_K8_SMI_ON_IO_TRAP_0";
1416 case 0xc0010051: return "AMD_K8_SMI_ON_IO_TRAP_1";
1417 case 0xc0010052: return "AMD_K8_SMI_ON_IO_TRAP_2";
1418 case 0xc0010053: return "AMD_K8_SMI_ON_IO_TRAP_3";
1419 case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
1420 case 0xc0010055: return "AMD_K8_INT_PENDING_MSG";
1421 case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
1422 case 0xc0010057: return "AMD_10H_UNK_c001_0057";
1423 case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
1424 case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
1425 case 0xc001005a: return "AMD_10H_UNK_c001_005a";
1426 case 0xc001005b: return "AMD_10H_UNK_c001_005b";
1427 case 0xc001005c: return "AMD_10H_UNK_c001_005c";
1428 case 0xc001005d: return "AMD_10H_UNK_c001_005d";
1429 case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
1430 case 0xc0010061: return "AMD_10H_P_ST_CUR_LIM";
1431 case 0xc0010062: return "AMD_10H_P_ST_CTL";
1432 case 0xc0010063: return "AMD_10H_P_ST_STS";
1433 case 0xc0010064: return "AMD_10H_P_ST_0";
1434 case 0xc0010065: return "AMD_10H_P_ST_1";
1435 case 0xc0010066: return "AMD_10H_P_ST_2";
1436 case 0xc0010067: return "AMD_10H_P_ST_3";
1437 case 0xc0010068: return "AMD_10H_P_ST_4";
1438 case 0xc0010069: return "AMD_10H_P_ST_5";
1439 case 0xc001006a: return "AMD_10H_P_ST_6";
1440 case 0xc001006b: return "AMD_10H_P_ST_7";
1441 case 0xc0010070: return "AMD_10H_COFVID_CTL";
1442 case 0xc0010071: return "AMD_10H_COFVID_STS";
1443 case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
1444 case 0xc0010074: return "AMD_10H_CPU_WD_TMR_CFG";
1445 // case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
1446 // case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
1447 // case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
1448 // case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
1449 // case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
1450 // case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
1451 case 0xc0010111: return "AMD_K8_SMM_BASE";
1452 case 0xc0010112: return "AMD_K8_SMM_ADDR";
1453 case 0xc0010113: return "AMD_K8_SMM_MASK";
1454 case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_CR" : "AMD_K8_UNK_c001_0114";
1455 case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_IGNNE" : "AMD_K8_UNK_c001_0115";
1456 case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_SMM_CTL" : "AMD_K8_UNK_c001_0116";
1457 case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_HSAVE_PA" : "AMD_K8_UNK_c001_0117";
1458 case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_10H_VM_LOCK_KEY" : "AMD_K8_UNK_c001_0118";
1459 case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_SSM_LOCK_KEY" : "AMD_K8_UNK_c001_0119";
1460 case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_LOCAL_SMI_STS" : "AMD_K8_UNK_c001_011a";
1461 case 0xc001011b: return "AMD_K8_UNK_c001_011b";
1462 case 0xc001011c: return "AMD_K8_UNK_c001_011c";
1463 case 0xc0010140: return "AMD_10H_OSVW_ID_LEN";
1464 case 0xc0010141: return "AMD_10H_OSVW_STS";
1465 case 0xc0010200: return "AMD_K8_PERF_CTL_0";
1466 case 0xc0010202: return "AMD_K8_PERF_CTL_1";
1467 case 0xc0010204: return "AMD_K8_PERF_CTL_2";
1468 case 0xc0010206: return "AMD_K8_PERF_CTL_3";
1469 case 0xc0010208: return "AMD_K8_PERF_CTL_4";
1470 case 0xc001020a: return "AMD_K8_PERF_CTL_5";
1471 //case 0xc001020c: return "AMD_K8_PERF_CTL_6";
1472 //case 0xc001020e: return "AMD_K8_PERF_CTL_7";
1473 case 0xc0010201: return "AMD_K8_PERF_CTR_0";
1474 case 0xc0010203: return "AMD_K8_PERF_CTR_1";
1475 case 0xc0010205: return "AMD_K8_PERF_CTR_2";
1476 case 0xc0010207: return "AMD_K8_PERF_CTR_3";
1477 case 0xc0010209: return "AMD_K8_PERF_CTR_4";
1478 case 0xc001020b: return "AMD_K8_PERF_CTR_5";
1479 //case 0xc001020d: return "AMD_K8_PERF_CTR_6";
1480 //case 0xc001020f: return "AMD_K8_PERF_CTR_7";
1481 case 0xc0010230: return "AMD_16H_L2I_PERF_CTL_0";
1482 case 0xc0010232: return "AMD_16H_L2I_PERF_CTL_1";
1483 case 0xc0010234: return "AMD_16H_L2I_PERF_CTL_2";
1484 case 0xc0010236: return "AMD_16H_L2I_PERF_CTL_3";
1485 //case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
1486 //case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
1487 //case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
1488 //case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
1489 case 0xc0010231: return "AMD_16H_L2I_PERF_CTR_0";
1490 case 0xc0010233: return "AMD_16H_L2I_PERF_CTR_1";
1491 case 0xc0010235: return "AMD_16H_L2I_PERF_CTR_2";
1492 case 0xc0010237: return "AMD_16H_L2I_PERF_CTR_3";
1493 //case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
1494 //case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
1495 //case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
1496 //case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
1497 case 0xc0010240: return "AMD_15H_NB_PERF_CTL_0";
1498 case 0xc0010242: return "AMD_15H_NB_PERF_CTL_1";
1499 case 0xc0010244: return "AMD_15H_NB_PERF_CTL_2";
1500 case 0xc0010246: return "AMD_15H_NB_PERF_CTL_3";
1501 //case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
1502 //case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
1503 //case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
1504 //case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
1505 case 0xc0010241: return "AMD_15H_NB_PERF_CTR_0";
1506 case 0xc0010243: return "AMD_15H_NB_PERF_CTR_1";
1507 case 0xc0010245: return "AMD_15H_NB_PERF_CTR_2";
1508 case 0xc0010247: return "AMD_15H_NB_PERF_CTR_3";
1509 //case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
1510 //case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
1511 //case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
1512 //case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
1513 case 0xc0011000: return "AMD_K7_MCODE_CTL";
1514 case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
1515 case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
1516 case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
1517 case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
1518 case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
1519 case 0xc0011006: return "AMD_K7_DEBUG_STS?";
1520 case 0xc0011007: return "AMD_K7_BH_TRACE_BASE?";
1521 case 0xc0011008: return "AMD_K7_BH_TRACE_PTR?";
1522 case 0xc0011009: return "AMD_K7_BH_TRACE_LIM?";
1523 case 0xc001100a: return "AMD_K7_HDT_CFG?";
1524 case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
1525 case 0xc001100c: return "AMD_K7_NODE_ID";
1526 case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
1527 case 0xc001100e: return "AMD_K8_WRMSR_BP?";
1528 case 0xc001100f: return "AMD_K8_WRMSR_BP_MASK?";
1529 case 0xc0011010: return "AMD_K8_BH_TRACE_CTL?";
1530 case 0xc0011011: return "AMD_K8_BH_TRACE_USRD?";
1531 case 0xc0011012: return "AMD_K7_UNK_c001_1012";
1532 case 0xc0011013: return "AMD_K7_UNK_c001_1013";
1533 case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
1534 case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
1535 case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
1536 case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
1537 case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
1538 case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
1539 case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
1540 case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
1541 case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
1542 case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
1543 case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
1544 case 0xc0011020: return "AMD_K7_LS_CFG";
1545 case 0xc0011021: return "AMD_K7_IC_CFG";
1546 case 0xc0011022: return "AMD_K7_DC_CFG";
1547 case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
1548 case 0xc0011024: return "AMD_K7_DEBUG_CTL_2?";
1549 case 0xc0011025: return "AMD_K7_DR0_DATA_MATCH?";
1550 case 0xc0011026: return "AMD_K7_DR0_DATA_MATCH?";
1551 case 0xc0011027: return "AMD_K7_DR0_ADDR_MASK";
1552 case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
1553 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
1554 : NULL;
1555 case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
1556 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
1557 : NULL;
1558 case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
1559 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
1560 ? "AMD_10H_BU_CFG2" /* 10h & 16h */ : NULL;
1561 case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
1562 case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
1563 case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
1564 case 0xc0011030: return "AMD_10H_IBS_FETCH_CTL";
1565 case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
1566 case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
1567 case 0xc0011033: return "AMD_10H_IBS_OP_EXEC_CTL";
1568 case 0xc0011034: return "AMD_10H_IBS_OP_RIP";
1569 case 0xc0011035: return "AMD_10H_IBS_OP_DATA";
1570 case 0xc0011036: return "AMD_10H_IBS_OP_DATA2";
1571 case 0xc0011037: return "AMD_10H_IBS_OP_DATA3";
1572 case 0xc0011038: return "AMD_10H_IBS_DC_LIN_ADDR";
1573 case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
1574 case 0xc001103a: return "AMD_10H_IBS_CTL";
1575 case 0xc001103b: return "AMD_14H_IBS_BR_TARGET";
1576
1577 case 0xc0011040: return "AMD_15H_UNK_c001_1040";
1578 case 0xc0011041: return "AMD_15H_UNK_c001_1041";
1579 case 0xc0011042: return "AMD_15H_UNK_c001_1042";
1580 case 0xc0011043: return "AMD_15H_UNK_c001_1043";
1581 case 0xc0011044: return "AMD_15H_UNK_c001_1044";
1582 case 0xc0011045: return "AMD_15H_UNK_c001_1045";
1583 case 0xc0011046: return "AMD_15H_UNK_c001_1046";
1584 case 0xc0011047: return "AMD_15H_UNK_c001_1047";
1585 case 0xc0011048: return "AMD_15H_UNK_c001_1048";
1586 case 0xc0011049: return "AMD_15H_UNK_c001_1049";
1587 case 0xc001104a: return "AMD_15H_UNK_c001_104a";
1588 case 0xc001104b: return "AMD_15H_UNK_c001_104b";
1589 case 0xc001104c: return "AMD_15H_UNK_c001_104c";
1590 case 0xc001104d: return "AMD_15H_UNK_c001_104d";
1591 case 0xc001104e: return "AMD_15H_UNK_c001_104e";
1592 case 0xc001104f: return "AMD_15H_UNK_c001_104f";
1593 case 0xc0011050: return "AMD_15H_UNK_c001_1050";
1594 case 0xc0011051: return "AMD_15H_UNK_c001_1051";
1595 case 0xc0011052: return "AMD_15H_UNK_c001_1052";
1596 case 0xc0011053: return "AMD_15H_UNK_c001_1053";
1597 case 0xc0011054: return "AMD_15H_UNK_c001_1054";
1598 case 0xc0011055: return "AMD_15H_UNK_c001_1055";
1599 case 0xc0011056: return "AMD_15H_UNK_c001_1056";
1600 case 0xc0011057: return "AMD_15H_UNK_c001_1057";
1601 case 0xc0011058: return "AMD_15H_UNK_c001_1058";
1602 case 0xc0011059: return "AMD_15H_UNK_c001_1059";
1603 case 0xc001105a: return "AMD_15H_UNK_c001_105a";
1604 case 0xc001105b: return "AMD_15H_UNK_c001_105b";
1605 case 0xc001105c: return "AMD_15H_UNK_c001_105c";
1606 case 0xc001105d: return "AMD_15H_UNK_c001_105d";
1607 case 0xc001105e: return "AMD_15H_UNK_c001_105e";
1608 case 0xc001105f: return "AMD_15H_UNK_c001_105f";
1609 case 0xc0011060: return "AMD_15H_UNK_c001_1060";
1610 case 0xc0011061: return "AMD_15H_UNK_c001_1061";
1611 case 0xc0011062: return "AMD_15H_UNK_c001_1062";
1612 case 0xc0011063: return "AMD_15H_UNK_c001_1063";
1613 case 0xc0011064: return "AMD_15H_UNK_c001_1064";
1614 case 0xc0011065: return "AMD_15H_UNK_c001_1065";
1615 case 0xc0011066: return "AMD_15H_UNK_c001_1066";
1616 case 0xc0011067: return "AMD_15H_UNK_c001_1067";
1617 case 0xc0011068: return "AMD_15H_UNK_c001_1068";
1618 case 0xc0011069: return "AMD_15H_UNK_c001_1069";
1619 case 0xc001106a: return "AMD_15H_UNK_c001_106a";
1620 case 0xc001106b: return "AMD_15H_UNK_c001_106b";
1621 case 0xc001106c: return "AMD_15H_UNK_c001_106c";
1622 case 0xc001106d: return "AMD_15H_UNK_c001_106d";
1623 case 0xc001106e: return "AMD_15H_UNK_c001_106e";
1624 case 0xc001106f: return "AMD_15H_UNK_c001_106f";
1625 case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
1626 case 0xc0011071: return "AMD_15H_UNK_c001_1071";
1627 case 0xc0011072: return "AMD_15H_UNK_c001_1072";
1628 case 0xc0011073: return "AMD_15H_UNK_c001_1073";
1629 case 0xc0011080: return "AMD_15H_UNK_c001_1080";
1630 }
1631
1632 /*
1633 * Uncore stuff on Sandy. Putting it here to avoid ugly microarch checks for each register.
1634 * Note! These are found on model 42 (2a) but not 45 (2d), the latter is the EP variant.
1635 */
1636 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
1637 switch (uMsr)
1638 {
1639 case 0x00000700: return "MSR_UNC_CBO_0_PERFEVTSEL0";
1640 case 0x00000701: return "MSR_UNC_CBO_0_PERFEVTSEL1";
1641 case 0x00000702: return "MSR_UNC_CBO_0_PERFEVTSEL2?";
1642 case 0x00000703: return "MSR_UNC_CBO_0_PERFEVTSEL3?";
1643 case 0x00000704: return "MSR_UNC_CBO_0_UNK_4";
1644 case 0x00000705: return "MSR_UNC_CBO_0_UNK_5";
1645 case 0x00000706: return "MSR_UNC_CBO_0_PER_CTR0";
1646 case 0x00000707: return "MSR_UNC_CBO_0_PER_CTR1";
1647 case 0x00000708: return "MSR_UNC_CBO_0_PER_CTR2?";
1648 case 0x00000709: return "MSR_UNC_CBO_0_PER_CTR3?";
1649 case 0x00000710: return "MSR_UNC_CBO_1_PERFEVTSEL0";
1650 case 0x00000711: return "MSR_UNC_CBO_1_PERFEVTSEL1";
1651 case 0x00000712: return "MSR_UNC_CBO_1_PERFEVTSEL2?";
1652 case 0x00000713: return "MSR_UNC_CBO_1_PERFEVTSEL3?";
1653 case 0x00000714: return "MSR_UNC_CBO_1_UNK_4";
1654 case 0x00000715: return "MSR_UNC_CBO_1_UNK_5";
1655 case 0x00000716: return "MSR_UNC_CBO_1_PER_CTR0";
1656 case 0x00000717: return "MSR_UNC_CBO_1_PER_CTR1";
1657 case 0x00000718: return "MSR_UNC_CBO_1_PER_CTR2?";
1658 case 0x00000719: return "MSR_UNC_CBO_1_PER_CTR3?";
1659 case 0x00000720: return "MSR_UNC_CBO_2_PERFEVTSEL0";
1660 case 0x00000721: return "MSR_UNC_CBO_2_PERFEVTSEL1";
1661 case 0x00000722: return "MSR_UNC_CBO_2_PERFEVTSEL2?";
1662 case 0x00000723: return "MSR_UNC_CBO_2_PERFEVTSEL3?";
1663 case 0x00000724: return "MSR_UNC_CBO_2_UNK_4";
1664 case 0x00000725: return "MSR_UNC_CBO_2_UNK_5";
1665 case 0x00000726: return "MSR_UNC_CBO_2_PER_CTR0";
1666 case 0x00000727: return "MSR_UNC_CBO_2_PER_CTR1";
1667 case 0x00000728: return "MSR_UNC_CBO_2_PER_CTR2?";
1668 case 0x00000729: return "MSR_UNC_CBO_2_PER_CTR3?";
1669 case 0x00000730: return "MSR_UNC_CBO_3_PERFEVTSEL0";
1670 case 0x00000731: return "MSR_UNC_CBO_3_PERFEVTSEL1";
1671 case 0x00000732: return "MSR_UNC_CBO_3_PERFEVTSEL2?";
1672 case 0x00000733: return "MSR_UNC_CBO_3_PERFEVTSEL3?";
1673 case 0x00000734: return "MSR_UNC_CBO_3_UNK_4";
1674 case 0x00000735: return "MSR_UNC_CBO_3_UNK_5";
1675 case 0x00000736: return "MSR_UNC_CBO_3_PER_CTR0";
1676 case 0x00000737: return "MSR_UNC_CBO_3_PER_CTR1";
1677 case 0x00000738: return "MSR_UNC_CBO_3_PER_CTR2?";
1678 case 0x00000739: return "MSR_UNC_CBO_3_PER_CTR3?";
1679 case 0x00000740: return "MSR_UNC_CBO_4_PERFEVTSEL0?";
1680 case 0x00000741: return "MSR_UNC_CBO_4_PERFEVTSEL1?";
1681 case 0x00000742: return "MSR_UNC_CBO_4_PERFEVTSEL2?";
1682 case 0x00000743: return "MSR_UNC_CBO_4_PERFEVTSEL3?";
1683 case 0x00000744: return "MSR_UNC_CBO_4_UNK_4";
1684 case 0x00000745: return "MSR_UNC_CBO_4_UNK_5";
1685 case 0x00000746: return "MSR_UNC_CBO_4_PER_CTR0?";
1686 case 0x00000747: return "MSR_UNC_CBO_4_PER_CTR1?";
1687 case 0x00000748: return "MSR_UNC_CBO_4_PER_CTR2?";
1688 case 0x00000749: return "MSR_UNC_CBO_4_PER_CTR3?";
1689
1690 }
1691
1692 /*
1693 * Bunch of unknown sandy bridge registers. They might seem like the
1694 * nehalem based xeon stuff, but the layout doesn't match. I bet it's the
1695 * same kind of registes though (i.e. uncore (UNC)).
1696 *
1697 * Kudos to Intel for keeping these a secret! Many thanks guys!!
1698 */
1699 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
1700 switch (uMsr)
1701 {
1702 case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
1703 case 0x00000a02: return "I7_SB_UNK_0000_0a02";
1704 case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
1705 case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
1706 case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
1707 case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
1708 case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
1709 case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
1710 case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
1711 case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
1712 case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
1713 case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
1714 case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
1715 case 0x00000d04: return "I7_SB_UNK_0000_0d04";
1716 case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
1717 case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
1718 case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
1719 case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
1720 case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
1721 case 0x00000d24: return "I7_SB_UNK_0000_0d24";
1722 case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
1723 case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
1724 case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
1725 case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
1726 case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
1727 case 0x00000d44: return "I7_SB_UNK_0000_0d44";
1728 case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
1729 case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
1730 case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
1731 case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
1732 case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
1733 case 0x00000d64: return "I7_SB_UNK_0000_0d64";
1734 case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
1735 case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
1736 case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
1737 case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
1738 case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
1739 case 0x00000d84: return "I7_SB_UNK_0000_0d84";
1740 case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
1741 case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
1742 case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
1743 case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
1744 case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
1745 case 0x00000da4: return "I7_SB_UNK_0000_0da4";
1746 case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
1747 case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
1748 case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
1749 case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
1750 case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
1751 }
1752
1753 /*
1754 * Ditto for ivy bridge (observed on the i5-3570). There are some haswell
1755 * and sandybridge related docs on registers in this ares, but either
1756 * things are different for ivy or they're very incomplete. Again, kudos
1757 * to intel!
1758 */
1759 if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
1760 switch (uMsr)
1761 {
1762 case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
1763 case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
1764 case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
1765 case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
1766 case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
1767 case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
1768 case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
1769 case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
1770 case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
1771 case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
1772 case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
1773 case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
1774 case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
1775 case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
1776 case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
1777 case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
1778 case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
1779 case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
1780 case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
1781 case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
1782 case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
1783 case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
1784 case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
1785 case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
1786 case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
1787
1788 }
1789 return NULL;
1790}
1791
1792
1793/**
1794 * Gets the name of an MSR.
1795 *
1796 * This may return a static buffer, so the content should only be considered
1797 * valid until the next time this function is called!.
1798 *
1799 * @returns MSR name.
1800 * @param uMsr The MSR in question.
1801 */
1802static const char *getMsrName(uint32_t uMsr)
1803{
1804 const char *pszReadOnly = getMsrNameHandled(uMsr);
1805 if (pszReadOnly)
1806 return pszReadOnly;
1807
1808 /*
1809 * This MSR needs looking into, return a TODO_XXXX_XXXX name.
1810 */
1811 static char s_szBuf[32];
1812 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1813 return s_szBuf;
1814}
1815
1816
1817
1818/**
1819 * Gets the name of an MSR range.
1820 *
1821 * This may return a static buffer, so the content should only be considered
1822 * valid until the next time this function is called!.
1823 *
1824 * @returns MSR name.
1825 * @param uMsr The first MSR in the range.
1826 */
1827static const char *getMsrRangeName(uint32_t uMsr)
1828{
1829 switch (uMsr)
1830 {
1831 case 0x00000040:
1832 return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
1833 case 0x00000060:
1834 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
1835 return "MSR_LASTBRANCH_n_TO_IP";
1836 break;
1837
1838 case 0x000003f8:
1839 case 0x000003f9:
1840 case 0x000003fa:
1841 return "I7_MSR_PKG_Cn_RESIDENCY";
1842 case 0x000003fc:
1843 case 0x000003fd:
1844 case 0x000003fe:
1845 return "I7_MSR_CORE_Cn_RESIDENCY";
1846
1847 case 0x00000400:
1848 return "IA32_MCi_CTL_STATUS_ADDR_MISC";
1849
1850 case 0x00000680:
1851 return "MSR_LASTBRANCH_n_FROM_IP";
1852 case 0x000006c0:
1853 return "MSR_LASTBRANCH_n_TO_IP";
1854
1855 case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
1856 case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
1857 case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
1858 case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
1859 return "IA32_X2APIC_n";
1860 }
1861
1862 static char s_szBuf[96];
1863 const char *pszReadOnly = getMsrNameHandled(uMsr);
1864 if (pszReadOnly)
1865 {
1866 /*
1867 * Replace the last char with 'n'.
1868 */
1869 RTStrCopy(s_szBuf, sizeof(s_szBuf), pszReadOnly);
1870 size_t off = strlen(s_szBuf);
1871 if (off > 0)
1872 off--;
1873 if (off + 1 < sizeof(s_szBuf))
1874 {
1875 s_szBuf[off] = 'n';
1876 s_szBuf[off + 1] = '\0';
1877 }
1878 }
1879 else
1880 {
1881 /*
1882 * This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
1883 */
1884 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
1885 }
1886 return s_szBuf;
1887}
1888
1889
1890/**
1891 * Returns the function name for MSRs that have one or two.
1892 *
1893 * @returns Function name if applicable, NULL if not.
1894 * @param uMsr The MSR in question.
1895 * @param pfTakesValue Whether this MSR function takes a value or not.
1896 * Optional.
1897 */
1898static const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
1899{
1900 bool fTmp;
1901 if (!pfTakesValue)
1902 pfTakesValue = &fTmp;
1903
1904 *pfTakesValue = false;
1905
1906 switch (uMsr)
1907 {
1908 case 0x00000000: return "Ia32P5McAddr";
1909 case 0x00000001: return "Ia32P5McType";
1910 case 0x00000006:
1911 if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
1912 return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
1913 return "Ia32MonitorFilterLineSize";
1914 case 0x00000010: return "Ia32TimestampCounter";
1915 case 0x00000017: *pfTakesValue = true; return "Ia32PlatformId";
1916 case 0x0000001b: return "Ia32ApicBase";
1917 case 0x0000002a: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcHardPowerOn" : "IntelEblCrPowerOn";
1918 case 0x0000002b: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcSoftPowerOn" : NULL;
1919 case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL;
1920 //case 0x00000033: return "IntelTestCtl";
1921 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch)
1922 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch)
1923 ? "IntelI7SmiCount" : NULL;
1924 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7CoreThreadCount" : NULL;
1925 case 0x0000003a: return "Ia32FeatureControl";
1926
1927 case 0x00000040:
1928 case 0x00000041:
1929 case 0x00000042:
1930 case 0x00000043:
1931 case 0x00000044:
1932 case 0x00000045:
1933 case 0x00000046:
1934 case 0x00000047:
1935 return "IntelLastBranchFromToN";
1936
1937 case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AmdK8PatchLevel" : "Ia32BiosSignId";
1938 case 0x0000009b: return "Ia32SmmMonitorCtl";
1939
1940 case 0x000000a8:
1941 case 0x000000a9:
1942 case 0x000000aa:
1943 case 0x000000ab:
1944 case 0x000000ac:
1945 case 0x000000ad:
1946 *pfTakesValue = true;
1947 return "IntelCore2EmttmCrTablesN";
1948
1949 case 0x000000c1:
1950 case 0x000000c2:
1951 case 0x000000c3:
1952 case 0x000000c4:
1953 return "Ia32PmcN";
1954 case 0x000000c5:
1955 case 0x000000c6:
1956 case 0x000000c7:
1957 case 0x000000c8:
1958 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
1959 return "Ia32PmcN";
1960 return NULL;
1961
1962 case 0x000000cd: *pfTakesValue = true; return "IntelP6FsbFrequency";
1963 case 0x000000ce: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelPlatformInfo" : NULL;
1964 case 0x000000e2: return "IntelPkgCStConfigControl";
1965 case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
1966 case 0x000000e4: return "IntelPmgIoCaptureBase";
1967 case 0x000000e7: return "Ia32MPerf";
1968 case 0x000000e8: return "Ia32APerf";
1969 case 0x000000ee: return "IntelCore1ExtConfig";
1970 case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap";
1971 case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl";
1972 case 0x0000011e: *pfTakesValue = true; return "IntelBblCrCtl3";
1973
1974 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1975 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1976 ? "IntelCpuId1FeatureMaskEcdx" : NULL;
1977 case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
1978 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
1979 ? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1980 case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1981 ? "IntelCpuId1FeatureMaskEax" : NULL;
1982 case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1983 ? "IntelCpuId1FeatureMaskEcdx" : NULL;
1984 case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
1985 ? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
1986 case 0x0000013c: return "IntelI7SandyAesNiCtl";
1987 case 0x0000015f: return "IntelCore1DtsCalControl";
1988 case 0x00000174: return "Ia32SysEnterCs";
1989 case 0x00000175: return "Ia32SysEnterEsp";
1990 case 0x00000176: return "Ia32SysEnterEip";
1991 case 0x00000179: *pfTakesValue = true; return "Ia32McgCap";
1992 case 0x0000017a: return "Ia32McgStatus";
1993 case 0x0000017b: return "Ia32McgCtl";
1994 case 0x0000017f: return "IntelI7SandyErrorControl"; /* SandyBridge. */
1995 case 0x00000186: return "Ia32PerfEvtSelN";
1996 case 0x00000187: return "Ia32PerfEvtSelN";
1997 case 0x00000193: return /*g_fIntelNetBurst ? NULL :*/ NULL /* Core2_Penryn. */;
1998 case 0x00000194: if (g_fIntelNetBurst) break; *pfTakesValue = true; return "IntelFlexRatio";
1999 case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
2000 case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
2001 case 0x0000019a: *pfTakesValue = true; return "Ia32ClockModulation";
2002 case 0x0000019b: *pfTakesValue = true; return "Ia32ThermInterrupt";
2003 case 0x0000019c: *pfTakesValue = true; return "Ia32ThermStatus";
2004 case 0x0000019d: *pfTakesValue = true; return "Ia32Therm2Ctl";
2005 case 0x000001a0: *pfTakesValue = true; return "Ia32MiscEnable";
2006 case 0x000001a2: *pfTakesValue = true; return "IntelI7TemperatureTarget";
2007 case 0x000001a6: return "IntelI7MsrOffCoreResponseN";
2008 case 0x000001a7: return "IntelI7MsrOffCoreResponseN";
2009 case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /*"P6PicSensCfg"*/;
2010 case 0x000001ad: *pfTakesValue = true; return "IntelI7TurboRatioLimit"; /* SandyBridge+, Silvermount+ */
2011 case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
2012 case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
2013 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
2014 ? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
2015 case 0x000001d7: return g_fIntelNetBurst ? "P6LastIntFromIp" : NULL;
2016 case 0x000001d8: return g_fIntelNetBurst ? "P6LastIntToIp" : NULL;
2017 case 0x000001d9: return "Ia32DebugCtl";
2018 case 0x000001da: return g_fIntelNetBurst ? "IntelLastBranchTos" : NULL;
2019 case 0x000001db: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchFromIp";
2020 case 0x000001dc: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchToIp";
2021 case 0x000001dd: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntFromIp";
2022 case 0x000001de: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntToIp";
2023 case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
2024 case 0x000001f2: return "Ia32SmrrPhysBase";
2025 case 0x000001f3: return "Ia32SmrrPhysMask";
2026 case 0x000001f8: return "Ia32PlatformDcaCap";
2027 case 0x000001f9: return "Ia32CpuDcaCap";
2028 case 0x000001fa: return "Ia32Dca0Cap";
2029 case 0x000001fc: return "IntelI7PowerCtl";
2030
2031 case 0x00000200: case 0x00000202: case 0x00000204: case 0x00000206:
2032 case 0x00000208: case 0x0000020a: case 0x0000020c: case 0x0000020e:
2033 case 0x00000210: case 0x00000212: case 0x00000214: case 0x00000216:
2034 case 0x00000218: case 0x0000021a: case 0x0000021c: case 0x0000021e:
2035 return "Ia32MtrrPhysBaseN";
2036 case 0x00000201: case 0x00000203: case 0x00000205: case 0x00000207:
2037 case 0x00000209: case 0x0000020b: case 0x0000020d: case 0x0000020f:
2038 case 0x00000211: case 0x00000213: case 0x00000215: case 0x00000217:
2039 case 0x00000219: case 0x0000021b: case 0x0000021d: case 0x0000021f:
2040 return "Ia32MtrrPhysMaskN";
2041 case 0x00000250:
2042 case 0x00000258: case 0x00000259:
2043 case 0x00000268: case 0x00000269: case 0x0000026a: case 0x0000026b:
2044 case 0x0000026c: case 0x0000026d: case 0x0000026e: case 0x0000026f:
2045 return "Ia32MtrrFixed";
2046 case 0x00000277: *pfTakesValue = true; return "Ia32Pat";
2047
2048 case 0x00000280: case 0x00000281: case 0x00000282: case 0x00000283:
2049 case 0x00000284: case 0x00000285: case 0x00000286: case 0x00000287:
2050 case 0x00000288: case 0x00000289: case 0x0000028a: case 0x0000028b:
2051 case 0x0000028c: case 0x0000028d: case 0x0000028e: case 0x0000028f:
2052 case 0x00000290: case 0x00000291: case 0x00000292: case 0x00000293:
2053 case 0x00000294: case 0x00000295: //case 0x00000296: case 0x00000297:
2054 //case 0x00000298: case 0x00000299: case 0x0000029a: case 0x0000029b:
2055 //case 0x0000029c: case 0x0000029d: case 0x0000029e: case 0x0000029f:
2056 return "Ia32McNCtl2";
2057
2058 case 0x000002ff: return "Ia32MtrrDefType";
2059 //case 0x00000305: return g_fIntelNetBurst ? TODO : NULL;
2060 case 0x00000309: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2061 case 0x0000030a: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2062 case 0x0000030b: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
2063 case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
2064 /* Note! Lots of P4 MSR 0x00000360..0x00000371. */
2065 case 0x0000038d: return "Ia32FixedCtrCtrl";
2066 case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
2067 case 0x0000038f: return "Ia32PerfGlobalCtrl";
2068 case 0x00000390: return "Ia32PerfGlobalOvfCtrl";
2069 case 0x00000391: return "IntelI7UncPerfGlobalCtrl"; /* S,H,X */
2070 case 0x00000392: return "IntelI7UncPerfGlobalStatus"; /* S,H,X */
2071 case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
2072 case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */
2073 case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */
2074 case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */
2075 case 0x0000039c: return "IntelI7SandyPebsNumAlt";
2076 /* Note! Lots of P4 MSR 0x000003a0..0x000003e1. */
2077 case 0x000003b0: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
2078 case 0x000003b1: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
2079 case 0x000003b2: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
2080 case 0x000003b3: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
2081 case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
2082 return g_fIntelNetBurst ? NULL : "IntelI7UncPmcN";
2083 case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
2084 case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
2085 return g_fIntelNetBurst ? NULL : "IntelI7UncPerfEvtSelN";
2086 case 0x000003f1: return "Ia32PebsEnable";
2087 case 0x000003f6: return g_fIntelNetBurst ? NULL /*??*/ : "IntelI7PebsLdLat";
2088 case 0x000003f8: return g_fIntelNetBurst ? NULL : "IntelI7PkgCnResidencyN";
2089 case 0x000003f9: return "IntelI7PkgCnResidencyN";
2090 case 0x000003fa: return "IntelI7PkgCnResidencyN";
2091 case 0x000003fc: return "IntelI7CoreCnResidencyN";
2092 case 0x000003fd: return "IntelI7CoreCnResidencyN";
2093 case 0x000003fe: return "IntelI7CoreCnResidencyN";
2094
2095 case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
2096 case 0x00000480: *pfTakesValue = true; return "Ia32VmxBase";
2097 case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls";
2098 case 0x00000482: *pfTakesValue = true; return "Ia32VmxProcbasedCtls";
2099 case 0x00000483: *pfTakesValue = true; return "Ia32VmxExitCtls";
2100 case 0x00000484: *pfTakesValue = true; return "Ia32VmxEntryCtls";
2101 case 0x00000485: *pfTakesValue = true; return "Ia32VmxMisc";
2102 case 0x00000486: *pfTakesValue = true; return "Ia32VmxCr0Fixed0";
2103 case 0x00000487: *pfTakesValue = true; return "Ia32VmxCr0Fixed1";
2104 case 0x00000488: *pfTakesValue = true; return "Ia32VmxCr4Fixed0";
2105 case 0x00000489: *pfTakesValue = true; return "Ia32VmxCr4Fixed1";
2106 case 0x0000048a: *pfTakesValue = true; return "Ia32VmxVmcsEnum";
2107 case 0x0000048b: *pfTakesValue = true; return "Ia32VmxProcBasedCtls2";
2108 case 0x0000048c: *pfTakesValue = true; return "Ia32VmxEptVpidCap";
2109 case 0x0000048d: *pfTakesValue = true; return "Ia32VmxTruePinbasedCtls";
2110 case 0x0000048e: *pfTakesValue = true; return "Ia32VmxTrueProcbasedCtls";
2111 case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls";
2112 case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls";
2113 case 0x00000491: *pfTakesValue = true; return "Ia32VmxVmFunc";
2114
2115 case 0x000004c1:
2116 case 0x000004c2:
2117 case 0x000004c3:
2118 case 0x000004c4:
2119 case 0x000004c5:
2120 case 0x000004c6:
2121 case 0x000004c7:
2122 case 0x000004c8:
2123 return "Ia32PmcN";
2124
2125 case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */
2126
2127 case 0x00000600: return "Ia32DsArea";
2128 case 0x00000601: *pfTakesValue = true; return "IntelI7SandyVrCurrentConfig";
2129 case 0x00000603: *pfTakesValue = true; return "IntelI7SandyVrMiscConfig";
2130 case 0x00000606: *pfTakesValue = true; return "IntelI7SandyRaplPowerUnit";
2131 case 0x0000060a: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2132 case 0x0000060b: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2133 case 0x0000060c: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN";
2134 case 0x0000060d: *pfTakesValue = true; return "IntelI7SandyPkgC2Residency";
2135
2136 case 0x00000610: *pfTakesValue = true; return "IntelI7RaplPkgPowerLimit";
2137 case 0x00000611: *pfTakesValue = true; return "IntelI7RaplPkgEnergyStatus";
2138 case 0x00000613: *pfTakesValue = true; return "IntelI7RaplPkgPerfStatus";
2139 case 0x00000614: *pfTakesValue = true; return "IntelI7RaplPkgPowerInfo";
2140 case 0x00000618: *pfTakesValue = true; return "IntelI7RaplDramPowerLimit";
2141 case 0x00000619: *pfTakesValue = true; return "IntelI7RaplDramEnergyStatus";
2142 case 0x0000061b: *pfTakesValue = true; return "IntelI7RaplDramPerfStatus";
2143 case 0x0000061c: *pfTakesValue = true; return "IntelI7RaplDramPowerInfo";
2144 case 0x00000638: *pfTakesValue = true; return "IntelI7RaplPp0PowerLimit";
2145 case 0x00000639: *pfTakesValue = true; return "IntelI7RaplPp0EnergyStatus";
2146 case 0x0000063a: *pfTakesValue = true; return "IntelI7RaplPp0Policy";
2147 case 0x0000063b: *pfTakesValue = true; return "IntelI7RaplPp0PerfStatus";
2148 case 0x00000640: *pfTakesValue = true; return "IntelI7RaplPp1PowerLimit";
2149 case 0x00000641: *pfTakesValue = true; return "IntelI7RaplPp1EnergyStatus";
2150 case 0x00000642: *pfTakesValue = true; return "IntelI7RaplPp1Policy";
2151 case 0x00000648: *pfTakesValue = true; return "IntelI7IvyConfigTdpNominal";
2152 case 0x00000649: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel1";
2153 case 0x0000064a: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel2";
2154 case 0x0000064b: return "IntelI7IvyConfigTdpControl";
2155 case 0x0000064c: return "IntelI7IvyTurboActivationRatio";
2156
2157 case 0x00000660: return "IntelAtSilvCoreC1Recidency";
2158
2159 case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
2160 case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687:
2161 case 0x00000688: case 0x00000689: case 0x0000068a: case 0x0000068b:
2162 case 0x0000068c: case 0x0000068d: case 0x0000068e: case 0x0000068f:
2163 //case 0x00000690: case 0x00000691: case 0x00000692: case 0x00000693:
2164 //case 0x00000694: case 0x00000695: case 0x00000696: case 0x00000697:
2165 //case 0x00000698: case 0x00000699: case 0x0000069a: case 0x0000069b:
2166 //case 0x0000069c: case 0x0000069d: case 0x0000069e: case 0x0000069f:
2167 return "IntelLastBranchFromN";
2168 case 0x000006c0: case 0x000006c1: case 0x000006c2: case 0x000006c3:
2169 case 0x000006c4: case 0x000006c5: case 0x000006c6: case 0x000006c7:
2170 case 0x000006c8: case 0x000006c9: case 0x000006ca: case 0x000006cb:
2171 case 0x000006cc: case 0x000006cd: case 0x000006ce: case 0x000006cf:
2172 //case 0x000006d0: case 0x000006d1: case 0x000006d2: case 0x000006d3:
2173 //case 0x000006d4: case 0x000006d5: case 0x000006d6: case 0x000006d7:
2174 //case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db:
2175 //case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df:
2176 return "IntelLastBranchToN";
2177 case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */
2178
2179 case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
2180
2181 case 0xc0000080: return "Amd64Efer";
2182 case 0xc0000081: return "Amd64SyscallTarget";
2183 case 0xc0000082: return "Amd64LongSyscallTarget";
2184 case 0xc0000083: return "Amd64CompSyscallTarget";
2185 case 0xc0000084: return "Amd64SyscallFlagMask";
2186 case 0xc0000100: return "Amd64FsBase";
2187 case 0xc0000101: return "Amd64GsBase";
2188 case 0xc0000102: return "Amd64KernelGsBase";
2189 case 0xc0000103: return "Amd64TscAux";
2190 case 0xc0000104: return "AmdFam15hTscRate";
2191 case 0xc0000105: return "AmdFam15hLwpCfg";
2192 case 0xc0000106: return "AmdFam15hLwpCbAddr";
2193 case 0xc0000408: return "AmdFam10hMc4MiscN";
2194 case 0xc0000409: return "AmdFam10hMc4MiscN";
2195 case 0xc000040a: return "AmdFam10hMc4MiscN";
2196 case 0xc000040b: return "AmdFam10hMc4MiscN";
2197 case 0xc000040c: return "AmdFam10hMc4MiscN";
2198 case 0xc000040d: return "AmdFam10hMc4MiscN";
2199 case 0xc000040e: return "AmdFam10hMc4MiscN";
2200 case 0xc000040f: return "AmdFam10hMc4MiscN";
2201 case 0xc0010000: return "AmdK8PerfCtlN";
2202 case 0xc0010001: return "AmdK8PerfCtlN";
2203 case 0xc0010002: return "AmdK8PerfCtlN";
2204 case 0xc0010003: return "AmdK8PerfCtlN";
2205 case 0xc0010004: return "AmdK8PerfCtrN";
2206 case 0xc0010005: return "AmdK8PerfCtrN";
2207 case 0xc0010006: return "AmdK8PerfCtrN";
2208 case 0xc0010007: return "AmdK8PerfCtrN";
2209 case 0xc0010010: *pfTakesValue = true; return "AmdK8SysCfg";
2210 case 0xc0010015: return "AmdK8HwCr";
2211 case 0xc0010016: case 0xc0010018: return "AmdK8IorrBaseN";
2212 case 0xc0010017: case 0xc0010019: return "AmdK8IorrMaskN";
2213 case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
2214 case 0xc001001f: return "AmdK8NbCfg1";
2215 case 0xc0010020: return "AmdK8PatchLoader";
2216 case 0xc0010022: return "AmdK8McXcptRedir";
2217 case 0xc0010030: case 0xc0010031: case 0xc0010032:
2218 case 0xc0010033: case 0xc0010034: case 0xc0010035:
2219 return "AmdK8CpuNameN";
2220 case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
2221 case 0xc001003f: return "AmdK8SwThermalCtrl";
2222 case 0xc0010041: *pfTakesValue = true; return "AmdK8FidVidControl";
2223 case 0xc0010042: *pfTakesValue = true; return "AmdK8FidVidStatus";
2224 case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
2225 case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
2226 return "AmdK8McCtlMaskN";
2227 case 0xc0010050: case 0xc0010051: case 0xc0010052: case 0xc0010053:
2228 return "AmdK8SmiOnIoTrapN";
2229 case 0xc0010054: return "AmdK8SmiOnIoTrapCtlSts";
2230 case 0xc0010055: return "AmdK8IntPendingMessage";
2231 case 0xc0010056: return "AmdK8SmiTriggerIoCycle";
2232 case 0xc0010058: return "AmdFam10hMmioCfgBaseAddr";
2233 case 0xc0010059: return "AmdFam10hTrapCtlMaybe";
2234 case 0xc0010061: *pfTakesValue = true; return "AmdFam10hPStateCurLimit";
2235 case 0xc0010062: *pfTakesValue = true; return "AmdFam10hPStateControl";
2236 case 0xc0010063: *pfTakesValue = true; return "AmdFam10hPStateStatus";
2237 case 0xc0010064: case 0xc0010065: case 0xc0010066: case 0xc0010067:
2238 case 0xc0010068: case 0xc0010069: case 0xc001006a: case 0xc001006b:
2239 *pfTakesValue = true; return "AmdFam10hPStateN";
2240 case 0xc0010070: *pfTakesValue = true; return "AmdFam10hCofVidControl";
2241 case 0xc0010071: *pfTakesValue = true; return "AmdFam10hCofVidStatus";
2242 case 0xc0010073: return "AmdFam10hCStateIoBaseAddr";
2243 case 0xc0010074: return "AmdFam10hCpuWatchdogTimer";
2244 // case 0xc0010075: return "AmdFam15hApmlTdpLimit";
2245 // case 0xc0010077: return "AmdFam15hCpuPowerInTdp";
2246 // case 0xc0010078: return "AmdFam15hPowerAveragingPeriod";
2247 // case 0xc0010079: return "AmdFam15hDramCtrlCmdThrottle";
2248 // case 0xc0010080: return "AmdFam16hFreqSensFeedbackMonActCnt0";
2249 // case 0xc0010081: return "AmdFam16hFreqSensFeedbackMonRefCnt0";
2250 case 0xc0010111: return "AmdK8SmmBase"; /** @todo probably misdetected ign/gp due to locking */
2251 case 0xc0010112: return "AmdK8SmmAddr"; /** @todo probably misdetected ign/gp due to locking */
2252 case 0xc0010113: return "AmdK8SmmMask"; /** @todo probably misdetected ign/gp due to locking */
2253 case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmCr" : NULL; /** @todo probably misdetected due to locking */
2254 case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8IgnNe" : NULL;
2255 case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8SmmCtl" : NULL;
2256 case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmHSavePa" : NULL; /** @todo probably misdetected due to locking */
2257 case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdFam10hVmLockKey" : NULL;
2258 case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hSmmLockKey" : NULL; /* Not documented by BKDG, found in netbsd patch. */
2259 case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hLocalSmiStatus" : NULL;
2260 case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
2261 case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
2262 case 0xc0010200: case 0xc0010202: case 0xc0010204: case 0xc0010206:
2263 case 0xc0010208: case 0xc001020a: //case 0xc001020c: case 0xc001020e:
2264 return "AmdK8PerfCtlN";
2265 case 0xc0010201: case 0xc0010203: case 0xc0010205: case 0xc0010207:
2266 case 0xc0010209: case 0xc001020b: //case 0xc001020d: case 0xc001020f:
2267 return "AmdK8PerfCtrN";
2268 case 0xc0010230: case 0xc0010232: case 0xc0010234: case 0xc0010236:
2269 //case 0xc0010238: case 0xc001023a: case 0xc001030c: case 0xc001023e:
2270 return "AmdFam16hL2IPerfCtlN";
2271 case 0xc0010231: case 0xc0010233: case 0xc0010235: case 0xc0010237:
2272 //case 0xc0010239: case 0xc001023b: case 0xc001023d: case 0xc001023f:
2273 return "AmdFam16hL2IPerfCtrN";
2274 case 0xc0010240: case 0xc0010242: case 0xc0010244: case 0xc0010246:
2275 //case 0xc0010248: case 0xc001024a: case 0xc001024c: case 0xc001024e:
2276 return "AmdFam15hNorthbridgePerfCtlN";
2277 case 0xc0010241: case 0xc0010243: case 0xc0010245: case 0xc0010247:
2278 //case 0xc0010249: case 0xc001024b: case 0xc001024d: case 0xc001024f:
2279 return "AmdFam15hNorthbridgePerfCtrN";
2280 case 0xc0011000: *pfTakesValue = true; return "AmdK7MicrocodeCtl";
2281 case 0xc0011001: *pfTakesValue = true; return "AmdK7ClusterIdMaybe";
2282 case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
2283 case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
2284 case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
2285 case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
2286 case 0xc0011006: return "AmdK7DebugStatusMaybe";
2287 case 0xc0011007: return "AmdK7BHTraceBaseMaybe";
2288 case 0xc0011008: return "AmdK7BHTracePtrMaybe";
2289 case 0xc0011009: return "AmdK7BHTraceLimitMaybe";
2290 case 0xc001100a: return "AmdK7HardwareDebugToolCfgMaybe";
2291 case 0xc001100b: return "AmdK7FastFlushCountMaybe";
2292 case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
2293 case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2294 case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2295 case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
2296 case 0xc0011020: return "AmdK7LoadStoreCfg";
2297 case 0xc0011021: return "AmdK7InstrCacheCfg";
2298 case 0xc0011022: return "AmdK7DataCacheCfg";
2299 case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
2300 case 0xc0011024: return "AmdK7DebugCtl2Maybe";
2301 case 0xc0011025: return "AmdK7Dr0DataMatchMaybe";
2302 case 0xc0011026: return "AmdK7Dr0DataMaskMaybe";
2303 case 0xc0011027: return "AmdK7DrXAddrMaskN";
2304 case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hFpuCfg" : NULL;
2305 case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
2306 case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg2"
2307 : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
2308 ? "AmdFam10hBusUnitCfg2" /* 10h & 16h */ : NULL;
2309 case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
2310 case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
2311 case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
2312 case 0xc0011030: return "AmdFam10hIbsFetchCtl";
2313 case 0xc0011031: return "AmdFam10hIbsFetchLinAddr";
2314 case 0xc0011032: return "AmdFam10hIbsFetchPhysAddr";
2315 case 0xc0011033: return "AmdFam10hIbsOpExecCtl";
2316 case 0xc0011034: return "AmdFam10hIbsOpRip";
2317 case 0xc0011035: return "AmdFam10hIbsOpData";
2318 case 0xc0011036: return "AmdFam10hIbsOpData2";
2319 case 0xc0011037: return "AmdFam10hIbsOpData3";
2320 case 0xc0011038: return "AmdFam10hIbsDcLinAddr";
2321 case 0xc0011039: return "AmdFam10hIbsDcPhysAddr";
2322 case 0xc001103a: return "AmdFam10hIbsCtl";
2323 case 0xc001103b: return "AmdFam14hIbsBrTarget";
2324 }
2325 return NULL;
2326}
2327
2328
2329/**
2330 * Names CPUMCPU variables that MSRs corresponds to.
2331 *
2332 * @returns The variable name @a uMsr corresponds to, NULL if no variable.
2333 * @param uMsr The MSR in question.
2334 */
2335static const char *getMsrCpumCpuVarName(uint32_t uMsr)
2336{
2337 switch (uMsr)
2338 {
2339 case 0x00000250: return "GuestMsrs.msr.MtrrFix64K_00000";
2340 case 0x00000258: return "GuestMsrs.msr.MtrrFix16K_80000";
2341 case 0x00000259: return "GuestMsrs.msr.MtrrFix16K_A0000";
2342 case 0x00000268: return "GuestMsrs.msr.MtrrFix4K_C0000";
2343 case 0x00000269: return "GuestMsrs.msr.MtrrFix4K_C8000";
2344 case 0x0000026a: return "GuestMsrs.msr.MtrrFix4K_D0000";
2345 case 0x0000026b: return "GuestMsrs.msr.MtrrFix4K_D8000";
2346 case 0x0000026c: return "GuestMsrs.msr.MtrrFix4K_E0000";
2347 case 0x0000026d: return "GuestMsrs.msr.MtrrFix4K_E8000";
2348 case 0x0000026e: return "GuestMsrs.msr.MtrrFix4K_F0000";
2349 case 0x0000026f: return "GuestMsrs.msr.MtrrFix4K_F8000";
2350 case 0x00000277: return "Guest.msrPAT";
2351 case 0x000002ff: return "GuestMsrs.msr.MtrrDefType";
2352 }
2353 return NULL;
2354}
2355
2356
2357/**
2358 * Checks whether the MSR should read as zero for some reason.
2359 *
2360 * @returns true if the register should read as zero, false if not.
2361 * @param uMsr The MSR.
2362 */
2363static bool doesMsrReadAsZero(uint32_t uMsr)
2364{
2365 switch (uMsr)
2366 {
2367 case 0x00000088: return true; // "BBL_CR_D0" - RAZ until understood/needed.
2368 case 0x00000089: return true; // "BBL_CR_D1" - RAZ until understood/needed.
2369 case 0x0000008a: return true; // "BBL_CR_D2" - RAZ until understood/needed.
2370
2371 /* Non-zero, but unknown register. */
2372 case 0x0000004a:
2373 case 0x0000004b:
2374 case 0x0000004c:
2375 case 0x0000004d:
2376 case 0x0000004e:
2377 case 0x0000004f:
2378 case 0x00000050:
2379 case 0x00000051:
2380 case 0x00000052:
2381 case 0x00000053:
2382 case 0x00000054:
2383 case 0x0000008c:
2384 case 0x0000008d:
2385 case 0x0000008e:
2386 case 0x0000008f:
2387 case 0x00000090:
2388 case 0xc0011011:
2389 return true;
2390 }
2391
2392 return false;
2393}
2394
2395
2396/**
2397 * Gets the skip mask for the given MSR.
2398 *
2399 * @returns Skip mask (0 means skipping nothing).
2400 * @param uMsr The MSR.
2401 */
2402static uint64_t getGenericSkipMask(uint32_t uMsr)
2403{
2404 switch (uMsr)
2405 {
2406 case 0x0000013c: return 3; /* AES-NI lock bit ++. */
2407
2408 case 0x000001f2: return UINT64_C(0xfffff00f); /* Ia32SmrrPhysBase - Only writable in SMM. */
2409 case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */
2410
2411 /* these two have lock bits. */
2412 case 0x0000064b: return UINT64_C(0x80000003);
2413 case 0x0000064c: return UINT64_C(0x800000ff);
2414
2415 case 0xc0010015: return 1; /* SmmLock bit */
2416
2417 /* SmmLock effect: */
2418 case 0xc0010111: return UINT32_MAX;
2419 case 0xc0010112: return UINT64_C(0xfffe0000) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2420 case 0xc0010113: return UINT64_C(0xfffe773f) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
2421 case 0xc0010116: return 0x1f;
2422
2423 case 0xc0010114: return RT_BIT_64(3) /* SVM lock */ | RT_BIT_64(4) /* SvmeDisable */;
2424
2425 /* Canonical */
2426 case 0xc0011034:
2427 case 0xc0011038:
2428 case 0xc001103b:
2429 return UINT64_C(0xffff800000000000);
2430
2431 case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063:
2432 case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067:
2433 case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
2434 case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
2435 case 0x00000600:
2436 if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
2437 return UINT64_C(0xffff800000000000);
2438 break;
2439
2440
2441 /* Write only bits. */
2442 case 0xc0010041: return RT_BIT_64(16); /* FIDVID_CTL.InitFidVid */
2443
2444 /* Time counters - fudge them to avoid incorrect ignore masks. */
2445 case 0x00000010:
2446 case 0x000000e7:
2447 case 0x000000e8:
2448 return RT_BIT_32(29) - 1;
2449 }
2450 return 0;
2451}
2452
2453
2454
2455
2456/** queryMsrWriteBadness return values. */
2457typedef enum
2458{
2459 /** . */
2460 VBCPUREPBADNESS_MOSTLY_HARMLESS = 0,
2461 /** Not a problem if accessed with care. */
2462 VBCPUREPBADNESS_MIGHT_BITE,
2463 /** Worse than a bad james bond villain. */
2464 VBCPUREPBADNESS_BOND_VILLAIN
2465} VBCPUREPBADNESS;
2466
2467
2468/**
2469 * Backlisting and graylisting of MSRs which may cause tripple faults.
2470 *
2471 * @returns Badness factor.
2472 * @param uMsr The MSR in question.
2473 */
2474static VBCPUREPBADNESS queryMsrWriteBadness(uint32_t uMsr)
2475{
2476 /** @todo Having trouble in the 0xc0010247,0xc0011006,?? region on Bulldozer. */
2477 /** @todo Having trouble in the 0xc001100f,0xc001100d,?? region on Opteron
2478 * 2384. */
2479
2480 switch (uMsr)
2481 {
2482 case 0x00000050:
2483 case 0x00000051:
2484 case 0x00000052:
2485 case 0x00000053:
2486 case 0x00000054:
2487
2488 case 0x00001006:
2489 case 0x00001007:
2490 return VBCPUREPBADNESS_BOND_VILLAIN;
2491
2492 case 0x0000120e:
2493 case 0x00001233:
2494 case 0x00001239:
2495 case 0x00001249:
2496 case 0x0000124a:
2497 case 0x00001404:
2498 case 0x00001405:
2499 case 0x00001413:
2500 case 0x0000142c: /* Caused rip to be set to 297 or some such weirdness... */
2501 case 0x0000142e:
2502 case 0x00001435:
2503 case 0x00001436:
2504 case 0x00001438:
2505 case 0x0000317f:
2506 if (g_enmVendor == CPUMCPUVENDOR_VIA)
2507 return VBCPUREPBADNESS_BOND_VILLAIN;
2508 break;
2509
2510 case 0xc0010010:
2511 case 0xc0010016:
2512 case 0xc0010017:
2513 case 0xc0010018:
2514 case 0xc0010019:
2515 case 0xc001001a:
2516 case 0xc001001d:
2517 case 0xc0010064: /* P-state fequency, voltage, ++. */
2518 case 0xc0010065: /* P-state fequency, voltage, ++. */
2519 case 0xc0010066: /* P-state fequency, voltage, ++. */
2520 case 0xc0010067: /* P-state fequency, voltage, ++. */
2521 case 0xc0010068: /* P-state fequency, voltage, ++. */
2522 case 0xc0010069: /* P-state fequency, voltage, ++. */
2523 case 0xc001006a: /* P-state fequency, voltage, ++. */
2524 case 0xc001006b: /* P-state fequency, voltage, ++. */
2525 case 0xc0010070: /* COFVID Control. */
2526 case 0xc001101e:
2527 case 0xc0011021: /* IC_CFG (instruction cache configuration) */
2528 case 0xc0011023: /* CU_CFG (combined unit configuration) */
2529 case 0xc001102c: /* EX_CFG (execution unit configuration) */
2530 return VBCPUREPBADNESS_BOND_VILLAIN;
2531
2532 case 0xc0011012:
2533 if (CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch))
2534 return VBCPUREPBADNESS_MIGHT_BITE;
2535 break;
2536
2537 case 0x000001a0: /* IA32_MISC_ENABLE */
2538 case 0x00000199: /* IA32_PERF_CTL */
2539 return VBCPUREPBADNESS_MIGHT_BITE;
2540 case 0x00002000: /* P6_CR0. */
2541 case 0x00002003: /* P6_CR3. */
2542 case 0x00002004: /* P6_CR4. */
2543 if (g_enmVendor == CPUMCPUVENDOR_INTEL)
2544 return VBCPUREPBADNESS_MIGHT_BITE;
2545 break;
2546 case 0xc0000080: /* MSR_K6_EFER */
2547 return VBCPUREPBADNESS_MIGHT_BITE;
2548 }
2549 return VBCPUREPBADNESS_MOSTLY_HARMLESS;
2550}
2551
2552
2553/**
2554 * Checks if this might be a VIA dummy register.
2555 *
2556 * @returns true if it's a dummy, false if it isn't.
2557 * @param uMsr The MSR.
2558 * @param uValue The value.
2559 * @param fFlags The flags.
2560 */
2561static bool isMsrViaDummy(uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
2562{
2563 if (g_enmVendor != CPUMCPUVENDOR_VIA)
2564 return false;
2565
2566 if (uValue)
2567 return false;
2568
2569 if (fFlags)
2570 return false;
2571
2572 switch (uMsr)
2573 {
2574 case 0x00000010:
2575 case 0x0000001b:
2576 case 0x000000c1:
2577 case 0x000000c2:
2578 case 0x0000011e:
2579 case 0x00000186:
2580 case 0x00000187:
2581 //case 0x00000200 ... (mtrrs will be detected)
2582 return false;
2583
2584 case 0xc0000080:
2585 case 0xc0000081:
2586 case 0xc0000082:
2587 case 0xc0000083:
2588 if (vbCpuRepSupportsLongMode())
2589 return false;
2590 break;
2591 }
2592
2593 if (uMsr >= 0x00001200 && uMsr <= 0x00003fff && queryMsrWriteBadness(uMsr) != VBCPUREPBADNESS_MOSTLY_HARMLESS)
2594 return false;
2595
2596 if ( !msrProberModifyNoChange(uMsr)
2597 && !msrProberModifyZero(uMsr))
2598 return false;
2599
2600 uint64_t fIgnMask = 0;
2601 uint64_t fGpMask = 0;
2602 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0);
2603 if (RT_FAILURE(rc))
2604 return false;
2605
2606 if (fIgnMask != UINT64_MAX)
2607 return false;
2608 if (fGpMask != 0)
2609 return false;
2610
2611 return true;
2612}
2613
2614
2615/**
2616 * Adjusts the ignore and GP masks for MSRs which contains canonical addresses.
2617 *
2618 * @param uMsr The MSR.
2619 * @param pfIgn Pointer to the ignore mask.
2620 * @param pfGp Pointer to the GP mask.
2621 */
2622static void adjustCanonicalIgnAndGpMasks(uint32_t uMsr, uint64_t *pfIgn, uint64_t *pfGp)
2623{
2624 RT_NOREF1(pfIgn);
2625 if (!vbCpuRepSupportsLongMode())
2626 return;
2627 switch (uMsr)
2628 {
2629 case 0x00000175:
2630 case 0x00000176:
2631 case 0x000001da:
2632 case 0x000001db:
2633 case 0x000001dc:
2634 case 0x000001de:
2635 case 0x00000600:
2636 if (*pfGp == UINT64_C(0xffff800000000000))
2637 *pfGp = 0;
2638 break;
2639 case 0x000001dd:
2640 if (*pfGp == UINT64_C(0x7fff800000000000) || *pfGp == UINT64_C(0xffff800000000000)) /* why is the top bit writable? */
2641 *pfGp = 0;
2642 break;
2643
2644 case 0xc0000082:
2645 case 0xc0000083:
2646 case 0xc0000100:
2647 case 0xc0000101:
2648 case 0xc0000102:
2649 *pfGp = 0;
2650 break;
2651 }
2652}
2653
2654
2655
2656/**
2657 * Prints a 64-bit value in the best way.
2658 *
2659 * @param uValue The value.
2660 */
2661static void printMsrValueU64(uint64_t uValue)
2662{
2663 if (uValue == 0)
2664 vbCpuRepPrintf(", 0");
2665 else if (uValue == UINT16_MAX)
2666 vbCpuRepPrintf(", UINT16_MAX");
2667 else if (uValue == UINT32_MAX)
2668 vbCpuRepPrintf(", UINT32_MAX");
2669 else if (uValue == UINT64_MAX)
2670 vbCpuRepPrintf(", UINT64_MAX");
2671 else if (uValue == UINT64_C(0xffffffff00000000))
2672 vbCpuRepPrintf(", ~(uint64_t)UINT32_MAX");
2673 else if (uValue <= (UINT32_MAX >> 1))
2674 vbCpuRepPrintf(", %#llx", uValue);
2675 else if (uValue <= UINT32_MAX)
2676 vbCpuRepPrintf(", UINT32_C(%#llx)", uValue);
2677 else
2678 vbCpuRepPrintf(", UINT64_C(%#llx)", uValue);
2679}
2680
2681
2682/**
2683 * Prints the newline after an MSR line has been printed.
2684 *
2685 * This is used as a hook to slow down the output and make sure the remote
2686 * terminal or/and output file has received the last update before we go and
2687 * crash probing the next MSR.
2688 */
2689static void printMsrNewLine(void)
2690{
2691 vbCpuRepPrintf("\n");
2692#if 1
2693 RTThreadSleep(8);
2694#endif
2695}
2696
2697static int printMsrWriteOnly(uint32_t uMsr, const char *pszWrFnName, const char *pszAnnotation)
2698{
2699 if (!pszWrFnName)
2700 pszWrFnName = "IgnoreWrite";
2701 vbCpuRepPrintf(pszAnnotation
2702 ? " MFN(%#010x, \"%s\", WriteOnly, %s), /* %s */"
2703 : " MFN(%#010x, \"%s\", WriteOnly, %s),",
2704 uMsr, getMsrName(uMsr), pszWrFnName, pszAnnotation);
2705 printMsrNewLine();
2706 return VINF_SUCCESS;
2707}
2708
2709
2710static int printMsrValueReadOnly(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2711{
2712 vbCpuRepPrintf(" MVO(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2713 printMsrValueU64(uValue);
2714 vbCpuRepPrintf("),");
2715 if (pszAnnotation)
2716 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2717 printMsrNewLine();
2718 return VINF_SUCCESS;
2719}
2720
2721
2722
2723static int printMsrValueIgnoreWritesNamed(uint32_t uMsr, uint64_t uValue, const char *pszName, const char *pszAnnotation)
2724{
2725 vbCpuRepPrintf(" MVI(%#010x, \"%s\"", uMsr, pszName);
2726 printMsrValueU64(uValue);
2727 vbCpuRepPrintf("),");
2728 if (pszAnnotation)
2729 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2730 printMsrNewLine();
2731 return VINF_SUCCESS;
2732}
2733
2734
2735static int printMsrValueIgnoreWrites(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
2736{
2737 return printMsrValueIgnoreWritesNamed(uMsr, uValue, getMsrName(uMsr), pszAnnotation);
2738}
2739
2740
2741static int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
2742 const char *pszAnnotation)
2743{
2744 vbCpuRepPrintf(" MVX(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
2745 printMsrValueU64(uValue);
2746 printMsrValueU64(fIgnMask);
2747 printMsrValueU64(fGpMask);
2748 vbCpuRepPrintf("),");
2749 if (pszAnnotation)
2750 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2751 printMsrNewLine();
2752 return VINF_SUCCESS;
2753}
2754
2755
2756static int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2757{
2758 vbCpuRepPrintf(" RVO(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
2759 printMsrValueU64(uValue);
2760 vbCpuRepPrintf("),");
2761 if (pszAnnotation)
2762 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2763 printMsrNewLine();
2764 return VINF_SUCCESS;
2765}
2766
2767
2768static int printMsrRangeValueIgnoreWritesNamed(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszName, const char *pszAnnotation)
2769{
2770 vbCpuRepPrintf(" RVI(%#010x, %#010x, \"%s\"", uMsr, uLast, pszName);
2771 printMsrValueU64(uValue);
2772 vbCpuRepPrintf("),");
2773 if (pszAnnotation)
2774 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2775 printMsrNewLine();
2776 return VINF_SUCCESS;
2777}
2778
2779
2780static int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
2781{
2782 return printMsrRangeValueIgnoreWritesNamed(uMsr, uLast, uValue, getMsrRangeName(uMsr), pszAnnotation);
2783}
2784
2785
2786static int printMsrFunction(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, const char *pszAnnotation)
2787{
2788 if (!pszRdFnName)
2789 pszRdFnName = getMsrFnName(uMsr, NULL);
2790 if (!pszWrFnName)
2791 pszWrFnName = pszRdFnName;
2792 vbCpuRepPrintf(" MFN(%#010x, \"%s\", %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2793 if (pszAnnotation)
2794 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2795 printMsrNewLine();
2796 return VINF_SUCCESS;
2797}
2798
2799
2800static int printMsrFunctionReadOnly(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
2801{
2802 if (!pszRdFnName)
2803 pszRdFnName = getMsrFnName(uMsr, NULL);
2804 vbCpuRepPrintf(" MFO(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2805 if (pszAnnotation)
2806 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2807 printMsrNewLine();
2808 return VINF_SUCCESS;
2809}
2810
2811
2812static int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
2813{
2814 if (!pszRdFnName)
2815 pszRdFnName = getMsrFnName(uMsr, NULL);
2816 vbCpuRepPrintf(" MFI(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
2817 if (pszAnnotation)
2818 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2819 printMsrNewLine();
2820 return VINF_SUCCESS;
2821}
2822
2823
2824static int printMsrFunctionIgnoreMask(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2825 uint64_t fIgnMask, const char *pszAnnotation)
2826{
2827 if (!pszRdFnName)
2828 pszRdFnName = getMsrFnName(uMsr, NULL);
2829 if (!pszWrFnName)
2830 pszWrFnName = pszRdFnName;
2831 vbCpuRepPrintf(" MFW(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2832 printMsrValueU64(fIgnMask);
2833 vbCpuRepPrintf("),");
2834 if (pszAnnotation)
2835 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2836 printMsrNewLine();
2837 return VINF_SUCCESS;
2838}
2839
2840
2841static int printMsrFunctionExtended(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
2842 uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2843{
2844 if (!pszRdFnName)
2845 pszRdFnName = getMsrFnName(uMsr, NULL);
2846 if (!pszWrFnName)
2847 pszWrFnName = pszRdFnName;
2848 vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
2849 printMsrValueU64(uValue);
2850 printMsrValueU64(fIgnMask);
2851 printMsrValueU64(fGpMask);
2852 vbCpuRepPrintf("),");
2853 if (pszAnnotation)
2854 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2855 printMsrNewLine();
2856 return VINF_SUCCESS;
2857}
2858
2859
2860static int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
2861 uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2862{
2863 if (!pszRdFnName)
2864 pszRdFnName = getMsrFnName(uMsr, NULL);
2865 if (!pszWrFnName)
2866 pszWrFnName = pszRdFnName;
2867 vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
2868 printMsrValueU64(fIgnMask);
2869 printMsrValueU64(fGpMask);
2870 vbCpuRepPrintf("),");
2871 if (pszAnnotation)
2872 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2873 printMsrNewLine();
2874 return VINF_SUCCESS;
2875}
2876
2877
2878static int printMsrFunctionCpumCpu(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2879 const char *pszCpumCpuStorage, const char *pszAnnotation)
2880{
2881 if (!pszRdFnName)
2882 pszRdFnName = getMsrFnName(uMsr, NULL);
2883 if (!pszWrFnName)
2884 pszWrFnName = pszRdFnName;
2885 if (!pszCpumCpuStorage)
2886 pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2887 if (!pszCpumCpuStorage)
2888 return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2889 vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2890 if (pszAnnotation)
2891 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2892 printMsrNewLine();
2893 return VINF_SUCCESS;
2894}
2895
2896
2897static int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
2898 const char *pszCpumCpuStorage, uint64_t fIgnMask, uint64_t fGpMask,
2899 const char *pszAnnotation)
2900{
2901 if (!pszRdFnName)
2902 pszRdFnName = getMsrFnName(uMsr, NULL);
2903 if (!pszWrFnName)
2904 pszWrFnName = pszRdFnName;
2905 if (!pszCpumCpuStorage)
2906 pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
2907 if (!pszCpumCpuStorage)
2908 return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
2909 vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
2910 printMsrValueU64(fIgnMask);
2911 printMsrValueU64(fGpMask);
2912 vbCpuRepPrintf("),");
2913 if (pszAnnotation)
2914 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2915 printMsrNewLine();
2916 return VINF_SUCCESS;
2917}
2918
2919
2920static int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
2921 const char *pszAnnotation)
2922{
2923 if (!pszRdFnName)
2924 pszRdFnName = getMsrFnName(uMsr, NULL);
2925 if (!pszWrFnName)
2926 pszWrFnName = pszRdFnName;
2927 vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2928 if (pszAnnotation)
2929 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2930 printMsrNewLine();
2931 return VINF_SUCCESS;
2932}
2933
2934
2935static int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
2936 uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2937{
2938 if (!pszRdFnName)
2939 pszRdFnName = getMsrFnName(uMsr, NULL);
2940 if (!pszWrFnName)
2941 pszWrFnName = pszRdFnName;
2942 vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
2943 printMsrValueU64(uValue);
2944 printMsrValueU64(fIgnMask);
2945 printMsrValueU64(fGpMask);
2946 vbCpuRepPrintf("),");
2947 if (pszAnnotation)
2948 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2949 printMsrNewLine();
2950 return VINF_SUCCESS;
2951}
2952
2953
2954static int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
2955 uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
2956{
2957 if (!pszRdFnName)
2958 pszRdFnName = getMsrFnName(uMsr, NULL);
2959 if (!pszWrFnName)
2960 pszWrFnName = pszRdFnName;
2961 vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s, %#x",
2962 uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName, uValue);
2963 printMsrValueU64(fIgnMask);
2964 printMsrValueU64(fGpMask);
2965 vbCpuRepPrintf("),");
2966 if (pszAnnotation)
2967 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2968 printMsrNewLine();
2969 return VINF_SUCCESS;
2970}
2971
2972
2973static int printMsrAlias(uint32_t uMsr, uint32_t uTarget, const char *pszAnnotation)
2974{
2975 vbCpuRepPrintf(" MAL(%#010x, \"%s\", %#010x),", uMsr, getMsrName(uMsr), uTarget);
2976 if (pszAnnotation)
2977 vbCpuRepPrintf(" /* %s */", pszAnnotation);
2978 printMsrNewLine();
2979 return VINF_SUCCESS;
2980}
2981
2982
2983
2984static const char *annotateValue(uint64_t uValue)
2985{
2986 static char s_szBuf[40];
2987 if (uValue <= UINT32_MAX)
2988 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#llx", uValue);
2989 else
2990 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#x`%08x", RT_HI_U32(uValue), RT_LO_U32(uValue));
2991 return s_szBuf;
2992}
2993
2994
2995static const char *annotateValueExtra(const char *pszExtra, uint64_t uValue)
2996{
2997 static char s_szBuf[40];
2998 if (uValue <= UINT32_MAX)
2999 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#llx", pszExtra, uValue);
3000 else
3001 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
3002 return s_szBuf;
3003}
3004
3005
3006static const char *annotateIfMissingBits(uint64_t uValue, uint64_t fBits)
3007{
3008 static char s_szBuf[80];
3009 if ((uValue & fBits) == fBits)
3010 return annotateValue(uValue);
3011 RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
3012 return s_szBuf;
3013}
3014
3015
3016static int reportMsr_Generic(uint32_t uMsr, uint32_t fFlags, uint64_t uValue)
3017{
3018 int rc;
3019 bool fTakesValue = false;
3020 const char *pszFnName = getMsrFnName(uMsr, &fTakesValue);
3021
3022 if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
3023 rc = printMsrWriteOnly(uMsr, pszFnName, NULL);
3024 else
3025 {
3026 bool fReadAsZero = doesMsrReadAsZero(uMsr);
3027 fTakesValue = fTakesValue && !fReadAsZero;
3028
3029
3030 switch (queryMsrWriteBadness(uMsr))
3031 {
3032 /* This is what we're here for... */
3033 case VBCPUREPBADNESS_MOSTLY_HARMLESS:
3034 {
3035 if ( msrProberModifyNoChange(uMsr)
3036 || msrProberModifyZero(uMsr))
3037 {
3038 uint64_t fSkipMask = getGenericSkipMask(uMsr);
3039 uint64_t fIgnMask = 0;
3040 uint64_t fGpMask = 0;
3041 rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3042 if (RT_FAILURE(rc))
3043 return rc;
3044 adjustCanonicalIgnAndGpMasks(uMsr, &fIgnMask, &fGpMask);
3045
3046 if (pszFnName)
3047 {
3048 if (fGpMask == 0 && fIgnMask == UINT64_MAX && !fTakesValue)
3049 rc = printMsrFunctionIgnoreWrites(uMsr, pszFnName, annotateValue(uValue));
3050 else if (fGpMask == 0 && fIgnMask == 0 && (!fTakesValue || uValue == 0))
3051 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValue(uValue));
3052 else
3053 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, fTakesValue ? uValue : 0,
3054 fIgnMask, fGpMask, annotateValue(uValue));
3055 }
3056 else if (fGpMask == 0 && fIgnMask == UINT64_MAX)
3057 rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
3058 else
3059 rc = printMsrValueExtended(uMsr, fReadAsZero ? 0 : uValue, fIgnMask, fGpMask,
3060 fReadAsZero ? annotateValue(uValue) : NULL);
3061 }
3062 /* Most likely read-only. */
3063 else if (pszFnName && !fTakesValue)
3064 rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValue(uValue));
3065 else if (pszFnName)
3066 rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, 0, annotateValue(uValue));
3067 else if (fReadAsZero)
3068 rc = printMsrValueReadOnly(uMsr, 0, annotateValue(uValue));
3069 else
3070 rc = printMsrValueReadOnly(uMsr, uValue, NULL);
3071 break;
3072 }
3073
3074 /* These should have special handling, so just do a simple
3075 write back same value check to see if it's writable. */
3076 case VBCPUREPBADNESS_MIGHT_BITE:
3077 if (msrProberModifyNoChange(uMsr))
3078 {
3079 if (pszFnName && !fTakesValue)
3080 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Might bite.", uValue));
3081 else if (pszFnName)
3082 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
3083 annotateValueExtra("Might bite.", uValue));
3084 else if (fReadAsZero)
3085 rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Might bite.", uValue));
3086 else
3087 rc = printMsrValueIgnoreWrites(uMsr, uValue, "Might bite.");
3088 }
3089 else if (pszFnName && !fTakesValue)
3090 rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValueExtra("Might bite.", uValue));
3091 else if (pszFnName)
3092 rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, UINT64_MAX,
3093 annotateValueExtra("Might bite.", uValue));
3094 else if (fReadAsZero)
3095 rc = printMsrValueReadOnly(uMsr, 0, annotateValueExtra("Might bite.", uValue));
3096 else
3097 rc = printMsrValueReadOnly(uMsr, uValue, "Might bite.");
3098 break;
3099
3100
3101 /* Don't try anything with these guys. */
3102 case VBCPUREPBADNESS_BOND_VILLAIN:
3103 default:
3104 if (pszFnName && !fTakesValue)
3105 rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Villain?", uValue));
3106 else if (pszFnName)
3107 rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
3108 annotateValueExtra("Villain?", uValue));
3109 else if (fReadAsZero)
3110 rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Villain?", uValue));
3111 else
3112 rc = printMsrValueIgnoreWrites(uMsr, uValue, "Villain?");
3113 break;
3114 }
3115 }
3116
3117 return rc;
3118}
3119
3120
3121static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
3122 uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop)
3123{
3124 uint32_t uMsr = paMsrs[0].uMsr;
3125 uint32_t iRange = uMsr - uMsrBase;
3126 Assert(cMax > iRange);
3127 cMax -= iRange;
3128
3129 /* Resolve default function name. */
3130 if (!pszRdWrFnName)
3131 {
3132 pszRdWrFnName = getMsrFnName(uMsr, NULL);
3133 if (!pszRdWrFnName)
3134 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
3135 }
3136
3137 /* Figure the possible register count. */
3138 if (cMax > cMsrs)
3139 cMax = cMsrs;
3140 uint32_t cRegs = 1;
3141 while ( cRegs < cMax
3142 && paMsrs[cRegs].uMsr == uMsr + cRegs)
3143 cRegs++;
3144
3145 /* Probe the first register and check that the others exhibit
3146 the same characteristics. */
3147 bool fReadOnly0;
3148 uint64_t fIgnMask0, fGpMask0;
3149 int rc = msrProberModifyBasicTests(uMsr, fSkipMask, &fReadOnly0, &fIgnMask0, &fGpMask0);
3150 if (RT_FAILURE(rc))
3151 return rc;
3152
3153 const char *pszAnnotation = NULL;
3154 for (uint32_t i = 1; i < cRegs; i++)
3155 {
3156 bool fReadOnlyN;
3157 uint64_t fIgnMaskN, fGpMaskN;
3158 rc = msrProberModifyBasicTests(paMsrs[i].uMsr, fSkipMask, &fReadOnlyN, &fIgnMaskN, &fGpMaskN);
3159 if (RT_FAILURE(rc))
3160 return rc;
3161 if ( fReadOnlyN != fReadOnly0
3162 || (fIgnMaskN != fIgnMask0 && !fNoIgnMask)
3163 || fGpMaskN != fGpMask0)
3164 {
3165 if (!fEarlyEndOk && !isMsrViaDummy(uMsr, paMsrs[i].uValue, paMsrs[i].fFlags))
3166 {
3167 vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
3168 getMsrNameHandled(uMsr), uMsr, paMsrs[i].uMsr,
3169 fReadOnlyN, fReadOnly0, fIgnMaskN, fIgnMask0, fGpMaskN, fGpMask0);
3170 pszAnnotation = "XXX: The range ended earlier than expected!";
3171 }
3172 cRegs = i;
3173 break;
3174 }
3175 }
3176
3177 /*
3178 * Report the range (or single MSR as it might be).
3179 */
3180 *pidxLoop += cRegs - 1;
3181
3182 if (fNoIgnMask)
3183 fIgnMask0 = 0;
3184 bool fSimple = fIgnMask0 == 0
3185 && (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0))
3186 && iRange == 0;
3187 if (cRegs == 1)
3188 return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3189 iRange, fIgnMask0, fGpMask0,
3190 pszAnnotation ? pszAnnotation : annotateValue(paMsrs[0].uValue));
3191 if (fSimple)
3192 return printMsrRangeFunction(uMsr, uMsr + cRegs - 1,
3193 pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, pszAnnotation);
3194
3195 return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
3196 iRange /*uValue*/, fIgnMask0, fGpMask0, pszAnnotation);
3197}
3198
3199
3200static int reportMsr_GenRangeFunction(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
3201 uint32_t *pidxLoop)
3202{
3203 return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/,
3204 getGenericSkipMask(paMsrs[0].uMsr), pidxLoop);
3205}
3206
3207
3208/**
3209 * Generic report for an MSR implemented by functions, extended version.
3210 *
3211 * @returns VBox status code.
3212 * @param uMsr The MSR.
3213 * @param pszRdWrFnName The read/write function name, optional.
3214 * @param uValue The MSR range value.
3215 * @param fSkipMask Mask of bits to skip.
3216 * @param fNoGpMask Mask of bits to remove from the GP mask after
3217 * probing
3218 * @param pszAnnotate Annotation.
3219 */
3220static int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue,
3221 uint64_t fSkipMask, uint64_t fNoGpMask, const char *pszAnnotate)
3222{
3223 /* Resolve default function name. */
3224 if (!pszRdWrFnName)
3225 {
3226 pszRdWrFnName = getMsrFnName(uMsr, NULL);
3227 if (!pszRdWrFnName)
3228 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
3229 }
3230
3231 /* Probe the register and report. */
3232 uint64_t fIgnMask = 0;
3233 uint64_t fGpMask = 0;
3234 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3235 if (RT_SUCCESS(rc))
3236 {
3237 fGpMask &= ~fNoGpMask;
3238
3239 if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr))
3240 rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate);
3241 else if (fIgnMask == UINT64_MAX && fGpMask == 0 && uValue == 0)
3242 rc = printMsrFunctionIgnoreWrites(uMsr, pszRdWrFnName, pszAnnotate);
3243 else if (fIgnMask != 0 && fGpMask == 0 && uValue == 0)
3244 rc = printMsrFunctionIgnoreMask(uMsr, pszRdWrFnName, NULL, fIgnMask, pszAnnotate);
3245 else if (fIgnMask == 0 && fGpMask == 0 && uValue == 0)
3246 rc = printMsrFunction(uMsr, pszRdWrFnName, NULL, pszAnnotate);
3247 else
3248 rc = printMsrFunctionExtended(uMsr, pszRdWrFnName, NULL, uValue, fIgnMask, fGpMask, pszAnnotate);
3249 }
3250 return rc;
3251}
3252
3253
3254/**
3255 * Reports a VIA dummy range.
3256 *
3257 * @returns VBox status code.
3258 * @param paMsrs Pointer to the first MSR.
3259 * @param cMsrs The number of MSRs in the array @a paMsr.
3260 * @param pidxLoop Index variable that should be advanced to the
3261 * last MSR entry in the range.
3262 */
3263static int reportMsr_ViaDummyRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3264{
3265 /* Figure how many. */
3266 uint32_t uMsr = paMsrs[0].uMsr;
3267 uint32_t cRegs = 1;
3268 while ( cRegs < cMsrs
3269 && paMsrs[cRegs].uMsr == uMsr + cRegs
3270 && isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags))
3271 {
3272 cRegs++;
3273 if (!(cRegs % 0x80))
3274 vbCpuRepDebug("VIA dummy detection %#llx..%#llx (%#x regs)...\n", uMsr, uMsr + cRegs - 1, cRegs);
3275 }
3276
3277 /* Advance. */
3278 *pidxLoop += cRegs - 1;
3279
3280 /* Report it/them. */
3281 char szName[80];
3282 if (cRegs == 1)
3283 {
3284 RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
3285 return printMsrValueIgnoreWritesNamed(uMsr, 0, szName, NULL);
3286 }
3287
3288 uint32_t uMsrLast = uMsr + cRegs - 1;
3289 RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x_THRU_%04x_%04x",
3290 RT_HI_U16(uMsr), RT_LO_U16(uMsr), RT_HI_U16(uMsrLast), RT_LO_U16(uMsrLast));
3291 return printMsrRangeValueIgnoreWritesNamed(uMsr, uMsrLast, 0, szName, NULL);
3292}
3293
3294
3295/**
3296 * Special function for reporting the IA32_APIC_BASE register, as it seems to be
3297 * causing trouble on newer systems.
3298 *
3299 * @returns
3300 * @param uMsr The MSR number.
3301 * @param uValue The value.
3302 */
3303static int reportMsr_Ia32ApicBase(uint32_t uMsr, uint64_t uValue)
3304{
3305 /* Trouble with the generic treatment of both the "APIC Global Enable" and
3306 "Enable x2APIC mode" bits on an i7-3820QM running OS X 10.8.5. */
3307 uint64_t fSkipMask = RT_BIT_64(11);
3308 if (vbCpuRepSupportsX2Apic())
3309 fSkipMask |= RT_BIT_64(10);
3310 /* For some reason, twiddling this bit kills a Tualatin PIII-S. */
3311 if (g_enmMicroarch == kCpumMicroarch_Intel_P6_III)
3312 fSkipMask |= RT_BIT(9);
3313 return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, 0, NULL);
3314}
3315
3316
3317/**
3318 * Special function for reporting the IA32_MISC_ENABLE register, as it seems to
3319 * be causing trouble on newer systems.
3320 *
3321 * @returns
3322 * @param uMsr The MSR number.
3323 * @param uValue The value.
3324 */
3325static int reportMsr_Ia32MiscEnable(uint32_t uMsr, uint64_t uValue)
3326{
3327 uint64_t fSkipMask = 0;
3328
3329 if ( ( g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
3330 && g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
3331 || ( g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
3332 && g_enmMicroarch <= kCpumMicroarch_Intel_Atom_End)
3333 )
3334 {
3335 vbCpuRepPrintf("WARNING: IA32_MISC_ENABLE probing needs hacking on this CPU!\n");
3336 RTThreadSleep(128);
3337 }
3338
3339 /* The no execute related flag is deadly if clear. */
3340 if ( !(uValue & MSR_IA32_MISC_ENABLE_XD_DISABLE)
3341 && ( g_enmMicroarch < kCpumMicroarch_Intel_First
3342 || g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
3343 || vbCpuRepSupportsNX() ) )
3344 fSkipMask |= MSR_IA32_MISC_ENABLE_XD_DISABLE;
3345
3346 uint64_t fIgnMask = 0;
3347 uint64_t fGpMask = 0;
3348 int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
3349 if (RT_SUCCESS(rc))
3350 rc = printMsrFunctionExtended(uMsr, "Ia32MiscEnable", "Ia32MiscEnable", uValue,
3351 fIgnMask, fGpMask, annotateValue(uValue));
3352 return rc;
3353}
3354
3355
3356/**
3357 * Verifies that MTRR type field works correctly in the given MSR.
3358 *
3359 * @returns VBox status code (failure if bad MSR behavior).
3360 * @param uMsr The MSR.
3361 * @param iBit The first bit of the type field (8-bit wide).
3362 * @param cExpected The number of types expected - PAT=8, MTRR=7.
3363 */
3364static int msrVerifyMtrrTypeGPs(uint32_t uMsr, uint32_t iBit, uint32_t cExpected)
3365{
3366 uint32_t uEndTypes = 0;
3367 while (uEndTypes < 255)
3368 {
3369 bool fGp = !msrProberModifySimpleGp(uMsr, ~(UINT64_C(0xff) << iBit), (uint64_t)uEndTypes << iBit);
3370 if (!fGp && (uEndTypes == 2 || uEndTypes == 3))
3371 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
3372 uEndTypes, uMsr);
3373 if (fGp && uEndTypes != 2 && uEndTypes != 3)
3374 break;
3375 uEndTypes++;
3376 }
3377 if (uEndTypes != cExpected)
3378 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
3379 uEndTypes, uMsr, cExpected);
3380 return VINF_SUCCESS;
3381}
3382
3383
3384/**
3385 * Deals with the variable MTRR MSRs.
3386 *
3387 * @returns VBox status code.
3388 * @param paMsrs Pointer to the first variable MTRR MSR (200h).
3389 * @param cMsrs The number of MSRs in the array @a paMsr.
3390 * @param pidxLoop Index variable that should be advanced to the
3391 * last MTRR MSR entry.
3392 */
3393static int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3394{
3395 uint32_t uMsr = paMsrs[0].uMsr;
3396
3397 /* Count them. */
3398 uint32_t cRegs = 1;
3399 while ( cRegs < cMsrs
3400 && paMsrs[cRegs].uMsr == uMsr + cRegs
3401 && !isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags) )
3402 cRegs++;
3403 if (cRegs & 1)
3404 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is odd: cRegs=%#x\n", cRegs);
3405 if (cRegs > 0x20)
3406 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
3407
3408 /* Find a disabled register that we can play around with. */
3409 uint32_t iGuineaPig;
3410 for (iGuineaPig = 0; iGuineaPig < cRegs; iGuineaPig += 2)
3411 if (!(paMsrs[iGuineaPig + 1].uValue & RT_BIT_32(11)))
3412 break;
3413 if (iGuineaPig >= cRegs)
3414 iGuineaPig = cRegs - 2;
3415 vbCpuRepDebug("iGuineaPig=%#x -> %#x\n", iGuineaPig, uMsr + iGuineaPig);
3416
3417 /* Probe the base. */
3418 uint64_t fIgnBase = 0;
3419 uint64_t fGpBase = 0;
3420 int rc = msrProberModifyBitChanges(uMsr + iGuineaPig, &fIgnBase, &fGpBase, 0);
3421 if (RT_FAILURE(rc))
3422 return rc;
3423 rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3424 if (RT_FAILURE(rc))
3425 return rc;
3426 vbCpuRepDebug("fIgnBase=%#llx fGpBase=%#llx\n", fIgnBase, fGpBase);
3427
3428 /* Probing the mask is relatively straight forward. */
3429 uint64_t fIgnMask = 0;
3430 uint64_t fGpMask = 0;
3431 rc = msrProberModifyBitChanges(uMsr + iGuineaPig + 1, &fIgnMask, &fGpMask, 0x800); /* enabling it may cause trouble */
3432 if (RT_FAILURE(rc))
3433 return rc;
3434 vbCpuRepDebug("fIgnMask=%#llx fGpMask=%#llx\n", fIgnMask, fGpMask);
3435
3436 /* Validate that the whole range subscribes to the apprimately same GP rules. */
3437 for (uint32_t i = 0; i < cRegs; i += 2)
3438 {
3439 uint64_t fSkipBase = ~fGpBase;
3440 uint64_t fSkipMask = ~fGpMask;
3441 if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3442 fSkipBase = fSkipMask = 0;
3443 fSkipBase |= 0x7; /* Always skip the type. */
3444 fSkipMask |= RT_BIT_32(11); /* Always skip the enable bit. */
3445
3446 vbCpuRepDebug("i=%#x fSkipBase=%#llx fSkipMask=%#llx\n", i, fSkipBase, fSkipMask);
3447
3448 if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
3449 {
3450 rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
3451 if (RT_FAILURE(rc))
3452 return rc;
3453 }
3454
3455 uint64_t fIgnBaseN = 0;
3456 uint64_t fGpBaseN = 0;
3457 rc = msrProberModifyBitChanges(uMsr + i, &fIgnBaseN, &fGpBaseN, fSkipBase);
3458 if (RT_FAILURE(rc))
3459 return rc;
3460
3461 if ( fIgnBaseN != (fIgnBase & ~fSkipBase)
3462 || fGpBaseN != (fGpBase & ~fSkipBase) )
3463 return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3464 "MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
3465 uMsr + i, uMsr + iGuineaPig,
3466 fIgnBaseN, fIgnBase & ~fSkipBase, fGpBaseN, fGpBase & ~fSkipBase, fSkipBase);
3467
3468 uint64_t fIgnMaskN = 0;
3469 uint64_t fGpMaskN = 0;
3470 rc = msrProberModifyBitChanges(uMsr + i + 1, &fIgnMaskN, &fGpMaskN, fSkipMask);
3471 if (RT_FAILURE(rc))
3472 return rc;
3473 if ( fIgnMaskN != (fIgnMask & ~fSkipMask)
3474 || fGpMaskN != (fGpMask & ~fSkipMask) )
3475 return RTMsgErrorRc(VERR_INVALID_PARAMETER,
3476 "MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
3477 uMsr + i + 1, uMsr + iGuineaPig + 1,
3478 fIgnMaskN, fIgnMask & ~fSkipMask, fGpMaskN, fGpMask & ~fSkipMask, fSkipMask);
3479 }
3480
3481 /* Print the whole range. */
3482 fGpBase &= ~(uint64_t)0x7; /* Valid type bits, see msrVerifyMtrrTypeGPs(). */
3483 for (uint32_t i = 0; i < cRegs; i += 2)
3484 {
3485 printMsrFunctionExtendedIdxVal(uMsr + i, "Ia32MtrrPhysBaseN", NULL, i / 2, fIgnBase, fGpBase,
3486 annotateValue(paMsrs[i].uValue));
3487 printMsrFunctionExtendedIdxVal(uMsr + i + 1, "Ia32MtrrPhysMaskN", NULL, i / 2, fIgnMask, fGpMask,
3488 annotateValue(paMsrs[i + 1].uValue));
3489 }
3490
3491 *pidxLoop += cRegs - 1;
3492 return VINF_SUCCESS;
3493}
3494
3495
3496/**
3497 * Deals with fixed MTRR and PAT MSRs, checking the 8 memory type fields.
3498 *
3499 * @returns VBox status code.
3500 * @param uMsr The MSR.
3501 */
3502static int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
3503{
3504 /* Had a spot of trouble on an old macbook pro with core2 duo T9900 (penryn)
3505 running 64-bit win81pe. Not giving PAT such a scrutiny fixes it. */
3506 if ( uMsr != 0x00000277
3507 || ( g_enmVendor == CPUMCPUVENDOR_INTEL
3508 ? g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First
3509 : g_enmVendor == CPUMCPUVENDOR_AMD
3510 ? g_enmMicroarch != kCpumMicroarch_AMD_K8_90nm_AMDV
3511 : true) )
3512 {
3513 /* Every 8 bytes is a type, check the type ranges one by one. */
3514 for (uint32_t iBit = 0; iBit < 64; iBit += 8)
3515 {
3516 int rc = msrVerifyMtrrTypeGPs(uMsr, iBit, 7 + (uMsr == 0x00000277));
3517 if (RT_FAILURE(rc))
3518 return rc;
3519 }
3520 }
3521
3522 return printMsrFunctionCpumCpu(uMsr, NULL, NULL, NULL, NULL);
3523}
3524
3525
3526/**
3527 * Deals with IA32_MTRR_DEF_TYPE.
3528 *
3529 * @returns VBox status code.
3530 * @param uMsr The MSR.
3531 */
3532static int reportMsr_Ia32MtrrDefType(uint32_t uMsr)
3533{
3534 uint64_t fGpMask = 0;
3535 uint64_t fIgnMask = 0;
3536 if (g_enmMicroarch == kCpumMicroarch_AMD_K8_90nm_AMDV)
3537 {
3538 /* Problematic CPU! Fake it for now. */
3539 fGpMask = ~(uint64_t)0xc07;
3540 fIgnMask = 0;
3541 }
3542 else
3543 {
3544 int rc = msrVerifyMtrrTypeGPs(uMsr, 0, 7);
3545 if (RT_FAILURE(rc))
3546 return rc;
3547
3548 rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0x7);
3549 if (RT_FAILURE(rc))
3550 return rc;
3551 Assert(!(fGpMask & 7)); Assert(!(fIgnMask & 7));
3552 }
3553
3554 return printMsrFunctionCpumCpuEx(uMsr, NULL, NULL, NULL, fIgnMask, fGpMask, NULL);
3555}
3556
3557
3558/**
3559 * Deals with the Machine Check (MC) MSRs in the 400h+ area.
3560 *
3561 * @returns VBox status code.
3562 * @param paMsrs Pointer to the first MC MSR (400h).
3563 * @param cMsrs The number of MSRs in the array @a paMsr.
3564 * @param pidxLoop Index variable that should be advanced to the
3565 * last MC MSR entry.
3566 */
3567static int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3568{
3569 uint32_t uMsr = paMsrs[0].uMsr;
3570
3571 /* Count them. */
3572 uint32_t cRegs = 1;
3573 uint32_t cDetectedRegs = 1;
3574 while ( cDetectedRegs < cMsrs
3575 && ( paMsrs[cDetectedRegs].uMsr == uMsr + cRegs
3576 || (cRegs & 3) == 2 /* ADDR may or may not be there, depends on STATUS and CPU. */
3577 || (cRegs & 3) == 3 /* MISC may or may not be there, depends on STATUS and CPU. */
3578 || cRegs == 0x13 /* MC4_MISC may not be there, depends on CPU. */
3579 || cRegs == 0x14 /* MC5_CTL may not be there, depends on CPU. */)
3580 && cRegs < 0x7f )
3581 {
3582 if (paMsrs[cDetectedRegs].uMsr == uMsr + cRegs)
3583 cDetectedRegs++;
3584 cRegs++;
3585 }
3586 if (cRegs & 3)
3587 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MC MSR range is odd: cRegs=%#x\n", cRegs);
3588
3589 /* Just report them. We don't bother probing here as the CTL format
3590 and such seems to be a lot of work to test correctly and changes between
3591 cpu generations. */
3592 *pidxLoop += cDetectedRegs - 1;
3593 return printMsrRangeFunction(uMsr, uMsr + cRegs - 1, "Ia32McCtlStatusAddrMiscN", NULL, NULL);
3594}
3595
3596
3597
3598/**
3599 * Deals with the X2APIC msrs.
3600 *
3601 * @returns VBox status code.
3602 * @param paMsrs Pointer to the first X2APIC MSR.
3603 * @param cMsrs The number of MSRs in the array @a paMsr.
3604 * @param pidxLoop Index variable that should be advanced to the
3605 * last X2APIC MSR entry.
3606 */
3607static int reportMsr_GenX2Apic(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3608{
3609 /* Advance. */
3610 uint32_t cRegs = 1;
3611 while ( cRegs < cMsrs
3612 && paMsrs[cRegs].uMsr <= 0x8ff)
3613 cRegs++;
3614 *pidxLoop += cRegs - 1;
3615
3616 /* Just emit an X2APIC range. */
3617 return printMsrRangeFunction(0x800, 0x8ff, "Ia32X2ApicN", NULL, NULL);
3618}
3619
3620
3621/**
3622 * Deals carefully with the EFER register.
3623 *
3624 * @returns VBox status code.
3625 * @param uMsr The MSR number.
3626 * @param uValue The current value.
3627 */
3628static int reportMsr_Amd64Efer(uint32_t uMsr, uint64_t uValue)
3629{
3630 uint64_t fSkipMask = 0;
3631 if (vbCpuRepSupportsLongMode())
3632 fSkipMask |= MSR_K6_EFER_LME;
3633 if ( (uValue & MSR_K6_EFER_NXE)
3634 || vbCpuRepSupportsNX())
3635 fSkipMask |= MSR_K6_EFER_NXE;
3636
3637 /* NetBurst prescott 2MB (model 4) hung or triple faulted here. The extra
3638 sleep or something seemed to help for some screwed up reason. */
3639 if (g_fIntelNetBurst)
3640 {
3641 // This doesn't matter:
3642 //fSkipMask |= MSR_K6_EFER_SCE;
3643 //if (vbCpuRepSupportsLongMode())
3644 // fSkipMask |= MSR_K6_EFER_LMA;
3645 //vbCpuRepDebug("EFER - netburst workaround - ignore SCE & LMA (fSkipMask=%#llx)\n", fSkipMask);
3646
3647 vbCpuRepDebug("EFER - netburst sleep fudge - fSkipMask=%#llx\n", fSkipMask);
3648 RTThreadSleep(1000);
3649 }
3650
3651 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, MSR_K6_EFER_LMA, NULL);
3652}
3653
3654
3655/**
3656 * Deals with the MC4_MISCn (n >= 1) range and the following reserved MSRs.
3657 *
3658 * @returns VBox status code.
3659 * @param paMsrs Pointer to the first MSR.
3660 * @param cMsrs The number of MSRs in the array @a paMsr.
3661 * @param pidxLoop Index variable that should be advanced to the
3662 * last MSR entry in the range.
3663 */
3664static int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3665{
3666 /* Count registers. */
3667 uint32_t cRegs = 1;
3668 while ( cRegs < cMsrs
3669 && cRegs < 8
3670 && paMsrs[cRegs].uMsr == paMsrs[0].uMsr + cRegs)
3671 cRegs++;
3672
3673 /* Probe & report used MSRs. */
3674 uint64_t fIgnMask = 0;
3675 uint64_t fGpMask = 0;
3676 uint32_t cUsed = 0;
3677 while (cUsed < cRegs)
3678 {
3679 uint64_t fIgnMaskN = 0;
3680 uint64_t fGpMaskN = 0;
3681 int rc = msrProberModifyBitChanges(paMsrs[cUsed].uMsr, &fIgnMaskN, &fGpMaskN, 0);
3682 if (RT_FAILURE(rc))
3683 return rc;
3684 if (fIgnMaskN == UINT64_MAX || fGpMaskN == UINT64_MAX)
3685 break;
3686 if (cUsed == 0)
3687 {
3688 fIgnMask = fIgnMaskN;
3689 fGpMask = fGpMaskN;
3690 }
3691 else if ( fIgnMaskN != fIgnMask
3692 || fGpMaskN != fGpMask)
3693 return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
3694 fIgnMaskN, fIgnMask, fGpMaskN, fGpMask, paMsrs[cUsed].uMsr);
3695 cUsed++;
3696 }
3697 if (cUsed > 0)
3698 printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
3699
3700 /* Probe & report reserved MSRs. */
3701 uint32_t cReserved = 0;
3702 while (cUsed + cReserved < cRegs)
3703 {
3704 fIgnMask = fGpMask = 0;
3705 int rc = msrProberModifyBitChanges(paMsrs[cUsed + cReserved].uMsr, &fIgnMask, &fGpMask, 0);
3706 if (RT_FAILURE(rc))
3707 return rc;
3708 if ((fIgnMask != UINT64_MAX && fGpMask != UINT64_MAX) || paMsrs[cUsed + cReserved].uValue)
3709 return RTMsgErrorRc(VERR_NOT_EQUAL,
3710 "Unexpected reserved AmdFam16hMc4MiscN: fIgn=%#llx fGp=%#llx uMsr=%#x uValue=%#llx\n",
3711 fIgnMask, fGpMask, paMsrs[cUsed + cReserved].uMsr, paMsrs[cUsed + cReserved].uValue);
3712 cReserved++;
3713 }
3714 if (cReserved > 0 && fIgnMask == UINT64_MAX)
3715 printMsrRangeValueIgnoreWrites(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3716 else if (cReserved > 0 && fGpMask == UINT64_MAX)
3717 printMsrRangeValueReadOnly(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
3718
3719 *pidxLoop += cRegs - 1;
3720 return VINF_SUCCESS;
3721}
3722
3723
3724/**
3725 * Deals with the AMD PERF_CTL range.
3726 *
3727 * @returns VBox status code.
3728 * @param paMsrs Pointer to the first MSR.
3729 * @param cMsrs The number of MSRs in the array @a paMsr.
3730 * @param pidxLoop Index variable that should be advanced to the
3731 * last MSR entry in the range.
3732 */
3733static int reportMsr_AmdK8PerfCtlN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3734{
3735 uint32_t uMsr = paMsrs[0].uMsr;
3736 Assert(uMsr == 0xc0010000);
3737
3738 /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3739 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3740 {
3741 for (uint32_t i = 0; i < 4; i++)
3742 printMsrAlias(uMsr + i, 0xc0010200 + i * 2, NULL);
3743 *pidxLoop += 3;
3744 }
3745 else
3746 return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtlN", pidxLoop);
3747 return VINF_SUCCESS;
3748}
3749
3750
3751/**
3752 * Deals with the AMD PERF_CTR range.
3753 *
3754 * @returns VBox status code.
3755 * @param paMsrs Pointer to the first MSR.
3756 * @param cMsrs The number of MSRs in the array @a paMsr.
3757 * @param pidxLoop Index variable that should be advanced to the
3758 * last MSR entry in the range.
3759 */
3760static int reportMsr_AmdK8PerfCtrN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3761{
3762 uint32_t uMsr = paMsrs[0].uMsr;
3763 Assert(uMsr == 0xc0010004);
3764
3765 /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
3766 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3767 {
3768 for (uint32_t i = 0; i < 4; i++)
3769 printMsrAlias(uMsr + i, 0xc0010201 + i * 2, NULL);
3770 *pidxLoop += 3;
3771 }
3772 else
3773 return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtrN", pidxLoop);
3774 return VINF_SUCCESS;
3775}
3776
3777
3778/**
3779 * Deals carefully with the SYS_CFG register.
3780 *
3781 * @returns VBox status code.
3782 * @param uMsr The MSR number.
3783 * @param uValue The current value.
3784 */
3785static int reportMsr_AmdK8SysCfg(uint32_t uMsr, uint64_t uValue)
3786{
3787 uint64_t fSkipMask = 0;
3788
3789 /* Bit 21 (MtrrTom2En) is marked reserved in family 0fh, while in family
3790 10h BKDG this changes (as does the document style). Testing this bit
3791 causes bulldozer running win64 to restart, thus this special treatment. */
3792 if (g_enmMicroarch >= kCpumMicroarch_AMD_K10)
3793 fSkipMask |= RT_BIT(21);
3794
3795 /* Turns out there are more killer bits here, at least on Opteron 2384.
3796 Skipping all known bits. */
3797 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV /* Not sure when introduced - harmless? */)
3798 fSkipMask |= RT_BIT(22); /* Tom2ForceMemTypeWB */
3799 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3800 fSkipMask |= RT_BIT(21); /* MtrrTom2En */
3801 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3802 fSkipMask |= RT_BIT(20); /* MtrrVarDramEn*/
3803 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3804 fSkipMask |= RT_BIT(19); /* MtrrFixDramModEn */
3805 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3806 fSkipMask |= RT_BIT(18); /* MtrrFixDramEn */
3807 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3808 fSkipMask |= RT_BIT(17); /* SysUcLockEn */
3809 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
3810 fSkipMask |= RT_BIT(16); /* ChgToDirtyDis */
3811 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3812 fSkipMask |= RT_BIT(10); /* SetDirtyEnO */
3813 if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
3814 fSkipMask |= RT_BIT(9); /* SetDirtyEnS */
3815 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3816 || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3817 fSkipMask |= RT_BIT(8); /* SetDirtyEnE */
3818 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3819 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3820 fSkipMask |= RT_BIT(7) /* SysVicLimit */
3821 | RT_BIT(6) /* SysVicLimit */
3822 | RT_BIT(5) /* SysVicLimit */
3823 | RT_BIT(4) /* SysAckLimit */
3824 | RT_BIT(3) /* SysAckLimit */
3825 | RT_BIT(2) /* SysAckLimit */
3826 | RT_BIT(1) /* SysAckLimit */
3827 | RT_BIT(0) /* SysAckLimit */;
3828
3829 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3830}
3831
3832
3833/**
3834 * Deals carefully with the HWCR register.
3835 *
3836 * @returns VBox status code.
3837 * @param uMsr The MSR number.
3838 * @param uValue The current value.
3839 */
3840static int reportMsr_AmdK8HwCr(uint32_t uMsr, uint64_t uValue)
3841{
3842 uint64_t fSkipMask = 0;
3843
3844 /* Trouble on Opteron 2384, skip some of the known bits. */
3845 if (g_enmMicroarch >= kCpumMicroarch_AMD_K10 && !CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch))
3846 fSkipMask |= /*RT_BIT(10)*/ 0 /* MonMwaitUserEn */
3847 | RT_BIT(9); /* MonMwaitDis */
3848 fSkipMask |= RT_BIT(8); /* #IGNNE port emulation */
3849 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3850 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3851 fSkipMask |= RT_BIT(7) /* DisLock */
3852 | RT_BIT(6); /* FFDis (TLB flush filter) */
3853 fSkipMask |= RT_BIT(4); /* INVD to WBINVD */
3854 fSkipMask |= RT_BIT(3); /* TLBCACHEDIS */
3855 if ( CPUMMICROARCH_IS_AMD_FAM_0FH(g_enmMicroarch)
3856 || CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3857 || CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
3858 fSkipMask |= RT_BIT(1); /* SLOWFENCE */
3859 fSkipMask |= RT_BIT(0); /* SMMLOCK */
3860
3861 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3862}
3863
3864
3865/**
3866 * Deals carefully with a IORRBasei register.
3867 *
3868 * @returns VBox status code.
3869 * @param uMsr The MSR number.
3870 * @param uValue The current value.
3871 */
3872static int reportMsr_AmdK8IorrBaseN(uint32_t uMsr, uint64_t uValue)
3873{
3874 /* Skip know bits here, as harm seems to come from messing with them. */
3875 uint64_t fSkipMask = RT_BIT(4) | RT_BIT(3);
3876 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3877 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, 0, annotateValue(uValue));
3878}
3879
3880
3881/**
3882 * Deals carefully with a IORRMaski register.
3883 *
3884 * @returns VBox status code.
3885 * @param uMsr The MSR number.
3886 * @param uValue The current value.
3887 */
3888static int reportMsr_AmdK8IorrMaskN(uint32_t uMsr, uint64_t uValue)
3889{
3890 /* Skip know bits here, as harm seems to come from messing with them. */
3891 uint64_t fSkipMask = RT_BIT(11);
3892 fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
3893 return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, 0, annotateValue(uValue));
3894}
3895
3896
3897/**
3898 * Deals carefully with a IORRMaski register.
3899 *
3900 * @returns VBox status code.
3901 * @param uMsr The MSR number.
3902 * @param uValue The current value.
3903 */
3904static int reportMsr_AmdK8TopMemN(uint32_t uMsr, uint64_t uValue)
3905{
3906 /* Skip know bits here, as harm seems to come from messing with them. */
3907 uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1);
3908 return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, 0, annotateValue(uValue));
3909}
3910
3911
3912/**
3913 * Deals with the AMD P-state config range.
3914 *
3915 * @returns VBox status code.
3916 * @param paMsrs Pointer to the first MSR.
3917 * @param cMsrs The number of MSRs in the array @a paMsr.
3918 * @param pidxLoop Index variable that should be advanced to the
3919 * last MSR entry in the range.
3920 */
3921static int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
3922{
3923 uint32_t uMsr = paMsrs[0].uMsr;
3924 AssertRelease(uMsr == 0xc0010064);
3925
3926 /* Count them. */
3927 uint32_t cRegs = 1;
3928 while ( cRegs < 8
3929 && cRegs < cMsrs
3930 && paMsrs[cRegs].uMsr == uMsr + cRegs)
3931 cRegs++;
3932
3933 /* Figure out which bits we should skip when probing. This is based on
3934 specs and may need adjusting for real life when handy. */
3935 uint64_t fSkipMask = RT_BIT_64(63); /* PstateEn */
3936 fSkipMask |= RT_BIT_64(41) | RT_BIT_64(40); /* IddDiv */
3937 fSkipMask |= UINT64_C(0x000000ff00000000); /* IddValue */
3938 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3939 fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
3940 if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3941 || CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
3942 fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
3943 if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
3944 fSkipMask |= RT_BIT_32(16); /* CpuVid[7] */
3945 fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
3946 fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
3947 fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
3948
3949 /* Probe and report them one by one since we're passing values instead of
3950 register indexes to the functions. */
3951 for (uint32_t i = 0; i < cRegs; i++)
3952 {
3953 uint64_t fIgnMask = 0;
3954 uint64_t fGpMask = 0;
3955 int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, fSkipMask);
3956 if (RT_FAILURE(rc))
3957 return rc;
3958 printMsrFunctionExtended(uMsr + i, "AmdFam10hPStateN", NULL, paMsrs[i].uValue, fIgnMask, fGpMask,
3959 annotateValue(paMsrs[i].uValue));
3960 }
3961
3962 /* Advance. */
3963 *pidxLoop += cRegs - 1;
3964 return VINF_SUCCESS;
3965}
3966
3967
3968/**
3969 * Deals carefully with a COFVID control register.
3970 *
3971 * @returns VBox status code.
3972 * @param uMsr The MSR number.
3973 * @param uValue The current value.
3974 */
3975static int reportMsr_AmdFam10hCofVidControl(uint32_t uMsr, uint64_t uValue)
3976{
3977 /* Skip know bits here, as harm seems to come from messing with them. */
3978 uint64_t fSkipMask = 0;
3979 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
3980 fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
3981 else if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
3982 fSkipMask |= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
3983 if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
3984 || g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
3985 fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
3986 if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
3987 fSkipMask |= RT_BIT_32(20); /* CpuVid[7] */
3988 fSkipMask |= UINT32_C(0x00070000); /* PstatId */
3989 fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
3990 fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
3991 fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
3992
3993 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
3994}
3995
3996
3997/**
3998 * Deals with the AMD [|L2I_|NB_]PERF_CT[LR] mixed ranges.
3999 *
4000 * Mixed here refers to the control and counter being in mixed in pairs as
4001 * opposed to them being two separate parallel arrays like in the 0xc0010000
4002 * area.
4003 *
4004 * @returns VBox status code.
4005 * @param paMsrs Pointer to the first MSR.
4006 * @param cMsrs The number of MSRs in the array @a paMsr.
4007 * @param cMax The max number of MSRs (not counters).
4008 * @param pidxLoop Index variable that should be advanced to the
4009 * last MSR entry in the range.
4010 */
4011static int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t *pidxLoop)
4012{
4013 uint32_t uMsr = paMsrs[0].uMsr;
4014
4015 /* Count them. */
4016 uint32_t cRegs = 1;
4017 while ( cRegs < cMax
4018 && cRegs < cMsrs
4019 && paMsrs[cRegs].uMsr == uMsr + cRegs)
4020 cRegs++;
4021 if (cRegs & 1)
4022 return RTMsgErrorRc(VERR_INVALID_PARAMETER, "PERF range at %#x is odd: cRegs=%#x\n", uMsr, cRegs);
4023
4024 /* Report them as individual entries, using default names and such. */
4025 for (uint32_t i = 0; i < cRegs; i++)
4026 {
4027 uint64_t fIgnMask = 0;
4028 uint64_t fGpMask = 0;
4029 int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, 0);
4030 if (RT_FAILURE(rc))
4031 return rc;
4032 printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
4033 }
4034
4035 /* Advance. */
4036 *pidxLoop += cRegs - 1;
4037 return VINF_SUCCESS;
4038}
4039
4040
4041/**
4042 * Deals carefully with a LS_CFG register.
4043 *
4044 * @returns VBox status code.
4045 * @param uMsr The MSR number.
4046 * @param uValue The current value.
4047 */
4048static int reportMsr_AmdK7InstrCacheCfg(uint32_t uMsr, uint64_t uValue)
4049{
4050 /* Skip know bits here, as harm seems to come from messing with them. */
4051 uint64_t fSkipMask = RT_BIT_64(9) /* DIS_SPEC_TLB_RLD */;
4052 if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
4053 fSkipMask |= RT_BIT_64(14); /* DIS_IND */
4054 if (CPUMMICROARCH_IS_AMD_FAM_16H(g_enmMicroarch))
4055 fSkipMask |= RT_BIT_64(26); /* DIS_WIDEREAD_PWR_SAVE */
4056 if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4057 {
4058 fSkipMask |= 0x1e; /* DisIcWayFilter */
4059 fSkipMask |= RT_BIT_64(39); /* DisLoopPredictor */
4060 fSkipMask |= RT_BIT_64(27); /* Unknown killer bit, possibly applicable to other microarchs. */
4061 fSkipMask |= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */
4062 }
4063 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4064}
4065
4066
4067/**
4068 * Deals carefully with a CU_CFG register.
4069 *
4070 * @returns VBox status code.
4071 * @param uMsr The MSR number.
4072 * @param uValue The current value.
4073 */
4074static int reportMsr_AmdFam15hCombUnitCfg(uint32_t uMsr, uint64_t uValue)
4075{
4076 /* Skip know bits here, as harm seems to come from messing with them. */
4077 uint64_t fSkipMask = RT_BIT_64(23) /* L2WayLock */
4078 | RT_BIT_64(22) /* L2FirstLockWay */
4079 | RT_BIT_64(21) /* L2FirstLockWay */
4080 | RT_BIT_64(20) /* L2FirstLockWay */
4081 | RT_BIT_64(19) /* L2FirstLockWay */
4082 | RT_BIT_64(10) /* DcacheAggressivePriority */;
4083 fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
4084 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4085}
4086
4087
4088/**
4089 * Deals carefully with a EX_CFG register.
4090 *
4091 * @returns VBox status code.
4092 * @param uMsr The MSR number.
4093 * @param uValue The current value.
4094 */
4095static int reportMsr_AmdFam15hExecUnitCfg(uint32_t uMsr, uint64_t uValue)
4096{
4097 /* Skip know bits here, as harm seems to come from messing with them. */
4098 uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */;
4099 fSkipMask |= RT_BIT_64(35); /* Undocumented killer bit. */
4100 return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
4101}
4102
4103
4104
4105static int produceMsrReport(VBCPUREPMSR *paMsrs, uint32_t cMsrs)
4106{
4107 vbCpuRepDebug("produceMsrReport\n");
4108 RTThreadSleep(500);
4109
4110 for (uint32_t i = 0; i < cMsrs; i++)
4111 {
4112 uint32_t uMsr = paMsrs[i].uMsr;
4113 uint32_t fFlags = paMsrs[i].fFlags;
4114 uint64_t uValue = paMsrs[i].uValue;
4115 int rc;
4116#if 0
4117 //if (uMsr < 0x00000000)
4118 // continue;
4119 if (uMsr >= 0x00000277)
4120 {
4121 vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
4122 RTThreadSleep(1000);
4123 }
4124#endif
4125 /*
4126 * Deal with write only regs first to avoid having to avoid them all the time.
4127 */
4128 if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
4129 {
4130 if (uMsr == 0x00000079)
4131 rc = printMsrWriteOnly(uMsr, NULL, NULL);
4132 else
4133 rc = reportMsr_Generic(uMsr, fFlags, uValue);
4134 }
4135 /*
4136 * VIA implement MSRs in a interesting way, so we have to select what we
4137 * want to handle there to avoid making the code below unreadable.
4138 */
4139 else if (isMsrViaDummy(uMsr, uValue, fFlags))
4140 rc = reportMsr_ViaDummyRange(&paMsrs[i], cMsrs - i, &i);
4141 /*
4142 * This shall be sorted by uMsr as much as possible.
4143 */
4144 else if (uMsr == 0x00000000 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
4145 rc = printMsrAlias(uMsr, 0x00000402, NULL);
4146 else if (uMsr == 0x00000001 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
4147 rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
4148 else if (uMsr == 0x0000001b)
4149 rc = reportMsr_Ia32ApicBase(uMsr, uValue);
4150 else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan)
4151 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i);
4152 else if (uMsr == 0x00000040)
4153 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false,
4154 true, getGenericSkipMask(uMsr), &i);
4155 else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
4156 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false,
4157 true, getGenericSkipMask(uMsr), &i);
4158 else if (uMsr == 0x000000c1)
4159 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i,
4160 g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? 8 : 4 /*cMax*/,
4161 NULL, &i);
4162 else if (uMsr == 0x00000186 && !g_fIntelNetBurst)
4163 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "Ia32PerfEvtSelN", &i);
4164 else if (uMsr == 0x000001a0)
4165 rc = reportMsr_Ia32MiscEnable(uMsr, uValue);
4166 else if (uMsr >= 0x000001a6 && uMsr <= 0x000001a7)
4167 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
4168 else if (uMsr == 0x000001db && g_fIntelNetBurst)
4169 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4 /*cMax*/, "IntelLastBranchFromToN", &i);
4170 else if (uMsr == 0x00000200)
4171 rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
4172 else if (uMsr >= 0x00000250 && uMsr <= 0x00000279)
4173 rc = reportMsr_Ia32MtrrFixedOrPat(uMsr);
4174 else if (uMsr >= 0x00000280 && uMsr <= 0x00000295)
4175 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i);
4176 else if (uMsr == 0x000002ff)
4177 rc = reportMsr_Ia32MtrrDefType(uMsr);
4178 else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b && !g_fIntelNetBurst)
4179 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
4180 else if ((uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a) && !g_fIntelNetBurst)
4181 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
4182 else if ((uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b) && !g_fIntelNetBurst)
4183 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
4184 else if ((uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c) && !g_fIntelNetBurst)
4185 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
4186 else if (uMsr >= 0x00000400 && uMsr <= 0x00000477)
4187 rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i);
4188 else if (uMsr == 0x000004c1)
4189 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
4190 else if (uMsr == 0x00000680 || uMsr == 0x000006c0)
4191 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false,
4192 g_fIntelNetBurst
4193 ? UINT64_C(0xffffffffffffff00) /* kludge */
4194 : UINT64_C(0xffff800000000000), &i);
4195 else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff)
4196 rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
4197 else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4198 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG, 0,
4199 annotateIfMissingBits(uValue, X86_CR0_PE | X86_CR0_PE | X86_CR0_ET));
4200 else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4201 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, 0, annotateValue(uValue));
4202 else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4203 {
4204 uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK);
4205 if (!vbCpuRepSupportsPae())
4206 fCr3Mask &= X86_CR3_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK;
4207 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, 0, annotateValue(uValue));
4208 }
4209 else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL)
4210 rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4,
4211 X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE, 0,
4212 annotateValue(uValue));
4213 else if (uMsr == 0xc0000080)
4214 rc = reportMsr_Amd64Efer(uMsr, uValue);
4215 else if (uMsr >= 0xc0000408 && uMsr <= 0xc000040f)
4216 rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
4217 else if (uMsr == 0xc0010000 && g_enmVendor == CPUMCPUVENDOR_AMD)
4218 rc = reportMsr_AmdK8PerfCtlN(&paMsrs[i], cMsrs - i, &i);
4219 else if (uMsr == 0xc0010004 && g_enmVendor == CPUMCPUVENDOR_AMD)
4220 rc = reportMsr_AmdK8PerfCtrN(&paMsrs[i], cMsrs - i, &i);
4221 else if (uMsr == 0xc0010010 && g_enmVendor == CPUMCPUVENDOR_AMD)
4222 rc = reportMsr_AmdK8SysCfg(uMsr, uValue);
4223 else if (uMsr == 0xc0010015 && g_enmVendor == CPUMCPUVENDOR_AMD)
4224 rc = reportMsr_AmdK8HwCr(uMsr, uValue);
4225 else if ((uMsr == 0xc0010016 || uMsr == 0xc0010018) && g_enmVendor == CPUMCPUVENDOR_AMD)
4226 rc = reportMsr_AmdK8IorrBaseN(uMsr, uValue);
4227 else if ((uMsr == 0xc0010017 || uMsr == 0xc0010019) && g_enmVendor == CPUMCPUVENDOR_AMD)
4228 rc = reportMsr_AmdK8IorrMaskN(uMsr, uValue);
4229 else if ((uMsr == 0xc001001a || uMsr == 0xc001001d) && g_enmVendor == CPUMCPUVENDOR_AMD)
4230 rc = reportMsr_AmdK8TopMemN(uMsr, uValue);
4231 else if (uMsr == 0xc0010030 && g_enmVendor == CPUMCPUVENDOR_AMD)
4232 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i);
4233 else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a && g_enmVendor == CPUMCPUVENDOR_AMD)
4234 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i);
4235 else if (uMsr == 0xc0010050 && g_enmVendor == CPUMCPUVENDOR_AMD)
4236 rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i);
4237 else if (uMsr == 0xc0010064 && g_enmVendor == CPUMCPUVENDOR_AMD)
4238 rc = reportMsr_AmdFam10hPStateN(&paMsrs[i], cMsrs - i, &i);
4239 else if (uMsr == 0xc0010070 && g_enmVendor == CPUMCPUVENDOR_AMD)
4240 rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
4241 else if ((uMsr == 0xc0010118 || uMsr == 0xc0010119) && getMsrFnName(uMsr, NULL) && g_enmVendor == CPUMCPUVENDOR_AMD)
4242 rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
4243 else if (uMsr == 0xc0010200 && g_enmVendor == CPUMCPUVENDOR_AMD)
4244 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 12, &i);
4245 else if (uMsr == 0xc0010230 && g_enmVendor == CPUMCPUVENDOR_AMD)
4246 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4247 else if (uMsr == 0xc0010240 && g_enmVendor == CPUMCPUVENDOR_AMD)
4248 rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
4249 else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver && g_enmVendor == CPUMCPUVENDOR_AMD)
4250 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1,
4251 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
4252 else if (uMsr == 0xc0011021 && g_enmVendor == CPUMCPUVENDOR_AMD)
4253 rc = reportMsr_AmdK7InstrCacheCfg(uMsr, uValue);
4254 else if (uMsr == 0xc0011023 && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4255 rc = reportMsr_AmdFam15hCombUnitCfg(uMsr, uValue);
4256 else if (uMsr == 0xc0011027 && g_enmVendor == CPUMCPUVENDOR_AMD)
4257 rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027,
4258 false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
4259 else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
4260 rc = reportMsr_AmdFam15hExecUnitCfg(uMsr, uValue);
4261 /* generic handling. */
4262 else
4263 rc = reportMsr_Generic(uMsr, fFlags, uValue);
4264
4265 if (RT_FAILURE(rc))
4266 return rc;
4267
4268 /*
4269 * A little ugly snooping.
4270 */
4271 if (uMsr == 0x000000cd && !(fFlags & VBCPUREPMSR_F_WRITE_ONLY))
4272 g_uMsrIntelP6FsbFrequency = uValue;
4273 }
4274
4275 return VINF_SUCCESS;
4276}
4277
4278
4279/**
4280 * Custom MSR hacking & probing.
4281 *
4282 * Called when the '-d' option is given.
4283 *
4284 * @returns VBox status code.
4285 */
4286static int hackingMsrs(void)
4287{
4288#if 0
4289 vbCpuRepDebug("\nhackingMsrs:\n"); RTStrmFlush(g_pDebugOut); RTThreadSleep(2000);
4290
4291 uint32_t uMsr = 0xc0000081;
4292 vbCpuRepDebug("%#x: msrProberModifyNoChange -> %RTbool\n", uMsr, msrProberModifyNoChange(uMsr));
4293 RTThreadSleep(3000);
4294
4295 vbCpuRepDebug("%#x: msrProberModifyBit 30 -> %d\n", uMsr, msrProberModifyBit(uMsr, 30));
4296 RTThreadSleep(3000);
4297
4298 vbCpuRepDebug("%#x: msrProberModifyZero -> %RTbool\n", uMsr, msrProberModifyZero(uMsr));
4299 RTThreadSleep(3000);
4300
4301 for (uint32_t i = 0; i < 63; i++)
4302 {
4303 vbCpuRepDebug("%#x: bit=%02u -> %d\n", msrProberModifyBit(uMsr, i));
4304 RTThreadSleep(500);
4305 }
4306#else
4307
4308 uint32_t uMsr = 0xc0010010;
4309 uint64_t uValue = 0;
4310 msrProberRead(uMsr, &uValue);
4311 reportMsr_AmdK8SysCfg(uMsr, uValue);
4312#endif
4313 return VINF_SUCCESS;
4314}
4315
4316
4317static int probeMsrs(bool fHacking, const char *pszNameC, const char *pszCpuDesc,
4318 char *pszMsrMask, size_t cbMsrMask)
4319{
4320 /* Initialize the mask. */
4321 if (pszMsrMask && cbMsrMask)
4322 RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX /** @todo */");
4323
4324 /*
4325 * Are MSRs supported by the CPU?
4326 */
4327 if ( !ASMIsValidStdRange(ASMCpuId_EAX(0))
4328 || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) )
4329 {
4330 vbCpuRepDebug("Skipping MSR probing, CPUID indicates there isn't any MSR support.\n");
4331 return VINF_SUCCESS;
4332 }
4333
4334 /*
4335 * Initialize the support library and check if we can read MSRs.
4336 */
4337 int rc = SUPR3Init(NULL);
4338 if (RT_FAILURE(rc))
4339 {
4340 vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc), skipping MSR detection.\n", rc);
4341 return VINF_SUCCESS;
4342 }
4343 uint64_t uValue;
4344 bool fGp;
4345 rc = SUPR3MsrProberRead(MSR_IA32_TSC, NIL_RTCPUID, &uValue, &fGp);
4346 if (RT_FAILURE(rc))
4347 {
4348 vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
4349 return VINF_SUCCESS;
4350 }
4351 vbCpuRepDebug("MSR_IA32_TSC: %#llx fGp=%RTbool\n", uValue, fGp);
4352 rc = SUPR3MsrProberRead(0xdeadface, NIL_RTCPUID, &uValue, &fGp);
4353 vbCpuRepDebug("0xdeadface: %#llx fGp=%RTbool rc=%Rrc\n", uValue, fGp, rc);
4354
4355 /*
4356 * Initialize globals we use.
4357 */
4358 uint32_t uEax, uEbx, uEcx, uEdx;
4359 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4360 if (!ASMIsValidStdRange(uEax))
4361 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4362 g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4363
4364 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4365 g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor,
4366 ASMGetCpuFamily(uEax),
4367 ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),
4368 ASMGetCpuStepping(uEax));
4369 g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch);
4370
4371 /*
4372 * Do the probing.
4373 */
4374 if (fHacking)
4375 rc = hackingMsrs();
4376 else
4377 {
4378 /* Determine the MSR mask. */
4379 uint32_t fMsrMask = determineMsrAndMask();
4380 if (fMsrMask == UINT32_MAX)
4381 RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX");
4382 else
4383 RTStrPrintf(pszMsrMask, cbMsrMask, "UINT32_C(%#x)", fMsrMask);
4384
4385 /* Detect MSR. */
4386 VBCPUREPMSR *paMsrs;
4387 uint32_t cMsrs;
4388 rc = findMsrs(&paMsrs, &cMsrs, fMsrMask);
4389 if (RT_FAILURE(rc))
4390 return rc;
4391
4392 /* Probe the MSRs and spit out the database table. */
4393 vbCpuRepPrintf("\n"
4394 "#ifndef CPUM_DB_STANDALONE\n"
4395 "/**\n"
4396 " * MSR ranges for %s.\n"
4397 " */\n"
4398 "static CPUMMSRRANGE const g_aMsrRanges_%s[] = \n{\n",
4399 pszCpuDesc,
4400 pszNameC);
4401 rc = produceMsrReport(paMsrs, cMsrs);
4402 vbCpuRepPrintf("};\n"
4403 "#endif /* !CPUM_DB_STANDALONE */\n"
4404 "\n"
4405 );
4406
4407 RTMemFree(paMsrs);
4408 paMsrs = NULL;
4409 }
4410 return rc;
4411}
4412
4413
4414static int produceCpuIdArray(const char *pszNameC, const char *pszCpuDesc)
4415{
4416 /*
4417 * Collect the data.
4418 */
4419 PCPUMCPUIDLEAF paLeaves;
4420 uint32_t cLeaves;
4421 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
4422 if (RT_FAILURE(rc))
4423 return RTMsgErrorRc(rc, "CPUMR3CollectCpuIdInfo failed: %Rrc\n", rc);
4424
4425 /*
4426 * Dump the array.
4427 */
4428 vbCpuRepPrintf("\n"
4429 "#ifndef CPUM_DB_STANDALONE\n"
4430 "/**\n"
4431 " * CPUID leaves for %s.\n"
4432 " */\n"
4433 "static CPUMCPUIDLEAF const g_aCpuIdLeaves_%s[] = \n{\n",
4434 pszCpuDesc,
4435 pszNameC);
4436 for (uint32_t i = 0; i < cLeaves; i++)
4437 {
4438 vbCpuRepPrintf(" { %#010x, %#010x, ", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf);
4439 if (paLeaves[i].fSubLeafMask == UINT32_MAX)
4440 vbCpuRepPrintf("UINT32_MAX, ");
4441 else
4442 vbCpuRepPrintf("%#010x, ", paLeaves[i].fSubLeafMask);
4443 vbCpuRepPrintf("%#010x, %#010x, %#010x, %#010x, ",
4444 paLeaves[i].uEax, paLeaves[i].uEbx, paLeaves[i].uEcx, paLeaves[i].uEdx);
4445 if (paLeaves[i].fFlags == 0)
4446 vbCpuRepPrintf("0 },\n");
4447 else
4448 {
4449 vbCpuRepPrintf("0");
4450 uint32_t fFlags = paLeaves[i].fFlags;
4451 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES)
4452 {
4453 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES");
4454 fFlags &= ~CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES;
4455 }
4456 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
4457 {
4458 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_CONTAINS_APIC_ID");
4459 fFlags &= ~CPUMCPUIDLEAF_F_CONTAINS_APIC_ID;
4460 }
4461 if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC)
4462 {
4463 vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_CONTAINS_APIC");
4464 fFlags &= ~CPUMCPUIDLEAF_F_CONTAINS_APIC;
4465 }
4466 if (fFlags)
4467 {
4468 RTMemFree(paLeaves);
4469 return RTMsgErrorRc(rc, "Unknown CPUID flags %#x\n", fFlags);
4470 }
4471 vbCpuRepPrintf(" },\n");
4472 }
4473 }
4474 vbCpuRepPrintf("};\n"
4475 "#endif /* !CPUM_DB_STANDALONE */\n"
4476 "\n");
4477 RTMemFree(paLeaves);
4478 return VINF_SUCCESS;
4479}
4480
4481
4482static const char *cpuVendorToString(CPUMCPUVENDOR enmCpuVendor)
4483{
4484 switch (enmCpuVendor)
4485 {
4486 case CPUMCPUVENDOR_INTEL: return "Intel";
4487 case CPUMCPUVENDOR_AMD: return "AMD";
4488 case CPUMCPUVENDOR_VIA: return "VIA";
4489 case CPUMCPUVENDOR_CYRIX: return "Cyrix";
4490 case CPUMCPUVENDOR_INVALID:
4491 case CPUMCPUVENDOR_UNKNOWN:
4492 case CPUMCPUVENDOR_32BIT_HACK:
4493 break;
4494 }
4495 return "invalid-cpu-vendor";
4496}
4497
4498
4499/**
4500 * Takes a shot a the bus frequency name (last part).
4501 *
4502 * @returns Name suffix.
4503 */
4504static const char *vbCpuRepGuessScalableBusFrequencyName(void)
4505{
4506 if (CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch))
4507 return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge ? "100MHZ" : "133MHZ";
4508
4509 if (g_uMsrIntelP6FsbFrequency != UINT64_MAX)
4510 switch (g_uMsrIntelP6FsbFrequency & 0x7)
4511 {
4512 case 5: return "100MHZ";
4513 case 1: return "133MHZ";
4514 case 3: return "167MHZ";
4515 case 2: return "200MHZ";
4516 case 0: return "267MHZ";
4517 case 4: return "333MHZ";
4518 case 6: return "400MHZ";
4519 }
4520
4521 return "UNKNOWN";
4522}
4523
4524
4525static int produceCpuReport(void)
4526{
4527 /*
4528 * Figure the cpu vendor.
4529 */
4530 if (!ASMHasCpuId())
4531 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "No CPUID support.\n");
4532 uint32_t uEax, uEbx, uEcx, uEdx;
4533 ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4534 if (!ASMIsValidStdRange(uEax))
4535 return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
4536
4537 CPUMCPUVENDOR enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
4538 if (enmVendor == CPUMCPUVENDOR_UNKNOWN)
4539 return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
4540 vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
4541
4542 /*
4543 * Determine the micro arch.
4544 */
4545 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4546 CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor,
4547 ASMGetCpuFamily(uEax),
4548 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4549 ASMGetCpuStepping(uEax));
4550
4551 /*
4552 * Generate a name.
4553 */
4554 char szName[16*3+1];
4555 char szNameC[16*3+1];
4556 char szNameRaw[16*3+1];
4557 char *pszName = szName;
4558 char *pszCpuDesc = (char *)"";
4559
4560 ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4561 if (ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))
4562 {
4563 /* Get the raw name and strip leading spaces. */
4564 ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
4565 ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
4566 ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
4567 szNameRaw[48] = '\0';
4568 pszCpuDesc = RTStrStrip(szNameRaw);
4569 vbCpuRepDebug("Name2: %s\n", pszCpuDesc);
4570
4571 /* Reduce the name. */
4572 pszName = strcpy(szName, pszCpuDesc);
4573
4574 static const char * const s_apszSuffixes[] =
4575 {
4576 "CPU @",
4577 };
4578 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszSuffixes); i++)
4579 {
4580 char *pszHit = strstr(pszName, s_apszSuffixes[i]);
4581 if (pszHit)
4582 RT_BZERO(pszHit, strlen(pszHit));
4583 }
4584
4585 static const char * const s_apszWords[] =
4586 {
4587 "(TM)", "(tm)", "(R)", "(r)", "Processor", "CPU", "@",
4588 };
4589 for (uint32_t i = 0; i < RT_ELEMENTS(s_apszWords); i++)
4590 {
4591 const char *pszWord = s_apszWords[i];
4592 size_t cchWord = strlen(pszWord);
4593 char *pszHit;
4594 while ((pszHit = strstr(pszName, pszWord)) != NULL)
4595 memmove(pszHit, pszHit + cchWord, strlen(pszHit + cchWord) + 1);
4596 }
4597
4598 RTStrStripR(pszName);
4599 for (char *psz = pszName; *psz; psz++)
4600 if (RT_C_IS_BLANK(*psz))
4601 {
4602 size_t cchBlanks = 1;
4603 while (RT_C_IS_BLANK(psz[cchBlanks]))
4604 cchBlanks++;
4605 *psz = ' ';
4606 if (cchBlanks > 1)
4607 memmove(psz + 1, psz + cchBlanks, strlen(psz + cchBlanks) + 1);
4608 }
4609 pszName = RTStrStripL(pszName);
4610 vbCpuRepDebug("Name: %s\n", pszName);
4611
4612 /* Make it C/C++ acceptable. */
4613 strcpy(szNameC, pszName);
4614 unsigned offDst = 0;
4615 for (unsigned offSrc = 0; ; offSrc++)
4616 {
4617 char ch = szNameC[offSrc];
4618 if (!RT_C_IS_ALNUM(ch) && ch != '_' && ch != '\0')
4619 ch = '_';
4620 if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
4621 offDst--;
4622 szNameC[offDst++] = ch;
4623 if (!ch)
4624 break;
4625 }
4626 while (offDst > 1 && szNameC[offDst - 1] == '_')
4627 szNameC[--offDst] = '\0';
4628
4629 vbCpuRepDebug("NameC: %s\n", szNameC);
4630 }
4631 else
4632 {
4633 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4634 RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
4635 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));
4636 pszCpuDesc = pszName = szNameC;
4637 vbCpuRepDebug("Name/NameC: %s\n", szNameC);
4638 }
4639
4640 /*
4641 * Print a file header, if we're not outputting to stdout (assumption being
4642 * that stdout is used while hacking the reporter and too much output is
4643 * unwanted).
4644 */
4645 if (g_pReportOut)
4646 {
4647 RTTIMESPEC Now;
4648 char szNow[64];
4649 RTTimeSpecToString(RTTimeNow(&Now), szNow, sizeof(szNow));
4650 char *pchDot = strchr(szNow, '.');
4651 if (pchDot)
4652 strcpy(pchDot, "Z");
4653
4654 vbCpuRepPrintf("/* $" "Id" "$ */\n"
4655 "/** @file\n"
4656 " * CPU database entry \"%s\".\n"
4657 " * Generated at %s by VBoxCpuReport v%sr%s on %s.%s.\n"
4658 " */\n"
4659 "\n"
4660 "/*\n"
4661 " * Copyright (C) 2013-2016 Oracle Corporation\n"
4662 " *\n"
4663 " * This file is part of VirtualBox Open Source Edition (OSE), as\n"
4664 " * available from http://www.virtualbox.org. This file is free software;\n"
4665 " * you can redistribute it and/or modify it under the terms of the GNU\n"
4666 " * General Public License (GPL) as published by the Free Software\n"
4667 " * Foundation, in version 2 as it comes in the \"COPYING\" file of the\n"
4668 " * VirtualBox OSE distribution. VirtualBox OSE is distributed in the\n"
4669 " * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.\n"
4670 " */\n"
4671 "\n"
4672 "#ifndef VBOX_CPUDB_%s\n"
4673 "#define VBOX_CPUDB_%s\n"
4674 "\n",
4675 pszName,
4676 szNow, RTBldCfgVersion(), RTBldCfgRevisionStr(), RTBldCfgTarget(), RTBldCfgTargetArch(),
4677 szNameC, szNameC);
4678 }
4679
4680 /*
4681 * Extract CPUID based data.
4682 */
4683 int rc = produceCpuIdArray(szNameC, pszCpuDesc);
4684 if (RT_FAILURE(rc))
4685 return rc;
4686
4687 CPUMUNKNOWNCPUID enmUnknownMethod;
4688 CPUMCPUID DefUnknown;
4689 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&enmUnknownMethod, &DefUnknown);
4690 if (RT_FAILURE(rc))
4691 return RTMsgErrorRc(rc, "CPUMR3DetectCpuIdUnknownMethod failed: %Rrc\n", rc);
4692 vbCpuRepDebug("enmUnknownMethod=%s\n", CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod));
4693
4694 /*
4695 * Do the MSRs, if we can.
4696 */
4697 char szMsrMask[64];
4698 probeMsrs(false /*fHacking*/, szNameC, pszCpuDesc, szMsrMask, sizeof(szMsrMask));
4699
4700 /*
4701 * Emit the CPUMDBENTRY record.
4702 */
4703 ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
4704 vbCpuRepPrintf("\n"
4705 "/**\n"
4706 " * Database entry for %s.\n"
4707 " */\n"
4708 "static CPUMDBENTRY const g_Entry_%s = \n"
4709 "{\n"
4710 " /*.pszName = */ \"%s\",\n"
4711 " /*.pszFullName = */ \"%s\",\n"
4712 " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
4713 " /*.uFamily = */ %u,\n"
4714 " /*.uModel = */ %u,\n"
4715 " /*.uStepping = */ %u,\n"
4716 " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
4717 " /*.uScalableBusFreq = */ CPUM_SBUSFREQ_%s,\n"
4718 " /*.fFlags = */ 0,\n"
4719 " /*.cMaxPhysAddrWidth= */ %u,\n"
4720 " /*.paCpuIdLeaves = */ NULL_ALONE(g_aCpuIdLeaves_%s),\n"
4721 " /*.cCpuIdLeaves = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_%s)),\n"
4722 " /*.enmUnknownCpuId = */ CPUMUNKNOWNCPUID_%s,\n"
4723 " /*.DefUnknownCpuId = */ { %#010x, %#010x, %#010x, %#010x },\n"
4724 " /*.fMsrMask = */ %s,\n"
4725 " /*.cMsrRanges = */ ZERO_ALONE(RT_ELEMENTS(g_aMsrRanges_%s)),\n"
4726 " /*.paMsrRanges = */ NULL_ALONE(g_aMsrRanges_%s),\n"
4727 "};\n"
4728 "\n"
4729 "#endif /* !VBOX_DB_%s */\n"
4730 "\n",
4731 pszCpuDesc,
4732 szNameC,
4733 pszName,
4734 pszCpuDesc,
4735 CPUMR3CpuVendorName(enmVendor),
4736 ASMGetCpuFamily(uEax),
4737 ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
4738 ASMGetCpuStepping(uEax),
4739 CPUMR3MicroarchName(enmMicroarch),
4740 vbCpuRepGuessScalableBusFrequencyName(),
4741 vbCpuRepGetPhysAddrWidth(),
4742 szNameC,
4743 szNameC,
4744 CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod),
4745 DefUnknown.uEax,
4746 DefUnknown.uEbx,
4747 DefUnknown.uEcx,
4748 DefUnknown.uEdx,
4749 szMsrMask,
4750 szNameC,
4751 szNameC,
4752 szNameC
4753 );
4754
4755 return VINF_SUCCESS;
4756}
4757
4758
4759int main(int argc, char **argv)
4760{
4761 int rc = RTR3InitExe(argc, &argv, 0 /*fFlags*/);
4762 if (RT_FAILURE(rc))
4763 return RTMsgInitFailure(rc);
4764
4765 /*
4766 * Argument parsing?
4767 */
4768 static const RTGETOPTDEF s_aOptions[] =
4769 {
4770 { "--msrs-only", 'm', RTGETOPT_REQ_NOTHING },
4771 { "--msrs-dev", 'd', RTGETOPT_REQ_NOTHING },
4772 { "--output", 'o', RTGETOPT_REQ_STRING },
4773 { "--log", 'l', RTGETOPT_REQ_STRING },
4774 };
4775 RTGETOPTSTATE State;
4776 RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
4777
4778 enum
4779 {
4780 kCpuReportOp_Normal,
4781 kCpuReportOp_MsrsOnly,
4782 kCpuReportOp_MsrsHacking
4783 } enmOp = kCpuReportOp_Normal;
4784 g_pReportOut = NULL;
4785 g_pDebugOut = NULL;
4786 const char *pszOutput = NULL;
4787 const char *pszDebugOut = NULL;
4788
4789 int iOpt;
4790 RTGETOPTUNION ValueUnion;
4791 while ((iOpt = RTGetOpt(&State, &ValueUnion)) != 0)
4792 {
4793 switch (iOpt)
4794 {
4795 case 'm':
4796 enmOp = kCpuReportOp_MsrsOnly;
4797 break;
4798
4799 case 'd':
4800 enmOp = kCpuReportOp_MsrsHacking;
4801 break;
4802
4803 case 'o':
4804 pszOutput = ValueUnion.psz;
4805 break;
4806
4807 case 'l':
4808 pszDebugOut = ValueUnion.psz;
4809 break;
4810
4811 case 'h':
4812 RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-h|--help] [-V|--version] [-o filename.h] [-l debug.log]\n");
4813 RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
4814 return RTEXITCODE_SUCCESS;
4815 case 'V':
4816 RTPrintf("%sr%s\n", RTBldCfgVersion(), RTBldCfgRevisionStr());
4817 return RTEXITCODE_SUCCESS;
4818 default:
4819 return RTGetOptPrintError(iOpt, &ValueUnion);
4820 }
4821 }
4822
4823 /*
4824 * Open the alternative debug log stream.
4825 */
4826 if (pszDebugOut)
4827 {
4828 if (RTFileExists(pszDebugOut) && !RTSymlinkExists(pszDebugOut))
4829 {
4830 char szOld[RTPATH_MAX];
4831 rc = RTStrCopy(szOld, sizeof(szOld), pszDebugOut);
4832 if (RT_SUCCESS(rc))
4833 rc = RTStrCat(szOld, sizeof(szOld), ".old");
4834 if (RT_SUCCESS(rc))
4835 RTFileRename(pszDebugOut, szOld, RTFILEMOVE_FLAGS_REPLACE);
4836 }
4837 rc = RTStrmOpen(pszDebugOut, "w", &g_pDebugOut);
4838 if (RT_FAILURE(rc))
4839 {
4840 RTMsgError("Error opening '%s': %Rrc", pszDebugOut, rc);
4841 g_pDebugOut = NULL;
4842 }
4843 }
4844
4845 /*
4846 * Do the requested job.
4847 */
4848 rc = VERR_INTERNAL_ERROR;
4849 switch (enmOp)
4850 {
4851 case kCpuReportOp_Normal:
4852 /* switch output file. */
4853 if (pszOutput)
4854 {
4855 if (RTFileExists(pszOutput) && !RTSymlinkExists(pszOutput))
4856 {
4857 char szOld[RTPATH_MAX];
4858 rc = RTStrCopy(szOld, sizeof(szOld), pszOutput);
4859 if (RT_SUCCESS(rc))
4860 rc = RTStrCat(szOld, sizeof(szOld), ".old");
4861 if (RT_SUCCESS(rc))
4862 RTFileRename(pszOutput, szOld, RTFILEMOVE_FLAGS_REPLACE);
4863 }
4864 rc = RTStrmOpen(pszOutput, "w", &g_pReportOut);
4865 if (RT_FAILURE(rc))
4866 {
4867 RTMsgError("Error opening '%s': %Rrc", pszOutput, rc);
4868 break;
4869 }
4870 }
4871 rc = produceCpuReport();
4872 break;
4873 case kCpuReportOp_MsrsOnly:
4874 case kCpuReportOp_MsrsHacking:
4875 rc = probeMsrs(enmOp == kCpuReportOp_MsrsHacking, NULL, NULL, NULL, 0);
4876 break;
4877 }
4878
4879 /*
4880 * Close the output files.
4881 */
4882 if (g_pReportOut)
4883 {
4884 RTStrmClose(g_pReportOut);
4885 g_pReportOut = NULL;
4886 }
4887
4888 if (g_pDebugOut)
4889 {
4890 RTStrmClose(g_pDebugOut);
4891 g_pDebugOut = NULL;
4892 }
4893
4894 return RT_SUCCESS(rc) ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
4895}
4896
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