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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bootsector2-cpu-instr-1-template.mac@ 61394

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1; $Id: bootsector2-cpu-instr-1-template.mac 56295 2015-06-09 14:29:55Z vboxsync $
2;; @file
3; Bootsector test for misc instruction - multi mode template.
4;
5
6;
7; Copyright (C) 2007-2015 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17; The contents of this file may alternatively be used under the terms
18; of the Common Development and Distribution License Version 1.0
19; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20; VirtualBox OSE distribution, in which case the provisions of the
21; CDDL are applicable instead of those of the GPL.
22;
23; You may elect to license modified versions of this file under the
24; terms and conditions of either the GPL or the CDDL or both.
25;
26
27
28%include "bootsector2-template-header.mac"
29
30
31
32;;
33; Memory fence instructions (SSE2).
34;
35; @uses No registers, but BS2_SEL_SPARE0 is trashed.
36;
37BEGINPROC TMPL_NM(TestMemFences)
38 push xBP
39 mov xBP, xSP
40 push sAX
41 push xBX
42 push xCX
43 push xDX
44 push xDI
45 push xSI
46 sub xSP, 80h ; iret stack frame space.
47 mov xSI, xSP ; Save the stack register.
48
49 mov xAX, .s_szSubTestName
50 call TMPL_NM_CMN(TestSub)
51
52 ;
53 ; SSE2 supported?
54 ;
55 mov eax, 1
56 xor ecx, ecx
57 cpuid
58 test edx, X86_CPUID_FEATURE_EDX_SSE2
59 jz .skip
60
61 ;
62 ; Check that the standard instruction encodings work.
63 ;
64 mov xBX, [xSP + 10h]
65 mov [xSP], xAX
66 mfence
67 mov [xSP], xCX
68 mov xBX, [xSP + 08h]
69 sfence
70 mov [xSP], xDX
71 mov xBX, [xSP]
72 lfence
73 mov bx, [xSP + 04h]
74
75
76 ;
77 ; The instruction encodings in the intel manual may open the RM as well
78 ; as prefixes open to interpretation. AMD sets RM=0 in their docs.
79 ;
80 ; lfence = 0f,ea,e8
81 ; mfence = 0f,ea,f0
82 ; sfence = 0f,ea,f8
83 ; (RM is the lower 3 bits of the last byte.)
84
85%assign MY_RM 0xe8
86%rep 18h
87 db 0fh, 0aeh, MY_RM
88 db X86_OP_PRF_CS, 0fh, 0aeh, MY_RM
89 db X86_OP_PRF_DS, 0fh, 0aeh, MY_RM
90 db X86_OP_PRF_ES, 0fh, 0aeh, MY_RM
91 db X86_OP_PRF_FS, 0fh, 0aeh, MY_RM
92 db X86_OP_PRF_GS, 0fh, 0aeh, MY_RM
93 db X86_OP_PRF_SS, 0fh, 0aeh, MY_RM
94 db X86_OP_PRF_SIZE_ADDR, 0fh, 0aeh, MY_RM
95 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, 0fh, 0aeh, MY_RM ; (used in group)
96 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, 0fh, 0aeh, MY_RM ; (used in group)
97 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, 0fh, 0aeh, MY_RM ; (used in group)
98 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group)
99%ifdef TMPL_64BIT
100 %assign MY_REX 0x40
101 %rep 10h
102 ; Rex prefixes doesn't change anything.
103 db MY_REX, 0fh, 0aeh, MY_RM
104 db X86_OP_PRF_CS, MY_REX, 0fh, 0aeh, MY_RM
105 db X86_OP_PRF_DS, MY_REX, 0fh, 0aeh, MY_RM
106 db X86_OP_PRF_ES, MY_REX, 0fh, 0aeh, MY_RM
107 db X86_OP_PRF_FS, MY_REX, 0fh, 0aeh, MY_RM
108 db X86_OP_PRF_GS, MY_REX, 0fh, 0aeh, MY_RM
109 db X86_OP_PRF_SS, MY_REX, 0fh, 0aeh, MY_RM
110 db X86_OP_PRF_SIZE_ADDR, MY_REX, 0fh, 0aeh, MY_RM
111 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
112 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
113 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
114 BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
115 %assign MY_REX (MY_REX + 1)
116 %endrep
117%endif
118 %assign MY_RM (MY_RM + 1)
119%endrep
120
121 ;
122 ; Done.
123 ;
124 call TMPL_NM_CMN(TestSubDone)
125.done:
126 mov xSP, xSI
127 add xSP, 80h
128 pop xSI
129 pop xDI
130 pop xDX
131 pop xCX
132 pop xBX
133 pop sAX
134 leave
135 ret
136
137.skip:
138 mov xAX, .s_szSse2Missing
139 call TMPL_NM_CMN(TestSubDone)
140 jmp .done
141
142.s_szSubTestName:
143 db TMPL_MODE_STR, ', mfence et al.', 0
144.s_szSse2Missing:
145 db 'SSE2 is missing', 0
146ENDPROC TMPL_NM(TestMemFences)
147
148
149;;
150; Proving intel manual wrong about using REX.X for BSWAP R8-R15 on 64-bit.
151; Checking the 'undefined' 16-bit bswap behavior.
152;
153; @uses No registers, but BS2_SEL_SPARE0 is trashed.
154;
155BEGINPROC TMPL_NM(TestBSwap)
156 push xBP
157 mov xBP, xSP
158 push sAX
159 push xBX
160 push xCX
161 push xDX
162 push xDI
163 push xSI
164 sub xSP, 80h ; iret stack frame space.
165 mov xSI, xSP ; Save the stack register.
166
167 mov xAX, .s_szSubTestName
168 call TMPL_NM_CMN(TestSub)
169
170 ;
171 ; Assert sanity.
172 ;
173 mov eax, 11223344h
174 bswap eax
175 TEST_ASSERT_SIMPLE eax, 44332211h, jz, "32-bit BSWAP EAX"
176
177 ;
178 ; Buggy manual (325383-041US, December 2011).
179 ;
180%ifdef TMPL_64BIT
181 push r8
182
183 mov r8d, 55667788h
184 mov eax, 55667788h
185 db X86_OP_REX_X
186 bswap eax ; does it access r8 or eax?
187 TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.X BSWAP EAX - Wrong EAX."
188 TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.X BSWAP EAX - Wrong R8."
189
190 mov r8d, 55667788h
191 mov eax, 55667788h
192 db X86_OP_REX_R
193 bswap eax ; does it access r8 or eax?
194 TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.R BSWAP EAX - Wrong EAX."
195 TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.R BSWAP EAX - Wrong R8."
196
197 mov r8d, 55667788h
198 mov eax, 55667788h
199 db X86_OP_REX_B
200 bswap eax ; does it access r8 or eax?
201 TEST_ASSERT_SIMPLE rax, 55667788h, jz, "REX.B BSWAP R8D - Wrong RAX."
202 TEST_ASSERT_SIMPLE r8d, 88776655h, jz, "REX.B BSWAP R8D - Wrong R8D."
203
204 pop r8
205%endif
206
207 ;
208 ; 'Undefined' 16-bit behavior.
209 ;
210 ; Zeroing of the lower 16-bits has been observed on:
211 ; - Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz
212 ;
213%ifndef TestBSwap16_defined
214 %define TestBSwap16_defined
215 %macro TestBSwap16 3,
216 mov %3, %2 ; save the primary register.
217 %ifdef TMPL_64BIT
218 mov %2, 0ffffffff98765432h ; Set the upper bit as well.
219 %else
220 mov %2, 98765432h
221 %endif
222 %ifndef TMPL_16BIT
223 db X86_OP_PRF_SIZE_OP
224 %endif
225 bswap %1
226 xchg %2, %3 ; Restore and save the result (xSP).
227 TEST_ASSERT_SIMPLE %3, 98760000h, jz, "Unexpected 16-bit BSWAP error."
228 %endmacro
229%endif
230
231 TestBSwap16 eax, sAX, sSI
232 TestBSwap16 ebx, sBX, sSI
233 TestBSwap16 ecx, sCX, sSI
234 TestBSwap16 edx, sDX, sSI
235 TestBSwap16 esp, sSP, sSI
236 TestBSwap16 ebp, sBP, sSI
237 TestBSwap16 edi, sDI, sSI
238 TestBSwap16 esi, sSI, sDI
239%ifdef TMPL_64BIT
240 TestBSwap16 r8d, r8, rax
241 TestBSwap16 r9d, r9, rax
242 TestBSwap16 r10d, r10, rax
243 TestBSwap16 r11d, r11, rax
244 TestBSwap16 r12d, r12, rax
245 TestBSwap16 r13d, r13, rax
246 TestBSwap16 r14d, r14, rax
247 TestBSwap16 r15d, r15, rax
248%endif
249
250 ;
251 ; Done.
252 ;
253 call TMPL_NM_CMN(TestSubDone)
254.done:
255 mov xSP, xSI
256 add xSP, 80h
257 pop xSI
258 pop xDI
259 pop xDX
260 pop xCX
261 pop xBX
262 pop sAX
263 leave
264 ret
265
266.s_szSubTestName:
267 db TMPL_MODE_STR, ', bswap', 0
268ENDPROC TMPL_NM(TestBSwap)
269
270
271;;
272; Do the tests for this mode.
273;
274; @uses nothing
275;
276BEGINCODELOW
277BITS 16
278BEGINPROC TMPL_NM(DoTestsForMode_rm)
279 push bp
280 mov bp, sp
281 push ax
282
283 ;
284 ; Check if the mode and NX is supported, do the switch.
285 ;
286 call TMPL_NM(Bs2IsModeSupported_rm)
287 jz .done
288 call TMPL_NM(Bs2EnterMode_rm)
289BITS TMPL_BITS
290
291 ;
292 ; Test exception handler basics using INT3 and #BP.
293 ;
294
295 call TMPL_NM(TestMemFences)
296 call TMPL_NM(TestBSwap)
297
298 ;
299 ; Back to real mode.
300 ;
301 call TMPL_NM(Bs2ExitMode)
302BITS 16
303 call Bs2DisableNX_r86
304
305.done:
306 pop ax
307 leave
308 ret
309ENDPROC TMPL_NM(DoTestsForMode_rm)
310TMPL_BEGINCODE
311BITS TMPL_BITS
312
313%include "bootsector2-template-footer.mac"
314
315
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