| 1 | ; $Id: bootsector2-cpu-instr-1-template.mac 76553 2019-01-01 01:45:53Z vboxsync $
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| 2 | ;; @file
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| 3 | ; Bootsector test for misc instruction - multi mode template.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2019 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; The contents of this file may alternatively be used under the terms
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| 18 | ; of the Common Development and Distribution License Version 1.0
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| 19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | ; VirtualBox OSE distribution, in which case the provisions of the
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| 21 | ; CDDL are applicable instead of those of the GPL.
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| 22 | ;
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| 23 | ; You may elect to license modified versions of this file under the
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| 24 | ; terms and conditions of either the GPL or the CDDL or both.
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| 25 | ;
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| 26 |
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| 27 |
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| 28 | %include "bootsector2-template-header.mac"
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| 29 |
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| 30 |
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| 31 |
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| 32 | ;;
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| 33 | ; Memory fence instructions (SSE2).
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| 34 | ;
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| 35 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
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| 36 | ;
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| 37 | BEGINPROC TMPL_NM(TestMemFences)
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| 38 | push xBP
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| 39 | mov xBP, xSP
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| 40 | push sAX
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| 41 | push xBX
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| 42 | push xCX
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| 43 | push xDX
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| 44 | push xDI
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| 45 | push xSI
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| 46 | sub xSP, 80h ; iret stack frame space.
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| 47 | mov xSI, xSP ; Save the stack register.
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| 48 |
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| 49 | mov xAX, .s_szSubTestName
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| 50 | call TMPL_NM_CMN(TestSub)
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| 51 |
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| 52 | ;
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| 53 | ; SSE2 supported?
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| 54 | ;
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| 55 | mov eax, 1
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| 56 | xor ecx, ecx
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| 57 | cpuid
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| 58 | test edx, X86_CPUID_FEATURE_EDX_SSE2
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| 59 | jz .skip
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| 60 |
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| 61 | ;
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| 62 | ; Check that the standard instruction encodings work.
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| 63 | ;
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| 64 | mov xBX, [xSP + 10h]
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| 65 | mov [xSP], xAX
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| 66 | mfence
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| 67 | mov [xSP], xCX
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| 68 | mov xBX, [xSP + 08h]
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| 69 | sfence
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| 70 | mov [xSP], xDX
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| 71 | mov xBX, [xSP]
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| 72 | lfence
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| 73 | mov bx, [xSP + 04h]
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| 74 |
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| 75 |
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| 76 | ;
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| 77 | ; The instruction encodings in the intel manual may open the RM as well
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| 78 | ; as prefixes open to interpretation. AMD sets RM=0 in their docs.
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| 79 | ;
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| 80 | ; lfence = 0f,ea,e8
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| 81 | ; mfence = 0f,ea,f0
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| 82 | ; sfence = 0f,ea,f8
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| 83 | ; (RM is the lower 3 bits of the last byte.)
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| 84 |
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| 85 | %assign MY_RM 0xe8
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| 86 | %rep 18h
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| 87 | db 0fh, 0aeh, MY_RM
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| 88 | db X86_OP_PRF_CS, 0fh, 0aeh, MY_RM
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| 89 | db X86_OP_PRF_DS, 0fh, 0aeh, MY_RM
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| 90 | db X86_OP_PRF_ES, 0fh, 0aeh, MY_RM
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| 91 | db X86_OP_PRF_FS, 0fh, 0aeh, MY_RM
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| 92 | db X86_OP_PRF_GS, 0fh, 0aeh, MY_RM
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| 93 | db X86_OP_PRF_SS, 0fh, 0aeh, MY_RM
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| 94 | db X86_OP_PRF_SIZE_ADDR, 0fh, 0aeh, MY_RM
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| 95 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, 0fh, 0aeh, MY_RM ; (used in group)
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| 96 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, 0fh, 0aeh, MY_RM ; (used in group)
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| 97 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, 0fh, 0aeh, MY_RM ; (used in group)
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| 98 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, 0fh, 0aeh, MY_RM ; (used in group)
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| 99 | %ifdef TMPL_64BIT
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| 100 | %assign MY_REX 0x40
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| 101 | %rep 10h
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| 102 | ; Rex prefixes doesn't change anything.
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| 103 | db MY_REX, 0fh, 0aeh, MY_RM
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| 104 | db X86_OP_PRF_CS, MY_REX, 0fh, 0aeh, MY_RM
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| 105 | db X86_OP_PRF_DS, MY_REX, 0fh, 0aeh, MY_RM
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| 106 | db X86_OP_PRF_ES, MY_REX, 0fh, 0aeh, MY_RM
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| 107 | db X86_OP_PRF_FS, MY_REX, 0fh, 0aeh, MY_RM
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| 108 | db X86_OP_PRF_GS, MY_REX, 0fh, 0aeh, MY_RM
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| 109 | db X86_OP_PRF_SS, MY_REX, 0fh, 0aeh, MY_RM
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| 110 | db X86_OP_PRF_SIZE_ADDR, MY_REX, 0fh, 0aeh, MY_RM
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| 111 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_SIZE_OP, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 112 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_LOCK, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 113 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPNZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 114 | BS2_TRAP_INSTR X86_XCPT_UD, 0, db X86_OP_PRF_REPZ, MY_REX, 0fh, 0aeh, MY_RM ; (used in group)
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| 115 | %assign MY_REX (MY_REX + 1)
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| 116 | %endrep
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| 117 | %endif
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| 118 | %assign MY_RM (MY_RM + 1)
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| 119 | %endrep
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| 120 |
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| 121 | ;
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| 122 | ; Done.
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| 123 | ;
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| 124 | call TMPL_NM_CMN(TestSubDone)
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| 125 | .done:
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| 126 | mov xSP, xSI
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| 127 | add xSP, 80h
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| 128 | pop xSI
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| 129 | pop xDI
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| 130 | pop xDX
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| 131 | pop xCX
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| 132 | pop xBX
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| 133 | pop sAX
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| 134 | leave
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| 135 | ret
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| 136 |
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| 137 | .skip:
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| 138 | mov xAX, .s_szSse2Missing
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| 139 | call TMPL_NM_CMN(TestSubDone)
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| 140 | jmp .done
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| 141 |
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| 142 | .s_szSubTestName:
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| 143 | db TMPL_MODE_STR, ', mfence et al.', 0
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| 144 | .s_szSse2Missing:
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| 145 | db 'SSE2 is missing', 0
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| 146 | ENDPROC TMPL_NM(TestMemFences)
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| 147 |
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| 148 |
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| 149 | ;;
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| 150 | ; Proving intel manual wrong about using REX.X for BSWAP R8-R15 on 64-bit.
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| 151 | ; Checking the 'undefined' 16-bit bswap behavior.
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| 152 | ;
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| 153 | ; @uses No registers, but BS2_SEL_SPARE0 is trashed.
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| 154 | ;
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| 155 | BEGINPROC TMPL_NM(TestBSwap)
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| 156 | push xBP
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| 157 | mov xBP, xSP
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| 158 | push sAX
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| 159 | push xBX
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| 160 | push xCX
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| 161 | push xDX
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| 162 | push xDI
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| 163 | push xSI
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| 164 | sub xSP, 80h ; iret stack frame space.
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| 165 | mov xSI, xSP ; Save the stack register.
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| 166 |
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| 167 | mov xAX, .s_szSubTestName
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| 168 | call TMPL_NM_CMN(TestSub)
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| 169 |
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| 170 | ;
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| 171 | ; Assert sanity.
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| 172 | ;
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| 173 | mov eax, 11223344h
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| 174 | bswap eax
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| 175 | TEST_ASSERT_SIMPLE eax, 44332211h, jz, "32-bit BSWAP EAX"
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| 176 |
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| 177 | ;
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| 178 | ; Buggy manual (325383-041US, December 2011).
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| 179 | ;
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| 180 | %ifdef TMPL_64BIT
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| 181 | push r8
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| 182 |
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| 183 | mov r8d, 55667788h
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| 184 | mov eax, 55667788h
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| 185 | db X86_OP_REX_X
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| 186 | bswap eax ; does it access r8 or eax?
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| 187 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.X BSWAP EAX - Wrong EAX."
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| 188 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.X BSWAP EAX - Wrong R8."
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| 189 |
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| 190 | mov r8d, 55667788h
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| 191 | mov eax, 55667788h
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| 192 | db X86_OP_REX_R
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| 193 | bswap eax ; does it access r8 or eax?
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| 194 | TEST_ASSERT_SIMPLE eax, 88776655h, jz, "REX.R BSWAP EAX - Wrong EAX."
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| 195 | TEST_ASSERT_SIMPLE r8, 55667788h, jz, "REX.R BSWAP EAX - Wrong R8."
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| 196 |
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| 197 | mov r8d, 55667788h
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| 198 | mov eax, 55667788h
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| 199 | db X86_OP_REX_B
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| 200 | bswap eax ; does it access r8 or eax?
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| 201 | TEST_ASSERT_SIMPLE rax, 55667788h, jz, "REX.B BSWAP R8D - Wrong RAX."
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| 202 | TEST_ASSERT_SIMPLE r8d, 88776655h, jz, "REX.B BSWAP R8D - Wrong R8D."
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| 203 |
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| 204 | pop r8
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| 205 | %endif
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| 206 |
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| 207 | ;
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| 208 | ; 'Undefined' 16-bit behavior.
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| 209 | ;
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| 210 | ; Zeroing of the lower 16-bits has been observed on:
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| 211 | ; - Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz
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| 212 | ;
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| 213 | %ifndef TestBSwap16_defined
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| 214 | %define TestBSwap16_defined
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| 215 | %macro TestBSwap16 3,
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| 216 | mov %3, %2 ; save the primary register.
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| 217 | %ifdef TMPL_64BIT
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| 218 | mov %2, 0ffffffff98765432h ; Set the upper bit as well.
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| 219 | %else
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| 220 | mov %2, 98765432h
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| 221 | %endif
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| 222 | %ifndef TMPL_16BIT
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| 223 | db X86_OP_PRF_SIZE_OP
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| 224 | %endif
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| 225 | bswap %1
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| 226 | xchg %2, %3 ; Restore and save the result (xSP).
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| 227 | TEST_ASSERT_SIMPLE %3, 98760000h, jz, "Unexpected 16-bit BSWAP error."
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| 228 | %endmacro
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| 229 | %endif
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| 230 |
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| 231 | TestBSwap16 eax, sAX, sSI
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| 232 | TestBSwap16 ebx, sBX, sSI
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| 233 | TestBSwap16 ecx, sCX, sSI
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| 234 | TestBSwap16 edx, sDX, sSI
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| 235 | TestBSwap16 esp, sSP, sSI
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| 236 | TestBSwap16 ebp, sBP, sSI
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| 237 | TestBSwap16 edi, sDI, sSI
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| 238 | TestBSwap16 esi, sSI, sDI
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| 239 | %ifdef TMPL_64BIT
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| 240 | TestBSwap16 r8d, r8, rax
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| 241 | TestBSwap16 r9d, r9, rax
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| 242 | TestBSwap16 r10d, r10, rax
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| 243 | TestBSwap16 r11d, r11, rax
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| 244 | TestBSwap16 r12d, r12, rax
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| 245 | TestBSwap16 r13d, r13, rax
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| 246 | TestBSwap16 r14d, r14, rax
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| 247 | TestBSwap16 r15d, r15, rax
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| 248 | %endif
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| 249 |
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| 250 | ;
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| 251 | ; Done.
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| 252 | ;
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| 253 | call TMPL_NM_CMN(TestSubDone)
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| 254 | .done:
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| 255 | mov xSP, xSI
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| 256 | add xSP, 80h
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| 257 | pop xSI
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| 258 | pop xDI
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| 259 | pop xDX
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| 260 | pop xCX
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| 261 | pop xBX
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| 262 | pop sAX
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| 263 | leave
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| 264 | ret
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| 265 |
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| 266 | .s_szSubTestName:
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| 267 | db TMPL_MODE_STR, ', bswap', 0
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| 268 | ENDPROC TMPL_NM(TestBSwap)
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| 269 |
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| 270 |
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| 271 | ;;
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| 272 | ; Do the tests for this mode.
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| 273 | ;
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| 274 | ; @uses nothing
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| 275 | ;
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| 276 | BEGINCODELOW
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| 277 | BITS 16
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| 278 | BEGINPROC TMPL_NM(DoTestsForMode_rm)
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| 279 | push bp
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| 280 | mov bp, sp
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| 281 | push ax
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| 282 |
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| 283 | ;
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| 284 | ; Check if the mode and NX is supported, do the switch.
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| 285 | ;
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| 286 | call TMPL_NM(Bs2IsModeSupported_rm)
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| 287 | jz .done
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| 288 | call TMPL_NM(Bs2EnterMode_rm)
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| 289 | BITS TMPL_BITS
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| 290 |
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| 291 | ;
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| 292 | ; Test exception handler basics using INT3 and #BP.
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| 293 | ;
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| 294 |
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| 295 | call TMPL_NM(TestMemFences)
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| 296 | call TMPL_NM(TestBSwap)
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| 297 |
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| 298 | ;
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| 299 | ; Back to real mode.
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| 300 | ;
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| 301 | call TMPL_NM(Bs2ExitMode)
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| 302 | BITS 16
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| 303 | call Bs2DisableNX_r86
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| 304 |
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| 305 | .done:
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| 306 | pop ax
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| 307 | leave
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| 308 | ret
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| 309 | ENDPROC TMPL_NM(DoTestsForMode_rm)
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| 310 | TMPL_BEGINCODE
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| 311 | BITS TMPL_BITS
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| 312 |
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| 313 | %include "bootsector2-template-footer.mac"
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| 314 |
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