bs3-cpu-basic-2-template.c@ 60585

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1	/* $Id: bs3-cpu-basic-2-template.c 60585 2016-04-20 09:48:09Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-basic-2, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifdef BS3_INSTANTIATING_MODE
29
30	/*********************************************************************************************************************************
31	* Header Files *
32	*********************************************************************************************************************************/
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35
36
37	/*********************************************************************************************************************************
38	* Defined Constants And Macros *
39	*********************************************************************************************************************************/
40	# undef MyBs3Idt
41	# undef MY_SYS_SEL_R0_CS
42	# undef MY_SYS_SEL_R0_CS_CNF
43	# undef MY_SYS_SEL_R0_DS
44	# undef MY_SYS_SEL_R0_SS
45	# if BS3_MODE_IS_16BIT_SYS(TMPL_MODE)
46	# define MyBs3Idt Bs3Idt16
47	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS16
48	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS16_CNF
49	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS16
50	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS16
51	# elif BS3_MODE_IS_32BIT_SYS(TMPL_MODE)
52	# define MyBs3Idt Bs3Idt32
53	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS32
54	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS32_CNF
55	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS32
56	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS32
57	# elif BS3_MODE_IS_64BIT_SYS(TMPL_MODE)
58	# define MyBs3Idt Bs3Idt64
59	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS64
60	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS64_CNF
61	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS64
62	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_DS64
63	# else
64	# error "TMPL_MODE"
65	# endif
66	#undef CHECK_MEMBER
67	#define CHECK_MEMBER(a_szName, a_szFmt, a_Actual, a_Expected) \
68	do \
69	{ \
70	if ((a_Actual) == (a_Expected)) { /* likely */ } \
71	else bs3CpuBasic2_FailedF(a_szName "=" a_szFmt " expected " a_szFmt, (a_Actual), (a_Expected)); \
72	} while (0)
73
74
75	/*********************************************************************************************************************************
76	* Structures and Typedefs *
77	*********************************************************************************************************************************/
78	#ifndef DONE_MODE_TYPES
79	#define DONE_MODE_TYPES
80	typedef struct BS3CB2INVLDESCTYPE
81	{
82	uint8_t u4Type;
83	uint8_t u1DescType;
84	} BS3CB2INVLDESCTYPE;
85	#endif
86
87
88	/*********************************************************************************************************************************
89	* External Symbols *
90	*********************************************************************************************************************************/
91	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int80)(void);
92	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int81)(void);
93	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int82)(void);
94	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int83)(void);
95	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_ud2)(void);
96	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_sidt_bx_ud2)(void);
97	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_lidt_bx_ud2)(void);
98	#ifndef DOXYGEN_RUNNING
99	# define g_bs3CpuBasic2_ud2_FlatAddr BS3_DATA_NM(g_bs3CpuBasic2_ud2_FlatAddr)
100	#endif
101	extern uint32_t g_bs3CpuBasic2_ud2_FlatAddr;
102
103
104	/*********************************************************************************************************************************
105	* Global Variables *
106	*********************************************************************************************************************************/
107	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
108	#define g_pszTestMode BS3_CMN_NM(g_pszTestMode)
109	static const char BS3_FAR g_pszTestMode = (const char )1;
110	#define g_bTestMode BS3_CMN_NM(g_bTestMode)
111	static uint8_t g_bTestMode = 1;
112	#define g_f16BitSys BS3_CMN_NM(g_f16BitSys)
113	static bool g_f16BitSys = 1;
114
115	/** Table containing invalid CS selector types. */
116	static const BS3CB2INVLDESCTYPE g_aInvalidCsTypes[] =
117	{
118	{ X86_SEL_TYPE_RO, 1 },
119	{ X86_SEL_TYPE_RO_ACC, 1 },
120	{ X86_SEL_TYPE_RW, 1 },
121	{ X86_SEL_TYPE_RW_ACC, 1 },
122	{ X86_SEL_TYPE_RO_DOWN, 1 },
123	{ X86_SEL_TYPE_RO_DOWN_ACC, 1 },
124	{ X86_SEL_TYPE_RW_DOWN, 1 },
125	{ X86_SEL_TYPE_RW_DOWN_ACC, 1 },
126	{ 0, 0 },
127	{ 1, 0 },
128	{ 2, 0 },
129	{ 3, 0 },
130	{ 4, 0 },
131	{ 5, 0 },
132	{ 6, 0 },
133	{ 7, 0 },
134	{ 8, 0 },
135	{ 9, 0 },
136	{ 10, 0 },
137	{ 11, 0 },
138	{ 12, 0 },
139	{ 13, 0 },
140	{ 14, 0 },
141	{ 15, 0 },
142	};
143
144	/** Table containing invalid SS selector types. */
145	static const BS3CB2INVLDESCTYPE g_aInvalidSsTypes[] =
146	{
147	{ X86_SEL_TYPE_EO, 1 },
148	{ X86_SEL_TYPE_EO_ACC, 1 },
149	{ X86_SEL_TYPE_ER, 1 },
150	{ X86_SEL_TYPE_ER_ACC, 1 },
151	{ X86_SEL_TYPE_EO_CONF, 1 },
152	{ X86_SEL_TYPE_EO_CONF_ACC, 1 },
153	{ X86_SEL_TYPE_ER_CONF, 1 },
154	{ X86_SEL_TYPE_ER_CONF_ACC, 1 },
155	{ 0, 0 },
156	{ 1, 0 },
157	{ 2, 0 },
158	{ 3, 0 },
159	{ 4, 0 },
160	{ 5, 0 },
161	{ 6, 0 },
162	{ 7, 0 },
163	{ 8, 0 },
164	{ 9, 0 },
165	{ 10, 0 },
166	{ 11, 0 },
167	{ 12, 0 },
168	{ 13, 0 },
169	{ 14, 0 },
170	{ 15, 0 },
171	};
172
173	#endif
174
175	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
176
177	/**
178	* Wrapper around Bs3TestFailedF that prefixes the error with g_usBs3TestStep
179	* and g_pszTestMode.
180	*/
181	#define bs3CpuBasic2_FailedF BS3_CMN_NM(bs3CpuBasic2_FailedF)
182	void bs3CpuBasic2_FailedF(const char *pszFormat, ...)
183	{
184	va_list va;
185
186	char szTmp[168];
187	va_start(va, pszFormat);
188	Bs3StrPrintfV(szTmp, sizeof(szTmp), pszFormat, va);
189	va_end(va);
190
191	Bs3TestFailedF("%u - %s: %s", g_usBs3TestStep, g_pszTestMode, szTmp);
192	}
193
194
195	/**
196	* Compares trap stuff.
197	*/
198	#define bs3CpuBasic2_CompareIntCtx1 BS3_CMN_NM(bs3CpuBasic2_CompareIntCtx1)
199	void bs3CpuBasic2_CompareIntCtx1(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint8_t bXcpt)
200	{
201	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
202	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
203	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
204	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 2 /int xx/, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
205	if (Bs3TestSubErrorCount() != cErrorsBefore)
206	{
207	Bs3TrapPrintFrame(pTrapCtx);
208	#if 1
209	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
210	Bs3TestPrintf("Halting in CompareTrapCtx1: bXcpt=%#x\n", bXcpt);
211	ASMHalt();
212	#endif
213	}
214	}
215
216
217	/**
218	* Compares trap stuff.
219	*/
220	#define bs3CpuBasic2_CompareTrapCtx2 BS3_CMN_NM(bs3CpuBasic2_CompareTrapCtx2)
221	void bs3CpuBasic2_CompareTrapCtx2(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t cbIpAdjust, uint8_t bXcpt,
222	uint16_t uHandlerCs)
223	{
224	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
225	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
226	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
227	CHECK_MEMBER("uHandlerCs", "%#06x", pTrapCtx->uHandlerCs, uHandlerCs);
228	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, cbIpAdjust, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
229	if (Bs3TestSubErrorCount() != cErrorsBefore)
230	{
231	Bs3TrapPrintFrame(pTrapCtx);
232	#if 1
233	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
234	Bs3TestPrintf("Halting in CompareTrapCtx2: bXcpt=%#x\n", bXcpt);
235	ASMHalt();
236	#endif
237	}
238	}
239
240	/**
241	* Compares a CPU trap.
242	*/
243	#define bs3CpuBasic2_CompareCpuTrapCtx BS3_CMN_NM(bs3CpuBasic2_CompareCpuTrapCtx)
244	void bs3CpuBasic2_CompareCpuTrapCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, uint8_t bXcpt,
245	bool f486ResumeFlagHint)
246	{
247	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
248	uint32_t fExtraEfl;
249
250	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
251	CHECK_MEMBER("bErrCd", "%#06RX16", (uint16_t)pTrapCtx->uErrCd, (uint16_t)uErrCd); /* 486 only writes a word */
252
253	fExtraEfl = X86_EFL_RF;
254	if ( g_f16BitSys
255	\|\| ( !f486ResumeFlagHint
256	&& (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) <= BS3CPU_80486 ) )
257	fExtraEfl = 0;
258	else
259	fExtraEfl = X86_EFL_RF;
260	#if 0 /** @todo Running on an AMD Phenom II X6 1100T under AMD-V I'm not getting good X86_EFL_RF results. Enable this to get on with other work. */
261	fExtraEfl = pTrapCtx->Ctx.rflags.u32 & X86_EFL_RF;
262	#endif
263	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 0 /cbIpAdjust/, 0 /cbSpAdjust/, fExtraEfl, g_pszTestMode, g_usBs3TestStep);
264	if (Bs3TestSubErrorCount() != cErrorsBefore)
265	{
266	Bs3TrapPrintFrame(pTrapCtx);
267	#if 1
268	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
269	Bs3TestPrintf("Halting: bXcpt=%#x uErrCd=%#x\n", bXcpt, uErrCd);
270	ASMHalt();
271	#endif
272	}
273	}
274
275
276	/**
277	* Compares \#GP trap.
278	*/
279	#define bs3CpuBasic2_CompareGpCtx BS3_CMN_NM(bs3CpuBasic2_CompareGpCtx)
280	void bs3CpuBasic2_CompareGpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
281	{
282	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_GP, true /f486ResumeFlagHint/);
283	}
284
285	/**
286	* Compares \#NP trap.
287	*/
288	#define bs3CpuBasic2_CompareNpCtx BS3_CMN_NM(bs3CpuBasic2_CompareNpCtx)
289	void bs3CpuBasic2_CompareNpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
290	{
291	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_NP, true /f486ResumeFlagHint/);
292	}
293
294	/**
295	* Compares \#SS trap.
296	*/
297	#define bs3CpuBasic2_CompareSsCtx BS3_CMN_NM(bs3CpuBasic2_CompareSsCtx)
298	void bs3CpuBasic2_CompareSsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, bool f486ResumeFlagHint)
299	{
300	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_SS, f486ResumeFlagHint);
301	}
302
303	/**
304	* Compares \#TS trap.
305	*/
306	#define bs3CpuBasic2_CompareTsCtx BS3_CMN_NM(bs3CpuBasic2_CompareTsCtx)
307	void bs3CpuBasic2_CompareTsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
308	{
309	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_TS, false /f486ResumeFlagHint/);
310	}
311
312	/**
313	* Compares \#PF trap.
314	*/
315	#define bs3CpuBasic2_ComparePfCtx BS3_CMN_NM(bs3CpuBasic2_ComparePfCtx)
316	void bs3CpuBasic2_ComparePfCtx(PCBS3TRAPFRAME pTrapCtx, PBS3REGCTX pStartCtx, uint16_t uErrCd, uint64_t uCr2Expected)
317	{
318	uint64_t const uCr2Saved = pStartCtx->cr2.u;
319	pStartCtx->cr2.u = uCr2Expected;
320	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_PF, true /f486ResumeFlagHint/);
321	pStartCtx->cr2.u = uCr2Saved;
322	}
323
324	/**
325	* Compares \#UD trap.
326	*/
327	#define bs3CpuBasic2_CompareUdCtx BS3_CMN_NM(bs3CpuBasic2_CompareUdCtx)
328	void bs3CpuBasic2_CompareUdCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx)
329	{
330	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /no error code/, X86_XCPT_UD, true /f486ResumeFlagHint/);
331	}
332
333
334	#define bs3CpuBasic2_RaiseXcpt1Common BS3_CMN_NM(bs3CpuBasic2_RaiseXcpt1Common)
335	static void bs3CpuBasic2_RaiseXcpt1Common(bool const g_f16BitSys,
336	uint16_t const uSysR0Cs, uint16_t const uSysR0CsConf, uint16_t const uSysR0Ss,
337	PX86DESC const paIdt, unsigned const cIdteShift)
338	{
339	BS3TRAPFRAME TrapCtx;
340	BS3REGCTX Ctx80;
341	BS3REGCTX Ctx81;
342	BS3REGCTX Ctx82;
343	BS3REGCTX Ctx83;
344	BS3REGCTX CtxTmp;
345	BS3REGCTX CtxTmp2;
346	PBS3REGCTX apCtx8x[4];
347	unsigned iCtx;
348	unsigned iRing;
349	unsigned iDpl;
350	unsigned iRpl;
351	unsigned i, j, k;
352	uint32_t uExpected;
353	bool const f486Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486;
354	# if TMPL_BITS == 16
355	bool const f386Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386;
356	bool const f286 = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) == BS3CPU_80286;
357	# else
358	bool const f286 = false;
359	bool const f386Plus = true;
360	int rc;
361	uint8_t *pbIdtCopyAlloc;
362	PX86DESC pIdtCopy;
363	const unsigned cbIdte = 1 << (3 + cIdteShift);
364	RTCCUINTXREG uCr0Saved = ASMGetCR0();
365	RTGDTR GdtrSaved;
366	# endif
367	RTIDTR IdtrSaved;
368	RTIDTR Idtr;
369
370	ASMGetIDTR(&IdtrSaved);
371	# if TMPL_BITS != 16
372	ASMGetGDTR(&GdtrSaved);
373	# endif
374
375	/* make sure they're allocated */
376	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
377	Bs3MemZero(&Ctx80, sizeof(Ctx80));
378	Bs3MemZero(&Ctx81, sizeof(Ctx81));
379	Bs3MemZero(&Ctx82, sizeof(Ctx82));
380	Bs3MemZero(&Ctx83, sizeof(Ctx83));
381	Bs3MemZero(&CtxTmp, sizeof(CtxTmp));
382	Bs3MemZero(&CtxTmp2, sizeof(CtxTmp2));
383
384	/* Context array. */
385	apCtx8x[0] = &Ctx80;
386	apCtx8x[1] = &Ctx81;
387	apCtx8x[2] = &Ctx82;
388	apCtx8x[3] = &Ctx83;
389
390	# if TMPL_BITS != 16
391	/* Allocate memory for playing around with the IDT. */
392	pbIdtCopyAlloc = NULL;
393	if (BS3_MODE_IS_PAGED(g_bTestMode))
394	pbIdtCopyAlloc = Bs3MemAlloc(BS3MEMKIND_FLAT32, 12*_1K);
395	# endif
396
397	/*
398	* IDT entry 80 thru 83 are assigned DPLs according to the number.
399	* (We'll be useing more, but this'll do for now.)
400	*/
401	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 0;
402	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 1;
403	paIdt[0x82 << cIdteShift].Gate.u2Dpl = 2;
404	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
405
406	Bs3RegCtxSave(&Ctx80);
407	Ctx80.rsp.u -= 0x300;
408	Ctx80.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
409	# if TMPL_BITS == 16
410	Ctx80.cs = BS3_MODE_IS_RM_OR_V86(g_bTestMode) ? BS3_SEL_TEXT16 : BS3_SEL_R0_CS16;
411	# elif TMPL_BITS == 32
412	g_uBs3TrapEipHint = Ctx80.rip.u32;
413	# endif
414	Bs3MemCpy(&Ctx81, &Ctx80, sizeof(Ctx80));
415	Ctx81.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int81));
416	Bs3MemCpy(&Ctx82, &Ctx80, sizeof(Ctx80));
417	Ctx82.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int82));
418	Bs3MemCpy(&Ctx83, &Ctx80, sizeof(Ctx80));
419	Ctx83.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int83));
420
421	/*
422	* Check that all the above gates work from ring-0.
423	*/
424	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
425	{
426	g_usBs3TestStep = iCtx;
427	# if TMPL_BITS == 32
428	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
429	# endif
430	Bs3TrapSetJmpAndRestore(apCtx8x[iCtx], &TrapCtx);
431	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, apCtx8x[iCtx], 0x80+iCtx /bXcpt/);
432	}
433
434	/*
435	* Check that the gate DPL checks works.
436	*/
437	g_usBs3TestStep = 100;
438	for (iRing = 0; iRing <= 3; iRing++)
439	{
440	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
441	{
442	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
443	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
444	# if TMPL_BITS == 32
445	g_uBs3TrapEipHint = CtxTmp.rip.u32;
446	# endif
447	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
448	if (iCtx < iRing)
449	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
450	else
451	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
452	g_usBs3TestStep++;
453	}
454	}
455
456	/*
457	* Modify the gate CS value and run the handler at a different CPL.
458	* Throw RPL variations into the mix (completely ignored) together
459	* with gate presence.
460	* 1. CPL <= GATE.DPL
461	* 2. GATE.P
462	* 3. GATE.CS.DPL <= CPL (non-conforming segments)
463	*/
464	g_usBs3TestStep = 1000;
465	for (i = 0; i <= 3; i++)
466	{
467	for (iRing = 0; iRing <= 3; iRing++)
468	{
469	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
470	{
471	# if TMPL_BITS == 32
472	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
473	# endif
474	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
475	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
476
477	for (j = 0; j <= 3; j++)
478	{
479	uint16_t const uCs = (uSysR0Cs \| j) + (i << BS3_SEL_RING_SHIFT);
480	for (k = 0; k < 2; k++)
481	{
482	g_usBs3TestStep++;
483	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
484	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
485	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = k;
486	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
487	/Bs3TrapPrintFrame(&TrapCtx);/
488	if (iCtx < iRing)
489	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
490	else if (k == 0)
491	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
492	else if (i > iRing)
493	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
494	else
495	{
496	uint16_t uExpectedCs = uCs & X86_SEL_MASK_OFF_RPL;
497	if (i <= iCtx && i <= iRing)
498	uExpectedCs \|= i;
499	bs3CpuBasic2_CompareTrapCtx2(&TrapCtx, &CtxTmp, 2 /int 8xh/, 0x80 + iCtx /bXcpt/, uExpectedCs);
500	}
501	}
502	}
503
504	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
505	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
506	}
507	}
508	}
509	BS3_ASSERT(g_usBs3TestStep < 1600);
510
511	/*
512	* Various CS and SS related faults
513	*
514	* We temporarily reconfigure gate 80 and 83 with new CS selectors, the
515	* latter have a CS.DPL of 2 for testing ring transisions and SS loading
516	* without making it impossible to handle faults.
517	*/
518	g_usBs3TestStep = 1600;
519	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
520	Bs3GdteTestPage00.Gen.u1Present = 0;
521	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
522	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
523
524	/* CS.PRESENT = 0 */
525	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
526	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
527	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
528	bs3CpuBasic2_FailedF("selector was accessed");
529	g_usBs3TestStep++;
530
531	/* Check that GATE.DPL is checked before CS.PRESENT. */
532	for (iRing = 1; iRing < 4; iRing++)
533	{
534	Bs3MemCpy(&CtxTmp, &Ctx80, sizeof(CtxTmp));
535	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
536	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
537	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x80 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
538	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
539	bs3CpuBasic2_FailedF("selector was accessed");
540	g_usBs3TestStep++;
541	}
542
543	/* CS.DPL mismatch takes precedence over CS.PRESENT = 0. */
544	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
545	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
546	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
547	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
548	bs3CpuBasic2_FailedF("CS selector was accessed");
549	g_usBs3TestStep++;
550	for (iDpl = 1; iDpl < 4; iDpl++)
551	{
552	Bs3GdteTestPage00.Gen.u2Dpl = iDpl;
553	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
554	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
555	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
556	bs3CpuBasic2_FailedF("CS selector was accessed");
557	g_usBs3TestStep++;
558	}
559
560	/* 1608: Check all the invalid CS selector types alone. */
561	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
562	for (i = 0; i < RT_ELEMENTS(g_aInvalidCsTypes); i++)
563	{
564	Bs3GdteTestPage00.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
565	Bs3GdteTestPage00.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
566	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
567	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
568	if (Bs3GdteTestPage00.Gen.u4Type != g_aInvalidCsTypes[i].u4Type)
569	bs3CpuBasic2_FailedF("Invalid CS type %#x/%u -> %#x/%u\n",
570	g_aInvalidCsTypes[i].u4Type, g_aInvalidCsTypes[i].u1DescType,
571	Bs3GdteTestPage00.Gen.u4Type, Bs3GdteTestPage00.Gen.u1DescType);
572	g_usBs3TestStep++;
573
574	/* Incorrect CS.TYPE takes precedence over CS.PRESENT = 0. */
575	Bs3GdteTestPage00.Gen.u1Present = 0;
576	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
577	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
578	Bs3GdteTestPage00.Gen.u1Present = 1;
579	g_usBs3TestStep++;
580	}
581
582	/* Fix CS again. */
583	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
584
585	/* 1632: Test SS. */
586	if (!BS3_MODE_IS_64BIT_SYS(g_bTestMode))
587	{
588	uint16_t BS3_FAR *puTssSs2 = BS3_MODE_IS_16BIT_SYS(g_bTestMode) ? &Bs3Tss16.ss2 : &Bs3Tss32.ss2;
589	uint16_t const uSavedSs2 = *puTssSs2;
590	X86DESC const SavedGate83 = paIdt[0x83 << cIdteShift];
591
592	/* Make the handler execute in ring-2. */
593	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
594	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
595	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_02 \| 2;
596
597	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
598	Bs3RegCtxConvertToRingX(&CtxTmp, 3); /* yeah, from 3 so SS:xSP is reloaded. */
599	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
600	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
601	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
602	bs3CpuBasic2_FailedF("CS selector was not access");
603	g_usBs3TestStep++;
604
605	/* Create a SS.DPL=2 stack segment and check that SS2.RPL matters and
606	that we get #SS if the selector isn't present. */
607	i = 0; /* used for cycling thru invalid CS types */
608	for (k = 0; k < 10; k++)
609	{
610	/* k=0: present,
611	k=1: not-present,
612	k=2: present but very low limit,
613	k=3: not-present, low limit.
614	k=4: present, read-only.
615	k=5: not-present, read-only.
616	k=6: present, code-selector.
617	k=7: not-present, code-selector.
618	k=8: present, read-write / no access + system (=LDT).
619	k=9: not-present, read-write / no access + system (=LDT).
620	*/
621	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
622	Bs3GdteTestPage03.Gen.u1Present = !(k & 1);
623	if (k >= 8)
624	{
625	Bs3GdteTestPage03.Gen.u1DescType = 0; /* system */
626	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW; /* = LDT */
627	}
628	else if (k >= 6)
629	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_ER;
630	else if (k >= 4)
631	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RO;
632	else if (k >= 2)
633	{
634	Bs3GdteTestPage03.Gen.u16LimitLow = 0x400;
635	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
636	Bs3GdteTestPage03.Gen.u1Granularity = 0;
637	}
638
639	for (iDpl = 0; iDpl < 4; iDpl++)
640	{
641	Bs3GdteTestPage03.Gen.u2Dpl = iDpl;
642
643	for (iRpl = 0; iRpl < 4; iRpl++)
644	{
645	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| iRpl;
646	//Bs3TestPrintf("k=%u iDpl=%u iRpl=%u step=%u\n", k, iDpl, iRpl, g_usBs3TestStep);
647	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
648	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
649	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
650	if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
651	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
652	else if (k != 0)
653	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03,
654	k == 2 /f486ResumeFlagHint/);
655	else
656	{
657	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
658	if (TrapCtx.uHandlerSs != (BS3_SEL_TEST_PAGE_03 \| 2))
659	bs3CpuBasic2_FailedF("uHandlerSs=%#x expected %#x\n", TrapCtx.uHandlerSs, BS3_SEL_TEST_PAGE_03 \| 2);
660	}
661	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
662	bs3CpuBasic2_FailedF("CS selector was not access");
663	if ( TrapCtx.bXcpt == 0x83
664	\|\| (TrapCtx.bXcpt == X86_XCPT_SS && k == 2) )
665	{
666	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
667	bs3CpuBasic2_FailedF("SS selector was not accessed");
668	}
669	else if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
670	bs3CpuBasic2_FailedF("SS selector was accessed");
671	g_usBs3TestStep++;
672
673	/* +1: Modify the gate DPL to check that this is checked before SS.DPL and SS.PRESENT. */
674	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 2;
675	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
676	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x83 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
677	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
678	g_usBs3TestStep++;
679
680	/* +2: Check the the CS.DPL check is done before the SS ones. Restoring the
681	ring-0 INT 83 context triggers the CS.DPL < CPL check. */
682	Bs3TrapSetJmpAndRestore(&Ctx83, &TrapCtx);
683	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx83, BS3_SEL_TEST_PAGE_02);
684	g_usBs3TestStep++;
685
686	/* +3: Now mark the CS selector not present and check that that also triggers before SS stuff. */
687	Bs3GdteTestPage02.Gen.u1Present = 0;
688	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
689	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
690	Bs3GdteTestPage02.Gen.u1Present = 1;
691	g_usBs3TestStep++;
692
693	/* +4: Make the CS selector some invalid type and check it triggers before SS stuff. */
694	Bs3GdteTestPage02.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
695	Bs3GdteTestPage02.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
696	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
697	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
698	Bs3GdteTestPage02.Gen.u4Type = X86_SEL_TYPE_ER_ACC;
699	Bs3GdteTestPage02.Gen.u1DescType = 1;
700	g_usBs3TestStep++;
701
702	/* +5: Now, make the CS selector limit too small and that it triggers after SS trouble.
703	The 286 had a simpler approach to these GP(0). */
704	Bs3GdteTestPage02.Gen.u16LimitLow = 0;
705	Bs3GdteTestPage02.Gen.u4LimitHigh = 0;
706	Bs3GdteTestPage02.Gen.u1Granularity = 0;
707	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
708	if (f286)
709	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/);
710	else if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
711	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
712	else if (k != 0)
713	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, k == 2 /f486ResumeFlagHint/);
714	else
715	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/);
716	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
717	g_usBs3TestStep++;
718	}
719	}
720	}
721
722	/* Check all the invalid SS selector types alone. */
723	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
724	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
725	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
726	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
727	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
728	g_usBs3TestStep++;
729	for (i = 0; i < RT_ELEMENTS(g_aInvalidSsTypes); i++)
730	{
731	Bs3GdteTestPage03.Gen.u4Type = g_aInvalidSsTypes[i].u4Type;
732	Bs3GdteTestPage03.Gen.u1DescType = g_aInvalidSsTypes[i].u1DescType;
733	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
734	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
735	if (Bs3GdteTestPage03.Gen.u4Type != g_aInvalidSsTypes[i].u4Type)
736	bs3CpuBasic2_FailedF("Invalid SS type %#x/%u -> %#x/%u\n",
737	g_aInvalidSsTypes[i].u4Type, g_aInvalidSsTypes[i].u1DescType,
738	Bs3GdteTestPage03.Gen.u4Type, Bs3GdteTestPage03.Gen.u1DescType);
739	g_usBs3TestStep++;
740	}
741
742	/*
743	* Continue the SS experiments with a expand down segment. We'll use
744	* the same setup as we already have with gate 83h being DPL and
745	* having CS.DPL=2.
746	*
747	* Expand down segments are weird. The valid area is practically speaking
748	* reversed. So, a 16-bit segment with a limit of 0x6000 will have valid
749	* addresses from 0xffff thru 0x6001.
750	*
751	* So, with expand down segments we can more easily cut partially into the
752	* pushing of the iret frame and trigger more interesting behavior than
753	* with regular "expand up" segments where the whole pushing area is either
754	* all fine or not not fine.
755	*/
756	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
757	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
758	Bs3GdteTestPage03.Gen.u2Dpl = 2;
759	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW_DOWN;
760	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
761
762	/* First test, limit = max --> no bytes accessible --> #GP */
763	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
764	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
765
766	/* Second test, limit = 0 --> all by zero byte accessible --> works */
767	Bs3GdteTestPage03.Gen.u16LimitLow = 0;
768	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
769	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
770	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
771
772	/* Modify the gate handler to be a dummy that immediately does UD2
773	and triggers #UD, then advance the limit down till we get the #UD. */
774	Bs3GdteTestPage03.Gen.u1Granularity = 0;
775
776	Bs3MemCpy(&CtxTmp2, &CtxTmp, sizeof(CtxTmp2)); /* #UD result context */
777	if (g_f16BitSys)
778	{
779	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr - BS3_ADDR_BS3TEXT16;
780	Bs3Trap16SetGate(0x83, X86_SEL_TYPE_SYS_286_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u16, 0 /cParams/);
781	CtxTmp2.rsp.u = Bs3Tss16.sp2 - 2*5;
782	}
783	else
784	{
785	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr;
786	Bs3Trap32SetGate(0x83, X86_SEL_TYPE_SYS_386_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u32, 0 /cParams/);
787	CtxTmp2.rsp.u = Bs3Tss32.esp2 - 4*5;
788	}
789	CtxTmp2.bMode = g_bTestMode; /* g_bBs3CurrentMode not changed by the UD2 handler. */
790	CtxTmp2.cs = BS3_SEL_TEST_PAGE_02 \| 2;
791	CtxTmp2.ss = BS3_SEL_TEST_PAGE_03 \| 2;
792	CtxTmp2.bCpl = 2;
793
794	/* test run. */
795	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
796	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
797	g_usBs3TestStep++;
798
799	/* Real run. */
800	i = (g_f16BitSys ? 2 : 4) * 6 + 1;
801	while (i-- > 0)
802	{
803	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
804	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
805	if (i > 0)
806	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
807	else
808	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
809	g_usBs3TestStep++;
810	}
811
812	/* Do a run where we do the same-ring kind of access. */
813	Bs3RegCtxConvertToRingX(&CtxTmp, 2);
814	if (g_f16BitSys)
815	{
816	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 2*3;
817	i = 2*3 - 1;
818	}
819	else
820	{
821	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 4*3;
822	i = 4*3 - 1;
823	}
824	CtxTmp.ss = BS3_SEL_TEST_PAGE_03 \| 2;
825	CtxTmp2.ds = CtxTmp.ds;
826	CtxTmp2.es = CtxTmp.es;
827	CtxTmp2.fs = CtxTmp.fs;
828	CtxTmp2.gs = CtxTmp.gs;
829	while (i-- > 0)
830	{
831	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
832	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
833	if (i > 0)
834	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, 0 /BS3_SEL_TEST_PAGE_03/, true /f486ResumeFlagHint/);
835	else
836	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
837	g_usBs3TestStep++;
838	}
839
840	*puTssSs2 = uSavedSs2;
841	paIdt[0x83 << cIdteShift] = SavedGate83;
842	}
843	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
844	BS3_ASSERT(g_usBs3TestStep < 3000);
845
846	/*
847	* Modify the gate CS value with a conforming segment.
848	*/
849	g_usBs3TestStep = 3000;
850	for (i = 0; i <= 3; i++) /* cs.dpl */
851	{
852	for (iRing = 0; iRing <= 3; iRing++)
853	{
854	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
855	{
856	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
857	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
858	# if TMPL_BITS == 32
859	g_uBs3TrapEipHint = CtxTmp.rip.u32;
860	# endif
861
862	for (j = 0; j <= 3; j++) /* rpl */
863	{
864	uint16_t const uCs = (uSysR0CsConf \| j) + (i << BS3_SEL_RING_SHIFT);
865	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
866	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
867	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
868	//Bs3TestPrintf("%u/%u/%u/%u: cs=%04x hcs=%04x xcpt=%02x\n", i, iRing, iCtx, j, uCs, TrapCtx.uHandlerCs, TrapCtx.bXcpt);
869	/Bs3TrapPrintFrame(&TrapCtx);/
870	g_usBs3TestStep++;
871	if (iCtx < iRing)
872	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
873	else if (i > iRing)
874	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
875	else
876	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
877	}
878	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
879	}
880	}
881	}
882	BS3_ASSERT(g_usBs3TestStep < 3500);
883
884	/*
885	* The gates must be 64-bit in long mode.
886	*/
887	if (cIdteShift != 0)
888	{
889	g_usBs3TestStep = 3500;
890	for (i = 0; i <= 3; i++)
891	{
892	for (iRing = 0; iRing <= 3; iRing++)
893	{
894	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
895	{
896	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
897	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
898
899	for (j = 0; j < 2; j++)
900	{
901	static const uint16_t s_auCSes[2] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32 };
902	uint16_t uCs = (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT);
903	g_usBs3TestStep++;
904	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
905	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
906	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
907	/Bs3TrapPrintFrame(&TrapCtx);/
908	if (iCtx < iRing)
909	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
910	else
911	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
912	}
913	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
914	}
915	}
916	}
917	BS3_ASSERT(g_usBs3TestStep < 4000);
918	}
919
920	/*
921	* IDT limit check. The 286 does not access X86DESCGATE::u16OffsetHigh.
922	*/
923	g_usBs3TestStep = 5000;
924	i = (0x80 << (cIdteShift + 3)) - 1;
925	j = (0x82 << (cIdteShift + 3)) - (!f286 ? 1 : 3);
926	k = (0x83 << (cIdteShift + 3)) - 1;
927	for (; i <= k; i++, g_usBs3TestStep++)
928	{
929	Idtr = IdtrSaved;
930	Idtr.cbIdt = i;
931	ASMSetIDTR(&Idtr);
932	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
933	if (i < j)
934	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx81, (0x81 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
935	else
936	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
937	}
938	ASMSetIDTR(&IdtrSaved);
939	BS3_ASSERT(g_usBs3TestStep < 5100);
940
941	# if TMPL_BITS != 16 /* Only do the paging related stuff in 32-bit and 64-bit modes. */
942
943	/*
944	* IDT page not present. Placing the IDT copy such that 0x80 is on the
945	* first page and 0x81 is on the second page. We need proceed to move
946	* it down byte by byte to check that any inaccessible byte means #PF.
947	*
948	* Note! We must reload the alternative IDTR for each run as any kind of
949	* printing to the string (like error reporting) will cause a switch
950	* to real mode and back, reloading the default IDTR.
951	*/
952	g_usBs3TestStep = 5200;
953	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
954	{
955	uint32_t const uCr2Expected = Bs3SelPtrToFlat(pbIdtCopyAlloc) + _4K;
956	for (j = 0; j < cbIdte; j++)
957	{
958	pIdtCopy = (PX86DESC)&pbIdtCopyAlloc[_4K - cbIdte * 0x81 - j];
959	Bs3MemCpy(pIdtCopy, paIdt, cbIdte * 256);
960
961	Idtr.cbIdt = IdtrSaved.cbIdt;
962	Idtr.pIdt = Bs3SelPtrToFlat(pIdtCopy);
963
964	ASMSetIDTR(&Idtr);
965	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
966	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
967	g_usBs3TestStep++;
968
969	ASMSetIDTR(&Idtr);
970	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
971	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
972	g_usBs3TestStep++;
973
974	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
975	if (RT_SUCCESS(rc))
976	{
977	ASMSetIDTR(&Idtr);
978	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
979	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
980	g_usBs3TestStep++;
981
982	ASMSetIDTR(&Idtr);
983	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
984	if (f486Plus)
985	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
986	else
987	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /uErrCd/, uCr2Expected + 4 - RT_MIN(j, 4));
988	g_usBs3TestStep++;
989
990	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
991
992	/* Check if that the entry type is checked after the whole IDTE has been cleared for #PF. */
993	pIdtCopy[0x80 << cIdteShift].Gate.u4Type = 0;
994	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
995	if (RT_SUCCESS(rc))
996	{
997	ASMSetIDTR(&Idtr);
998	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
999	if (f486Plus)
1000	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
1001	else
1002	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /uErrCd/, uCr2Expected + 4 - RT_MIN(j, 4));
1003	g_usBs3TestStep++;
1004
1005	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
1006	}
1007	}
1008	else
1009	Bs3TestPrintf("Bs3PagingProtectPtr: %d\n", i);
1010
1011	ASMSetIDTR(&IdtrSaved);
1012	}
1013	}
1014
1015	/*
1016	* The read/write and user/supervisor bits the IDT PTEs are irrelevant.
1017	*/
1018	g_usBs3TestStep = 5300;
1019	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1020	{
1021	Bs3MemCpy(pbIdtCopyAlloc, paIdt, cbIdte * 256);
1022	Idtr.cbIdt = IdtrSaved.cbIdt;
1023	Idtr.pIdt = Bs3SelPtrToFlat(pbIdtCopyAlloc);
1024
1025	ASMSetIDTR(&Idtr);
1026	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1027	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1028	g_usBs3TestStep++;
1029
1030	rc = Bs3PagingProtect(Idtr.pIdt, _4K, 0 /fSet/, X86_PTE_RW \| X86_PTE_US /fClear/);
1031	if (RT_SUCCESS(rc))
1032	{
1033	ASMSetIDTR(&Idtr);
1034	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1035	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1036	g_usBs3TestStep++;
1037
1038	Bs3PagingProtect(Idtr.pIdt, _4K, X86_PTE_RW \| X86_PTE_US /fSet/, 0 /fClear/);
1039	}
1040	ASMSetIDTR(&IdtrSaved);
1041	}
1042
1043	/*
1044	* Check that CS.u1Accessed is set to 1. Use the test page selector #0 and #3 together
1045	* with interrupt gates 80h and 83h, respectively.
1046	*/
1047	/** @todo Throw in SS.u1Accessed too. */
1048	g_usBs3TestStep = 5400;
1049	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1050	{
1051	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
1052	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1053	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
1054
1055	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Cs + (3 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
1056	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1057	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_03; /* rpl is ignored, so leave it as zero. */
1058
1059	/* Check that the CS.A bit is being set on a general basis and that
1060	the special CS values work with out generic handler code. */
1061	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1062	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1063	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1064	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed", Bs3GdteTestPage00.Gen.u4Type);
1065	g_usBs3TestStep++;
1066
1067	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1068	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1069	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1070	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1071	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1072	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1073	if (TrapCtx.uHandlerCs != (BS3_SEL_TEST_PAGE_03 \| 3))
1074	bs3CpuBasic2_FailedF("uHandlerCs=%#x, expected %#x", TrapCtx.uHandlerCs, (BS3_SEL_TEST_PAGE_03 \| 3));
1075	g_usBs3TestStep++;
1076
1077	/*
1078	* Now check that setting CS.u1Access to 1 does __NOT__ trigger a page
1079	* fault due to the RW bit being zero.
1080	* (We check both with with and without the WP bit if 80486.)
1081	*/
1082	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1083	ASMSetCR0(uCr0Saved \| X86_CR0_WP);
1084
1085	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1086	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1087	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_RW /fClear/);
1088	if (RT_SUCCESS(rc))
1089	{
1090	/* ring-0 handler */
1091	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1092	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1093	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1094	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1095	g_usBs3TestStep++;
1096
1097	/* ring-3 handler */
1098	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1099	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1100	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1101	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1102	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1103	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1104	g_usBs3TestStep++;
1105
1106	/* clear WP and repeat the above. */
1107	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1108	ASMSetCR0(uCr0Saved & ~X86_CR0_WP);
1109	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1110	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1111
1112	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1113	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1114	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1115	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1116	g_usBs3TestStep++;
1117
1118	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1119	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1120	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1121	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!n", Bs3GdteTestPage03.Gen.u4Type);
1122	g_usBs3TestStep++;
1123
1124	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_RW /fSet/, 0 /fClear/);
1125	}
1126
1127	ASMSetCR0(uCr0Saved);
1128
1129	/*
1130	* While we're here, check that if the CS GDT entry is a non-present
1131	* page we do get a #PF with the rigth error code and CR2.
1132	*/
1133	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* Just for fun, really a pointless gesture. */
1134	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1135	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_P /fClear/);
1136	if (RT_SUCCESS(rc))
1137	{
1138	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1139	if (f486Plus)
1140	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00);
1141	else
1142	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00 + 4);
1143	g_usBs3TestStep++;
1144
1145	/* Do it from ring-3 to check ErrCd, which doesn't set X86_TRAP_PF_US it turns out. */
1146	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1147	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1148	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1149
1150	if (f486Plus)
1151	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03);
1152	else
1153	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03 + 4);
1154	g_usBs3TestStep++;
1155
1156	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_P /fSet/, 0 /fClear/);
1157	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1158	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #1", Bs3GdteTestPage00.Gen.u4Type);
1159	if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1160	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #2", Bs3GdteTestPage03.Gen.u4Type);
1161	}
1162
1163	/* restore */
1164	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
1165	paIdt[0x83 << cIdteShift].Gate.u16Sel = uSysR0Cs;// + (3 << BS3_SEL_RING_SHIFT) + 3;
1166	}
1167
1168	# endif /* 32 \|\| 64*/
1169
1170	/*
1171	* Check broad EFLAGS effects.
1172	*/
1173	g_usBs3TestStep = 5600;
1174	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1175	{
1176	for (iRing = 0; iRing < 4; iRing++)
1177	{
1178	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1179	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1180
1181	/* all set */
1182	CtxTmp.rflags.u32 &= X86_EFL_VM \| X86_EFL_1;
1183	CtxTmp.rflags.u32 \|= X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF /* \| X86_EFL_TF / /\| X86_EFL_IF*/
1184	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL /* \| X86_EFL_NT*/;
1185	if (f486Plus)
1186	CtxTmp.rflags.u32 \|= X86_EFL_AC;
1187	if (f486Plus && !g_f16BitSys)
1188	CtxTmp.rflags.u32 \|= X86_EFL_RF;
1189	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
1190	CtxTmp.rflags.u32 \|= X86_EFL_VIF \| X86_EFL_VIP;
1191	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1192	CtxTmp.rflags.u32 &= ~X86_EFL_RF;
1193
1194	if (iCtx >= iRing)
1195	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1196	else
1197	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1198	uExpected = CtxTmp.rflags.u32
1199	& ( X86_EFL_1 \| X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_DF
1200	\| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP
1201	\| X86_EFL_ID /\| X86_EFL_TF/ /\| X86_EFL_IF/ /\| X86_EFL_RF/ );
1202	if (TrapCtx.fHandlerRfl != uExpected)
1203	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1204	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1205	g_usBs3TestStep++;
1206
1207	/* all cleared */
1208	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80286)
1209	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_RA1_MASK \| UINT16_C(0xf000));
1210	else
1211	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_VM \| X86_EFL_RA1_MASK);
1212	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1213	if (iCtx >= iRing)
1214	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1215	else
1216	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1217	uExpected = CtxTmp.rflags.u32;
1218	if (TrapCtx.fHandlerRfl != uExpected)
1219	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1220	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1221	g_usBs3TestStep++;
1222	}
1223	}
1224
1225	/** @todo CS.LIMIT / canonical(CS) */
1226
1227
1228	/*
1229	* Check invalid gate types.
1230	*/
1231	g_usBs3TestStep = 32000;
1232	for (iRing = 0; iRing <= 3; iRing++)
1233	{
1234	static const uint16_t s_auCSes[] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32, BS3_SEL_R0_CS64,
1235	BS3_SEL_TSS16, BS3_SEL_TSS32, BS3_SEL_TSS64, 0, BS3_SEL_SPARE_1f };
1236	static uint16_t const s_auInvlTypes64[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
1237	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1238	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f };
1239	static uint16_t const s_auInvlTypes32[] = { 0, 1, 2, 3, 8, 9, 10, 11, 13,
1240	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1241	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
1242	/286:/ 12, 14, 15 };
1243	uint16_t const * const pauInvTypes = cIdteShift != 0 ? s_auInvlTypes64 : s_auInvlTypes32;
1244	uint16_t const cInvTypes = cIdteShift != 0 ? RT_ELEMENTS(s_auInvlTypes64)
1245	: f386Plus ? RT_ELEMENTS(s_auInvlTypes32) - 3 : RT_ELEMENTS(s_auInvlTypes32);
1246
1247
1248	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1249	{
1250	unsigned iType;
1251
1252	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1253	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1254	# if TMPL_BITS == 32
1255	g_uBs3TrapEipHint = CtxTmp.rip.u32;
1256	# endif
1257	for (iType = 0; iType < cInvTypes; iType++)
1258	{
1259	uint8_t const bSavedType = paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type;
1260	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = pauInvTypes[iType] >> 4;
1261	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = pauInvTypes[iType] & 0xf;
1262
1263	for (i = 0; i < 4; i++)
1264	{
1265	for (j = 0; j < RT_ELEMENTS(s_auCSes); j++)
1266	{
1267	uint16_t uCs = (unsigned)(s_auCSes[j] - BS3_SEL_R0_FIRST) < (unsigned)(4 << BS3_SEL_RING_SHIFT)
1268	? (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT)
1269	: s_auCSes[j] \| i;
1270	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x type=%#x\n", g_usBs3TestStep, iCtx, iRing, i, uCs, pauInvTypes[iType]);/
1271	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
1272	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1273	g_usBs3TestStep++;
1274	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1275
1276	/* Mark it not-present to check that invalid type takes precedence. */
1277	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 0;
1278	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1279	g_usBs3TestStep++;
1280	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1281	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1282	}
1283	}
1284
1285	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = MY_SYS_SEL_R0_CS;
1286	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = bSavedType;
1287	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = 0;
1288	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1289	}
1290	}
1291	}
1292	BS3_ASSERT(g_usBs3TestStep < 62000U && g_usBs3TestStep > 32000U);
1293
1294
1295	/** @todo
1296	* - Run \#PF and \#GP (and others?) at CPLs other than zero.
1297	* - Quickly generate all faults.
1298	* - All the peculiarities v8086.
1299	*/
1300
1301	# if TMPL_BITS != 16
1302	Bs3MemFree(pbIdtCopyAlloc, 12*_1K);
1303	# endif
1304	}
1305
1306
1307	#define bs3CpuBasic2_sidt_Common BS3_CMN_NM(bs3CpuBasic2_sidt_Common)
1308	void bs3CpuBasic2_sidt_Common(void)
1309	{
1310	BS3TRAPFRAME TrapCtx;
1311	BS3REGCTX Ctx;
1312	BS3REGCTX TmpCtx;
1313	uint8_t abBuf[16];
1314	uint8_t BS3_FAR *pbBuf = abBuf;
1315
1316	/* make sure they're allocated */
1317	Bs3MemZero(&Ctx, sizeof(Ctx));
1318	Bs3MemZero(&TmpCtx, sizeof(TmpCtx));
1319	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
1320	Bs3MemZero(&abBuf, sizeof(abBuf));
1321
1322	/* Create a context, give this routine some more stack space, point the context
1323	at our SIDT [xBX] + UD2 combo, and point DS:xBX at abBuf. */
1324	Bs3RegCtxSave(&Ctx);
1325	Ctx.rsp.u -= 0x80;
1326	Ctx.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_sidt_bx_ud2));
1327	# if TMPL_BITS == 32
1328	g_uBs3TrapEipHint = Ctx.rip.u32;
1329	# endif
1330	Ctx.rbx.u = BS3_FP_OFF(pbBuf);
1331	# if TMPL_BITS == 16
1332	Ctx.ds = BS3_FP_SEG(pbBuf);
1333	# endif
1334
1335	/*
1336	* Check that it works at all.
1337	*/
1338	Bs3MemZero(&abBuf, sizeof(abBuf));
1339	Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
1340	g_usBs3TestStep = 0;
1341	//bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx, 0x80 /bXcpt/);
1342
1343	}
1344
1345	#endif /* once for each bitcount */
1346
1347
1348	#if TMPL_MODE == BS3_MODE_PE16 \|\| TMPL_MODE == BS3_MODE_PE16_32
1349
1350	/**
1351	* Worker for bs3CpuBasic2_TssGateEsp that tests the INT 80 from outer rings.
1352	*/
1353	#define bs3CpuBasic2_TssGateEsp_AltStackOuterRing BS3_CMN_NM(bs3CpuBasic2_TssGateEsp_AltStackOuterRing)
1354	void bs3CpuBasic2_TssGateEsp_AltStackOuterRing(PCBS3REGCTX pCtx, uint8_t bRing, uint8_t *pbAltStack, size_t cbAltStack,
1355	bool f16BitStack, bool f16BitTss, bool f16BitHandler, unsigned uLine)
1356	{
1357	uint8_t const cbIretFrame = f16BitHandler ? 52 : 54;
1358	BS3REGCTX Ctx2;
1359	BS3TRAPFRAME TrapCtx;
1360	uint8_t *pbTmp;
1361	g_usBs3TestStep = uLine;
1362
1363	Bs3MemCpy(&Ctx2, pCtx, sizeof(Ctx2));
1364	Bs3RegCtxConvertToRingX(&Ctx2, bRing);
1365
1366	if (pbAltStack)
1367	{
1368	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1369	Bs3MemZero(pbAltStack, cbAltStack);
1370	}
1371
1372	Bs3TrapSetJmpAndRestore(&Ctx2, &TrapCtx);
1373
1374	if (!f16BitStack && f16BitTss)
1375	Ctx2.rsp.u &= UINT16_MAX;
1376
1377	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1378	CHECK_MEMBER("bCpl", "%u", TrapCtx.Ctx.bCpl, bRing);
1379	CHECK_MEMBER("cbIretFrame", "%#x", TrapCtx.cbIretFrame, cbIretFrame);
1380
1381	if (pbAltStack)
1382	{
1383	uint64_t uExpectedRsp = (f16BitTss ? Bs3Tss16.sp0 : Bs3Tss32.esp0) - cbIretFrame;
1384	if (f16BitStack)
1385	{
1386	uExpectedRsp &= UINT16_MAX;
1387	uExpectedRsp \|= Ctx2.rsp.u & ~(uint64_t)UINT16_MAX;
1388	}
1389	if ( TrapCtx.uHandlerRsp != uExpectedRsp
1390	\|\| TrapCtx.uHandlerSs != (f16BitTss ? Bs3Tss16.ss0 : Bs3Tss32.ss0))
1391	bs3CpuBasic2_FailedF("handler SS:ESP=%04x:%08RX64, expected %04x:%08RX16",
1392	TrapCtx.uHandlerSs, TrapCtx.uHandlerRsp, Bs3Tss16.ss0, uExpectedRsp);
1393
1394	pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack);
1395	if ((f16BitStack \|\| TrapCtx.uHandlerRsp <= UINT16_MAX) && pbTmp != NULL)
1396	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x",
1397	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1398	else if (!f16BitStack && TrapCtx.uHandlerRsp > UINT16_MAX && pbTmp == NULL)
1399	bs3CpuBasic2_FailedF("the alt stack (%p) was not used SS:ESP=%04x:%#RX32\n", pbAltStack, Ctx2.ss, Ctx2.rsp.u32);
1400	}
1401	}
1402
1403	#define bs3CpuBasic2_TssGateEspCommon BS3_CMN_NM(bs3CpuBasic2_TssGateEspCommon)
1404	void bs3CpuBasic2_TssGateEspCommon(bool const g_f16BitSys, PX86DESC const paIdt, unsigned const cIdteShift)
1405	{
1406	BS3TRAPFRAME TrapCtx;
1407	BS3REGCTX Ctx;
1408	BS3REGCTX Ctx2;
1409	# if TMPL_BITS == 16
1410	uint8_t *pbTmp;
1411	# endif
1412
1413	/* make sure they're allocated */
1414	Bs3MemZero(&Ctx, sizeof(Ctx));
1415	Bs3MemZero(&Ctx2, sizeof(Ctx2));
1416	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
1417
1418	Bs3RegCtxSave(&Ctx);
1419	Ctx.rsp.u -= 0x80;
1420	Ctx.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
1421	# if TMPL_BITS == 32
1422	g_uBs3TrapEipHint = Ctx.rip.u32;
1423	# endif
1424
1425	/*
1426	* We'll be using IDT entry 80 and 81 here. The first one will be
1427	* accessible from all DPLs, the latter not. So, start with setting
1428	* the DPLs.
1429	*/
1430	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 3;
1431	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 0;
1432
1433	/*
1434	* Check that the basic stuff works first.
1435	*/
1436	Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
1437	g_usBs3TestStep = __LINE__;
1438	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx, 0x80 /bXcpt/);
1439
1440	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1441	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1442	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1443
1444	/*
1445	* Check that the upper part of ESP is preserved when doing .
1446	*/
1447	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1448	{
1449	size_t const cbAltStack = _8K;
1450	uint8_t *pbAltStack = Bs3MemAllocZ(BS3MEMKIND_TILED, cbAltStack);
1451	if (pbAltStack)
1452	{
1453	/* same ring */
1454	g_usBs3TestStep = __LINE__;
1455	Bs3MemCpy(&Ctx2, &Ctx, sizeof(Ctx2));
1456	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1457	if (Bs3TrapSetJmp(&TrapCtx))
1458	Bs3RegCtxRestore(&Ctx2, 0); /* (does not return) */
1459	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1460	# if TMPL_BITS == 16
1461	if ((pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack)) != NULL)
1462	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x\n",
1463	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1464	# else
1465	if (ASMMemIsZero(pbAltStack, cbAltStack))
1466	bs3CpuBasic2_FailedF("alt stack wasn't used despite SS:ESP=%04x:%#RX32\n", Ctx2.ss, Ctx2.rsp.u32);
1467	# endif
1468
1469	/* Different rings (load SS0:SP0 from TSS). */
1470	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1471	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1472	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, pbAltStack, cbAltStack,
1473	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1474	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, pbAltStack, cbAltStack,
1475	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1476
1477	/* Different rings but switch the SS bitness in the TSS. */
1478	if (g_f16BitSys)
1479	{
1480	Bs3Tss16.ss0 = BS3_SEL_R0_SS32;
1481	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1482	false, g_f16BitSys, g_f16BitSys, __LINE__);
1483	Bs3Tss16.ss0 = BS3_SEL_R0_SS16;
1484	}
1485	else
1486	{
1487	Bs3Tss32.ss0 = BS3_SEL_R0_SS16;
1488	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1489	true, g_f16BitSys, g_f16BitSys, __LINE__);
1490	Bs3Tss32.ss0 = BS3_SEL_R0_SS32;
1491	}
1492
1493	Bs3MemFree(pbAltStack, cbAltStack);
1494	}
1495	else
1496	Bs3TestPrintf("%s: Skipping ESP check, alloc failed\n", g_pszTestMode);
1497	}
1498	else
1499	Bs3TestPrintf("%s: Skipping ESP check, CPU too old\n", g_pszTestMode);
1500	}
1501
1502	#endif /* PE16 \|\| PE32 */
1503
1504
1505	BS3_DECL_FAR(uint8_t) TMPL_NM(bs3CpuBasic2_TssGateEsp)(uint8_t bMode)
1506	{
1507	uint8_t bRet = 0;
1508
1509	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1510	g_bTestMode = bMode;
1511	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1512
1513	#if TMPL_MODE == BS3_MODE_PE16 \
1514	\|\| TMPL_MODE == BS3_MODE_PE16_32 \
1515	\|\| TMPL_MODE == BS3_MODE_PP16 \
1516	\|\| TMPL_MODE == BS3_MODE_PP16_32 \
1517	\|\| TMPL_MODE == BS3_MODE_PAE16 \
1518	\|\| TMPL_MODE == BS3_MODE_PAE16_32 \
1519	\|\| TMPL_MODE == BS3_MODE_PE32
1520	bs3CpuBasic2_TssGateEspCommon(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1521	(PX86DESC)MyBs3Idt,
1522	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1523	#else
1524	bRet = BS3TESTDOMODE_SKIPPED;
1525	#endif
1526
1527	/*
1528	* Re-initialize the IDT.
1529	*/
1530	Bs3TrapInit();
1531	return bRet;
1532	}
1533
1534
1535	BS3_DECL_FAR(uint8_t) TMPL_NM(bs3CpuBasic2_RaiseXcpt1)(uint8_t bMode)
1536	{
1537	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1538	g_bTestMode = bMode;
1539	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1540
1541	#if !BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
1542
1543	/*
1544	* Pass to common worker which is only compiled once per mode.
1545	*/
1546	bs3CpuBasic2_RaiseXcpt1Common(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1547	MY_SYS_SEL_R0_CS,
1548	MY_SYS_SEL_R0_CS_CNF,
1549	MY_SYS_SEL_R0_SS,
1550	(PX86DESC)MyBs3Idt,
1551	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1552
1553	/*
1554	* Re-initialize the IDT.
1555	*/
1556	Bs3TrapInit();
1557	return 0;
1558	#elif TMPL_MODE == BS3_MODE_RM
1559
1560	/*
1561	* Check
1562	*/
1563	/** @todo check */
1564	return BS3TESTDOMODE_SKIPPED;
1565
1566	#else
1567	return BS3TESTDOMODE_SKIPPED;
1568	#endif
1569	}
1570
1571
1572	BS3_DECL_FAR(uint8_t) TMPL_NM(bs3CpuBasic2_iret)(uint8_t bMode)
1573	{
1574	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1575	g_bTestMode = bMode;
1576	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1577
1578	Bs3PrintStrN(RT_STR_TUPLE("Hello world!\n"));
1579	#if !BS3_MODE_IS_V86(TMPL_MODE)
1580	Bs3TestPrintf(RT_STR_TUPLE("Hi there!\n"));
1581	#endif
1582	return BS3TESTDOMODE_SKIPPED;
1583	}
1584
1585
1586	BS3_DECL_FAR(uint8_t) TMPL_NM(bs3CpuBasic2_sidt)(uint8_t bMode)
1587	{
1588	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1589	g_bTestMode = bMode;
1590	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1591
1592	BS3_ASSERT(bMode == TMPL_MODE);
1593
1594	/*
1595	* Pass to common worker which is only compiled once per mode.
1596	*/
1597	bs3CpuBasic2_sidt_Common();
1598
1599	/*
1600	* Re-initialize the IDT.
1601	*/
1602	Bs3TrapInit();
1603	return 0;
1604	}
1605
1606
1607	#endif /* BS3_INSTANTIATING_MODE */
1608

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c@ 60585

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