bs3-cpu-basic-2-template.mac@ 97510

Last change on this file since 97510 was 97510, checked in by vboxsync, 2 years ago
ValKit/bs3-cpu-basic-2: More updates on the far jumps test (intel). bugref:9898
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1	; $Id: bs3-cpu-basic-2-template.mac 97510 2022-11-11 12:21:18Z vboxsync $
2	;; @file
3	; BS3Kit - bs3-cpu-basic-2 assembly template.
4	;
5
6	;
7	; Copyright (C) 2007-2022 Oracle and/or its affiliates.
8	;
9	; This file is part of VirtualBox base platform packages, as
10	; available from https://www.virtualbox.org.
11	;
12	; This program is free software; you can redistribute it and/or
13	; modify it under the terms of the GNU General Public License
14	; as published by the Free Software Foundation, in version 3 of the
15	; License.
16	;
17	; This program is distributed in the hope that it will be useful, but
18	; WITHOUT ANY WARRANTY; without even the implied warranty of
19	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	; General Public License for more details.
21	;
22	; You should have received a copy of the GNU General Public License
23	; along with this program; if not, see <https://www.gnu.org/licenses>.
24	;
25	; The contents of this file may alternatively be used under the terms
26	; of the Common Development and Distribution License Version 1.0
27	; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	; in the VirtualBox distribution, in which case the provisions of the
29	; CDDL are applicable instead of those of the GPL.
30	;
31	; You may elect to license modified versions of this file under the
32	; terms and conditions of either the GPL or the CDDL or both.
33	;
34	; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	;
36
37
38	;*********************************************************************************************************************************
39	;* Header Files *
40	;*********************************************************************************************************************************
41	%include "bs3kit-template-header.mac" ; setup environment
42
43
44	;*********************************************************************************************************************************
45	;* Defined Constants And Macros *
46	;*********************************************************************************************************************************
47	%ifndef BS3_CPUBAS2_UD_OFF_DEFINED
48	%define BS3_CPUBAS2_UD_OFF_DEFINED
49	%macro BS3_CPUBAS2_UD_OFF 1
50	BS3_GLOBAL_NAME_EX BS3_CMN_NM(%1) %+ _offUD, , 1
51	db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1)
52	%endmacro
53	%endif
54
55	%undef BS3_CPUBAS2_REF_LABEL_VIA_CS
56	%if TMPL_BITS == 16
57	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) cs:a_Label
58	%define BS3_CPUBAS2_JMP_FAR_MEM_LABEL(a_Label) jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label)]
59	%elif TMPL_BITS == 32
60	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) cs:a_Label wrt FLAT
61	%define BS3_CPUBAS2_JMP_FAR_MEM_LABEL(a_Label) jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label)]
62	%elif TMPL_BITS == 64
63	%define BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label) a_Label wrt FLAT
64	%define BS3_CPUBAS2_JMP_FAR_MEM_LABEL(a_Label) jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(a_Label)]
65	%else
66	%error TMPL_BITS
67	%endif
68
69	%ifndef BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
70	%define BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
71	%macro BS3_CPUBAS2_JMP_FAR_MEM_LABEL 2
72	%if TMPL_BITS != 64
73	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(%1)]
74	%elif TMPL_BITS == 64
75	; 48FF2C25[040C0000] <3> jmp far [BS3_CPUBAS2_REF_LABLE_VIA_CS(.fpfn)]
76	%if %2 != 0
77	db 048h ; REX.W
78	%endif
79	db 0ffh, 02ch, 025h
80	dd %1 wrt FLAT
81	%else
82	%error TMPL_BITS
83	%endif
84	%endmacro
85	%endif ; BS3_CPUBAS2_JMP_FAR_MEM_LABEL_DEFINED
86
87
88	;*********************************************************************************************************************************
89	;* External Symbols *
90	;*********************************************************************************************************************************
91	TMPL_BEGIN_TEXT
92
93
94
95	;
96	; Test code snippets containing code which differs between 16-bit, 32-bit
97	; and 64-bit CPUs modes.
98	;
99	%ifdef BS3_INSTANTIATING_CMN
100
101	;
102	; SIDT
103	;
104	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_bx_ud2
105	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_bx_ud2, BS3_PBC_NEAR
106	sidt [xBX]
107	.again: ud2
108	jmp .again
109	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_bx_ud2) == 3)
110	BS3_PROC_END_CMN bs3CpuBasic2_sidt_bx_ud2
111
112	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_bx_ud2
113	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_bx_ud2, BS3_PBC_NEAR
114	db X86_OP_PRF_SIZE_OP
115	sidt [xBX]
116	.again: ud2
117	jmp .again
118	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_bx_ud2) == 4)
119	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_bx_ud2
120
121	%if TMPL_BITS == 64
122	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_rexw_bx_ud2
123	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_rexw_bx_ud2, BS3_PBC_NEAR
124	db X86_OP_REX_W
125	sidt [xBX]
126	.again: ud2
127	jmp .again
128	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_rexw_bx_ud2) == 4)
129	BS3_PROC_END_CMN bs3CpuBasic2_sidt_rexw_bx_ud2
130
131	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_rexw_bx_ud2
132	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_rexw_bx_ud2, BS3_PBC_NEAR
133	db X86_OP_PRF_SIZE_OP
134	db X86_OP_REX_W
135	sidt [xBX]
136	.again: ud2
137	jmp .again
138	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_rexw_bx_ud2) == 5)
139	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_rexw_bx_ud2
140	%endif
141
142	%if TMPL_BITS != 64
143	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_ss_bx_ud2
144	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_ss_bx_ud2, BS3_PBC_NEAR
145	sidt [ss:xBX]
146	.again: ud2
147	jmp .again
148	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_ss_bx_ud2) == 4)
149	BS3_PROC_END_CMN bs3CpuBasic2_sidt_ss_bx_ud2
150
151	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sidt_opsize_ss_bx_ud2
152	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sidt_opsize_ss_bx_ud2, BS3_PBC_NEAR
153	db X86_OP_PRF_SIZE_OP
154	sidt [ss:xBX]
155	.again: ud2
156	jmp .again
157	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sidt_opsize_ss_bx_ud2) == 5)
158	BS3_PROC_END_CMN bs3CpuBasic2_sidt_opsize_ss_bx_ud2
159	%endif
160
161
162	;
163	; SGDT
164	;
165	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_bx_ud2
166	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_bx_ud2, BS3_PBC_NEAR
167	sgdt [xBX]
168	.again: ud2
169	jmp .again
170	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_bx_ud2) == 3)
171	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_bx_ud2
172
173	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_bx_ud2
174	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_bx_ud2, BS3_PBC_NEAR
175	db X86_OP_PRF_SIZE_OP
176	sgdt [xBX]
177	.again: ud2
178	jmp .again
179	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_bx_ud2) == 4)
180	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_bx_ud2
181
182	%if TMPL_BITS == 64
183	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_rexw_bx_ud2
184	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_rexw_bx_ud2, BS3_PBC_NEAR
185	db X86_OP_REX_W
186	sgdt [xBX]
187	.again: ud2
188	jmp .again
189	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_rexw_bx_ud2) == 4)
190	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_rexw_bx_ud2
191
192	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2
193	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2, BS3_PBC_NEAR
194	db X86_OP_PRF_SIZE_OP
195	db X86_OP_REX_W
196	sgdt [xBX]
197	.again: ud2
198	jmp .again
199	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2) == 5)
200	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_rexw_bx_ud2
201	%endif
202
203	%if TMPL_BITS != 64
204	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_ss_bx_ud2
205	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_ss_bx_ud2, BS3_PBC_NEAR
206	sgdt [ss:xBX]
207	.again: ud2
208	jmp .again
209	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_ss_bx_ud2) == 4)
210	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_ss_bx_ud2
211
212	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_sgdt_opsize_ss_bx_ud2
213	BS3_PROC_BEGIN_CMN bs3CpuBasic2_sgdt_opsize_ss_bx_ud2, BS3_PBC_NEAR
214	db X86_OP_PRF_SIZE_OP
215	sgdt [ss:xBX]
216	.again: ud2
217	jmp .again
218	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_sgdt_opsize_ss_bx_ud2) == 5)
219	BS3_PROC_END_CMN bs3CpuBasic2_sgdt_opsize_ss_bx_ud2
220	%endif
221
222
223	;
224	; LIDT
225	;
226	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2
227	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
228	lidt [xBX]
229	sidt [BS3_NOT_64BIT(es:) xDI]
230	lidt [BS3_NOT_64BIT(es:) xSI]
231	.again:
232	ud2
233	jmp .again
234	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(9,11))
235	BS3_PROC_END_CMN bs3CpuBasic2_lidt_bx__sidt_es_di__lidt_es_si__ud2
236
237	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2
238	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
239	db X86_OP_PRF_SIZE_OP
240	lidt [xBX]
241	sidt [BS3_NOT_64BIT(es:) xDI]
242	lidt [BS3_NOT_64BIT(es:) xSI]
243	.again:
244	ud2
245	jmp .again
246	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(10,12))
247	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt_es_di__lidt_es_si__ud2
248
249	%if TMPL_BITS == 16
250	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2
251	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
252	db X86_OP_PRF_SIZE_OP
253	lidt [xBX]
254	jmp dword BS3_SEL_R0_CS32:.in_32bit wrt FLAT
255	BS3_SET_BITS 32
256	.in_32bit:
257	sidt [es:edi]
258	lidt [es:esi]
259	jmp dword BS3_SEL_R0_CS16:.again wrt CGROUP16
260	BS3_SET_BITS 16
261	.again:
262	ud2
263	jmp .again
264	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2) == 27)
265	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_bx__sidt32_es_di__lidt_es_si__ud2
266	%endif
267
268	%if TMPL_BITS == 64
269	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2
270	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
271	db X86_OP_REX_W
272	lidt [xBX]
273	sidt [xDI]
274	lidt [xSI]
275	.again:
276	ud2
277	jmp .again
278	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2) == 10)
279	BS3_PROC_END_CMN bs3CpuBasic2_lidt_rexw_bx__sidt_es_di__lidt_es_si__ud2
280
281	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2
282	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
283	db X86_OP_PRF_SIZE_OP
284	db X86_OP_REX_W
285	lidt [xBX]
286	sidt [xDI]
287	lidt [xSI]
288	.again:
289	ud2
290	jmp .again
291	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2) == 11)
292	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_rexw_bx__sidt_es_di__lidt_es_si__ud2
293	%endif
294
295	%if TMPL_BITS != 64
296	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2
297	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
298	lidt [ss:xBX]
299	sidt [BS3_NOT_64BIT(es:) xDI]
300	lidt [BS3_NOT_64BIT(es:) xSI]
301	.again:
302	ud2
303	jmp .again
304	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2) == 12)
305	BS3_PROC_END_CMN bs3CpuBasic2_lidt_ss_bx__sidt_es_di__lidt_es_si__ud2
306
307	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2
308	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2, BS3_PBC_NEAR
309	db X86_OP_PRF_SIZE_OP
310	lidt [ss:xBX]
311	sidt [BS3_NOT_64BIT(es:) xDI]
312	lidt [BS3_NOT_64BIT(es:) xSI]
313	.again:
314	ud2
315	jmp .again
316	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2) == 13)
317	BS3_PROC_END_CMN bs3CpuBasic2_lidt_opsize_ss_bx__sidt_es_di__lidt_es_si__ud2
318	%endif
319
320
321	;
322	; LGDT
323	;
324	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2
325	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
326	lgdt [xBX]
327	sgdt [BS3_NOT_64BIT(es:) xDI]
328	lgdt [BS3_NOT_64BIT(es:) xSI]
329	.again:
330	ud2
331	jmp .again
332	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(9,11))
333	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_bx__sgdt_es_di__lgdt_es_si__ud2
334
335	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2
336	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
337	db X86_OP_PRF_SIZE_OP
338	lgdt [xBX]
339	sgdt [BS3_NOT_64BIT(es:) xDI]
340	lgdt [BS3_NOT_64BIT(es:) xSI]
341	.again:
342	ud2
343	jmp .again
344	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2) == BS3_IF_64BIT_OTHERWISE(10,12))
345	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_bx__sgdt_es_di__lgdt_es_si__ud2
346
347	%if TMPL_BITS == 64
348	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
349	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
350	db X86_OP_REX_W
351	lgdt [xBX]
352	sgdt [xDI]
353	lgdt [xSI]
354	.again:
355	ud2
356	jmp .again
357	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 10)
358	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
359
360	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
361	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
362	db X86_OP_PRF_SIZE_OP
363	db X86_OP_REX_W
364	lgdt [xBX]
365	sgdt [xDI]
366	lgdt [xSI]
367	.again:
368	ud2
369	jmp .again
370	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2) == 11)
371	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_rexw_bx__sgdt_es_di__lgdt_es_si__ud2
372	%endif
373
374	%if TMPL_BITS != 64
375	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2
376	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
377	lgdt [ss:xBX]
378	sgdt [BS3_NOT_64BIT(es:) xDI]
379	lgdt [BS3_NOT_64BIT(es:) xSI]
380	.again:
381	ud2
382	jmp .again
383	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 12)
384	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_ss_bx__sgdt_es_di__lgdt_es_si__ud2
385
386	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2
387	BS3_PROC_BEGIN_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2, BS3_PBC_NEAR
388	db X86_OP_PRF_SIZE_OP
389	lgdt [ss:xBX]
390	sgdt [BS3_NOT_64BIT(es:) xDI]
391	lgdt [BS3_NOT_64BIT(es:) xSI]
392	.again:
393	ud2
394	jmp .again
395	AssertCompile(.again - BS3_CMN_NM(bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2) == 13)
396	BS3_PROC_END_CMN bs3CpuBasic2_lgdt_opsize_ss_bx__sgdt_es_di__lgdt_es_si__ud2
397	%endif ; TMPL_BITS != 64
398
399	;
400	; #PF & #AC
401	;
402
403	; For testing read access.
404	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_mov_ax_ds_bx__ud2
405	BS3_PROC_BEGIN_CMN bs3CpuBasic2_mov_ax_ds_bx__ud2, BS3_PBC_NEAR
406	mov xAX, [xBX]
407	.again: ud2
408	jmp .again
409	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
410	BS3_PROC_END_CMN bs3CpuBasic2_mov_ax_ds_bx__ud2
411
412
413	; For testing write access.
414	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_mov_ds_bx_ax__ud2
415	BS3_PROC_BEGIN_CMN bs3CpuBasic2_mov_ds_bx_ax__ud2, BS3_PBC_NEAR
416	mov [xBX], xAX
417	.again: ud2
418	jmp .again
419	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
420	BS3_PROC_END_CMN bs3CpuBasic2_mov_ds_bx_ax__ud2
421
422
423	; For testing read+write access.
424	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_xchg_ds_bx_ax__ud2
425	BS3_PROC_BEGIN_CMN bs3CpuBasic2_xchg_ds_bx_ax__ud2, BS3_PBC_NEAR
426	xchg [xBX], xAX
427	.again: ud2
428	jmp .again
429	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
430	BS3_PROC_END_CMN bs3CpuBasic2_xchg_ds_bx_ax__ud2
431
432
433	; Another read+write access test.
434	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2
435	BS3_PROC_BEGIN_CMN bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2, BS3_PBC_NEAR
436	cmpxchg [xBX], xCX
437	.again: ud2
438	jmp .again
439	AssertCompile(.again - BS3_LAST_LABEL == 3 + (TMPL_BITS == 64))
440	BS3_PROC_END_CMN bs3CpuBasic2_cmpxchg_ds_bx_cx__ud2
441
442
443	; For testing read access from an aborted instruction: DIV by zero
444	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_div_ds_bx__ud2
445	BS3_PROC_BEGIN_CMN bs3CpuBasic2_div_ds_bx__ud2, BS3_PBC_NEAR
446	div xPRE [xBX]
447	.again: ud2
448	jmp .again
449	AssertCompile(.again - BS3_LAST_LABEL == 2 + (TMPL_BITS == 64))
450	BS3_PROC_END_CMN bs3CpuBasic2_div_ds_bx__ud2
451
452	; For testing FLD m80 alignment (#AC).
453	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fld_ds_bx__ud2
454	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2, BS3_PBC_NEAR
455	fninit ; make sure to not trigger a stack overflow.
456	.actual_test_instruction:
457	fld tword [xBX]
458	.again: ud2
459	jmp .again
460	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2)
461	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fld_ds_bx__ud2
462
463	; For testing FBLD m80 alignment (#AC).
464	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fbld_ds_bx__ud2
465	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2, BS3_PBC_NEAR
466	fninit ; make sure to not trigger a stack overflow.
467	.actual_test_instruction:
468	fbld tword [xBX]
469	.again: ud2
470	jmp .again
471	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 2)
472	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fbld_ds_bx__ud2
473
474	; For testing FST m80 alignment (#AC).
475	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2
476	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2, BS3_PBC_NEAR
477	fninit ; make sure to not trigger a stack overflow.
478	fldz ; make sure we've got something to store
479	.actual_test_instruction:
480	fstp tword [xBX]
481	.again: ud2
482	jmp .again
483	AssertCompile(.actual_test_instruction - BS3_LAST_LABEL == 4)
484	BS3_PROC_END_CMN bs3CpuBasic2_fninit_fldz_fstp_ds_bx__ud2
485
486	; For testing FXSAVE alignment (#AC/#GP).
487	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_fxsave_ds_bx__ud2
488	BS3_PROC_BEGIN_CMN bs3CpuBasic2_fxsave_ds_bx__ud2, BS3_PBC_NEAR
489	fxsave [xBX]
490	.again: ud2
491	jmp .again
492	BS3_PROC_END_CMN bs3CpuBasic2_fxsave_ds_bx__ud2
493
494
495	; Two memory operands: push [mem]
496	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_push_ds_bx__ud2
497	BS3_PROC_BEGIN_CMN bs3CpuBasic2_push_ds_bx__ud2, BS3_PBC_NEAR
498	push xPRE [xBX]
499	.again: ud2
500	jmp .again
501	AssertCompile(.again - BS3_LAST_LABEL == 2)
502	BS3_PROC_END_CMN bs3CpuBasic2_push_ds_bx__ud2
503
504	; Two memory operands: pop [mem]
505	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_push_ax__pop_ds_bx__ud2
506	BS3_PROC_BEGIN_CMN bs3CpuBasic2_push_ax__pop_ds_bx__ud2, BS3_PBC_NEAR
507	push xAX
508	pop xPRE [xBX]
509	.again: ud2
510	jmp .again
511	AssertCompile(.again - BS3_LAST_LABEL == 3)
512	BS3_PROC_END_CMN bs3CpuBasic2_push_ax__pop_ds_bx__ud2
513
514	; Two memory operands: call [mem]
515	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ds_bx__ud2
516	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ds_bx__ud2, BS3_PBC_NEAR
517	call xPRE [xBX]
518	.again: ud2
519	jmp .again
520	AssertCompile(.again - BS3_LAST_LABEL == 2)
521	BS3_PROC_END_CMN bs3CpuBasic2_call_ds_bx__ud2
522
523	; For testing #GP vs #PF write
524	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_insb__ud2
525	BS3_PROC_BEGIN_CMN bs3CpuBasic2_insb__ud2, BS3_PBC_NEAR
526	insb
527	.again: ud2
528	jmp .again
529	AssertCompile(.again - BS3_LAST_LABEL == 1)
530	BS3_PROC_END_CMN bs3CpuBasic2_insb__ud2
531
532
533	;*********************************************************************************************************************************
534	;* Non-far JMP & CALL Tests (simple ones). *
535	;*********************************************************************************************************************************
536
537	; jmp rel8 (forwards)
538	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb__ud2
539	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb__ud2, BS3_PBC_NEAR
540	jmp short .again
541	.post_jmp:
542	times 7 int3
543	.again: ud2
544	int3
545	jmp .again
546	AssertCompile(.post_jmp - BS3_LAST_LABEL == 2)
547	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb__ud2
548
549
550	; jmp rel8 (backwards)
551	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jb_back__ud2),.again), function, 2
552	ud2
553	times 7 int3
554	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_back__ud2
555	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_back__ud2, BS3_PBC_NEAR
556	jmp short .again
557	.post_jmp:
558	int3
559	AssertCompile(.post_jmp - BS3_LAST_LABEL == 2)
560	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_back__ud2
561
562
563	; jmp rel16 (forwards)
564	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv__ud2
565	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv__ud2, BS3_PBC_NEAR
566	jmp near .again
567	.post_jmp:
568	times 9 int3
569	.again: ud2
570	int3
571	jmp .again
572	%if TMPL_BITS == 16
573	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
574	%else
575	AssertCompile(.post_jmp - BS3_LAST_LABEL == 5)
576	%endif
577	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv__ud2
578
579
580	; jmp rel16 (backwards)
581	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_back__ud2),.again), function, 2
582	ud2
583	times 6 int3
584	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_back__ud2
585	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_back__ud2, BS3_PBC_NEAR
586	jmp near .again
587	.post_jmp:
588	int3
589	%if TMPL_BITS == 16
590	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
591	%else
592	AssertCompile(.post_jmp - BS3_LAST_LABEL == 5)
593	%endif
594	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_back__ud2
595
596
597	; jmp [indirect]
598	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem__ud2
599	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem__ud2, BS3_PBC_NEAR
600	%if TMPL_BITS == 16
601	jmp [word cs:.npAgain]
602	%elif TMPL_BITS == 32
603	jmp [dword cs:.npAgain]
604	%else
605	jmp [.npAgain]
606	%endif
607	.post_jmp:
608	times 9 int3
609	.npAgain:
610	%if TMPL_BITS == 16
611	dw BS3_TEXT16_WRT(.again)
612	%else
613	dd .again wrt FLAT
614	%if TMPL_BITS == 64
615	dd 0
616	%endif
617	%endif
618	.again: ud2
619	int3
620	jmp .again
621	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem__ud2
622
623	; jmp [xAX]
624	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xAX__ud2
625	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xAX__ud2, BS3_PBC_NEAR
626	jmp xAX
627	.post_jmp:
628	times 17 int3
629	.again: ud2
630	int3
631	jmp .again
632	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xAX__ud2
633
634	; jmp [xDI]
635	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xDI__ud2
636	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xDI__ud2, BS3_PBC_NEAR
637	jmp xDI
638	.post_jmp:
639	times 17 int3
640	.again: ud2
641	int3
642	jmp .again
643	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xDI__ud2
644
645	%if TMPL_BITS == 64
646	; jmp [xAX]
647	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_r9__ud2
648	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_r9__ud2, BS3_PBC_NEAR
649	jmp r9
650	.post_jmp:
651	times 17 int3
652	.again: ud2
653	int3
654	jmp .again
655	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_r9__ud2
656	%endif
657
658
659	; call rel16/32 (forwards)
660	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv__ud2
661	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv__ud2, BS3_PBC_NEAR
662	call near .again
663	.post_call:
664	times 9 int3
665	.again: ud2
666	int3
667	jmp .again
668	%if TMPL_BITS == 16
669	AssertCompile(.post_call - BS3_LAST_LABEL == 3)
670	%else
671	AssertCompile(.post_call - BS3_LAST_LABEL == 5)
672	%endif
673	BS3_PROC_END_CMN bs3CpuBasic2_call_jv__ud2
674
675	; call rel16/32 (backwards)
676	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_back__ud2),.again), function, 2
677	ud2
678	times 6 int3
679	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_back__ud2
680	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_back__ud2, BS3_PBC_NEAR
681	call near .again
682	.post_call:
683	int3
684	%if TMPL_BITS == 16
685	AssertCompile(.post_call - BS3_LAST_LABEL == 3)
686	%else
687	AssertCompile(.post_call - BS3_LAST_LABEL == 5)
688	%endif
689	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_back__ud2
690
691	; call [indirect]
692	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem__ud2
693	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem__ud2, BS3_PBC_NEAR
694	%if TMPL_BITS == 16
695	call [word cs:.npAgain]
696	%elif TMPL_BITS == 32
697	call [dword cs:.npAgain]
698	%else
699	call [.npAgain]
700	%endif
701	.post_call:
702	times 9 int3
703	.npAgain:
704	%if TMPL_BITS == 16
705	dw BS3_TEXT16_WRT(.again)
706	%else
707	dd .again wrt FLAT
708	%if TMPL_BITS == 64
709	dd 0
710	%endif
711	%endif
712	.again: ud2
713	int3
714	jmp .again
715	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem__ud2
716
717	; call [xAX]
718	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xAX__ud2
719	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xAX__ud2, BS3_PBC_NEAR
720	call xAX
721	.post_call:
722	times 17 int3
723	.again: ud2
724	int3
725	jmp .again
726	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xAX__ud2
727
728	; call [xDI]
729	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xDI__ud2
730	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xDI__ud2, BS3_PBC_NEAR
731	call xDI
732	.post_call:
733	times 17 int3
734	.again: ud2
735	int3
736	jmp .again
737	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xDI__ud2
738
739	%if TMPL_BITS == 64
740	; call [xAX]
741	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_r9__ud2
742	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_r9__ud2, BS3_PBC_NEAR
743	call r9
744	.post_call:
745	times 17 int3
746	.again: ud2
747	int3
748	jmp .again
749	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_r9__ud2
750	%endif
751
752
753	;
754	; When applying opsize, we need to put this in the 16-bit text segment to
755	; better control where we end up in 32-bit and 64-bit mode.
756	;
757	; Try keep the code out of the IVT and BIOS data area. This unfortunately
758	; requires manual padding here.
759	;
760	BS3_BEGIN_TEXT16
761	BS3_SET_BITS TMPL_BITS
762	%if TMPL_BITS == 32
763	align 0x100, int3 ; Currently takes us up to 0x400 (max align value is 0x100)
764	times 0x200 int3 ; Brings us up to 0x600.
765	%endif
766
767	BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_begin), , 1
768
769
770	; jmp rel8 (forwards) with opsize override.
771	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize__ud2
772	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize__ud2, BS3_PBC_NEAR
773	db 66h
774	jmp short .again
775	.post_jmp:
776	times 8 int3
777	.again: ud2
778	int3
779	jmp .again
780	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
781	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize__ud2
782
783
784	; jmp rel8 (backwards) with opsize override.
785	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jb_opsize_back__ud2),.again), function, 2
786	ud2
787	times 19 int3
788	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize_back__ud2
789	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2, BS3_PBC_NEAR
790	db 66h
791	jmp short .again
792	.post_jmp:
793	int3
794	AssertCompile(.post_jmp - BS3_LAST_LABEL == 3)
795	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2
796
797
798	; jmp rel16 (forwards) with opsize override.
799	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize__ud2
800	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize__ud2, BS3_PBC_NEAR
801	db 66h, 0e9h ; o32 jmp near .again
802	%if TMPL_BITS != 32
803	dd 11
804	%else
805	dw 11
806	%endif
807	.post_jmp:
808	times 11 int3
809	.again: ud2
810	int3
811	jmp .again
812	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize__ud2
813
814
815	; jmp rel16 (backwards) with opsize override.
816	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again), function, 2
817	ud2
818	times 19 int3
819	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize_back__ud2
820	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2, BS3_PBC_NEAR
821	%if TMPL_BITS != 32
822	db 66h, 0e9h ; o32 jmp near .again
823	dd RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again) - .post_jmp
824	%else
825	db 66h, 0e9h ; o16 jmp near .again
826	dw RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_jmp_jv_opsize_back__ud2),.again) - .post_jmp
827	%endif
828	.post_jmp:
829	int3
830	BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2
831
832
833	BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_end), , 1
834	int3
835
836	; jmp [indirect]
837	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem_opsize__ud2
838	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2, BS3_PBC_NEAR
839	db 66h
840	%if TMPL_BITS == 16
841	jmp [word cs:.npAgain]
842	%elif TMPL_BITS == 32
843	jmp [dword cs:.npAgain wrt FLAT]
844	%else
845	jmp [.npAgain wrt FLAT]
846	%endif
847	.post_jmp:
848	times 9 int3
849	.npAgain:
850	%if TMPL_BITS == 16
851	dw BS3_TEXT16_WRT(.again)
852	dw 0
853	%else
854	dw .again wrt CGROUP16
855	dw 0faceh, 0f00dh, 07777h ; non-canonical address
856	%endif
857	.again: ud2
858	int3
859	jmp .again
860	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2
861
862	%if TMPL_BITS == 64
863	; jmp [indirect] - 64-bit intel version
864	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel
865	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel, BS3_PBC_NEAR
866	db 66h
867	jmp [.npAgain wrt FLAT]
868	.post_jmp:
869	times 8 int3
870	.npAgain:
871	dd .again wrt FLAT
872	dd 0
873	.again: ud2
874	int3
875	jmp .again
876	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_mem_opsize__ud2__intel
877	%endif
878
879	; jmp [xAX]
880	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_ind_xAX_opsize__ud2
881	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_ind_xAX_opsize__ud2, BS3_PBC_NEAR
882	db 66h
883	jmp xAX
884	.post_jmp:
885	times 8 int3
886	.again: ud2
887	int3
888	jmp .again
889	BS3_PROC_END_CMN bs3CpuBasic2_jmp_ind_xAX_opsize__ud2
890
891
892	; call rel16/32 (forwards) with opsize override.
893	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_opsize__ud2
894	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_opsize__ud2, BS3_PBC_NEAR
895	db 66h, 0e8h ; o32 jmp near .again
896	%if TMPL_BITS != 32
897	dd 12
898	%else
899	dw 12
900	%endif
901	.post_call:
902	times 12 int3
903	.again: ud2
904	int3
905	jmp .again
906	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_opsize__ud2
907
908
909	; call rel16/32 (backwards) with opsize override.
910	BS3_GLOBAL_NAME_EX RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again), function, 2
911	ud2
912	times 19 int3
913	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_jv_opsize_back__ud2
914	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_jv_opsize_back__ud2, BS3_PBC_NEAR
915	%if TMPL_BITS != 32
916	db 66h, 0e8h ; o32 call near .again
917	dd RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again) - .post_call
918	%else
919	db 66h, 0e8h ; o16 call near .again
920	dw RT_CONCAT(BS3_CMN_NM(bs3CpuBasic2_call_jv_opsize_back__ud2),.again) - .post_call
921	%endif
922	.post_call:
923	int3
924	BS3_PROC_END_CMN bs3CpuBasic2_call_jv_opsize_back__ud2
925
926	; call [indirect]
927	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem_opsize__ud2
928	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2, BS3_PBC_NEAR
929	db 66h
930	%if TMPL_BITS == 16
931	call [word cs:.npAgain]
932	%elif TMPL_BITS == 32
933	call [dword cs:.npAgain wrt FLAT]
934	%else
935	call [.npAgain wrt FLAT]
936	%endif
937	.post_call:
938	times 9 int3
939	.npAgain:
940	%if TMPL_BITS == 16
941	dw BS3_TEXT16_WRT(.again)
942	dw 0
943	%else
944	dw .again wrt CGROUP16
945	dw 0faceh, 0f00dh, 07777h ; non-canonical address
946	%endif
947	.again: ud2
948	int3
949	jmp .again
950	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2
951
952	%if TMPL_BITS == 64
953	; call [indirect] - 64-bit intel version
954	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_mem_opsize__ud2__intel
955	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2__intel, BS3_PBC_NEAR
956	db 66h
957	call [.npAgain wrt FLAT]
958	.post_call:
959	times 8 int3
960	.npAgain:
961	dd .again wrt FLAT
962	dd 0
963	.again: ud2
964	int3
965	jmp .again
966	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_mem_opsize__ud2__intel
967	%endif
968
969	; call [xAX]
970	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_call_ind_xAX_opsize__ud2
971	BS3_PROC_BEGIN_CMN bs3CpuBasic2_call_ind_xAX_opsize__ud2, BS3_PBC_NEAR
972	db 66h
973	call xAX
974	.post_call:
975	times 8 int3
976	.again: ud2
977	int3
978	jmp .again
979	BS3_PROC_END_CMN bs3CpuBasic2_call_ind_xAX_opsize__ud2
980
981
982
983	;*********************************************************************************************************************************
984	;* FAR JMP ABS *
985	;*********************************************************************************************************************************
986
987	%if TMPL_BITS == 16
988	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_rm__ud2
989	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_rm__ud2, BS3_PBC_NEAR
990	db 0eah
991	dw .again wrt CGROUP16
992	dw BS3_SEL_TEXT16
993	.post_jmp:
994	times 2 int3
995	.again: ud2
996	int3
997	jmp .again
998	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_rm__ud2
999	%endif
1000
1001	%if TMPL_BITS != 64
1002
1003	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r0__ud2
1004	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r0__ud2, BS3_PBC_NEAR
1005	db 0eah
1006	%if TMPL_BITS == 16
1007	dw .again wrt CGROUP16
1008	dw BS3_SEL_R0_CS16
1009	%else
1010	dd .again wrt FLAT
1011	dw BS3_SEL_R0_CS32
1012	%endif
1013	.post_jmp:
1014	times 7 int3
1015	.again: ud2
1016	int3
1017	jmp .again
1018	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r0__ud2
1019
1020	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r1__ud2
1021	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r1__ud2, BS3_PBC_NEAR
1022	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1023	%if TMPL_BITS == 16
1024	dw .again wrt CGROUP16
1025	dw BS3_SEL_R1_CS16 \| 1
1026	%else
1027	dd .again wrt FLAT
1028	dw BS3_SEL_R1_CS32 \| 1
1029	%endif
1030	.again: ud2
1031	jmp .again
1032	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r1__ud2
1033
1034	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r2__ud2
1035	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r2__ud2, BS3_PBC_NEAR
1036	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1037	%if TMPL_BITS == 16
1038	dw .again wrt CGROUP16
1039	dw BS3_SEL_R2_CS16 \| 2
1040	%else
1041	dd .again wrt FLAT
1042	dw BS3_SEL_R2_CS32 \| 2
1043	%endif
1044	.again: ud2
1045	jmp .again
1046	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r2__ud2
1047
1048	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_same_r3__ud2
1049	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_same_r3__ud2, BS3_PBC_NEAR
1050	db 0eah ; inter privilege jmp -> #GP(dst-cs)
1051	%if TMPL_BITS == 16
1052	dw .again wrt CGROUP16
1053	dw BS3_SEL_R3_CS16 \| 3
1054	%else
1055	dd .again wrt FLAT
1056	dw BS3_SEL_R3_CS32 \| 3
1057	%endif
1058	.again: ud2
1059	jmp .again
1060	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_same_r3__ud2
1061
1062	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2
1063	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2, BS3_PBC_NEAR
1064	db 066h, 0eah
1065	%if TMPL_BITS == 32
1066	dw .again wrt CGROUP16
1067	dw BS3_SEL_R0_CS16
1068	%else
1069	dd .again wrt FLAT
1070	dw BS3_SEL_R0_CS32
1071	%endif
1072	times 4 int3
1073	.again: ud2
1074	jmp .again
1075	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_opsize_flipbit_r0__ud2
1076
1077	; Do a jmp to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1078	; result in a 16-bit CS with zero base and 4G limit.
1079	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2
1080	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2, BS3_PBC_NEAR
1081	%if TMPL_BITS == 16
1082	db 066h
1083	%endif
1084	db 0eah
1085	dd .jmp_target wrt FLAT
1086	dw BS3_SEL_R0_CS64
1087	times 8 int3
1088	.jmp_target:
1089	salc ; #UD in 64-bit mode
1090	.again: ud2
1091	jmp .again
1092	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_r0_cs64__ud2
1093
1094	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1095	; pre-AMD64 software using the L bit for other stuff. (Don't run in long mode
1096	; w/o copying the 3 bytes to the 0xxxxh memory range.)
1097	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2
1098	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2, BS3_PBC_NEAR
1099	%if TMPL_BITS != 16
1100	db 066h
1101	%endif
1102	db 0eah
1103	dw .jmp_target wrt CGROUP16
1104	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1105	times 3 int3
1106	.jmp_target:
1107	salc ; #UD in 64-bit mode
1108	.again: ud2
1109	jmp .again
1110	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_ptr_r0_cs16l__ud2
1111
1112	%endif ; TMPL_BITS != 64
1113
1114
1115
1116	;*********************************************************************************************************************************
1117	;* FAR CALL ABS *
1118	;*********************************************************************************************************************************
1119
1120	%if TMPL_BITS == 16
1121	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_rm__ud2
1122	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_rm__ud2, BS3_PBC_NEAR
1123	db 09ah
1124	dw .again wrt CGROUP16
1125	dw BS3_SEL_TEXT16
1126	.post_call:
1127	times 2 int3
1128	.again: ud2
1129	int3
1130	jmp .again
1131	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_rm__ud2
1132	%endif
1133
1134	%if TMPL_BITS != 64
1135
1136	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r0__ud2
1137	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r0__ud2, BS3_PBC_NEAR
1138	db 09ah
1139	%if TMPL_BITS == 16
1140	dw .again wrt CGROUP16
1141	dw BS3_SEL_R0_CS16
1142	%else
1143	dd .again wrt FLAT
1144	dw BS3_SEL_R0_CS32
1145	%endif
1146	.post_call:
1147	times 7 int3
1148	.again: ud2
1149	int3
1150	jmp .again
1151	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r0__ud2
1152
1153	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r1__ud2
1154	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r1__ud2, BS3_PBC_NEAR
1155	db 09ah
1156	%if TMPL_BITS == 16
1157	dw .again wrt CGROUP16
1158	dw BS3_SEL_R1_CS16 \| 1
1159	%else
1160	dd .again wrt FLAT
1161	dw BS3_SEL_R1_CS32 \| 1
1162	%endif
1163	.again: ud2
1164	jmp .again
1165	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r1__ud2
1166
1167	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r2__ud2
1168	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r2__ud2, BS3_PBC_NEAR
1169	db 09ah
1170	%if TMPL_BITS == 16
1171	dw .again wrt CGROUP16
1172	dw BS3_SEL_R2_CS16 \| 2
1173	%else
1174	dd .again wrt FLAT
1175	dw BS3_SEL_R2_CS32 \| 2
1176	%endif
1177	.again: ud2
1178	jmp .again
1179	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r2__ud2
1180
1181	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_same_r3__ud2
1182	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_same_r3__ud2, BS3_PBC_NEAR
1183	db 09ah
1184	%if TMPL_BITS == 16
1185	dw .again wrt CGROUP16
1186	dw BS3_SEL_R3_CS16 \| 3
1187	%else
1188	dd .again wrt FLAT
1189	dw BS3_SEL_R3_CS32 \| 3
1190	%endif
1191	.again: ud2
1192	jmp .again
1193	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_same_r3__ud2
1194
1195	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2
1196	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2, BS3_PBC_NEAR
1197	db 066h, 09ah
1198	%if TMPL_BITS == 32
1199	dw .again wrt CGROUP16
1200	dw BS3_SEL_R0_CS16
1201	%else
1202	dd .again wrt FLAT
1203	dw BS3_SEL_R0_CS32
1204	%endif
1205	times 4 int3
1206	.again: ud2
1207	jmp .again
1208	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_opsize_flipbit_r0__ud2
1209
1210	; Do a call to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1211	; result in a 16-bit CS with zero base and 4G limit.
1212	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_r0_cs64__ud2
1213	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_r0_cs64__ud2, BS3_PBC_NEAR
1214	%if TMPL_BITS == 16
1215	db 066h
1216	%endif
1217	db 09ah
1218	dd .call_target wrt FLAT
1219	dw BS3_SEL_R0_CS64
1220	times 8 int3
1221	.call_target:
1222	salc ; #UD in 64-bit mode
1223	.again: ud2
1224	jmp .again
1225	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_r0_cs64__ud2
1226
1227	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1228	; pre-AMD64 software using the L bit for other stuff. (Don't run in long mode
1229	; w/o copying the 3 bytes to the 0xxxxh memory range.)
1230	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_callf_ptr_r0_cs16l__ud2
1231	BS3_PROC_BEGIN_CMN bs3CpuBasic2_callf_ptr_r0_cs16l__ud2, BS3_PBC_NEAR
1232	%if TMPL_BITS != 16
1233	db 066h
1234	%endif
1235	db 09ah
1236	dw .call_target wrt CGROUP16
1237	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1238	times 3 int3
1239	.call_target:
1240	salc ; #UD in 64-bit mode
1241	.again: ud2
1242	jmp .again
1243	BS3_PROC_END_CMN bs3CpuBasic2_callf_ptr_r0_cs16l__ud2
1244
1245	%endif ; TMPL_BITS != 64
1246
1247
1248	;*********************************************************************************************************************************
1249	;* INDIRECT FAR JMP *
1250	;*********************************************************************************************************************************
1251
1252	%if TMPL_BITS == 16
1253	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_rm__ud2
1254	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_rm__ud2, BS3_PBC_NEAR
1255	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1256	int3
1257	.fpfn:
1258	dw .again wrt CGROUP16
1259	dw BS3_SEL_TEXT16
1260	.post_jmp:
1261	times 2 int3
1262	.again: ud2
1263	int3
1264	jmp .again
1265	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_rm__ud2
1266	%endif
1267
1268	; The first 64-bit versions follow AMD behaviour
1269
1270	%ifndef jmpf_macro_defined
1271	%define jmpf_macro_defined
1272	%macro jmpf_macro 2
1273
1274	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1
1275	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1, BS3_PBC_NEAR
1276	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1277	.fpfn:
1278	%if TMPL_BITS == 16
1279	dw .again wrt CGROUP16
1280	dw BS3_SEL_R0_CS16
1281	%elif TMPL_BITS == 32
1282	dd .again wrt FLAT
1283	dw BS3_SEL_R0_CS32
1284	%else
1285	dd .again wrt FLAT
1286	%if %2 != 0
1287	dd 0fffff000h
1288	%endif
1289	dw BS3_SEL_R0_CS64
1290	%endif
1291	.post_jmp:
1292	times 7 int3
1293	.again: ud2
1294	int3
1295	jmp .again
1296	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r0__ud2 %+ %1
1297
1298	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1
1299	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1, BS3_PBC_NEAR
1300	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1301	.fpfn:
1302	%if TMPL_BITS == 16
1303	dw .again wrt CGROUP16
1304	dw BS3_SEL_R1_CS16 \| 1
1305	%elif TMPL_BITS == 32
1306	dd .again wrt FLAT
1307	dw BS3_SEL_R1_CS32 \| 1
1308	%else
1309	dd .again wrt FLAT
1310	%if %2 != 0
1311	dd 0fffff000h
1312	%endif
1313	dw BS3_SEL_R1_CS64 \| 1
1314	%endif
1315	.again: ud2
1316	jmp .again
1317	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r1__ud2 %+ %1
1318
1319	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1
1320	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1, BS3_PBC_NEAR
1321	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 0
1322	.fpfn:
1323	%if TMPL_BITS == 16
1324	dw .again wrt CGROUP16
1325	dw BS3_SEL_R2_CS16 \| 2
1326	%elif TMPL_BITS == 32
1327	dd .again wrt FLAT
1328	dw BS3_SEL_R2_CS32 \| 2
1329	%else
1330	dd .again wrt FLAT
1331	dw BS3_SEL_R2_CS64 \| 2
1332	%endif
1333	.again: ud2
1334	jmp .again
1335	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r2__ud2 %+ %1
1336
1337	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1
1338	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1, BS3_PBC_NEAR
1339	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 1
1340	.fpfn:
1341	%if TMPL_BITS == 16
1342	dw .again wrt CGROUP16
1343	dw BS3_SEL_R3_CS16 \| 3
1344	%elif TMPL_BITS == 32
1345	dd .again wrt FLAT
1346	dw BS3_SEL_R3_CS32 \| 3
1347	%else
1348	dd .again wrt FLAT
1349	%if %2 != 0
1350	dd 0fffff000h
1351	%endif
1352	dw BS3_SEL_R3_CS64 \| 3
1353	%endif
1354	.again: ud2
1355	jmp .again
1356	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_same_r3__ud2 %+ %1
1357
1358	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1
1359	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1, BS3_PBC_NEAR
1360	%if TMPL_BITS != 16
1361	db 66h
1362	%endif
1363	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 0
1364	.fpfn:
1365	;%if TMPL_BITS != 64 \|\| %2 == 0
1366	dw .again wrt CGROUP16
1367	;%else
1368	; dd .again wrt CGROUP16, 0
1369	;%endif
1370	dw BS3_SEL_R0_CS16
1371	times 4 int3
1372	.again: ud2
1373	jmp .again
1374	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs16__ud2 %+ %1
1375
1376	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1
1377	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1, BS3_PBC_NEAR
1378	%if TMPL_BITS == 16
1379	db 66h
1380	%endif
1381	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 0
1382	.fpfn:
1383	dd .again wrt FLAT
1384	dw BS3_SEL_R0_CS32
1385	times 4 int3
1386	.again: ud2
1387	jmp .again
1388	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs32__ud2 %+ %1
1389
1390	; Do a jmp to BS3_SEL_R0_CS64. Except for when we're in long mode, this will
1391	; result in a 16-bit CS with zero base and 4G limit.
1392	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1
1393	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1, BS3_PBC_NEAR
1394	%if TMPL_BITS == 16
1395	db 066h
1396	%endif
1397	jmp far [BS3_CPUBAS2_REF_LABEL_VIA_CS(.fpfn)]
1398	.fpfn:
1399	dd .jmp_target wrt FLAT
1400	%if TMPL_BITS == 64 && %2 != 0
1401	dd 0fffff000h
1402	%endif
1403	dw BS3_SEL_R0_CS64
1404	times 8 int3
1405	.jmp_target:
1406	%if TMPL_BITS != 64
1407	salc ; #UD in 64-bit mode
1408	%endif
1409	.again: ud2
1410	jmp .again
1411	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs64__ud2 %+ %1
1412
1413	; Variation of the previous with a CS16 copy that has the L bit set, emulating
1414	; pre-AMD64 software using the L bit for other stuff. (Don't run _c16/32 in
1415	; long mode w/o copying the 3 bytes to the 0xxxxh memory range.)
1416	; The _c64 version will test that the base is ignored.
1417	BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1
1418	BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1, BS3_PBC_NEAR
1419	%if TMPL_BITS == 32
1420	db 066h
1421	%endif
1422	BS3_CPUBAS2_JMP_FAR_MEM_LABEL .fpfn, 0
1423	.fpfn:
1424	%if TMPL_BITS != 64
1425	dw .jmp_target wrt CGROUP16
1426	%else
1427	dd .jmp_target wrt FLAT
1428	%endif
1429	dw BS3_SEL_SPARE_00 ; ASSUMES this is set up as CGROUP16 but with L=1.
1430	times 3 int3
1431	.jmp_target:
1432	%if TMPL_BITS != 64
1433	salc ; #UD in 64-bit mode
1434	%endif
1435	.again: ud2
1436	jmp .again
1437	BS3_PROC_END_CMN bs3CpuBasic2_jmpf_mem_r0_cs16l__ud2 %+ %1
1438
1439	%endmacro
1440	%endif
1441
1442	; Instantiate the above code
1443	jmpf_macro , 0
1444	%if TMPL_BITS == 64
1445	jmpf_macro _intel, 1
1446	%endif
1447
1448
1449	%endif ; BS3_INSTANTIATING_CMN
1450
1451	%include "bs3kit-template-footer.mac" ; reset environment
1452

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