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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 66327

Last change on this file since 66327 was 66327, checked in by vboxsync, 8 years ago

IEM,CPUM: Implemented clflush Mb (0f ae /7).
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1/* $Id: bs3-cpu-generated-1-template.c 66327 2017-03-29 10:12:02Z vboxsync $ */
2/** @file
3 * BS3Kit - bs3-cpu-generated-1, C code template.
4 */
5
6/*
7 * Copyright (C) 2007-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27#ifndef BS3_INSTANTIATING_CMN
28# error "BS3_INSTANTIATING_CMN not defined"
29#endif
30
31
32/*********************************************************************************************************************************
33* Header Files *
34*********************************************************************************************************************************/
35#include <iprt/asm.h>
36#include <iprt/asm-amd64-x86.h>
37
38#include "bs3-cpu-generated-1.h"
39
40
41/*********************************************************************************************************************************
42* Defined Constants And Macros *
43*********************************************************************************************************************************/
44#define P_CS X86_OP_PRF_CS
45#define P_SS X86_OP_PRF_SS
46#define P_DS X86_OP_PRF_DS
47#define P_ES X86_OP_PRF_ES
48#define P_FS X86_OP_PRF_FS
49#define P_GS X86_OP_PRF_GS
50#define P_OZ X86_OP_PRF_SIZE_OP
51#define P_AZ X86_OP_PRF_SIZE_ADDR
52#define P_LK X86_OP_PRF_LOCK
53#define P_RN X86_OP_PRF_REPNZ
54#define P_RZ X86_OP_PRF_REPZ
55
56#define REX_WRBX (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_B | X86_OP_REX_X)
57#define REX_W___ (X86_OP_REX_W)
58#define REX_WR__ (X86_OP_REX_W | X86_OP_REX_R)
59#define REX_W_B_ (X86_OP_REX_W | X86_OP_REX_B)
60#define REX_W__X (X86_OP_REX_W | X86_OP_REX_X)
61#define REX_WRB_ (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_B)
62#define REX_WR_X (X86_OP_REX_W | X86_OP_REX_R | X86_OP_REX_X)
63#define REX_W_BX (X86_OP_REX_W | X86_OP_REX_B | X86_OP_REX_X)
64#define REX__R__ (X86_OP_REX_R)
65#define REX__RB_ (X86_OP_REX_R | X86_OP_REX_B)
66#define REX__R_X (X86_OP_REX_R | X86_OP_REX_X)
67#define REX__RBX (X86_OP_REX_R | X86_OP_REX_B | X86_OP_REX_X)
68#define REX___B_ (X86_OP_REX_B)
69#define REX___BX (X86_OP_REX_B | X86_OP_REX_X)
70#define REX____X (X86_OP_REX_X)
71#define REX_____ (0x40)
72
73
74/** @def BS3CG1_DPRINTF
75 * Debug print macro.
76 */
77#if 0
78# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
79# define BS3CG1_DEBUG_CTX_MOD
80#else
81# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
82#endif
83
84
85
86/*********************************************************************************************************************************
87* Structures and Typedefs *
88*********************************************************************************************************************************/
89/** Operand value location. */
90typedef enum BS3CG1OPLOC
91{
92 BS3CG1OPLOC_INVALID = 0,
93 BS3CG1OPLOC_CTX,
94 BS3CG1OPLOC_IMM,
95 BS3CG1OPLOC_MEM,
96 BS3CG1OPLOC_MEM_RW,
97 BS3CG1OPLOC_END
98} BS3CG1OPLOC;
99
100/**
101 * The state.
102 */
103typedef struct BS3CG1STATE
104{
105 /** @name Instruction details (expanded from BS3CG1INSTR).
106 * @{ */
107 /** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
108 const char BS3_FAR *pchMnemonic;
109 /** Pointer to the test header. */
110 PCBS3CG1TESTHDR pTestHdr;
111 /** Pointer to the per operand flags (g_abBs3Cg1Operands). */
112 const uint8_t BS3_FAR *pabOperands;
113 /** Opcode bytes (g_abBs3Cg1Opcodes). */
114 const uint8_t BS3_FAR *pabOpcodes;
115 /** The current instruction number in the input array (for error reporting). */
116 uint32_t iInstr;
117
118 /** The instruction flags. */
119 uint32_t fFlags;
120 /** The encoding. */
121 BS3CG1ENC enmEncoding;
122 /** The CPU test / CPU ID. */
123 BS3CG1CPU enmCpuTest;
124 /** Prefix sensitivity and requirements. */
125 BS3CG1PFXKIND enmPrefixKind;
126 /** Exception type (SSE, AVX). */
127 BS3CG1XCPTTYPE enmXcptType;
128 /** Per operand flags. */
129 BS3CG1OP aenmOperands[4];
130 /** Opcode bytes. */
131 uint8_t abOpcodes[4];
132
133 /** The length of the mnemonic. */
134 uint8_t cchMnemonic;
135 /** Whether to advance the mnemonic pointer or not. */
136 uint8_t fAdvanceMnemonic;
137 /** The number of opcode bytes. */
138 uint8_t cbOpcodes;
139 /** Number of operands. */
140 uint8_t cOperands;
141 /** @} */
142
143 /** Operand size in bytes (0 if not applicable). */
144 uint8_t cbOperand;
145 /** Current target ring (0..3). */
146 uint8_t uCpl;
147
148 /** The current test number. */
149 uint8_t iTest;
150
151 /** Target mode (g_bBs3CurrentMode). */
152 uint8_t bMode;
153 /** First ring being tested. */
154 uint8_t iFirstRing;
155 /** End of rings being tested. */
156 uint8_t iEndRing;
157
158
159 /** @name Current encoded instruction.
160 * @{ */
161 /** The size of the current instruction that we're testing. */
162 uint8_t cbCurInstr;
163 /** The size the prefixes. */
164 uint8_t cbCurPrefix;
165 /** The offset into abCurInstr of the immediate. */
166 uint8_t offCurImm;
167 /** Buffer for assembling the current instruction. */
168 uint8_t abCurInstr[24];
169
170 /** Set if the encoding can't be tested in the same ring as this test code.
171 * This is used to deal with encodings modifying SP/ESP/RSP. */
172 bool fSameRingNotOkay;
173 /** Whether to work the extended context too. */
174 bool fWorkExtCtx;
175 /** The aOperands index of the modrm.reg operand (if applicable). */
176 uint8_t iRegOp;
177 /** The aOperands index of the modrm.rm operand (if applicable). */
178 uint8_t iRmOp;
179
180 /** Operands details. */
181 struct
182 {
183 uint8_t cbOp;
184 /** BS3CG1OPLOC_XXX. */
185 uint8_t enmLocation;
186 /** The BS3CG1DST value for this field.
187 * Set to BS3CG1DST_INVALID if memory or immediate. */
188 uint8_t idxField;
189 /** Depends on enmLocation.
190 * - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
191 * - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
192 * - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
193 * - BS3CG1OPLOC_CTX: not used (use idxField instead).
194 */
195 uint8_t off;
196 } aOperands[4];
197 /** @} */
198
199 /** Page to put code in. When paging is enabled, the page before and after
200 * are marked not-present. */
201 uint8_t BS3_FAR *pbCodePg;
202 /** The flat address corresponding to pbCodePg. */
203 uintptr_t uCodePgFlat;
204 /** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
205 RTFAR16 CodePgFar;
206 /** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
207 uintptr_t CodePgRip;
208
209 /** Page for placing data operands in. When paging is enabled, the page before
210 * and after are marked not-present. */
211 uint8_t BS3_FAR *pbDataPg;
212 /** The flat address corresponding to pbDataPg. */
213 uintptr_t uDataPgFlat;
214 /** The 16-bit address corresponding to pbDataPg. */
215 RTFAR16 DataPgFar;
216
217 /** The name corresponding to bMode. */
218 const char BS3_FAR *pszMode;
219 /** The short name corresponding to bMode. */
220 const char BS3_FAR *pszModeShort;
221
222 /** @name Expected result (modifiable by output program).
223 * @{ */
224 /** The expected exception based on operand values or result.
225 * UINT8_MAX if no special exception expected. */
226 uint8_t bValueXcpt;
227 /** @} */
228 /** Alignment exception expected by the encoder.
229 * UINT8_MAX if no special exception expected. */
230 uint8_t bAlignmentXcpt;
231
232 /** The context we're working on. */
233 BS3REGCTX Ctx;
234 /** The trap context and frame. */
235 BS3TRAPFRAME TrapFrame;
236 /** Initial contexts, one for each ring. */
237 BS3REGCTX aInitialCtxs[4];
238
239 /** The extended context we're working on (input, expected output). */
240 PBS3EXTCTX pExtCtx;
241 /** The extended result context (analoguous to TrapFrame). */
242 PBS3EXTCTX pResultExtCtx;
243 /** The initial extended context. */
244 PBS3EXTCTX pInitialExtCtx;
245
246 /** Memory operand scratch space. */
247 union
248 {
249 uint8_t ab[128];
250 uint16_t au16[128 / sizeof(uint16_t)];
251 uint32_t au32[128 / sizeof(uint32_t)];
252 uint64_t au64[128 / sizeof(uint64_t)];
253 } MemOp;
254
255 /** Array parallel to aInitialCtxs for saving segment registers. */
256 struct
257 {
258 RTSEL ds;
259 } aSavedSegRegs[4];
260
261} BS3CG1STATE;
262/** Pointer to the generated test state. */
263typedef BS3CG1STATE *PBS3CG1STATE;
264
265
266#define BS3CG1_PF_OZ UINT16_C(0x0001)
267#define BS3CG1_PF_AZ UINT16_C(0x0002)
268#define BS3CG1_PF_CS UINT16_C(0x0004)
269#define BS3CG1_PF_DS UINT16_C(0x0008)
270#define BS3CG1_PF_ES UINT16_C(0x0010)
271#define BS3CG1_PF_FS UINT16_C(0x0020)
272#define BS3CG1_PF_GS UINT16_C(0x0040)
273#define BS3CG1_PF_SS UINT16_C(0x0080)
274#define BS3CG1_PF_SEGS (BS3CG1_PF_CS | BS3CG1_PF_DS | BS3CG1_PF_ES | BS3CG1_PF_FS | BS3CG1_PF_GS | BS3CG1_PF_SS)
275#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS | BS3CG1_PF_AZ)
276#define BS3CG1_PF_LK UINT16_C(0x0100)
277#define BS3CG1_PF_RN UINT16_C(0x0200)
278#define BS3CG1_PF_RZ UINT16_C(0x0400)
279#define BS3CG1_PF_W UINT16_C(0x0800) /**< REX.W */
280#define BS3CG1_PF_R UINT16_C(0x1000) /**< REX.R */
281#define BS3CG1_PF_B UINT16_C(0x2000) /**< REX.B */
282#define BS3CG1_PF_X UINT16_C(0x4000) /**< REX.X */
283
284
285/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
286#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
287/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
288 * the field size (2, 4, or 8). */
289#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
290
291
292
293/*********************************************************************************************************************************
294* Global Variables *
295*********************************************************************************************************************************/
296/** Destination field sizes indexed by bBS3CG1DST.
297 * Zero means operand size sized. */
298static const uint8_t g_acbBs3Cg1DstFields[] =
299{
300 /* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
301
302 /* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
303 /* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
304 /* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
305 /* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
306 /* [BS3CG1DST_EFL] = */ 4,
307 /* [BS3CG1DST_EFL_UNDEF]=*/ 4,
308
309 /* [BS3CG1DST_AL] = */ 1,
310 /* [BS3CG1DST_CL] = */ 1,
311 /* [BS3CG1DST_DL] = */ 1,
312 /* [BS3CG1DST_BL] = */ 1,
313 /* [BS3CG1DST_AH] = */ 1,
314 /* [BS3CG1DST_CH] = */ 1,
315 /* [BS3CG1DST_DH] = */ 1,
316 /* [BS3CG1DST_BH] = */ 1,
317 /* [BS3CG1DST_SPL] = */ 1,
318 /* [BS3CG1DST_BPL] = */ 1,
319 /* [BS3CG1DST_SIL] = */ 1,
320 /* [BS3CG1DST_DIL] = */ 1,
321 /* [BS3CG1DST_R8L] = */ 1,
322 /* [BS3CG1DST_R9L] = */ 1,
323 /* [BS3CG1DST_R10L] = */ 1,
324 /* [BS3CG1DST_R11L] = */ 1,
325 /* [BS3CG1DST_R12L] = */ 1,
326 /* [BS3CG1DST_R13L] = */ 1,
327 /* [BS3CG1DST_R14L] = */ 1,
328 /* [BS3CG1DST_R15L] = */ 1,
329
330 /* [BS3CG1DST_AX] = */ 2,
331 /* [BS3CG1DST_CX] = */ 2,
332 /* [BS3CG1DST_DX] = */ 2,
333 /* [BS3CG1DST_BX] = */ 2,
334 /* [BS3CG1DST_SP] = */ 2,
335 /* [BS3CG1DST_BP] = */ 2,
336 /* [BS3CG1DST_SI] = */ 2,
337 /* [BS3CG1DST_DI] = */ 2,
338 /* [BS3CG1DST_R8W] = */ 2,
339 /* [BS3CG1DST_R9W] = */ 2,
340 /* [BS3CG1DST_R10W] = */ 2,
341 /* [BS3CG1DST_R11W] = */ 2,
342 /* [BS3CG1DST_R12W] = */ 2,
343 /* [BS3CG1DST_R13W] = */ 2,
344 /* [BS3CG1DST_R14W] = */ 2,
345 /* [BS3CG1DST_R15W] = */ 2,
346
347 /* [BS3CG1DST_EAX] = */ 4,
348 /* [BS3CG1DST_ECX] = */ 4,
349 /* [BS3CG1DST_EDX] = */ 4,
350 /* [BS3CG1DST_EBX] = */ 4,
351 /* [BS3CG1DST_ESP] = */ 4,
352 /* [BS3CG1DST_EBP] = */ 4,
353 /* [BS3CG1DST_ESI] = */ 4,
354 /* [BS3CG1DST_EDI] = */ 4,
355 /* [BS3CG1DST_R8D] = */ 4,
356 /* [BS3CG1DST_R9D] = */ 4,
357 /* [BS3CG1DST_R10D] = */ 4,
358 /* [BS3CG1DST_R11D] = */ 4,
359 /* [BS3CG1DST_R12D] = */ 4,
360 /* [BS3CG1DST_R13D] = */ 4,
361 /* [BS3CG1DST_R14D] = */ 4,
362 /* [BS3CG1DST_R15D] = */ 4,
363
364 /* [BS3CG1DST_RAX] = */ 8,
365 /* [BS3CG1DST_RCX] = */ 8,
366 /* [BS3CG1DST_RDX] = */ 8,
367 /* [BS3CG1DST_RBX] = */ 8,
368 /* [BS3CG1DST_RSP] = */ 8,
369 /* [BS3CG1DST_RBP] = */ 8,
370 /* [BS3CG1DST_RSI] = */ 8,
371 /* [BS3CG1DST_RDI] = */ 8,
372 /* [BS3CG1DST_R8] = */ 8,
373 /* [BS3CG1DST_R9] = */ 8,
374 /* [BS3CG1DST_R10] = */ 8,
375 /* [BS3CG1DST_R11] = */ 8,
376 /* [BS3CG1DST_R12] = */ 8,
377 /* [BS3CG1DST_R13] = */ 8,
378 /* [BS3CG1DST_R14] = */ 8,
379 /* [BS3CG1DST_R15] = */ 8,
380
381 /* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
382 /* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
383 /* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
384 /* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
385 /* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
386 /* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
387 /* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
388 /* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
389 /* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
390 /* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
391 /* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
392 /* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
393 /* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
394 /* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
395 /* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
396 /* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
397
398 /* [BS3CG1DST_FCW] = */ 2,
399 /* [BS3CG1DST_FSW] = */ 2,
400 /* [BS3CG1DST_FTW] = */ 2,
401 /* [BS3CG1DST_FOP] = */ 2,
402 /* [BS3CG1DST_FPUIP] = */ 2,
403 /* [BS3CG1DST_FPUCS] = */ 2,
404 /* [BS3CG1DST_FPUDP] = */ 2,
405 /* [BS3CG1DST_FPUDS] = */ 2,
406 /* [BS3CG1DST_MXCSR] = */ 4,
407 /* [BS3CG1DST_MXCSR_MASK] = */ 4,
408 /* [BS3CG1DST_ST0] = */ 12,
409 /* [BS3CG1DST_ST1] = */ 12,
410 /* [BS3CG1DST_ST2] = */ 12,
411 /* [BS3CG1DST_ST3] = */ 12,
412 /* [BS3CG1DST_ST4] = */ 12,
413 /* [BS3CG1DST_ST5] = */ 12,
414 /* [BS3CG1DST_ST6] = */ 12,
415 /* [BS3CG1DST_ST7] = */ 12,
416 /* [BS3CG1DST_MM0] = */ 8,
417 /* [BS3CG1DST_MM1] = */ 8,
418 /* [BS3CG1DST_MM2] = */ 8,
419 /* [BS3CG1DST_MM3] = */ 8,
420 /* [BS3CG1DST_MM4] = */ 8,
421 /* [BS3CG1DST_MM5] = */ 8,
422 /* [BS3CG1DST_MM6] = */ 8,
423 /* [BS3CG1DST_MM7] = */ 8,
424 /* [BS3CG1DST_XMM0] = */ 16,
425 /* [BS3CG1DST_XMM1] = */ 16,
426 /* [BS3CG1DST_XMM2] = */ 16,
427 /* [BS3CG1DST_XMM3] = */ 16,
428 /* [BS3CG1DST_XMM4] = */ 16,
429 /* [BS3CG1DST_XMM5] = */ 16,
430 /* [BS3CG1DST_XMM6] = */ 16,
431 /* [BS3CG1DST_XMM7] = */ 16,
432 /* [BS3CG1DST_XMM8] = */ 16,
433 /* [BS3CG1DST_XMM9] = */ 16,
434 /* [BS3CG1DST_XMM10] = */ 16,
435 /* [BS3CG1DST_XMM11] = */ 16,
436 /* [BS3CG1DST_XMM12] = */ 16,
437 /* [BS3CG1DST_XMM13] = */ 16,
438 /* [BS3CG1DST_XMM14] = */ 16,
439 /* [BS3CG1DST_XMM15] = */ 16,
440 /* [BS3CG1DST_XMM0_LO] = */ 8,
441 /* [BS3CG1DST_XMM1_LO] = */ 8,
442 /* [BS3CG1DST_XMM2_LO] = */ 8,
443 /* [BS3CG1DST_XMM3_LO] = */ 8,
444 /* [BS3CG1DST_XMM4_LO] = */ 8,
445 /* [BS3CG1DST_XMM5_LO] = */ 8,
446 /* [BS3CG1DST_XMM6_LO] = */ 8,
447 /* [BS3CG1DST_XMM7_LO] = */ 8,
448 /* [BS3CG1DST_XMM8_LO] = */ 8,
449 /* [BS3CG1DST_XMM9_LO] = */ 8,
450 /* [BS3CG1DST_XMM10_LO] = */ 8,
451 /* [BS3CG1DST_XMM11_LO] = */ 8,
452 /* [BS3CG1DST_XMM12_LO] = */ 8,
453 /* [BS3CG1DST_XMM13_LO] = */ 8,
454 /* [BS3CG1DST_XMM14_LO] = */ 8,
455 /* [BS3CG1DST_XMM15_LO] = */ 8,
456 /* [BS3CG1DST_XMM0_HI] = */ 8,
457 /* [BS3CG1DST_XMM1_HI] = */ 8,
458 /* [BS3CG1DST_XMM2_HI] = */ 8,
459 /* [BS3CG1DST_XMM3_HI] = */ 8,
460 /* [BS3CG1DST_XMM4_HI] = */ 8,
461 /* [BS3CG1DST_XMM5_HI] = */ 8,
462 /* [BS3CG1DST_XMM6_HI] = */ 8,
463 /* [BS3CG1DST_XMM7_HI] = */ 8,
464 /* [BS3CG1DST_XMM8_HI] = */ 8,
465 /* [BS3CG1DST_XMM9_HI] = */ 8,
466 /* [BS3CG1DST_XMM10_HI] = */ 8,
467 /* [BS3CG1DST_XMM11_HI] = */ 8,
468 /* [BS3CG1DST_XMM12_HI] = */ 8,
469 /* [BS3CG1DST_XMM13_HI] = */ 8,
470 /* [BS3CG1DST_XMM14_HI] = */ 8,
471 /* [BS3CG1DST_XMM15_HI] = */ 8,
472 /* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
473 /* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
474 /* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
475 /* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
476 /* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
477 /* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
478 /* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
479 /* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
480 /* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
481 /* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
482 /* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
483 /* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
484 /* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
485 /* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
486 /* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
487 /* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
488 /* [BS3CG1DST_XMM0_DW0] = */ 4,
489 /* [BS3CG1DST_XMM1_DW0] = */ 4,
490 /* [BS3CG1DST_XMM2_DW0] = */ 4,
491 /* [BS3CG1DST_XMM3_DW0] = */ 4,
492 /* [BS3CG1DST_XMM4_DW0] = */ 4,
493 /* [BS3CG1DST_XMM5_DW0] = */ 4,
494 /* [BS3CG1DST_XMM6_DW0] = */ 4,
495 /* [BS3CG1DST_XMM7_DW0] = */ 4,
496 /* [BS3CG1DST_XMM8_DW0] = */ 4,
497 /* [BS3CG1DST_XMM9_DW0] = */ 4,
498 /* [BS3CG1DST_XMM10_DW0] = */ 4,
499 /* [BS3CG1DST_XMM11_DW0] = */ 4,
500 /* [BS3CG1DST_XMM12_DW0] = */ 4,
501 /* [BS3CG1DST_XMM13_DW0] = */ 4,
502 /* [BS3CG1DST_XMM14_DW0] = */ 4,
503 /* [BS3CG1DST_XMM15_DW0] = */ 4,
504 /* [BS3CG1DST_YMM0] = */ 32,
505 /* [BS3CG1DST_YMM1] = */ 32,
506 /* [BS3CG1DST_YMM2] = */ 32,
507 /* [BS3CG1DST_YMM3] = */ 32,
508 /* [BS3CG1DST_YMM4] = */ 32,
509 /* [BS3CG1DST_YMM5] = */ 32,
510 /* [BS3CG1DST_YMM6] = */ 32,
511 /* [BS3CG1DST_YMM7] = */ 32,
512 /* [BS3CG1DST_YMM8] = */ 32,
513 /* [BS3CG1DST_YMM9] = */ 32,
514 /* [BS3CG1DST_YMM10] = */ 32,
515 /* [BS3CG1DST_YMM11] = */ 32,
516 /* [BS3CG1DST_YMM12] = */ 32,
517 /* [BS3CG1DST_YMM13] = */ 32,
518 /* [BS3CG1DST_YMM14] = */ 32,
519 /* [BS3CG1DST_YMM15] = */ 32,
520
521 /* [BS3CG1DST_VALUE_XCPT] = */ 1,
522};
523AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
524
525/** Destination field offset indexed by bBS3CG1DST.
526 * Zero means operand size sized. */
527static const unsigned g_aoffBs3Cg1DstFields[] =
528{
529 /* [BS3CG1DST_INVALID] = */ ~0U,
530 /* [BS3CG1DST_OP1] = */ ~0U,
531 /* [BS3CG1DST_OP2] = */ ~0U,
532 /* [BS3CG1DST_OP3] = */ ~0U,
533 /* [BS3CG1DST_OP4] = */ ~0U,
534 /* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
535 /* [BS3CG1DST_EFL_UNDEF]=*/ ~0, /* special field */
536
537 /* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
538 /* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
539 /* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
540 /* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
541 /* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
542 /* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
543 /* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
544 /* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
545 /* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
546 /* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
547 /* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
548 /* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
549 /* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
550 /* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
551 /* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
552 /* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
553 /* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
554 /* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
555 /* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
556 /* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
557
558 /* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
559 /* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
560 /* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
561 /* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
562 /* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
563 /* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
564 /* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
565 /* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
566 /* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
567 /* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
568 /* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
569 /* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
570 /* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
571 /* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
572 /* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
573 /* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
574
575 /* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
576 /* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
577 /* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
578 /* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
579 /* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
580 /* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
581 /* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
582 /* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
583 /* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
584 /* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
585 /* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
586 /* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
587 /* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
588 /* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
589 /* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
590 /* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
591
592 /* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
593 /* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
594 /* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
595 /* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
596 /* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
597 /* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
598 /* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
599 /* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
600 /* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
601 /* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
602 /* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
603 /* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
604 /* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
605 /* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
606 /* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
607 /* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
608
609 /* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
610 /* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
611 /* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
612 /* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
613 /* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
614 /* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
615 /* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
616 /* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
617 /* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
618 /* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
619 /* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
620 /* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
621 /* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
622 /* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
623 /* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
624 /* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
625
626 /* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
627 /* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
628 /* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
629 /* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
630 /* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
631 /* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
632 /* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
633 /* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
634 /* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
635 /* [BS3CG1DST_MXCSR_MASK] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR_MASK),
636 /* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
637 /* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
638 /* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
639 /* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
640 /* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
641 /* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
642 /* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
643 /* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
644 /* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
645 /* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
646 /* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
647 /* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
648 /* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
649 /* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
650 /* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
651 /* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
652
653 /* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
654 /* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
655 /* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
656 /* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
657 /* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
658 /* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
659 /* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
660 /* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
661 /* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
662 /* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
663 /* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
664 /* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
665 /* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
666 /* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
667 /* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
668 /* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
669 /* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
670 /* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
671 /* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
672 /* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
673 /* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
674 /* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
675 /* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
676 /* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
677 /* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
678 /* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
679 /* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
680 /* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
681 /* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
682 /* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
683 /* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
684 /* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
685 /* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
686 /* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
687 /* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
688 /* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
689 /* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
690 /* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
691 /* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
692 /* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
693 /* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
694 /* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
695 /* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
696 /* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
697 /* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
698 /* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
699 /* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
700 /* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
701 /* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
702 /* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
703 /* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
704 /* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
705 /* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
706 /* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
707 /* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
708 /* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
709 /* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
710 /* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
711 /* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
712 /* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
713 /* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
714 /* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
715 /* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
716 /* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
717 /* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
718 /* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
719 /* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
720 /* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
721 /* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
722 /* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
723 /* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
724 /* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
725 /* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
726 /* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
727 /* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
728 /* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
729 /* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
730 /* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
731 /* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
732 /* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
733
734 /* [BS3CG1DST_YMM0] = */ ~0U,
735 /* [BS3CG1DST_YMM1] = */ ~0U,
736 /* [BS3CG1DST_YMM2] = */ ~0U,
737 /* [BS3CG1DST_YMM3] = */ ~0U,
738 /* [BS3CG1DST_YMM4] = */ ~0U,
739 /* [BS3CG1DST_YMM5] = */ ~0U,
740 /* [BS3CG1DST_YMM6] = */ ~0U,
741 /* [BS3CG1DST_YMM7] = */ ~0U,
742 /* [BS3CG1DST_YMM8] = */ ~0U,
743 /* [BS3CG1DST_YMM9] = */ ~0U,
744 /* [BS3CG1DST_YMM10] = */ ~0U,
745 /* [BS3CG1DST_YMM11] = */ ~0U,
746 /* [BS3CG1DST_YMM12] = */ ~0U,
747 /* [BS3CG1DST_YMM13] = */ ~0U,
748 /* [BS3CG1DST_YMM14] = */ ~0U,
749 /* [BS3CG1DST_YMM15] = */ ~0U,
750
751 /* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
752};
753AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
754
755#ifdef BS3CG1_DEBUG_CTX_MOD
756/** Destination field names. */
757static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
758{
759 { "INVALID" },
760 { "OP1" },
761 { "OP2" },
762 { "OP3" },
763 { "OP4" },
764 { "EFL" },
765 { "EFL_UND" },
766
767 { "AL" },
768 { "CL" },
769 { "DL" },
770 { "BL" },
771 { "AH" },
772 { "CH" },
773 { "DH" },
774 { "BH" },
775 { "SPL" },
776 { "BPL" },
777 { "SIL" },
778 { "DIL" },
779 { "R8L" },
780 { "R9L" },
781 { "R10L" },
782 { "R11L" },
783 { "R12L" },
784 { "R13L" },
785 { "R14L" },
786 { "R15L" },
787
788 { "AX" },
789 { "CX" },
790 { "DX" },
791 { "BX" },
792 { "SP" },
793 { "BP" },
794 { "SI" },
795 { "DI" },
796 { "R8W" },
797 { "R9W" },
798 { "R10W" },
799 { "R11W" },
800 { "R12W" },
801 { "R13W" },
802 { "R14W" },
803 { "R15W" },
804
805 { "EAX" },
806 { "ECX" },
807 { "EDX" },
808 { "EBX" },
809 { "ESP" },
810 { "EBP" },
811 { "ESI" },
812 { "EDI" },
813 { "R8D" },
814 { "R9D" },
815 { "R10D" },
816 { "R11D" },
817 { "R12D" },
818 { "R13D" },
819 { "R14D" },
820 { "R15D" },
821
822 { "RAX" },
823 { "RCX" },
824 { "RDX" },
825 { "RBX" },
826 { "RSP" },
827 { "RBP" },
828 { "RSI" },
829 { "RDI" },
830 { "R8" },
831 { "R9" },
832 { "R10" },
833 { "R11" },
834 { "R12" },
835 { "R13" },
836 { "R14" },
837 { "R15" },
838
839 { "OZ_RAX" },
840 { "OZ_RCX" },
841 { "OZ_RDX" },
842 { "OZ_RBX" },
843 { "OZ_RSP" },
844 { "OZ_RBP" },
845 { "OZ_RSI" },
846 { "OZ_RDI" },
847 { "OZ_R8" },
848 { "OZ_R9" },
849 { "OZ_R10" },
850 { "OZ_R11" },
851 { "OZ_R12" },
852 { "OZ_R13" },
853 { "OZ_R14" },
854 { "OZ_R15" },
855
856 { "FCW" },
857 { "FSW" },
858 { "FTW" },
859 { "FOP" },
860 { "FPUIP" },
861 { "FPUCS" },
862 { "FPUDP" },
863 { "FPUDS" },
864 { "MXCSR" },
865 { "MXCSR_M" },
866 { "ST0" },
867 { "ST1" },
868 { "ST2" },
869 { "ST3" },
870 { "ST4" },
871 { "ST5" },
872 { "ST6" },
873 { "ST7" },
874 { "MM0" },
875 { "MM1" },
876 { "MM2" },
877 { "MM3" },
878 { "MM4" },
879 { "MM5" },
880 { "MM6" },
881 { "MM7" },
882 { "XMM0" },
883 { "XMM1" },
884 { "XMM2" },
885 { "XMM3" },
886 { "XMM4" },
887 { "XMM5" },
888 { "XMM6" },
889 { "XMM7" },
890 { "XMM8" },
891 { "XMM9" },
892 { "XMM10" },
893 { "XMM11" },
894 { "XMM12" },
895 { "XMM13" },
896 { "XMM14" },
897 { "XMM15" },
898 { "XMM0_LO" },
899 { "XMM1_LO" },
900 { "XMM2_LO" },
901 { "XMM3_LO" },
902 { "XMM4_LO" },
903 { "XMM5_LO" },
904 { "XMM6_LO" },
905 { "XMM7_LO" },
906 { "XMM8_LO" },
907 { "XMM9_LO" },
908 { "XMM10_LO" },
909 { "XMM11_LO" },
910 { "XMM12_LO" },
911 { "XMM13_LO" },
912 { "XMM14_LO" },
913 { "XMM15_LO" },
914 { "XMM0_HI" },
915 { "XMM1_HI" },
916 { "XMM2_HI" },
917 { "XMM3_HI" },
918 { "XMM4_HI" },
919 { "XMM5_HI" },
920 { "XMM6_HI" },
921 { "XMM7_HI" },
922 { "XMM8_HI" },
923 { "XMM9_HI" },
924 { "XMM10_HI" },
925 { "XMM11_HI" },
926 { "XMM12_HI" },
927 { "XMM13_HI" },
928 { "XMM14_HI" },
929 { "XMM15_HI" },
930 { "XMM0_LO_ZX" },
931 { "XMM1_LO_ZX" },
932 { "XMM2_LO_ZX" },
933 { "XMM3_LO_ZX" },
934 { "XMM4_LO_ZX" },
935 { "XMM5_LO_ZX" },
936 { "XMM6_LO_ZX" },
937 { "XMM7_LO_ZX" },
938 { "XMM8_LO_ZX" },
939 { "XMM9_LO_ZX" },
940 { "XMM10_LO_ZX" },
941 { "XMM11_LO_ZX" },
942 { "XMM12_LO_ZX" },
943 { "XMM13_LO_ZX" },
944 { "XMM14_LO_ZX" },
945 { "XMM15_LO_ZX" },
946 { "XMM0_DW0" },
947 { "XMM1_DW0" },
948 { "XMM2_DW0" },
949 { "XMM3_DW0" },
950 { "XMM4_DW0" },
951 { "XMM5_DW0" },
952 { "XMM6_DW0" },
953 { "XMM7_DW0" },
954 { "XMM8_DW0" },
955 { "XMM9_DW0" },
956 { "XMM10_DW0" },
957 { "XMM11_DW0" },
958 { "XMM12_DW0" },
959 { "XMM13_DW0" },
960 { "XMM14_DW0" },
961 { "XMM15_DW0" },
962 { "YMM0" },
963 { "YMM1" },
964 { "YMM2" },
965 { "YMM3" },
966 { "YMM4" },
967 { "YMM5" },
968 { "YMM6" },
969 { "YMM7" },
970 { "YMM8" },
971 { "YMM9" },
972 { "YMM10" },
973 { "YMM11" },
974 { "YMM12" },
975 { "YMM13" },
976 { "YMM14" },
977 { "YMM15" },
978
979 { "VALXCPT" },
980};
981AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
982
983#endif
984
985#if 0
986static const struct
987{
988 uint8_t cbPrefixes;
989 uint8_t abPrefixes[14];
990 uint16_t fEffective;
991} g_aPrefixVariations[] =
992{
993 { 0, { 0x00 }, BS3CG1_PF_NONE },
994
995 { 1, { P_OZ }, BS3CG1_PF_OZ },
996 { 1, { P_CS }, BS3CG1_PF_CS },
997 { 1, { P_DS }, BS3CG1_PF_DS },
998 { 1, { P_ES }, BS3CG1_PF_ES },
999 { 1, { P_FS }, BS3CG1_PF_FS },
1000 { 1, { P_GS }, BS3CG1_PF_GS },
1001 { 1, { P_SS }, BS3CG1_PF_SS },
1002 { 1, { P_LK }, BS3CG1_PF_LK },
1003
1004 { 2, { P_CS, P_OZ, }, BS3CG1_PF_CS | BS3CFG1_PF_OZ },
1005 { 2, { P_DS, P_OZ, }, BS3CG1_PF_DS | BS3CFG1_PF_OZ },
1006 { 2, { P_ES, P_OZ, }, BS3CG1_PF_ES | BS3CFG1_PF_OZ },
1007 { 2, { P_FS, P_OZ, }, BS3CG1_PF_FS | BS3CFG1_PF_OZ },
1008 { 2, { P_GS, P_OZ, }, BS3CG1_PF_GS | BS3CFG1_PF_OZ },
1009 { 2, { P_GS, P_OZ, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1010 { 2, { P_SS, P_OZ, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1011
1012 { 2, { P_OZ, P_CS, }, BS3CG1_PF_CS | BS3CFG1_PF_OZ },
1013 { 2, { P_OZ, P_DS, }, BS3CG1_PF_DS | BS3CFG1_PF_OZ },
1014 { 2, { P_OZ, P_ES, }, BS3CG1_PF_ES | BS3CFG1_PF_OZ },
1015 { 2, { P_OZ, P_FS, }, BS3CG1_PF_FS | BS3CFG1_PF_OZ },
1016 { 2, { P_OZ, P_GS, }, BS3CG1_PF_GS | BS3CFG1_PF_OZ },
1017 { 2, { P_OZ, P_GS, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1018 { 2, { P_OZ, P_SS, }, BS3CG1_PF_SS | BS3CFG1_PF_OZ },
1019};
1020
1021static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1022{
1023 /* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1024 /* [BS3CG1PFXKIND_MODRM] = */ 0,
1025 /* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ | BS3CG1_PF_W,
1026};
1027
1028#endif
1029
1030
1031/**
1032 * Checks if >= 16 byte SSE/AVX alignment are exempted for the exception type.
1033 *
1034 * @returns true / false.
1035 * @param enmXcptType The type to check.
1036 */
1037static bool Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1038{
1039 switch (enmXcptType)
1040 {
1041 case BS3CG1XCPTTYPE_4UA:
1042 case BS3CG1XCPTTYPE_5:
1043 return true;
1044 default:
1045 return false;
1046 }
1047}
1048
1049
1050DECLINLINE(unsigned) Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1051{
1052 switch (pThis->enmPrefixKind)
1053 {
1054 case BS3CG1PFXKIND_REQ_66:
1055 pThis->abCurInstr[offDst] = 0x66;
1056 break;
1057 case BS3CG1PFXKIND_REQ_F2:
1058 pThis->abCurInstr[offDst] = 0xf2;
1059 break;
1060 case BS3CG1PFXKIND_REQ_F3:
1061 pThis->abCurInstr[offDst] = 0xf3;
1062 break;
1063 default:
1064 return offDst;
1065 }
1066 return offDst + 1;
1067}
1068
1069
1070DECLINLINE(unsigned) Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1071{
1072 switch (pThis->cbOpcodes)
1073 {
1074 case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1075 case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1076 case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1077 case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1078 return offDst + pThis->cbOpcodes;
1079
1080 default:
1081 BS3_ASSERT(0);
1082 return 0;
1083 }
1084}
1085
1086
1087/**
1088 * Cleans up state and context changes made by the encoder.
1089 *
1090 * @param pThis The state.
1091 */
1092static void Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1093{
1094 /* Restore the DS registers in the contexts. */
1095 unsigned iRing = 4;
1096 while (iRing-- > 0)
1097 pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1098
1099 switch (pThis->enmEncoding)
1100 {
1101 /* Most encodings currently doesn't need any special cleaning up. */
1102 default:
1103 return;
1104 }
1105}
1106
1107
1108static unsigned Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1109 uint8_t cbOp, uint8_t cbMissalign, BS3CG1OPLOC enmLocation)
1110{
1111 pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1112 pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1113 pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1114 pThis->aOperands[pThis->iRmOp].off = cbOp + cbMissalign;
1115
1116 if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1117 || (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1118 {
1119 /*
1120 * 16-bit code doing 16-bit or 32-bit addressing,
1121 * or 32-bit code doing 16-bit addressing.
1122 */
1123 unsigned iRing = 4;
1124 if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1125 while (iRing-- > 0)
1126 pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1127 else
1128 while (iRing-- > 0)
1129 pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel | iRing;
1130 if (!fAddrOverride || BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1131 {
1132 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /*disp16*/);
1133 *(uint16_t *)&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1134 off += 2;
1135 }
1136 else
1137 {
1138 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /*disp32*/);
1139 *(uint32_t *)&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1140 off += 4;
1141 }
1142 }
1143 else
1144 {
1145 /*
1146 * 32-bit code doing 32-bit addressing,
1147 * or 64-bit code doing either 64-bit or 32-bit addressing.
1148 */
1149 pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /*disp32*/);
1150 *(uint32_t *)&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMissalign;
1151
1152 /* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1153 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1154 *(uint32_t *)&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1155 off += 4;
1156 }
1157
1158 /*
1159 * Fill the memory with 0xcc.
1160 */
1161 switch (cbOp + cbMissalign)
1162 {
1163 case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; /* fall thru */
1164 case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; /* fall thru */
1165 case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; /* fall thru */
1166 case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; /* fall thru */
1167 case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; /* fall thru */
1168 case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; /* fall thru */
1169 case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; /* fall thru */
1170 case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; /* fall thru */
1171 case 0: break;
1172 default:
1173 Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign);
1174 break;
1175 }
1176
1177 return off;
1178}
1179
1180
1181/**
1182 * Encodes the next instruction.
1183 *
1184 * @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
1185 * that there are no more encodings to test.
1186 * @param pThis The state.
1187 * @param iEncoding The encoding to produce. Meaning is specific to each
1188 * BS3CG1ENC_XXX value and should be considered internal.
1189 */
1190static unsigned Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
1191{
1192 unsigned off;
1193 unsigned cbOp;
1194
1195 pThis->bAlignmentXcpt = UINT8_MAX;
1196
1197 switch (pThis->enmEncoding)
1198 {
1199 case BS3CG1ENC_MODRM_Eb_Gb:
1200 /* Start by reg,reg encoding. */
1201 if (iEncoding == 0)
1202 {
1203 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1204 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1205 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1206 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1207 }
1208 else if (iEncoding == 1)
1209 {
1210 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1211 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1212 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM_RW);
1213 }
1214 else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1215 {
1216 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1217 pThis->abCurInstr[0] = P_AZ;
1218 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1219 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM_RW);
1220 }
1221 else
1222 break;
1223 pThis->cbCurInstr = off;
1224 iEncoding++;
1225 break;
1226
1227 case BS3CG1ENC_MODRM_Gb_Eb:
1228 /* Start by reg,reg encoding. */
1229 if (iEncoding == 0)
1230 {
1231 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1232 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1233 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1234 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1235 }
1236 else if (iEncoding == 1)
1237 {
1238 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1239 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1240 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM);
1241 }
1242 else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1243 {
1244 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1245 pThis->abCurInstr[0] = P_AZ;
1246 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1247 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM);
1248 }
1249 else
1250 break;
1251 pThis->cbCurInstr = off;
1252 iEncoding++;
1253 break;
1254
1255 case BS3CG1ENC_MODRM_Gv_Ev:
1256 case BS3CG1ENC_MODRM_Ev_Gv:
1257 if (iEncoding == 0)
1258 {
1259 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1260 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1261 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1262 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1263 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1264 }
1265 else if (iEncoding == 1)
1266 {
1267 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1268 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1269 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1270 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp, 0,
1271 pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1272 }
1273 else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1274 {
1275 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1276 pThis->abCurInstr[0] = P_OZ;
1277 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1278 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1279 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1280 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1281 pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1282 }
1283 else if (iEncoding == 3)
1284 {
1285 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1286 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1287 pThis->abCurInstr[0] = P_OZ;
1288 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1289 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xSI, cbOp, 0,
1290 pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1291 }
1292 else if (iEncoding == 4)
1293 {
1294 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1295 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RDI;
1296 pThis->abCurInstr[0] = P_AZ;
1297 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1298 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, cbOp, 0,
1299 pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1300 }
1301 else if (iEncoding == 5)
1302 {
1303 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1304 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1305 pThis->abCurInstr[0] = P_OZ;
1306 pThis->abCurInstr[1] = P_AZ;
1307 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1308 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xSI, cbOp, 0,
1309 pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1310 }
1311 else if (iEncoding == 6 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1312 {
1313 cbOp = 8;
1314 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1315 pThis->abCurInstr[off++] = REX_W___;
1316 off = Bs3Cg1InsertOpcodes(pThis, off);
1317 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1318 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_RBX;
1319 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_RDX;
1320 pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1321 }
1322 else
1323 break;
1324 pThis->aOperands[0].cbOp = cbOp;
1325 pThis->aOperands[1].cbOp = cbOp;
1326 pThis->cbOperand = cbOp;
1327 pThis->cbCurInstr = off;
1328 iEncoding++;
1329 break;
1330
1331 case BS3CG1ENC_MODRM_Wss_Vss:
1332 if (iEncoding == 0)
1333 {
1334 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1335 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1336 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_DW0;
1337 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0;
1338 }
1339 else if (iEncoding == 1)
1340 {
1341 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0;
1342 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1343 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 4, 0, BS3CG1OPLOC_MEM_RW);
1344 }
1345 else if (iEncoding == 2)
1346 {
1347 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0;
1348 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1349 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 4, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW);
1350 }
1351 else
1352 break;
1353 pThis->cbCurInstr = off;
1354 iEncoding++;
1355 break;
1356
1357 case BS3CG1ENC_MODRM_Wsd_Vsd:
1358 if (iEncoding == 0)
1359 {
1360 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1361 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1362 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1363 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1364 }
1365 else if (iEncoding == 1)
1366 {
1367 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1368 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1369 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_RW);
1370 }
1371 else if (iEncoding == 2)
1372 {
1373 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1374 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1375 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW);
1376 }
1377 else
1378 break;
1379 pThis->cbCurInstr = off;
1380 iEncoding++;
1381 break;
1382
1383 case BS3CG1ENC_MODRM_Wps_Vps:
1384 case BS3CG1ENC_MODRM_Wpd_Vpd:
1385 if (iEncoding == 0)
1386 {
1387 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1388 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1389 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1390 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1391 }
1392 else if (iEncoding == 1)
1393 {
1394 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1395 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1396 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 16, 0, BS3CG1OPLOC_MEM_RW);
1397 }
1398 else if (iEncoding == 2)
1399 {
1400 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1401 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1402 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW);
1403 if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1404 pThis->bAlignmentXcpt = X86_XCPT_GP;
1405 }
1406 else
1407 break;
1408 pThis->cbCurInstr = off;
1409 iEncoding++;
1410 break;
1411
1412 case BS3CG1ENC_MODRM_WqZxReg_Vq:
1413 if (iEncoding == 0)
1414 {
1415 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1416 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1417 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO_ZX;
1418 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1419 }
1420 else if (iEncoding == 1)
1421 {
1422 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1423 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1424 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM_RW);
1425 }
1426 else if (iEncoding == 2)
1427 {
1428 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1429 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1430 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM_RW);
1431 }
1432 else
1433 break;
1434 pThis->cbCurInstr = off;
1435 iEncoding++;
1436 break;
1437
1438 case BS3CG1ENC_MODRM_Vq_UqHi:
1439 if (iEncoding == 0)
1440 {
1441 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1442 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1443 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_HI;
1444 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1445 }
1446 else if (iEncoding == 1)
1447 {
1448 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1449 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 2);
1450 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM2_HI;
1451 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1452 }
1453 else
1454 break;
1455 pThis->cbCurInstr = off;
1456 iEncoding++;
1457 break;
1458
1459 case BS3CG1ENC_MODRM_Vq_Mq:
1460 if (iEncoding == 0)
1461 {
1462 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1463 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1464 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 8, 0, BS3CG1OPLOC_MEM);
1465 }
1466 else if (iEncoding == 1)
1467 {
1468 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1469 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1470 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 8, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
1471 }
1472 else
1473 break;
1474 pThis->cbCurInstr = off;
1475 iEncoding++;
1476 break;
1477
1478 case BS3CG1ENC_MODRM_Vdq_Wdq:
1479 if (iEncoding == 0)
1480 {
1481 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1482 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1483 pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1484 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1485 }
1486 else if (iEncoding == 1)
1487 {
1488 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1489 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1490 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /*iReg*/, 16, 0, BS3CG1OPLOC_MEM);
1491 }
1492 else if (iEncoding == 2)
1493 {
1494 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1495 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1496 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /*iReg*/, 16, 1 /*cbMissalign*/, BS3CG1OPLOC_MEM);
1497 if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1498 pThis->bAlignmentXcpt = X86_XCPT_GP;
1499 }
1500 else
1501 break;
1502 pThis->cbCurInstr = off;
1503 iEncoding++;
1504 break;
1505
1506 case BS3CG1ENC_MODRM_Gv_Ma:
1507 cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1508 if (iEncoding == 0)
1509 {
1510 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1511 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1512 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1513 }
1514 else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1515 {
1516 cbOp = cbOp == 2 ? 4 : 2;
1517 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1518 pThis->abCurInstr[0] = P_OZ;
1519 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1520 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1521 }
1522 else if (iEncoding == 2)
1523 {
1524 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1525 pThis->abCurInstr[0] = P_AZ;
1526 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1527 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1528 }
1529 else if (iEncoding == 3)
1530 {
1531 cbOp = cbOp == 2 ? 4 : 2;
1532 pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1533 pThis->abCurInstr[0] = P_AZ;
1534 pThis->abCurInstr[1] = P_OZ;
1535 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1536 off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1537 }
1538 else
1539 break;
1540 pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
1541 pThis->cbOperand = cbOp;
1542 pThis->cbCurInstr = off;
1543 iEncoding++;
1544 break;
1545
1546 case BS3CG1ENC_MODRM_MbRO:
1547 if (iEncoding == 0)
1548 {
1549 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1550 off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1551 (pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1552 1, 0, BS3CG1OPLOC_MEM);
1553 }
1554 else
1555 break;
1556 pThis->cbCurInstr = off;
1557 iEncoding++;
1558 break;
1559
1560
1561 case BS3CG1ENC_FIXED:
1562 if (iEncoding == 0)
1563 {
1564 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1565 pThis->cbCurInstr = off;
1566 iEncoding++;
1567 }
1568 break;
1569
1570 case BS3CG1ENC_FIXED_AL_Ib:
1571 if (iEncoding == 0)
1572 {
1573 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1574 pThis->aOperands[1].off = (uint8_t)off;
1575 pThis->abCurInstr[off++] = 0xff;
1576 pThis->cbCurInstr = off;
1577 iEncoding++;
1578 }
1579 break;
1580
1581 case BS3CG1ENC_FIXED_rAX_Iz:
1582 if (iEncoding == 0)
1583 {
1584 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1585 pThis->aOperands[1].off = (uint8_t)off;
1586 if (BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1587 {
1588 *(uint16_t *)&pThis->abCurInstr[off] = UINT16_MAX;
1589 off += 2;
1590 pThis->aOperands[0].cbOp = 2;
1591 pThis->aOperands[1].cbOp = 2;
1592 pThis->cbOperand = 2;
1593 }
1594 else
1595 {
1596 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
1597 off += 4;
1598 pThis->aOperands[0].cbOp = 4;
1599 pThis->aOperands[1].cbOp = 4;
1600 pThis->cbOperand = 4;
1601 }
1602 }
1603 else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1604 {
1605 pThis->abCurInstr[0] = P_OZ;
1606 off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1607 pThis->aOperands[1].off = (uint8_t)off;
1608 if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1609 {
1610 *(uint16_t *)&pThis->abCurInstr[off] = UINT16_MAX;
1611 off += 2;
1612 pThis->aOperands[0].cbOp = 2;
1613 pThis->aOperands[1].cbOp = 2;
1614 pThis->cbOperand = 2;
1615 }
1616 else
1617 {
1618 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
1619 off += 4;
1620 pThis->aOperands[0].cbOp = 4;
1621 pThis->aOperands[1].cbOp = 4;
1622 pThis->cbOperand = 4;
1623 }
1624 }
1625 else if (iEncoding == 2 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1626 {
1627 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1628 pThis->abCurInstr[off++] = REX_W___;
1629 off = Bs3Cg1InsertOpcodes(pThis, off);
1630 pThis->aOperands[1].off = (uint8_t)off;
1631 *(uint32_t *)&pThis->abCurInstr[off] = UINT32_MAX;
1632 off += 4;
1633 pThis->aOperands[0].cbOp = 8;
1634 pThis->aOperands[1].cbOp = 4;
1635 pThis->cbOperand = 8;
1636 }
1637 else
1638 break;
1639 pThis->cbCurInstr = off;
1640 iEncoding++;
1641 break;
1642
1643 case BS3CG1ENC_MODRM_MOD_EQ_3:
1644 if (iEncoding < 8)
1645 {
1646 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1647 off = Bs3Cg1InsertOpcodes(pThis, off);
1648 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
1649 }
1650 else if (iEncoding < 16)
1651 {
1652 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1653 off = Bs3Cg1InsertOpcodes(pThis, off);
1654 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding);
1655 }
1656 else
1657 break;
1658 pThis->cbCurInstr = off;
1659 iEncoding++;
1660 break;
1661
1662 case BS3CG1ENC_MODRM_MOD_NE_3:
1663 if (iEncoding < 3)
1664 {
1665 off = Bs3Cg1InsertReqPrefix(pThis, 0);
1666 off = Bs3Cg1InsertOpcodes(pThis, off);
1667 pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
1668 if (iEncoding >= 1)
1669 pThis->abCurInstr[off++] = 0x7f;
1670 if (iEncoding == 2)
1671 {
1672 pThis->abCurInstr[off++] = 0x5f;
1673 if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1674 {
1675 pThis->abCurInstr[off++] = 0x3f;
1676 pThis->abCurInstr[off++] = 0x1f;
1677 }
1678 }
1679 }
1680 else
1681 break;
1682 pThis->cbCurInstr = off;
1683 iEncoding++;
1684 break;
1685
1686 default:
1687 Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
1688 break;
1689 }
1690
1691
1692 return iEncoding;
1693}
1694
1695
1696/**
1697 * Prepares doing instruction encodings.
1698 *
1699 * This is in part specific to how the instruction is encoded, but generally it
1700 * sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
1701 * is called from within the loop.
1702 *
1703 * @returns Success indicator (true/false).
1704 * @param pThis The state.
1705 */
1706static bool Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
1707{
1708 unsigned iRing = 4;
1709 while (iRing-- > 0)
1710 pThis->aSavedSegRegs[iRing].ds = pThis->aInitialCtxs[iRing].ds;
1711
1712 pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
1713 pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
1714 pThis->fSameRingNotOkay = false;
1715 pThis->cbOperand = 0;
1716
1717 switch (pThis->enmEncoding)
1718 {
1719 case BS3CG1ENC_MODRM_Eb_Gb:
1720 pThis->iRmOp = 0;
1721 pThis->iRegOp = 1;
1722 pThis->aOperands[0].cbOp = 1;
1723 pThis->aOperands[1].cbOp = 1;
1724 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1725 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1726 break;
1727
1728 case BS3CG1ENC_MODRM_Ev_Gv:
1729 pThis->iRmOp = 0;
1730 pThis->iRegOp = 1;
1731 pThis->cbOperand = 2;
1732 pThis->aOperands[0].cbOp = 2;
1733 pThis->aOperands[1].cbOp = 2;
1734 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1735 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1736 break;
1737
1738 case BS3CG1ENC_MODRM_Gb_Eb:
1739 pThis->iRmOp = 1;
1740 pThis->iRegOp = 0;
1741 pThis->aOperands[0].cbOp = 1;
1742 pThis->aOperands[1].cbOp = 1;
1743 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1744 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1745 break;
1746
1747 case BS3CG1ENC_MODRM_Gv_Ev:
1748 pThis->iRmOp = 1;
1749 pThis->iRegOp = 0;
1750 pThis->cbOperand = 2;
1751 pThis->aOperands[0].cbOp = 2;
1752 pThis->aOperands[1].cbOp = 2;
1753 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1754 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1755 break;
1756
1757 case BS3CG1ENC_MODRM_Gv_Ma:
1758 pThis->iRmOp = 1;
1759 pThis->iRegOp = 0;
1760 pThis->cbOperand = 2;
1761 pThis->aOperands[0].cbOp = 2;
1762 pThis->aOperands[1].cbOp = 4;
1763 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1764 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
1765 pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1766 break;
1767
1768 case BS3CG1ENC_MODRM_Wss_Vss:
1769 pThis->iRmOp = 0;
1770 pThis->iRegOp = 1;
1771 pThis->aOperands[0].cbOp = 4;
1772 pThis->aOperands[1].cbOp = 4;
1773 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1774 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1775 break;
1776
1777 case BS3CG1ENC_MODRM_Wsd_Vsd:
1778 case BS3CG1ENC_MODRM_WqZxReg_Vq:
1779 pThis->iRmOp = 0;
1780 pThis->iRegOp = 1;
1781 pThis->aOperands[0].cbOp = 8;
1782 pThis->aOperands[1].cbOp = 8;
1783 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1784 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1785 break;
1786
1787 case BS3CG1ENC_MODRM_Wps_Vps:
1788 case BS3CG1ENC_MODRM_Wpd_Vpd:
1789 pThis->iRmOp = 0;
1790 pThis->iRegOp = 1;
1791 pThis->aOperands[0].cbOp = 16;
1792 pThis->aOperands[1].cbOp = 16;
1793 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1794 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1795 break;
1796
1797 case BS3CG1ENC_MODRM_Vdq_Wdq:
1798 pThis->iRmOp = 1;
1799 pThis->iRegOp = 0;
1800 pThis->aOperands[0].cbOp = 16;
1801 pThis->aOperands[1].cbOp = 16;
1802 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1803 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1804 break;
1805
1806 case BS3CG1ENC_MODRM_Vq_UqHi:
1807 pThis->iRmOp = 1;
1808 pThis->iRegOp = 0;
1809 pThis->aOperands[0].cbOp = 8;
1810 pThis->aOperands[1].cbOp = 8;
1811 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1812 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1813 break;
1814
1815 case BS3CG1ENC_MODRM_Vq_Mq:
1816 pThis->iRmOp = 1;
1817 pThis->iRegOp = 0;
1818 pThis->aOperands[0].cbOp = 8;
1819 pThis->aOperands[1].cbOp = 8;
1820 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1821 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
1822 break;
1823
1824 case BS3CG1ENC_MODRM_MbRO:
1825 pThis->iRmOp = 0;
1826 pThis->aOperands[0].cbOp = 1;
1827 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
1828 break;
1829
1830 case BS3CG1ENC_FIXED:
1831 /* nothing to do here */
1832 break;
1833
1834 case BS3CG1ENC_FIXED_AL_Ib:
1835 pThis->aOperands[0].cbOp = 1;
1836 pThis->aOperands[1].cbOp = 1;
1837 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1838 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
1839 pThis->aOperands[0].idxField = BS3CG1DST_AL;
1840 pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1841 break;
1842
1843 case BS3CG1ENC_FIXED_rAX_Iz:
1844 pThis->aOperands[0].cbOp = 2;
1845 pThis->aOperands[1].cbOp = 2;
1846 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1847 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
1848 pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
1849 pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1850 break;
1851
1852 case BS3CG1ENC_MODRM_MOD_EQ_3:
1853 case BS3CG1ENC_MODRM_MOD_NE_3:
1854 /* Unused or invalid instructions mostly. */
1855 break;
1856
1857 default:
1858 return Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
1859 pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
1860 }
1861 return true;
1862}
1863
1864
1865/**
1866 * Sets up SSE and maybe AVX.
1867 *
1868 * @returns true (if successful, false if not and the SSE instructions ends up
1869 * being invalid).
1870 * @param pThis The state.
1871 */
1872static bool Bs3Cg3SetupSseAndAvx(PBS3CG1STATE pThis)
1873{
1874 if (!pThis->fWorkExtCtx)
1875 {
1876 unsigned i;
1877 uint32_t cr0 = ASMGetCR0();
1878 uint32_t cr4 = ASMGetCR4();
1879
1880 cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM);
1881 cr0 |= X86_CR0_NE;
1882 ASMSetCR0(cr0);
1883 if (pThis->pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
1884 {
1885 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE;
1886 ASMSetCR4(cr4);
1887 ASMSetXcr0(pThis->pExtCtx->fXcr0);
1888 }
1889 else
1890 {
1891 cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT;
1892 ASMSetCR4(cr4);
1893 }
1894
1895 for (i = 0; i < RT_ELEMENTS(pThis->aInitialCtxs); i++)
1896 {
1897 pThis->aInitialCtxs[i].cr0.u32 = cr0;
1898 pThis->aInitialCtxs[i].cr4.u32 = cr4;
1899 }
1900 pThis->fWorkExtCtx = true;
1901 }
1902
1903 return true;
1904}
1905
1906
1907/**
1908 * Next CPU configuration to test the current instruction in.
1909 *
1910 * This is for testing FPU, SSE and AVX instructions with the various lazy state
1911 * load and enable bits in different configurations to ensure we're getting the
1912 * right response.
1913 *
1914 * This also cleans up the CPU and test driver state.
1915 *
1916 * @returns true if we're to do another round, false if we're done.
1917 * @param pThis The state.
1918 * @param iCpuSetup The current CPU setup number.
1919 * @param pfInvalidInstr Where to indicate whether the setup causes an
1920 * invalid instruction or not. This is also used as
1921 * input to avoid unnecessary CPUID work.
1922 */
1923static bool Bs3Cg1CpuSetupNext(PBS3CG1STATE pThis, unsigned iCpuSetup, bool *pfInvalidInstr)
1924{
1925 if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
1926 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1927 return false;
1928
1929 switch (pThis->enmCpuTest)
1930 {
1931 case BS3CG1CPU_ANY:
1932 case BS3CG1CPU_GE_80186:
1933 case BS3CG1CPU_GE_80286:
1934 case BS3CG1CPU_GE_80386:
1935 case BS3CG1CPU_GE_80486:
1936 case BS3CG1CPU_GE_Pentium:
1937 case BS3CG1CPU_CLFSH:
1938 return false;
1939
1940 case BS3CG1CPU_SSE:
1941 case BS3CG1CPU_SSE2:
1942 case BS3CG1CPU_SSE3:
1943 case BS3CG1CPU_AVX:
1944 case BS3CG1CPU_AVX2:
1945 if (iCpuSetup > 0 || *pfInvalidInstr)
1946 {
1947 /** @todo do more configs here. */
1948 pThis->fWorkExtCtx = false;
1949 ASMSetCR0(ASMGetCR0() | X86_CR0_EM | X86_CR0_MP);
1950 ASMSetCR4(ASMGetCR4() & ~(X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE));
1951 return false;
1952 }
1953 return false;
1954
1955 default:
1956 Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
1957 return false;
1958 }
1959}
1960
1961
1962/**
1963 * Check if the instruction is supported by the CPU, possibly making state
1964 * adjustments to enable support for it.
1965 *
1966 * @returns true if supported, false if not.
1967 * @param pThis The state.
1968 */
1969static bool Bs3Cg1CpuSetupFirst(PBS3CG1STATE pThis)
1970{
1971 uint32_t fEax;
1972 uint32_t fEbx;
1973 uint32_t fEcx;
1974 uint32_t fEdx;
1975
1976 if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
1977 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1978 return false;
1979
1980 switch (pThis->enmCpuTest)
1981 {
1982 case BS3CG1CPU_ANY:
1983 return true;
1984
1985 case BS3CG1CPU_GE_80186:
1986 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80186)
1987 return true;
1988 return false;
1989
1990 case BS3CG1CPU_GE_80286:
1991 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286)
1992 return true;
1993 return false;
1994
1995 case BS3CG1CPU_GE_80386:
1996 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1997 return true;
1998 return false;
1999
2000 case BS3CG1CPU_GE_80486:
2001 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
2002 return true;
2003 return false;
2004
2005 case BS3CG1CPU_GE_Pentium:
2006 if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_Pentium)
2007 return true;
2008 return false;
2009
2010 case BS3CG1CPU_SSE:
2011 case BS3CG1CPU_SSE2:
2012 case BS3CG1CPU_SSE3:
2013 case BS3CG1CPU_AVX:
2014 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2015 {
2016 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
2017 switch (pThis->enmCpuTest)
2018 {
2019 case BS3CG1CPU_SSE:
2020 if (fEdx & X86_CPUID_FEATURE_EDX_SSE)
2021 return Bs3Cg3SetupSseAndAvx(pThis);
2022 return false;
2023 case BS3CG1CPU_SSE2:
2024 if (fEdx & X86_CPUID_FEATURE_EDX_SSE2)
2025 return Bs3Cg3SetupSseAndAvx(pThis);
2026 return false;
2027 case BS3CG1CPU_SSE3:
2028 if (fEcx & X86_CPUID_FEATURE_ECX_SSE3)
2029 return Bs3Cg3SetupSseAndAvx(pThis);
2030 return false;
2031 case BS3CG1CPU_AVX:
2032 if (fEcx & X86_CPUID_FEATURE_ECX_AVX)
2033 return Bs3Cg3SetupSseAndAvx(pThis);
2034 return false;
2035 default: BS3_ASSERT(0); /* impossible */
2036 }
2037 }
2038 return false;
2039
2040 case BS3CG1CPU_AVX2:
2041 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2042 {
2043 ASMCpuIdExSlow(7, 0, 0/*leaf*/, 0, &fEax, &fEbx, &fEcx, &fEdx);
2044 switch (pThis->enmCpuTest)
2045 {
2046 case BS3CG1CPU_AVX2:
2047 if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2)
2048 return Bs3Cg3SetupSseAndAvx(pThis);
2049 return false;
2050 default: BS3_ASSERT(0); return false; /* impossible */
2051 }
2052 }
2053 return false;
2054
2055 case BS3CG1CPU_CLFSH:
2056 if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2057 {
2058 ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
2059 if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
2060 return true;
2061 }
2062 return false;
2063
2064
2065 default:
2066 Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2067 return false;
2068 }
2069}
2070
2071
2072
2073/**
2074 * Checks the preconditions for a test.
2075 *
2076 * @returns true if the test be executed, false if not.
2077 * @param pThis The state.
2078 * @param pHdr The test header.
2079 */
2080static bool Bs3Cg1RunSelector(PBS3CG1STATE pThis, PCBS3CG1TESTHDR pHdr)
2081{
2082
2083 uint8_t const BS3_FAR *pbCode = (uint8_t const BS3_FAR *)(pHdr + 1);
2084 unsigned cbLeft = pHdr->cbSelector;
2085 while (cbLeft-- > 0)
2086 {
2087 switch (*pbCode++)
2088 {
2089#define CASE_PRED(a_Pred, a_Expr) \
2090 case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) | BS3CG1SEL_OP_IS_TRUE: \
2091 if (!(a_Expr)) return false; \
2092 break; \
2093 case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) | BS3CG1SEL_OP_IS_FALSE: \
2094 if (a_Expr) return false; \
2095 break
2096 CASE_PRED(BS3CG1PRED_SIZE_O16, pThis->cbOperand == 2);
2097 CASE_PRED(BS3CG1PRED_SIZE_O32, pThis->cbOperand == 4);
2098 CASE_PRED(BS3CG1PRED_SIZE_O64, pThis->cbOperand == 8);
2099 CASE_PRED(BS3CG1PRED_RING_0, pThis->uCpl == 0);
2100 CASE_PRED(BS3CG1PRED_RING_1, pThis->uCpl == 1);
2101 CASE_PRED(BS3CG1PRED_RING_2, pThis->uCpl == 2);
2102 CASE_PRED(BS3CG1PRED_RING_3, pThis->uCpl == 3);
2103 CASE_PRED(BS3CG1PRED_RING_0_THRU_2, pThis->uCpl <= 2);
2104 CASE_PRED(BS3CG1PRED_RING_1_THRU_3, pThis->uCpl >= 1);
2105 CASE_PRED(BS3CG1PRED_CODE_64BIT, BS3_MODE_IS_64BIT_CODE(pThis->bMode));
2106 CASE_PRED(BS3CG1PRED_CODE_32BIT, BS3_MODE_IS_32BIT_CODE(pThis->bMode));
2107 CASE_PRED(BS3CG1PRED_CODE_16BIT, BS3_MODE_IS_16BIT_CODE(pThis->bMode));
2108 CASE_PRED(BS3CG1PRED_MODE_REAL, BS3_MODE_IS_RM_SYS(pThis->bMode));
2109 CASE_PRED(BS3CG1PRED_MODE_PROT, BS3_MODE_IS_PM_SYS(pThis->bMode));
2110 CASE_PRED(BS3CG1PRED_MODE_LONG, BS3_MODE_IS_64BIT_SYS(pThis->bMode));
2111 CASE_PRED(BS3CG1PRED_MODE_SMM, false);
2112 CASE_PRED(BS3CG1PRED_MODE_VMX, false);
2113 CASE_PRED(BS3CG1PRED_MODE_SVM, false);
2114 CASE_PRED(BS3CG1PRED_PAGING_ON, BS3_MODE_IS_PAGED(pThis->bMode));
2115 CASE_PRED(BS3CG1PRED_PAGING_OFF, !BS3_MODE_IS_PAGED(pThis->bMode));
2116
2117#undef CASE_PRED
2118 default:
2119 return Bs3TestFailedF("Invalid selector opcode %#x!", pbCode[-1]);
2120 }
2121 }
2122
2123 return true;
2124}
2125
2126
2127#ifdef BS3CG1_DEBUG_CTX_MOD
2128/**
2129 * Translates the operator into a string.
2130 *
2131 * @returns Read-only string pointer.
2132 * @param bOpcode The context modifier program opcode.
2133 */
2134static const char BS3_FAR *Bs3Cg1CtxOpToString(uint8_t bOpcode)
2135{
2136 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2137 {
2138 case BS3CG1_CTXOP_ASSIGN: return "=";
2139 case BS3CG1_CTXOP_OR: return "|=";
2140 case BS3CG1_CTXOP_AND: return "&=";
2141 case BS3CG1_CTXOP_AND_INV: return "&~=";
2142 }
2143}
2144#endif
2145
2146
2147/**
2148 * Runs a context modifier program.
2149 *
2150 * @returns Success indicator (true/false).
2151 * @param pThis The state.
2152 * @param pCtx The context.
2153 * @param pHdr The program header.
2154 * @param off The program offset relative to the end of the header.
2155 * @param cb The program size.
2156 * @param pEflCtx The context to take undefined EFLAGS from. (This is NULL
2157 * if we're processing a input context modifier program.)
2158 * @param pbInstr Points to the first instruction byte. For storing
2159 * immediate operands during input context modification.
2160 * NULL for output contexts.
2161 */
2162static bool Bs3Cg1RunContextModifier(PBS3CG1STATE pThis, PBS3REGCTX pCtx, PCBS3CG1TESTHDR pHdr, unsigned off, unsigned cb,
2163 PCBS3REGCTX pEflCtx, uint8_t BS3_FAR *pbInstr)
2164{
2165 uint8_t const BS3_FAR *pbCode = (uint8_t const BS3_FAR *)(pHdr + 1) + off;
2166 int cbLeft = cb;
2167 while (cbLeft-- > 0)
2168 {
2169 /*
2170 * Decode the instruction.
2171 */
2172 uint8_t const bOpcode = *pbCode++;
2173 unsigned cbValue;
2174 unsigned cbDst;
2175 BS3CG1DST idxField;
2176 BS3PTRUNION PtrField;
2177
2178 /* Expand the destiation field (can be escaped). */
2179 switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
2180 {
2181 case BS3CG1_CTXOP_OP1:
2182 idxField = pThis->aOperands[0].idxField;
2183 if (idxField == BS3CG1DST_INVALID)
2184 idxField = BS3CG1DST_OP1;
2185 break;
2186
2187 case BS3CG1_CTXOP_OP2:
2188 idxField = pThis->aOperands[1].idxField;
2189 if (idxField == BS3CG1DST_INVALID)
2190 idxField = BS3CG1DST_OP2;
2191 break;
2192
2193 case BS3CG1_CTXOP_EFL:
2194 idxField = BS3CG1DST_EFL;
2195 break;
2196
2197 case BS3CG1_CTXOP_DST_ESC:
2198 if (cbLeft-- > 0)
2199 {
2200 idxField = (BS3CG1DST)*pbCode++;
2201 if (idxField <= BS3CG1DST_OP4)
2202 {
2203 if (idxField > BS3CG1DST_INVALID)
2204 {
2205 uint8_t idxField2 = pThis->aOperands[idxField - BS3CG1DST_OP1].idxField;
2206 if (idxField2 != BS3CG1DST_INVALID)
2207 idxField = idxField2;
2208 break;
2209 }
2210 }
2211 else if (idxField < BS3CG1DST_END)
2212 break;
2213 return Bs3TestFailedF("Malformed context instruction: idxField=%d", idxField);
2214 }
2215 /* fall thru */
2216 default:
2217 return Bs3TestFailed("Malformed context instruction: Destination");
2218 }
2219
2220
2221 /* Expand value size (can be escaped). */
2222 switch (bOpcode & BS3CG1_CTXOP_SIZE_MASK)
2223 {
2224 case BS3CG1_CTXOP_1_BYTE: cbValue = 1; break;
2225 case BS3CG1_CTXOP_2_BYTES: cbValue = 2; break;
2226 case BS3CG1_CTXOP_4_BYTES: cbValue = 4; break;
2227 case BS3CG1_CTXOP_8_BYTES: cbValue = 8; break;
2228 case BS3CG1_CTXOP_16_BYTES: cbValue = 16; break;
2229 case BS3CG1_CTXOP_32_BYTES: cbValue = 32; break;
2230 case BS3CG1_CTXOP_12_BYTES: cbValue = 12; break;
2231 case BS3CG1_CTXOP_SIZE_ESC:
2232 if (cbLeft-- > 0)
2233 {
2234 cbValue = *pbCode++;
2235 if (cbValue)
2236 break;
2237 }
2238 /* fall thru */
2239 default:
2240 return Bs3TestFailed("Malformed context instruction: size");
2241 }
2242
2243 /* Make sure there is enough instruction bytes for the value. */
2244 if (cbValue <= cbLeft)
2245 { /* likely */ }
2246 else
2247 return Bs3TestFailedF("Malformed context instruction: %u bytes value, %u bytes left", cbValue, cbLeft);
2248
2249 /*
2250 * Do value processing specific to the target field size.
2251 */
2252 cbDst = g_acbBs3Cg1DstFields[idxField];
2253 if (cbDst == BS3CG1DSTSIZE_OPERAND)
2254 cbDst = pThis->aOperands[idxField - BS3CG1DST_OP1].cbOp;
2255 else if (cbDst == BS3CG1DSTSIZE_OPERAND_SIZE_GRP)
2256 cbDst = pThis->cbOperand;
2257 if (cbDst <= 8)
2258 {
2259 unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2260
2261 /*
2262 * Deal with fields up to 8-byte wide.
2263 */
2264 /* Get the value. */
2265 uint64_t uValue;
2266 if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT))
2267 switch (cbValue)
2268 {
2269 case 1: uValue = *(int8_t const BS3_FAR *)pbCode; break;
2270 case 2: uValue = *(int16_t const BS3_FAR *)pbCode; break;
2271 case 4: uValue = *(int32_t const BS3_FAR *)pbCode; break;
2272 default:
2273 if (cbValue >= 8)
2274 {
2275 uValue = *(uint64_t const BS3_FAR *)pbCode;
2276 break;
2277 }
2278 return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2279 }
2280 else
2281 switch (cbValue)
2282 {
2283 case 1: uValue = *(uint8_t const BS3_FAR *)pbCode; break;
2284 case 2: uValue = *(uint16_t const BS3_FAR *)pbCode; break;
2285 case 4: uValue = *(uint32_t const BS3_FAR *)pbCode; break;
2286 default:
2287 if (cbValue >= 8)
2288 {
2289 uValue = *(uint64_t const BS3_FAR *)pbCode;
2290 break;
2291 }
2292 return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2293 }
2294
2295 /* Find the field. */
2296 if (offField < sizeof(BS3REGCTX))
2297 PtrField.pu8 = (uint8_t BS3_FAR *)pCtx + offField;
2298 /* Non-register operands: */
2299 else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2300 {
2301 unsigned const idxOp = idxField - BS3CG1DST_OP1;
2302
2303 switch (pThis->aOperands[idxOp].enmLocation)
2304 {
2305 case BS3CG1OPLOC_IMM:
2306 if (pbInstr)
2307 PtrField.pu8 = &pbInstr[pThis->aOperands[idxOp].off];
2308 else
2309 return Bs3TestFailedF("Immediate operand referenced in output context!");
2310 break;
2311
2312 case BS3CG1OPLOC_MEM:
2313 if (!pbInstr)
2314 return Bs3TestFailedF("Read only operand specified in output!");
2315 PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2316 break;
2317
2318 case BS3CG1OPLOC_MEM_RW:
2319 if (pbInstr)
2320 PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2321 else
2322 PtrField.pu8 = pThis->MemOp.ab;
2323 break;
2324
2325 default:
2326 return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
2327 cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
2328 pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2329 }
2330 }
2331 /* Special field: Copying in undefined EFLAGS from the result context. */
2332 else if (idxField == BS3CG1DST_EFL_UNDEF)
2333 {
2334 if (!pEflCtx || (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN)
2335 return Bs3TestFailed("Invalid BS3CG1DST_EFL_UNDEF usage");
2336 PtrField.pu32 = &pCtx->rflags.u32;
2337 uValue = (*PtrField.pu32 & ~(uint32_t)uValue) | (pEflCtx->rflags.u32 & (uint32_t)uValue);
2338 }
2339 /* Special field: Expected value (in/result) exception. */
2340 else if (idxField == BS3CG1DST_VALUE_XCPT)
2341 {
2342 if (!pEflCtx || (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN || cbDst != 1)
2343 return Bs3TestFailed("Invalid BS3CG1DST_VALUE_XCPT usage");
2344 PtrField.pu8 = &pThis->bValueXcpt;
2345 }
2346 /* FPU and FXSAVE format. */
2347 else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2348 && offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2349 {
2350 if (!pThis->fWorkExtCtx)
2351 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2352 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2353 }
2354 /** @todo other FPU fields and FPU state formats. */
2355 else
2356 return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
2357
2358#ifdef BS3CG1_DEBUG_CTX_MOD
2359 switch (cbDst)
2360 {
2361 case 1:
2362 BS3CG1_DPRINTF(("dbg: modify %s: %#04RX8 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2363 *PtrField.pu8, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2364 break;
2365 case 2:
2366 BS3CG1_DPRINTF(("dbg: modify %s: %#06RX16 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2367 *PtrField.pu16, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2368 break;
2369 case 4:
2370 BS3CG1_DPRINTF(("dbg: modify %s: %#010RX32 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2371 *PtrField.pu32, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2372 break;
2373 default:
2374 BS3CG1_DPRINTF(("dbg: modify %s: %#018RX64 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2375 *PtrField.pu64, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2376 break;
2377 }
2378#endif
2379
2380 /* Modify the field. */
2381 switch (cbDst)
2382 {
2383 case 1:
2384 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2385 {
2386 case BS3CG1_CTXOP_ASSIGN: *PtrField.pu8 = (uint8_t)uValue; break;
2387 case BS3CG1_CTXOP_OR: *PtrField.pu8 |= (uint8_t)uValue; break;
2388 case BS3CG1_CTXOP_AND: *PtrField.pu8 &= (uint8_t)uValue; break;
2389 case BS3CG1_CTXOP_AND_INV: *PtrField.pu8 &= ~(uint8_t)uValue; break;
2390 }
2391 break;
2392
2393 case 2:
2394 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2395 {
2396 case BS3CG1_CTXOP_ASSIGN: *PtrField.pu16 = (uint16_t)uValue; break;
2397 case BS3CG1_CTXOP_OR: *PtrField.pu16 |= (uint16_t)uValue; break;
2398 case BS3CG1_CTXOP_AND: *PtrField.pu16 &= (uint16_t)uValue; break;
2399 case BS3CG1_CTXOP_AND_INV: *PtrField.pu16 &= ~(uint16_t)uValue; break;
2400 }
2401 break;
2402
2403 case 4:
2404 if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
2405 PtrField.pu32[1] = 0;
2406 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2407 {
2408 case BS3CG1_CTXOP_ASSIGN: *PtrField.pu32 = (uint32_t)uValue; break;
2409 case BS3CG1_CTXOP_OR: *PtrField.pu32 |= (uint32_t)uValue; break;
2410 case BS3CG1_CTXOP_AND: *PtrField.pu32 &= (uint32_t)uValue; break;
2411 case BS3CG1_CTXOP_AND_INV: *PtrField.pu32 &= ~(uint32_t)uValue; break;
2412 }
2413 break;
2414
2415 case 8:
2416 if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
2417 PtrField.pu64[1] = 0;
2418 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2419 {
2420 case BS3CG1_CTXOP_ASSIGN: *PtrField.pu64 = (uint64_t)uValue; break;
2421 case BS3CG1_CTXOP_OR: *PtrField.pu64 |= (uint64_t)uValue; break;
2422 case BS3CG1_CTXOP_AND: *PtrField.pu64 &= (uint64_t)uValue; break;
2423 case BS3CG1_CTXOP_AND_INV: *PtrField.pu64 &= ~(uint64_t)uValue; break;
2424 }
2425 break;
2426
2427 default:
2428 return Bs3TestFailedF("Malformed context instruction: cbDst=%u, expected 1, 2, 4, or 8", cbDst);
2429 }
2430
2431#ifdef BS3CG1_DEBUG_CTX_MOD
2432 switch (cbDst)
2433 {
2434 case 1: BS3CG1_DPRINTF(("dbg: --> %s: %#04RX8\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu8)); break;
2435 case 2: BS3CG1_DPRINTF(("dbg: --> %s: %#06RX16\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu16)); break;
2436 case 4: BS3CG1_DPRINTF(("dbg: --> %s: %#010RX32\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu32)); break;
2437 default: BS3CG1_DPRINTF(("dbg: --> %s: %#018RX64\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu64)); break;
2438 }
2439#endif
2440
2441 }
2442 /*
2443 * Deal with larger field (FPU, SSE, AVX, ...).
2444 */
2445 else
2446 {
2447 union
2448 {
2449 X86FPUREG FpuReg;
2450 X86XMMREG XmmReg;
2451 X86YMMREG YmmReg;
2452 X86ZMMREG ZmmReg;
2453 uint8_t ab[sizeof(X86ZMMREG)];
2454 uint32_t au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
2455 } Value;
2456 unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2457
2458 if (!pThis->fWorkExtCtx)
2459 return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2460
2461 /* Copy the value into the union, doing the zero padding / extending. */
2462 Bs3MemCpy(&Value, pbCode, cbValue);
2463 if (cbValue < sizeof(Value))
2464 {
2465 if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
2466 Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
2467 else
2468 Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
2469 }
2470
2471 /* Optimized access to XMM and STx registers. */
2472 if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2473 && offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2474 PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2475 /* Non-register operands: */
2476 else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2477 {
2478 unsigned const idxOp = idxField - BS3CG1DST_OP1;
2479 switch (pThis->aOperands[idxOp].enmLocation)
2480 {
2481 case BS3CG1OPLOC_MEM:
2482 if (!pbInstr)
2483 return Bs3TestFailedF("Read only operand specified in output!");
2484 PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2485 break;
2486
2487 case BS3CG1OPLOC_MEM_RW:
2488 if (pbInstr)
2489 PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2490 else
2491 PtrField.pu8 = pThis->MemOp.ab;
2492 break;
2493
2494 default:
2495 return Bs3TestFailedF("Internal error: Field %d (%d) @ %#x LB %u: enmLocation=%u off=%#x idxField=%u",
2496 idxField, idxOp, offField, cbDst, pThis->aOperands[idxOp].enmLocation,
2497 pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2498 }
2499 }
2500 /* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
2501 the state, so they need special handling. */
2502 else
2503 {
2504 return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
2505 }
2506
2507 if (PtrField.pb)
2508 {
2509 /* Modify the field / memory. */
2510 unsigned i;
2511 if (cbDst & 3)
2512 return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
2513
2514#ifdef BS3CG1_DEBUG_CTX_MOD
2515 BS3CG1_DPRINTF(("dbg: modify %s: %.*Rhxs (LB %u) %s %.*Rhxs (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2516 cbDst, PtrField.pb, cbDst, Bs3Cg1CtxOpToString(bOpcode), cbValue, Value.ab, cbValue));
2517#endif
2518
2519 i = cbDst / 4;
2520 while (i-- > 0)
2521 {
2522 switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2523 {
2524 case BS3CG1_CTXOP_ASSIGN: PtrField.pu32[i] = Value.au32[i]; break;
2525 case BS3CG1_CTXOP_OR: PtrField.pu32[i] |= Value.au32[i]; break;
2526 case BS3CG1_CTXOP_AND: PtrField.pu32[i] &= Value.au32[i]; break;
2527 case BS3CG1_CTXOP_AND_INV: PtrField.pu32[i] &= ~Value.au32[i]; break;
2528 }
2529 }
2530
2531#ifdef BS3CG1_DEBUG_CTX_MOD
2532 BS3CG1_DPRINTF(("dbg: --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
2533#endif
2534 }
2535 }
2536
2537 /*
2538 * Advance to the next instruction.
2539 */
2540 pbCode += cbValue;
2541 cbLeft -= cbValue;
2542 }
2543
2544 return true;
2545}
2546
2547
2548/**
2549 * Checks the result of a run.
2550 *
2551 * @returns true if successful, false if not.
2552 * @param pThis The state.
2553 * @param fInvalidInstr Whether this is an invalid instruction.
2554 * @param bTestXcptExpected The exception causing the test code to stop
2555 * executing.
2556 * @param iEncoding For error reporting.
2557 */
2558static bool Bs3Cg1CheckResult(PBS3CG1STATE pThis, bool fInvalidInstr, uint8_t bTestXcptExpected, unsigned iEncoding)
2559{
2560 unsigned iOperand;
2561
2562 /*
2563 * Check the exception state first.
2564 */
2565 uint8_t bExpectedXcpt;
2566 uint8_t cbAdjustPc;
2567 if (!fInvalidInstr)
2568 {
2569 bExpectedXcpt = pThis->bAlignmentXcpt;
2570 if (bExpectedXcpt == UINT8_MAX)
2571 bExpectedXcpt = pThis->bValueXcpt;
2572 if (bExpectedXcpt == UINT8_MAX)
2573 {
2574 cbAdjustPc = pThis->cbCurInstr;
2575 bExpectedXcpt = bTestXcptExpected;
2576 if (bTestXcptExpected == X86_XCPT_PF)
2577 pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
2578 }
2579 else
2580 cbAdjustPc = 0;
2581 }
2582 else
2583 {
2584 cbAdjustPc = 0;
2585 bExpectedXcpt = bTestXcptExpected;
2586 }
2587 if (RT_LIKELY( pThis->TrapFrame.bXcpt == bExpectedXcpt
2588 && pThis->TrapFrame.Ctx.rip.u == pThis->Ctx.rip.u + cbAdjustPc))
2589 {
2590 /*
2591 * Check the register content.
2592 */
2593 bool fOkay = Bs3TestCheckRegCtxEx(&pThis->TrapFrame.Ctx, &pThis->Ctx,
2594 cbAdjustPc, 0 /*cbSpAdjust*/, 0 /*fExtraEfl*/,
2595 pThis->pszMode, iEncoding);
2596
2597 /*
2598 * Check memory output operands.
2599 */
2600 iOperand = pThis->cOperands;
2601 while (iOperand-- > 0)
2602 if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
2603 {
2604 BS3PTRUNION PtrUnion;
2605 PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
2606 switch (pThis->aOperands[iOperand].cbOp)
2607 {
2608 case 1:
2609 if (*PtrUnion.pu8 == pThis->MemOp.ab[0])
2610 continue;
2611 Bs3TestFailedF("op%u: Wrote %#04RX8, expected %#04RX8", iOperand, *PtrUnion.pu8, pThis->MemOp.ab[0]);
2612 break;
2613 case 2:
2614 if (*PtrUnion.pu16 == pThis->MemOp.au16[0])
2615 continue;
2616 Bs3TestFailedF("op%u: Wrote %#06RX16, expected %#06RX16",
2617 iOperand, *PtrUnion.pu16, pThis->MemOp.au16[0]);
2618 break;
2619 case 4:
2620 if (*PtrUnion.pu32 == pThis->MemOp.au32[0])
2621 continue;
2622 Bs3TestFailedF("op%u: Wrote %#010RX32, expected %#010RX32",
2623 iOperand, *PtrUnion.pu32, pThis->MemOp.au32[0]);
2624 break;
2625 case 8:
2626 if (*PtrUnion.pu64 == pThis->MemOp.au64[0])
2627 continue;
2628 Bs3TestFailedF("op%u: Wrote %#018RX64, expected %#018RX64",
2629 iOperand, *PtrUnion.pu64, pThis->MemOp.au64[0]);
2630 break;
2631 default:
2632 if (Bs3MemCmp(PtrUnion.pb, pThis->MemOp.ab, pThis->aOperands[iOperand].cbOp) == 0)
2633 continue;
2634 Bs3TestFailedF("op%u: Wrote %.*Rhxs, expected %.*Rhxs",
2635 iOperand,
2636 pThis->aOperands[iOperand].cbOp, PtrUnion.pb,
2637 pThis->aOperands[iOperand].cbOp, pThis->MemOp.ab);
2638 break;
2639 }
2640 fOkay = false;
2641 }
2642
2643 /*
2644 * Check extended context if enabled.
2645 */
2646 if (pThis->fWorkExtCtx)
2647 {
2648 PBS3EXTCTX pExpect = pThis->pExtCtx;
2649 PBS3EXTCTX pResult = pThis->pResultExtCtx;
2650 unsigned i;
2651 if ( pExpect->enmMethod == BS3EXTCTXMETHOD_XSAVE
2652 || pExpect->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
2653 {
2654 /* Compare the x87 state, ASSUMING XCR0 bit 1 is set. */
2655#define CHECK_FIELD(a_Field, a_szFmt) \
2656 if (pResult->Ctx.a_Field != pExpect->Ctx.a_Field) fOkay = Bs3TestFailedF(a_szFmt, pResult->Ctx.a_Field, pExpect->Ctx.a_Field)
2657 CHECK_FIELD(x87.FCW, "FCW: %#06x, expected %#06x");
2658 CHECK_FIELD(x87.FSW, "FSW: %#06x, expected %#06x");
2659 CHECK_FIELD(x87.FTW, "FTW: %#06x, expected %#06x");
2660 //CHECK_FIELD(x87.FOP, "FOP: %#06x, expected %#06x");
2661 //CHECK_FIELD(x87.FPUIP, "FPUIP: %#010x, expected %#010x");
2662 //CHECK_FIELD(x87.CS, "FPUCS: %#06x, expected %#06x");
2663 //CHECK_FIELD(x87.Rsrvd1, "Rsrvd1: %#06x, expected %#06x");
2664 //CHECK_FIELD(x87.DP, "FPUDP: %#010x, expected %#010x");
2665 //CHECK_FIELD(x87.DS, "FPUDS: %#06x, expected %#06x");
2666 //CHECK_FIELD(x87.Rsrvd2, "Rsrvd2: %#06x, expected %#06x");
2667 CHECK_FIELD(x87.MXCSR, "MXCSR: %#010x, expected %#010x");
2668 //CHECK_FIELD(x87.MXCSR_MASK, "MXCSR_MASK: %#010x, expected %#010x");
2669#undef CHECK_FIELD
2670 for (i = 0; i < RT_ELEMENTS(pExpect->Ctx.x87.aRegs); i++)
2671 if ( pResult->Ctx.x87.aRegs[i].au64[0] != pExpect->Ctx.x87.aRegs[i].au64[0]
2672 || pResult->Ctx.x87.aRegs[i].au16[4] != pExpect->Ctx.x87.aRegs[i].au16[4])
2673 fOkay = Bs3TestFailedF("ST[%u]: %c m=%#RX64 e=%d, expected %c m=%#RX64 e=%d", i,
2674 pResult->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
2675 pResult->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
2676 pResult->Ctx.x87.aRegs[i].r80Ex.s.uExponent,
2677 pExpect->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
2678 pExpect->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
2679 pExpect->Ctx.x87.aRegs[i].r80Ex.s.uExponent);
2680 for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
2681 if ( pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
2682 || pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
2683 fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%08RX64, expected %#010RX64'%08RX64", i,
2684 pResult->Ctx.x87.aXMM[i].au64[0],
2685 pResult->Ctx.x87.aXMM[i].au64[1],
2686 pExpect->Ctx.x87.aXMM[i].au64[0],
2687 pExpect->Ctx.x87.aXMM[i].au64[1]);
2688 }
2689 else
2690 fOkay = Bs3TestFailedF("Unsupported extended CPU context method: %d", pExpect->enmMethod);
2691 }
2692
2693 /*
2694 * Done.
2695 */
2696 if (fOkay)
2697 return true;
2698
2699 /*
2700 * Report failure.
2701 */
2702 Bs3TestFailedF("%RU32[%u]: encoding#%u: %.*Rhxs",
2703 pThis->iInstr, pThis->iTest, iEncoding, pThis->cbCurInstr, pThis->abCurInstr);
2704 }
2705 else
2706 Bs3TestFailedF("%RU32[%u]: bXcpt=%#x expected %#x; rip=%RX64 expected %RX64; encoding#%u: %.*Rhxs",
2707 pThis->iInstr, pThis->iTest,
2708 pThis->TrapFrame.bXcpt, bExpectedXcpt,
2709 pThis->TrapFrame.Ctx.rip.u, pThis->Ctx.rip.u + cbAdjustPc,
2710 iEncoding, pThis->cbCurInstr, pThis->abCurInstr);
2711 Bs3TestPrintf("cpl=%u cbOperands=%u\n", pThis->uCpl, pThis->cbOperand);
2712
2713 /*
2714 * Display memory operands.
2715 */
2716 for (iOperand = 0; iOperand < pThis->cOperands; iOperand++)
2717 {
2718 BS3PTRUNION PtrUnion;
2719 switch (pThis->aOperands[iOperand].enmLocation)
2720 {
2721 case BS3CG1OPLOC_CTX:
2722 {
2723 uint8_t idxField = pThis->aOperands[iOperand].idxField;
2724 unsigned offField = g_aoffBs3Cg1DstFields[idxField];
2725 if (offField <= sizeof(BS3REGCTX))
2726 PtrUnion.pb = (uint8_t BS3_FAR *)&pThis->Ctx + offField;
2727 else
2728 {
2729 Bs3TestPrintf("op%u: ctx%u: xxxx\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
2730 break;
2731 }
2732 switch (pThis->aOperands[iOperand].cbOp)
2733 {
2734 case 1: Bs3TestPrintf("op%u: ctx08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2735 case 2: Bs3TestPrintf("op%u: ctx16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2736 case 4: Bs3TestPrintf("op%u: ctx32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2737 case 8: Bs3TestPrintf("op%u: ctx64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2738 default:
2739 Bs3TestPrintf("op%u: ctx%u: %.*Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp * 8,
2740 pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2741 break;
2742 }
2743 break;
2744 }
2745
2746 case BS3CG1OPLOC_IMM:
2747 PtrUnion.pb = &pThis->pbCodePg[pThis->aOperands[iOperand].off];
2748 switch (pThis->aOperands[iOperand].cbOp)
2749 {
2750 case 1: Bs3TestPrintf("op%u: imm08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2751 case 2: Bs3TestPrintf("op%u: imm16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2752 case 4: Bs3TestPrintf("op%u: imm32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2753 case 8: Bs3TestPrintf("op%u: imm64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2754 default:
2755 Bs3TestPrintf("op%u: imm%u: %.*Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp * 8,
2756 pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2757 break;
2758 }
2759 break;
2760
2761 case BS3CG1OPLOC_MEM:
2762 case BS3CG1OPLOC_MEM_RW:
2763 PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
2764 switch (pThis->aOperands[iOperand].cbOp)
2765 {
2766 case 1: Bs3TestPrintf("op%u: result mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2767 case 2: Bs3TestPrintf("op%u: result mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2768 case 4: Bs3TestPrintf("op%u: result mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2769 case 8: Bs3TestPrintf("op%u: result mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2770 default:
2771 Bs3TestPrintf("op%u: result mem%u: %.*Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp * 8,
2772 pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2773 break;
2774 }
2775 if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
2776 {
2777 PtrUnion.pb = pThis->MemOp.ab;
2778 switch (pThis->aOperands[iOperand].cbOp)
2779 {
2780 case 1: Bs3TestPrintf("op%u: expect mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2781 case 2: Bs3TestPrintf("op%u: expect mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2782 case 4: Bs3TestPrintf("op%u: expect mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2783 case 8: Bs3TestPrintf("op%u: expect mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2784 default:
2785 Bs3TestPrintf("op%u: expect mem%u: %.*Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp * 8,
2786 pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2787 break;
2788 }
2789 }
2790 break;
2791 }
2792 }
2793
2794 /*
2795 * Display contexts.
2796 */
2797 Bs3TestPrintf("-- Expected context:\n");
2798 Bs3RegCtxPrint(&pThis->Ctx);
2799 Bs3TestPrintf("-- Actual context:\n");
2800 Bs3TrapPrintFrame(&pThis->TrapFrame);
2801 Bs3TestPrintf("\n");
2802 return false;
2803}
2804
2805
2806/**
2807 * Destroys the state, freeing all allocations and such.
2808 *
2809 * @param pThis The state.
2810 */
2811static void Bs3Cg1Destroy(PBS3CG1STATE pThis)
2812{
2813 if (BS3_MODE_IS_PAGED(pThis->bMode))
2814 {
2815#if ARCH_BITS != 16
2816 Bs3MemGuardedTestPageFree(pThis->pbCodePg);
2817 Bs3MemGuardedTestPageFree(pThis->pbDataPg);
2818#endif
2819 }
2820 else
2821 {
2822 Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
2823 Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
2824 }
2825
2826 if (pThis->pExtCtx)
2827 Bs3MemFree(pThis->pExtCtx, pThis->pExtCtx->cb * 3);
2828
2829 pThis->pbCodePg = NULL;
2830 pThis->pbDataPg = NULL;
2831 pThis->pExtCtx = NULL;
2832 pThis->pResultExtCtx = NULL;
2833 pThis->pInitialExtCtx = NULL;
2834}
2835
2836
2837/**
2838 * Initializes the state.
2839 *
2840 * @returns Success indicator (true/false)
2841 * @param pThis The state.
2842 * @param bMode The mode being tested.
2843 */
2844bool BS3_CMN_NM(Bs3Cg1Init)(PBS3CG1STATE pThis, uint8_t bMode)
2845{
2846 BS3MEMKIND const enmMemKind = BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL
2847 : !BS3_MODE_IS_64BIT_CODE(bMode) ? BS3MEMKIND_TILED : BS3MEMKIND_FLAT32;
2848 unsigned iRing;
2849 unsigned cb;
2850 unsigned i;
2851 uint64_t fFlags;
2852 PBS3EXTCTX pExtCtx;
2853
2854 Bs3MemSet(pThis, 0, sizeof(*pThis));
2855
2856 pThis->iFirstRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
2857 pThis->iEndRing = BS3_MODE_IS_RM_SYS(bMode) ? 1 : 4;
2858 pThis->bMode = bMode;
2859 pThis->pszMode = Bs3GetModeName(bMode);
2860 pThis->pszModeShort = Bs3GetModeNameShortLower(bMode);
2861 pThis->pchMnemonic = g_achBs3Cg1Mnemonics;
2862 pThis->pabOperands = g_abBs3Cg1Operands;
2863 pThis->pabOpcodes = g_abBs3Cg1Opcodes;
2864 pThis->fAdvanceMnemonic = 1;
2865
2866 /* Allocate extended context structures. */
2867 cb = Bs3ExtCtxGetSize(&fFlags);
2868 pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 3);
2869 if (!pExtCtx)
2870 return Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 3);
2871 pThis->pExtCtx = pExtCtx;
2872 pThis->pResultExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb);
2873 pThis->pInitialExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb + cb);
2874
2875 Bs3ExtCtxInit(pThis->pExtCtx, cb, fFlags);
2876 Bs3ExtCtxInit(pThis->pResultExtCtx, cb, fFlags);
2877 Bs3ExtCtxInit(pThis->pInitialExtCtx, cb, fFlags);
2878 //Bs3TestPrintf("fCR0=%RX64 cbExtCtx=%#x method=%d\n", fFlags, cb, pExtCtx->enmMethod);
2879
2880 /* Allocate guarded exectuable and data memory. */
2881 if (BS3_MODE_IS_PAGED(bMode))
2882 {
2883#if ARCH_BITS != 16
2884 pThis->pbCodePg = Bs3MemGuardedTestPageAlloc(enmMemKind);
2885 pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
2886 if (!pThis->pbCodePg || !pThis->pbDataPg)
2887 {
2888 Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
2889 Bs3MemPrintInfo();
2890 Bs3Shutdown();
2891 return Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
2892 }
2893 if ( BS3_MODE_IS_64BIT_CODE(bMode)
2894 && (uintptr_t)pThis->pbDataPg >= _2G)
2895 return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
2896#else
2897 return Bs3TestFailed("WTF?! #1");
2898#endif
2899 }
2900 else
2901 {
2902 pThis->pbCodePg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
2903 pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
2904 if (!pThis->pbCodePg || !pThis->pbDataPg)
2905 {
2906 Bs3MemPrintInfo();
2907 return Bs3TestFailedF("Bs3MemAlloc(%d,Pg) failed", enmMemKind);
2908 }
2909 }
2910 pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
2911 pThis->uDataPgFlat = Bs3SelPtrToFlat(pThis->pbDataPg);
2912#if ARCH_BITS == 16
2913 pThis->CodePgFar.sel = BS3_FP_SEG(pThis->pbCodePg);
2914 pThis->CodePgFar.off = BS3_FP_OFF(pThis->pbCodePg);
2915 pThis->CodePgRip = BS3_FP_OFF(pThis->pbCodePg);
2916 pThis->DataPgFar.sel = BS3_FP_SEG(pThis->pbDataPg);
2917 pThis->DataPgFar.off = BS3_FP_OFF(pThis->pbDataPg);
2918#else
2919 if (BS3_MODE_IS_RM_OR_V86(bMode))
2920 {
2921 *(uint32_t *)&pThis->DataPgFar = Bs3SelFlatDataToRealMode(pThis->uDataPgFlat);
2922 ASMCompilerBarrier();
2923 pThis->CodePgFar.off = 0;
2924 pThis->CodePgFar.sel = pThis->uCodePgFlat >> 4;
2925 pThis->CodePgRip = pThis->CodePgFar.off;
2926 }
2927 else if (BS3_MODE_IS_16BIT_CODE(bMode))
2928 {
2929 *(uint32_t *)&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
2930 ASMCompilerBarrier();
2931 pThis->CodePgFar.sel = BS3_SEL_SPARE_00;
2932 pThis->CodePgFar.off = 0;
2933 pThis->CodePgRip = 0;
2934 }
2935 else if (BS3_MODE_IS_32BIT_CODE(bMode))
2936 {
2937 *(uint32_t *)&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
2938 ASMCompilerBarrier();
2939 pThis->CodePgFar.sel = 0;
2940 pThis->CodePgFar.off = 0;
2941 pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
2942 }
2943 else
2944 {
2945 pThis->DataPgFar.off = 0;
2946 pThis->DataPgFar.sel = 0;
2947 pThis->CodePgFar.off = 0;
2948 pThis->CodePgFar.sel = 0;
2949 pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
2950 }
2951#endif
2952
2953 /*
2954 * Create basic context for each target ring.
2955 *
2956 * In protected 16-bit code we need set up code selectors that can access
2957 * pbCodePg.
2958 *
2959 * In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
2960 * bits set so we can check that the implicit clearing is tested.
2961 */
2962 Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
2963#if ARCH_BITS == 64
2964 pThis->aInitialCtxs[pThis->iFirstRing].rax.u |= UINT64_C(0x0101010100000000);
2965 pThis->aInitialCtxs[pThis->iFirstRing].rbx.u |= UINT64_C(0x0202020200000000);
2966 pThis->aInitialCtxs[pThis->iFirstRing].rcx.u |= UINT64_C(0x0303030300000000);
2967 pThis->aInitialCtxs[pThis->iFirstRing].rdx.u |= UINT64_C(0x0404040400000000);
2968 pThis->aInitialCtxs[pThis->iFirstRing].rbp.u |= UINT64_C(0x0505050500000000);
2969 pThis->aInitialCtxs[pThis->iFirstRing].rdi.u |= UINT64_C(0x0606060600000000);
2970 pThis->aInitialCtxs[pThis->iFirstRing].rsi.u |= UINT64_C(0x0707070700000000);
2971 pThis->aInitialCtxs[pThis->iFirstRing].r8.u |= UINT64_C(0x0808080800000000);
2972 pThis->aInitialCtxs[pThis->iFirstRing].r9.u |= UINT64_C(0x0909090900000000);
2973 pThis->aInitialCtxs[pThis->iFirstRing].r10.u |= UINT64_C(0x1010101000000000);
2974 pThis->aInitialCtxs[pThis->iFirstRing].r11.u |= UINT64_C(0x1111111100000000);
2975 pThis->aInitialCtxs[pThis->iFirstRing].r12.u |= UINT64_C(0x1212121200000000);
2976 pThis->aInitialCtxs[pThis->iFirstRing].r13.u |= UINT64_C(0x1313131300000000);
2977 pThis->aInitialCtxs[pThis->iFirstRing].r14.u |= UINT64_C(0x1414141400000000);
2978 pThis->aInitialCtxs[pThis->iFirstRing].r15.u |= UINT64_C(0x1515151500000000);
2979#endif
2980
2981 if (BS3_MODE_IS_RM_OR_V86(bMode))
2982 {
2983 pThis->aInitialCtxs[pThis->iFirstRing].cs = pThis->CodePgFar.sel;
2984 BS3_ASSERT(pThis->iFirstRing + 1 == pThis->iEndRing);
2985 }
2986 else if (BS3_MODE_IS_16BIT_CODE(bMode))
2987 {
2988#if ARCH_BITS == 16
2989 uintptr_t const uFlatCodePgSeg = Bs3SelPtrToFlat(BS3_FP_MAKE(BS3_FP_SEG(pThis->pbCodePg), 0));
2990#else
2991 uintptr_t const uFlatCodePgSeg = (uintptr_t)pThis->pbCodePg;
2992#endif
2993 for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
2994 {
2995 Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
2996 Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
2997 }
2998 for (iRing = pThis->iFirstRing; iRing < pThis->iEndRing; iRing++)
2999 {
3000 pThis->aInitialCtxs[iRing].cs = BS3_SEL_SPARE_00 + iRing * 8 + iRing;
3001 Bs3SelSetup16BitCode(&Bs3GdteSpare00 + iRing, uFlatCodePgSeg, iRing);
3002 }
3003 }
3004 else
3005 {
3006 Bs3RegCtxSetRipCsFromCurPtr(&pThis->aInitialCtxs[pThis->iFirstRing], (FPFNBS3FAR)pThis->pbCodePg);
3007 for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3008 {
3009 Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3010 Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3011 }
3012 }
3013
3014 /*
3015 * Create an initial extended CPU context.
3016 */
3017 pExtCtx = pThis->pInitialExtCtx;
3018 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
3019 || pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
3020 {
3021 pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL | X86_FCW_PC_64 | X86_FCW_RC_NEAREST;
3022 pExtCtx->Ctx.x87.FSW = 0;
3023 pExtCtx->Ctx.x87.MXCSR = X86_MXSCR_IM | X86_MXSCR_DM | X86_MXSCR_RC_NEAREST;
3024 pExtCtx->Ctx.x87.MXCSR_MASK = 0;
3025 for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
3026 {
3027 pExtCtx->Ctx.x87.aRegs[i].au16[0] = i << 4;
3028 pExtCtx->Ctx.x87.aRegs[i].au16[1] = i << 4;
3029 pExtCtx->Ctx.x87.aRegs[i].au16[2] = i << 4;
3030 pExtCtx->Ctx.x87.aRegs[i].au16[3] = i << 4;
3031 }
3032 for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
3033 {
3034 pExtCtx->Ctx.x87.aXMM[i].au16[0] = i;
3035 pExtCtx->Ctx.x87.aXMM[i].au16[1] = i;
3036 pExtCtx->Ctx.x87.aXMM[i].au16[2] = i;
3037 pExtCtx->Ctx.x87.aXMM[i].au16[3] = i;
3038 pExtCtx->Ctx.x87.aXMM[i].au16[4] = i;
3039 pExtCtx->Ctx.x87.aXMM[i].au16[5] = i;
3040 pExtCtx->Ctx.x87.aXMM[i].au16[6] = i;
3041 pExtCtx->Ctx.x87.aXMM[i].au16[7] = i;
3042 }
3043 if (pExtCtx->fXcr0 & XSAVE_C_YMM)
3044 for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi); i++)
3045 {
3046 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[0] = i << 8;
3047 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[1] = i << 8;
3048 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[2] = i << 8;
3049 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[3] = i << 8;
3050 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[4] = i << 8;
3051 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[5] = i << 8;
3052 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[6] = i << 8;
3053 pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[7] = i << 8;
3054 }
3055
3056 }
3057 //else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_ANCIENT)
3058 else
3059 return Bs3TestFailedF("Unsupported extended CPU context method: %d", pExtCtx->enmMethod);
3060
3061 return true;
3062}
3063
3064
3065static uint8_t BS3_CMN_NM(Bs3Cg1WorkerInner)(PBS3CG1STATE pThis)
3066{
3067 uint8_t iRing;
3068 unsigned iInstr;
3069
3070 /*
3071 * Test the instructions.
3072 */
3073 for (iInstr = 0; iInstr < g_cBs3Cg1Instructions;
3074 iInstr++,
3075 pThis->pchMnemonic += pThis->fAdvanceMnemonic * pThis->cchMnemonic,
3076 pThis->pabOperands += pThis->cOperands,
3077 pThis->pabOpcodes += pThis->cbOpcodes)
3078 {
3079 bool fInvalidInstr = false;
3080 unsigned iCpuSetup;
3081 uint8_t bTestXcptExpected = BS3_MODE_IS_PAGED(pThis->bMode) ? X86_XCPT_PF : X86_XCPT_UD;
3082
3083 /*
3084 * Expand the instruction information into the state.
3085 * Note! 16-bit will switch to a two level test header lookup once we exceed 64KB.
3086 */
3087 PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
3088 pThis->iInstr = iInstr;
3089 pThis->pTestHdr = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
3090 pThis->fFlags = pInstr->fFlags;
3091 pThis->enmEncoding = (BS3CG1ENC)pInstr->enmEncoding;
3092 pThis->enmCpuTest = (BS3CG1CPU)pInstr->enmCpuTest;
3093 pThis->enmPrefixKind = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
3094 pThis->enmXcptType = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
3095 pThis->cchMnemonic = pInstr->cchMnemonic;
3096 if (pThis->fAdvanceMnemonic)
3097 Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
3098 pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
3099 pThis->cOperands = pInstr->cOperands;
3100 pThis->cbOpcodes = pInstr->cbOpcodes;
3101 switch (pThis->cOperands)
3102 {
3103 case 3: pThis->aenmOperands[3] = (BS3CG1OP)pThis->pabOperands[3];
3104 case 2: pThis->aenmOperands[2] = (BS3CG1OP)pThis->pabOperands[2];
3105 case 1: pThis->aenmOperands[1] = (BS3CG1OP)pThis->pabOperands[1];
3106 case 0: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
3107 }
3108
3109 switch (pThis->cbOpcodes)
3110 {
3111 case 3: pThis->abOpcodes[3] = pThis->pabOpcodes[3];
3112 case 2: pThis->abOpcodes[2] = pThis->pabOpcodes[2];
3113 case 1: pThis->abOpcodes[1] = pThis->pabOpcodes[1];
3114 case 0: pThis->abOpcodes[0] = pThis->pabOpcodes[0];
3115 }
3116
3117 /*
3118 * Check if the CPU supports the instruction.
3119 */
3120 if ( !Bs3Cg1CpuSetupFirst(pThis)
3121 || (pThis->fFlags & BS3CG1INSTR_F_UNUSED))
3122 {
3123 fInvalidInstr = true;
3124 bTestXcptExpected = X86_XCPT_UD;
3125 }
3126
3127 for (iCpuSetup = 0;; iCpuSetup++)
3128 {
3129 unsigned iEncoding;
3130 unsigned iEncodingNext;
3131
3132 /*
3133 * Prep the operands and encoding handling.
3134 */
3135 if (!Bs3Cg1EncodePrep(pThis))
3136 break;
3137
3138 /*
3139 * Encode the instruction in various ways and check out the test values.
3140 */
3141 for (iEncoding = 0;; iEncoding = iEncodingNext)
3142 {
3143 /*
3144 * Encode the next instruction variation.
3145 */
3146 iEncodingNext = Bs3Cg1EncodeNext(pThis, iEncoding);
3147 if (iEncodingNext <= iEncoding)
3148 break;
3149 BS3CG1_DPRINTF(("\ndbg: Encoding #%u: cbCurInst=%u: %.*Rhxs\n",
3150 iEncoding, pThis->cbCurInstr, pThis->cbCurInstr, pThis->abCurInstr));
3151
3152 /*
3153 * Do the rings.
3154 */
3155 for (iRing = pThis->iFirstRing + pThis->fSameRingNotOkay; iRing < pThis->iEndRing; iRing++)
3156 {
3157 PCBS3CG1TESTHDR pHdr;
3158
3159 pThis->uCpl = iRing;
3160 BS3CG1_DPRINTF(("dbg: Ring %u\n", iRing));
3161
3162 /*
3163 * Do the tests one by one.
3164 */
3165 pHdr = pThis->pTestHdr;
3166 for (pThis->iTest = 0;; pThis->iTest++)
3167 {
3168 if (Bs3Cg1RunSelector(pThis, pHdr))
3169 {
3170 /* Okay, set up the execution context. */
3171 unsigned offCode;
3172 uint8_t BS3_FAR *pbCode;
3173
3174 Bs3MemCpy(&pThis->Ctx, &pThis->aInitialCtxs[iRing], sizeof(pThis->Ctx));
3175 if (pThis->fWorkExtCtx)
3176 Bs3ExtCtxCopy(pThis->pExtCtx, pThis->pInitialExtCtx);
3177 if (BS3_MODE_IS_PAGED(pThis->bMode))
3178 {
3179 offCode = X86_PAGE_SIZE - pThis->cbCurInstr;
3180 pbCode = &pThis->pbCodePg[offCode];
3181 //if (iEncoding > 0) { pbCode[-1] = 0xf4; offCode--; }
3182 }
3183 else
3184 {
3185 pbCode = pThis->pbCodePg;
3186 pbCode[pThis->cbCurInstr] = 0x0f; /* UD2 */
3187 pbCode[pThis->cbCurInstr + 1] = 0x0b;
3188 offCode = 0;
3189 }
3190 pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3191 Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr);
3192
3193 if (Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr, pHdr->cbSelector, pHdr->cbInput, NULL, pbCode))
3194 {
3195 /* Run the instruction. */
3196 BS3CG1_DPRINTF(("dbg: Running test #%u\n", pThis->iTest));
3197 //Bs3RegCtxPrint(&pThis->Ctx);
3198 if (pThis->fWorkExtCtx)
3199 Bs3ExtCtxRestore(pThis->pExtCtx);
3200 Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3201 if (pThis->fWorkExtCtx)
3202 Bs3ExtCtxSave(pThis->pResultExtCtx);
3203 BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64\n",
3204 pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3205
3206 /*
3207 * Apply the output modification program to the context.
3208 */
3209 pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3210 pThis->Ctx.rflags.u32 |= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3211 pThis->bValueXcpt = UINT8_MAX;
3212 if ( fInvalidInstr
3213 || pThis->bAlignmentXcpt != UINT8_MAX
3214 || pThis->bValueXcpt != UINT8_MAX
3215 || Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr,
3216 pHdr->cbSelector + pHdr->cbInput, pHdr->cbOutput,
3217 &pThis->TrapFrame.Ctx, NULL /*pbCode*/))
3218 {
3219 Bs3Cg1CheckResult(pThis, fInvalidInstr, bTestXcptExpected, iEncoding);
3220 }
3221 }
3222 }
3223 else
3224 BS3CG1_DPRINTF(("dbg: Skipping #%u\n", pThis->iTest));
3225
3226 /* advance */
3227 if (pHdr->fLast)
3228 {
3229 BS3CG1_DPRINTF(("dbg: Last\n\n"));
3230 break;
3231 }
3232 pHdr = (PCBS3CG1TESTHDR)((uint8_t BS3_FAR *)(pHdr + 1) + pHdr->cbInput + pHdr->cbOutput + pHdr->cbSelector);
3233 }
3234 }
3235 }
3236
3237 /*
3238 * Clean up (segment registers, etc) and get the next CPU config.
3239 */
3240 Bs3Cg1EncodeCleanup(pThis);
3241 if (!Bs3Cg1CpuSetupNext(pThis, iCpuSetup, &fInvalidInstr))
3242 break;
3243 if (pThis->fFlags & BS3CG1INSTR_F_UNUSED)
3244 fInvalidInstr = true;
3245 if (fInvalidInstr)
3246 bTestXcptExpected = X86_XCPT_UD;
3247 }
3248 }
3249
3250 return 0;
3251}
3252
3253
3254BS3_DECL_FAR(uint8_t) BS3_CMN_NM(Bs3Cg1Worker)(uint8_t bMode)
3255{
3256 uint8_t bRet = 1;
3257 BS3CG1STATE This;
3258
3259#if 0
3260 /* (for debugging) */
3261 if (!BS3_MODE_IS_RM_OR_V86(bMode))
3262 return BS3TESTDOMODE_SKIPPED;
3263#endif
3264
3265 if (BS3_CMN_NM(Bs3Cg1Init)(&This, bMode))
3266 {
3267 bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
3268 Bs3TestSubDone();
3269 }
3270 Bs3Cg1Destroy(&This);
3271
3272#if 0
3273 /* (for debugging) */
3274 if (bMode >= BS3_MODE_RM)
3275 {
3276 Bs3TestTerm();
3277 Bs3Shutdown();
3278 }
3279#endif
3280 return bRet;
3281}
3282
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