bs3-cpu-generated-1-template.c@ 66331

Last change on this file since 66331 was 66331, checked in by vboxsync, 8 years ago
IEM: Converted iemOp_Grp15 from switch to tables; implemented clflushopt Mb (66 0f ae /7).
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1	/* $Id: bs3-cpu-generated-1-template.c 66331 2017-03-29 11:36:49Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	#ifndef BS3_INSTANTIATING_CMN
28	# error "BS3_INSTANTIATING_CMN not defined"
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Header Files *
34	*********************************************************************************************************************************/
35	#include <iprt/asm.h>
36	#include <iprt/asm-amd64-x86.h>
37
38	#include "bs3-cpu-generated-1.h"
39
40
41	/*********************************************************************************************************************************
42	* Defined Constants And Macros *
43	*********************************************************************************************************************************/
44	#define P_CS X86_OP_PRF_CS
45	#define P_SS X86_OP_PRF_SS
46	#define P_DS X86_OP_PRF_DS
47	#define P_ES X86_OP_PRF_ES
48	#define P_FS X86_OP_PRF_FS
49	#define P_GS X86_OP_PRF_GS
50	#define P_OZ X86_OP_PRF_SIZE_OP
51	#define P_AZ X86_OP_PRF_SIZE_ADDR
52	#define P_LK X86_OP_PRF_LOCK
53	#define P_RN X86_OP_PRF_REPNZ
54	#define P_RZ X86_OP_PRF_REPZ
55
56	#define REX_WRBX (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
57	#define REX_W___ (X86_OP_REX_W)
58	#define REX_WR__ (X86_OP_REX_W \| X86_OP_REX_R)
59	#define REX_W_B_ (X86_OP_REX_W \| X86_OP_REX_B)
60	#define REX_W__X (X86_OP_REX_W \| X86_OP_REX_X)
61	#define REX_WRB_ (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B)
62	#define REX_WR_X (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_X)
63	#define REX_W_BX (X86_OP_REX_W \| X86_OP_REX_B \| X86_OP_REX_X)
64	#define REX__R__ (X86_OP_REX_R)
65	#define REX__RB_ (X86_OP_REX_R \| X86_OP_REX_B)
66	#define REX__R_X (X86_OP_REX_R \| X86_OP_REX_X)
67	#define REX__RBX (X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
68	#define REX___B_ (X86_OP_REX_B)
69	#define REX___BX (X86_OP_REX_B \| X86_OP_REX_X)
70	#define REX____X (X86_OP_REX_X)
71	#define REX_____ (0x40)
72
73
74	/** @def BS3CG1_DPRINTF
75	* Debug print macro.
76	*/
77	#if 0
78	# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
79	# define BS3CG1_DEBUG_CTX_MOD
80	#else
81	# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
82	#endif
83
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/** Operand value location. */
90	typedef enum BS3CG1OPLOC
91	{
92	BS3CG1OPLOC_INVALID = 0,
93	BS3CG1OPLOC_CTX,
94	BS3CG1OPLOC_IMM,
95	BS3CG1OPLOC_MEM,
96	BS3CG1OPLOC_MEM_RW,
97	BS3CG1OPLOC_END
98	} BS3CG1OPLOC;
99
100	/**
101	* The state.
102	*/
103	typedef struct BS3CG1STATE
104	{
105	/** @name Instruction details (expanded from BS3CG1INSTR).
106	* @{ */
107	/** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
108	const char BS3_FAR *pchMnemonic;
109	/** Pointer to the test header. */
110	PCBS3CG1TESTHDR pTestHdr;
111	/** Pointer to the per operand flags (g_abBs3Cg1Operands). */
112	const uint8_t BS3_FAR *pabOperands;
113	/** Opcode bytes (g_abBs3Cg1Opcodes). */
114	const uint8_t BS3_FAR *pabOpcodes;
115	/** The current instruction number in the input array (for error reporting). */
116	uint32_t iInstr;
117
118	/** The instruction flags. */
119	uint32_t fFlags;
120	/** The encoding. */
121	BS3CG1ENC enmEncoding;
122	/** The CPU test / CPU ID. */
123	BS3CG1CPU enmCpuTest;
124	/** Prefix sensitivity and requirements. */
125	BS3CG1PFXKIND enmPrefixKind;
126	/** Exception type (SSE, AVX). */
127	BS3CG1XCPTTYPE enmXcptType;
128	/** Per operand flags. */
129	BS3CG1OP aenmOperands[4];
130	/** Opcode bytes. */
131	uint8_t abOpcodes[4];
132
133	/** The length of the mnemonic. */
134	uint8_t cchMnemonic;
135	/** Whether to advance the mnemonic pointer or not. */
136	uint8_t fAdvanceMnemonic;
137	/** The number of opcode bytes. */
138	uint8_t cbOpcodes;
139	/** Number of operands. */
140	uint8_t cOperands;
141	/** @} */
142
143	/** Operand size in bytes (0 if not applicable). */
144	uint8_t cbOperand;
145	/** Current target ring (0..3). */
146	uint8_t uCpl;
147
148	/** The current test number. */
149	uint8_t iTest;
150
151	/** Target mode (g_bBs3CurrentMode). */
152	uint8_t bMode;
153	/** First ring being tested. */
154	uint8_t iFirstRing;
155	/** End of rings being tested. */
156	uint8_t iEndRing;
157
158
159	/** @name Current encoded instruction.
160	* @{ */
161	/** The size of the current instruction that we're testing. */
162	uint8_t cbCurInstr;
163	/** The size the prefixes. */
164	uint8_t cbCurPrefix;
165	/** The offset into abCurInstr of the immediate. */
166	uint8_t offCurImm;
167	/** Buffer for assembling the current instruction. */
168	uint8_t abCurInstr[24];
169
170	/** Set if the encoding can't be tested in the same ring as this test code.
171	* This is used to deal with encodings modifying SP/ESP/RSP. */
172	bool fSameRingNotOkay;
173	/** Whether to work the extended context too. */
174	bool fWorkExtCtx;
175	/** The aOperands index of the modrm.reg operand (if applicable). */
176	uint8_t iRegOp;
177	/** The aOperands index of the modrm.rm operand (if applicable). */
178	uint8_t iRmOp;
179
180	/** Operands details. */
181	struct
182	{
183	uint8_t cbOp;
184	/** BS3CG1OPLOC_XXX. */
185	uint8_t enmLocation;
186	/** The BS3CG1DST value for this field.
187	* Set to BS3CG1DST_INVALID if memory or immediate. */
188	uint8_t idxField;
189	/** Depends on enmLocation.
190	* - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
191	* - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
192	* - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
193	* - BS3CG1OPLOC_CTX: not used (use idxField instead).
194	*/
195	uint8_t off;
196	} aOperands[4];
197	/** @} */
198
199	/** Page to put code in. When paging is enabled, the page before and after
200	* are marked not-present. */
201	uint8_t BS3_FAR *pbCodePg;
202	/** The flat address corresponding to pbCodePg. */
203	uintptr_t uCodePgFlat;
204	/** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
205	RTFAR16 CodePgFar;
206	/** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
207	uintptr_t CodePgRip;
208
209	/** Page for placing data operands in. When paging is enabled, the page before
210	* and after are marked not-present. */
211	uint8_t BS3_FAR *pbDataPg;
212	/** The flat address corresponding to pbDataPg. */
213	uintptr_t uDataPgFlat;
214	/** The 16-bit address corresponding to pbDataPg. */
215	RTFAR16 DataPgFar;
216
217	/** The name corresponding to bMode. */
218	const char BS3_FAR *pszMode;
219	/** The short name corresponding to bMode. */
220	const char BS3_FAR *pszModeShort;
221
222	/** @name Expected result (modifiable by output program).
223	* @{ */
224	/** The expected exception based on operand values or result.
225	* UINT8_MAX if no special exception expected. */
226	uint8_t bValueXcpt;
227	/** @} */
228	/** Alignment exception expected by the encoder.
229	* UINT8_MAX if no special exception expected. */
230	uint8_t bAlignmentXcpt;
231
232	/** The context we're working on. */
233	BS3REGCTX Ctx;
234	/** The trap context and frame. */
235	BS3TRAPFRAME TrapFrame;
236	/** Initial contexts, one for each ring. */
237	BS3REGCTX aInitialCtxs[4];
238
239	/** The extended context we're working on (input, expected output). */
240	PBS3EXTCTX pExtCtx;
241	/** The extended result context (analoguous to TrapFrame). */
242	PBS3EXTCTX pResultExtCtx;
243	/** The initial extended context. */
244	PBS3EXTCTX pInitialExtCtx;
245
246	/** Memory operand scratch space. */
247	union
248	{
249	uint8_t ab[128];
250	uint16_t au16[128 / sizeof(uint16_t)];
251	uint32_t au32[128 / sizeof(uint32_t)];
252	uint64_t au64[128 / sizeof(uint64_t)];
253	} MemOp;
254
255	/** Array parallel to aInitialCtxs for saving segment registers. */
256	struct
257	{
258	RTSEL ds;
259	} aSavedSegRegs[4];
260
261	} BS3CG1STATE;
262	/** Pointer to the generated test state. */
263	typedef BS3CG1STATE *PBS3CG1STATE;
264
265
266	#define BS3CG1_PF_OZ UINT16_C(0x0001)
267	#define BS3CG1_PF_AZ UINT16_C(0x0002)
268	#define BS3CG1_PF_CS UINT16_C(0x0004)
269	#define BS3CG1_PF_DS UINT16_C(0x0008)
270	#define BS3CG1_PF_ES UINT16_C(0x0010)
271	#define BS3CG1_PF_FS UINT16_C(0x0020)
272	#define BS3CG1_PF_GS UINT16_C(0x0040)
273	#define BS3CG1_PF_SS UINT16_C(0x0080)
274	#define BS3CG1_PF_SEGS (BS3CG1_PF_CS \| BS3CG1_PF_DS \| BS3CG1_PF_ES \| BS3CG1_PF_FS \| BS3CG1_PF_GS \| BS3CG1_PF_SS)
275	#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS \| BS3CG1_PF_AZ)
276	#define BS3CG1_PF_LK UINT16_C(0x0100)
277	#define BS3CG1_PF_RN UINT16_C(0x0200)
278	#define BS3CG1_PF_RZ UINT16_C(0x0400)
279	#define BS3CG1_PF_W UINT16_C(0x0800) /*< REX.W /
280	#define BS3CG1_PF_R UINT16_C(0x1000) /*< REX.R /
281	#define BS3CG1_PF_B UINT16_C(0x2000) /*< REX.B /
282	#define BS3CG1_PF_X UINT16_C(0x4000) /*< REX.X /
283
284
285	/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
286	#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
287	/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
288	* the field size (2, 4, or 8). */
289	#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
290
291
292
293	/*********************************************************************************************************************************
294	* Global Variables *
295	*********************************************************************************************************************************/
296	/** Destination field sizes indexed by bBS3CG1DST.
297	* Zero means operand size sized. */
298	static const uint8_t g_acbBs3Cg1DstFields[] =
299	{
300	/* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
301
302	/* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
303	/* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
304	/* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
305	/* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
306	/* [BS3CG1DST_EFL] = */ 4,
307	/* [BS3CG1DST_EFL_UNDEF]=*/ 4,
308
309	/* [BS3CG1DST_AL] = */ 1,
310	/* [BS3CG1DST_CL] = */ 1,
311	/* [BS3CG1DST_DL] = */ 1,
312	/* [BS3CG1DST_BL] = */ 1,
313	/* [BS3CG1DST_AH] = */ 1,
314	/* [BS3CG1DST_CH] = */ 1,
315	/* [BS3CG1DST_DH] = */ 1,
316	/* [BS3CG1DST_BH] = */ 1,
317	/* [BS3CG1DST_SPL] = */ 1,
318	/* [BS3CG1DST_BPL] = */ 1,
319	/* [BS3CG1DST_SIL] = */ 1,
320	/* [BS3CG1DST_DIL] = */ 1,
321	/* [BS3CG1DST_R8L] = */ 1,
322	/* [BS3CG1DST_R9L] = */ 1,
323	/* [BS3CG1DST_R10L] = */ 1,
324	/* [BS3CG1DST_R11L] = */ 1,
325	/* [BS3CG1DST_R12L] = */ 1,
326	/* [BS3CG1DST_R13L] = */ 1,
327	/* [BS3CG1DST_R14L] = */ 1,
328	/* [BS3CG1DST_R15L] = */ 1,
329
330	/* [BS3CG1DST_AX] = */ 2,
331	/* [BS3CG1DST_CX] = */ 2,
332	/* [BS3CG1DST_DX] = */ 2,
333	/* [BS3CG1DST_BX] = */ 2,
334	/* [BS3CG1DST_SP] = */ 2,
335	/* [BS3CG1DST_BP] = */ 2,
336	/* [BS3CG1DST_SI] = */ 2,
337	/* [BS3CG1DST_DI] = */ 2,
338	/* [BS3CG1DST_R8W] = */ 2,
339	/* [BS3CG1DST_R9W] = */ 2,
340	/* [BS3CG1DST_R10W] = */ 2,
341	/* [BS3CG1DST_R11W] = */ 2,
342	/* [BS3CG1DST_R12W] = */ 2,
343	/* [BS3CG1DST_R13W] = */ 2,
344	/* [BS3CG1DST_R14W] = */ 2,
345	/* [BS3CG1DST_R15W] = */ 2,
346
347	/* [BS3CG1DST_EAX] = */ 4,
348	/* [BS3CG1DST_ECX] = */ 4,
349	/* [BS3CG1DST_EDX] = */ 4,
350	/* [BS3CG1DST_EBX] = */ 4,
351	/* [BS3CG1DST_ESP] = */ 4,
352	/* [BS3CG1DST_EBP] = */ 4,
353	/* [BS3CG1DST_ESI] = */ 4,
354	/* [BS3CG1DST_EDI] = */ 4,
355	/* [BS3CG1DST_R8D] = */ 4,
356	/* [BS3CG1DST_R9D] = */ 4,
357	/* [BS3CG1DST_R10D] = */ 4,
358	/* [BS3CG1DST_R11D] = */ 4,
359	/* [BS3CG1DST_R12D] = */ 4,
360	/* [BS3CG1DST_R13D] = */ 4,
361	/* [BS3CG1DST_R14D] = */ 4,
362	/* [BS3CG1DST_R15D] = */ 4,
363
364	/* [BS3CG1DST_RAX] = */ 8,
365	/* [BS3CG1DST_RCX] = */ 8,
366	/* [BS3CG1DST_RDX] = */ 8,
367	/* [BS3CG1DST_RBX] = */ 8,
368	/* [BS3CG1DST_RSP] = */ 8,
369	/* [BS3CG1DST_RBP] = */ 8,
370	/* [BS3CG1DST_RSI] = */ 8,
371	/* [BS3CG1DST_RDI] = */ 8,
372	/* [BS3CG1DST_R8] = */ 8,
373	/* [BS3CG1DST_R9] = */ 8,
374	/* [BS3CG1DST_R10] = */ 8,
375	/* [BS3CG1DST_R11] = */ 8,
376	/* [BS3CG1DST_R12] = */ 8,
377	/* [BS3CG1DST_R13] = */ 8,
378	/* [BS3CG1DST_R14] = */ 8,
379	/* [BS3CG1DST_R15] = */ 8,
380
381	/* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
382	/* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
383	/* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
384	/* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
385	/* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
386	/* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
387	/* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
388	/* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
389	/* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
390	/* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
391	/* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
392	/* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
393	/* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
394	/* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
395	/* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
396	/* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
397
398	/* [BS3CG1DST_FCW] = */ 2,
399	/* [BS3CG1DST_FSW] = */ 2,
400	/* [BS3CG1DST_FTW] = */ 2,
401	/* [BS3CG1DST_FOP] = */ 2,
402	/* [BS3CG1DST_FPUIP] = */ 2,
403	/* [BS3CG1DST_FPUCS] = */ 2,
404	/* [BS3CG1DST_FPUDP] = */ 2,
405	/* [BS3CG1DST_FPUDS] = */ 2,
406	/* [BS3CG1DST_MXCSR] = */ 4,
407	/* [BS3CG1DST_MXCSR_MASK] = */ 4,
408	/* [BS3CG1DST_ST0] = */ 12,
409	/* [BS3CG1DST_ST1] = */ 12,
410	/* [BS3CG1DST_ST2] = */ 12,
411	/* [BS3CG1DST_ST3] = */ 12,
412	/* [BS3CG1DST_ST4] = */ 12,
413	/* [BS3CG1DST_ST5] = */ 12,
414	/* [BS3CG1DST_ST6] = */ 12,
415	/* [BS3CG1DST_ST7] = */ 12,
416	/* [BS3CG1DST_MM0] = */ 8,
417	/* [BS3CG1DST_MM1] = */ 8,
418	/* [BS3CG1DST_MM2] = */ 8,
419	/* [BS3CG1DST_MM3] = */ 8,
420	/* [BS3CG1DST_MM4] = */ 8,
421	/* [BS3CG1DST_MM5] = */ 8,
422	/* [BS3CG1DST_MM6] = */ 8,
423	/* [BS3CG1DST_MM7] = */ 8,
424	/* [BS3CG1DST_XMM0] = */ 16,
425	/* [BS3CG1DST_XMM1] = */ 16,
426	/* [BS3CG1DST_XMM2] = */ 16,
427	/* [BS3CG1DST_XMM3] = */ 16,
428	/* [BS3CG1DST_XMM4] = */ 16,
429	/* [BS3CG1DST_XMM5] = */ 16,
430	/* [BS3CG1DST_XMM6] = */ 16,
431	/* [BS3CG1DST_XMM7] = */ 16,
432	/* [BS3CG1DST_XMM8] = */ 16,
433	/* [BS3CG1DST_XMM9] = */ 16,
434	/* [BS3CG1DST_XMM10] = */ 16,
435	/* [BS3CG1DST_XMM11] = */ 16,
436	/* [BS3CG1DST_XMM12] = */ 16,
437	/* [BS3CG1DST_XMM13] = */ 16,
438	/* [BS3CG1DST_XMM14] = */ 16,
439	/* [BS3CG1DST_XMM15] = */ 16,
440	/* [BS3CG1DST_XMM0_LO] = */ 8,
441	/* [BS3CG1DST_XMM1_LO] = */ 8,
442	/* [BS3CG1DST_XMM2_LO] = */ 8,
443	/* [BS3CG1DST_XMM3_LO] = */ 8,
444	/* [BS3CG1DST_XMM4_LO] = */ 8,
445	/* [BS3CG1DST_XMM5_LO] = */ 8,
446	/* [BS3CG1DST_XMM6_LO] = */ 8,
447	/* [BS3CG1DST_XMM7_LO] = */ 8,
448	/* [BS3CG1DST_XMM8_LO] = */ 8,
449	/* [BS3CG1DST_XMM9_LO] = */ 8,
450	/* [BS3CG1DST_XMM10_LO] = */ 8,
451	/* [BS3CG1DST_XMM11_LO] = */ 8,
452	/* [BS3CG1DST_XMM12_LO] = */ 8,
453	/* [BS3CG1DST_XMM13_LO] = */ 8,
454	/* [BS3CG1DST_XMM14_LO] = */ 8,
455	/* [BS3CG1DST_XMM15_LO] = */ 8,
456	/* [BS3CG1DST_XMM0_HI] = */ 8,
457	/* [BS3CG1DST_XMM1_HI] = */ 8,
458	/* [BS3CG1DST_XMM2_HI] = */ 8,
459	/* [BS3CG1DST_XMM3_HI] = */ 8,
460	/* [BS3CG1DST_XMM4_HI] = */ 8,
461	/* [BS3CG1DST_XMM5_HI] = */ 8,
462	/* [BS3CG1DST_XMM6_HI] = */ 8,
463	/* [BS3CG1DST_XMM7_HI] = */ 8,
464	/* [BS3CG1DST_XMM8_HI] = */ 8,
465	/* [BS3CG1DST_XMM9_HI] = */ 8,
466	/* [BS3CG1DST_XMM10_HI] = */ 8,
467	/* [BS3CG1DST_XMM11_HI] = */ 8,
468	/* [BS3CG1DST_XMM12_HI] = */ 8,
469	/* [BS3CG1DST_XMM13_HI] = */ 8,
470	/* [BS3CG1DST_XMM14_HI] = */ 8,
471	/* [BS3CG1DST_XMM15_HI] = */ 8,
472	/* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
473	/* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
474	/* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
475	/* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
476	/* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
477	/* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
478	/* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
479	/* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
480	/* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
481	/* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
482	/* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
483	/* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
484	/* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
485	/* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
486	/* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
487	/* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
488	/* [BS3CG1DST_XMM0_DW0] = */ 4,
489	/* [BS3CG1DST_XMM1_DW0] = */ 4,
490	/* [BS3CG1DST_XMM2_DW0] = */ 4,
491	/* [BS3CG1DST_XMM3_DW0] = */ 4,
492	/* [BS3CG1DST_XMM4_DW0] = */ 4,
493	/* [BS3CG1DST_XMM5_DW0] = */ 4,
494	/* [BS3CG1DST_XMM6_DW0] = */ 4,
495	/* [BS3CG1DST_XMM7_DW0] = */ 4,
496	/* [BS3CG1DST_XMM8_DW0] = */ 4,
497	/* [BS3CG1DST_XMM9_DW0] = */ 4,
498	/* [BS3CG1DST_XMM10_DW0] = */ 4,
499	/* [BS3CG1DST_XMM11_DW0] = */ 4,
500	/* [BS3CG1DST_XMM12_DW0] = */ 4,
501	/* [BS3CG1DST_XMM13_DW0] = */ 4,
502	/* [BS3CG1DST_XMM14_DW0] = */ 4,
503	/* [BS3CG1DST_XMM15_DW0] = */ 4,
504	/* [BS3CG1DST_YMM0] = */ 32,
505	/* [BS3CG1DST_YMM1] = */ 32,
506	/* [BS3CG1DST_YMM2] = */ 32,
507	/* [BS3CG1DST_YMM3] = */ 32,
508	/* [BS3CG1DST_YMM4] = */ 32,
509	/* [BS3CG1DST_YMM5] = */ 32,
510	/* [BS3CG1DST_YMM6] = */ 32,
511	/* [BS3CG1DST_YMM7] = */ 32,
512	/* [BS3CG1DST_YMM8] = */ 32,
513	/* [BS3CG1DST_YMM9] = */ 32,
514	/* [BS3CG1DST_YMM10] = */ 32,
515	/* [BS3CG1DST_YMM11] = */ 32,
516	/* [BS3CG1DST_YMM12] = */ 32,
517	/* [BS3CG1DST_YMM13] = */ 32,
518	/* [BS3CG1DST_YMM14] = */ 32,
519	/* [BS3CG1DST_YMM15] = */ 32,
520
521	/* [BS3CG1DST_VALUE_XCPT] = */ 1,
522	};
523	AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
524
525	/** Destination field offset indexed by bBS3CG1DST.
526	* Zero means operand size sized. */
527	static const unsigned g_aoffBs3Cg1DstFields[] =
528	{
529	/* [BS3CG1DST_INVALID] = */ ~0U,
530	/* [BS3CG1DST_OP1] = */ ~0U,
531	/* [BS3CG1DST_OP2] = */ ~0U,
532	/* [BS3CG1DST_OP3] = */ ~0U,
533	/* [BS3CG1DST_OP4] = */ ~0U,
534	/* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
535	/* [BS3CG1DST_EFL_UNDEF]=/ ~0, / special field */
536
537	/* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
538	/* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
539	/* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
540	/* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
541	/* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
542	/* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
543	/* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
544	/* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
545	/* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
546	/* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
547	/* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
548	/* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
549	/* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
550	/* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
551	/* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
552	/* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
553	/* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
554	/* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
555	/* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
556	/* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
557
558	/* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
559	/* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
560	/* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
561	/* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
562	/* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
563	/* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
564	/* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
565	/* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
566	/* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
567	/* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
568	/* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
569	/* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
570	/* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
571	/* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
572	/* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
573	/* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
574
575	/* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
576	/* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
577	/* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
578	/* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
579	/* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
580	/* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
581	/* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
582	/* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
583	/* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
584	/* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
585	/* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
586	/* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
587	/* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
588	/* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
589	/* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
590	/* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
591
592	/* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
593	/* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
594	/* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
595	/* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
596	/* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
597	/* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
598	/* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
599	/* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
600	/* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
601	/* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
602	/* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
603	/* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
604	/* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
605	/* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
606	/* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
607	/* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
608
609	/* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
610	/* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
611	/* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
612	/* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
613	/* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
614	/* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
615	/* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
616	/* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
617	/* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
618	/* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
619	/* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
620	/* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
621	/* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
622	/* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
623	/* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
624	/* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
625
626	/* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
627	/* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
628	/* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
629	/* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
630	/* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
631	/* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
632	/* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
633	/* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
634	/* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
635	/* [BS3CG1DST_MXCSR_MASK] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR_MASK),
636	/* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
637	/* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
638	/* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
639	/* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
640	/* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
641	/* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
642	/* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
643	/* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
644	/* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
645	/* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
646	/* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
647	/* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
648	/* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
649	/* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
650	/* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
651	/* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
652
653	/* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
654	/* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
655	/* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
656	/* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
657	/* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
658	/* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
659	/* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
660	/* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
661	/* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
662	/* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
663	/* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
664	/* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
665	/* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
666	/* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
667	/* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
668	/* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
669	/* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
670	/* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
671	/* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
672	/* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
673	/* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
674	/* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
675	/* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
676	/* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
677	/* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
678	/* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
679	/* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
680	/* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
681	/* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
682	/* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
683	/* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
684	/* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
685	/* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
686	/* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
687	/* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
688	/* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
689	/* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
690	/* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
691	/* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
692	/* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
693	/* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
694	/* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
695	/* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
696	/* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
697	/* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
698	/* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
699	/* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
700	/* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
701	/* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
702	/* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
703	/* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
704	/* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
705	/* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
706	/* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
707	/* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
708	/* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
709	/* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
710	/* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
711	/* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
712	/* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
713	/* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
714	/* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
715	/* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
716	/* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
717	/* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
718	/* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
719	/* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
720	/* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
721	/* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
722	/* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
723	/* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
724	/* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
725	/* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
726	/* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
727	/* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
728	/* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
729	/* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
730	/* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
731	/* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
732	/* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
733
734	/* [BS3CG1DST_YMM0] = */ ~0U,
735	/* [BS3CG1DST_YMM1] = */ ~0U,
736	/* [BS3CG1DST_YMM2] = */ ~0U,
737	/* [BS3CG1DST_YMM3] = */ ~0U,
738	/* [BS3CG1DST_YMM4] = */ ~0U,
739	/* [BS3CG1DST_YMM5] = */ ~0U,
740	/* [BS3CG1DST_YMM6] = */ ~0U,
741	/* [BS3CG1DST_YMM7] = */ ~0U,
742	/* [BS3CG1DST_YMM8] = */ ~0U,
743	/* [BS3CG1DST_YMM9] = */ ~0U,
744	/* [BS3CG1DST_YMM10] = */ ~0U,
745	/* [BS3CG1DST_YMM11] = */ ~0U,
746	/* [BS3CG1DST_YMM12] = */ ~0U,
747	/* [BS3CG1DST_YMM13] = */ ~0U,
748	/* [BS3CG1DST_YMM14] = */ ~0U,
749	/* [BS3CG1DST_YMM15] = */ ~0U,
750
751	/* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
752	};
753	AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
754
755	#ifdef BS3CG1_DEBUG_CTX_MOD
756	/** Destination field names. */
757	static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
758	{
759	{ "INVALID" },
760	{ "OP1" },
761	{ "OP2" },
762	{ "OP3" },
763	{ "OP4" },
764	{ "EFL" },
765	{ "EFL_UND" },
766
767	{ "AL" },
768	{ "CL" },
769	{ "DL" },
770	{ "BL" },
771	{ "AH" },
772	{ "CH" },
773	{ "DH" },
774	{ "BH" },
775	{ "SPL" },
776	{ "BPL" },
777	{ "SIL" },
778	{ "DIL" },
779	{ "R8L" },
780	{ "R9L" },
781	{ "R10L" },
782	{ "R11L" },
783	{ "R12L" },
784	{ "R13L" },
785	{ "R14L" },
786	{ "R15L" },
787
788	{ "AX" },
789	{ "CX" },
790	{ "DX" },
791	{ "BX" },
792	{ "SP" },
793	{ "BP" },
794	{ "SI" },
795	{ "DI" },
796	{ "R8W" },
797	{ "R9W" },
798	{ "R10W" },
799	{ "R11W" },
800	{ "R12W" },
801	{ "R13W" },
802	{ "R14W" },
803	{ "R15W" },
804
805	{ "EAX" },
806	{ "ECX" },
807	{ "EDX" },
808	{ "EBX" },
809	{ "ESP" },
810	{ "EBP" },
811	{ "ESI" },
812	{ "EDI" },
813	{ "R8D" },
814	{ "R9D" },
815	{ "R10D" },
816	{ "R11D" },
817	{ "R12D" },
818	{ "R13D" },
819	{ "R14D" },
820	{ "R15D" },
821
822	{ "RAX" },
823	{ "RCX" },
824	{ "RDX" },
825	{ "RBX" },
826	{ "RSP" },
827	{ "RBP" },
828	{ "RSI" },
829	{ "RDI" },
830	{ "R8" },
831	{ "R9" },
832	{ "R10" },
833	{ "R11" },
834	{ "R12" },
835	{ "R13" },
836	{ "R14" },
837	{ "R15" },
838
839	{ "OZ_RAX" },
840	{ "OZ_RCX" },
841	{ "OZ_RDX" },
842	{ "OZ_RBX" },
843	{ "OZ_RSP" },
844	{ "OZ_RBP" },
845	{ "OZ_RSI" },
846	{ "OZ_RDI" },
847	{ "OZ_R8" },
848	{ "OZ_R9" },
849	{ "OZ_R10" },
850	{ "OZ_R11" },
851	{ "OZ_R12" },
852	{ "OZ_R13" },
853	{ "OZ_R14" },
854	{ "OZ_R15" },
855
856	{ "FCW" },
857	{ "FSW" },
858	{ "FTW" },
859	{ "FOP" },
860	{ "FPUIP" },
861	{ "FPUCS" },
862	{ "FPUDP" },
863	{ "FPUDS" },
864	{ "MXCSR" },
865	{ "MXCSR_M" },
866	{ "ST0" },
867	{ "ST1" },
868	{ "ST2" },
869	{ "ST3" },
870	{ "ST4" },
871	{ "ST5" },
872	{ "ST6" },
873	{ "ST7" },
874	{ "MM0" },
875	{ "MM1" },
876	{ "MM2" },
877	{ "MM3" },
878	{ "MM4" },
879	{ "MM5" },
880	{ "MM6" },
881	{ "MM7" },
882	{ "XMM0" },
883	{ "XMM1" },
884	{ "XMM2" },
885	{ "XMM3" },
886	{ "XMM4" },
887	{ "XMM5" },
888	{ "XMM6" },
889	{ "XMM7" },
890	{ "XMM8" },
891	{ "XMM9" },
892	{ "XMM10" },
893	{ "XMM11" },
894	{ "XMM12" },
895	{ "XMM13" },
896	{ "XMM14" },
897	{ "XMM15" },
898	{ "XMM0_LO" },
899	{ "XMM1_LO" },
900	{ "XMM2_LO" },
901	{ "XMM3_LO" },
902	{ "XMM4_LO" },
903	{ "XMM5_LO" },
904	{ "XMM6_LO" },
905	{ "XMM7_LO" },
906	{ "XMM8_LO" },
907	{ "XMM9_LO" },
908	{ "XMM10_LO" },
909	{ "XMM11_LO" },
910	{ "XMM12_LO" },
911	{ "XMM13_LO" },
912	{ "XMM14_LO" },
913	{ "XMM15_LO" },
914	{ "XMM0_HI" },
915	{ "XMM1_HI" },
916	{ "XMM2_HI" },
917	{ "XMM3_HI" },
918	{ "XMM4_HI" },
919	{ "XMM5_HI" },
920	{ "XMM6_HI" },
921	{ "XMM7_HI" },
922	{ "XMM8_HI" },
923	{ "XMM9_HI" },
924	{ "XMM10_HI" },
925	{ "XMM11_HI" },
926	{ "XMM12_HI" },
927	{ "XMM13_HI" },
928	{ "XMM14_HI" },
929	{ "XMM15_HI" },
930	{ "XMM0_LO_ZX" },
931	{ "XMM1_LO_ZX" },
932	{ "XMM2_LO_ZX" },
933	{ "XMM3_LO_ZX" },
934	{ "XMM4_LO_ZX" },
935	{ "XMM5_LO_ZX" },
936	{ "XMM6_LO_ZX" },
937	{ "XMM7_LO_ZX" },
938	{ "XMM8_LO_ZX" },
939	{ "XMM9_LO_ZX" },
940	{ "XMM10_LO_ZX" },
941	{ "XMM11_LO_ZX" },
942	{ "XMM12_LO_ZX" },
943	{ "XMM13_LO_ZX" },
944	{ "XMM14_LO_ZX" },
945	{ "XMM15_LO_ZX" },
946	{ "XMM0_DW0" },
947	{ "XMM1_DW0" },
948	{ "XMM2_DW0" },
949	{ "XMM3_DW0" },
950	{ "XMM4_DW0" },
951	{ "XMM5_DW0" },
952	{ "XMM6_DW0" },
953	{ "XMM7_DW0" },
954	{ "XMM8_DW0" },
955	{ "XMM9_DW0" },
956	{ "XMM10_DW0" },
957	{ "XMM11_DW0" },
958	{ "XMM12_DW0" },
959	{ "XMM13_DW0" },
960	{ "XMM14_DW0" },
961	{ "XMM15_DW0" },
962	{ "YMM0" },
963	{ "YMM1" },
964	{ "YMM2" },
965	{ "YMM3" },
966	{ "YMM4" },
967	{ "YMM5" },
968	{ "YMM6" },
969	{ "YMM7" },
970	{ "YMM8" },
971	{ "YMM9" },
972	{ "YMM10" },
973	{ "YMM11" },
974	{ "YMM12" },
975	{ "YMM13" },
976	{ "YMM14" },
977	{ "YMM15" },
978
979	{ "VALXCPT" },
980	};
981	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
982
983	#endif
984
985	#if 0
986	static const struct
987	{
988	uint8_t cbPrefixes;
989	uint8_t abPrefixes[14];
990	uint16_t fEffective;
991	} g_aPrefixVariations[] =
992	{
993	{ 0, { 0x00 }, BS3CG1_PF_NONE },
994
995	{ 1, { P_OZ }, BS3CG1_PF_OZ },
996	{ 1, { P_CS }, BS3CG1_PF_CS },
997	{ 1, { P_DS }, BS3CG1_PF_DS },
998	{ 1, { P_ES }, BS3CG1_PF_ES },
999	{ 1, { P_FS }, BS3CG1_PF_FS },
1000	{ 1, { P_GS }, BS3CG1_PF_GS },
1001	{ 1, { P_SS }, BS3CG1_PF_SS },
1002	{ 1, { P_LK }, BS3CG1_PF_LK },
1003
1004	{ 2, { P_CS, P_OZ, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1005	{ 2, { P_DS, P_OZ, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1006	{ 2, { P_ES, P_OZ, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1007	{ 2, { P_FS, P_OZ, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1008	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1009	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1010	{ 2, { P_SS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1011
1012	{ 2, { P_OZ, P_CS, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1013	{ 2, { P_OZ, P_DS, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1014	{ 2, { P_OZ, P_ES, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1015	{ 2, { P_OZ, P_FS, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1016	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1017	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1018	{ 2, { P_OZ, P_SS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1019	};
1020
1021	static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1022	{
1023	/* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1024	/* [BS3CG1PFXKIND_MODRM] = */ 0,
1025	/* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ \| BS3CG1_PF_W,
1026	};
1027
1028	#endif
1029
1030
1031	/**
1032	* Checks if >= 16 byte SSE/AVX alignment are exempted for the exception type.
1033	*
1034	* @returns true / false.
1035	* @param enmXcptType The type to check.
1036	*/
1037	static bool Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1038	{
1039	switch (enmXcptType)
1040	{
1041	case BS3CG1XCPTTYPE_4UA:
1042	case BS3CG1XCPTTYPE_5:
1043	return true;
1044	default:
1045	return false;
1046	}
1047	}
1048
1049
1050	DECLINLINE(unsigned) Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1051	{
1052	switch (pThis->enmPrefixKind)
1053	{
1054	case BS3CG1PFXKIND_REQ_66:
1055	pThis->abCurInstr[offDst] = 0x66;
1056	break;
1057	case BS3CG1PFXKIND_REQ_F2:
1058	pThis->abCurInstr[offDst] = 0xf2;
1059	break;
1060	case BS3CG1PFXKIND_REQ_F3:
1061	pThis->abCurInstr[offDst] = 0xf3;
1062	break;
1063	default:
1064	return offDst;
1065	}
1066	return offDst + 1;
1067	}
1068
1069
1070	DECLINLINE(unsigned) Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1071	{
1072	switch (pThis->cbOpcodes)
1073	{
1074	case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1075	case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1076	case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1077	case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1078	return offDst + pThis->cbOpcodes;
1079
1080	default:
1081	BS3_ASSERT(0);
1082	return 0;
1083	}
1084	}
1085
1086
1087	/**
1088	* Cleans up state and context changes made by the encoder.
1089	*
1090	* @param pThis The state.
1091	*/
1092	static void Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1093	{
1094	/* Restore the DS registers in the contexts. */
1095	unsigned iRing = 4;
1096	while (iRing-- > 0)
1097	pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1098
1099	switch (pThis->enmEncoding)
1100	{
1101	/* Most encodings currently doesn't need any special cleaning up. */
1102	default:
1103	return;
1104	}
1105	}
1106
1107
1108	static unsigned Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1109	uint8_t cbOp, uint8_t cbMissalign, BS3CG1OPLOC enmLocation)
1110	{
1111	pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1112	pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1113	pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1114	pThis->aOperands[pThis->iRmOp].off = cbOp + cbMissalign;
1115
1116	if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1117	\|\| (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1118	{
1119	/*
1120	* 16-bit code doing 16-bit or 32-bit addressing,
1121	* or 32-bit code doing 16-bit addressing.
1122	*/
1123	unsigned iRing = 4;
1124	if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1125	while (iRing-- > 0)
1126	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1127	else
1128	while (iRing-- > 0)
1129	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel \| iRing;
1130	if (!fAddrOverride \|\| BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1131	{
1132	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /disp16/);
1133	(uint16_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1134	off += 2;
1135	}
1136	else
1137	{
1138	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1139	(uint32_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1140	off += 4;
1141	}
1142	}
1143	else
1144	{
1145	/*
1146	* 32-bit code doing 32-bit addressing,
1147	* or 64-bit code doing either 64-bit or 32-bit addressing.
1148	*/
1149	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1150	(uint32_t )&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMissalign;
1151
1152	/* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1153	if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1154	(uint32_t )&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1155	off += 4;
1156	}
1157
1158	/*
1159	* Fill the memory with 0xcc.
1160	*/
1161	switch (cbOp + cbMissalign)
1162	{
1163	case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; /* fall thru */
1164	case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; /* fall thru */
1165	case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; /* fall thru */
1166	case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; /* fall thru */
1167	case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; /* fall thru */
1168	case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; /* fall thru */
1169	case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; /* fall thru */
1170	case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; /* fall thru */
1171	case 0: break;
1172	default:
1173	Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign);
1174	break;
1175	}
1176
1177	return off;
1178	}
1179
1180
1181	/**
1182	* Encodes the next instruction.
1183	*
1184	* @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
1185	* that there are no more encodings to test.
1186	* @param pThis The state.
1187	* @param iEncoding The encoding to produce. Meaning is specific to each
1188	* BS3CG1ENC_XXX value and should be considered internal.
1189	*/
1190	static unsigned Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
1191	{
1192	unsigned off;
1193	unsigned cbOp;
1194
1195	pThis->bAlignmentXcpt = UINT8_MAX;
1196
1197	switch (pThis->enmEncoding)
1198	{
1199	case BS3CG1ENC_MODRM_Eb_Gb:
1200	/* Start by reg,reg encoding. */
1201	if (iEncoding == 0)
1202	{
1203	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1204	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1205	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1206	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1207	}
1208	else if (iEncoding == 1)
1209	{
1210	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1211	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1212	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM_RW);
1213	}
1214	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1215	{
1216	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1217	pThis->abCurInstr[0] = P_AZ;
1218	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1219	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM_RW);
1220	}
1221	else
1222	break;
1223	pThis->cbCurInstr = off;
1224	iEncoding++;
1225	break;
1226
1227	case BS3CG1ENC_MODRM_Gb_Eb:
1228	/* Start by reg,reg encoding. */
1229	if (iEncoding == 0)
1230	{
1231	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1232	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1233	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1234	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1235	}
1236	else if (iEncoding == 1)
1237	{
1238	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1239	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1240	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM);
1241	}
1242	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1243	{
1244	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1245	pThis->abCurInstr[0] = P_AZ;
1246	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1247	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM);
1248	}
1249	else
1250	break;
1251	pThis->cbCurInstr = off;
1252	iEncoding++;
1253	break;
1254
1255	case BS3CG1ENC_MODRM_Gv_Ev:
1256	case BS3CG1ENC_MODRM_Ev_Gv:
1257	if (iEncoding == 0)
1258	{
1259	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1260	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1261	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1262	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1263	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1264	}
1265	else if (iEncoding == 1)
1266	{
1267	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1268	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1269	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1270	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp, 0,
1271	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1272	}
1273	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1274	{
1275	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1276	pThis->abCurInstr[0] = P_OZ;
1277	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1278	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1279	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1280	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1281	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1282	}
1283	else if (iEncoding == 3)
1284	{
1285	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1286	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1287	pThis->abCurInstr[0] = P_OZ;
1288	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1289	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xSI, cbOp, 0,
1290	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1291	}
1292	else if (iEncoding == 4)
1293	{
1294	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1295	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RDI;
1296	pThis->abCurInstr[0] = P_AZ;
1297	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1298	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, cbOp, 0,
1299	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1300	}
1301	else if (iEncoding == 5)
1302	{
1303	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1304	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1305	pThis->abCurInstr[0] = P_OZ;
1306	pThis->abCurInstr[1] = P_AZ;
1307	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1308	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xSI, cbOp, 0,
1309	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1310	}
1311	else if (iEncoding == 6 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1312	{
1313	cbOp = 8;
1314	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1315	pThis->abCurInstr[off++] = REX_W___;
1316	off = Bs3Cg1InsertOpcodes(pThis, off);
1317	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1318	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_RBX;
1319	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_RDX;
1320	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1321	}
1322	else
1323	break;
1324	pThis->aOperands[0].cbOp = cbOp;
1325	pThis->aOperands[1].cbOp = cbOp;
1326	pThis->cbOperand = cbOp;
1327	pThis->cbCurInstr = off;
1328	iEncoding++;
1329	break;
1330
1331	case BS3CG1ENC_MODRM_Wss_Vss:
1332	if (iEncoding == 0)
1333	{
1334	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1335	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1336	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_DW0;
1337	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0;
1338	}
1339	else if (iEncoding == 1)
1340	{
1341	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0;
1342	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1343	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 4, 0, BS3CG1OPLOC_MEM_RW);
1344	}
1345	else if (iEncoding == 2)
1346	{
1347	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0;
1348	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1349	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 4, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1350	}
1351	else
1352	break;
1353	pThis->cbCurInstr = off;
1354	iEncoding++;
1355	break;
1356
1357	case BS3CG1ENC_MODRM_Wsd_Vsd:
1358	if (iEncoding == 0)
1359	{
1360	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1361	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1362	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1363	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1364	}
1365	else if (iEncoding == 1)
1366	{
1367	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1368	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1369	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1370	}
1371	else if (iEncoding == 2)
1372	{
1373	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1374	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1375	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1376	}
1377	else
1378	break;
1379	pThis->cbCurInstr = off;
1380	iEncoding++;
1381	break;
1382
1383	case BS3CG1ENC_MODRM_Wps_Vps:
1384	case BS3CG1ENC_MODRM_Wpd_Vpd:
1385	if (iEncoding == 0)
1386	{
1387	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1388	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1389	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1390	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1391	}
1392	else if (iEncoding == 1)
1393	{
1394	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1395	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1396	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM_RW);
1397	}
1398	else if (iEncoding == 2)
1399	{
1400	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1401	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1402	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1403	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1404	pThis->bAlignmentXcpt = X86_XCPT_GP;
1405	}
1406	else
1407	break;
1408	pThis->cbCurInstr = off;
1409	iEncoding++;
1410	break;
1411
1412	case BS3CG1ENC_MODRM_WqZxReg_Vq:
1413	if (iEncoding == 0)
1414	{
1415	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1416	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1417	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO_ZX;
1418	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1419	}
1420	else if (iEncoding == 1)
1421	{
1422	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1423	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1424	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1425	}
1426	else if (iEncoding == 2)
1427	{
1428	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1429	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1430	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1431	}
1432	else
1433	break;
1434	pThis->cbCurInstr = off;
1435	iEncoding++;
1436	break;
1437
1438	case BS3CG1ENC_MODRM_Vq_UqHi:
1439	if (iEncoding == 0)
1440	{
1441	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1442	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1443	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_HI;
1444	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1445	}
1446	else if (iEncoding == 1)
1447	{
1448	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1449	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 2);
1450	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM2_HI;
1451	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1452	}
1453	else
1454	break;
1455	pThis->cbCurInstr = off;
1456	iEncoding++;
1457	break;
1458
1459	case BS3CG1ENC_MODRM_Vq_Mq:
1460	if (iEncoding == 0)
1461	{
1462	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1463	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1464	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM);
1465	}
1466	else if (iEncoding == 1)
1467	{
1468	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1469	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1470	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1471	}
1472	else
1473	break;
1474	pThis->cbCurInstr = off;
1475	iEncoding++;
1476	break;
1477
1478	case BS3CG1ENC_MODRM_Vdq_Wdq:
1479	if (iEncoding == 0)
1480	{
1481	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1482	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1483	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1484	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1485	}
1486	else if (iEncoding == 1)
1487	{
1488	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1489	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1490	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM);
1491	}
1492	else if (iEncoding == 2)
1493	{
1494	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1495	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1496	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1497	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1498	pThis->bAlignmentXcpt = X86_XCPT_GP;
1499	}
1500	else
1501	break;
1502	pThis->cbCurInstr = off;
1503	iEncoding++;
1504	break;
1505
1506	case BS3CG1ENC_MODRM_Gv_Ma:
1507	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1508	if (iEncoding == 0)
1509	{
1510	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1511	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1512	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1513	}
1514	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1515	{
1516	cbOp = cbOp == 2 ? 4 : 2;
1517	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1518	pThis->abCurInstr[0] = P_OZ;
1519	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1520	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1521	}
1522	else if (iEncoding == 2)
1523	{
1524	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1525	pThis->abCurInstr[0] = P_AZ;
1526	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1527	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1528	}
1529	else if (iEncoding == 3)
1530	{
1531	cbOp = cbOp == 2 ? 4 : 2;
1532	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1533	pThis->abCurInstr[0] = P_AZ;
1534	pThis->abCurInstr[1] = P_OZ;
1535	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1536	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1537	}
1538	else
1539	break;
1540	pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
1541	pThis->cbOperand = cbOp;
1542	pThis->cbCurInstr = off;
1543	iEncoding++;
1544	break;
1545
1546	case BS3CG1ENC_MODRM_MbRO:
1547	if (iEncoding == 0)
1548	{
1549	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1550	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1551	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1552	1, 0, BS3CG1OPLOC_MEM);
1553	}
1554	else
1555	break;
1556	pThis->cbCurInstr = off;
1557	iEncoding++;
1558	break;
1559
1560
1561	case BS3CG1ENC_FIXED:
1562	if (iEncoding == 0)
1563	{
1564	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1565	pThis->cbCurInstr = off;
1566	iEncoding++;
1567	}
1568	break;
1569
1570	case BS3CG1ENC_FIXED_AL_Ib:
1571	if (iEncoding == 0)
1572	{
1573	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1574	pThis->aOperands[1].off = (uint8_t)off;
1575	pThis->abCurInstr[off++] = 0xff;
1576	pThis->cbCurInstr = off;
1577	iEncoding++;
1578	}
1579	break;
1580
1581	case BS3CG1ENC_FIXED_rAX_Iz:
1582	if (iEncoding == 0)
1583	{
1584	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1585	pThis->aOperands[1].off = (uint8_t)off;
1586	if (BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1587	{
1588	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
1589	off += 2;
1590	pThis->aOperands[0].cbOp = 2;
1591	pThis->aOperands[1].cbOp = 2;
1592	pThis->cbOperand = 2;
1593	}
1594	else
1595	{
1596	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
1597	off += 4;
1598	pThis->aOperands[0].cbOp = 4;
1599	pThis->aOperands[1].cbOp = 4;
1600	pThis->cbOperand = 4;
1601	}
1602	}
1603	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1604	{
1605	pThis->abCurInstr[0] = P_OZ;
1606	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1607	pThis->aOperands[1].off = (uint8_t)off;
1608	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1609	{
1610	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
1611	off += 2;
1612	pThis->aOperands[0].cbOp = 2;
1613	pThis->aOperands[1].cbOp = 2;
1614	pThis->cbOperand = 2;
1615	}
1616	else
1617	{
1618	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
1619	off += 4;
1620	pThis->aOperands[0].cbOp = 4;
1621	pThis->aOperands[1].cbOp = 4;
1622	pThis->cbOperand = 4;
1623	}
1624	}
1625	else if (iEncoding == 2 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1626	{
1627	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1628	pThis->abCurInstr[off++] = REX_W___;
1629	off = Bs3Cg1InsertOpcodes(pThis, off);
1630	pThis->aOperands[1].off = (uint8_t)off;
1631	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
1632	off += 4;
1633	pThis->aOperands[0].cbOp = 8;
1634	pThis->aOperands[1].cbOp = 4;
1635	pThis->cbOperand = 8;
1636	}
1637	else
1638	break;
1639	pThis->cbCurInstr = off;
1640	iEncoding++;
1641	break;
1642
1643	case BS3CG1ENC_MODRM_MOD_EQ_3:
1644	if (iEncoding < 8)
1645	{
1646	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1647	off = Bs3Cg1InsertOpcodes(pThis, off);
1648	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
1649	}
1650	else if (iEncoding < 16)
1651	{
1652	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1653	off = Bs3Cg1InsertOpcodes(pThis, off);
1654	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding);
1655	}
1656	else
1657	break;
1658	pThis->cbCurInstr = off;
1659	iEncoding++;
1660	break;
1661
1662	case BS3CG1ENC_MODRM_MOD_NE_3:
1663	if (iEncoding < 3)
1664	{
1665	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1666	off = Bs3Cg1InsertOpcodes(pThis, off);
1667	pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
1668	if (iEncoding >= 1)
1669	pThis->abCurInstr[off++] = 0x7f;
1670	if (iEncoding == 2)
1671	{
1672	pThis->abCurInstr[off++] = 0x5f;
1673	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1674	{
1675	pThis->abCurInstr[off++] = 0x3f;
1676	pThis->abCurInstr[off++] = 0x1f;
1677	}
1678	}
1679	}
1680	else
1681	break;
1682	pThis->cbCurInstr = off;
1683	iEncoding++;
1684	break;
1685
1686	default:
1687	Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
1688	break;
1689	}
1690
1691
1692	return iEncoding;
1693	}
1694
1695
1696	/**
1697	* Prepares doing instruction encodings.
1698	*
1699	* This is in part specific to how the instruction is encoded, but generally it
1700	* sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
1701	* is called from within the loop.
1702	*
1703	* @returns Success indicator (true/false).
1704	* @param pThis The state.
1705	*/
1706	static bool Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
1707	{
1708	unsigned iRing = 4;
1709	while (iRing-- > 0)
1710	pThis->aSavedSegRegs[iRing].ds = pThis->aInitialCtxs[iRing].ds;
1711
1712	pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
1713	pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
1714	pThis->fSameRingNotOkay = false;
1715	pThis->cbOperand = 0;
1716
1717	switch (pThis->enmEncoding)
1718	{
1719	case BS3CG1ENC_MODRM_Eb_Gb:
1720	pThis->iRmOp = 0;
1721	pThis->iRegOp = 1;
1722	pThis->aOperands[0].cbOp = 1;
1723	pThis->aOperands[1].cbOp = 1;
1724	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1725	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1726	break;
1727
1728	case BS3CG1ENC_MODRM_Ev_Gv:
1729	pThis->iRmOp = 0;
1730	pThis->iRegOp = 1;
1731	pThis->cbOperand = 2;
1732	pThis->aOperands[0].cbOp = 2;
1733	pThis->aOperands[1].cbOp = 2;
1734	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1735	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1736	break;
1737
1738	case BS3CG1ENC_MODRM_Gb_Eb:
1739	pThis->iRmOp = 1;
1740	pThis->iRegOp = 0;
1741	pThis->aOperands[0].cbOp = 1;
1742	pThis->aOperands[1].cbOp = 1;
1743	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1744	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1745	break;
1746
1747	case BS3CG1ENC_MODRM_Gv_Ev:
1748	pThis->iRmOp = 1;
1749	pThis->iRegOp = 0;
1750	pThis->cbOperand = 2;
1751	pThis->aOperands[0].cbOp = 2;
1752	pThis->aOperands[1].cbOp = 2;
1753	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1754	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1755	break;
1756
1757	case BS3CG1ENC_MODRM_Gv_Ma:
1758	pThis->iRmOp = 1;
1759	pThis->iRegOp = 0;
1760	pThis->cbOperand = 2;
1761	pThis->aOperands[0].cbOp = 2;
1762	pThis->aOperands[1].cbOp = 4;
1763	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1764	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
1765	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1766	break;
1767
1768	case BS3CG1ENC_MODRM_Wss_Vss:
1769	pThis->iRmOp = 0;
1770	pThis->iRegOp = 1;
1771	pThis->aOperands[0].cbOp = 4;
1772	pThis->aOperands[1].cbOp = 4;
1773	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1774	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1775	break;
1776
1777	case BS3CG1ENC_MODRM_Wsd_Vsd:
1778	case BS3CG1ENC_MODRM_WqZxReg_Vq:
1779	pThis->iRmOp = 0;
1780	pThis->iRegOp = 1;
1781	pThis->aOperands[0].cbOp = 8;
1782	pThis->aOperands[1].cbOp = 8;
1783	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1784	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1785	break;
1786
1787	case BS3CG1ENC_MODRM_Wps_Vps:
1788	case BS3CG1ENC_MODRM_Wpd_Vpd:
1789	pThis->iRmOp = 0;
1790	pThis->iRegOp = 1;
1791	pThis->aOperands[0].cbOp = 16;
1792	pThis->aOperands[1].cbOp = 16;
1793	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1794	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1795	break;
1796
1797	case BS3CG1ENC_MODRM_Vdq_Wdq:
1798	pThis->iRmOp = 1;
1799	pThis->iRegOp = 0;
1800	pThis->aOperands[0].cbOp = 16;
1801	pThis->aOperands[1].cbOp = 16;
1802	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1803	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1804	break;
1805
1806	case BS3CG1ENC_MODRM_Vq_UqHi:
1807	pThis->iRmOp = 1;
1808	pThis->iRegOp = 0;
1809	pThis->aOperands[0].cbOp = 8;
1810	pThis->aOperands[1].cbOp = 8;
1811	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1812	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
1813	break;
1814
1815	case BS3CG1ENC_MODRM_Vq_Mq:
1816	pThis->iRmOp = 1;
1817	pThis->iRegOp = 0;
1818	pThis->aOperands[0].cbOp = 8;
1819	pThis->aOperands[1].cbOp = 8;
1820	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1821	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
1822	break;
1823
1824	case BS3CG1ENC_MODRM_MbRO:
1825	pThis->iRmOp = 0;
1826	pThis->aOperands[0].cbOp = 1;
1827	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
1828	break;
1829
1830	case BS3CG1ENC_FIXED:
1831	/* nothing to do here */
1832	break;
1833
1834	case BS3CG1ENC_FIXED_AL_Ib:
1835	pThis->aOperands[0].cbOp = 1;
1836	pThis->aOperands[1].cbOp = 1;
1837	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1838	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
1839	pThis->aOperands[0].idxField = BS3CG1DST_AL;
1840	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1841	break;
1842
1843	case BS3CG1ENC_FIXED_rAX_Iz:
1844	pThis->aOperands[0].cbOp = 2;
1845	pThis->aOperands[1].cbOp = 2;
1846	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
1847	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
1848	pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
1849	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
1850	break;
1851
1852	case BS3CG1ENC_MODRM_MOD_EQ_3:
1853	case BS3CG1ENC_MODRM_MOD_NE_3:
1854	/* Unused or invalid instructions mostly. */
1855	break;
1856
1857	default:
1858	return Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
1859	pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
1860	}
1861	return true;
1862	}
1863
1864
1865	/**
1866	* Sets up SSE and maybe AVX.
1867	*
1868	* @returns true (if successful, false if not and the SSE instructions ends up
1869	* being invalid).
1870	* @param pThis The state.
1871	*/
1872	static bool Bs3Cg3SetupSseAndAvx(PBS3CG1STATE pThis)
1873	{
1874	if (!pThis->fWorkExtCtx)
1875	{
1876	unsigned i;
1877	uint32_t cr0 = ASMGetCR0();
1878	uint32_t cr4 = ASMGetCR4();
1879
1880	cr0 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
1881	cr0 \|= X86_CR0_NE;
1882	ASMSetCR0(cr0);
1883	if (pThis->pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
1884	{
1885	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE;
1886	ASMSetCR4(cr4);
1887	ASMSetXcr0(pThis->pExtCtx->fXcr0);
1888	}
1889	else
1890	{
1891	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT;
1892	ASMSetCR4(cr4);
1893	}
1894
1895	for (i = 0; i < RT_ELEMENTS(pThis->aInitialCtxs); i++)
1896	{
1897	pThis->aInitialCtxs[i].cr0.u32 = cr0;
1898	pThis->aInitialCtxs[i].cr4.u32 = cr4;
1899	}
1900	pThis->fWorkExtCtx = true;
1901	}
1902
1903	return true;
1904	}
1905
1906
1907	/**
1908	* Next CPU configuration to test the current instruction in.
1909	*
1910	* This is for testing FPU, SSE and AVX instructions with the various lazy state
1911	* load and enable bits in different configurations to ensure we're getting the
1912	* right response.
1913	*
1914	* This also cleans up the CPU and test driver state.
1915	*
1916	* @returns true if we're to do another round, false if we're done.
1917	* @param pThis The state.
1918	* @param iCpuSetup The current CPU setup number.
1919	* @param pfInvalidInstr Where to indicate whether the setup causes an
1920	* invalid instruction or not. This is also used as
1921	* input to avoid unnecessary CPUID work.
1922	*/
1923	static bool Bs3Cg1CpuSetupNext(PBS3CG1STATE pThis, unsigned iCpuSetup, bool *pfInvalidInstr)
1924	{
1925	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
1926	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1927	return false;
1928
1929	switch (pThis->enmCpuTest)
1930	{
1931	case BS3CG1CPU_ANY:
1932	case BS3CG1CPU_GE_80186:
1933	case BS3CG1CPU_GE_80286:
1934	case BS3CG1CPU_GE_80386:
1935	case BS3CG1CPU_GE_80486:
1936	case BS3CG1CPU_GE_Pentium:
1937	case BS3CG1CPU_CLFSH:
1938	case BS3CG1CPU_CLFLUSHOPT:
1939	return false;
1940
1941	case BS3CG1CPU_SSE:
1942	case BS3CG1CPU_SSE2:
1943	case BS3CG1CPU_SSE3:
1944	case BS3CG1CPU_AVX:
1945	case BS3CG1CPU_AVX2:
1946	if (iCpuSetup > 0 \|\| *pfInvalidInstr)
1947	{
1948	/** @todo do more configs here. */
1949	pThis->fWorkExtCtx = false;
1950	ASMSetCR0(ASMGetCR0() \| X86_CR0_EM \| X86_CR0_MP);
1951	ASMSetCR4(ASMGetCR4() & ~(X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE));
1952	return false;
1953	}
1954	return false;
1955
1956	default:
1957	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
1958	return false;
1959	}
1960	}
1961
1962
1963	/**
1964	* Check if the instruction is supported by the CPU, possibly making state
1965	* adjustments to enable support for it.
1966	*
1967	* @returns true if supported, false if not.
1968	* @param pThis The state.
1969	*/
1970	static bool Bs3Cg1CpuSetupFirst(PBS3CG1STATE pThis)
1971	{
1972	uint32_t fEax;
1973	uint32_t fEbx;
1974	uint32_t fEcx;
1975	uint32_t fEdx;
1976
1977	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
1978	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1979	return false;
1980
1981	switch (pThis->enmCpuTest)
1982	{
1983	case BS3CG1CPU_ANY:
1984	return true;
1985
1986	case BS3CG1CPU_GE_80186:
1987	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80186)
1988	return true;
1989	return false;
1990
1991	case BS3CG1CPU_GE_80286:
1992	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286)
1993	return true;
1994	return false;
1995
1996	case BS3CG1CPU_GE_80386:
1997	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1998	return true;
1999	return false;
2000
2001	case BS3CG1CPU_GE_80486:
2002	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
2003	return true;
2004	return false;
2005
2006	case BS3CG1CPU_GE_Pentium:
2007	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_Pentium)
2008	return true;
2009	return false;
2010
2011	case BS3CG1CPU_SSE:
2012	case BS3CG1CPU_SSE2:
2013	case BS3CG1CPU_SSE3:
2014	case BS3CG1CPU_AVX:
2015	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2016	{
2017	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
2018	switch (pThis->enmCpuTest)
2019	{
2020	case BS3CG1CPU_SSE:
2021	if (fEdx & X86_CPUID_FEATURE_EDX_SSE)
2022	return Bs3Cg3SetupSseAndAvx(pThis);
2023	return false;
2024	case BS3CG1CPU_SSE2:
2025	if (fEdx & X86_CPUID_FEATURE_EDX_SSE2)
2026	return Bs3Cg3SetupSseAndAvx(pThis);
2027	return false;
2028	case BS3CG1CPU_SSE3:
2029	if (fEcx & X86_CPUID_FEATURE_ECX_SSE3)
2030	return Bs3Cg3SetupSseAndAvx(pThis);
2031	return false;
2032	case BS3CG1CPU_AVX:
2033	if (fEcx & X86_CPUID_FEATURE_ECX_AVX)
2034	return Bs3Cg3SetupSseAndAvx(pThis);
2035	return false;
2036	default: BS3_ASSERT(0); /* impossible */
2037	}
2038	}
2039	return false;
2040
2041	case BS3CG1CPU_AVX2:
2042	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2043	{
2044	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, &fEax, &fEbx, &fEcx, &fEdx);
2045	switch (pThis->enmCpuTest)
2046	{
2047	case BS3CG1CPU_AVX2:
2048	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2)
2049	return Bs3Cg3SetupSseAndAvx(pThis);
2050	return false;
2051	default: BS3_ASSERT(0); return false; /* impossible */
2052	}
2053	}
2054	return false;
2055
2056	case BS3CG1CPU_CLFSH:
2057	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2058	{
2059	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
2060	if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
2061	return true;
2062	}
2063	return false;
2064
2065	case BS3CG1CPU_CLFLUSHOPT:
2066	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2067	{
2068	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, NULL, &fEbx, NULL, NULL);
2069	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
2070	return true;
2071	}
2072	return false;
2073
2074	default:
2075	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2076	return false;
2077	}
2078	}
2079
2080
2081
2082	/**
2083	* Checks the preconditions for a test.
2084	*
2085	* @returns true if the test be executed, false if not.
2086	* @param pThis The state.
2087	* @param pHdr The test header.
2088	*/
2089	static bool Bs3Cg1RunSelector(PBS3CG1STATE pThis, PCBS3CG1TESTHDR pHdr)
2090	{
2091
2092	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1);
2093	unsigned cbLeft = pHdr->cbSelector;
2094	while (cbLeft-- > 0)
2095	{
2096	switch (*pbCode++)
2097	{
2098	#define CASE_PRED(a_Pred, a_Expr) \
2099	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_TRUE: \
2100	if (!(a_Expr)) return false; \
2101	break; \
2102	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_FALSE: \
2103	if (a_Expr) return false; \
2104	break
2105	CASE_PRED(BS3CG1PRED_SIZE_O16, pThis->cbOperand == 2);
2106	CASE_PRED(BS3CG1PRED_SIZE_O32, pThis->cbOperand == 4);
2107	CASE_PRED(BS3CG1PRED_SIZE_O64, pThis->cbOperand == 8);
2108	CASE_PRED(BS3CG1PRED_RING_0, pThis->uCpl == 0);
2109	CASE_PRED(BS3CG1PRED_RING_1, pThis->uCpl == 1);
2110	CASE_PRED(BS3CG1PRED_RING_2, pThis->uCpl == 2);
2111	CASE_PRED(BS3CG1PRED_RING_3, pThis->uCpl == 3);
2112	CASE_PRED(BS3CG1PRED_RING_0_THRU_2, pThis->uCpl <= 2);
2113	CASE_PRED(BS3CG1PRED_RING_1_THRU_3, pThis->uCpl >= 1);
2114	CASE_PRED(BS3CG1PRED_CODE_64BIT, BS3_MODE_IS_64BIT_CODE(pThis->bMode));
2115	CASE_PRED(BS3CG1PRED_CODE_32BIT, BS3_MODE_IS_32BIT_CODE(pThis->bMode));
2116	CASE_PRED(BS3CG1PRED_CODE_16BIT, BS3_MODE_IS_16BIT_CODE(pThis->bMode));
2117	CASE_PRED(BS3CG1PRED_MODE_REAL, BS3_MODE_IS_RM_SYS(pThis->bMode));
2118	CASE_PRED(BS3CG1PRED_MODE_PROT, BS3_MODE_IS_PM_SYS(pThis->bMode));
2119	CASE_PRED(BS3CG1PRED_MODE_LONG, BS3_MODE_IS_64BIT_SYS(pThis->bMode));
2120	CASE_PRED(BS3CG1PRED_MODE_SMM, false);
2121	CASE_PRED(BS3CG1PRED_MODE_VMX, false);
2122	CASE_PRED(BS3CG1PRED_MODE_SVM, false);
2123	CASE_PRED(BS3CG1PRED_PAGING_ON, BS3_MODE_IS_PAGED(pThis->bMode));
2124	CASE_PRED(BS3CG1PRED_PAGING_OFF, !BS3_MODE_IS_PAGED(pThis->bMode));
2125
2126	#undef CASE_PRED
2127	default:
2128	return Bs3TestFailedF("Invalid selector opcode %#x!", pbCode[-1]);
2129	}
2130	}
2131
2132	return true;
2133	}
2134
2135
2136	#ifdef BS3CG1_DEBUG_CTX_MOD
2137	/**
2138	* Translates the operator into a string.
2139	*
2140	* @returns Read-only string pointer.
2141	* @param bOpcode The context modifier program opcode.
2142	*/
2143	static const char BS3_FAR *Bs3Cg1CtxOpToString(uint8_t bOpcode)
2144	{
2145	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2146	{
2147	case BS3CG1_CTXOP_ASSIGN: return "=";
2148	case BS3CG1_CTXOP_OR: return "\|=";
2149	case BS3CG1_CTXOP_AND: return "&=";
2150	case BS3CG1_CTXOP_AND_INV: return "&~=";
2151	}
2152	}
2153	#endif
2154
2155
2156	/**
2157	* Runs a context modifier program.
2158	*
2159	* @returns Success indicator (true/false).
2160	* @param pThis The state.
2161	* @param pCtx The context.
2162	* @param pHdr The program header.
2163	* @param off The program offset relative to the end of the header.
2164	* @param cb The program size.
2165	* @param pEflCtx The context to take undefined EFLAGS from. (This is NULL
2166	* if we're processing a input context modifier program.)
2167	* @param pbInstr Points to the first instruction byte. For storing
2168	* immediate operands during input context modification.
2169	* NULL for output contexts.
2170	*/
2171	static bool Bs3Cg1RunContextModifier(PBS3CG1STATE pThis, PBS3REGCTX pCtx, PCBS3CG1TESTHDR pHdr, unsigned off, unsigned cb,
2172	PCBS3REGCTX pEflCtx, uint8_t BS3_FAR *pbInstr)
2173	{
2174	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1) + off;
2175	int cbLeft = cb;
2176	while (cbLeft-- > 0)
2177	{
2178	/*
2179	* Decode the instruction.
2180	*/
2181	uint8_t const bOpcode = *pbCode++;
2182	unsigned cbValue;
2183	unsigned cbDst;
2184	BS3CG1DST idxField;
2185	BS3PTRUNION PtrField;
2186
2187	/* Expand the destiation field (can be escaped). */
2188	switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
2189	{
2190	case BS3CG1_CTXOP_OP1:
2191	idxField = pThis->aOperands[0].idxField;
2192	if (idxField == BS3CG1DST_INVALID)
2193	idxField = BS3CG1DST_OP1;
2194	break;
2195
2196	case BS3CG1_CTXOP_OP2:
2197	idxField = pThis->aOperands[1].idxField;
2198	if (idxField == BS3CG1DST_INVALID)
2199	idxField = BS3CG1DST_OP2;
2200	break;
2201
2202	case BS3CG1_CTXOP_EFL:
2203	idxField = BS3CG1DST_EFL;
2204	break;
2205
2206	case BS3CG1_CTXOP_DST_ESC:
2207	if (cbLeft-- > 0)
2208	{
2209	idxField = (BS3CG1DST)*pbCode++;
2210	if (idxField <= BS3CG1DST_OP4)
2211	{
2212	if (idxField > BS3CG1DST_INVALID)
2213	{
2214	uint8_t idxField2 = pThis->aOperands[idxField - BS3CG1DST_OP1].idxField;
2215	if (idxField2 != BS3CG1DST_INVALID)
2216	idxField = idxField2;
2217	break;
2218	}
2219	}
2220	else if (idxField < BS3CG1DST_END)
2221	break;
2222	return Bs3TestFailedF("Malformed context instruction: idxField=%d", idxField);
2223	}
2224	/* fall thru */
2225	default:
2226	return Bs3TestFailed("Malformed context instruction: Destination");
2227	}
2228
2229
2230	/* Expand value size (can be escaped). */
2231	switch (bOpcode & BS3CG1_CTXOP_SIZE_MASK)
2232	{
2233	case BS3CG1_CTXOP_1_BYTE: cbValue = 1; break;
2234	case BS3CG1_CTXOP_2_BYTES: cbValue = 2; break;
2235	case BS3CG1_CTXOP_4_BYTES: cbValue = 4; break;
2236	case BS3CG1_CTXOP_8_BYTES: cbValue = 8; break;
2237	case BS3CG1_CTXOP_16_BYTES: cbValue = 16; break;
2238	case BS3CG1_CTXOP_32_BYTES: cbValue = 32; break;
2239	case BS3CG1_CTXOP_12_BYTES: cbValue = 12; break;
2240	case BS3CG1_CTXOP_SIZE_ESC:
2241	if (cbLeft-- > 0)
2242	{
2243	cbValue = *pbCode++;
2244	if (cbValue)
2245	break;
2246	}
2247	/* fall thru */
2248	default:
2249	return Bs3TestFailed("Malformed context instruction: size");
2250	}
2251
2252	/* Make sure there is enough instruction bytes for the value. */
2253	if (cbValue <= cbLeft)
2254	{ /* likely */ }
2255	else
2256	return Bs3TestFailedF("Malformed context instruction: %u bytes value, %u bytes left", cbValue, cbLeft);
2257
2258	/*
2259	* Do value processing specific to the target field size.
2260	*/
2261	cbDst = g_acbBs3Cg1DstFields[idxField];
2262	if (cbDst == BS3CG1DSTSIZE_OPERAND)
2263	cbDst = pThis->aOperands[idxField - BS3CG1DST_OP1].cbOp;
2264	else if (cbDst == BS3CG1DSTSIZE_OPERAND_SIZE_GRP)
2265	cbDst = pThis->cbOperand;
2266	if (cbDst <= 8)
2267	{
2268	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2269
2270	/*
2271	* Deal with fields up to 8-byte wide.
2272	*/
2273	/* Get the value. */
2274	uint64_t uValue;
2275	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT))
2276	switch (cbValue)
2277	{
2278	case 1: uValue = (int8_t const BS3_FAR )pbCode; break;
2279	case 2: uValue = (int16_t const BS3_FAR )pbCode; break;
2280	case 4: uValue = (int32_t const BS3_FAR )pbCode; break;
2281	default:
2282	if (cbValue >= 8)
2283	{
2284	uValue = (uint64_t const BS3_FAR )pbCode;
2285	break;
2286	}
2287	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2288	}
2289	else
2290	switch (cbValue)
2291	{
2292	case 1: uValue = (uint8_t const BS3_FAR )pbCode; break;
2293	case 2: uValue = (uint16_t const BS3_FAR )pbCode; break;
2294	case 4: uValue = (uint32_t const BS3_FAR )pbCode; break;
2295	default:
2296	if (cbValue >= 8)
2297	{
2298	uValue = (uint64_t const BS3_FAR )pbCode;
2299	break;
2300	}
2301	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2302	}
2303
2304	/* Find the field. */
2305	if (offField < sizeof(BS3REGCTX))
2306	PtrField.pu8 = (uint8_t BS3_FAR *)pCtx + offField;
2307	/* Non-register operands: */
2308	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2309	{
2310	unsigned const idxOp = idxField - BS3CG1DST_OP1;
2311
2312	switch (pThis->aOperands[idxOp].enmLocation)
2313	{
2314	case BS3CG1OPLOC_IMM:
2315	if (pbInstr)
2316	PtrField.pu8 = &pbInstr[pThis->aOperands[idxOp].off];
2317	else
2318	return Bs3TestFailedF("Immediate operand referenced in output context!");
2319	break;
2320
2321	case BS3CG1OPLOC_MEM:
2322	if (!pbInstr)
2323	return Bs3TestFailedF("Read only operand specified in output!");
2324	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2325	break;
2326
2327	case BS3CG1OPLOC_MEM_RW:
2328	if (pbInstr)
2329	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2330	else
2331	PtrField.pu8 = pThis->MemOp.ab;
2332	break;
2333
2334	default:
2335	return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
2336	cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
2337	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2338	}
2339	}
2340	/* Special field: Copying in undefined EFLAGS from the result context. */
2341	else if (idxField == BS3CG1DST_EFL_UNDEF)
2342	{
2343	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN)
2344	return Bs3TestFailed("Invalid BS3CG1DST_EFL_UNDEF usage");
2345	PtrField.pu32 = &pCtx->rflags.u32;
2346	uValue = (*PtrField.pu32 & ~(uint32_t)uValue) \| (pEflCtx->rflags.u32 & (uint32_t)uValue);
2347	}
2348	/* Special field: Expected value (in/result) exception. */
2349	else if (idxField == BS3CG1DST_VALUE_XCPT)
2350	{
2351	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN \|\| cbDst != 1)
2352	return Bs3TestFailed("Invalid BS3CG1DST_VALUE_XCPT usage");
2353	PtrField.pu8 = &pThis->bValueXcpt;
2354	}
2355	/* FPU and FXSAVE format. */
2356	else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2357	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2358	{
2359	if (!pThis->fWorkExtCtx)
2360	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2361	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2362	}
2363	/** @todo other FPU fields and FPU state formats. */
2364	else
2365	return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
2366
2367	#ifdef BS3CG1_DEBUG_CTX_MOD
2368	switch (cbDst)
2369	{
2370	case 1:
2371	BS3CG1_DPRINTF(("dbg: modify %s: %#04RX8 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2372	*PtrField.pu8, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2373	break;
2374	case 2:
2375	BS3CG1_DPRINTF(("dbg: modify %s: %#06RX16 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2376	*PtrField.pu16, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2377	break;
2378	case 4:
2379	BS3CG1_DPRINTF(("dbg: modify %s: %#010RX32 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2380	*PtrField.pu32, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2381	break;
2382	default:
2383	BS3CG1_DPRINTF(("dbg: modify %s: %#018RX64 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2384	*PtrField.pu64, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2385	break;
2386	}
2387	#endif
2388
2389	/* Modify the field. */
2390	switch (cbDst)
2391	{
2392	case 1:
2393	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2394	{
2395	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu8 = (uint8_t)uValue; break;
2396	case BS3CG1_CTXOP_OR: *PtrField.pu8 \|= (uint8_t)uValue; break;
2397	case BS3CG1_CTXOP_AND: *PtrField.pu8 &= (uint8_t)uValue; break;
2398	case BS3CG1_CTXOP_AND_INV: *PtrField.pu8 &= ~(uint8_t)uValue; break;
2399	}
2400	break;
2401
2402	case 2:
2403	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2404	{
2405	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu16 = (uint16_t)uValue; break;
2406	case BS3CG1_CTXOP_OR: *PtrField.pu16 \|= (uint16_t)uValue; break;
2407	case BS3CG1_CTXOP_AND: *PtrField.pu16 &= (uint16_t)uValue; break;
2408	case BS3CG1_CTXOP_AND_INV: *PtrField.pu16 &= ~(uint16_t)uValue; break;
2409	}
2410	break;
2411
2412	case 4:
2413	if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
2414	PtrField.pu32[1] = 0;
2415	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2416	{
2417	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu32 = (uint32_t)uValue; break;
2418	case BS3CG1_CTXOP_OR: *PtrField.pu32 \|= (uint32_t)uValue; break;
2419	case BS3CG1_CTXOP_AND: *PtrField.pu32 &= (uint32_t)uValue; break;
2420	case BS3CG1_CTXOP_AND_INV: *PtrField.pu32 &= ~(uint32_t)uValue; break;
2421	}
2422	break;
2423
2424	case 8:
2425	if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
2426	PtrField.pu64[1] = 0;
2427	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2428	{
2429	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu64 = (uint64_t)uValue; break;
2430	case BS3CG1_CTXOP_OR: *PtrField.pu64 \|= (uint64_t)uValue; break;
2431	case BS3CG1_CTXOP_AND: *PtrField.pu64 &= (uint64_t)uValue; break;
2432	case BS3CG1_CTXOP_AND_INV: *PtrField.pu64 &= ~(uint64_t)uValue; break;
2433	}
2434	break;
2435
2436	default:
2437	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, expected 1, 2, 4, or 8", cbDst);
2438	}
2439
2440	#ifdef BS3CG1_DEBUG_CTX_MOD
2441	switch (cbDst)
2442	{
2443	case 1: BS3CG1_DPRINTF(("dbg: --> %s: %#04RX8\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu8)); break;
2444	case 2: BS3CG1_DPRINTF(("dbg: --> %s: %#06RX16\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu16)); break;
2445	case 4: BS3CG1_DPRINTF(("dbg: --> %s: %#010RX32\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu32)); break;
2446	default: BS3CG1_DPRINTF(("dbg: --> %s: %#018RX64\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu64)); break;
2447	}
2448	#endif
2449
2450	}
2451	/*
2452	* Deal with larger field (FPU, SSE, AVX, ...).
2453	*/
2454	else
2455	{
2456	union
2457	{
2458	X86FPUREG FpuReg;
2459	X86XMMREG XmmReg;
2460	X86YMMREG YmmReg;
2461	X86ZMMREG ZmmReg;
2462	uint8_t ab[sizeof(X86ZMMREG)];
2463	uint32_t au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
2464	} Value;
2465	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2466
2467	if (!pThis->fWorkExtCtx)
2468	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2469
2470	/* Copy the value into the union, doing the zero padding / extending. */
2471	Bs3MemCpy(&Value, pbCode, cbValue);
2472	if (cbValue < sizeof(Value))
2473	{
2474	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
2475	Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
2476	else
2477	Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
2478	}
2479
2480	/* Optimized access to XMM and STx registers. */
2481	if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2482	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2483	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2484	/* Non-register operands: */
2485	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2486	{
2487	unsigned const idxOp = idxField - BS3CG1DST_OP1;
2488	switch (pThis->aOperands[idxOp].enmLocation)
2489	{
2490	case BS3CG1OPLOC_MEM:
2491	if (!pbInstr)
2492	return Bs3TestFailedF("Read only operand specified in output!");
2493	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2494	break;
2495
2496	case BS3CG1OPLOC_MEM_RW:
2497	if (pbInstr)
2498	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2499	else
2500	PtrField.pu8 = pThis->MemOp.ab;
2501	break;
2502
2503	default:
2504	return Bs3TestFailedF("Internal error: Field %d (%d) @ %#x LB %u: enmLocation=%u off=%#x idxField=%u",
2505	idxField, idxOp, offField, cbDst, pThis->aOperands[idxOp].enmLocation,
2506	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2507	}
2508	}
2509	/* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
2510	the state, so they need special handling. */
2511	else
2512	{
2513	return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
2514	}
2515
2516	if (PtrField.pb)
2517	{
2518	/* Modify the field / memory. */
2519	unsigned i;
2520	if (cbDst & 3)
2521	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
2522
2523	#ifdef BS3CG1_DEBUG_CTX_MOD
2524	BS3CG1_DPRINTF(("dbg: modify %s: %.Rhxs (LB %u) %s %.Rhxs (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2525	cbDst, PtrField.pb, cbDst, Bs3Cg1CtxOpToString(bOpcode), cbValue, Value.ab, cbValue));
2526	#endif
2527
2528	i = cbDst / 4;
2529	while (i-- > 0)
2530	{
2531	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2532	{
2533	case BS3CG1_CTXOP_ASSIGN: PtrField.pu32[i] = Value.au32[i]; break;
2534	case BS3CG1_CTXOP_OR: PtrField.pu32[i] \|= Value.au32[i]; break;
2535	case BS3CG1_CTXOP_AND: PtrField.pu32[i] &= Value.au32[i]; break;
2536	case BS3CG1_CTXOP_AND_INV: PtrField.pu32[i] &= ~Value.au32[i]; break;
2537	}
2538	}
2539
2540	#ifdef BS3CG1_DEBUG_CTX_MOD
2541	BS3CG1_DPRINTF(("dbg: --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
2542	#endif
2543	}
2544	}
2545
2546	/*
2547	* Advance to the next instruction.
2548	*/
2549	pbCode += cbValue;
2550	cbLeft -= cbValue;
2551	}
2552
2553	return true;
2554	}
2555
2556
2557	/**
2558	* Checks the result of a run.
2559	*
2560	* @returns true if successful, false if not.
2561	* @param pThis The state.
2562	* @param fInvalidInstr Whether this is an invalid instruction.
2563	* @param bTestXcptExpected The exception causing the test code to stop
2564	* executing.
2565	* @param iEncoding For error reporting.
2566	*/
2567	static bool Bs3Cg1CheckResult(PBS3CG1STATE pThis, bool fInvalidInstr, uint8_t bTestXcptExpected, unsigned iEncoding)
2568	{
2569	unsigned iOperand;
2570
2571	/*
2572	* Check the exception state first.
2573	*/
2574	uint8_t bExpectedXcpt;
2575	uint8_t cbAdjustPc;
2576	if (!fInvalidInstr)
2577	{
2578	bExpectedXcpt = pThis->bAlignmentXcpt;
2579	if (bExpectedXcpt == UINT8_MAX)
2580	bExpectedXcpt = pThis->bValueXcpt;
2581	if (bExpectedXcpt == UINT8_MAX)
2582	{
2583	cbAdjustPc = pThis->cbCurInstr;
2584	bExpectedXcpt = bTestXcptExpected;
2585	if (bTestXcptExpected == X86_XCPT_PF)
2586	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
2587	}
2588	else
2589	cbAdjustPc = 0;
2590	}
2591	else
2592	{
2593	cbAdjustPc = 0;
2594	bExpectedXcpt = bTestXcptExpected;
2595	}
2596	if (RT_LIKELY( pThis->TrapFrame.bXcpt == bExpectedXcpt
2597	&& pThis->TrapFrame.Ctx.rip.u == pThis->Ctx.rip.u + cbAdjustPc))
2598	{
2599	/*
2600	* Check the register content.
2601	*/
2602	bool fOkay = Bs3TestCheckRegCtxEx(&pThis->TrapFrame.Ctx, &pThis->Ctx,
2603	cbAdjustPc, 0 /cbSpAdjust/, 0 /fExtraEfl/,
2604	pThis->pszMode, iEncoding);
2605
2606	/*
2607	* Check memory output operands.
2608	*/
2609	iOperand = pThis->cOperands;
2610	while (iOperand-- > 0)
2611	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
2612	{
2613	BS3PTRUNION PtrUnion;
2614	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
2615	switch (pThis->aOperands[iOperand].cbOp)
2616	{
2617	case 1:
2618	if (*PtrUnion.pu8 == pThis->MemOp.ab[0])
2619	continue;
2620	Bs3TestFailedF("op%u: Wrote %#04RX8, expected %#04RX8", iOperand, *PtrUnion.pu8, pThis->MemOp.ab[0]);
2621	break;
2622	case 2:
2623	if (*PtrUnion.pu16 == pThis->MemOp.au16[0])
2624	continue;
2625	Bs3TestFailedF("op%u: Wrote %#06RX16, expected %#06RX16",
2626	iOperand, *PtrUnion.pu16, pThis->MemOp.au16[0]);
2627	break;
2628	case 4:
2629	if (*PtrUnion.pu32 == pThis->MemOp.au32[0])
2630	continue;
2631	Bs3TestFailedF("op%u: Wrote %#010RX32, expected %#010RX32",
2632	iOperand, *PtrUnion.pu32, pThis->MemOp.au32[0]);
2633	break;
2634	case 8:
2635	if (*PtrUnion.pu64 == pThis->MemOp.au64[0])
2636	continue;
2637	Bs3TestFailedF("op%u: Wrote %#018RX64, expected %#018RX64",
2638	iOperand, *PtrUnion.pu64, pThis->MemOp.au64[0]);
2639	break;
2640	default:
2641	if (Bs3MemCmp(PtrUnion.pb, pThis->MemOp.ab, pThis->aOperands[iOperand].cbOp) == 0)
2642	continue;
2643	Bs3TestFailedF("op%u: Wrote %.Rhxs, expected %.Rhxs",
2644	iOperand,
2645	pThis->aOperands[iOperand].cbOp, PtrUnion.pb,
2646	pThis->aOperands[iOperand].cbOp, pThis->MemOp.ab);
2647	break;
2648	}
2649	fOkay = false;
2650	}
2651
2652	/*
2653	* Check extended context if enabled.
2654	*/
2655	if (pThis->fWorkExtCtx)
2656	{
2657	PBS3EXTCTX pExpect = pThis->pExtCtx;
2658	PBS3EXTCTX pResult = pThis->pResultExtCtx;
2659	unsigned i;
2660	if ( pExpect->enmMethod == BS3EXTCTXMETHOD_XSAVE
2661	\|\| pExpect->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
2662	{
2663	/* Compare the x87 state, ASSUMING XCR0 bit 1 is set. */
2664	#define CHECK_FIELD(a_Field, a_szFmt) \
2665	if (pResult->Ctx.a_Field != pExpect->Ctx.a_Field) fOkay = Bs3TestFailedF(a_szFmt, pResult->Ctx.a_Field, pExpect->Ctx.a_Field)
2666	CHECK_FIELD(x87.FCW, "FCW: %#06x, expected %#06x");
2667	CHECK_FIELD(x87.FSW, "FSW: %#06x, expected %#06x");
2668	CHECK_FIELD(x87.FTW, "FTW: %#06x, expected %#06x");
2669	//CHECK_FIELD(x87.FOP, "FOP: %#06x, expected %#06x");
2670	//CHECK_FIELD(x87.FPUIP, "FPUIP: %#010x, expected %#010x");
2671	//CHECK_FIELD(x87.CS, "FPUCS: %#06x, expected %#06x");
2672	//CHECK_FIELD(x87.Rsrvd1, "Rsrvd1: %#06x, expected %#06x");
2673	//CHECK_FIELD(x87.DP, "FPUDP: %#010x, expected %#010x");
2674	//CHECK_FIELD(x87.DS, "FPUDS: %#06x, expected %#06x");
2675	//CHECK_FIELD(x87.Rsrvd2, "Rsrvd2: %#06x, expected %#06x");
2676	CHECK_FIELD(x87.MXCSR, "MXCSR: %#010x, expected %#010x");
2677	//CHECK_FIELD(x87.MXCSR_MASK, "MXCSR_MASK: %#010x, expected %#010x");
2678	#undef CHECK_FIELD
2679	for (i = 0; i < RT_ELEMENTS(pExpect->Ctx.x87.aRegs); i++)
2680	if ( pResult->Ctx.x87.aRegs[i].au64[0] != pExpect->Ctx.x87.aRegs[i].au64[0]
2681	\|\| pResult->Ctx.x87.aRegs[i].au16[4] != pExpect->Ctx.x87.aRegs[i].au16[4])
2682	fOkay = Bs3TestFailedF("ST[%u]: %c m=%#RX64 e=%d, expected %c m=%#RX64 e=%d", i,
2683	pResult->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
2684	pResult->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
2685	pResult->Ctx.x87.aRegs[i].r80Ex.s.uExponent,
2686	pExpect->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
2687	pExpect->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
2688	pExpect->Ctx.x87.aRegs[i].r80Ex.s.uExponent);
2689	for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
2690	if ( pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
2691	\|\| pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
2692	fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%08RX64, expected %#010RX64'%08RX64", i,
2693	pResult->Ctx.x87.aXMM[i].au64[0],
2694	pResult->Ctx.x87.aXMM[i].au64[1],
2695	pExpect->Ctx.x87.aXMM[i].au64[0],
2696	pExpect->Ctx.x87.aXMM[i].au64[1]);
2697	}
2698	else
2699	fOkay = Bs3TestFailedF("Unsupported extended CPU context method: %d", pExpect->enmMethod);
2700	}
2701
2702	/*
2703	* Done.
2704	*/
2705	if (fOkay)
2706	return true;
2707
2708	/*
2709	* Report failure.
2710	*/
2711	Bs3TestFailedF("%RU32[%u]: encoding#%u: %.*Rhxs",
2712	pThis->iInstr, pThis->iTest, iEncoding, pThis->cbCurInstr, pThis->abCurInstr);
2713	}
2714	else
2715	Bs3TestFailedF("%RU32[%u]: bXcpt=%#x expected %#x; rip=%RX64 expected %RX64; encoding#%u: %.*Rhxs",
2716	pThis->iInstr, pThis->iTest,
2717	pThis->TrapFrame.bXcpt, bExpectedXcpt,
2718	pThis->TrapFrame.Ctx.rip.u, pThis->Ctx.rip.u + cbAdjustPc,
2719	iEncoding, pThis->cbCurInstr, pThis->abCurInstr);
2720	Bs3TestPrintf("cpl=%u cbOperands=%u\n", pThis->uCpl, pThis->cbOperand);
2721
2722	/*
2723	* Display memory operands.
2724	*/
2725	for (iOperand = 0; iOperand < pThis->cOperands; iOperand++)
2726	{
2727	BS3PTRUNION PtrUnion;
2728	switch (pThis->aOperands[iOperand].enmLocation)
2729	{
2730	case BS3CG1OPLOC_CTX:
2731	{
2732	uint8_t idxField = pThis->aOperands[iOperand].idxField;
2733	unsigned offField = g_aoffBs3Cg1DstFields[idxField];
2734	if (offField <= sizeof(BS3REGCTX))
2735	PtrUnion.pb = (uint8_t BS3_FAR *)&pThis->Ctx + offField;
2736	else
2737	{
2738	Bs3TestPrintf("op%u: ctx%u: xxxx\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
2739	break;
2740	}
2741	switch (pThis->aOperands[iOperand].cbOp)
2742	{
2743	case 1: Bs3TestPrintf("op%u: ctx08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2744	case 2: Bs3TestPrintf("op%u: ctx16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2745	case 4: Bs3TestPrintf("op%u: ctx32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2746	case 8: Bs3TestPrintf("op%u: ctx64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2747	default:
2748	Bs3TestPrintf("op%u: ctx%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
2749	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2750	break;
2751	}
2752	break;
2753	}
2754
2755	case BS3CG1OPLOC_IMM:
2756	PtrUnion.pb = &pThis->pbCodePg[pThis->aOperands[iOperand].off];
2757	switch (pThis->aOperands[iOperand].cbOp)
2758	{
2759	case 1: Bs3TestPrintf("op%u: imm08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2760	case 2: Bs3TestPrintf("op%u: imm16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2761	case 4: Bs3TestPrintf("op%u: imm32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2762	case 8: Bs3TestPrintf("op%u: imm64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2763	default:
2764	Bs3TestPrintf("op%u: imm%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
2765	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2766	break;
2767	}
2768	break;
2769
2770	case BS3CG1OPLOC_MEM:
2771	case BS3CG1OPLOC_MEM_RW:
2772	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
2773	switch (pThis->aOperands[iOperand].cbOp)
2774	{
2775	case 1: Bs3TestPrintf("op%u: result mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2776	case 2: Bs3TestPrintf("op%u: result mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2777	case 4: Bs3TestPrintf("op%u: result mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2778	case 8: Bs3TestPrintf("op%u: result mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2779	default:
2780	Bs3TestPrintf("op%u: result mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
2781	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2782	break;
2783	}
2784	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
2785	{
2786	PtrUnion.pb = pThis->MemOp.ab;
2787	switch (pThis->aOperands[iOperand].cbOp)
2788	{
2789	case 1: Bs3TestPrintf("op%u: expect mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
2790	case 2: Bs3TestPrintf("op%u: expect mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
2791	case 4: Bs3TestPrintf("op%u: expect mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
2792	case 8: Bs3TestPrintf("op%u: expect mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
2793	default:
2794	Bs3TestPrintf("op%u: expect mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
2795	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
2796	break;
2797	}
2798	}
2799	break;
2800	}
2801	}
2802
2803	/*
2804	* Display contexts.
2805	*/
2806	Bs3TestPrintf("-- Expected context:\n");
2807	Bs3RegCtxPrint(&pThis->Ctx);
2808	Bs3TestPrintf("-- Actual context:\n");
2809	Bs3TrapPrintFrame(&pThis->TrapFrame);
2810	Bs3TestPrintf("\n");
2811	return false;
2812	}
2813
2814
2815	/**
2816	* Destroys the state, freeing all allocations and such.
2817	*
2818	* @param pThis The state.
2819	*/
2820	static void Bs3Cg1Destroy(PBS3CG1STATE pThis)
2821	{
2822	if (BS3_MODE_IS_PAGED(pThis->bMode))
2823	{
2824	#if ARCH_BITS != 16
2825	Bs3MemGuardedTestPageFree(pThis->pbCodePg);
2826	Bs3MemGuardedTestPageFree(pThis->pbDataPg);
2827	#endif
2828	}
2829	else
2830	{
2831	Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
2832	Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
2833	}
2834
2835	if (pThis->pExtCtx)
2836	Bs3MemFree(pThis->pExtCtx, pThis->pExtCtx->cb * 3);
2837
2838	pThis->pbCodePg = NULL;
2839	pThis->pbDataPg = NULL;
2840	pThis->pExtCtx = NULL;
2841	pThis->pResultExtCtx = NULL;
2842	pThis->pInitialExtCtx = NULL;
2843	}
2844
2845
2846	/**
2847	* Initializes the state.
2848	*
2849	* @returns Success indicator (true/false)
2850	* @param pThis The state.
2851	* @param bMode The mode being tested.
2852	*/
2853	bool BS3_CMN_NM(Bs3Cg1Init)(PBS3CG1STATE pThis, uint8_t bMode)
2854	{
2855	BS3MEMKIND const enmMemKind = BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL
2856	: !BS3_MODE_IS_64BIT_CODE(bMode) ? BS3MEMKIND_TILED : BS3MEMKIND_FLAT32;
2857	unsigned iRing;
2858	unsigned cb;
2859	unsigned i;
2860	uint64_t fFlags;
2861	PBS3EXTCTX pExtCtx;
2862
2863	Bs3MemSet(pThis, 0, sizeof(*pThis));
2864
2865	pThis->iFirstRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
2866	pThis->iEndRing = BS3_MODE_IS_RM_SYS(bMode) ? 1 : 4;
2867	pThis->bMode = bMode;
2868	pThis->pszMode = Bs3GetModeName(bMode);
2869	pThis->pszModeShort = Bs3GetModeNameShortLower(bMode);
2870	pThis->pchMnemonic = g_achBs3Cg1Mnemonics;
2871	pThis->pabOperands = g_abBs3Cg1Operands;
2872	pThis->pabOpcodes = g_abBs3Cg1Opcodes;
2873	pThis->fAdvanceMnemonic = 1;
2874
2875	/* Allocate extended context structures. */
2876	cb = Bs3ExtCtxGetSize(&fFlags);
2877	pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 3);
2878	if (!pExtCtx)
2879	return Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 3);
2880	pThis->pExtCtx = pExtCtx;
2881	pThis->pResultExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb);
2882	pThis->pInitialExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb + cb);
2883
2884	Bs3ExtCtxInit(pThis->pExtCtx, cb, fFlags);
2885	Bs3ExtCtxInit(pThis->pResultExtCtx, cb, fFlags);
2886	Bs3ExtCtxInit(pThis->pInitialExtCtx, cb, fFlags);
2887	//Bs3TestPrintf("fCR0=%RX64 cbExtCtx=%#x method=%d\n", fFlags, cb, pExtCtx->enmMethod);
2888
2889	/* Allocate guarded exectuable and data memory. */
2890	if (BS3_MODE_IS_PAGED(bMode))
2891	{
2892	#if ARCH_BITS != 16
2893	pThis->pbCodePg = Bs3MemGuardedTestPageAlloc(enmMemKind);
2894	pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
2895	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
2896	{
2897	Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
2898	Bs3MemPrintInfo();
2899	Bs3Shutdown();
2900	return Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
2901	}
2902	if ( BS3_MODE_IS_64BIT_CODE(bMode)
2903	&& (uintptr_t)pThis->pbDataPg >= _2G)
2904	return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
2905	#else
2906	return Bs3TestFailed("WTF?! #1");
2907	#endif
2908	}
2909	else
2910	{
2911	pThis->pbCodePg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
2912	pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
2913	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
2914	{
2915	Bs3MemPrintInfo();
2916	return Bs3TestFailedF("Bs3MemAlloc(%d,Pg) failed", enmMemKind);
2917	}
2918	}
2919	pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
2920	pThis->uDataPgFlat = Bs3SelPtrToFlat(pThis->pbDataPg);
2921	#if ARCH_BITS == 16
2922	pThis->CodePgFar.sel = BS3_FP_SEG(pThis->pbCodePg);
2923	pThis->CodePgFar.off = BS3_FP_OFF(pThis->pbCodePg);
2924	pThis->CodePgRip = BS3_FP_OFF(pThis->pbCodePg);
2925	pThis->DataPgFar.sel = BS3_FP_SEG(pThis->pbDataPg);
2926	pThis->DataPgFar.off = BS3_FP_OFF(pThis->pbDataPg);
2927	#else
2928	if (BS3_MODE_IS_RM_OR_V86(bMode))
2929	{
2930	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToRealMode(pThis->uDataPgFlat);
2931	ASMCompilerBarrier();
2932	pThis->CodePgFar.off = 0;
2933	pThis->CodePgFar.sel = pThis->uCodePgFlat >> 4;
2934	pThis->CodePgRip = pThis->CodePgFar.off;
2935	}
2936	else if (BS3_MODE_IS_16BIT_CODE(bMode))
2937	{
2938	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
2939	ASMCompilerBarrier();
2940	pThis->CodePgFar.sel = BS3_SEL_SPARE_00;
2941	pThis->CodePgFar.off = 0;
2942	pThis->CodePgRip = 0;
2943	}
2944	else if (BS3_MODE_IS_32BIT_CODE(bMode))
2945	{
2946	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
2947	ASMCompilerBarrier();
2948	pThis->CodePgFar.sel = 0;
2949	pThis->CodePgFar.off = 0;
2950	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
2951	}
2952	else
2953	{
2954	pThis->DataPgFar.off = 0;
2955	pThis->DataPgFar.sel = 0;
2956	pThis->CodePgFar.off = 0;
2957	pThis->CodePgFar.sel = 0;
2958	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
2959	}
2960	#endif
2961
2962	/*
2963	* Create basic context for each target ring.
2964	*
2965	* In protected 16-bit code we need set up code selectors that can access
2966	* pbCodePg.
2967	*
2968	* In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
2969	* bits set so we can check that the implicit clearing is tested.
2970	*/
2971	Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
2972	#if ARCH_BITS == 64
2973	pThis->aInitialCtxs[pThis->iFirstRing].rax.u \|= UINT64_C(0x0101010100000000);
2974	pThis->aInitialCtxs[pThis->iFirstRing].rbx.u \|= UINT64_C(0x0202020200000000);
2975	pThis->aInitialCtxs[pThis->iFirstRing].rcx.u \|= UINT64_C(0x0303030300000000);
2976	pThis->aInitialCtxs[pThis->iFirstRing].rdx.u \|= UINT64_C(0x0404040400000000);
2977	pThis->aInitialCtxs[pThis->iFirstRing].rbp.u \|= UINT64_C(0x0505050500000000);
2978	pThis->aInitialCtxs[pThis->iFirstRing].rdi.u \|= UINT64_C(0x0606060600000000);
2979	pThis->aInitialCtxs[pThis->iFirstRing].rsi.u \|= UINT64_C(0x0707070700000000);
2980	pThis->aInitialCtxs[pThis->iFirstRing].r8.u \|= UINT64_C(0x0808080800000000);
2981	pThis->aInitialCtxs[pThis->iFirstRing].r9.u \|= UINT64_C(0x0909090900000000);
2982	pThis->aInitialCtxs[pThis->iFirstRing].r10.u \|= UINT64_C(0x1010101000000000);
2983	pThis->aInitialCtxs[pThis->iFirstRing].r11.u \|= UINT64_C(0x1111111100000000);
2984	pThis->aInitialCtxs[pThis->iFirstRing].r12.u \|= UINT64_C(0x1212121200000000);
2985	pThis->aInitialCtxs[pThis->iFirstRing].r13.u \|= UINT64_C(0x1313131300000000);
2986	pThis->aInitialCtxs[pThis->iFirstRing].r14.u \|= UINT64_C(0x1414141400000000);
2987	pThis->aInitialCtxs[pThis->iFirstRing].r15.u \|= UINT64_C(0x1515151500000000);
2988	#endif
2989
2990	if (BS3_MODE_IS_RM_OR_V86(bMode))
2991	{
2992	pThis->aInitialCtxs[pThis->iFirstRing].cs = pThis->CodePgFar.sel;
2993	BS3_ASSERT(pThis->iFirstRing + 1 == pThis->iEndRing);
2994	}
2995	else if (BS3_MODE_IS_16BIT_CODE(bMode))
2996	{
2997	#if ARCH_BITS == 16
2998	uintptr_t const uFlatCodePgSeg = Bs3SelPtrToFlat(BS3_FP_MAKE(BS3_FP_SEG(pThis->pbCodePg), 0));
2999	#else
3000	uintptr_t const uFlatCodePgSeg = (uintptr_t)pThis->pbCodePg;
3001	#endif
3002	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3003	{
3004	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3005	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3006	}
3007	for (iRing = pThis->iFirstRing; iRing < pThis->iEndRing; iRing++)
3008	{
3009	pThis->aInitialCtxs[iRing].cs = BS3_SEL_SPARE_00 + iRing * 8 + iRing;
3010	Bs3SelSetup16BitCode(&Bs3GdteSpare00 + iRing, uFlatCodePgSeg, iRing);
3011	}
3012	}
3013	else
3014	{
3015	Bs3RegCtxSetRipCsFromCurPtr(&pThis->aInitialCtxs[pThis->iFirstRing], (FPFNBS3FAR)pThis->pbCodePg);
3016	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3017	{
3018	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3019	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3020	}
3021	}
3022
3023	/*
3024	* Create an initial extended CPU context.
3025	*/
3026	pExtCtx = pThis->pInitialExtCtx;
3027	if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
3028	\|\| pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
3029	{
3030	pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL \| X86_FCW_PC_64 \| X86_FCW_RC_NEAREST;
3031	pExtCtx->Ctx.x87.FSW = 0;
3032	pExtCtx->Ctx.x87.MXCSR = X86_MXSCR_IM \| X86_MXSCR_DM \| X86_MXSCR_RC_NEAREST;
3033	pExtCtx->Ctx.x87.MXCSR_MASK = 0;
3034	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
3035	{
3036	pExtCtx->Ctx.x87.aRegs[i].au16[0] = i << 4;
3037	pExtCtx->Ctx.x87.aRegs[i].au16[1] = i << 4;
3038	pExtCtx->Ctx.x87.aRegs[i].au16[2] = i << 4;
3039	pExtCtx->Ctx.x87.aRegs[i].au16[3] = i << 4;
3040	}
3041	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
3042	{
3043	pExtCtx->Ctx.x87.aXMM[i].au16[0] = i;
3044	pExtCtx->Ctx.x87.aXMM[i].au16[1] = i;
3045	pExtCtx->Ctx.x87.aXMM[i].au16[2] = i;
3046	pExtCtx->Ctx.x87.aXMM[i].au16[3] = i;
3047	pExtCtx->Ctx.x87.aXMM[i].au16[4] = i;
3048	pExtCtx->Ctx.x87.aXMM[i].au16[5] = i;
3049	pExtCtx->Ctx.x87.aXMM[i].au16[6] = i;
3050	pExtCtx->Ctx.x87.aXMM[i].au16[7] = i;
3051	}
3052	if (pExtCtx->fXcr0 & XSAVE_C_YMM)
3053	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi); i++)
3054	{
3055	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[0] = i << 8;
3056	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[1] = i << 8;
3057	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[2] = i << 8;
3058	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[3] = i << 8;
3059	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[4] = i << 8;
3060	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[5] = i << 8;
3061	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[6] = i << 8;
3062	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[7] = i << 8;
3063	}
3064
3065	}
3066	//else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_ANCIENT)
3067	else
3068	return Bs3TestFailedF("Unsupported extended CPU context method: %d", pExtCtx->enmMethod);
3069
3070	return true;
3071	}
3072
3073
3074	static uint8_t BS3_CMN_NM(Bs3Cg1WorkerInner)(PBS3CG1STATE pThis)
3075	{
3076	uint8_t iRing;
3077	unsigned iInstr;
3078
3079	/*
3080	* Test the instructions.
3081	*/
3082	for (iInstr = 0; iInstr < g_cBs3Cg1Instructions;
3083	iInstr++,
3084	pThis->pchMnemonic += pThis->fAdvanceMnemonic * pThis->cchMnemonic,
3085	pThis->pabOperands += pThis->cOperands,
3086	pThis->pabOpcodes += pThis->cbOpcodes)
3087	{
3088	bool fInvalidInstr = false;
3089	unsigned iCpuSetup;
3090	uint8_t bTestXcptExpected = BS3_MODE_IS_PAGED(pThis->bMode) ? X86_XCPT_PF : X86_XCPT_UD;
3091
3092	/*
3093	* Expand the instruction information into the state.
3094	* Note! 16-bit will switch to a two level test header lookup once we exceed 64KB.
3095	*/
3096	PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
3097	pThis->iInstr = iInstr;
3098	pThis->pTestHdr = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
3099	pThis->fFlags = pInstr->fFlags;
3100	pThis->enmEncoding = (BS3CG1ENC)pInstr->enmEncoding;
3101	pThis->enmCpuTest = (BS3CG1CPU)pInstr->enmCpuTest;
3102	pThis->enmPrefixKind = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
3103	pThis->enmXcptType = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
3104	pThis->cchMnemonic = pInstr->cchMnemonic;
3105	if (pThis->fAdvanceMnemonic)
3106	Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
3107	pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
3108	pThis->cOperands = pInstr->cOperands;
3109	pThis->cbOpcodes = pInstr->cbOpcodes;
3110	switch (pThis->cOperands)
3111	{
3112	case 3: pThis->aenmOperands[3] = (BS3CG1OP)pThis->pabOperands[3];
3113	case 2: pThis->aenmOperands[2] = (BS3CG1OP)pThis->pabOperands[2];
3114	case 1: pThis->aenmOperands[1] = (BS3CG1OP)pThis->pabOperands[1];
3115	case 0: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
3116	}
3117
3118	switch (pThis->cbOpcodes)
3119	{
3120	case 3: pThis->abOpcodes[3] = pThis->pabOpcodes[3];
3121	case 2: pThis->abOpcodes[2] = pThis->pabOpcodes[2];
3122	case 1: pThis->abOpcodes[1] = pThis->pabOpcodes[1];
3123	case 0: pThis->abOpcodes[0] = pThis->pabOpcodes[0];
3124	}
3125
3126	/*
3127	* Check if the CPU supports the instruction.
3128	*/
3129	if ( !Bs3Cg1CpuSetupFirst(pThis)
3130	\|\| (pThis->fFlags & BS3CG1INSTR_F_UNUSED))
3131	{
3132	fInvalidInstr = true;
3133	bTestXcptExpected = X86_XCPT_UD;
3134	}
3135
3136	for (iCpuSetup = 0;; iCpuSetup++)
3137	{
3138	unsigned iEncoding;
3139	unsigned iEncodingNext;
3140
3141	/*
3142	* Prep the operands and encoding handling.
3143	*/
3144	if (!Bs3Cg1EncodePrep(pThis))
3145	break;
3146
3147	/*
3148	* Encode the instruction in various ways and check out the test values.
3149	*/
3150	for (iEncoding = 0;; iEncoding = iEncodingNext)
3151	{
3152	/*
3153	* Encode the next instruction variation.
3154	*/
3155	iEncodingNext = Bs3Cg1EncodeNext(pThis, iEncoding);
3156	if (iEncodingNext <= iEncoding)
3157	break;
3158	BS3CG1_DPRINTF(("\ndbg: Encoding #%u: cbCurInst=%u: %.*Rhxs\n",
3159	iEncoding, pThis->cbCurInstr, pThis->cbCurInstr, pThis->abCurInstr));
3160
3161	/*
3162	* Do the rings.
3163	*/
3164	for (iRing = pThis->iFirstRing + pThis->fSameRingNotOkay; iRing < pThis->iEndRing; iRing++)
3165	{
3166	PCBS3CG1TESTHDR pHdr;
3167
3168	pThis->uCpl = iRing;
3169	BS3CG1_DPRINTF(("dbg: Ring %u\n", iRing));
3170
3171	/*
3172	* Do the tests one by one.
3173	*/
3174	pHdr = pThis->pTestHdr;
3175	for (pThis->iTest = 0;; pThis->iTest++)
3176	{
3177	if (Bs3Cg1RunSelector(pThis, pHdr))
3178	{
3179	/* Okay, set up the execution context. */
3180	unsigned offCode;
3181	uint8_t BS3_FAR *pbCode;
3182
3183	Bs3MemCpy(&pThis->Ctx, &pThis->aInitialCtxs[iRing], sizeof(pThis->Ctx));
3184	if (pThis->fWorkExtCtx)
3185	Bs3ExtCtxCopy(pThis->pExtCtx, pThis->pInitialExtCtx);
3186	if (BS3_MODE_IS_PAGED(pThis->bMode))
3187	{
3188	offCode = X86_PAGE_SIZE - pThis->cbCurInstr;
3189	pbCode = &pThis->pbCodePg[offCode];
3190	//if (iEncoding > 0) { pbCode[-1] = 0xf4; offCode--; }
3191	}
3192	else
3193	{
3194	pbCode = pThis->pbCodePg;
3195	pbCode[pThis->cbCurInstr] = 0x0f; /* UD2 */
3196	pbCode[pThis->cbCurInstr + 1] = 0x0b;
3197	offCode = 0;
3198	}
3199	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3200	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr);
3201
3202	if (Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr, pHdr->cbSelector, pHdr->cbInput, NULL, pbCode))
3203	{
3204	/* Run the instruction. */
3205	BS3CG1_DPRINTF(("dbg: Running test #%u\n", pThis->iTest));
3206	//Bs3RegCtxPrint(&pThis->Ctx);
3207	if (pThis->fWorkExtCtx)
3208	Bs3ExtCtxRestore(pThis->pExtCtx);
3209	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3210	if (pThis->fWorkExtCtx)
3211	Bs3ExtCtxSave(pThis->pResultExtCtx);
3212	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64\n",
3213	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3214
3215	/*
3216	* Apply the output modification program to the context.
3217	*/
3218	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3219	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3220	pThis->bValueXcpt = UINT8_MAX;
3221	if ( fInvalidInstr
3222	\|\| pThis->bAlignmentXcpt != UINT8_MAX
3223	\|\| pThis->bValueXcpt != UINT8_MAX
3224	\|\| Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr,
3225	pHdr->cbSelector + pHdr->cbInput, pHdr->cbOutput,
3226	&pThis->TrapFrame.Ctx, NULL /pbCode/))
3227	{
3228	Bs3Cg1CheckResult(pThis, fInvalidInstr, bTestXcptExpected, iEncoding);
3229	}
3230	}
3231	}
3232	else
3233	BS3CG1_DPRINTF(("dbg: Skipping #%u\n", pThis->iTest));
3234
3235	/* advance */
3236	if (pHdr->fLast)
3237	{
3238	BS3CG1_DPRINTF(("dbg: Last\n\n"));
3239	break;
3240	}
3241	pHdr = (PCBS3CG1TESTHDR)((uint8_t BS3_FAR *)(pHdr + 1) + pHdr->cbInput + pHdr->cbOutput + pHdr->cbSelector);
3242	}
3243	}
3244	}
3245
3246	/*
3247	* Clean up (segment registers, etc) and get the next CPU config.
3248	*/
3249	Bs3Cg1EncodeCleanup(pThis);
3250	if (!Bs3Cg1CpuSetupNext(pThis, iCpuSetup, &fInvalidInstr))
3251	break;
3252	if (pThis->fFlags & BS3CG1INSTR_F_UNUSED)
3253	fInvalidInstr = true;
3254	if (fInvalidInstr)
3255	bTestXcptExpected = X86_XCPT_UD;
3256	}
3257	}
3258
3259	return 0;
3260	}
3261
3262
3263	BS3_DECL_FAR(uint8_t) BS3_CMN_NM(Bs3Cg1Worker)(uint8_t bMode)
3264	{
3265	uint8_t bRet = 1;
3266	BS3CG1STATE This;
3267
3268	#if 0
3269	/* (for debugging) */
3270	if (!BS3_MODE_IS_RM_OR_V86(bMode))
3271	return BS3TESTDOMODE_SKIPPED;
3272	#endif
3273
3274	if (BS3_CMN_NM(Bs3Cg1Init)(&This, bMode))
3275	{
3276	bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
3277	Bs3TestSubDone();
3278	}
3279	Bs3Cg1Destroy(&This);
3280
3281	#if 0
3282	/* (for debugging) */
3283	if (bMode >= BS3_MODE_RM)
3284	{
3285	Bs3TestTerm();
3286	Bs3Shutdown();
3287	}
3288	#endif
3289	return bRet;
3290	}
3291

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 66331

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