bs3-cpu-generated-1-template.c@ 66785

Last change on this file since 66785 was 66785, checked in by vboxsync, 8 years ago
IEM: Implemented movlhps Vdq,Uq and movhps Vdq,Mq (0f 16).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 162.6 KB

Line
1	/* $Id: bs3-cpu-generated-1-template.c 66785 2017-05-04 11:48:37Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	#ifndef BS3_INSTANTIATING_CMN
28	# error "BS3_INSTANTIATING_CMN not defined"
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Header Files *
34	*********************************************************************************************************************************/
35	#include <iprt/asm.h>
36	#include <iprt/asm-amd64-x86.h>
37
38	#include "bs3-cpu-generated-1.h"
39
40
41	/*********************************************************************************************************************************
42	* Defined Constants And Macros *
43	*********************************************************************************************************************************/
44	#define P_CS X86_OP_PRF_CS
45	#define P_SS X86_OP_PRF_SS
46	#define P_DS X86_OP_PRF_DS
47	#define P_ES X86_OP_PRF_ES
48	#define P_FS X86_OP_PRF_FS
49	#define P_GS X86_OP_PRF_GS
50	#define P_OZ X86_OP_PRF_SIZE_OP
51	#define P_AZ X86_OP_PRF_SIZE_ADDR
52	#define P_LK X86_OP_PRF_LOCK
53	#define P_RN X86_OP_PRF_REPNZ
54	#define P_RZ X86_OP_PRF_REPZ
55
56	#define REX_WRBX (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
57	#define REX_W___ (X86_OP_REX_W)
58	#define REX_WR__ (X86_OP_REX_W \| X86_OP_REX_R)
59	#define REX_W_B_ (X86_OP_REX_W \| X86_OP_REX_B)
60	#define REX_W__X (X86_OP_REX_W \| X86_OP_REX_X)
61	#define REX_WRB_ (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B)
62	#define REX_WR_X (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_X)
63	#define REX_W_BX (X86_OP_REX_W \| X86_OP_REX_B \| X86_OP_REX_X)
64	#define REX__R__ (X86_OP_REX_R)
65	#define REX__RB_ (X86_OP_REX_R \| X86_OP_REX_B)
66	#define REX__R_X (X86_OP_REX_R \| X86_OP_REX_X)
67	#define REX__RBX (X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
68	#define REX___B_ (X86_OP_REX_B)
69	#define REX___BX (X86_OP_REX_B \| X86_OP_REX_X)
70	#define REX____X (X86_OP_REX_X)
71	#define REX_____ (0x40)
72
73
74	/** @def BS3CG1_DPRINTF
75	* Debug print macro.
76	*/
77	#if 0
78	# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
79	# define BS3CG1_DEBUG_CTX_MOD
80	#else
81	# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
82	#endif
83
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/** Operand value location. */
90	typedef enum BS3CG1OPLOC
91	{
92	BS3CG1OPLOC_INVALID = 0,
93	BS3CG1OPLOC_CTX,
94	BS3CG1OPLOC_IMM,
95	BS3CG1OPLOC_MEM,
96	BS3CG1OPLOC_MEM_RW,
97	BS3CG1OPLOC_END
98	} BS3CG1OPLOC;
99
100
101	/**
102	* The state.
103	*/
104	typedef struct BS3CG1STATE
105	{
106	/** @name Instruction details (expanded from BS3CG1INSTR).
107	* @{ */
108	/** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
109	const char BS3_FAR *pchMnemonic;
110	/** Pointer to the test header. */
111	PCBS3CG1TESTHDR pTestHdr;
112	/** Pointer to the per operand flags (g_abBs3Cg1Operands). */
113	const uint8_t BS3_FAR *pabOperands;
114	/** Opcode bytes (g_abBs3Cg1Opcodes). */
115	const uint8_t BS3_FAR *pabOpcodes;
116	/** The current instruction number in the input array (for error reporting). */
117	uint32_t iInstr;
118
119	/** The instruction flags. */
120	uint32_t fFlags;
121	/** The encoding. */
122	BS3CG1ENC enmEncoding;
123	/** The non-invalid encoding. This differs from enmEncoding when
124	* Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */
125	BS3CG1ENC enmEncodingNonInvalid;
126	/** The CPU test / CPU ID. */
127	BS3CG1CPU enmCpuTest;
128	/** Prefix sensitivity and requirements. */
129	BS3CG1PFXKIND enmPrefixKind;
130	/** Exception type (SSE, AVX). */
131	BS3CG1XCPTTYPE enmXcptType;
132	/** Per operand flags. */
133	BS3CG1OP aenmOperands[4];
134	/** Opcode bytes. */
135	uint8_t abOpcodes[4];
136
137	/** The length of the mnemonic. */
138	uint8_t cchMnemonic;
139	/** Whether to advance the mnemonic pointer or not. */
140	uint8_t fAdvanceMnemonic;
141	/** The number of opcode bytes. */
142	uint8_t cbOpcodes;
143	/** Number of operands. */
144	uint8_t cOperands;
145	/** @} */
146
147	/** Operand size in bytes (0 if not applicable). */
148	uint8_t cbOperand;
149	/** Current target ring (0..3). */
150	uint8_t uCpl;
151
152	/** The current test number. */
153	uint8_t iTest;
154
155	/** Target mode (g_bBs3CurrentMode). */
156	uint8_t bMode;
157	/** The CPU vendor (BS3CPUVENDOR). */
158	uint8_t bCpuVendor;
159	/** First ring being tested. */
160	uint8_t iFirstRing;
161	/** End of rings being tested. */
162	uint8_t iEndRing;
163
164
165	/** @name Current encoded instruction.
166	* @{ */
167	/** The size of the current instruction that we're testing. */
168	uint8_t cbCurInstr;
169	/** The size the prefixes. */
170	uint8_t cbCurPrefix;
171	/** The offset into abCurInstr of the immediate. */
172	uint8_t offCurImm;
173	/** Buffer for assembling the current instruction. */
174	uint8_t abCurInstr[23];
175
176	/** Set if the encoding can't be tested in the same ring as this test code.
177	* This is used to deal with encodings modifying SP/ESP/RSP. */
178	bool fSameRingNotOkay;
179	/** Whether to work the extended context too. */
180	bool fWorkExtCtx;
181	/** The aOperands index of the modrm.reg operand (if applicable). */
182	uint8_t iRegOp;
183	/** The aOperands index of the modrm.rm operand (if applicable). */
184	uint8_t iRmOp;
185
186	/** Operands details. */
187	struct
188	{
189	uint8_t cbOp;
190	/** BS3CG1OPLOC_XXX. */
191	uint8_t enmLocation;
192	/** The BS3CG1DST value for this field.
193	* Set to BS3CG1DST_INVALID if memory or immediate. */
194	uint8_t idxField;
195	/** Depends on enmLocation.
196	* - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
197	* - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
198	* - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
199	* - BS3CG1OPLOC_CTX: not used (use idxField instead).
200	*/
201	uint8_t off;
202	} aOperands[4];
203	/** @} */
204
205	/** Page to put code in. When paging is enabled, the page before and after
206	* are marked not-present. */
207	uint8_t BS3_FAR *pbCodePg;
208	/** The flat address corresponding to pbCodePg. */
209	uintptr_t uCodePgFlat;
210	/** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
211	RTFAR16 CodePgFar;
212	/** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
213	uintptr_t CodePgRip;
214
215	/** Page for placing data operands in. When paging is enabled, the page before
216	* and after are marked not-present. */
217	uint8_t BS3_FAR *pbDataPg;
218	/** The flat address corresponding to pbDataPg. */
219	uintptr_t uDataPgFlat;
220	/** The 16-bit address corresponding to pbDataPg. */
221	RTFAR16 DataPgFar;
222
223	/** The name corresponding to bMode. */
224	const char BS3_FAR *pszMode;
225	/** The short name corresponding to bMode. */
226	const char BS3_FAR *pszModeShort;
227
228	/** @name Expected result (modifiable by output program).
229	* @{ */
230	/** The expected exception based on operand values or result.
231	* UINT8_MAX if no special exception expected. */
232	uint8_t bValueXcpt;
233	/** @} */
234	/** Alignment exception expected by the encoder.
235	* UINT8_MAX if no special exception expected. */
236	uint8_t bAlignmentXcpt;
237	/** Set by the encoding method to indicating invalid encoding. */
238	bool fInvalidEncoding;
239
240	/** The context we're working on. */
241	BS3REGCTX Ctx;
242	/** The trap context and frame. */
243	BS3TRAPFRAME TrapFrame;
244	/** Initial contexts, one for each ring. */
245	BS3REGCTX aInitialCtxs[4];
246
247	/** The extended context we're working on (input, expected output). */
248	PBS3EXTCTX pExtCtx;
249	/** The extended result context (analoguous to TrapFrame). */
250	PBS3EXTCTX pResultExtCtx;
251	/** The initial extended context. */
252	PBS3EXTCTX pInitialExtCtx;
253
254	/** Memory operand scratch space. */
255	union
256	{
257	uint8_t ab[128];
258	uint16_t au16[128 / sizeof(uint16_t)];
259	uint32_t au32[128 / sizeof(uint32_t)];
260	uint64_t au64[128 / sizeof(uint64_t)];
261	} MemOp;
262
263	/** Array parallel to aInitialCtxs for saving segment registers. */
264	struct
265	{
266	RTSEL ds;
267	} aSavedSegRegs[4];
268
269	} BS3CG1STATE;
270	/** Pointer to the generated test state. */
271	typedef BS3CG1STATE *PBS3CG1STATE;
272
273
274	#define BS3CG1_PF_OZ UINT16_C(0x0001)
275	#define BS3CG1_PF_AZ UINT16_C(0x0002)
276	#define BS3CG1_PF_CS UINT16_C(0x0004)
277	#define BS3CG1_PF_DS UINT16_C(0x0008)
278	#define BS3CG1_PF_ES UINT16_C(0x0010)
279	#define BS3CG1_PF_FS UINT16_C(0x0020)
280	#define BS3CG1_PF_GS UINT16_C(0x0040)
281	#define BS3CG1_PF_SS UINT16_C(0x0080)
282	#define BS3CG1_PF_SEGS (BS3CG1_PF_CS \| BS3CG1_PF_DS \| BS3CG1_PF_ES \| BS3CG1_PF_FS \| BS3CG1_PF_GS \| BS3CG1_PF_SS)
283	#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS \| BS3CG1_PF_AZ)
284	#define BS3CG1_PF_LK UINT16_C(0x0100)
285	#define BS3CG1_PF_RN UINT16_C(0x0200)
286	#define BS3CG1_PF_RZ UINT16_C(0x0400)
287	#define BS3CG1_PF_W UINT16_C(0x0800) /*< REX.W /
288	#define BS3CG1_PF_R UINT16_C(0x1000) /*< REX.R /
289	#define BS3CG1_PF_B UINT16_C(0x2000) /*< REX.B /
290	#define BS3CG1_PF_X UINT16_C(0x4000) /*< REX.X /
291
292
293	/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
294	#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
295	/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
296	* the field size (2, 4, or 8). */
297	#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
298
299
300
301	/*********************************************************************************************************************************
302	* Global Variables *
303	*********************************************************************************************************************************/
304	/** Destination field sizes indexed by bBS3CG1DST.
305	* Zero means operand size sized. */
306	static const uint8_t g_acbBs3Cg1DstFields[] =
307	{
308	/* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
309
310	/* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
311	/* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
312	/* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
313	/* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
314	/* [BS3CG1DST_EFL] = */ 4,
315	/* [BS3CG1DST_EFL_UNDEF]=*/ 4,
316
317	/* [BS3CG1DST_AL] = */ 1,
318	/* [BS3CG1DST_CL] = */ 1,
319	/* [BS3CG1DST_DL] = */ 1,
320	/* [BS3CG1DST_BL] = */ 1,
321	/* [BS3CG1DST_AH] = */ 1,
322	/* [BS3CG1DST_CH] = */ 1,
323	/* [BS3CG1DST_DH] = */ 1,
324	/* [BS3CG1DST_BH] = */ 1,
325	/* [BS3CG1DST_SPL] = */ 1,
326	/* [BS3CG1DST_BPL] = */ 1,
327	/* [BS3CG1DST_SIL] = */ 1,
328	/* [BS3CG1DST_DIL] = */ 1,
329	/* [BS3CG1DST_R8L] = */ 1,
330	/* [BS3CG1DST_R9L] = */ 1,
331	/* [BS3CG1DST_R10L] = */ 1,
332	/* [BS3CG1DST_R11L] = */ 1,
333	/* [BS3CG1DST_R12L] = */ 1,
334	/* [BS3CG1DST_R13L] = */ 1,
335	/* [BS3CG1DST_R14L] = */ 1,
336	/* [BS3CG1DST_R15L] = */ 1,
337
338	/* [BS3CG1DST_AX] = */ 2,
339	/* [BS3CG1DST_CX] = */ 2,
340	/* [BS3CG1DST_DX] = */ 2,
341	/* [BS3CG1DST_BX] = */ 2,
342	/* [BS3CG1DST_SP] = */ 2,
343	/* [BS3CG1DST_BP] = */ 2,
344	/* [BS3CG1DST_SI] = */ 2,
345	/* [BS3CG1DST_DI] = */ 2,
346	/* [BS3CG1DST_R8W] = */ 2,
347	/* [BS3CG1DST_R9W] = */ 2,
348	/* [BS3CG1DST_R10W] = */ 2,
349	/* [BS3CG1DST_R11W] = */ 2,
350	/* [BS3CG1DST_R12W] = */ 2,
351	/* [BS3CG1DST_R13W] = */ 2,
352	/* [BS3CG1DST_R14W] = */ 2,
353	/* [BS3CG1DST_R15W] = */ 2,
354
355	/* [BS3CG1DST_EAX] = */ 4,
356	/* [BS3CG1DST_ECX] = */ 4,
357	/* [BS3CG1DST_EDX] = */ 4,
358	/* [BS3CG1DST_EBX] = */ 4,
359	/* [BS3CG1DST_ESP] = */ 4,
360	/* [BS3CG1DST_EBP] = */ 4,
361	/* [BS3CG1DST_ESI] = */ 4,
362	/* [BS3CG1DST_EDI] = */ 4,
363	/* [BS3CG1DST_R8D] = */ 4,
364	/* [BS3CG1DST_R9D] = */ 4,
365	/* [BS3CG1DST_R10D] = */ 4,
366	/* [BS3CG1DST_R11D] = */ 4,
367	/* [BS3CG1DST_R12D] = */ 4,
368	/* [BS3CG1DST_R13D] = */ 4,
369	/* [BS3CG1DST_R14D] = */ 4,
370	/* [BS3CG1DST_R15D] = */ 4,
371
372	/* [BS3CG1DST_RAX] = */ 8,
373	/* [BS3CG1DST_RCX] = */ 8,
374	/* [BS3CG1DST_RDX] = */ 8,
375	/* [BS3CG1DST_RBX] = */ 8,
376	/* [BS3CG1DST_RSP] = */ 8,
377	/* [BS3CG1DST_RBP] = */ 8,
378	/* [BS3CG1DST_RSI] = */ 8,
379	/* [BS3CG1DST_RDI] = */ 8,
380	/* [BS3CG1DST_R8] = */ 8,
381	/* [BS3CG1DST_R9] = */ 8,
382	/* [BS3CG1DST_R10] = */ 8,
383	/* [BS3CG1DST_R11] = */ 8,
384	/* [BS3CG1DST_R12] = */ 8,
385	/* [BS3CG1DST_R13] = */ 8,
386	/* [BS3CG1DST_R14] = */ 8,
387	/* [BS3CG1DST_R15] = */ 8,
388
389	/* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
390	/* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
391	/* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
392	/* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
393	/* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
394	/* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
395	/* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
396	/* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
397	/* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
398	/* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
399	/* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
400	/* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
401	/* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
402	/* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
403	/* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
404	/* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
405
406	/* [BS3CG1DST_CR0] = */ 4,
407	/* [BS3CG1DST_CR4] = */ 4,
408	/* [BS3CG1DST_XCR0] = */ 8,
409
410	/* [BS3CG1DST_FCW] = */ 2,
411	/* [BS3CG1DST_FSW] = */ 2,
412	/* [BS3CG1DST_FTW] = */ 2,
413	/* [BS3CG1DST_FOP] = */ 2,
414	/* [BS3CG1DST_FPUIP] = */ 2,
415	/* [BS3CG1DST_FPUCS] = */ 2,
416	/* [BS3CG1DST_FPUDP] = */ 2,
417	/* [BS3CG1DST_FPUDS] = */ 2,
418	/* [BS3CG1DST_MXCSR] = */ 4,
419	/* [BS3CG1DST_ST0] = */ 12,
420	/* [BS3CG1DST_ST1] = */ 12,
421	/* [BS3CG1DST_ST2] = */ 12,
422	/* [BS3CG1DST_ST3] = */ 12,
423	/* [BS3CG1DST_ST4] = */ 12,
424	/* [BS3CG1DST_ST5] = */ 12,
425	/* [BS3CG1DST_ST6] = */ 12,
426	/* [BS3CG1DST_ST7] = */ 12,
427	/* [BS3CG1DST_MM0] = */ 8,
428	/* [BS3CG1DST_MM1] = */ 8,
429	/* [BS3CG1DST_MM2] = */ 8,
430	/* [BS3CG1DST_MM3] = */ 8,
431	/* [BS3CG1DST_MM4] = */ 8,
432	/* [BS3CG1DST_MM5] = */ 8,
433	/* [BS3CG1DST_MM6] = */ 8,
434	/* [BS3CG1DST_MM7] = */ 8,
435	/* [BS3CG1DST_XMM0] = */ 16,
436	/* [BS3CG1DST_XMM1] = */ 16,
437	/* [BS3CG1DST_XMM2] = */ 16,
438	/* [BS3CG1DST_XMM3] = */ 16,
439	/* [BS3CG1DST_XMM4] = */ 16,
440	/* [BS3CG1DST_XMM5] = */ 16,
441	/* [BS3CG1DST_XMM6] = */ 16,
442	/* [BS3CG1DST_XMM7] = */ 16,
443	/* [BS3CG1DST_XMM8] = */ 16,
444	/* [BS3CG1DST_XMM9] = */ 16,
445	/* [BS3CG1DST_XMM10] = */ 16,
446	/* [BS3CG1DST_XMM11] = */ 16,
447	/* [BS3CG1DST_XMM12] = */ 16,
448	/* [BS3CG1DST_XMM13] = */ 16,
449	/* [BS3CG1DST_XMM14] = */ 16,
450	/* [BS3CG1DST_XMM15] = */ 16,
451	/* [BS3CG1DST_XMM0_LO] = */ 8,
452	/* [BS3CG1DST_XMM1_LO] = */ 8,
453	/* [BS3CG1DST_XMM2_LO] = */ 8,
454	/* [BS3CG1DST_XMM3_LO] = */ 8,
455	/* [BS3CG1DST_XMM4_LO] = */ 8,
456	/* [BS3CG1DST_XMM5_LO] = */ 8,
457	/* [BS3CG1DST_XMM6_LO] = */ 8,
458	/* [BS3CG1DST_XMM7_LO] = */ 8,
459	/* [BS3CG1DST_XMM8_LO] = */ 8,
460	/* [BS3CG1DST_XMM9_LO] = */ 8,
461	/* [BS3CG1DST_XMM10_LO] = */ 8,
462	/* [BS3CG1DST_XMM11_LO] = */ 8,
463	/* [BS3CG1DST_XMM12_LO] = */ 8,
464	/* [BS3CG1DST_XMM13_LO] = */ 8,
465	/* [BS3CG1DST_XMM14_LO] = */ 8,
466	/* [BS3CG1DST_XMM15_LO] = */ 8,
467	/* [BS3CG1DST_XMM0_HI] = */ 8,
468	/* [BS3CG1DST_XMM1_HI] = */ 8,
469	/* [BS3CG1DST_XMM2_HI] = */ 8,
470	/* [BS3CG1DST_XMM3_HI] = */ 8,
471	/* [BS3CG1DST_XMM4_HI] = */ 8,
472	/* [BS3CG1DST_XMM5_HI] = */ 8,
473	/* [BS3CG1DST_XMM6_HI] = */ 8,
474	/* [BS3CG1DST_XMM7_HI] = */ 8,
475	/* [BS3CG1DST_XMM8_HI] = */ 8,
476	/* [BS3CG1DST_XMM9_HI] = */ 8,
477	/* [BS3CG1DST_XMM10_HI] = */ 8,
478	/* [BS3CG1DST_XMM11_HI] = */ 8,
479	/* [BS3CG1DST_XMM12_HI] = */ 8,
480	/* [BS3CG1DST_XMM13_HI] = */ 8,
481	/* [BS3CG1DST_XMM14_HI] = */ 8,
482	/* [BS3CG1DST_XMM15_HI] = */ 8,
483	/* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
484	/* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
485	/* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
486	/* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
487	/* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
488	/* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
489	/* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
490	/* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
491	/* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
492	/* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
493	/* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
494	/* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
495	/* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
496	/* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
497	/* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
498	/* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
499	/* [BS3CG1DST_XMM0_DW0] = */ 4,
500	/* [BS3CG1DST_XMM1_DW0] = */ 4,
501	/* [BS3CG1DST_XMM2_DW0] = */ 4,
502	/* [BS3CG1DST_XMM3_DW0] = */ 4,
503	/* [BS3CG1DST_XMM4_DW0] = */ 4,
504	/* [BS3CG1DST_XMM5_DW0] = */ 4,
505	/* [BS3CG1DST_XMM6_DW0] = */ 4,
506	/* [BS3CG1DST_XMM7_DW0] = */ 4,
507	/* [BS3CG1DST_XMM8_DW0] = */ 4,
508	/* [BS3CG1DST_XMM9_DW0] = */ 4,
509	/* [BS3CG1DST_XMM10_DW0] = */ 4,
510	/* [BS3CG1DST_XMM11_DW0] = */ 4,
511	/* [BS3CG1DST_XMM12_DW0] = */ 4,
512	/* [BS3CG1DST_XMM13_DW0] = */ 4,
513	/* [BS3CG1DST_XMM14_DW0] = */ 4,
514	/* [BS3CG1DST_XMM15_DW0] = */ 4,
515	/* [BS3CG1DST_XMM0_DW0_ZX] = */ 4,
516	/* [BS3CG1DST_XMM1_DW0_ZX] = */ 4,
517	/* [BS3CG1DST_XMM2_DW0_ZX] = */ 4,
518	/* [BS3CG1DST_XMM3_DW0_ZX] = */ 4,
519	/* [BS3CG1DST_XMM4_DW0_ZX] = */ 4,
520	/* [BS3CG1DST_XMM5_DW0_ZX] = */ 4,
521	/* [BS3CG1DST_XMM6_DW0_ZX] = */ 4,
522	/* [BS3CG1DST_XMM7_DW0_ZX] = */ 4,
523	/* [BS3CG1DST_XMM8_DW0_ZX] = */ 4,
524	/* [BS3CG1DST_XMM9_DW0_ZX] = */ 4,
525	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ 4,
526	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ 4,
527	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ 4,
528	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ 4,
529	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
530	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
531	/* [BS3CG1DST_YMM0] = */ 32,
532	/* [BS3CG1DST_YMM1] = */ 32,
533	/* [BS3CG1DST_YMM2] = */ 32,
534	/* [BS3CG1DST_YMM3] = */ 32,
535	/* [BS3CG1DST_YMM4] = */ 32,
536	/* [BS3CG1DST_YMM5] = */ 32,
537	/* [BS3CG1DST_YMM6] = */ 32,
538	/* [BS3CG1DST_YMM7] = */ 32,
539	/* [BS3CG1DST_YMM8] = */ 32,
540	/* [BS3CG1DST_YMM9] = */ 32,
541	/* [BS3CG1DST_YMM10] = */ 32,
542	/* [BS3CG1DST_YMM11] = */ 32,
543	/* [BS3CG1DST_YMM12] = */ 32,
544	/* [BS3CG1DST_YMM13] = */ 32,
545	/* [BS3CG1DST_YMM14] = */ 32,
546	/* [BS3CG1DST_YMM15] = */ 32,
547
548	/* [BS3CG1DST_VALUE_XCPT] = */ 1,
549	};
550	AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
551
552	/** Destination field offset indexed by bBS3CG1DST.
553	* Zero means operand size sized. */
554	static const unsigned g_aoffBs3Cg1DstFields[] =
555	{
556	/* [BS3CG1DST_INVALID] = */ ~0U,
557	/* [BS3CG1DST_OP1] = */ ~0U,
558	/* [BS3CG1DST_OP2] = */ ~0U,
559	/* [BS3CG1DST_OP3] = */ ~0U,
560	/* [BS3CG1DST_OP4] = */ ~0U,
561	/* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
562	/* [BS3CG1DST_EFL_UNDEF]=/ ~0, / special field */
563
564	/* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
565	/* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
566	/* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
567	/* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
568	/* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
569	/* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
570	/* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
571	/* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
572	/* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
573	/* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
574	/* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
575	/* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
576	/* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
577	/* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
578	/* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
579	/* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
580	/* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
581	/* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
582	/* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
583	/* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
584
585	/* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
586	/* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
587	/* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
588	/* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
589	/* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
590	/* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
591	/* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
592	/* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
593	/* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
594	/* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
595	/* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
596	/* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
597	/* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
598	/* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
599	/* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
600	/* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
601
602	/* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
603	/* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
604	/* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
605	/* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
606	/* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
607	/* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
608	/* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
609	/* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
610	/* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
611	/* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
612	/* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
613	/* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
614	/* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
615	/* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
616	/* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
617	/* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
618
619	/* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
620	/* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
621	/* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
622	/* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
623	/* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
624	/* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
625	/* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
626	/* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
627	/* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
628	/* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
629	/* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
630	/* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
631	/* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
632	/* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
633	/* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
634	/* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
635
636	/* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
637	/* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
638	/* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
639	/* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
640	/* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
641	/* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
642	/* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
643	/* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
644	/* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
645	/* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
646	/* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
647	/* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
648	/* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
649	/* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
650	/* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
651	/* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
652
653	/* [BS3CG1DST_CR0] = */ RT_OFFSETOF(BS3REGCTX, cr0),
654	/* [BS3CG1DST_CR4] = */ RT_OFFSETOF(BS3REGCTX, cr4),
655	/* [BS3CG1DST_XCR0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, fXcr0Saved),
656
657	/* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
658	/* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
659	/* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
660	/* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
661	/* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
662	/* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
663	/* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
664	/* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
665	/* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
666	/* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
667	/* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
668	/* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
669	/* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
670	/* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
671	/* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
672	/* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
673	/* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
674	/* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
675	/* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
676	/* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
677	/* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
678	/* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
679	/* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
680	/* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
681	/* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
682
683	/* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
684	/* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
685	/* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
686	/* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
687	/* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
688	/* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
689	/* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
690	/* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
691	/* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
692	/* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
693	/* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
694	/* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
695	/* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
696	/* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
697	/* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
698	/* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
699	/* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
700	/* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
701	/* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
702	/* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
703	/* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
704	/* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
705	/* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
706	/* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
707	/* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
708	/* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
709	/* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
710	/* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
711	/* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
712	/* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
713	/* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
714	/* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
715	/* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
716	/* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
717	/* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
718	/* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
719	/* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
720	/* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
721	/* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
722	/* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
723	/* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
724	/* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
725	/* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
726	/* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
727	/* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
728	/* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
729	/* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
730	/* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
731	/* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
732	/* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
733	/* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
734	/* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
735	/* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
736	/* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
737	/* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
738	/* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
739	/* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
740	/* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
741	/* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
742	/* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
743	/* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
744	/* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
745	/* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
746	/* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
747	/* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
748	/* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
749	/* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
750	/* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
751	/* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
752	/* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
753	/* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
754	/* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
755	/* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
756	/* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
757	/* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
758	/* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
759	/* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
760	/* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
761	/* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
762	/* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
763	/* [BS3CG1DST_XMM0_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
764	/* [BS3CG1DST_XMM1_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
765	/* [BS3CG1DST_XMM2_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
766	/* [BS3CG1DST_XMM3_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
767	/* [BS3CG1DST_XMM4_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
768	/* [BS3CG1DST_XMM5_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
769	/* [BS3CG1DST_XMM6_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
770	/* [BS3CG1DST_XMM7_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
771	/* [BS3CG1DST_XMM8_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
772	/* [BS3CG1DST_XMM9_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
773	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
774	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
775	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
776	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
777	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
778	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
779
780	/* [BS3CG1DST_YMM0] = */ ~0U,
781	/* [BS3CG1DST_YMM1] = */ ~0U,
782	/* [BS3CG1DST_YMM2] = */ ~0U,
783	/* [BS3CG1DST_YMM3] = */ ~0U,
784	/* [BS3CG1DST_YMM4] = */ ~0U,
785	/* [BS3CG1DST_YMM5] = */ ~0U,
786	/* [BS3CG1DST_YMM6] = */ ~0U,
787	/* [BS3CG1DST_YMM7] = */ ~0U,
788	/* [BS3CG1DST_YMM8] = */ ~0U,
789	/* [BS3CG1DST_YMM9] = */ ~0U,
790	/* [BS3CG1DST_YMM10] = */ ~0U,
791	/* [BS3CG1DST_YMM11] = */ ~0U,
792	/* [BS3CG1DST_YMM12] = */ ~0U,
793	/* [BS3CG1DST_YMM13] = */ ~0U,
794	/* [BS3CG1DST_YMM14] = */ ~0U,
795	/* [BS3CG1DST_YMM15] = */ ~0U,
796
797	/* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
798	};
799	AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
800
801	#ifdef BS3CG1_DEBUG_CTX_MOD
802	/** Destination field names. */
803	static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
804	{
805	{ "INVALID" },
806	{ "OP1" },
807	{ "OP2" },
808	{ "OP3" },
809	{ "OP4" },
810	{ "EFL" },
811	{ "EFL_UND" },
812
813	{ "AL" },
814	{ "CL" },
815	{ "DL" },
816	{ "BL" },
817	{ "AH" },
818	{ "CH" },
819	{ "DH" },
820	{ "BH" },
821	{ "SPL" },
822	{ "BPL" },
823	{ "SIL" },
824	{ "DIL" },
825	{ "R8L" },
826	{ "R9L" },
827	{ "R10L" },
828	{ "R11L" },
829	{ "R12L" },
830	{ "R13L" },
831	{ "R14L" },
832	{ "R15L" },
833
834	{ "AX" },
835	{ "CX" },
836	{ "DX" },
837	{ "BX" },
838	{ "SP" },
839	{ "BP" },
840	{ "SI" },
841	{ "DI" },
842	{ "R8W" },
843	{ "R9W" },
844	{ "R10W" },
845	{ "R11W" },
846	{ "R12W" },
847	{ "R13W" },
848	{ "R14W" },
849	{ "R15W" },
850
851	{ "EAX" },
852	{ "ECX" },
853	{ "EDX" },
854	{ "EBX" },
855	{ "ESP" },
856	{ "EBP" },
857	{ "ESI" },
858	{ "EDI" },
859	{ "R8D" },
860	{ "R9D" },
861	{ "R10D" },
862	{ "R11D" },
863	{ "R12D" },
864	{ "R13D" },
865	{ "R14D" },
866	{ "R15D" },
867
868	{ "RAX" },
869	{ "RCX" },
870	{ "RDX" },
871	{ "RBX" },
872	{ "RSP" },
873	{ "RBP" },
874	{ "RSI" },
875	{ "RDI" },
876	{ "R8" },
877	{ "R9" },
878	{ "R10" },
879	{ "R11" },
880	{ "R12" },
881	{ "R13" },
882	{ "R14" },
883	{ "R15" },
884
885	{ "OZ_RAX" },
886	{ "OZ_RCX" },
887	{ "OZ_RDX" },
888	{ "OZ_RBX" },
889	{ "OZ_RSP" },
890	{ "OZ_RBP" },
891	{ "OZ_RSI" },
892	{ "OZ_RDI" },
893	{ "OZ_R8" },
894	{ "OZ_R9" },
895	{ "OZ_R10" },
896	{ "OZ_R11" },
897	{ "OZ_R12" },
898	{ "OZ_R13" },
899	{ "OZ_R14" },
900	{ "OZ_R15" },
901
902	{ "CR0" },
903	{ "CR4" },
904	{ "XCR0" },
905
906	{ "FCW" },
907	{ "FSW" },
908	{ "FTW" },
909	{ "FOP" },
910	{ "FPUIP" },
911	{ "FPUCS" },
912	{ "FPUDP" },
913	{ "FPUDS" },
914	{ "MXCSR" },
915	{ "ST0" },
916	{ "ST1" },
917	{ "ST2" },
918	{ "ST3" },
919	{ "ST4" },
920	{ "ST5" },
921	{ "ST6" },
922	{ "ST7" },
923	{ "MM0" },
924	{ "MM1" },
925	{ "MM2" },
926	{ "MM3" },
927	{ "MM4" },
928	{ "MM5" },
929	{ "MM6" },
930	{ "MM7" },
931	{ "XMM0" },
932	{ "XMM1" },
933	{ "XMM2" },
934	{ "XMM3" },
935	{ "XMM4" },
936	{ "XMM5" },
937	{ "XMM6" },
938	{ "XMM7" },
939	{ "XMM8" },
940	{ "XMM9" },
941	{ "XMM10" },
942	{ "XMM11" },
943	{ "XMM12" },
944	{ "XMM13" },
945	{ "XMM14" },
946	{ "XMM15" },
947	{ "XMM0_LO" },
948	{ "XMM1_LO" },
949	{ "XMM2_LO" },
950	{ "XMM3_LO" },
951	{ "XMM4_LO" },
952	{ "XMM5_LO" },
953	{ "XMM6_LO" },
954	{ "XMM7_LO" },
955	{ "XMM8_LO" },
956	{ "XMM9_LO" },
957	{ "XMM10_LO" },
958	{ "XMM11_LO" },
959	{ "XMM12_LO" },
960	{ "XMM13_LO" },
961	{ "XMM14_LO" },
962	{ "XMM15_LO" },
963	{ "XMM0_HI" },
964	{ "XMM1_HI" },
965	{ "XMM2_HI" },
966	{ "XMM3_HI" },
967	{ "XMM4_HI" },
968	{ "XMM5_HI" },
969	{ "XMM6_HI" },
970	{ "XMM7_HI" },
971	{ "XMM8_HI" },
972	{ "XMM9_HI" },
973	{ "XMM10_HI" },
974	{ "XMM11_HI" },
975	{ "XMM12_HI" },
976	{ "XMM13_HI" },
977	{ "XMM14_HI" },
978	{ "XMM15_HI" },
979	{ "XMM0_LO_ZX" },
980	{ "XMM1_LO_ZX" },
981	{ "XMM2_LO_ZX" },
982	{ "XMM3_LO_ZX" },
983	{ "XMM4_LO_ZX" },
984	{ "XMM5_LO_ZX" },
985	{ "XMM6_LO_ZX" },
986	{ "XMM7_LO_ZX" },
987	{ "XMM8_LO_ZX" },
988	{ "XMM9_LO_ZX" },
989	{ "XMM10_LO_ZX" },
990	{ "XMM11_LO_ZX" },
991	{ "XMM12_LO_ZX" },
992	{ "XMM13_LO_ZX" },
993	{ "XMM14_LO_ZX" },
994	{ "XMM15_LO_ZX" },
995	{ "XMM0_DW0" },
996	{ "XMM1_DW0" },
997	{ "XMM2_DW0" },
998	{ "XMM3_DW0" },
999	{ "XMM4_DW0" },
1000	{ "XMM5_DW0" },
1001	{ "XMM6_DW0" },
1002	{ "XMM7_DW0" },
1003	{ "XMM8_DW0" },
1004	{ "XMM9_DW0" },
1005	{ "XMM10_DW0" },
1006	{ "XMM11_DW0" },
1007	{ "XMM12_DW0" },
1008	{ "XMM13_DW0" },
1009	{ "XMM14_DW0" },
1010	{ "XMM15_DW0" },
1011	{ "XMM0_DW0_ZX" },
1012	{ "XMM1_DW0_ZX" },
1013	{ "XMM2_DW0_ZX" },
1014	{ "XMM3_DW0_ZX" },
1015	{ "XMM4_DW0_ZX" },
1016	{ "XMM5_DW0_ZX" },
1017	{ "XMM6_DW0_ZX" },
1018	{ "XMM7_DW0_ZX" },
1019	{ "XMM8_DW0_ZX" },
1020	{ "XMM9_DW0_ZX" },
1021	{ "XMM10_DW0_ZX" },
1022	{ "XMM11_DW0_ZX" },
1023	{ "XMM12_DW0_ZX" },
1024	{ "XMM13_DW0_ZX" },
1025	{ "XMM14_DW0_ZX" },
1026	{ "XMM15_DW0_ZX" },
1027	{ "YMM0" },
1028	{ "YMM1" },
1029	{ "YMM2" },
1030	{ "YMM3" },
1031	{ "YMM4" },
1032	{ "YMM5" },
1033	{ "YMM6" },
1034	{ "YMM7" },
1035	{ "YMM8" },
1036	{ "YMM9" },
1037	{ "YMM10" },
1038	{ "YMM11" },
1039	{ "YMM12" },
1040	{ "YMM13" },
1041	{ "YMM14" },
1042	{ "YMM15" },
1043
1044	{ "VALXCPT" },
1045	};
1046	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) >= BS3CG1DST_END);
1047	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
1048
1049	#endif
1050
1051	#if 0
1052	static const struct
1053	{
1054	uint8_t cbPrefixes;
1055	uint8_t abPrefixes[14];
1056	uint16_t fEffective;
1057	} g_aPrefixVariations[] =
1058	{
1059	{ 0, { 0x00 }, BS3CG1_PF_NONE },
1060
1061	{ 1, { P_OZ }, BS3CG1_PF_OZ },
1062	{ 1, { P_CS }, BS3CG1_PF_CS },
1063	{ 1, { P_DS }, BS3CG1_PF_DS },
1064	{ 1, { P_ES }, BS3CG1_PF_ES },
1065	{ 1, { P_FS }, BS3CG1_PF_FS },
1066	{ 1, { P_GS }, BS3CG1_PF_GS },
1067	{ 1, { P_SS }, BS3CG1_PF_SS },
1068	{ 1, { P_LK }, BS3CG1_PF_LK },
1069
1070	{ 2, { P_CS, P_OZ, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1071	{ 2, { P_DS, P_OZ, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1072	{ 2, { P_ES, P_OZ, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1073	{ 2, { P_FS, P_OZ, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1074	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1075	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1076	{ 2, { P_SS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1077
1078	{ 2, { P_OZ, P_CS, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1079	{ 2, { P_OZ, P_DS, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1080	{ 2, { P_OZ, P_ES, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1081	{ 2, { P_OZ, P_FS, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1082	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1083	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1084	{ 2, { P_OZ, P_SS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1085	};
1086
1087	static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1088	{
1089	/* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1090	/* [BS3CG1PFXKIND_MODRM] = */ 0,
1091	/* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ \| BS3CG1_PF_W,
1092	};
1093
1094	#endif
1095
1096
1097	/**
1098	* Checks if >= 16 byte SSE/AVX alignment are exempted for the exception type.
1099	*
1100	* @returns true / false.
1101	* @param enmXcptType The type to check.
1102	*/
1103	static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1104	{
1105	switch (enmXcptType)
1106	{
1107	case BS3CG1XCPTTYPE_4UA:
1108	case BS3CG1XCPTTYPE_5:
1109	return true;
1110	default:
1111	return false;
1112	}
1113	}
1114
1115
1116	/**
1117	* Inserts a 2-byte VEX prefix.
1118	*
1119	* @returns New offDst value.
1120	* @param pThis The state.
1121	* @param offDst The current instruction offset.
1122	* @param uVexL The VEX.L value.
1123	* @param uVexV The VEX.V value (caller inverted it already).
1124	* @param uVexR The VEX.R value (caller inverted it already).
1125	*/
1126	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
1127	uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
1128	{
1129	uint8_t b = uVexR << 7;
1130	b \|= uVexV << 3;
1131	b \|= uVexL << 2;
1132	switch (pThis->enmPrefixKind)
1133	{
1134	case BS3CG1PFXKIND_NO_F2_F3_66: b \|= 0; break;
1135	case BS3CG1PFXKIND_REQ_66: b \|= 1; break;
1136	case BS3CG1PFXKIND_REQ_F3: b \|= 2; break;
1137	case BS3CG1PFXKIND_REQ_F2: b \|= 3; break;
1138	default:
1139	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
1140	break;
1141	}
1142
1143	pThis->abCurInstr[offDst] = 0xc5; /* vex2 */
1144	pThis->abCurInstr[offDst + 1] = b;
1145	return offDst + 2;
1146	}
1147
1148
1149	/**
1150	* Inserts a 3-byte VEX prefix.
1151	*
1152	* @returns New offDst value.
1153	* @param pThis The state.
1154	* @param offDst The current instruction offset.
1155	* @param uVexL The VEX.L value.
1156	* @param uVexV The VEX.V value (caller inverted it already).
1157	* @param uVexR The VEX.R value (caller inverted it already).
1158	* @param uVexR The VEX.X value (caller inverted it already).
1159	* @param uVexR The VEX.B value (caller inverted it already).
1160	* @param uVexR The VEX.W value (straight).
1161	*/
1162	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
1163	uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
1164	{
1165	uint8_t b1;
1166	uint8_t b2;
1167	b1 = uVexR << 7;
1168	b1 \|= uVexX << 6;
1169	b1 \|= uVexB << 5;
1170	b1 \|= 1; /* VEX.mmmmm = 1/ /* @todo three byte opcode tables */
1171	b2 = uVexV << 3;
1172	b2 \|= uVexW << 7;
1173	b2 \|= uVexL << 2;
1174	switch (pThis->enmPrefixKind)
1175	{
1176	case BS3CG1PFXKIND_NO_F2_F3_66: b2 \|= 0; break;
1177	case BS3CG1PFXKIND_REQ_66: b2 \|= 1; break;
1178	case BS3CG1PFXKIND_REQ_F3: b2 \|= 2; break;
1179	case BS3CG1PFXKIND_REQ_F2: b2 \|= 3; break;
1180	default:
1181	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
1182	break;
1183	}
1184
1185	pThis->abCurInstr[offDst] = 0xc4; /* vex3 */
1186	pThis->abCurInstr[offDst + 1] = b1;
1187	pThis->abCurInstr[offDst + 2] = b2;
1188	return offDst + 3;
1189	}
1190
1191
1192	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1193	{
1194	switch (pThis->enmPrefixKind)
1195	{
1196	case BS3CG1PFXKIND_REQ_66:
1197	pThis->abCurInstr[offDst] = 0x66;
1198	break;
1199	case BS3CG1PFXKIND_REQ_F2:
1200	pThis->abCurInstr[offDst] = 0xf2;
1201	break;
1202	case BS3CG1PFXKIND_REQ_F3:
1203	pThis->abCurInstr[offDst] = 0xf3;
1204	break;
1205	default:
1206	return offDst;
1207	}
1208	return offDst + 1;
1209	}
1210
1211
1212	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1213	{
1214	switch (pThis->cbOpcodes)
1215	{
1216	case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1217	case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1218	case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1219	case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1220	return offDst + pThis->cbOpcodes;
1221
1222	default:
1223	BS3_ASSERT(0);
1224	return 0;
1225	}
1226	}
1227
1228
1229	/**
1230	* Cleans up state and context changes made by the encoder.
1231	*
1232	* @param pThis The state.
1233	*/
1234	static void BS3_NEAR_CODE Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1235	{
1236	/* Restore the DS registers in the contexts. */
1237	unsigned iRing = 4;
1238	while (iRing-- > 0)
1239	pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1240
1241	switch (pThis->enmEncoding)
1242	{
1243	/* Most encodings currently doesn't need any special cleaning up. */
1244	default:
1245	return;
1246	}
1247	}
1248
1249
1250	static unsigned BS3_NEAR_CODE Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1251	uint8_t cbOp, uint8_t cbMissalign, BS3CG1OPLOC enmLocation)
1252	{
1253	pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1254	pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1255	pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1256	pThis->aOperands[pThis->iRmOp].off = cbOp + cbMissalign;
1257
1258	if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1259	\|\| (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1260	{
1261	/*
1262	* 16-bit code doing 16-bit or 32-bit addressing,
1263	* or 32-bit code doing 16-bit addressing.
1264	*/
1265	unsigned iRing = 4;
1266	if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1267	while (iRing-- > 0)
1268	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1269	else
1270	while (iRing-- > 0)
1271	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel \| iRing;
1272	if (!fAddrOverride \|\| BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1273	{
1274	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /disp16/);
1275	(uint16_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1276	off += 2;
1277	}
1278	else
1279	{
1280	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1281	(uint32_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1282	off += 4;
1283	}
1284	}
1285	else
1286	{
1287	/*
1288	* 32-bit code doing 32-bit addressing,
1289	* or 64-bit code doing either 64-bit or 32-bit addressing.
1290	*/
1291	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1292	(uint32_t )&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMissalign;
1293
1294	/* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1295	if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1296	(uint32_t )&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1297	off += 4;
1298	}
1299
1300	/*
1301	* Fill the memory with 0xcc.
1302	*/
1303	switch (cbOp + cbMissalign)
1304	{
1305	case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; /* fall thru */
1306	case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; /* fall thru */
1307	case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; /* fall thru */
1308	case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; /* fall thru */
1309	case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; /* fall thru */
1310	case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; /* fall thru */
1311	case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; /* fall thru */
1312	case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; /* fall thru */
1313	case 0: break;
1314	default:
1315	{
1316	BS3CG1_DPRINTF(("Bs3MemSet(%p,%#x,%#x)\n", &pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign));
1317	Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign);
1318	break;
1319	}
1320	}
1321
1322	return off;
1323	}
1324
1325
1326	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(PBS3CG1STATE pThis, unsigned iEncoding)
1327	{
1328	unsigned off;
1329	/* Start by reg,reg encoding. */
1330	if (iEncoding == 0)
1331	{
1332	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1333	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1334	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1335	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1336	}
1337	else if (iEncoding == 1)
1338	{
1339	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1340	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1341	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM_RW);
1342	}
1343	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1344	{
1345	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1346	pThis->abCurInstr[0] = P_AZ;
1347	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1348	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM_RW);
1349	}
1350	else
1351	return 0;
1352	pThis->cbCurInstr = off;
1353	return iEncoding + 1;
1354	}
1355
1356
1357	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(PBS3CG1STATE pThis, unsigned iEncoding)
1358	{
1359	unsigned off;
1360	/* Start by reg,reg encoding. */
1361	if (iEncoding == 0)
1362	{
1363	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1364	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1365	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1366	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1367	}
1368	else if (iEncoding == 1)
1369	{
1370	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1371	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1372	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM);
1373	}
1374	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1375	{
1376	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1377	pThis->abCurInstr[0] = P_AZ;
1378	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1379	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM);
1380	}
1381	else
1382	return 0;
1383	pThis->cbCurInstr = off;
1384	return iEncoding + 1;
1385	}
1386
1387
1388	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(PBS3CG1STATE pThis, unsigned iEncoding)
1389	{
1390	unsigned off;
1391	unsigned cbOp;
1392	if (iEncoding == 0)
1393	{
1394	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1395	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1396	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1397	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1398	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1399	}
1400	else if (iEncoding == 1)
1401	{
1402	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1403	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1404	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1405	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp, 0,
1406	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1407	}
1408	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1409	{
1410	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1411	pThis->abCurInstr[0] = P_OZ;
1412	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1413	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1414	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1415	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1416	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1417	}
1418	else if (iEncoding == 3)
1419	{
1420	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1421	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1422	pThis->abCurInstr[0] = P_OZ;
1423	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1424	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xSI, cbOp, 0,
1425	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1426	}
1427	else if (iEncoding == 4)
1428	{
1429	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1430	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RDI;
1431	pThis->abCurInstr[0] = P_AZ;
1432	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1433	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, cbOp, 0,
1434	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1435	}
1436	else if (iEncoding == 5)
1437	{
1438	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1439	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1440	pThis->abCurInstr[0] = P_OZ;
1441	pThis->abCurInstr[1] = P_AZ;
1442	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1443	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xSI, cbOp, 0,
1444	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1445	}
1446	else if (iEncoding == 6 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1447	{
1448	cbOp = 8;
1449	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1450	pThis->abCurInstr[off++] = REX_W___;
1451	off = Bs3Cg1InsertOpcodes(pThis, off);
1452	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1453	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_RBX;
1454	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_RDX;
1455	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1456	}
1457	else
1458	return 0;
1459	pThis->aOperands[0].cbOp = cbOp;
1460	pThis->aOperands[1].cbOp = cbOp;
1461	pThis->cbOperand = cbOp;
1462	pThis->cbCurInstr = off;
1463	return iEncoding + 1;
1464	}
1465
1466
1467	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_Vss(PBS3CG1STATE pThis, unsigned iEncoding)
1468	{
1469	unsigned off;
1470	if (iEncoding == 0)
1471	{
1472	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1473	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1474	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_DW0;
1475	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0;
1476	}
1477	else if (iEncoding == 1)
1478	{
1479	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0;
1480	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1481	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 4, 0, BS3CG1OPLOC_MEM_RW);
1482	}
1483	else if (iEncoding == 2)
1484	{
1485	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0;
1486	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1487	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 4, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1488	}
1489	else
1490	return 0;
1491	pThis->cbCurInstr = off;
1492	return iEncoding + 1;
1493	}
1494
1495
1496	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_Vsd(PBS3CG1STATE pThis, unsigned iEncoding)
1497	{
1498	unsigned off;
1499	if (iEncoding == 0)
1500	{
1501	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1502	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1503	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1504	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1505	}
1506	else if (iEncoding == 1)
1507	{
1508	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1509	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1510	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1511	}
1512	else if (iEncoding == 2)
1513	{
1514	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1515	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1516	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1517	}
1518	else
1519	return 0;
1520	pThis->cbCurInstr = off;
1521	return iEncoding + 1;
1522	}
1523
1524
1525	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_Vps__OR__BS3CG1ENC_MODRM_Wpd_Vpd(PBS3CG1STATE pThis, unsigned iEncoding)
1526	{
1527	unsigned off;
1528	if (iEncoding == 0)
1529	{
1530	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1531	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1532	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1533	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1534	}
1535	else if (iEncoding == 1)
1536	{
1537	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1538	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1539	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM_RW);
1540	}
1541	else if (iEncoding == 2)
1542	{
1543	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1544	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1545	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1546	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1547	pThis->bAlignmentXcpt = X86_XCPT_GP;
1548	}
1549	else
1550	return 0;
1551	pThis->cbCurInstr = off;
1552	return iEncoding + 1;
1553	}
1554
1555
1556	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
1557	{
1558	unsigned off;
1559	if (iEncoding == 0)
1560	{
1561	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1562	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1563	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO_ZX;
1564	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1565	}
1566	else if (iEncoding == 1)
1567	{
1568	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1569	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1570	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1571	}
1572	else if (iEncoding == 2)
1573	{
1574	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1575	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1576	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1577	}
1578	else
1579	return 0;
1580	pThis->cbCurInstr = off;
1581	return iEncoding + 1;
1582	}
1583
1584
1585	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
1586	{
1587	unsigned off;
1588	if (iEncoding == 0)
1589	{
1590	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1591	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1592	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_HI;
1593	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1594	}
1595	else if (iEncoding == 1)
1596	{
1597	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1598	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 2);
1599	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM2_HI;
1600	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1601	}
1602	else
1603	return 0;
1604	pThis->cbCurInstr = off;
1605	return iEncoding + 1;
1606	}
1607
1608
1609	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
1610	{
1611	unsigned off;
1612	if (iEncoding == 0)
1613	{
1614	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1615	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1616	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM);
1617	}
1618	else if (iEncoding == 1)
1619	{
1620	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1621	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1622	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1623	}
1624	else
1625	return 0;
1626	pThis->cbCurInstr = off;
1627	return iEncoding + 1;
1628	}
1629
1630
1631	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
1632	{
1633	unsigned off;
1634	if (iEncoding == 0)
1635	{
1636	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1637	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1638	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1639	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_HI;
1640	}
1641	else if (iEncoding == 1)
1642	{
1643	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1644	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 2);
1645	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM2_LO;
1646	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_HI;
1647	}
1648	else
1649	return 0;
1650	pThis->cbCurInstr = off;
1651	return iEncoding + 1;
1652	}
1653
1654
1655	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
1656	{
1657	unsigned off;
1658	if (iEncoding == 0)
1659	{
1660	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_HI;
1661	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1662	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM);
1663	}
1664	else if (iEncoding == 1)
1665	{
1666	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_HI;
1667	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1668	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1669	}
1670	else
1671	return 0;
1672	pThis->cbCurInstr = off;
1673	return iEncoding + 1;
1674	}
1675
1676
1677	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
1678	{
1679	unsigned off;
1680	if (iEncoding == 0)
1681	{
1682	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1683	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1684	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1685	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1686	}
1687	else if (iEncoding == 1)
1688	{
1689	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1690	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1691	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM);
1692	}
1693	else if (iEncoding == 2)
1694	{
1695	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1696	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1697	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1698	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1699	pThis->bAlignmentXcpt = X86_XCPT_GP;
1700	}
1701	else
1702	return 0;
1703	pThis->cbCurInstr = off;
1704	return iEncoding + 1;
1705	}
1706
1707
1708	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_Wps__OR__BS3CG1ENC_MODRM_Vpd_Wpd(PBS3CG1STATE pThis,
1709	unsigned iEncoding)
1710	{
1711	unsigned off;
1712	if (iEncoding == 0)
1713	{
1714	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1715	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1716	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1717	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1718	}
1719	else if (iEncoding == 1)
1720	{
1721	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1722	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1723	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM);
1724	}
1725	else if (iEncoding == 2)
1726	{
1727	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1728	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1729	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1730	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1731	pThis->bAlignmentXcpt = X86_XCPT_GP;
1732	}
1733	else
1734	return 0;
1735	pThis->cbCurInstr = off;
1736	return iEncoding + 1;
1737	}
1738
1739
1740	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
1741	{
1742	unsigned off;
1743	if (iEncoding == 0)
1744	{
1745	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1746	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1747	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1748	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0_ZX;
1749	}
1750	else if (iEncoding == 1)
1751	{
1752	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0_ZX;
1753	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1754	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 4, 0, BS3CG1OPLOC_MEM);
1755	}
1756	else if (iEncoding == 2)
1757	{
1758	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0_ZX;
1759	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1760	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 4, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1761	}
1762	else
1763	return 0;
1764	pThis->cbCurInstr = off;
1765	return iEncoding + 1;
1766	}
1767
1768
1769	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd(PBS3CG1STATE pThis, unsigned iEncoding)
1770	{
1771	unsigned off;
1772	if (iEncoding == 0)
1773	{
1774	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1775	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1776	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1777	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO_ZX;
1778	}
1779	else if (iEncoding == 1)
1780	{
1781	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO_ZX;
1782	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1783	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM);
1784	}
1785	else if (iEncoding == 2)
1786	{
1787	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO_ZX;
1788	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1789	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1790	}
1791	else
1792	return 0;
1793	pThis->cbCurInstr = off;
1794	return iEncoding + 1;
1795	}
1796
1797
1798	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(PBS3CG1STATE pThis, unsigned iEncoding)
1799	{
1800	unsigned off;
1801	unsigned cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1802	if (iEncoding == 0)
1803	{
1804	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1805	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1806	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1807	}
1808	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1809	{
1810	cbOp = cbOp == 2 ? 4 : 2;
1811	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1812	pThis->abCurInstr[0] = P_OZ;
1813	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1814	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1815	}
1816	else if (iEncoding == 2)
1817	{
1818	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1819	pThis->abCurInstr[0] = P_AZ;
1820	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1821	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1822	}
1823	else if (iEncoding == 3)
1824	{
1825	cbOp = cbOp == 2 ? 4 : 2;
1826	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1827	pThis->abCurInstr[0] = P_AZ;
1828	pThis->abCurInstr[1] = P_OZ;
1829	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1830	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1831	}
1832	else
1833	return 0;
1834	pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
1835	pThis->cbOperand = cbOp;
1836	pThis->cbCurInstr = off;
1837	return iEncoding + 1;
1838	}
1839
1840
1841	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(PBS3CG1STATE pThis, unsigned iEncoding)
1842	{
1843	unsigned off;
1844	if (iEncoding == 0)
1845	{
1846	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1847	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1848	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1849	1, 0, BS3CG1OPLOC_MEM);
1850	}
1851	else
1852	return 0;
1853	pThis->cbCurInstr = off;
1854	return iEncoding + 1;
1855	}
1856
1857
1858	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(PBS3CG1STATE pThis, unsigned iEncoding)
1859	{
1860	unsigned off;
1861	if (iEncoding == 0)
1862	{
1863	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1864	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1865	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1866	4, 0, BS3CG1OPLOC_MEM);
1867	}
1868	else
1869	return 0;
1870	pThis->cbCurInstr = off;
1871	return iEncoding + 1;
1872	}
1873
1874
1875	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(PBS3CG1STATE pThis, unsigned iEncoding)
1876	{
1877	unsigned off;
1878	if (iEncoding == 0)
1879	{
1880	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1881	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1882	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1883	4, 0, BS3CG1OPLOC_MEM_RW);
1884	}
1885	else
1886	return 0;
1887	pThis->cbCurInstr = off;
1888	return iEncoding + 1;
1889	}
1890
1891
1892	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_MdWO(PBS3CG1STATE pThis, unsigned iEncoding)
1893	{
1894	unsigned off;
1895	if (iEncoding == 0)
1896	{
1897	/** @todo three by opcode needs some tweaking. */
1898	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
1899	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1900	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1901	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1902	4, 0, BS3CG1OPLOC_MEM_RW);
1903	}
1904	else if (iEncoding == 1)
1905	{
1906	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1907	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1908	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1909	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1910	4, 0, BS3CG1OPLOC_MEM_RW);
1911	}
1912	else if (iEncoding == 2)
1913	{
1914	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0x7 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1915	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1916	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1917	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1918	4, 0, BS3CG1OPLOC_MEM_RW);
1919	pThis->fInvalidEncoding = true;
1920	}
1921	else if (iEncoding == 3)
1922	{
1923	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1924	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1925	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1926	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1927	4, 0, BS3CG1OPLOC_MEM_RW);
1928	pThis->fInvalidEncoding = true;
1929	}
1930	else if (iEncoding == 4)
1931	{
1932	pThis->abCurInstr[0] = P_OZ;
1933	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1934	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1935	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1936	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1937	4, 0, BS3CG1OPLOC_MEM_RW);
1938	pThis->fInvalidEncoding = true;
1939	}
1940	else if (iEncoding == 5)
1941	{
1942	pThis->abCurInstr[0] = P_RZ;
1943	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1944	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1945	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1946	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1947	4, 0, BS3CG1OPLOC_MEM_RW);
1948	pThis->fInvalidEncoding = true;
1949	}
1950	else if (iEncoding == 6)
1951	{
1952	pThis->abCurInstr[0] = P_RN;
1953	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1954	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1955	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1956	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1957	4, 0, BS3CG1OPLOC_MEM_RW);
1958	pThis->fInvalidEncoding = true;
1959	}
1960	else if (iEncoding == 7)
1961	{
1962	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
1963	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1964	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1965	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1966	4, 0, BS3CG1OPLOC_MEM_RW);
1967	}
1968	#if ARCH_BITS == 64
1969	else if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1970	{
1971	if (iEncoding == 8)
1972	{
1973	pThis->abCurInstr[0] = REX_____;
1974	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1975	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1976	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1977	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1978	4, 0, BS3CG1OPLOC_MEM_RW);
1979	pThis->fInvalidEncoding = true;
1980	}
1981	else
1982	return 0;
1983	}
1984	#endif
1985	else
1986	return 0;
1987	pThis->cbCurInstr = off;
1988	return iEncoding + 1;
1989	}
1990
1991
1992	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MqWO_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
1993	{
1994	unsigned off;
1995	if (iEncoding == 0)
1996	{
1997	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1998	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1999	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
2000	}
2001	else if (iEncoding == 1)
2002	{
2003	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
2004	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2005	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
2006	}
2007	else
2008	return 0;
2009	pThis->cbCurInstr = off;
2010	return iEncoding + 1;
2011	}
2012
2013
2014	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
2015	{
2016	unsigned off;
2017	if (iEncoding == 0)
2018	{
2019	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2020	pThis->cbCurInstr = off;
2021	iEncoding++;
2022	}
2023	else
2024	return 0;
2025	return iEncoding + 1;
2026	}
2027
2028
2029	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
2030	{
2031	unsigned off;
2032	if (iEncoding == 0)
2033	{
2034	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2035	pThis->aOperands[1].off = (uint8_t)off;
2036	pThis->abCurInstr[off++] = 0xff;
2037	pThis->cbCurInstr = off;
2038	}
2039	else
2040	return 0;
2041	return iEncoding + 1;
2042	}
2043
2044
2045	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
2046	{
2047	unsigned off;
2048	if (iEncoding == 0)
2049	{
2050	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2051	pThis->aOperands[1].off = (uint8_t)off;
2052	if (BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2053	{
2054	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
2055	off += 2;
2056	pThis->aOperands[0].cbOp = 2;
2057	pThis->aOperands[1].cbOp = 2;
2058	pThis->cbOperand = 2;
2059	}
2060	else
2061	{
2062	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2063	off += 4;
2064	pThis->aOperands[0].cbOp = 4;
2065	pThis->aOperands[1].cbOp = 4;
2066	pThis->cbOperand = 4;
2067	}
2068	}
2069	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
2070	{
2071	pThis->abCurInstr[0] = P_OZ;
2072	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2073	pThis->aOperands[1].off = (uint8_t)off;
2074	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2075	{
2076	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
2077	off += 2;
2078	pThis->aOperands[0].cbOp = 2;
2079	pThis->aOperands[1].cbOp = 2;
2080	pThis->cbOperand = 2;
2081	}
2082	else
2083	{
2084	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2085	off += 4;
2086	pThis->aOperands[0].cbOp = 4;
2087	pThis->aOperands[1].cbOp = 4;
2088	pThis->cbOperand = 4;
2089	}
2090	}
2091	else if (iEncoding == 2 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
2092	{
2093	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2094	pThis->abCurInstr[off++] = REX_W___;
2095	off = Bs3Cg1InsertOpcodes(pThis, off);
2096	pThis->aOperands[1].off = (uint8_t)off;
2097	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2098	off += 4;
2099	pThis->aOperands[0].cbOp = 8;
2100	pThis->aOperands[1].cbOp = 4;
2101	pThis->cbOperand = 8;
2102	}
2103	else
2104	return 0;
2105	pThis->cbCurInstr = off;
2106	return iEncoding + 1;
2107	}
2108
2109
2110	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
2111	{
2112	unsigned off;
2113	if (iEncoding < 8)
2114	{
2115	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2116	off = Bs3Cg1InsertOpcodes(pThis, off);
2117	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
2118	}
2119	else if (iEncoding < 16)
2120	{
2121	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2122	off = Bs3Cg1InsertOpcodes(pThis, off);
2123	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding);
2124	}
2125	else
2126	return 0;
2127	pThis->cbCurInstr = off;
2128
2129	return iEncoding + 1;
2130	}
2131
2132
2133	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
2134	{
2135	unsigned off;
2136	if (iEncoding < 3)
2137	{
2138	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2139	off = Bs3Cg1InsertOpcodes(pThis, off);
2140	pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
2141	if (iEncoding >= 1)
2142	pThis->abCurInstr[off++] = 0x7f;
2143	if (iEncoding == 2)
2144	{
2145	pThis->abCurInstr[off++] = 0x5f;
2146	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2147	{
2148	pThis->abCurInstr[off++] = 0x3f;
2149	pThis->abCurInstr[off++] = 0x1f;
2150	}
2151	}
2152	}
2153	else
2154	return 0;
2155	pThis->cbCurInstr = off;
2156	return iEncoding + 1;
2157	}
2158
2159
2160	/**
2161	* Encodes the next instruction.
2162	*
2163	* @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
2164	* that there are no more encodings to test.
2165	* @param pThis The state.
2166	* @param iEncoding The encoding to produce. Meaning is specific to
2167	* each BS3CG1ENC_XXX value and should be considered
2168	* internal.
2169	*/
2170	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
2171	{
2172	pThis->bAlignmentXcpt = UINT8_MAX;
2173
2174	switch (pThis->enmEncoding)
2175	{
2176	case BS3CG1ENC_MODRM_Eb_Gb:
2177	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(pThis, iEncoding);
2178	case BS3CG1ENC_MODRM_Gb_Eb:
2179	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(pThis, iEncoding);
2180	case BS3CG1ENC_MODRM_Gv_Ev:
2181	case BS3CG1ENC_MODRM_Ev_Gv:
2182	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(pThis, iEncoding);
2183
2184	case BS3CG1ENC_MODRM_Wss_Vss:
2185	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_Vss(pThis, iEncoding);
2186	case BS3CG1ENC_MODRM_Wsd_Vsd:
2187	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_Vsd(pThis, iEncoding);
2188	case BS3CG1ENC_MODRM_Wps_Vps:
2189	case BS3CG1ENC_MODRM_Wpd_Vpd:
2190	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_Vps__OR__BS3CG1ENC_MODRM_Wpd_Vpd(pThis, iEncoding);
2191	case BS3CG1ENC_MODRM_WqZxReg_Vq:
2192	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_Vq(pThis, iEncoding);
2193
2194	case BS3CG1ENC_MODRM_Vq_UqHi:
2195	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(pThis, iEncoding);
2196	case BS3CG1ENC_MODRM_Vq_Mq:
2197	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_Mq(pThis, iEncoding);
2198	case BS3CG1ENC_MODRM_VqHi_Uq:
2199	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Uq(pThis, iEncoding);
2200	case BS3CG1ENC_MODRM_VqHi_Mq:
2201	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VqHi_Mq(pThis, iEncoding);
2202	case BS3CG1ENC_MODRM_Vdq_Wdq:
2203	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(pThis, iEncoding);
2204	case BS3CG1ENC_MODRM_Vpd_Wpd:
2205	case BS3CG1ENC_MODRM_Vps_Wps:
2206	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_Wps__OR__BS3CG1ENC_MODRM_Vpd_Wpd(pThis, iEncoding);
2207	case BS3CG1ENC_MODRM_VssZxReg_Wss:
2208	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(pThis, iEncoding);
2209	case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
2210	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd(pThis, iEncoding);
2211
2212	case BS3CG1ENC_MODRM_Gv_Ma:
2213	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(pThis, iEncoding);
2214
2215	case BS3CG1ENC_MODRM_MbRO:
2216	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(pThis, iEncoding);
2217	case BS3CG1ENC_MODRM_MdRO:
2218	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(pThis, iEncoding);
2219	case BS3CG1ENC_MODRM_MdWO:
2220	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(pThis, iEncoding);
2221	case BS3CG1ENC_VEX_MODRM_MdWO:
2222	return Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_MdWO(pThis, iEncoding);
2223	case BS3CG1ENC_MODRM_MqWO_Vq:
2224	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MqWO_Vq(pThis, iEncoding);
2225
2226	case BS3CG1ENC_FIXED:
2227	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(pThis, iEncoding);
2228	case BS3CG1ENC_FIXED_AL_Ib:
2229	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(pThis, iEncoding);
2230	case BS3CG1ENC_FIXED_rAX_Iz:
2231	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(pThis, iEncoding);
2232
2233	case BS3CG1ENC_MODRM_MOD_EQ_3:
2234	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(pThis, iEncoding);
2235	case BS3CG1ENC_MODRM_MOD_NE_3:
2236	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(pThis, iEncoding);
2237
2238	default:
2239	Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
2240	break;
2241	}
2242
2243
2244	return iEncoding;
2245	}
2246
2247
2248	/**
2249	* Prepares doing instruction encodings.
2250	*
2251	* This is in part specific to how the instruction is encoded, but generally it
2252	* sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
2253	* is called from within the loop.
2254	*
2255	* @returns Success indicator (true/false).
2256	* @param pThis The state.
2257	*/
2258	#define Bs3Cg1EncodePrep BS3_CMN_NM(Bs3Cg1EncodePrep)
2259	bool BS3_NEAR_CODE Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
2260	{
2261	unsigned iRing = 4;
2262	while (iRing-- > 0)
2263	pThis->aSavedSegRegs[iRing].ds = pThis->aInitialCtxs[iRing].ds;
2264
2265	pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
2266	pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
2267	pThis->fSameRingNotOkay = false;
2268	pThis->cbOperand = 0;
2269
2270	switch (pThis->enmEncoding)
2271	{
2272	case BS3CG1ENC_MODRM_Eb_Gb:
2273	pThis->iRmOp = 0;
2274	pThis->iRegOp = 1;
2275	pThis->aOperands[0].cbOp = 1;
2276	pThis->aOperands[1].cbOp = 1;
2277	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2278	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2279	break;
2280
2281	case BS3CG1ENC_MODRM_Ev_Gv:
2282	pThis->iRmOp = 0;
2283	pThis->iRegOp = 1;
2284	pThis->cbOperand = 2;
2285	pThis->aOperands[0].cbOp = 2;
2286	pThis->aOperands[1].cbOp = 2;
2287	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2288	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2289	break;
2290
2291	case BS3CG1ENC_MODRM_Gb_Eb:
2292	pThis->iRmOp = 1;
2293	pThis->iRegOp = 0;
2294	pThis->aOperands[0].cbOp = 1;
2295	pThis->aOperands[1].cbOp = 1;
2296	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2297	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2298	break;
2299
2300	case BS3CG1ENC_MODRM_Gv_Ev:
2301	pThis->iRmOp = 1;
2302	pThis->iRegOp = 0;
2303	pThis->cbOperand = 2;
2304	pThis->aOperands[0].cbOp = 2;
2305	pThis->aOperands[1].cbOp = 2;
2306	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2307	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2308	break;
2309
2310	case BS3CG1ENC_MODRM_Gv_Ma:
2311	pThis->iRmOp = 1;
2312	pThis->iRegOp = 0;
2313	pThis->cbOperand = 2;
2314	pThis->aOperands[0].cbOp = 2;
2315	pThis->aOperands[1].cbOp = 4;
2316	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2317	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
2318	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2319	break;
2320
2321	case BS3CG1ENC_MODRM_Wss_Vss:
2322	pThis->iRmOp = 0;
2323	pThis->iRegOp = 1;
2324	pThis->aOperands[0].cbOp = 4;
2325	pThis->aOperands[1].cbOp = 4;
2326	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2327	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2328	break;
2329
2330	case BS3CG1ENC_MODRM_Wsd_Vsd:
2331	case BS3CG1ENC_MODRM_WqZxReg_Vq:
2332	pThis->iRmOp = 0;
2333	pThis->iRegOp = 1;
2334	pThis->aOperands[0].cbOp = 8;
2335	pThis->aOperands[1].cbOp = 8;
2336	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2337	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2338	break;
2339
2340	case BS3CG1ENC_MODRM_Wps_Vps:
2341	case BS3CG1ENC_MODRM_Wpd_Vpd:
2342	pThis->iRmOp = 0;
2343	pThis->iRegOp = 1;
2344	pThis->aOperands[0].cbOp = 16;
2345	pThis->aOperands[1].cbOp = 16;
2346	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2347	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2348	break;
2349
2350	case BS3CG1ENC_MODRM_Vdq_Wdq:
2351	pThis->iRmOp = 1;
2352	pThis->iRegOp = 0;
2353	pThis->aOperands[0].cbOp = 16;
2354	pThis->aOperands[1].cbOp = 16;
2355	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2356	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2357	break;
2358
2359	case BS3CG1ENC_MODRM_Vpd_Wpd:
2360	case BS3CG1ENC_MODRM_Vps_Wps:
2361	pThis->iRmOp = 1;
2362	pThis->iRegOp = 0;
2363	pThis->aOperands[0].cbOp = 16;
2364	pThis->aOperands[1].cbOp = 16;
2365	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2366	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2367	break;
2368
2369	case BS3CG1ENC_MODRM_Vq_UqHi:
2370	case BS3CG1ENC_MODRM_VqHi_Uq:
2371	pThis->iRmOp = 1;
2372	pThis->iRegOp = 0;
2373	pThis->aOperands[0].cbOp = 8;
2374	pThis->aOperands[1].cbOp = 8;
2375	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2376	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2377	break;
2378
2379	case BS3CG1ENC_MODRM_Vq_Mq:
2380	case BS3CG1ENC_MODRM_VqHi_Mq:
2381	pThis->iRmOp = 1;
2382	pThis->iRegOp = 0;
2383	pThis->aOperands[0].cbOp = 8;
2384	pThis->aOperands[1].cbOp = 8;
2385	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2386	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
2387	break;
2388
2389	case BS3CG1ENC_MODRM_VssZxReg_Wss:
2390	pThis->iRmOp = 1;
2391	pThis->iRegOp = 0;
2392	pThis->aOperands[0].cbOp = 4;
2393	pThis->aOperands[1].cbOp = 4;
2394	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2395	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2396	break;
2397
2398	case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
2399	pThis->iRmOp = 1;
2400	pThis->iRegOp = 0;
2401	pThis->aOperands[0].cbOp = 8;
2402	pThis->aOperands[1].cbOp = 8;
2403	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2404	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2405	break;
2406
2407	case BS3CG1ENC_MODRM_MbRO:
2408	pThis->iRmOp = 0;
2409	pThis->aOperands[0].cbOp = 1;
2410	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
2411	break;
2412
2413	case BS3CG1ENC_MODRM_MdRO:
2414	pThis->iRmOp = 0;
2415	pThis->aOperands[0].cbOp = 4;
2416	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
2417	break;
2418
2419	case BS3CG1ENC_MODRM_MdWO:
2420	case BS3CG1ENC_VEX_MODRM_MdWO:
2421	pThis->iRmOp = 0;
2422	pThis->aOperands[0].cbOp = 4;
2423	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_RW;
2424	break;
2425
2426	case BS3CG1ENC_MODRM_MqWO_Vq:
2427	pThis->iRmOp = 0;
2428	pThis->iRegOp = 1;
2429	pThis->aOperands[0].cbOp = 8;
2430	pThis->aOperands[1].cbOp = 8;
2431	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_RW;
2432	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2433	break;
2434
2435	case BS3CG1ENC_FIXED:
2436	/* nothing to do here */
2437	break;
2438
2439	case BS3CG1ENC_FIXED_AL_Ib:
2440	pThis->aOperands[0].cbOp = 1;
2441	pThis->aOperands[1].cbOp = 1;
2442	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2443	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
2444	pThis->aOperands[0].idxField = BS3CG1DST_AL;
2445	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2446	break;
2447
2448	case BS3CG1ENC_FIXED_rAX_Iz:
2449	pThis->aOperands[0].cbOp = 2;
2450	pThis->aOperands[1].cbOp = 2;
2451	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2452	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
2453	pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
2454	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2455	break;
2456
2457	case BS3CG1ENC_MODRM_MOD_EQ_3:
2458	case BS3CG1ENC_MODRM_MOD_NE_3:
2459	/* Unused or invalid instructions mostly. */
2460	break;
2461
2462	default:
2463	Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
2464	pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
2465	return false;
2466	}
2467	return true;
2468	}
2469
2470
2471	/**
2472	* Calculates the appropriate non-intel invalid instruction encoding.
2473	*
2474	* @returns the encoding to use instead.
2475	* @param enmEncoding The intel invalid instruction encoding.
2476	*/
2477	static BS3CG1ENC Bs3Cg1CalcNoneIntelInvalidEncoding(BS3CG1ENC enmEncoding)
2478	{
2479	switch (enmEncoding)
2480	{
2481	case BS3CG1ENC_MODRM_Gb_Eb:
2482	case BS3CG1ENC_MODRM_Gv_Ma:
2483	case BS3CG1ENC_FIXED:
2484	return BS3CG1ENC_FIXED;
2485	default:
2486	Bs3TestFailedF("Bs3Cg1CalcNoneIntelInvalidEncoding: Unsupported encoding: %d\n", enmEncoding);
2487	return BS3CG1ENC_FIXED;
2488	}
2489	}
2490
2491
2492	/**
2493	* Sets up SSE and maybe AVX.
2494	*
2495	* @returns true (if successful, false if not and the SSE instructions ends up
2496	* being invalid).
2497	* @param pThis The state.
2498	*/
2499	static bool BS3_NEAR_CODE Bs3Cg3SetupSseAndAvx(PBS3CG1STATE pThis)
2500	{
2501	if (!pThis->fWorkExtCtx)
2502	{
2503	unsigned i;
2504	uint32_t cr0 = ASMGetCR0();
2505	uint32_t cr4 = ASMGetCR4();
2506
2507	cr0 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
2508	cr0 \|= X86_CR0_NE;
2509	ASMSetCR0(cr0);
2510	if (pThis->pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
2511	{
2512	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE;
2513	ASMSetCR4(cr4);
2514	ASMSetXcr0(pThis->pExtCtx->fXcr0Nominal);
2515	}
2516	else
2517	{
2518	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT;
2519	ASMSetCR4(cr4);
2520	}
2521
2522	for (i = 0; i < RT_ELEMENTS(pThis->aInitialCtxs); i++)
2523	{
2524	pThis->aInitialCtxs[i].cr0.u32 = cr0;
2525	pThis->aInitialCtxs[i].cr4.u32 = cr4;
2526	}
2527	pThis->fWorkExtCtx = true;
2528	}
2529
2530	return true;
2531	}
2532
2533
2534	/**
2535	* Next CPU configuration to test the current instruction in.
2536	*
2537	* This is for testing FPU, SSE and AVX instructions with the various lazy state
2538	* load and enable bits in different configurations to ensure we're getting the
2539	* right response.
2540	*
2541	* This also cleans up the CPU and test driver state.
2542	*
2543	* @returns true if we're to do another round, false if we're done.
2544	* @param pThis The state.
2545	* @param iCpuSetup The current CPU setup number.
2546	* @param pfInvalidInstr Where to indicate whether the setup causes an
2547	* invalid instruction or not. This is also used as
2548	* input to avoid unnecessary CPUID work.
2549	*/
2550	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupNext(PBS3CG1STATE pThis, unsigned iCpuSetup, bool BS3_FAR *pfInvalidInstr)
2551	{
2552	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
2553	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
2554	return false;
2555
2556	switch (pThis->enmCpuTest)
2557	{
2558	case BS3CG1CPU_ANY:
2559	case BS3CG1CPU_GE_80186:
2560	case BS3CG1CPU_GE_80286:
2561	case BS3CG1CPU_GE_80386:
2562	case BS3CG1CPU_GE_80486:
2563	case BS3CG1CPU_GE_Pentium:
2564	case BS3CG1CPU_CLFSH:
2565	case BS3CG1CPU_CLFLUSHOPT:
2566	return false;
2567
2568	case BS3CG1CPU_SSE:
2569	case BS3CG1CPU_SSE2:
2570	case BS3CG1CPU_SSE3:
2571	case BS3CG1CPU_AVX:
2572	case BS3CG1CPU_AVX2:
2573	if (iCpuSetup > 0 \|\| *pfInvalidInstr)
2574	{
2575	/** @todo do more configs here. */
2576	pThis->fWorkExtCtx = false;
2577	ASMSetCR0(ASMGetCR0() \| X86_CR0_EM \| X86_CR0_MP);
2578	ASMSetCR4(ASMGetCR4() & ~(X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE));
2579	return false;
2580	}
2581	return false;
2582
2583	default:
2584	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2585	return false;
2586	}
2587	}
2588
2589
2590	/**
2591	* Check if the instruction is supported by the CPU, possibly making state
2592	* adjustments to enable support for it.
2593	*
2594	* @returns true if supported, false if not.
2595	* @param pThis The state.
2596	*/
2597	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupFirst(PBS3CG1STATE pThis)
2598	{
2599	uint32_t fEax;
2600	uint32_t fEbx;
2601	uint32_t fEcx;
2602	uint32_t fEdx;
2603
2604	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
2605	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
2606	return false;
2607
2608	switch (pThis->enmCpuTest)
2609	{
2610	case BS3CG1CPU_ANY:
2611	return true;
2612
2613	case BS3CG1CPU_GE_80186:
2614	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80186)
2615	return true;
2616	return false;
2617
2618	case BS3CG1CPU_GE_80286:
2619	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286)
2620	return true;
2621	return false;
2622
2623	case BS3CG1CPU_GE_80386:
2624	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
2625	return true;
2626	return false;
2627
2628	case BS3CG1CPU_GE_80486:
2629	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
2630	return true;
2631	return false;
2632
2633	case BS3CG1CPU_GE_Pentium:
2634	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_Pentium)
2635	return true;
2636	return false;
2637
2638	case BS3CG1CPU_SSE:
2639	case BS3CG1CPU_SSE2:
2640	case BS3CG1CPU_SSE3:
2641	case BS3CG1CPU_AVX:
2642	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2643	{
2644	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
2645	switch (pThis->enmCpuTest)
2646	{
2647	case BS3CG1CPU_SSE:
2648	if (fEdx & X86_CPUID_FEATURE_EDX_SSE)
2649	return Bs3Cg3SetupSseAndAvx(pThis);
2650	return false;
2651	case BS3CG1CPU_SSE2:
2652	if (fEdx & X86_CPUID_FEATURE_EDX_SSE2)
2653	return Bs3Cg3SetupSseAndAvx(pThis);
2654	return false;
2655	case BS3CG1CPU_SSE3:
2656	if (fEcx & X86_CPUID_FEATURE_ECX_SSE3)
2657	return Bs3Cg3SetupSseAndAvx(pThis);
2658	return false;
2659	case BS3CG1CPU_AVX:
2660	if (fEcx & X86_CPUID_FEATURE_ECX_AVX)
2661	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
2662	return false;
2663	default: BS3_ASSERT(0); /* impossible */
2664	}
2665	}
2666	return false;
2667
2668	case BS3CG1CPU_AVX2:
2669	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2670	{
2671	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, &fEax, &fEbx, &fEcx, &fEdx);
2672	switch (pThis->enmCpuTest)
2673	{
2674	case BS3CG1CPU_AVX2:
2675	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2)
2676	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
2677	return false;
2678	default: BS3_ASSERT(0); return false; /* impossible */
2679	}
2680	}
2681	return false;
2682
2683	case BS3CG1CPU_CLFSH:
2684	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2685	{
2686	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
2687	if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
2688	return true;
2689	}
2690	return false;
2691
2692	case BS3CG1CPU_CLFLUSHOPT:
2693	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2694	{
2695	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, NULL, &fEbx, NULL, NULL);
2696	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
2697	return true;
2698	}
2699	return false;
2700
2701	default:
2702	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2703	return false;
2704	}
2705	}
2706
2707
2708
2709	/**
2710	* Checks the preconditions for a test.
2711	*
2712	* @returns true if the test be executed, false if not.
2713	* @param pThis The state.
2714	* @param pHdr The test header.
2715	*/
2716	static bool BS3_NEAR_CODE Bs3Cg1RunSelector(PBS3CG1STATE pThis, PCBS3CG1TESTHDR pHdr)
2717	{
2718
2719	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1);
2720	unsigned cbLeft = pHdr->cbSelector;
2721	while (cbLeft-- > 0)
2722	{
2723	switch (*pbCode++)
2724	{
2725	#define CASE_PRED(a_Pred, a_Expr) \
2726	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_TRUE: \
2727	if (!(a_Expr)) return false; \
2728	break; \
2729	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_FALSE: \
2730	if (a_Expr) return false; \
2731	break
2732	CASE_PRED(BS3CG1PRED_SIZE_O16, pThis->cbOperand == 2);
2733	CASE_PRED(BS3CG1PRED_SIZE_O32, pThis->cbOperand == 4);
2734	CASE_PRED(BS3CG1PRED_SIZE_O64, pThis->cbOperand == 8);
2735	CASE_PRED(BS3CG1PRED_RING_0, pThis->uCpl == 0);
2736	CASE_PRED(BS3CG1PRED_RING_1, pThis->uCpl == 1);
2737	CASE_PRED(BS3CG1PRED_RING_2, pThis->uCpl == 2);
2738	CASE_PRED(BS3CG1PRED_RING_3, pThis->uCpl == 3);
2739	CASE_PRED(BS3CG1PRED_RING_0_THRU_2, pThis->uCpl <= 2);
2740	CASE_PRED(BS3CG1PRED_RING_1_THRU_3, pThis->uCpl >= 1);
2741	CASE_PRED(BS3CG1PRED_CODE_64BIT, BS3_MODE_IS_64BIT_CODE(pThis->bMode));
2742	CASE_PRED(BS3CG1PRED_CODE_32BIT, BS3_MODE_IS_32BIT_CODE(pThis->bMode));
2743	CASE_PRED(BS3CG1PRED_CODE_16BIT, BS3_MODE_IS_16BIT_CODE(pThis->bMode));
2744	CASE_PRED(BS3CG1PRED_MODE_REAL, BS3_MODE_IS_RM_SYS(pThis->bMode));
2745	CASE_PRED(BS3CG1PRED_MODE_PROT, BS3_MODE_IS_PM_SYS(pThis->bMode));
2746	CASE_PRED(BS3CG1PRED_MODE_LONG, BS3_MODE_IS_64BIT_SYS(pThis->bMode));
2747	CASE_PRED(BS3CG1PRED_MODE_SMM, false);
2748	CASE_PRED(BS3CG1PRED_MODE_VMX, false);
2749	CASE_PRED(BS3CG1PRED_MODE_SVM, false);
2750	CASE_PRED(BS3CG1PRED_PAGING_ON, BS3_MODE_IS_PAGED(pThis->bMode));
2751	CASE_PRED(BS3CG1PRED_PAGING_OFF, !BS3_MODE_IS_PAGED(pThis->bMode));
2752	CASE_PRED(BS3CG1PRED_VENDOR_AMD, pThis->bCpuVendor == BS3CPUVENDOR_AMD);
2753	CASE_PRED(BS3CG1PRED_VENDOR_INTEL, pThis->bCpuVendor == BS3CPUVENDOR_INTEL);
2754	CASE_PRED(BS3CG1PRED_VENDOR_VIA, pThis->bCpuVendor == BS3CPUVENDOR_VIA);
2755
2756	#undef CASE_PRED
2757	default:
2758	return Bs3TestFailedF("Invalid selector opcode %#x!", pbCode[-1]);
2759	}
2760	}
2761
2762	return true;
2763	}
2764
2765
2766	#ifdef BS3CG1_DEBUG_CTX_MOD
2767	/**
2768	* Translates the operator into a string.
2769	*
2770	* @returns Read-only string pointer.
2771	* @param bOpcode The context modifier program opcode.
2772	*/
2773	static const char BS3_FAR * BS3_NEAR_CODE Bs3Cg1CtxOpToString(uint8_t bOpcode)
2774	{
2775	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2776	{
2777	case BS3CG1_CTXOP_ASSIGN: return "=";
2778	case BS3CG1_CTXOP_OR: return "\|=";
2779	case BS3CG1_CTXOP_AND: return "&=";
2780	case BS3CG1_CTXOP_AND_INV: return "&~=";
2781	default: return "?WTF?";
2782	}
2783	}
2784	#endif
2785
2786
2787	/**
2788	* Runs a context modifier program.
2789	*
2790	* @returns Success indicator (true/false).
2791	* @param pThis The state.
2792	* @param pCtx The context.
2793	* @param pHdr The program header.
2794	* @param off The program offset relative to the end of the header.
2795	* @param cb The program size.
2796	* @param pEflCtx The context to take undefined EFLAGS from. (This is NULL
2797	* if we're processing a input context modifier program.)
2798	* @param pbInstr Points to the first instruction byte. For storing
2799	* immediate operands during input context modification.
2800	* NULL for output contexts.
2801	*/
2802	static bool BS3_NEAR_CODE Bs3Cg1RunContextModifier(PBS3CG1STATE pThis, PBS3REGCTX pCtx, PCBS3CG1TESTHDR pHdr,
2803	unsigned off, unsigned cb,
2804	PCBS3REGCTX pEflCtx, uint8_t BS3_FAR *pbInstr)
2805	{
2806	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1) + off;
2807	int cbLeft = cb;
2808	while (cbLeft-- > 0)
2809	{
2810	/*
2811	* Decode the instruction.
2812	*/
2813	uint8_t const bOpcode = *pbCode++;
2814	unsigned cbValue;
2815	unsigned cbDst;
2816	BS3CG1DST idxField;
2817	BS3PTRUNION PtrField;
2818
2819	/* Expand the destiation field (can be escaped). */
2820	switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
2821	{
2822	case BS3CG1_CTXOP_OP1:
2823	idxField = pThis->aOperands[0].idxField;
2824	if (idxField == BS3CG1DST_INVALID)
2825	idxField = BS3CG1DST_OP1;
2826	break;
2827
2828	case BS3CG1_CTXOP_OP2:
2829	idxField = pThis->aOperands[1].idxField;
2830	if (idxField == BS3CG1DST_INVALID)
2831	idxField = BS3CG1DST_OP2;
2832	break;
2833
2834	case BS3CG1_CTXOP_EFL:
2835	idxField = BS3CG1DST_EFL;
2836	break;
2837
2838	case BS3CG1_CTXOP_DST_ESC:
2839	if (cbLeft-- > 0)
2840	{
2841	idxField = (BS3CG1DST)*pbCode++;
2842	if (idxField <= BS3CG1DST_OP4)
2843	{
2844	if (idxField > BS3CG1DST_INVALID)
2845	{
2846	uint8_t idxField2 = pThis->aOperands[idxField - BS3CG1DST_OP1].idxField;
2847	if (idxField2 != BS3CG1DST_INVALID)
2848	idxField = idxField2;
2849	break;
2850	}
2851	}
2852	else if (idxField < BS3CG1DST_END)
2853	break;
2854	return Bs3TestFailedF("Malformed context instruction: idxField=%d", idxField);
2855	}
2856	/* fall thru */
2857	default:
2858	return Bs3TestFailed("Malformed context instruction: Destination");
2859	}
2860
2861
2862	/* Expand value size (can be escaped). */
2863	switch (bOpcode & BS3CG1_CTXOP_SIZE_MASK)
2864	{
2865	case BS3CG1_CTXOP_1_BYTE: cbValue = 1; break;
2866	case BS3CG1_CTXOP_2_BYTES: cbValue = 2; break;
2867	case BS3CG1_CTXOP_4_BYTES: cbValue = 4; break;
2868	case BS3CG1_CTXOP_8_BYTES: cbValue = 8; break;
2869	case BS3CG1_CTXOP_16_BYTES: cbValue = 16; break;
2870	case BS3CG1_CTXOP_32_BYTES: cbValue = 32; break;
2871	case BS3CG1_CTXOP_12_BYTES: cbValue = 12; break;
2872	case BS3CG1_CTXOP_SIZE_ESC:
2873	if (cbLeft-- > 0)
2874	{
2875	cbValue = *pbCode++;
2876	if (cbValue)
2877	break;
2878	}
2879	/* fall thru */
2880	default:
2881	return Bs3TestFailed("Malformed context instruction: size");
2882	}
2883
2884	/* Make sure there is enough instruction bytes for the value. */
2885	if (cbValue <= cbLeft)
2886	{ /* likely */ }
2887	else
2888	return Bs3TestFailedF("Malformed context instruction: %u bytes value, %u bytes left", cbValue, cbLeft);
2889
2890	/*
2891	* Do value processing specific to the target field size.
2892	*/
2893	cbDst = g_acbBs3Cg1DstFields[idxField];
2894	if (cbDst == BS3CG1DSTSIZE_OPERAND)
2895	cbDst = pThis->aOperands[idxField - BS3CG1DST_OP1].cbOp;
2896	else if (cbDst == BS3CG1DSTSIZE_OPERAND_SIZE_GRP)
2897	cbDst = pThis->cbOperand;
2898	if (cbDst <= 8)
2899	{
2900	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2901
2902	/*
2903	* Deal with fields up to 8-byte wide.
2904	*/
2905	/* Get the value. */
2906	uint64_t uValue;
2907	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT))
2908	switch (cbValue)
2909	{
2910	case 1: uValue = (int8_t const BS3_FAR )pbCode; break;
2911	case 2: uValue = (int16_t const BS3_FAR )pbCode; break;
2912	case 4: uValue = (int32_t const BS3_FAR )pbCode; break;
2913	default:
2914	if (cbValue >= 8)
2915	{
2916	uValue = (uint64_t const BS3_FAR )pbCode;
2917	break;
2918	}
2919	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2920	}
2921	else
2922	switch (cbValue)
2923	{
2924	case 1: uValue = (uint8_t const BS3_FAR )pbCode; break;
2925	case 2: uValue = (uint16_t const BS3_FAR )pbCode; break;
2926	case 4: uValue = (uint32_t const BS3_FAR )pbCode; break;
2927	default:
2928	if (cbValue >= 8)
2929	{
2930	uValue = (uint64_t const BS3_FAR )pbCode;
2931	break;
2932	}
2933	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2934	}
2935
2936	/* Find the field. */
2937	if (offField < sizeof(BS3REGCTX))
2938	PtrField.pu8 = (uint8_t BS3_FAR *)pCtx + offField;
2939	/* Non-register operands: */
2940	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2941	{
2942	unsigned const idxOp = idxField - BS3CG1DST_OP1;
2943
2944	switch (pThis->aOperands[idxOp].enmLocation)
2945	{
2946	case BS3CG1OPLOC_IMM:
2947	if (pbInstr)
2948	PtrField.pu8 = &pbInstr[pThis->aOperands[idxOp].off];
2949	else
2950	return Bs3TestFailedF("Immediate operand referenced in output context!");
2951	break;
2952
2953	case BS3CG1OPLOC_MEM:
2954	if (!pbInstr)
2955	return Bs3TestFailedF("Read only operand specified in output!");
2956	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2957	break;
2958
2959	case BS3CG1OPLOC_MEM_RW:
2960	if (pbInstr)
2961	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2962	else
2963	PtrField.pu8 = pThis->MemOp.ab;
2964	break;
2965
2966	default:
2967	if (pThis->enmEncoding != pThis->enmEncodingNonInvalid)
2968	goto l_advance_to_next;
2969	return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
2970	cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
2971	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2972	}
2973	}
2974	/* Special field: Copying in undefined EFLAGS from the result context. */
2975	else if (idxField == BS3CG1DST_EFL_UNDEF)
2976	{
2977	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN)
2978	return Bs3TestFailed("Invalid BS3CG1DST_EFL_UNDEF usage");
2979	PtrField.pu32 = &pCtx->rflags.u32;
2980	uValue = (*PtrField.pu32 & ~(uint32_t)uValue) \| (pEflCtx->rflags.u32 & (uint32_t)uValue);
2981	}
2982	/* Special field: Expected value (in/result) exception. */
2983	else if (idxField == BS3CG1DST_VALUE_XCPT)
2984	{
2985	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN \|\| cbDst != 1)
2986	return Bs3TestFailed("Invalid BS3CG1DST_VALUE_XCPT usage");
2987	PtrField.pu8 = &pThis->bValueXcpt;
2988	}
2989	/* FPU and FXSAVE format. */
2990	else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2991	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2992	{
2993	if (!pThis->fWorkExtCtx)
2994	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2995	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2996	}
2997	/** @todo other FPU fields and FPU state formats. */
2998	else
2999	return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
3000
3001	#ifdef BS3CG1_DEBUG_CTX_MOD
3002	switch (cbDst)
3003	{
3004	case 1:
3005	BS3CG1_DPRINTF(("dbg: modify %s: %#04RX8 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3006	*PtrField.pu8, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
3007	break;
3008	case 2:
3009	BS3CG1_DPRINTF(("dbg: modify %s: %#06RX16 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3010	*PtrField.pu16, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
3011	break;
3012	case 4:
3013	BS3CG1_DPRINTF(("dbg: modify %s: %#010RX32 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3014	*PtrField.pu32, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
3015	break;
3016	default:
3017	BS3CG1_DPRINTF(("dbg: modify %s: %#018RX64 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3018	*PtrField.pu64, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
3019	break;
3020	}
3021	#endif
3022
3023	/* Modify the field. */
3024	switch (cbDst)
3025	{
3026	case 1:
3027	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3028	{
3029	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu8 = (uint8_t)uValue; break;
3030	case BS3CG1_CTXOP_OR: *PtrField.pu8 \|= (uint8_t)uValue; break;
3031	case BS3CG1_CTXOP_AND: *PtrField.pu8 &= (uint8_t)uValue; break;
3032	case BS3CG1_CTXOP_AND_INV: *PtrField.pu8 &= ~(uint8_t)uValue; break;
3033	}
3034	break;
3035
3036	case 2:
3037	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3038	{
3039	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu16 = (uint16_t)uValue; break;
3040	case BS3CG1_CTXOP_OR: *PtrField.pu16 \|= (uint16_t)uValue; break;
3041	case BS3CG1_CTXOP_AND: *PtrField.pu16 &= (uint16_t)uValue; break;
3042	case BS3CG1_CTXOP_AND_INV: *PtrField.pu16 &= ~(uint16_t)uValue; break;
3043	}
3044	break;
3045
3046	case 4:
3047	if ((unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX))
3048	{
3049	PtrField.pu32[1] = 0;
3050	PtrField.pu64[1] = 0;
3051	}
3052	else if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
3053	PtrField.pu32[1] = 0;
3054	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3055	{
3056	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu32 = (uint32_t)uValue; break;
3057	case BS3CG1_CTXOP_OR: *PtrField.pu32 \|= (uint32_t)uValue; break;
3058	case BS3CG1_CTXOP_AND: *PtrField.pu32 &= (uint32_t)uValue; break;
3059	case BS3CG1_CTXOP_AND_INV: *PtrField.pu32 &= ~(uint32_t)uValue; break;
3060	}
3061	break;
3062
3063	case 8:
3064	if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
3065	PtrField.pu64[1] = 0;
3066	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3067	{
3068	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu64 = (uint64_t)uValue; break;
3069	case BS3CG1_CTXOP_OR: *PtrField.pu64 \|= (uint64_t)uValue; break;
3070	case BS3CG1_CTXOP_AND: *PtrField.pu64 &= (uint64_t)uValue; break;
3071	case BS3CG1_CTXOP_AND_INV: *PtrField.pu64 &= ~(uint64_t)uValue; break;
3072	}
3073	break;
3074
3075	default:
3076	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, expected 1, 2, 4, or 8", cbDst);
3077	}
3078
3079	#ifdef BS3CG1_DEBUG_CTX_MOD
3080	switch (cbDst)
3081	{
3082	case 1: BS3CG1_DPRINTF(("dbg: --> %s: %#04RX8\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu8)); break;
3083	case 2: BS3CG1_DPRINTF(("dbg: --> %s: %#06RX16\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu16)); break;
3084	case 4: BS3CG1_DPRINTF(("dbg: --> %s: %#010RX32\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu32)); break;
3085	default: BS3CG1_DPRINTF(("dbg: --> %s: %#018RX64\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu64)); break;
3086	}
3087	#endif
3088
3089	}
3090	/*
3091	* Deal with larger field (FPU, SSE, AVX, ...).
3092	*/
3093	else
3094	{
3095	union
3096	{
3097	X86FPUREG FpuReg;
3098	X86XMMREG XmmReg;
3099	X86YMMREG YmmReg;
3100	X86ZMMREG ZmmReg;
3101	uint8_t ab[sizeof(X86ZMMREG)];
3102	uint32_t au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
3103	} Value;
3104	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
3105
3106	if (!pThis->fWorkExtCtx)
3107	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
3108
3109	/* Copy the value into the union, doing the zero padding / extending. */
3110	Bs3MemCpy(&Value, pbCode, cbValue);
3111	if (cbValue < sizeof(Value))
3112	{
3113	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
3114	Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
3115	else
3116	Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
3117	}
3118
3119	/* Optimized access to XMM and STx registers. */
3120	if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
3121	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
3122	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
3123	/* Non-register operands: */
3124	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
3125	{
3126	unsigned const idxOp = idxField - BS3CG1DST_OP1;
3127	switch (pThis->aOperands[idxOp].enmLocation)
3128	{
3129	case BS3CG1OPLOC_MEM:
3130	if (!pbInstr)
3131	return Bs3TestFailedF("Read only operand specified in output!");
3132	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
3133	break;
3134
3135	case BS3CG1OPLOC_MEM_RW:
3136	if (pbInstr)
3137	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
3138	else
3139	PtrField.pu8 = pThis->MemOp.ab;
3140	break;
3141
3142	default:
3143	return Bs3TestFailedF("Internal error: Field %d (%d) @ %#x LB %u: enmLocation=%u off=%#x idxField=%u",
3144	idxField, idxOp, offField, cbDst, pThis->aOperands[idxOp].enmLocation,
3145	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
3146	}
3147	}
3148	/* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
3149	the state, so they need special handling. */
3150	else
3151	{
3152	return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
3153	}
3154
3155	if (PtrField.pb)
3156	{
3157	/* Modify the field / memory. */
3158	unsigned i;
3159	if (cbDst & 3)
3160	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
3161
3162	#ifdef BS3CG1_DEBUG_CTX_MOD
3163	BS3CG1_DPRINTF(("dbg: modify %s: %.Rhxs (LB %u) %s %.Rhxs (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3164	cbDst, PtrField.pb, cbDst, Bs3Cg1CtxOpToString(bOpcode), cbValue, Value.ab, cbValue));
3165	#endif
3166
3167	i = cbDst / 4;
3168	while (i-- > 0)
3169	{
3170	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3171	{
3172	case BS3CG1_CTXOP_ASSIGN: PtrField.pu32[i] = Value.au32[i]; break;
3173	case BS3CG1_CTXOP_OR: PtrField.pu32[i] \|= Value.au32[i]; break;
3174	case BS3CG1_CTXOP_AND: PtrField.pu32[i] &= Value.au32[i]; break;
3175	case BS3CG1_CTXOP_AND_INV: PtrField.pu32[i] &= ~Value.au32[i]; break;
3176	}
3177	}
3178
3179	#ifdef BS3CG1_DEBUG_CTX_MOD
3180	BS3CG1_DPRINTF(("dbg: --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
3181	#endif
3182	}
3183	}
3184
3185	/*
3186	* Advance to the next instruction.
3187	*/
3188	l_advance_to_next:
3189	pbCode += cbValue;
3190	cbLeft -= cbValue;
3191	}
3192
3193	return true;
3194	}
3195
3196
3197	/**
3198	* Checks the result of a run.
3199	*
3200	* @returns true if successful, false if not.
3201	* @param pThis The state.
3202	* @param bTestXcptExpected The exception causing the test code to stop
3203	* executing.
3204	* @param fInvalidEncodingPgFault Set if we've cut the instruction a byte
3205	* short and is expecting a \#PF on the page
3206	* boundrary rather than a \#UD. Only set if
3207	* fInvalidEncoding is also set.
3208	* @param iEncoding For error reporting.
3209	*/
3210	static bool BS3_NEAR_CODE Bs3Cg1CheckResult(PBS3CG1STATE pThis, uint8_t bTestXcptExpected,
3211	bool fInvalidEncodingPgFault, unsigned iEncoding)
3212	{
3213	unsigned iOperand;
3214
3215	/*
3216	* Check the exception state first.
3217	*/
3218	uint8_t bExpectedXcpt;
3219	uint8_t cbAdjustPc;
3220	if (!pThis->fInvalidEncoding)
3221	{
3222	bExpectedXcpt = pThis->bAlignmentXcpt;
3223	if (bExpectedXcpt == UINT8_MAX)
3224	bExpectedXcpt = pThis->bValueXcpt;
3225	if (bExpectedXcpt == UINT8_MAX)
3226	{
3227	cbAdjustPc = pThis->cbCurInstr;
3228	bExpectedXcpt = bTestXcptExpected;
3229	if (bTestXcptExpected == X86_XCPT_PF)
3230	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
3231	}
3232	else
3233	cbAdjustPc = 0;
3234	}
3235	else
3236	{
3237	cbAdjustPc = 0;
3238	if (!fInvalidEncodingPgFault)
3239	bExpectedXcpt = X86_XCPT_UD;
3240	else
3241	{
3242	bExpectedXcpt = X86_XCPT_PF;
3243	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
3244	}
3245	}
3246	if (RT_LIKELY( pThis->TrapFrame.bXcpt == bExpectedXcpt
3247	&& pThis->TrapFrame.Ctx.rip.u == pThis->Ctx.rip.u + cbAdjustPc))
3248	{
3249	/*
3250	* Check the register content.
3251	*/
3252	bool fOkay = Bs3TestCheckRegCtxEx(&pThis->TrapFrame.Ctx, &pThis->Ctx,
3253	cbAdjustPc, 0 /cbSpAdjust/, 0 /fExtraEfl/,
3254	pThis->pszMode, iEncoding);
3255
3256	/*
3257	* Check memory output operands.
3258	*/
3259	if (!pThis->fInvalidEncoding)
3260	{
3261	iOperand = pThis->cOperands;
3262	while (iOperand-- > 0)
3263	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
3264	{
3265	if (pThis->aOperands[iOperand].off)
3266	{
3267	BS3PTRUNION PtrUnion;
3268	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
3269	switch (pThis->aOperands[iOperand].cbOp)
3270	{
3271	case 1:
3272	if (*PtrUnion.pu8 == pThis->MemOp.ab[0])
3273	continue;
3274	Bs3TestFailedF("op%u: Wrote %#04RX8, expected %#04RX8",
3275	iOperand, *PtrUnion.pu8, pThis->MemOp.ab[0]);
3276	break;
3277	case 2:
3278	if (*PtrUnion.pu16 == pThis->MemOp.au16[0])
3279	continue;
3280	Bs3TestFailedF("op%u: Wrote %#06RX16, expected %#06RX16",
3281	iOperand, *PtrUnion.pu16, pThis->MemOp.au16[0]);
3282	break;
3283	case 4:
3284	if (*PtrUnion.pu32 == pThis->MemOp.au32[0])
3285	continue;
3286	Bs3TestFailedF("op%u: Wrote %#010RX32, expected %#010RX32",
3287	iOperand, *PtrUnion.pu32, pThis->MemOp.au32[0]);
3288	break;
3289	case 8:
3290	if (*PtrUnion.pu64 == pThis->MemOp.au64[0])
3291	continue;
3292	Bs3TestFailedF("op%u: Wrote %#018RX64, expected %#018RX64",
3293	iOperand, *PtrUnion.pu64, pThis->MemOp.au64[0]);
3294	break;
3295	default:
3296	if (Bs3MemCmp(PtrUnion.pb, pThis->MemOp.ab, pThis->aOperands[iOperand].cbOp) == 0)
3297	continue;
3298	Bs3TestFailedF("op%u: Wrote %.Rhxs, expected %.Rhxs",
3299	iOperand,
3300	pThis->aOperands[iOperand].cbOp, PtrUnion.pb,
3301	pThis->aOperands[iOperand].cbOp, pThis->MemOp.ab);
3302	break;
3303	}
3304	}
3305	else
3306	Bs3TestFailedF("op%u: off is zero\n", iOperand);
3307	fOkay = false;
3308	}
3309	}
3310
3311	/*
3312	* Check extended context if enabled.
3313	*/
3314	if (pThis->fWorkExtCtx)
3315	{
3316	PBS3EXTCTX pExpect = pThis->pExtCtx;
3317	PBS3EXTCTX pResult = pThis->pResultExtCtx;
3318	unsigned i;
3319	if ( pExpect->enmMethod == BS3EXTCTXMETHOD_XSAVE
3320	\|\| pExpect->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
3321	{
3322	/* Compare the x87 state, ASSUMING XCR0 bit 1 is set. */
3323	#define CHECK_FIELD(a_Field, a_szFmt) \
3324	if (pResult->Ctx.a_Field != pExpect->Ctx.a_Field) fOkay = Bs3TestFailedF(a_szFmt, pResult->Ctx.a_Field, pExpect->Ctx.a_Field)
3325	CHECK_FIELD(x87.FCW, "FCW: %#06x, expected %#06x");
3326	CHECK_FIELD(x87.FSW, "FSW: %#06x, expected %#06x");
3327	CHECK_FIELD(x87.FTW, "FTW: %#06x, expected %#06x");
3328	//CHECK_FIELD(x87.FOP, "FOP: %#06x, expected %#06x");
3329	//CHECK_FIELD(x87.FPUIP, "FPUIP: %#010RX32, expected %#010RX32");
3330	//CHECK_FIELD(x87.CS, "FPUCS: %#06x, expected %#06x");
3331	//CHECK_FIELD(x87.Rsrvd1, "Rsrvd1: %#06x, expected %#06x");
3332	//CHECK_FIELD(x87.DP, "FPUDP: %#010RX32, expected %#010RX32");
3333	//CHECK_FIELD(x87.DS, "FPUDS: %#06x, expected %#06x");
3334	//CHECK_FIELD(x87.Rsrvd2, "Rsrvd2: %#06x, expected %#06x");
3335	CHECK_FIELD(x87.MXCSR, "MXCSR: %#010RX32, expected %#010RX32");
3336	#undef CHECK_FIELD
3337	for (i = 0; i < RT_ELEMENTS(pExpect->Ctx.x87.aRegs); i++)
3338	if ( pResult->Ctx.x87.aRegs[i].au64[0] != pExpect->Ctx.x87.aRegs[i].au64[0]
3339	\|\| pResult->Ctx.x87.aRegs[i].au16[4] != pExpect->Ctx.x87.aRegs[i].au16[4])
3340	fOkay = Bs3TestFailedF("ST[%u]: %c m=%#RX64 e=%d, expected %c m=%#RX64 e=%d", i,
3341	pResult->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
3342	pResult->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
3343	pResult->Ctx.x87.aRegs[i].r80Ex.s.uExponent,
3344	pExpect->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
3345	pExpect->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
3346	pExpect->Ctx.x87.aRegs[i].r80Ex.s.uExponent);
3347	for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
3348	if ( pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
3349	\|\| pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
3350	fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
3351	pResult->Ctx.x87.aXMM[i].au64[1],
3352	pResult->Ctx.x87.aXMM[i].au64[0],
3353	pExpect->Ctx.x87.aXMM[i].au64[1],
3354	pExpect->Ctx.x87.aXMM[i].au64[0]);
3355	}
3356	else
3357	fOkay = Bs3TestFailedF("Unsupported extended CPU context method: %d", pExpect->enmMethod);
3358	}
3359
3360	/*
3361	* Done.
3362	*/
3363	if (fOkay)
3364	return true;
3365
3366	/*
3367	* Report failure.
3368	*/
3369	Bs3TestFailedF("ins#%RU32/test#%u: encoding #%u: %.*Rhxs%s",
3370	pThis->iInstr, pThis->iTest, iEncoding, pThis->cbCurInstr, pThis->abCurInstr,
3371	fInvalidEncodingPgFault ? " (cut short)" : "");
3372	}
3373	else
3374	Bs3TestFailedF("ins#%RU32/test#%u: bXcpt=%#x expected %#x; rip=%RX64 expected %RX64; encoding#%u: %.*Rhxs%s",
3375	pThis->iInstr, pThis->iTest,
3376	pThis->TrapFrame.bXcpt, bExpectedXcpt,
3377	pThis->TrapFrame.Ctx.rip.u, pThis->Ctx.rip.u + cbAdjustPc,
3378	iEncoding, pThis->cbCurInstr, pThis->abCurInstr, fInvalidEncodingPgFault ? " (cut short)" : "");
3379	Bs3TestPrintf("cpl=%u cbOperands=%u\n", pThis->uCpl, pThis->cbOperand);
3380
3381	/*
3382	* Display memory operands.
3383	*/
3384	for (iOperand = 0; iOperand < pThis->cOperands; iOperand++)
3385	{
3386	BS3PTRUNION PtrUnion;
3387	switch (pThis->aOperands[iOperand].enmLocation)
3388	{
3389	case BS3CG1OPLOC_CTX:
3390	{
3391	uint8_t idxField = pThis->aOperands[iOperand].idxField;
3392	unsigned offField = g_aoffBs3Cg1DstFields[idxField];
3393	if (offField <= sizeof(BS3REGCTX))
3394	PtrUnion.pb = (uint8_t BS3_FAR *)&pThis->Ctx + offField;
3395	else
3396	{
3397	Bs3TestPrintf("op%u: ctx%u: xxxx\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
3398	break;
3399	}
3400	switch (pThis->aOperands[iOperand].cbOp)
3401	{
3402	case 1: Bs3TestPrintf("op%u: ctx08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3403	case 2: Bs3TestPrintf("op%u: ctx16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3404	case 4: Bs3TestPrintf("op%u: ctx32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3405	case 8: Bs3TestPrintf("op%u: ctx64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3406	default:
3407	Bs3TestPrintf("op%u: ctx%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3408	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3409	break;
3410	}
3411	break;
3412	}
3413
3414	case BS3CG1OPLOC_IMM:
3415	PtrUnion.pb = &pThis->pbCodePg[pThis->aOperands[iOperand].off];
3416	switch (pThis->aOperands[iOperand].cbOp)
3417	{
3418	case 1: Bs3TestPrintf("op%u: imm08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3419	case 2: Bs3TestPrintf("op%u: imm16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3420	case 4: Bs3TestPrintf("op%u: imm32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3421	case 8: Bs3TestPrintf("op%u: imm64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3422	default:
3423	Bs3TestPrintf("op%u: imm%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3424	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3425	break;
3426	}
3427	break;
3428
3429	case BS3CG1OPLOC_MEM:
3430	case BS3CG1OPLOC_MEM_RW:
3431	if (pThis->aOperands[iOperand].off)
3432	{
3433	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
3434	switch (pThis->aOperands[iOperand].cbOp)
3435	{
3436	case 1: Bs3TestPrintf("op%u: result mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3437	case 2: Bs3TestPrintf("op%u: result mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3438	case 4: Bs3TestPrintf("op%u: result mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3439	case 8: Bs3TestPrintf("op%u: result mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3440	default:
3441	Bs3TestPrintf("op%u: result mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3442	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3443	break;
3444	}
3445	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
3446	{
3447	PtrUnion.pb = pThis->MemOp.ab;
3448	switch (pThis->aOperands[iOperand].cbOp)
3449	{
3450	case 1: Bs3TestPrintf("op%u: expect mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3451	case 2: Bs3TestPrintf("op%u: expect mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3452	case 4: Bs3TestPrintf("op%u: expect mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3453	case 8: Bs3TestPrintf("op%u: expect mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3454	default:
3455	Bs3TestPrintf("op%u: expect mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3456	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3457	break;
3458	}
3459	}
3460	}
3461	else
3462	Bs3TestPrintf("op%u: mem%u: zero off value!!\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
3463	break;
3464	}
3465	}
3466
3467	/*
3468	* Display contexts.
3469	*/
3470	Bs3TestPrintf("-- Expected context:\n");
3471	Bs3RegCtxPrint(&pThis->Ctx);
3472	if (pThis->fWorkExtCtx)
3473	Bs3TestPrintf("xcr0=%RX64\n", pThis->pExtCtx->fXcr0Saved);
3474	Bs3TestPrintf("-- Actual context:\n");
3475	Bs3TrapPrintFrame(&pThis->TrapFrame);
3476	if (pThis->fWorkExtCtx)
3477	Bs3TestPrintf("xcr0=%RX64\n", pThis->pResultExtCtx->fXcr0Saved);
3478	Bs3TestPrintf("\n");
3479	return false;
3480	}
3481
3482
3483	/**
3484	* Destroys the state, freeing all allocations and such.
3485	*
3486	* @param pThis The state.
3487	*/
3488	static void BS3_NEAR_CODE Bs3Cg1Destroy(PBS3CG1STATE pThis)
3489	{
3490	if (BS3_MODE_IS_PAGED(pThis->bMode))
3491	{
3492	#if ARCH_BITS != 16
3493	Bs3MemGuardedTestPageFree(pThis->pbCodePg);
3494	Bs3MemGuardedTestPageFree(pThis->pbDataPg);
3495	#endif
3496	}
3497	else
3498	{
3499	Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
3500	Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
3501	}
3502
3503	if (pThis->pExtCtx)
3504	Bs3MemFree(pThis->pExtCtx, pThis->pExtCtx->cb * 3);
3505
3506	pThis->pbCodePg = NULL;
3507	pThis->pbDataPg = NULL;
3508	pThis->pExtCtx = NULL;
3509	pThis->pResultExtCtx = NULL;
3510	pThis->pInitialExtCtx = NULL;
3511	}
3512
3513
3514	/**
3515	* Initializes the state.
3516	*
3517	* @returns Success indicator (true/false)
3518	* @param pThis The state.
3519	* @param bMode The mode being tested.
3520	*/
3521	bool BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1Init)(PBS3CG1STATE pThis, uint8_t bMode)
3522	{
3523	BS3MEMKIND const enmMemKind = BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL
3524	: !BS3_MODE_IS_64BIT_CODE(bMode) ? BS3MEMKIND_TILED : BS3MEMKIND_FLAT32;
3525	unsigned iRing;
3526	unsigned cb;
3527	unsigned i;
3528	uint64_t fFlags;
3529	PBS3EXTCTX pExtCtx;
3530
3531	Bs3MemSet(pThis, 0, sizeof(*pThis));
3532
3533	pThis->iFirstRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
3534	pThis->iEndRing = BS3_MODE_IS_RM_SYS(bMode) ? 1 : 4;
3535	pThis->bMode = bMode;
3536	pThis->pszMode = Bs3GetModeName(bMode);
3537	pThis->pszModeShort = Bs3GetModeNameShortLower(bMode);
3538	pThis->bCpuVendor = Bs3GetCpuVendor();
3539	pThis->pchMnemonic = g_achBs3Cg1Mnemonics;
3540	pThis->pabOperands = g_abBs3Cg1Operands;
3541	pThis->pabOpcodes = g_abBs3Cg1Opcodes;
3542	pThis->fAdvanceMnemonic = 1;
3543
3544	/* Allocate extended context structures. */
3545	cb = Bs3ExtCtxGetSize(&fFlags);
3546	pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 3);
3547	if (!pExtCtx)
3548	return Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 3);
3549	pThis->pExtCtx = pExtCtx;
3550	pThis->pResultExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb);
3551	pThis->pInitialExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb + cb);
3552
3553	Bs3ExtCtxInit(pThis->pExtCtx, cb, fFlags);
3554	Bs3ExtCtxInit(pThis->pResultExtCtx, cb, fFlags);
3555	Bs3ExtCtxInit(pThis->pInitialExtCtx, cb, fFlags);
3556	//Bs3TestPrintf("fCR0=%RX64 cbExtCtx=%#x method=%d\n", fFlags, cb, pExtCtx->enmMethod);
3557
3558	/* Allocate guarded exectuable and data memory. */
3559	if (BS3_MODE_IS_PAGED(bMode))
3560	{
3561	#if ARCH_BITS != 16
3562	pThis->pbCodePg = Bs3MemGuardedTestPageAlloc(enmMemKind);
3563	pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
3564	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
3565	{
3566	Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
3567	Bs3MemPrintInfo();
3568	Bs3Shutdown();
3569	return Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
3570	}
3571	if ( BS3_MODE_IS_64BIT_CODE(bMode)
3572	&& (uintptr_t)pThis->pbDataPg >= _2G)
3573	return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
3574	#else
3575	return Bs3TestFailed("WTF?! #1");
3576	#endif
3577	}
3578	else
3579	{
3580	pThis->pbCodePg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
3581	pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
3582	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
3583	{
3584	Bs3MemPrintInfo();
3585	return Bs3TestFailedF("Bs3MemAlloc(%d,Pg) failed", enmMemKind);
3586	}
3587	}
3588	pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
3589	pThis->uDataPgFlat = Bs3SelPtrToFlat(pThis->pbDataPg);
3590	#if ARCH_BITS == 16
3591	pThis->CodePgFar.sel = BS3_FP_SEG(pThis->pbCodePg);
3592	pThis->CodePgFar.off = BS3_FP_OFF(pThis->pbCodePg);
3593	pThis->CodePgRip = BS3_FP_OFF(pThis->pbCodePg);
3594	pThis->DataPgFar.sel = BS3_FP_SEG(pThis->pbDataPg);
3595	pThis->DataPgFar.off = BS3_FP_OFF(pThis->pbDataPg);
3596	#else
3597	if (BS3_MODE_IS_RM_OR_V86(bMode))
3598	{
3599	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToRealMode(pThis->uDataPgFlat);
3600	ASMCompilerBarrier();
3601	pThis->CodePgFar.off = 0;
3602	pThis->CodePgFar.sel = pThis->uCodePgFlat >> 4;
3603	pThis->CodePgRip = pThis->CodePgFar.off;
3604	}
3605	else if (BS3_MODE_IS_16BIT_CODE(bMode))
3606	{
3607	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
3608	ASMCompilerBarrier();
3609	pThis->CodePgFar.sel = BS3_SEL_SPARE_00;
3610	pThis->CodePgFar.off = 0;
3611	pThis->CodePgRip = 0;
3612	}
3613	else if (BS3_MODE_IS_32BIT_CODE(bMode))
3614	{
3615	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
3616	ASMCompilerBarrier();
3617	pThis->CodePgFar.sel = 0;
3618	pThis->CodePgFar.off = 0;
3619	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
3620	}
3621	else
3622	{
3623	pThis->DataPgFar.off = 0;
3624	pThis->DataPgFar.sel = 0;
3625	pThis->CodePgFar.off = 0;
3626	pThis->CodePgFar.sel = 0;
3627	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
3628	}
3629	#endif
3630	BS3CG1_DPRINTF(("pbDataPg=%p %04x:%04x pbCodePg=%p %04x:%04x\n",
3631	pThis->pbDataPg, pThis->DataPgFar.sel, pThis->DataPgFar.off,
3632	pThis->pbCodePg, pThis->CodePgFar.sel, pThis->CodePgFar.off));
3633
3634	/*
3635	* Create basic context for each target ring.
3636	*
3637	* In protected 16-bit code we need set up code selectors that can access
3638	* pbCodePg.
3639	*
3640	* In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
3641	* bits set so we can check that the implicit clearing is tested.
3642	*/
3643	Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
3644	#if ARCH_BITS == 64
3645	pThis->aInitialCtxs[pThis->iFirstRing].rax.u \|= UINT64_C(0x0101010100000000);
3646	pThis->aInitialCtxs[pThis->iFirstRing].rbx.u \|= UINT64_C(0x0202020200000000);
3647	pThis->aInitialCtxs[pThis->iFirstRing].rcx.u \|= UINT64_C(0x0303030300000000);
3648	pThis->aInitialCtxs[pThis->iFirstRing].rdx.u \|= UINT64_C(0x0404040400000000);
3649	pThis->aInitialCtxs[pThis->iFirstRing].rbp.u \|= UINT64_C(0x0505050500000000);
3650	pThis->aInitialCtxs[pThis->iFirstRing].rdi.u \|= UINT64_C(0x0606060600000000);
3651	pThis->aInitialCtxs[pThis->iFirstRing].rsi.u \|= UINT64_C(0x0707070700000000);
3652	pThis->aInitialCtxs[pThis->iFirstRing].r8.u \|= UINT64_C(0x0808080800000000);
3653	pThis->aInitialCtxs[pThis->iFirstRing].r9.u \|= UINT64_C(0x0909090900000000);
3654	pThis->aInitialCtxs[pThis->iFirstRing].r10.u \|= UINT64_C(0x1010101000000000);
3655	pThis->aInitialCtxs[pThis->iFirstRing].r11.u \|= UINT64_C(0x1111111100000000);
3656	pThis->aInitialCtxs[pThis->iFirstRing].r12.u \|= UINT64_C(0x1212121200000000);
3657	pThis->aInitialCtxs[pThis->iFirstRing].r13.u \|= UINT64_C(0x1313131300000000);
3658	pThis->aInitialCtxs[pThis->iFirstRing].r14.u \|= UINT64_C(0x1414141400000000);
3659	pThis->aInitialCtxs[pThis->iFirstRing].r15.u \|= UINT64_C(0x1515151500000000);
3660	#endif
3661
3662	if (BS3_MODE_IS_RM_OR_V86(bMode))
3663	{
3664	pThis->aInitialCtxs[pThis->iFirstRing].cs = pThis->CodePgFar.sel;
3665	BS3_ASSERT(pThis->iFirstRing + 1 == pThis->iEndRing);
3666	}
3667	else if (BS3_MODE_IS_16BIT_CODE(bMode))
3668	{
3669	#if ARCH_BITS == 16
3670	uintptr_t const uFlatCodePgSeg = Bs3SelPtrToFlat(BS3_FP_MAKE(BS3_FP_SEG(pThis->pbCodePg), 0));
3671	#else
3672	uintptr_t const uFlatCodePgSeg = (uintptr_t)pThis->pbCodePg;
3673	#endif
3674	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3675	{
3676	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3677	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3678	}
3679	for (iRing = pThis->iFirstRing; iRing < pThis->iEndRing; iRing++)
3680	{
3681	pThis->aInitialCtxs[iRing].cs = BS3_SEL_SPARE_00 + iRing * 8 + iRing;
3682	Bs3SelSetup16BitCode(&Bs3GdteSpare00 + iRing, uFlatCodePgSeg, iRing);
3683	}
3684	}
3685	else
3686	{
3687	Bs3RegCtxSetRipCsFromCurPtr(&pThis->aInitialCtxs[pThis->iFirstRing], (FPFNBS3FAR)pThis->pbCodePg);
3688	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3689	{
3690	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3691	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3692	}
3693	}
3694
3695	/*
3696	* Create an initial extended CPU context.
3697	*/
3698	pExtCtx = pThis->pInitialExtCtx;
3699	if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
3700	\|\| pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
3701	{
3702	pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL \| X86_FCW_PC_64 \| X86_FCW_RC_NEAREST;
3703	pExtCtx->Ctx.x87.FSW = 0;
3704	pExtCtx->Ctx.x87.MXCSR = X86_MXCSR_IM \| X86_MXCSR_DM \| X86_MXCSR_RC_NEAREST;
3705	pExtCtx->Ctx.x87.MXCSR_MASK = 0;
3706	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
3707	{
3708	pExtCtx->Ctx.x87.aRegs[i].au16[0] = i << 4;
3709	pExtCtx->Ctx.x87.aRegs[i].au16[1] = i << 4;
3710	pExtCtx->Ctx.x87.aRegs[i].au16[2] = i << 4;
3711	pExtCtx->Ctx.x87.aRegs[i].au16[3] = i << 4;
3712	}
3713	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
3714	{
3715	pExtCtx->Ctx.x87.aXMM[i].au16[0] = i;
3716	pExtCtx->Ctx.x87.aXMM[i].au16[1] = i;
3717	pExtCtx->Ctx.x87.aXMM[i].au16[2] = i;
3718	pExtCtx->Ctx.x87.aXMM[i].au16[3] = i;
3719	pExtCtx->Ctx.x87.aXMM[i].au16[4] = i;
3720	pExtCtx->Ctx.x87.aXMM[i].au16[5] = i;
3721	pExtCtx->Ctx.x87.aXMM[i].au16[6] = i;
3722	pExtCtx->Ctx.x87.aXMM[i].au16[7] = i;
3723	}
3724	if (pExtCtx->fXcr0Nominal & XSAVE_C_YMM)
3725	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi); i++)
3726	{
3727	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[0] = i << 8;
3728	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[1] = i << 8;
3729	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[2] = i << 8;
3730	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[3] = i << 8;
3731	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[4] = i << 8;
3732	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[5] = i << 8;
3733	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[6] = i << 8;
3734	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[7] = i << 8;
3735	}
3736
3737	}
3738	//else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_ANCIENT)
3739	else
3740	return Bs3TestFailedF("Unsupported extended CPU context method: %d", pExtCtx->enmMethod);
3741
3742	return true;
3743	}
3744
3745
3746	static uint8_t BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1WorkerInner)(PBS3CG1STATE pThis)
3747	{
3748	uint8_t iRing;
3749	unsigned iInstr;
3750
3751	/*
3752	* Test the instructions.
3753	*/
3754	for (iInstr = 0; iInstr < g_cBs3Cg1Instructions;
3755	iInstr++,
3756	pThis->pchMnemonic += pThis->fAdvanceMnemonic * pThis->cchMnemonic,
3757	pThis->pabOperands += pThis->cOperands,
3758	pThis->pabOpcodes += pThis->cbOpcodes)
3759	{
3760	uint8_t const bTestXcptExpected = BS3_MODE_IS_PAGED(pThis->bMode) ? X86_XCPT_PF : X86_XCPT_UD;
3761	bool fOuterInvalidInstr = false;
3762	unsigned iCpuSetup;
3763
3764	/*
3765	* Expand the instruction information into the state.
3766	* Note! 16-bit will switch to a two level test header lookup once we exceed 64KB.
3767	*/
3768	PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
3769	pThis->iInstr = iInstr;
3770	pThis->pTestHdr = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
3771	pThis->fFlags = pInstr->fFlags;
3772	pThis->enmEncoding = (BS3CG1ENC)pInstr->enmEncoding;
3773	pThis->enmEncodingNonInvalid = (BS3CG1ENC)pInstr->enmEncoding;
3774	pThis->enmCpuTest = (BS3CG1CPU)pInstr->enmCpuTest;
3775	pThis->enmPrefixKind = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
3776	pThis->enmXcptType = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
3777	pThis->cchMnemonic = pInstr->cchMnemonic;
3778	if (pThis->fAdvanceMnemonic)
3779	Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
3780	pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
3781	pThis->cOperands = pInstr->cOperands;
3782	pThis->cbOpcodes = pInstr->cbOpcodes;
3783	switch (pThis->cOperands)
3784	{
3785	case 4: pThis->aenmOperands[3] = (BS3CG1OP)pThis->pabOperands[3];
3786	case 3: pThis->aenmOperands[2] = (BS3CG1OP)pThis->pabOperands[2];
3787	case 2: pThis->aenmOperands[1] = (BS3CG1OP)pThis->pabOperands[1];
3788	case 1: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
3789	}
3790	switch (pThis->cbOpcodes)
3791	{
3792	case 4: pThis->abOpcodes[3] = pThis->pabOpcodes[3];
3793	case 3: pThis->abOpcodes[2] = pThis->pabOpcodes[2];
3794	case 2: pThis->abOpcodes[1] = pThis->pabOpcodes[1];
3795	case 1: pThis->abOpcodes[0] = pThis->pabOpcodes[0];
3796	}
3797
3798	/*
3799	* Check if the CPU supports the instruction.
3800	*/
3801	if ( !Bs3Cg1CpuSetupFirst(pThis)
3802	\|\| (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID)))
3803	fOuterInvalidInstr = true;
3804
3805	/* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
3806	if ( (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
3807	&& pThis->bCpuVendor != BS3CPUVENDOR_INTEL
3808	&& ( (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
3809	\|\| (BS3_MODE_IS_64BIT_CODE(pThis->bMode) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT))
3810	\|\| fOuterInvalidInstr ) )
3811	pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
3812
3813	for (iCpuSetup = 0;; iCpuSetup++)
3814	{
3815	unsigned iEncoding;
3816	unsigned iEncodingNext;
3817
3818	/*
3819	* Prep the operands and encoding handling.
3820	*/
3821	if (!Bs3Cg1EncodePrep(pThis))
3822	break;
3823
3824	/*
3825	* Encode the instruction in various ways and check out the test values.
3826	*/
3827	for (iEncoding = 0;; iEncoding = iEncodingNext)
3828	{
3829	/*
3830	* Encode the next instruction variation.
3831	*/
3832	pThis->fInvalidEncoding = fOuterInvalidInstr;
3833	iEncodingNext = Bs3Cg1EncodeNext(pThis, iEncoding);
3834	if (iEncodingNext <= iEncoding)
3835	break;
3836	BS3CG1_DPRINTF(("\ndbg: Encoding #%u: cbCurInst=%u: %.*Rhxs fInvalidEncoding=%d\n",
3837	iEncoding, pThis->cbCurInstr, pThis->cbCurInstr, pThis->abCurInstr, pThis->fInvalidEncoding));
3838
3839	/*
3840	* Do the rings.
3841	*/
3842	for (iRing = pThis->iFirstRing + pThis->fSameRingNotOkay; iRing < pThis->iEndRing; iRing++)
3843	{
3844	PCBS3CG1TESTHDR pHdr;
3845
3846	pThis->uCpl = iRing;
3847	BS3CG1_DPRINTF(("dbg: Ring %u\n", iRing));
3848
3849	/*
3850	* Do the tests one by one.
3851	*/
3852	pHdr = pThis->pTestHdr;
3853	for (pThis->iTest = 0;; pThis->iTest++)
3854	{
3855	if (Bs3Cg1RunSelector(pThis, pHdr))
3856	{
3857	/* Okay, set up the execution context. */
3858	unsigned offCode;
3859	uint8_t BS3_FAR *pbCode;
3860
3861	Bs3MemCpy(&pThis->Ctx, &pThis->aInitialCtxs[iRing], sizeof(pThis->Ctx));
3862	if (pThis->fWorkExtCtx)
3863	Bs3ExtCtxCopy(pThis->pExtCtx, pThis->pInitialExtCtx);
3864	if (BS3_MODE_IS_PAGED(pThis->bMode))
3865	{
3866	offCode = X86_PAGE_SIZE - pThis->cbCurInstr;
3867	pbCode = &pThis->pbCodePg[offCode];
3868	//if (iEncoding > 0) { pbCode[-1] = 0xf4; offCode--; }
3869	}
3870	else
3871	{
3872	pbCode = pThis->pbCodePg;
3873	pbCode[pThis->cbCurInstr] = 0x0f; /* UD2 */
3874	pbCode[pThis->cbCurInstr + 1] = 0x0b;
3875	offCode = 0;
3876	}
3877	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3878	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr);
3879
3880	if (Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr, pHdr->cbSelector, pHdr->cbInput, NULL, pbCode))
3881	{
3882	/* Run the instruction. */
3883	BS3CG1_DPRINTF(("dbg: Running test #%u\n", pThis->iTest));
3884	//Bs3RegCtxPrint(&pThis->Ctx);
3885	if (pThis->fWorkExtCtx)
3886	Bs3ExtCtxRestore(pThis->pExtCtx);
3887	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3888	if (pThis->fWorkExtCtx)
3889	Bs3ExtCtxSave(pThis->pResultExtCtx);
3890	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64\n",
3891	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3892
3893	/*
3894	* Apply the output modification program to the context.
3895	*/
3896	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3897	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3898	pThis->bValueXcpt = UINT8_MAX; //???
3899	if ( pThis->fInvalidEncoding
3900	\|\| pThis->bAlignmentXcpt != UINT8_MAX
3901	\|\| pThis->bValueXcpt != UINT8_MAX
3902	\|\| Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr,
3903	pHdr->cbSelector + pHdr->cbInput, pHdr->cbOutput,
3904	&pThis->TrapFrame.Ctx, NULL /pbCode/))
3905	{
3906	Bs3Cg1CheckResult(pThis, bTestXcptExpected, false /fInvalidEncodingPgFault/, iEncoding);
3907	}
3908
3909	/*
3910	* If this is an invalid encoding or instruction, check that we
3911	* get a page fault when shortening it by one byte.
3912	* (Since we didn't execute the output context modifier, we don't
3913	* need to re-initialize the start context.)
3914	*/
3915	if ( pThis->fInvalidEncoding
3916	&& BS3_MODE_IS_PAGED(pThis->bMode)
3917	&& pThis->cbCurInstr)
3918	{
3919	pbCode += 1;
3920	offCode += 1;
3921	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3922	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr - 1);
3923
3924	/* Run the instruction. */
3925	BS3CG1_DPRINTF(("dbg: Running test #%u (cut short #PF)\n", pThis->iTest));
3926	//Bs3RegCtxPrint(&pThis->Ctx);
3927	if (pThis->fWorkExtCtx)
3928	Bs3ExtCtxRestore(pThis->pExtCtx);
3929	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3930	if (pThis->fWorkExtCtx)
3931	Bs3ExtCtxSave(pThis->pResultExtCtx);
3932	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64 (cut short #PF)\n",
3933	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3934
3935	/* Check it */
3936	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3937	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3938	Bs3Cg1CheckResult(pThis, X86_XCPT_PF, true /fInvalidEncodingPgFault/, iEncoding);
3939	}
3940	}
3941	}
3942	else
3943	BS3CG1_DPRINTF(("dbg: Skipping #%u\n", pThis->iTest));
3944
3945	/* advance */
3946	if (pHdr->fLast)
3947	{
3948	BS3CG1_DPRINTF(("dbg: Last\n\n"));
3949	break;
3950	}
3951	pHdr = (PCBS3CG1TESTHDR)((uint8_t BS3_FAR *)(pHdr + 1) + pHdr->cbInput + pHdr->cbOutput + pHdr->cbSelector);
3952	}
3953	}
3954	}
3955
3956	/*
3957	* Clean up (segment registers, etc) and get the next CPU config.
3958	*/
3959	Bs3Cg1EncodeCleanup(pThis);
3960	if (!Bs3Cg1CpuSetupNext(pThis, iCpuSetup, &fOuterInvalidInstr))
3961	break;
3962	if (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
3963	fOuterInvalidInstr = true;
3964	}
3965	}
3966
3967	return 0;
3968	}
3969
3970
3971	BS3_DECL_FAR(uint8_t) BS3_CMN_NM(Bs3Cg1Worker)(uint8_t bMode)
3972	{
3973	uint8_t bRet = 1;
3974	BS3CG1STATE This;
3975
3976	#if 0
3977	/* (for debugging) */
3978	if (bMode != BS3_MODE_PP32)
3979	return BS3TESTDOMODE_SKIPPED;
3980	#endif
3981
3982	if (BS3_CMN_NM(Bs3Cg1Init)(&This, bMode))
3983	{
3984	bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
3985	Bs3TestSubDone();
3986	}
3987	Bs3Cg1Destroy(&This);
3988
3989	#if 0
3990	/* (for debugging) */
3991	//if (bMode == BS3_MODE_PP32)
3992	{
3993	Bs3TestTerm();
3994	Bs3Shutdown();
3995	}
3996	#endif
3997	return bRet;
3998	}
3999

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 66785

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