bs3-cpu-generated-1-template.c@ 83878

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1	/* $Id: bs3-cpu-generated-1-template.c 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	#ifndef BS3_INSTANTIATING_CMN
28	# error "BS3_INSTANTIATING_CMN not defined"
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Header Files *
34	*********************************************************************************************************************************/
35	#include <iprt/asm.h>
36	#include <iprt/asm-amd64-x86.h>
37
38	#include "bs3-cpu-generated-1.h"
39
40
41	/*********************************************************************************************************************************
42	* Defined Constants And Macros *
43	*********************************************************************************************************************************/
44	#define BS3CG1_WITH_VEX
45
46	#define P_CS X86_OP_PRF_CS
47	#define P_SS X86_OP_PRF_SS
48	#define P_DS X86_OP_PRF_DS
49	#define P_ES X86_OP_PRF_ES
50	#define P_FS X86_OP_PRF_FS
51	#define P_GS X86_OP_PRF_GS
52	#define P_OZ X86_OP_PRF_SIZE_OP
53	#define P_AZ X86_OP_PRF_SIZE_ADDR
54	#define P_LK X86_OP_PRF_LOCK
55	#define P_RN X86_OP_PRF_REPNZ
56	#define P_RZ X86_OP_PRF_REPZ
57
58	#define REX_WRBX (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
59	#define REX_W___ (X86_OP_REX_W)
60	#define REX_WR__ (X86_OP_REX_W \| X86_OP_REX_R)
61	#define REX_W_B_ (X86_OP_REX_W \| X86_OP_REX_B)
62	#define REX_W__X (X86_OP_REX_W \| X86_OP_REX_X)
63	#define REX_WRB_ (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B)
64	#define REX_WR_X (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_X)
65	#define REX_W_BX (X86_OP_REX_W \| X86_OP_REX_B \| X86_OP_REX_X)
66	#define REX__R__ (X86_OP_REX_R)
67	#define REX__RB_ (X86_OP_REX_R \| X86_OP_REX_B)
68	#define REX__R_X (X86_OP_REX_R \| X86_OP_REX_X)
69	#define REX__RBX (X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
70	#define REX___B_ (X86_OP_REX_B)
71	#define REX___BX (X86_OP_REX_B \| X86_OP_REX_X)
72	#define REX____X (X86_OP_REX_X)
73	#define REX_____ (0x40)
74
75
76	/** @def BS3CG1_DPRINTF
77	* Debug print macro.
78	*/
79	#if 0
80	# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
81	# define BS3CG1_DEBUG_CTX_MOD
82	#else
83	# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
84	#endif
85
86	/**
87	* Checks if this is a 64-bit test target or not.
88	* Helps avoid ifdefs or code bloat.
89	*/
90	#if ARCH_BITS == 64
91	# define BS3CG1_IS_64BIT_TARGET(a_pThis) BS3_MODE_IS_64BIT_CODE((a_pThis)->bMode)
92	#else
93	# define BS3CG1_IS_64BIT_TARGET(a_pThis) (false)
94	#endif
95
96
97	/*********************************************************************************************************************************
98	* Structures and Typedefs *
99	*********************************************************************************************************************************/
100	/** Operand value location. */
101	typedef enum BS3CG1OPLOC
102	{
103	BS3CG1OPLOC_INVALID = 0,
104	BS3CG1OPLOC_CTX,
105	BS3CG1OPLOC_CTX_ZX_VLMAX,
106	BS3CG1OPLOC_IMM,
107	BS3CG1OPLOC_MEM,
108	BS3CG1OPLOC_MEM_RW,
109	BS3CG1OPLOC_MEM_WO,
110	BS3CG1OPLOC_END
111	} BS3CG1OPLOC;
112	AssertCompile(BS3CG1OPLOC_END <= 16);
113
114
115	/** Pointer to the generated test state. */
116	typedef struct BS3CG1STATE *PBS3CG1STATE;
117
118	/**
119	* Encoder callback.
120	* @returns Next encoding. If equal or less to @a iEncoding, no
121	* further encodings are available for testing.
122	* @param pThis The state.
123	* @param iEncoding The encoding.
124	*/
125	typedef unsigned BS3_NEAR_CODE FNBS3CG1ENCODER(PBS3CG1STATE pThis, unsigned iEncoding);
126	/** Pointer to a encoder callback. */
127	typedef FNBS3CG1ENCODER *PFNBS3CG1ENCODER;
128
129
130	/**
131	* The state.
132	*/
133	typedef struct BS3CG1STATE
134	{
135	/** @name Instruction details (expanded from BS3CG1INSTR).
136	* @{ */
137	/** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
138	const char BS3_FAR *pchMnemonic;
139	/** Pointer to the test header. */
140	PCBS3CG1TESTHDR pTestHdr;
141	/** Pointer to the per operand flags (g_abBs3Cg1Operands). */
142	const uint8_t BS3_FAR *pabOperands;
143	/** Opcode bytes (g_abBs3Cg1Opcodes). */
144	const uint8_t BS3_FAR *pabOpcodes;
145	/** The current instruction number in the input array (for error reporting). */
146	uint32_t iInstr;
147
148	/** The instruction flags. */
149	uint32_t fFlags;
150	/** The encoding. */
151	BS3CG1ENC enmEncoding;
152	/** The non-invalid encoding. This may differ from enmEncoding when
153	* Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */
154	BS3CG1ENC enmEncodingNonInvalid;
155	/** The CPU test / CPU ID. */
156	BS3CG1CPU enmCpuTest;
157	/** Prefix sensitivity and requirements. */
158	BS3CG1PFXKIND enmPrefixKind;
159	/** Exception type (SSE, AVX). */
160	BS3CG1XCPTTYPE enmXcptType;
161	/** Per operand flags. */
162	BS3CG1OP aenmOperands[4];
163	/** Opcode bytes. */
164	uint8_t abOpcodes[4];
165	/** The instruction encoder. */
166	PFNBS3CG1ENCODER pfnEncoder;
167
168	/** The length of the mnemonic. */
169	uint8_t cchMnemonic;
170	/** Whether to advance the mnemonic pointer or not. */
171	uint8_t fAdvanceMnemonic;
172	/** The opcode map number. */
173	uint8_t uOpcodeMap;
174	/** The number of opcode bytes. */
175	uint8_t cbOpcodes;
176	/** Number of operands. */
177	uint8_t cOperands;
178	/** @} */
179
180	/** Default operand size. */
181	uint8_t cbOpDefault;
182	/** Operand size when overridden by 066h. */
183	uint8_t cbOpOvrd66;
184	/** Operand size when overridden by REX.W. */
185	uint8_t cbOpOvrdRexW;
186
187	/** Operand size in bytes (0 if not applicable). */
188	uint8_t cbOperand;
189	/** Current VEX.L value (UINT8_MAX if not applicable). */
190	uint8_t uVexL;
191	/** Current target ring (0..3). */
192	uint8_t uCpl;
193
194	/** The current test number. */
195	uint8_t iTest;
196
197	/** Target mode (g_bBs3CurrentMode). */
198	uint8_t bMode;
199	/** The CPU vendor (BS3CPUVENDOR). */
200	uint8_t bCpuVendor;
201	/** First ring being tested. */
202	uint8_t iFirstRing;
203	/** End of rings being tested. */
204	uint8_t iEndRing;
205
206	/** @name Current encoded instruction.
207	* @{ */
208	/** The size of the current instruction that we're testing. */
209	uint8_t cbCurInstr;
210	/** The size the prefixes. */
211	uint8_t cbCurPrefix;
212	/** The offset into abCurInstr of the immediate. */
213	uint8_t offCurImm;
214	/** Buffer for assembling the current instruction. */
215	uint8_t abCurInstr[23];
216
217	/** Set if the encoding can't be tested in the same ring as this test code.
218	* This is used to deal with encodings modifying SP/ESP/RSP. */
219	bool fSameRingNotOkay;
220	/** Whether to work the extended context too. */
221	bool fWorkExtCtx;
222	/** The aOperands index of the modrm.reg operand (if applicable). */
223	uint8_t iRegOp;
224	/** The aOperands index of the modrm.rm operand (if applicable). */
225	uint8_t iRmOp;
226
227	/** Operands details. */
228	struct
229	{
230	uint8_t cbOp;
231	/** BS3CG1OPLOC_XXX. */
232	uint8_t enmLocation;
233	/** BS3CG1OPLOC_XXX for memory encodings (MODRM.rm field). */
234	uint8_t enmLocationMem : 4;
235	/** BS3CG1OPLOC_XXX for register encodings (MODRM.rm field). */
236	uint8_t enmLocationReg : 4;
237	/** The BS3CG1DST value for this field.
238	* Set to BS3CG1DST_INVALID if memory or immediate. */
239	uint8_t idxField;
240	/** The base BS3CG1DST value for this field.
241	* Used only by some generalized encoders when dealing with registers. */
242	uint8_t idxFieldBase;
243	/** Depends on enmLocation.
244	* - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
245	* - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
246	* - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
247	* - BS3CG1OPLOC_MEM_RO: offset should be subtracted from &pbDataPg[_4K].
248	* - BS3CG1OPLOC_CTX: not used (use idxField instead).
249	*/
250	uint8_t off;
251	} aOperands[4];
252	/** @} */
253
254	/** Page to put code in. When paging is enabled, the page before and after
255	* are marked not-present. */
256	uint8_t BS3_FAR *pbCodePg;
257	/** The flat address corresponding to pbCodePg. */
258	uintptr_t uCodePgFlat;
259	/** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
260	RTFAR16 CodePgFar;
261	/** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
262	uintptr_t CodePgRip;
263
264	/** Page for placing data operands in. When paging is enabled, the page before
265	* and after are marked not-present. */
266	uint8_t BS3_FAR *pbDataPg;
267	/** The flat address corresponding to pbDataPg. */
268	uintptr_t uDataPgFlat;
269	/** The 16-bit address corresponding to pbDataPg. */
270	RTFAR16 DataPgFar;
271
272	/** The name corresponding to bMode. */
273	const char BS3_FAR *pszMode;
274	/** The short name corresponding to bMode. */
275	const char BS3_FAR *pszModeShort;
276
277	/** @name Expected result (modifiable by output program).
278	* @{ */
279	/** The expected exception based on operand values or result.
280	* UINT8_MAX if no special exception expected. */
281	uint8_t bValueXcpt;
282	/** @} */
283	/** Alignment exception expected by the encoder.
284	* UINT8_MAX if no special exception expected. */
285	uint8_t bAlignmentXcpt;
286	/** Set by the encoding method to indicating invalid encoding. */
287	bool fInvalidEncoding;
288	/** The result of Bs3Cg1CpuSetupFirst(). */
289	bool fCpuSetupFirstResult;
290
291	/** The context we're working on. */
292	BS3REGCTX Ctx;
293	/** The trap context and frame. */
294	BS3TRAPFRAME TrapFrame;
295	/** Initial contexts, one for each ring. */
296	BS3REGCTX aInitialCtxs[4];
297
298	/** The extended context we're working on (input, expected output). */
299	PBS3EXTCTX pExtCtx;
300	/** The extended result context (analoguous to TrapFrame). */
301	PBS3EXTCTX pResultExtCtx;
302	/** The initial extended context. */
303	PBS3EXTCTX pInitialExtCtx;
304
305	/** Memory operand scratch space. */
306	union
307	{
308	uint8_t ab[128];
309	uint16_t au16[128 / sizeof(uint16_t)];
310	uint32_t au32[128 / sizeof(uint32_t)];
311	uint64_t au64[128 / sizeof(uint64_t)];
312	} MemOp;
313
314	/** Array parallel to aInitialCtxs for saving segment registers. */
315	struct
316	{
317	RTSEL ds;
318	} aSavedSegRegs[4];
319
320	} BS3CG1STATE;
321
322
323	#define BS3CG1_PF_OZ UINT16_C(0x0001)
324	#define BS3CG1_PF_AZ UINT16_C(0x0002)
325	#define BS3CG1_PF_CS UINT16_C(0x0004)
326	#define BS3CG1_PF_DS UINT16_C(0x0008)
327	#define BS3CG1_PF_ES UINT16_C(0x0010)
328	#define BS3CG1_PF_FS UINT16_C(0x0020)
329	#define BS3CG1_PF_GS UINT16_C(0x0040)
330	#define BS3CG1_PF_SS UINT16_C(0x0080)
331	#define BS3CG1_PF_SEGS (BS3CG1_PF_CS \| BS3CG1_PF_DS \| BS3CG1_PF_ES \| BS3CG1_PF_FS \| BS3CG1_PF_GS \| BS3CG1_PF_SS)
332	#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS \| BS3CG1_PF_AZ)
333	#define BS3CG1_PF_LK UINT16_C(0x0100)
334	#define BS3CG1_PF_RN UINT16_C(0x0200)
335	#define BS3CG1_PF_RZ UINT16_C(0x0400)
336	#define BS3CG1_PF_W UINT16_C(0x0800) /*< REX.W /
337	#define BS3CG1_PF_R UINT16_C(0x1000) /*< REX.R /
338	#define BS3CG1_PF_B UINT16_C(0x2000) /*< REX.B /
339	#define BS3CG1_PF_X UINT16_C(0x4000) /*< REX.X /
340
341
342	/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
343	#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
344	/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
345	* the field size (2, 4, or 8). */
346	#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
347
348
349
350	/*********************************************************************************************************************************
351	* Global Variables *
352	*********************************************************************************************************************************/
353	/** Destination field sizes indexed by bBS3CG1DST.
354	* Zero means operand size sized. */
355	static const uint8_t g_acbBs3Cg1DstFields[] =
356	{
357	/* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
358
359	/* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
360	/* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
361	/* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
362	/* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
363	/* [BS3CG1DST_EFL] = */ 4,
364	/* [BS3CG1DST_EFL_UNDEF]=*/ 4,
365
366	/* [BS3CG1DST_AL] = */ 1,
367	/* [BS3CG1DST_CL] = */ 1,
368	/* [BS3CG1DST_DL] = */ 1,
369	/* [BS3CG1DST_BL] = */ 1,
370	/* [BS3CG1DST_AH] = */ 1,
371	/* [BS3CG1DST_CH] = */ 1,
372	/* [BS3CG1DST_DH] = */ 1,
373	/* [BS3CG1DST_BH] = */ 1,
374	/* [BS3CG1DST_SPL] = */ 1,
375	/* [BS3CG1DST_BPL] = */ 1,
376	/* [BS3CG1DST_SIL] = */ 1,
377	/* [BS3CG1DST_DIL] = */ 1,
378	/* [BS3CG1DST_R8L] = */ 1,
379	/* [BS3CG1DST_R9L] = */ 1,
380	/* [BS3CG1DST_R10L] = */ 1,
381	/* [BS3CG1DST_R11L] = */ 1,
382	/* [BS3CG1DST_R12L] = */ 1,
383	/* [BS3CG1DST_R13L] = */ 1,
384	/* [BS3CG1DST_R14L] = */ 1,
385	/* [BS3CG1DST_R15L] = */ 1,
386
387	/* [BS3CG1DST_AX] = */ 2,
388	/* [BS3CG1DST_CX] = */ 2,
389	/* [BS3CG1DST_DX] = */ 2,
390	/* [BS3CG1DST_BX] = */ 2,
391	/* [BS3CG1DST_SP] = */ 2,
392	/* [BS3CG1DST_BP] = */ 2,
393	/* [BS3CG1DST_SI] = */ 2,
394	/* [BS3CG1DST_DI] = */ 2,
395	/* [BS3CG1DST_R8W] = */ 2,
396	/* [BS3CG1DST_R9W] = */ 2,
397	/* [BS3CG1DST_R10W] = */ 2,
398	/* [BS3CG1DST_R11W] = */ 2,
399	/* [BS3CG1DST_R12W] = */ 2,
400	/* [BS3CG1DST_R13W] = */ 2,
401	/* [BS3CG1DST_R14W] = */ 2,
402	/* [BS3CG1DST_R15W] = */ 2,
403
404	/* [BS3CG1DST_EAX] = */ 4,
405	/* [BS3CG1DST_ECX] = */ 4,
406	/* [BS3CG1DST_EDX] = */ 4,
407	/* [BS3CG1DST_EBX] = */ 4,
408	/* [BS3CG1DST_ESP] = */ 4,
409	/* [BS3CG1DST_EBP] = */ 4,
410	/* [BS3CG1DST_ESI] = */ 4,
411	/* [BS3CG1DST_EDI] = */ 4,
412	/* [BS3CG1DST_R8D] = */ 4,
413	/* [BS3CG1DST_R9D] = */ 4,
414	/* [BS3CG1DST_R10D] = */ 4,
415	/* [BS3CG1DST_R11D] = */ 4,
416	/* [BS3CG1DST_R12D] = */ 4,
417	/* [BS3CG1DST_R13D] = */ 4,
418	/* [BS3CG1DST_R14D] = */ 4,
419	/* [BS3CG1DST_R15D] = */ 4,
420
421	/* [BS3CG1DST_RAX] = */ 8,
422	/* [BS3CG1DST_RCX] = */ 8,
423	/* [BS3CG1DST_RDX] = */ 8,
424	/* [BS3CG1DST_RBX] = */ 8,
425	/* [BS3CG1DST_RSP] = */ 8,
426	/* [BS3CG1DST_RBP] = */ 8,
427	/* [BS3CG1DST_RSI] = */ 8,
428	/* [BS3CG1DST_RDI] = */ 8,
429	/* [BS3CG1DST_R8] = */ 8,
430	/* [BS3CG1DST_R9] = */ 8,
431	/* [BS3CG1DST_R10] = */ 8,
432	/* [BS3CG1DST_R11] = */ 8,
433	/* [BS3CG1DST_R12] = */ 8,
434	/* [BS3CG1DST_R13] = */ 8,
435	/* [BS3CG1DST_R14] = */ 8,
436	/* [BS3CG1DST_R15] = */ 8,
437
438	/* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
439	/* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
440	/* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
441	/* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
442	/* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
443	/* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
444	/* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
445	/* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
446	/* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
447	/* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
448	/* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
449	/* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
450	/* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
451	/* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
452	/* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
453	/* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
454
455	/* [BS3CG1DST_CR0] = */ 4,
456	/* [BS3CG1DST_CR4] = */ 4,
457	/* [BS3CG1DST_XCR0] = */ 8,
458
459	/* [BS3CG1DST_FCW] = */ 2,
460	/* [BS3CG1DST_FSW] = */ 2,
461	/* [BS3CG1DST_FTW] = */ 2,
462	/* [BS3CG1DST_FOP] = */ 2,
463	/* [BS3CG1DST_FPUIP] = */ 2,
464	/* [BS3CG1DST_FPUCS] = */ 2,
465	/* [BS3CG1DST_FPUDP] = */ 2,
466	/* [BS3CG1DST_FPUDS] = */ 2,
467	/* [BS3CG1DST_MXCSR] = */ 4,
468	/* [BS3CG1DST_ST0] = */ 12,
469	/* [BS3CG1DST_ST1] = */ 12,
470	/* [BS3CG1DST_ST2] = */ 12,
471	/* [BS3CG1DST_ST3] = */ 12,
472	/* [BS3CG1DST_ST4] = */ 12,
473	/* [BS3CG1DST_ST5] = */ 12,
474	/* [BS3CG1DST_ST6] = */ 12,
475	/* [BS3CG1DST_ST7] = */ 12,
476	/* [BS3CG1DST_MM0] = */ 8,
477	/* [BS3CG1DST_MM1] = */ 8,
478	/* [BS3CG1DST_MM2] = */ 8,
479	/* [BS3CG1DST_MM3] = */ 8,
480	/* [BS3CG1DST_MM4] = */ 8,
481	/* [BS3CG1DST_MM5] = */ 8,
482	/* [BS3CG1DST_MM6] = */ 8,
483	/* [BS3CG1DST_MM7] = */ 8,
484	/* [BS3CG1DST_MM0_LO_ZX] = */ 4,
485	/* [BS3CG1DST_MM1_LO_ZX] = */ 4,
486	/* [BS3CG1DST_MM2_LO_ZX] = */ 4,
487	/* [BS3CG1DST_MM3_LO_ZX] = */ 4,
488	/* [BS3CG1DST_MM4_LO_ZX] = */ 4,
489	/* [BS3CG1DST_MM5_LO_ZX] = */ 4,
490	/* [BS3CG1DST_MM6_LO_ZX] = */ 4,
491	/* [BS3CG1DST_MM7_LO_ZX] = */ 4,
492	/* [BS3CG1DST_XMM0] = */ 16,
493	/* [BS3CG1DST_XMM1] = */ 16,
494	/* [BS3CG1DST_XMM2] = */ 16,
495	/* [BS3CG1DST_XMM3] = */ 16,
496	/* [BS3CG1DST_XMM4] = */ 16,
497	/* [BS3CG1DST_XMM5] = */ 16,
498	/* [BS3CG1DST_XMM6] = */ 16,
499	/* [BS3CG1DST_XMM7] = */ 16,
500	/* [BS3CG1DST_XMM8] = */ 16,
501	/* [BS3CG1DST_XMM9] = */ 16,
502	/* [BS3CG1DST_XMM10] = */ 16,
503	/* [BS3CG1DST_XMM11] = */ 16,
504	/* [BS3CG1DST_XMM12] = */ 16,
505	/* [BS3CG1DST_XMM13] = */ 16,
506	/* [BS3CG1DST_XMM14] = */ 16,
507	/* [BS3CG1DST_XMM15] = */ 16,
508	/* [BS3CG1DST_XMM0_LO] = */ 8,
509	/* [BS3CG1DST_XMM1_LO] = */ 8,
510	/* [BS3CG1DST_XMM2_LO] = */ 8,
511	/* [BS3CG1DST_XMM3_LO] = */ 8,
512	/* [BS3CG1DST_XMM4_LO] = */ 8,
513	/* [BS3CG1DST_XMM5_LO] = */ 8,
514	/* [BS3CG1DST_XMM6_LO] = */ 8,
515	/* [BS3CG1DST_XMM7_LO] = */ 8,
516	/* [BS3CG1DST_XMM8_LO] = */ 8,
517	/* [BS3CG1DST_XMM9_LO] = */ 8,
518	/* [BS3CG1DST_XMM10_LO] = */ 8,
519	/* [BS3CG1DST_XMM11_LO] = */ 8,
520	/* [BS3CG1DST_XMM12_LO] = */ 8,
521	/* [BS3CG1DST_XMM13_LO] = */ 8,
522	/* [BS3CG1DST_XMM14_LO] = */ 8,
523	/* [BS3CG1DST_XMM15_LO] = */ 8,
524	/* [BS3CG1DST_XMM0_HI] = */ 8,
525	/* [BS3CG1DST_XMM1_HI] = */ 8,
526	/* [BS3CG1DST_XMM2_HI] = */ 8,
527	/* [BS3CG1DST_XMM3_HI] = */ 8,
528	/* [BS3CG1DST_XMM4_HI] = */ 8,
529	/* [BS3CG1DST_XMM5_HI] = */ 8,
530	/* [BS3CG1DST_XMM6_HI] = */ 8,
531	/* [BS3CG1DST_XMM7_HI] = */ 8,
532	/* [BS3CG1DST_XMM8_HI] = */ 8,
533	/* [BS3CG1DST_XMM9_HI] = */ 8,
534	/* [BS3CG1DST_XMM10_HI] = */ 8,
535	/* [BS3CG1DST_XMM11_HI] = */ 8,
536	/* [BS3CG1DST_XMM12_HI] = */ 8,
537	/* [BS3CG1DST_XMM13_HI] = */ 8,
538	/* [BS3CG1DST_XMM14_HI] = */ 8,
539	/* [BS3CG1DST_XMM15_HI] = */ 8,
540	/* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
541	/* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
542	/* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
543	/* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
544	/* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
545	/* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
546	/* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
547	/* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
548	/* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
549	/* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
550	/* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
551	/* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
552	/* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
553	/* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
554	/* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
555	/* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
556	/* [BS3CG1DST_XMM0_DW0] = */ 4,
557	/* [BS3CG1DST_XMM1_DW0] = */ 4,
558	/* [BS3CG1DST_XMM2_DW0] = */ 4,
559	/* [BS3CG1DST_XMM3_DW0] = */ 4,
560	/* [BS3CG1DST_XMM4_DW0] = */ 4,
561	/* [BS3CG1DST_XMM5_DW0] = */ 4,
562	/* [BS3CG1DST_XMM6_DW0] = */ 4,
563	/* [BS3CG1DST_XMM7_DW0] = */ 4,
564	/* [BS3CG1DST_XMM8_DW0] = */ 4,
565	/* [BS3CG1DST_XMM9_DW0] = */ 4,
566	/* [BS3CG1DST_XMM10_DW0] = */ 4,
567	/* [BS3CG1DST_XMM11_DW0] = */ 4,
568	/* [BS3CG1DST_XMM12_DW0] = */ 4,
569	/* [BS3CG1DST_XMM13_DW0] = */ 4,
570	/* [BS3CG1DST_XMM14_DW0] = */ 4,
571	/* [BS3CG1DST_XMM15_DW0] = */ 4,
572	/* [BS3CG1DST_XMM0_DW0_ZX] = */ 4,
573	/* [BS3CG1DST_XMM1_DW0_ZX] = */ 4,
574	/* [BS3CG1DST_XMM2_DW0_ZX] = */ 4,
575	/* [BS3CG1DST_XMM3_DW0_ZX] = */ 4,
576	/* [BS3CG1DST_XMM4_DW0_ZX] = */ 4,
577	/* [BS3CG1DST_XMM5_DW0_ZX] = */ 4,
578	/* [BS3CG1DST_XMM6_DW0_ZX] = */ 4,
579	/* [BS3CG1DST_XMM7_DW0_ZX] = */ 4,
580	/* [BS3CG1DST_XMM8_DW0_ZX] = */ 4,
581	/* [BS3CG1DST_XMM9_DW0_ZX] = */ 4,
582	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ 4,
583	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ 4,
584	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ 4,
585	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ 4,
586	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
587	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
588	/* [BS3CG1DST_XMM0_HI96] = */ 12,
589	/* [BS3CG1DST_XMM1_HI96] = */ 12,
590	/* [BS3CG1DST_XMM2_HI96] = */ 12,
591	/* [BS3CG1DST_XMM3_HI96] = */ 12,
592	/* [BS3CG1DST_XMM4_HI96] = */ 12,
593	/* [BS3CG1DST_XMM5_HI96] = */ 12,
594	/* [BS3CG1DST_XMM6_HI96] = */ 12,
595	/* [BS3CG1DST_XMM7_HI96] = */ 12,
596	/* [BS3CG1DST_XMM8_HI96] = */ 12,
597	/* [BS3CG1DST_XMM9_HI96] = */ 12,
598	/* [BS3CG1DST_XMM10_HI96] =*/ 12,
599	/* [BS3CG1DST_XMM11_HI96] =*/ 12,
600	/* [BS3CG1DST_XMM12_HI96] =*/ 12,
601	/* [BS3CG1DST_XMM13_HI96] =*/ 12,
602	/* [BS3CG1DST_XMM14_HI96] =*/ 12,
603	/* [BS3CG1DST_XMM15_HI96] =*/ 12,
604	/* [BS3CG1DST_YMM0] = */ 32,
605	/* [BS3CG1DST_YMM1] = */ 32,
606	/* [BS3CG1DST_YMM2] = */ 32,
607	/* [BS3CG1DST_YMM3] = */ 32,
608	/* [BS3CG1DST_YMM4] = */ 32,
609	/* [BS3CG1DST_YMM5] = */ 32,
610	/* [BS3CG1DST_YMM6] = */ 32,
611	/* [BS3CG1DST_YMM7] = */ 32,
612	/* [BS3CG1DST_YMM8] = */ 32,
613	/* [BS3CG1DST_YMM9] = */ 32,
614	/* [BS3CG1DST_YMM10] = */ 32,
615	/* [BS3CG1DST_YMM11] = */ 32,
616	/* [BS3CG1DST_YMM12] = */ 32,
617	/* [BS3CG1DST_YMM13] = */ 32,
618	/* [BS3CG1DST_YMM14] = */ 32,
619	/* [BS3CG1DST_YMM15] = */ 32,
620
621	/* [BS3CG1DST_VALUE_XCPT] = */ 1,
622	};
623	AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
624
625	/** Destination field offset indexed by bBS3CG1DST.
626	* Zero means operand size sized. */
627	static const unsigned g_aoffBs3Cg1DstFields[] =
628	{
629	/* [BS3CG1DST_INVALID] = */ ~0U,
630	/* [BS3CG1DST_OP1] = */ ~0U,
631	/* [BS3CG1DST_OP2] = */ ~0U,
632	/* [BS3CG1DST_OP3] = */ ~0U,
633	/* [BS3CG1DST_OP4] = */ ~0U,
634	/* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
635	/* [BS3CG1DST_EFL_UNDEF]=/ ~0, / special field */
636
637	/* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
638	/* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
639	/* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
640	/* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
641	/* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
642	/* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
643	/* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
644	/* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
645	/* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
646	/* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
647	/* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
648	/* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
649	/* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
650	/* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
651	/* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
652	/* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
653	/* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
654	/* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
655	/* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
656	/* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
657
658	/* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
659	/* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
660	/* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
661	/* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
662	/* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
663	/* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
664	/* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
665	/* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
666	/* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
667	/* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
668	/* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
669	/* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
670	/* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
671	/* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
672	/* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
673	/* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
674
675	/* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
676	/* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
677	/* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
678	/* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
679	/* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
680	/* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
681	/* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
682	/* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
683	/* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
684	/* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
685	/* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
686	/* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
687	/* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
688	/* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
689	/* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
690	/* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
691
692	/* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
693	/* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
694	/* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
695	/* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
696	/* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
697	/* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
698	/* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
699	/* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
700	/* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
701	/* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
702	/* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
703	/* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
704	/* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
705	/* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
706	/* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
707	/* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
708
709	/* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
710	/* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
711	/* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
712	/* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
713	/* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
714	/* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
715	/* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
716	/* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
717	/* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
718	/* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
719	/* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
720	/* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
721	/* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
722	/* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
723	/* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
724	/* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
725
726	/* [BS3CG1DST_CR0] = */ RT_OFFSETOF(BS3REGCTX, cr0),
727	/* [BS3CG1DST_CR4] = */ RT_OFFSETOF(BS3REGCTX, cr4),
728	/* [BS3CG1DST_XCR0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, fXcr0Saved),
729
730	/* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
731	/* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
732	/* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
733	/* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
734	/* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
735	/* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
736	/* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
737	/* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
738	/* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
739	/* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
740	/* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
741	/* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
742	/* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
743	/* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
744	/* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
745	/* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
746	/* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
747	/* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
748	/* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
749	/* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
750	/* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
751	/* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
752	/* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
753	/* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
754	/* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
755	/* [BS3CG1DST_MM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
756	/* [BS3CG1DST_MM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
757	/* [BS3CG1DST_MM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
758	/* [BS3CG1DST_MM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
759	/* [BS3CG1DST_MM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
760	/* [BS3CG1DST_MM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
761	/* [BS3CG1DST_MM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
762	/* [BS3CG1DST_MM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
763
764	/* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
765	/* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
766	/* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
767	/* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
768	/* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
769	/* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
770	/* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
771	/* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
772	/* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
773	/* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
774	/* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
775	/* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
776	/* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
777	/* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
778	/* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
779	/* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
780	/* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
781	/* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
782	/* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
783	/* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
784	/* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
785	/* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
786	/* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
787	/* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
788	/* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
789	/* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
790	/* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
791	/* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
792	/* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
793	/* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
794	/* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
795	/* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
796	/* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
797	/* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
798	/* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
799	/* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
800	/* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
801	/* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
802	/* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
803	/* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
804	/* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
805	/* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
806	/* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
807	/* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
808	/* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
809	/* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
810	/* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
811	/* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
812	/* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
813	/* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
814	/* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
815	/* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
816	/* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
817	/* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
818	/* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
819	/* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
820	/* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
821	/* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
822	/* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
823	/* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
824	/* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
825	/* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
826	/* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
827	/* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
828	/* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
829	/* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
830	/* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
831	/* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
832	/* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
833	/* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
834	/* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
835	/* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
836	/* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
837	/* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
838	/* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
839	/* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
840	/* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
841	/* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
842	/* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
843	/* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
844	/* [BS3CG1DST_XMM0_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
845	/* [BS3CG1DST_XMM1_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
846	/* [BS3CG1DST_XMM2_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
847	/* [BS3CG1DST_XMM3_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
848	/* [BS3CG1DST_XMM4_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
849	/* [BS3CG1DST_XMM5_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
850	/* [BS3CG1DST_XMM6_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
851	/* [BS3CG1DST_XMM7_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
852	/* [BS3CG1DST_XMM8_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
853	/* [BS3CG1DST_XMM9_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
854	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
855	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
856	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
857	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
858	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
859	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
860	/* [BS3CG1DST_XMM0_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0].au32[1]),
861	/* [BS3CG1DST_XMM1_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1].au32[1]),
862	/* [BS3CG1DST_XMM2_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2].au32[1]),
863	/* [BS3CG1DST_XMM3_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3].au32[1]),
864	/* [BS3CG1DST_XMM4_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4].au32[1]),
865	/* [BS3CG1DST_XMM5_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5].au32[1]),
866	/* [BS3CG1DST_XMM6_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6].au32[1]),
867	/* [BS3CG1DST_XMM7_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7].au32[1]),
868	/* [BS3CG1DST_XMM8_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8].au32[1]),
869	/* [BS3CG1DST_XMM9_HI96] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9].au32[1]),
870	/* [BS3CG1DST_XMM10_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10].au32[1]),
871	/* [BS3CG1DST_XMM11_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11].au32[1]),
872	/* [BS3CG1DST_XMM12_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12].au32[1]),
873	/* [BS3CG1DST_XMM13_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13].au32[1]),
874	/* [BS3CG1DST_XMM14_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14].au32[1]),
875	/* [BS3CG1DST_XMM15_HI96] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15].au32[1]),
876
877	/* [BS3CG1DST_YMM0] = */ ~0U,
878	/* [BS3CG1DST_YMM1] = */ ~0U,
879	/* [BS3CG1DST_YMM2] = */ ~0U,
880	/* [BS3CG1DST_YMM3] = */ ~0U,
881	/* [BS3CG1DST_YMM4] = */ ~0U,
882	/* [BS3CG1DST_YMM5] = */ ~0U,
883	/* [BS3CG1DST_YMM6] = */ ~0U,
884	/* [BS3CG1DST_YMM7] = */ ~0U,
885	/* [BS3CG1DST_YMM8] = */ ~0U,
886	/* [BS3CG1DST_YMM9] = */ ~0U,
887	/* [BS3CG1DST_YMM10] = */ ~0U,
888	/* [BS3CG1DST_YMM11] = */ ~0U,
889	/* [BS3CG1DST_YMM12] = */ ~0U,
890	/* [BS3CG1DST_YMM13] = */ ~0U,
891	/* [BS3CG1DST_YMM14] = */ ~0U,
892	/* [BS3CG1DST_YMM15] = */ ~0U,
893
894	/* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
895	};
896	AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
897
898	/** Destination field names. */
899	static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
900	{
901	{ "INVALID" },
902	{ "OP1" },
903	{ "OP2" },
904	{ "OP3" },
905	{ "OP4" },
906	{ "EFL" },
907	{ "EFL_UND" },
908
909	{ "AL" },
910	{ "CL" },
911	{ "DL" },
912	{ "BL" },
913	{ "AH" },
914	{ "CH" },
915	{ "DH" },
916	{ "BH" },
917	{ "SPL" },
918	{ "BPL" },
919	{ "SIL" },
920	{ "DIL" },
921	{ "R8L" },
922	{ "R9L" },
923	{ "R10L" },
924	{ "R11L" },
925	{ "R12L" },
926	{ "R13L" },
927	{ "R14L" },
928	{ "R15L" },
929
930	{ "AX" },
931	{ "CX" },
932	{ "DX" },
933	{ "BX" },
934	{ "SP" },
935	{ "BP" },
936	{ "SI" },
937	{ "DI" },
938	{ "R8W" },
939	{ "R9W" },
940	{ "R10W" },
941	{ "R11W" },
942	{ "R12W" },
943	{ "R13W" },
944	{ "R14W" },
945	{ "R15W" },
946
947	{ "EAX" },
948	{ "ECX" },
949	{ "EDX" },
950	{ "EBX" },
951	{ "ESP" },
952	{ "EBP" },
953	{ "ESI" },
954	{ "EDI" },
955	{ "R8D" },
956	{ "R9D" },
957	{ "R10D" },
958	{ "R11D" },
959	{ "R12D" },
960	{ "R13D" },
961	{ "R14D" },
962	{ "R15D" },
963
964	{ "RAX" },
965	{ "RCX" },
966	{ "RDX" },
967	{ "RBX" },
968	{ "RSP" },
969	{ "RBP" },
970	{ "RSI" },
971	{ "RDI" },
972	{ "R8" },
973	{ "R9" },
974	{ "R10" },
975	{ "R11" },
976	{ "R12" },
977	{ "R13" },
978	{ "R14" },
979	{ "R15" },
980
981	{ "OZ_RAX" },
982	{ "OZ_RCX" },
983	{ "OZ_RDX" },
984	{ "OZ_RBX" },
985	{ "OZ_RSP" },
986	{ "OZ_RBP" },
987	{ "OZ_RSI" },
988	{ "OZ_RDI" },
989	{ "OZ_R8" },
990	{ "OZ_R9" },
991	{ "OZ_R10" },
992	{ "OZ_R11" },
993	{ "OZ_R12" },
994	{ "OZ_R13" },
995	{ "OZ_R14" },
996	{ "OZ_R15" },
997
998	{ "CR0" },
999	{ "CR4" },
1000	{ "XCR0" },
1001
1002	{ "FCW" },
1003	{ "FSW" },
1004	{ "FTW" },
1005	{ "FOP" },
1006	{ "FPUIP" },
1007	{ "FPUCS" },
1008	{ "FPUDP" },
1009	{ "FPUDS" },
1010	{ "MXCSR" },
1011	{ "ST0" },
1012	{ "ST1" },
1013	{ "ST2" },
1014	{ "ST3" },
1015	{ "ST4" },
1016	{ "ST5" },
1017	{ "ST6" },
1018	{ "ST7" },
1019	{ "MM0" },
1020	{ "MM1" },
1021	{ "MM2" },
1022	{ "MM3" },
1023	{ "MM4" },
1024	{ "MM5" },
1025	{ "MM6" },
1026	{ "MM7" },
1027	{ "MM0_LO_ZX" },
1028	{ "MM1_LO_ZX" },
1029	{ "MM2_LO_ZX" },
1030	{ "MM3_LO_ZX" },
1031	{ "MM4_LO_ZX" },
1032	{ "MM5_LO_ZX" },
1033	{ "MM6_LO_ZX" },
1034	{ "MM7_LO_ZX" },
1035	{ "XMM0" },
1036	{ "XMM1" },
1037	{ "XMM2" },
1038	{ "XMM3" },
1039	{ "XMM4" },
1040	{ "XMM5" },
1041	{ "XMM6" },
1042	{ "XMM7" },
1043	{ "XMM8" },
1044	{ "XMM9" },
1045	{ "XMM10" },
1046	{ "XMM11" },
1047	{ "XMM12" },
1048	{ "XMM13" },
1049	{ "XMM14" },
1050	{ "XMM15" },
1051	{ "XMM0_LO" },
1052	{ "XMM1_LO" },
1053	{ "XMM2_LO" },
1054	{ "XMM3_LO" },
1055	{ "XMM4_LO" },
1056	{ "XMM5_LO" },
1057	{ "XMM6_LO" },
1058	{ "XMM7_LO" },
1059	{ "XMM8_LO" },
1060	{ "XMM9_LO" },
1061	{ "XMM10_LO" },
1062	{ "XMM11_LO" },
1063	{ "XMM12_LO" },
1064	{ "XMM13_LO" },
1065	{ "XMM14_LO" },
1066	{ "XMM15_LO" },
1067	{ "XMM0_HI" },
1068	{ "XMM1_HI" },
1069	{ "XMM2_HI" },
1070	{ "XMM3_HI" },
1071	{ "XMM4_HI" },
1072	{ "XMM5_HI" },
1073	{ "XMM6_HI" },
1074	{ "XMM7_HI" },
1075	{ "XMM8_HI" },
1076	{ "XMM9_HI" },
1077	{ "XMM10_HI" },
1078	{ "XMM11_HI" },
1079	{ "XMM12_HI" },
1080	{ "XMM13_HI" },
1081	{ "XMM14_HI" },
1082	{ "XMM15_HI" },
1083	{ "XMM0_LO_ZX" },
1084	{ "XMM1_LO_ZX" },
1085	{ "XMM2_LO_ZX" },
1086	{ "XMM3_LO_ZX" },
1087	{ "XMM4_LO_ZX" },
1088	{ "XMM5_LO_ZX" },
1089	{ "XMM6_LO_ZX" },
1090	{ "XMM7_LO_ZX" },
1091	{ "XMM8_LO_ZX" },
1092	{ "XMM9_LO_ZX" },
1093	{ "XMM10_LO_ZX" },
1094	{ "XMM11_LO_ZX" },
1095	{ "XMM12_LO_ZX" },
1096	{ "XMM13_LO_ZX" },
1097	{ "XMM14_LO_ZX" },
1098	{ "XMM15_LO_ZX" },
1099	{ "XMM0_DW0" },
1100	{ "XMM1_DW0" },
1101	{ "XMM2_DW0" },
1102	{ "XMM3_DW0" },
1103	{ "XMM4_DW0" },
1104	{ "XMM5_DW0" },
1105	{ "XMM6_DW0" },
1106	{ "XMM7_DW0" },
1107	{ "XMM8_DW0" },
1108	{ "XMM9_DW0" },
1109	{ "XMM10_DW0" },
1110	{ "XMM11_DW0" },
1111	{ "XMM12_DW0" },
1112	{ "XMM13_DW0" },
1113	{ "XMM14_DW0" },
1114	{ "XMM15_DW0" },
1115	{ "XMM0_DW0_ZX" },
1116	{ "XMM1_DW0_ZX" },
1117	{ "XMM2_DW0_ZX" },
1118	{ "XMM3_DW0_ZX" },
1119	{ "XMM4_DW0_ZX" },
1120	{ "XMM5_DW0_ZX" },
1121	{ "XMM6_DW0_ZX" },
1122	{ "XMM7_DW0_ZX" },
1123	{ "XMM8_DW0_ZX" },
1124	{ "XMM9_DW0_ZX" },
1125	{ "XMM10_DW0_ZX" },
1126	{ "XMM11_DW0_ZX" },
1127	{ "XMM12_DW0_ZX" },
1128	{ "XMM13_DW0_ZX" },
1129	{ "XMM14_DW0_ZX" },
1130	{ "XMM15_DW0_ZX" },
1131	{ "XMM0_HI96" },
1132	{ "XMM1_HI96" },
1133	{ "XMM2_HI96" },
1134	{ "XMM3_HI96" },
1135	{ "XMM4_HI96" },
1136	{ "XMM5_HI96" },
1137	{ "XMM6_HI96" },
1138	{ "XMM7_HI96" },
1139	{ "XMM8_HI96" },
1140	{ "XMM9_HI96" },
1141	{ "XMM10_HI96" },
1142	{ "XMM11_HI96" },
1143	{ "XMM12_HI96" },
1144	{ "XMM13_HI96" },
1145	{ "XMM14_HI96" },
1146	{ "XMM15_HI96" },
1147	{ "YMM0" },
1148	{ "YMM1" },
1149	{ "YMM2" },
1150	{ "YMM3" },
1151	{ "YMM4" },
1152	{ "YMM5" },
1153	{ "YMM6" },
1154	{ "YMM7" },
1155	{ "YMM8" },
1156	{ "YMM9" },
1157	{ "YMM10" },
1158	{ "YMM11" },
1159	{ "YMM12" },
1160	{ "YMM13" },
1161	{ "YMM14" },
1162	{ "YMM15" },
1163
1164	{ "VALXCPT" },
1165	};
1166	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) >= BS3CG1DST_END);
1167	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
1168
1169
1170	#if 0
1171	static const struct
1172	{
1173	uint8_t cbPrefixes;
1174	uint8_t abPrefixes[14];
1175	uint16_t fEffective;
1176	} g_aPrefixVariations[] =
1177	{
1178	{ 0, { 0x00 }, BS3CG1_PF_NONE },
1179
1180	{ 1, { P_OZ }, BS3CG1_PF_OZ },
1181	{ 1, { P_CS }, BS3CG1_PF_CS },
1182	{ 1, { P_DS }, BS3CG1_PF_DS },
1183	{ 1, { P_ES }, BS3CG1_PF_ES },
1184	{ 1, { P_FS }, BS3CG1_PF_FS },
1185	{ 1, { P_GS }, BS3CG1_PF_GS },
1186	{ 1, { P_SS }, BS3CG1_PF_SS },
1187	{ 1, { P_LK }, BS3CG1_PF_LK },
1188
1189	{ 2, { P_CS, P_OZ, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1190	{ 2, { P_DS, P_OZ, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1191	{ 2, { P_ES, P_OZ, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1192	{ 2, { P_FS, P_OZ, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1193	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1194	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1195	{ 2, { P_SS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1196
1197	{ 2, { P_OZ, P_CS, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1198	{ 2, { P_OZ, P_DS, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1199	{ 2, { P_OZ, P_ES, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1200	{ 2, { P_OZ, P_FS, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1201	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1202	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1203	{ 2, { P_OZ, P_SS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1204	};
1205
1206	static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1207	{
1208	/* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1209	/* [BS3CG1PFXKIND_MODRM] = */ 0,
1210	/* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ \| BS3CG1_PF_W,
1211	};
1212
1213	#endif
1214
1215
1216	/**
1217	* Checks if >= 16 byte SSE alignment are exempted for the exception type.
1218	*
1219	* @returns true / false.
1220	* @param enmXcptType The type to check.
1221	*/
1222	static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1223	{
1224	switch (enmXcptType)
1225	{
1226	case BS3CG1XCPTTYPE_1:
1227	case BS3CG1XCPTTYPE_2:
1228	case BS3CG1XCPTTYPE_4:
1229	return false;
1230	case BS3CG1XCPTTYPE_NONE:
1231	case BS3CG1XCPTTYPE_3:
1232	case BS3CG1XCPTTYPE_4UA:
1233	case BS3CG1XCPTTYPE_5:
1234	return true;
1235	default:
1236	return false;
1237	}
1238	}
1239
1240
1241	/**
1242	* Checks if >= 16 byte AVX alignment are exempted for the exception type.
1243	*
1244	* @returns true / false.
1245	* @param enmXcptType The type to check.
1246	*/
1247	static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsVexUnaligned(BS3CG1XCPTTYPE enmXcptType)
1248	{
1249	switch (enmXcptType)
1250	{
1251	case BS3CG1XCPTTYPE_1:
1252	return false;
1253
1254	case BS3CG1XCPTTYPE_NONE:
1255	case BS3CG1XCPTTYPE_2:
1256	case BS3CG1XCPTTYPE_3:
1257	case BS3CG1XCPTTYPE_4:
1258	case BS3CG1XCPTTYPE_4UA:
1259	case BS3CG1XCPTTYPE_5:
1260	case BS3CG1XCPTTYPE_6:
1261	case BS3CG1XCPTTYPE_11:
1262	case BS3CG1XCPTTYPE_12:
1263	return true;
1264
1265	default:
1266	return false;
1267	}
1268	}
1269
1270
1271	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1272	{
1273	switch (pThis->enmPrefixKind)
1274	{
1275	case BS3CG1PFXKIND_REQ_66:
1276	pThis->abCurInstr[offDst] = 0x66;
1277	break;
1278	case BS3CG1PFXKIND_REQ_F2:
1279	pThis->abCurInstr[offDst] = 0xf2;
1280	break;
1281	case BS3CG1PFXKIND_REQ_F3:
1282	pThis->abCurInstr[offDst] = 0xf3;
1283	break;
1284	default:
1285	return offDst;
1286	}
1287	return offDst + 1;
1288	}
1289
1290
1291	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1292	{
1293	switch (pThis->cbOpcodes)
1294	{
1295	case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1296	case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1297	case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1298	case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1299	return offDst + pThis->cbOpcodes;
1300
1301	default:
1302	BS3_ASSERT(0);
1303	return 0;
1304	}
1305	}
1306
1307
1308	/**
1309	* Inserts a ModR/M byte with mod=3 and set the two idxFields members.
1310	*
1311	* @returns off + 1.
1312	* @param pThis The state.
1313	* @param off Current instruction offset.
1314	* @param uReg Register index for ModR/M.reg.
1315	* @param uRegMem Register index for ModR/M.rm.
1316	*/
1317	static unsigned Bs3Cg1InsertModRmWithRegFields(PBS3CG1STATE pThis, unsigned off, uint8_t uReg, uint8_t uRegMem)
1318	{
1319	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, uReg & 7, uRegMem & 7);
1320	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + uReg;
1321	pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + uRegMem;
1322	return off;
1323	}
1324
1325
1326
1327	/**
1328	* Cleans up state and context changes made by the encoder.
1329	*
1330	* @param pThis The state.
1331	*/
1332	static void BS3_NEAR_CODE Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1333	{
1334	/* Restore the DS registers in the contexts. */
1335	unsigned iRing = 4;
1336	while (iRing-- > 0)
1337	pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1338
1339	switch (pThis->enmEncoding)
1340	{
1341	/* Most encodings currently doesn't need any special cleaning up. */
1342	default:
1343	return;
1344	}
1345	}
1346
1347
1348	static unsigned BS3_NEAR_CODE Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1349	uint8_t cbOp, uint8_t cbMisalign, BS3CG1OPLOC enmLocation)
1350	{
1351	pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1352	pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1353	pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1354	pThis->aOperands[pThis->iRmOp].off = cbOp + cbMisalign;
1355
1356	if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1357	\|\| (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1358	{
1359	/*
1360	* 16-bit code doing 16-bit or 32-bit addressing,
1361	* or 32-bit code doing 16-bit addressing.
1362	*/
1363	unsigned iRing = 4;
1364	if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1365	while (iRing-- > 0)
1366	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1367	else
1368	while (iRing-- > 0)
1369	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel \| iRing;
1370	if (!fAddrOverride \|\| BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1371	{
1372	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /disp16/);
1373	(uint16_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMisalign;
1374	off += 2;
1375	}
1376	else
1377	{
1378	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1379	(uint32_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMisalign;
1380	off += 4;
1381	}
1382	}
1383	else
1384	{
1385	/*
1386	* 32-bit code doing 32-bit addressing,
1387	* or 64-bit code doing either 64-bit or 32-bit addressing.
1388	*/
1389	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1390	(uint32_t )&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMisalign;
1391
1392	#if ARCH_BITS == 64
1393	/* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1394	if (BS3CG1_IS_64BIT_TARGET(pThis))
1395	(uint32_t )&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1396	#endif
1397	off += 4;
1398	}
1399
1400	/*
1401	* Fill the memory with 0xcc.
1402	*/
1403	switch (cbOp + cbMisalign)
1404	{
1405	case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; RT_FALL_THRU();
1406	case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; RT_FALL_THRU();
1407	case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; RT_FALL_THRU();
1408	case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; RT_FALL_THRU();
1409	case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; RT_FALL_THRU();
1410	case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; RT_FALL_THRU();
1411	case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; RT_FALL_THRU();
1412	case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; RT_FALL_THRU();
1413	case 0: break;
1414	default:
1415	{
1416	BS3CG1_DPRINTF(("Bs3MemSet(%p,%#x,%#x)\n", &pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMisalign], 0xcc, cbOp - cbMisalign));
1417	Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMisalign], 0xcc, cbOp - cbMisalign);
1418	break;
1419	}
1420	}
1421
1422	return off;
1423	}
1424
1425
1426	#if 0 /* unused */
1427	/** Also encodes idxField of the register operand using idxFieldBase. */
1428	static unsigned BS3_NEAR_CODE
1429	Bs3Cfg1EncodeMemMod0DispWithRegField(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1430	uint8_t cbOp, uint8_t cbMisalign, BS3CG1OPLOC enmLocation)
1431	{
1432	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1433	return Bs3Cfg1EncodeMemMod0Disp(pThis, fAddrOverride, off, iReg & 7, cbOp, cbMisalign, enmLocation);
1434	}
1435	#endif
1436
1437	/** Also encodes idxField of the register operand using idxFieldBase. */
1438	static unsigned BS3_NEAR_CODE
1439	Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(PBS3CG1STATE pThis, unsigned off, uint8_t iReg)
1440	{
1441	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1442	return Bs3Cfg1EncodeMemMod0Disp(pThis, false /fAddrOverride/, off, iReg & 7,
1443	pThis->aOperands[pThis->iRmOp].cbOp,
1444	0 /cbMisalign/,
1445	pThis->aOperands[pThis->iRmOp].enmLocation);
1446	}
1447
1448	/** Also encodes idxField of the register operand using idxFieldBase. */
1449	static unsigned BS3_NEAR_CODE
1450	Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsAddrOverride(PBS3CG1STATE pThis, unsigned off, uint8_t iReg)
1451	{
1452	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1453	return Bs3Cfg1EncodeMemMod0Disp(pThis, true /fAddrOverride/, off, iReg & 7,
1454	pThis->aOperands[pThis->iRmOp].cbOp,
1455	0 /cbMisalign/,
1456	pThis->aOperands[pThis->iRmOp].enmLocation);
1457	}
1458
1459
1460	/** Also encodes idxField of the register operand using idxFieldBase. */
1461	static unsigned BS3_NEAR_CODE
1462	Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbMisalign)
1463	{
1464	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1465	return Bs3Cfg1EncodeMemMod0Disp(pThis, false /fAddrOverride/, off, iReg & 7,
1466	pThis->aOperands[pThis->iRmOp].cbOp,
1467	cbMisalign,
1468	pThis->aOperands[pThis->iRmOp].enmLocation);
1469	}
1470
1471
1472	/** Also encodes idxField of the register operand using idxFieldBase. */
1473	static unsigned BS3_NEAR_CODE
1474	Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbOp)
1475	{
1476	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1477	return Bs3Cfg1EncodeMemMod0Disp(pThis, false /fAddrOverride/, off, iReg & 7, cbOp, 0 /cbMisalign/,
1478	pThis->aOperands[pThis->iRmOp].enmLocation);
1479	}
1480
1481	/** Also encodes idxField of the register operand using idxFieldBase. */
1482	static unsigned BS3_NEAR_CODE
1483	Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(PBS3CG1STATE pThis, unsigned off, uint8_t iReg, uint8_t cbOp)
1484	{
1485	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + iReg;
1486	return Bs3Cfg1EncodeMemMod0Disp(pThis, true /fAddrOverride/, off, iReg & 7, cbOp, 0 /cbMisalign/,
1487	pThis->aOperands[pThis->iRmOp].enmLocation);
1488	}
1489
1490
1491	/** The modrm.reg value is taken from the instruction byte at @a off. */
1492	static unsigned BS3_NEAR_CODE
1493	Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(PBS3CG1STATE pThis, unsigned off)
1494	{
1495	return Bs3Cfg1EncodeMemMod0Disp(pThis, false /fAddrOverride/, off,
1496	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1497	pThis->aOperands[pThis->iRmOp].cbOp,
1498	0 /cbMisalign/,
1499	pThis->aOperands[pThis->iRmOp].enmLocation);
1500	}
1501
1502
1503
1504	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1505	{
1506	unsigned off;
1507	switch (iEncoding)
1508	{
1509	/* Start by reg,reg encoding. */
1510	case 0:
1511	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1512	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1513	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xAX, X86_GREG_xCX);
1514	break;
1515	case 1:
1516	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1517	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1518	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5 /CH/);
1519	break;
1520	case 2:
1521	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
1522	return 0;
1523	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1524	pThis->abCurInstr[0] = P_OZ;
1525	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1526	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 6 /DH/);
1527	break;
1528	/* Tests with address overrides go last! */
1529	case 3:
1530	pThis->abCurInstr[0] = P_AZ;
1531	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1532	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsAddrOverride(pThis, off, 7 /BH/);
1533	break;
1534
1535	default:
1536	return 0;
1537	}
1538	pThis->cbCurInstr = off;
1539	return iEncoding + 1;
1540	}
1541
1542
1543	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv(PBS3CG1STATE pThis, unsigned iEncoding)
1544	{
1545	unsigned off;
1546	unsigned cbOp;
1547	switch (iEncoding)
1548	{
1549	case 0:
1550	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1551	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1552	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xBX, X86_GREG_xDX);
1553	cbOp = pThis->cbOpDefault;
1554	break;
1555	case 1:
1556	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1557	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1558	cbOp = pThis->cbOpDefault;
1559	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp);
1560	break;
1561	case 2:
1562	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
1563	return 0;
1564	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1565	pThis->abCurInstr[0] = P_OZ;
1566	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1567	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xAX, X86_GREG_xCX);
1568	cbOp = pThis->cbOpOvrd66;
1569	break;
1570	case 3:
1571	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1572	pThis->abCurInstr[0] = P_OZ;
1573	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1574	cbOp = pThis->cbOpOvrd66;
1575	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xSI, cbOp);
1576	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
1577	break;
1578	case 4:
1579	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1580	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1581	pThis->abCurInstr[off++] = REX_W___;
1582	off = Bs3Cg1InsertOpcodes(pThis, off);
1583	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_xBX, X86_GREG_xDX);
1584	cbOp = pThis->cbOpOvrdRexW;
1585	break;
1586	case 5:
1587	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1588	pThis->abCurInstr[off++] = REX__RB_;
1589	off = Bs3Cg1InsertOpcodes(pThis, off);
1590	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, X86_GREG_x14, X86_GREG_x12);
1591	cbOp = pThis->cbOpDefault;
1592	break;
1593	/* Tests with address overrides go last!*/
1594	case 6:
1595	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1596	pThis->abCurInstr[0] = P_AZ;
1597	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1598	cbOp = pThis->cbOpDefault;
1599	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xDI, cbOp);
1600	break;
1601	case 7:
1602	pThis->abCurInstr[0] = P_OZ;
1603	pThis->abCurInstr[1] = P_AZ;
1604	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1605	cbOp = pThis->cbOpOvrd66;
1606	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xDI, cbOp);
1607	break;
1608	default:
1609	return 0;
1610	}
1611	pThis->aOperands[0].cbOp = cbOp;
1612	pThis->aOperands[1].cbOp = cbOp;
1613	pThis->cbOperand = cbOp;
1614	pThis->cbCurInstr = off;
1615	return iEncoding + 1;
1616	}
1617
1618
1619	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Qq(PBS3CG1STATE pThis, unsigned iEncoding)
1620	{
1621	unsigned off;
1622	switch (iEncoding)
1623	{
1624	case 0:
1625	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1626	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1627	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1628	break;
1629	case 1:
1630	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1631	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1632	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 7);
1633	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1634	break;
1635	#if ARCH_BITS == 64
1636	case 2:
1637	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1638	pThis->abCurInstr[off++] = REX__RBX;
1639	off = Bs3Cg1InsertOpcodes(pThis, off);
1640	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /no +8/, 2 /no +8/);
1641	break;
1642	#endif
1643	case 3:
1644	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1645	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1646	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
1647	break;
1648	case 4:
1649	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1650	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
1651	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1652	break;
1653	#if ARCH_BITS == 64
1654	case 5:
1655	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1656	pThis->abCurInstr[off++] = REX__RBX;
1657	off = Bs3Cg1InsertOpcodes(pThis, off);
1658	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /iReg - no +8/);
1659	break;
1660	#endif
1661
1662	default:
1663	return 0;
1664	}
1665
1666	pThis->cbCurInstr = off;
1667	return iEncoding + 1;
1668	}
1669
1670
1671	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq(PBS3CG1STATE pThis, unsigned iEncoding)
1672	{
1673	unsigned off;
1674	switch (iEncoding)
1675	{
1676	case 0:
1677	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1678	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1679	break;
1680	case 1:
1681	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1682	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1683	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1684	break;
1685	case 2:
1686	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1687	pThis->abCurInstr[off++] = REX__RBX;
1688	off = Bs3Cg1InsertOpcodes(pThis, off);
1689	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /no+8/, 2 + 8);
1690	break;
1691	default:
1692	return 0;
1693	}
1694	pThis->cbCurInstr = off;
1695	return iEncoding + 1;
1696	}
1697
1698
1699	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
1700	{
1701	unsigned off;
1702	switch (iEncoding)
1703	{
1704	case 0:
1705	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1706	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1707	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1708	break;
1709	case 1:
1710	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1711	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1712	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1713	break;
1714	#if ARCH_BITS == 64
1715	case 2:
1716	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1717	pThis->abCurInstr[off++] = REX__RBX;
1718	off = Bs3Cg1InsertOpcodes(pThis, off);
1719	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /no +8/, 2+8);
1720	break;
1721	#endif
1722	case 3:
1723	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1724	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1725	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
1726	break;
1727	case 4:
1728	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1729	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
1730	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1731	break;
1732	#if ARCH_BITS == 64
1733	case 5:
1734	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1735	pThis->abCurInstr[off++] = REX__RBX;
1736	off = Bs3Cg1InsertOpcodes(pThis, off);
1737	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /iReg/);
1738	break;
1739	#endif
1740
1741	default:
1742	return 0;
1743	}
1744	pThis->cbCurInstr = off;
1745	return iEncoding + 1;
1746	}
1747
1748
1749	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
1750	{
1751	#if ARCH_BITS == 64
1752	if (BS3CG1_IS_64BIT_TARGET(pThis))
1753	{
1754	unsigned off;
1755	switch (iEncoding)
1756	{
1757	case 0:
1758	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1759	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1760	pThis->abCurInstr[off++] = REX_W___;
1761	off = Bs3Cg1InsertOpcodes(pThis, off);
1762	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1763	break;
1764	case 1:
1765	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1766	pThis->abCurInstr[off++] = REX_W___;
1767	off = Bs3Cg1InsertOpcodes(pThis, off);
1768	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1769	break;
1770	case 2:
1771	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1772	pThis->abCurInstr[off++] = REX_WRBX;
1773	off = Bs3Cg1InsertOpcodes(pThis, off);
1774	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 /no +8/, 2+8);
1775	break;
1776	case 3:
1777	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1778	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1779	pThis->abCurInstr[off++] = REX_W___;
1780	off = Bs3Cg1InsertOpcodes(pThis, off);
1781	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
1782	break;
1783	case 4:
1784	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1785	pThis->abCurInstr[off++] = REX_W___;
1786	off = Bs3Cg1InsertOpcodes(pThis, off);
1787	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
1788	break;
1789	case 5:
1790	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1791	pThis->abCurInstr[off++] = REX_WRBX;
1792	off = Bs3Cg1InsertOpcodes(pThis, off);
1793	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /iReg/);
1794	break;
1795
1796	default:
1797	return 0;
1798	}
1799	pThis->cbCurInstr = off;
1800	return iEncoding + 1;
1801	}
1802	#endif
1803	return 0;
1804	}
1805
1806
1807	/* Differs from Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ in that REX.R isn't ignored. */
1808	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
1809	{
1810	unsigned off;
1811	switch (iEncoding)
1812	{
1813	case 0:
1814	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1815	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1816	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1817	break;
1818	case 1:
1819	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1820	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1821	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1822	break;
1823	#if ARCH_BITS == 64
1824	case 2:
1825	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1826	pThis->abCurInstr[off++] = REX__RBX;
1827	off = Bs3Cg1InsertOpcodes(pThis, off);
1828	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
1829	break;
1830	#endif
1831	case 3:
1832	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1833	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1834	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
1835	break;
1836	case 4:
1837	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1838	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
1839	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1840	break;
1841	#if ARCH_BITS == 64
1842	case 5:
1843	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1844	pThis->abCurInstr[off++] = REX__RBX;
1845	off = Bs3Cg1InsertOpcodes(pThis, off);
1846	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /iReg/);
1847	break;
1848	#endif
1849
1850	default:
1851	return 0;
1852	}
1853	pThis->cbCurInstr = off;
1854	return iEncoding + 1;
1855	}
1856
1857
1858	/* Differs from Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ in that REX.R isn't ignored. */
1859	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
1860	{
1861	#if ARCH_BITS == 64
1862	if (BS3CG1_IS_64BIT_TARGET(pThis))
1863	{
1864	unsigned off;
1865	switch (iEncoding)
1866	{
1867	case 0:
1868	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1869	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1870	pThis->abCurInstr[off++] = REX_W___;
1871	off = Bs3Cg1InsertOpcodes(pThis, off);
1872	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1873	break;
1874	case 1:
1875	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1876	pThis->abCurInstr[off++] = REX_W___;
1877	off = Bs3Cg1InsertOpcodes(pThis, off);
1878	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
1879	break;
1880	case 2:
1881	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1882	pThis->abCurInstr[off++] = REX_WRBX;
1883	off = Bs3Cg1InsertOpcodes(pThis, off);
1884	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
1885	break;
1886	case 4:
1887	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1888	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1889	pThis->abCurInstr[off++] = REX_W___;
1890	off = Bs3Cg1InsertOpcodes(pThis, off);
1891	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
1892	break;
1893	case 5:
1894	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1895	pThis->abCurInstr[off++] = REX_W___;
1896	off = Bs3Cg1InsertOpcodes(pThis, off);
1897	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
1898	break;
1899	case 6:
1900	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1901	pThis->abCurInstr[off++] = REX_WRBX;
1902	off = Bs3Cg1InsertOpcodes(pThis, off);
1903	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7+8 /iReg/);
1904	break;
1905
1906	default:
1907	return 0;
1908	}
1909	pThis->cbCurInstr = off;
1910	return iEncoding + 1;
1911	}
1912	#endif
1913	return 0;
1914	}
1915
1916
1917	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1918	{
1919	unsigned off;
1920	switch (iEncoding)
1921	{
1922	case 0:
1923	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1924	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1925	break;
1926	case 1:
1927	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1928	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 2, 2);
1929	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1930	break;
1931	case 2:
1932	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1933	pThis->abCurInstr[off++] = REX__RBX;
1934	off = Bs3Cg1InsertOpcodes(pThis, off);
1935	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 3+8, 7+8);
1936	break;
1937	default:
1938	return 0;
1939	}
1940	pThis->cbCurInstr = off;
1941	return iEncoding + 1;
1942	}
1943
1944
1945	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
1946	{
1947	unsigned off;
1948	switch (iEncoding)
1949	{
1950	case 0:
1951	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
1952	off = Bs3Cg1InsertModRmWithRegFields(pThis, Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)), 1, 0);
1953	break;
1954	case 1:
1955	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
1956	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1957	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /iReg/);
1958	break;
1959	case 2:
1960	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1961	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /iReg/, 1 /cbMisalign/);
1962	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1963	pThis->bAlignmentXcpt = X86_XCPT_GP;
1964	break;
1965	default:
1966	return 0;
1967	}
1968	pThis->cbCurInstr = off;
1969	return iEncoding + 1;
1970	}
1971
1972
1973	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Vsomething_Nsomething(PBS3CG1STATE pThis, unsigned iEncoding)
1974	{
1975	unsigned off;
1976	switch (iEncoding)
1977	{
1978	case 0:
1979	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1980	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
1981	break;
1982	case 1:
1983	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1984	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 7);
1985	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
1986	break;
1987	case 2:
1988	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1989	pThis->abCurInstr[off++] = REX_WRBX;
1990	off = Bs3Cg1InsertOpcodes(pThis, off);
1991	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6 + 8, 7 /no +8/);
1992	break;
1993
1994	default:
1995	return 0;
1996	}
1997	pThis->cbCurInstr = off;
1998	return iEncoding + 1;
1999	}
2000
2001
2002	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma(PBS3CG1STATE pThis, unsigned iEncoding) /* bound instr */
2003	{
2004	unsigned off;
2005	unsigned cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
2006	switch (iEncoding)
2007	{
2008	case 0:
2009	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2010	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp * 2);
2011	break;
2012	case 1:
2013	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
2014	return 0;
2015	cbOp = cbOp == 2 ? 4 : 2;
2016	pThis->abCurInstr[0] = P_OZ;
2017	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2018	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaults(pThis, off, X86_GREG_xBP, cbOp * 2);
2019	break;
2020	case 2:
2021	pThis->abCurInstr[0] = P_AZ;
2022	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2023	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xBP, cbOp * 2);
2024	break;
2025	case 3:
2026	cbOp = cbOp == 2 ? 4 : 2;
2027	pThis->abCurInstr[0] = P_AZ;
2028	pThis->abCurInstr[1] = P_OZ;
2029	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
2030	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndSizeAndDefaultsAddrOverride(pThis, off, X86_GREG_xBP, cbOp * 2);
2031	break;
2032	default:
2033	return 0;
2034	}
2035	pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
2036	pThis->cbOperand = cbOp;
2037	pThis->cbCurInstr = off;
2038	return iEncoding + 1;
2039	}
2040
2041
2042	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething(PBS3CG1STATE pThis, unsigned iEncoding)
2043	{
2044	unsigned off;
2045	switch (iEncoding)
2046	{
2047	case 0:
2048	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
2049	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
2050	break;
2051	default:
2052	return 0;
2053	}
2054	pThis->cbCurInstr = off;
2055	return iEncoding + 1;
2056	}
2057
2058
2059	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething_Psomething(PBS3CG1STATE pThis, unsigned iEncoding)
2060	{
2061	unsigned off;
2062	switch (iEncoding)
2063	{
2064	case 0:
2065	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2066	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
2067	break;
2068	case 1:
2069	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2070	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 7 /iReg/, 1 /cbMisalign/);
2071	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2072	break;
2073	#if ARCH_BITS == 64
2074	case 2:
2075	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2076	pThis->abCurInstr[off++] = REX__RBX;
2077	off = Bs3Cg1InsertOpcodes(pThis, off);
2078	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 /iReg - no +8/);
2079	break;
2080	#endif
2081
2082	default:
2083	return 0;
2084	}
2085
2086	pThis->cbCurInstr = off;
2087	return iEncoding + 1;
2088	}
2089
2090
2091	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2092	{
2093	unsigned off;
2094	switch (iEncoding)
2095	{
2096	case 0:
2097	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2098	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /iReg/);
2099	break;
2100	case 1:
2101	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2102	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 2 /iReg/, 1 /cbMisalign/ );
2103	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
2104	pThis->bAlignmentXcpt = X86_XCPT_GP;
2105	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2106	break;
2107	case 2:
2108	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2109	pThis->abCurInstr[off++] = REX__R__;
2110	off = Bs3Cg1InsertOpcodes(pThis, off);
2111	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2+8 /iReg/);
2112	break;
2113	default:
2114	return 0;
2115	}
2116	pThis->cbCurInstr = off;
2117	return iEncoding + 1;
2118	}
2119
2120
2121	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
2122	{
2123	unsigned off;
2124	switch (iEncoding)
2125	{
2126	case 0:
2127	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2128	pThis->cbCurInstr = off;
2129	break;
2130	default:
2131	return 0;
2132	}
2133	return iEncoding + 1;
2134	}
2135
2136
2137	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
2138	{
2139	unsigned off;
2140	switch (iEncoding)
2141	{
2142	case 0:
2143	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2144	pThis->aOperands[1].off = (uint8_t)off;
2145	pThis->abCurInstr[off++] = 0xff;
2146	pThis->cbCurInstr = off;
2147	break;
2148	default:
2149	return 0;
2150	}
2151	return iEncoding + 1;
2152	}
2153
2154
2155	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
2156	{
2157	unsigned off;
2158	unsigned cbOp;
2159	switch (iEncoding)
2160	{
2161	case 0:
2162	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
2163	pThis->aOperands[1].off = (uint8_t)off;
2164	cbOp = pThis->cbOpDefault;
2165	if (cbOp == 2)
2166	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
2167	else
2168	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2169	off += cbOp;
2170	pThis->aOperands[0].cbOp = cbOp;
2171	pThis->aOperands[1].cbOp = cbOp;
2172	pThis->cbOperand = cbOp;
2173	break;
2174	case 1:
2175	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80386)
2176	return 0;
2177	pThis->abCurInstr[0] = P_OZ;
2178	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
2179	pThis->aOperands[1].off = (uint8_t)off;
2180	cbOp = pThis->cbOpOvrd66;
2181	if (cbOp == 2)
2182	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
2183	else
2184	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2185	off += cbOp;
2186	pThis->aOperands[0].cbOp = cbOp;
2187	pThis->aOperands[1].cbOp = cbOp;
2188	pThis->cbOperand = cbOp;
2189	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2190	break;
2191	case 2:
2192	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2193	pThis->abCurInstr[off++] = REX_W___;
2194	off = Bs3Cg1InsertOpcodes(pThis, off);
2195	pThis->aOperands[1].off = (uint8_t)off;
2196	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2197	off += 4;
2198	pThis->aOperands[0].cbOp = 8;
2199	pThis->aOperands[1].cbOp = 4;
2200	pThis->cbOperand = 8;
2201	break;
2202	default:
2203	return 0;
2204
2205	/* IMAGE PADDING - workaround for "rd err" - remove later! */
2206	case 4:
2207	ASMHalt();
2208	ASMHalt();
2209	ASMHalt();
2210	return 0;
2211
2212	}
2213	pThis->cbCurInstr = off;
2214	return iEncoding + 1;
2215	}
2216
2217
2218	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
2219	{
2220	unsigned off;
2221	if (iEncoding < 8)
2222	{
2223	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2224	off = Bs3Cg1InsertOpcodes(pThis, off);
2225	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
2226	}
2227	else if (iEncoding < 16)
2228	{
2229	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2230	off = Bs3Cg1InsertOpcodes(pThis, off);
2231	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
2232	}
2233	else
2234	return 0;
2235	pThis->cbCurInstr = off;
2236
2237	return iEncoding + 1;
2238	}
2239
2240
2241	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
2242	{
2243	unsigned off;
2244	if (iEncoding < 3)
2245	{
2246	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2247	off = Bs3Cg1InsertOpcodes(pThis, off);
2248	pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
2249	if (iEncoding >= 1)
2250	pThis->abCurInstr[off++] = 0x7f;
2251	if (iEncoding == 2)
2252	{
2253	pThis->abCurInstr[off++] = 0x5f;
2254	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2255	{
2256	pThis->abCurInstr[off++] = 0x3f;
2257	pThis->abCurInstr[off++] = 0x1f;
2258	}
2259	}
2260	}
2261	else
2262	return 0;
2263	pThis->cbCurInstr = off;
2264	return iEncoding + 1;
2265	}
2266
2267
2268	/*
2269	*
2270	* VEX
2271	* VEX
2272	* VEX
2273	*
2274	*/
2275	#ifdef BS3CG1_WITH_VEX
2276
2277	/**
2278	* Inserts a 3-byte VEX prefix.
2279	*
2280	* @returns New offDst value.
2281	* @param pThis The state.
2282	* @param offDst The current instruction offset.
2283	* @param uVexL The VEX.L value.
2284	* @param uVexV The VEX.V value (caller inverted it already).
2285	* @param uVexR The VEX.R value (caller inverted it already).
2286	* @param uVexX The VEX.X value (caller inverted it already).
2287	* @param uVexB The VEX.B value (caller inverted it already).
2288	* @param uVexW The VEX.W value (straight).
2289	*/
2290	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
2291	uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
2292	{
2293	uint8_t b1;
2294	uint8_t b2;
2295	b1 = uVexR << 7;
2296	b1 \|= uVexX << 6;
2297	b1 \|= uVexB << 5;
2298	b1 \|= pThis->uOpcodeMap;
2299	b2 = uVexV << 3;
2300	b2 \|= uVexW << 7;
2301	b2 \|= uVexL << 2;
2302	switch (pThis->enmPrefixKind)
2303	{
2304	case BS3CG1PFXKIND_NO_F2_F3_66: b2 \|= 0; break;
2305	case BS3CG1PFXKIND_REQ_66: b2 \|= 1; break;
2306	case BS3CG1PFXKIND_REQ_F3: b2 \|= 2; break;
2307	case BS3CG1PFXKIND_REQ_F2: b2 \|= 3; break;
2308	default:
2309	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
2310	break;
2311	}
2312
2313	pThis->abCurInstr[offDst] = 0xc4; /* vex3 */
2314	pThis->abCurInstr[offDst + 1] = b1;
2315	pThis->abCurInstr[offDst + 2] = b2;
2316	pThis->uVexL = uVexL;
2317	return offDst + 3;
2318	}
2319
2320
2321	/**
2322	* Inserts a 2-byte VEX prefix.
2323	*
2324	* @note Will switch to 3-byte VEX prefix if uOpcodeMap isn't one.
2325	*
2326	* @returns New offDst value.
2327	* @param pThis The state.
2328	* @param offDst The current instruction offset.
2329	* @param uVexL The VEX.L value.
2330	* @param uVexV The VEX.V value (caller inverted it already).
2331	* @param uVexR The VEX.R value (caller inverted it already).
2332	*/
2333	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
2334	uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
2335	{
2336	if (pThis->uOpcodeMap == 1)
2337	{
2338	uint8_t b = uVexR << 7;
2339	b \|= uVexV << 3;
2340	b \|= uVexL << 2;
2341	switch (pThis->enmPrefixKind)
2342	{
2343	case BS3CG1PFXKIND_NO_F2_F3_66: b \|= 0; break;
2344	case BS3CG1PFXKIND_REQ_66: b \|= 1; break;
2345	case BS3CG1PFXKIND_REQ_F3: b \|= 2; break;
2346	case BS3CG1PFXKIND_REQ_F2: b \|= 3; break;
2347	default:
2348	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
2349	break;
2350	}
2351
2352	pThis->abCurInstr[offDst] = 0xc5; /* vex2 */
2353	pThis->abCurInstr[offDst + 1] = b;
2354	pThis->uVexL = uVexL;
2355	return offDst + 2;
2356	}
2357	return Bs3Cg1InsertVex3bPrefix(pThis, offDst, uVexV, uVexL, uVexR, 1 /uVexX/, 1 /uVexB/, 0/uVexW/);
2358	}
2359
2360
2361	/**
2362	* Inserts a ModR/M byte with mod=3 and set the two idxFields members.
2363	*
2364	* @returns off + 1.
2365	* @param pThis The state.
2366	* @param off Current instruction offset.
2367	* @param uReg Register index for ModR/M.reg.
2368	* @param uRegMem Register index for ModR/M.rm.
2369	* @param uVexVvvv The VEX.vvvv register.
2370	*/
2371	static unsigned Bs3Cg1InsertModRmWithRegFieldsAndVvvv(PBS3CG1STATE pThis, unsigned off,
2372	uint8_t uReg, uint8_t uRegMem, uint8_t uVexVvvv)
2373	{
2374	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, uReg & 7, uRegMem & 7);
2375	pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + uReg;
2376	pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + uVexVvvv;
2377	pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + uRegMem;
2378	return off;
2379	}
2380
2381
2382	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Vd_WO_Ed_WZ(PBS3CG1STATE pThis, unsigned iEncoding)
2383	{
2384	unsigned off;
2385	switch (iEncoding)
2386	{
2387	case 0:
2388	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
2389	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2390	off = Bs3Cg1InsertOpcodes(pThis, off);
2391	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
2392	break;
2393	case 1:
2394	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2395	off = Bs3Cg1InsertOpcodes(pThis, off);
2396	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2397	break;
2398	case 2:
2399	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L-invalid/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2400	off = Bs3Cg1InsertOpcodes(pThis, off);
2401	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2402	pThis->fInvalidEncoding = true;
2403	break;
2404	case 3:
2405	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xe /~V-invalid/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2406	off = Bs3Cg1InsertOpcodes(pThis, off);
2407	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2408	pThis->fInvalidEncoding = true;
2409	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2410	break;
2411	#if ARCH_BITS == 64
2412	case 4:
2413	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 0 /~B/, 0 /W/);
2414	off = Bs3Cg1InsertOpcodes(pThis, off);
2415	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
2416	break;
2417	#endif
2418	case 5:
2419	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
2420	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2421	off = Bs3Cg1InsertOpcodes(pThis, off);
2422	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
2423	break;
2424	case 6:
2425	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2426	off = Bs3Cg1InsertOpcodes(pThis, off);
2427	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
2428	break;
2429	case 7:
2430	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2431	off = Bs3Cg1InsertOpcodes(pThis, off);
2432	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /iReg/, 1 /cbMisalign/);
2433	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2434	break;
2435	#if ARCH_BITS == 64
2436	case 8:
2437	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2438	off = Bs3Cg1InsertOpcodes(pThis, off);
2439	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /iReg/);
2440	break;
2441	case 9:
2442	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/);
2443	off = Bs3Cg1InsertOpcodes(pThis, off);
2444	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8 /iReg/);
2445	iEncoding += 2;
2446	break;
2447	#endif
2448	case 10: /* VEX.W is ignored in 32-bit mode. flag? */
2449	BS3_ASSERT(!BS3CG1_IS_64BIT_TARGET(pThis));
2450	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2451	off = Bs3Cg1InsertOpcodes(pThis, off);
2452	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
2453	break;
2454
2455	default:
2456	return 0;
2457	}
2458	pThis->cbCurInstr = off;
2459	return iEncoding + 1;
2460	}
2461
2462
2463	/* Differs from Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ in that REX.R isn't ignored. */
2464	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Vq_WO_Eq_WNZ(PBS3CG1STATE pThis, unsigned iEncoding)
2465	{
2466	#if ARCH_BITS == 64
2467	if (BS3CG1_IS_64BIT_TARGET(pThis))
2468	{
2469	unsigned off;
2470	switch (iEncoding)
2471	{
2472	case 0:
2473	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
2474	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2475	off = Bs3Cg1InsertOpcodes(pThis, off);
2476	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2477	break;
2478	case 1:
2479	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L-invalid/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2480	off = Bs3Cg1InsertOpcodes(pThis, off);
2481	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2482	pThis->fInvalidEncoding = true;
2483	break;
2484	case 2:
2485	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xe /~V-invalid/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2486	off = Bs3Cg1InsertOpcodes(pThis, off);
2487	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6, 2);
2488	pThis->fInvalidEncoding = true;
2489	break;
2490	case 3:
2491	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 0 /~B/, 1 /W/);
2492	off = Bs3Cg1InsertOpcodes(pThis, off);
2493	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 6+8, 2+8);
2494	break;
2495	case 4:
2496	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
2497	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2498	off = Bs3Cg1InsertOpcodes(pThis, off);
2499	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4 /iReg/);
2500	break;
2501	case 5:
2502	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2503	off = Bs3Cg1InsertOpcodes(pThis, off);
2504	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 4 /iReg/, 1 /cbMisalign/);
2505	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2506	break;
2507	case 6:
2508	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
2509	off = Bs3Cg1InsertOpcodes(pThis, off);
2510	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 4+8 /iReg/);
2511	break;
2512
2513	default:
2514	return 0;
2515	}
2516	pThis->cbCurInstr = off;
2517	return iEncoding + 1;
2518	}
2519	#endif
2520	return 0;
2521	}
2522
2523
2524	/**
2525	* Wip - VEX.W ignored.
2526	* Lig - VEX.L ignored.
2527	*/
2528	static unsigned BS3_NEAR_CODE
2529	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2530	{
2531	unsigned off;
2532	switch (iEncoding)
2533	{
2534	case 0:
2535	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2536	off = Bs3Cg1InsertOpcodes(pThis, off);
2537	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2538	break;
2539	case 1:
2540	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0x8 /~V/, 1 /L-ignored/, 1 /~R/);
2541	off = Bs3Cg1InsertOpcodes(pThis, off);
2542	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3, 1, 7);
2543	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2544	break;
2545	case 2:
2546	#if ARCH_BITS == 64
2547	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 0 /~R/);
2548	off = Bs3Cg1InsertOpcodes(pThis, off);
2549	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3+8, 2, 15);
2550	break;
2551	#endif
2552	case 3:
2553	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2554	off = Bs3Cg1InsertOpcodes(pThis, off);
2555	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2556	break;
2557	case 4:
2558	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - ignored/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2559	off = Bs3Cg1InsertOpcodes(pThis, off);
2560	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2561	break;
2562	case 5:
2563	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xc /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2564	off = Bs3Cg1InsertOpcodes(pThis, off);
2565	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 3);
2566	break;
2567	case 6:
2568	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2569	off = Bs3Cg1InsertOpcodes(pThis, off);
2570	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2571	break;
2572	case 7:
2573	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2574	off = Bs3Cg1InsertOpcodes(pThis, off);
2575	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2576	break;
2577	default:
2578	return 0;
2579	}
2580	pThis->cbCurInstr = off;
2581	return iEncoding + 1;
2582	}
2583
2584
2585	/**
2586	* Wip - VEX.W ignored.
2587	*/
2588	static unsigned BS3_NEAR_CODE
2589	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2590	{
2591	unsigned off;
2592	switch (iEncoding)
2593	{
2594	case 0:
2595	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2596	off = Bs3Cg1InsertOpcodes(pThis, off);
2597	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2598	break;
2599	case 1:
2600	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0x8 /~V/, 1 /L-ignored/, 1 /~R/);
2601	off = Bs3Cg1InsertOpcodes(pThis, off);
2602	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3, 1, 7);
2603	pThis->fInvalidEncoding = true;
2604	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2605	break;
2606	case 2:
2607	#if ARCH_BITS == 64
2608	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 0 /~R/);
2609	off = Bs3Cg1InsertOpcodes(pThis, off);
2610	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 3+8, 2, 15);
2611	break;
2612	#endif
2613	case 3:
2614	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2615	off = Bs3Cg1InsertOpcodes(pThis, off);
2616	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2617	break;
2618	case 4:
2619	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - ignored/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2620	off = Bs3Cg1InsertOpcodes(pThis, off);
2621	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 0);
2622	pThis->fInvalidEncoding = true;
2623	break;
2624	case 5:
2625	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xc /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2626	off = Bs3Cg1InsertOpcodes(pThis, off);
2627	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, 3);
2628	break;
2629	case 6:
2630	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2631	off = Bs3Cg1InsertOpcodes(pThis, off);
2632	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2633	break;
2634	case 7:
2635	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2636	off = Bs3Cg1InsertOpcodes(pThis, off);
2637	off = Bs3Cg1InsertModRmWithRegFieldsAndVvvv(pThis, off, 2, 1, BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
2638	break;
2639	default:
2640	return 0;
2641	}
2642	pThis->cbCurInstr = off;
2643	return iEncoding + 1;
2644	}
2645
2646
2647	/**
2648	* Wip - VEX.W ignored.
2649	*/
2650	static unsigned BS3_NEAR_CODE
2651	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2652	{
2653	unsigned off;
2654	switch (iEncoding)
2655	{
2656	case 20: /* Switch to 256-bit operands. */
2657	pThis->aOperands[pThis->iRegOp].idxFieldBase = BS3CG1DST_YMM0;
2658	pThis->aOperands[pThis->iRegOp].cbOp = 32;
2659	pThis->aOperands[pThis->iRmOp ].cbOp = 32;
2660	RT_FALL_THRU();
2661	case 0:
2662	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/);
2663	off = Bs3Cg1InsertOpcodes(pThis, off);
2664	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2665	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2666	break;
2667	#if ARCH_BITS == 64
2668	case 1:
2669	case 21:
2670	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 0 /~R/);
2671	off = Bs3Cg1InsertOpcodes(pThis, off);
2672	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2673	break;
2674	#endif
2675	case 2:
2676	case 22:
2677	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, iEncoding >= 20 /L/, 1 /~R/);
2678	off = Bs3Cg1InsertOpcodes(pThis, off);
2679	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2680	pThis->fInvalidEncoding = true;
2681	break;
2682	case 3:
2683	case 23:
2684	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2685	off = Bs3Cg1InsertOpcodes(pThis, off);
2686	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2687	break;
2688	case 4:
2689	case 24:
2690	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2691	off = Bs3Cg1InsertOpcodes(pThis, off);
2692	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2693	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2694	break;
2695	#if ARCH_BITS == 64
2696	case 5:
2697	case 25:
2698	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2699	off = Bs3Cg1InsertOpcodes(pThis, off);
2700	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2701	break;
2702	case 6:
2703	case 26:
2704	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 0 /~B-ignored/, 0 /W/);
2705	off = Bs3Cg1InsertOpcodes(pThis, off);
2706	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2707	break;
2708	case 7:
2709	case 27:
2710	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 0 /~X-ignored/, 1 /~B/, 0 /W/);
2711	off = Bs3Cg1InsertOpcodes(pThis, off);
2712	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2713	break;
2714	#endif
2715	case 8:
2716	case 28:
2717	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2718	off = Bs3Cg1InsertOpcodes(pThis, off);
2719	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2720	pThis->fInvalidEncoding = true;
2721	break;
2722	case 9:
2723	case 29:
2724	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 7 /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2725	off = Bs3Cg1InsertOpcodes(pThis, off);
2726	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2727	pThis->fInvalidEncoding = true;
2728	iEncoding += 10;
2729	break;
2730
2731	default:
2732	return 0;
2733	}
2734	pThis->cbCurInstr = off;
2735	return iEncoding + 1;
2736	}
2737
2738
2739
2740	/**
2741	* Wip - VEX.W ignored.
2742	* Lig - VEX.L ignored.
2743	*/
2744	static unsigned BS3_NEAR_CODE
2745	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2746	{
2747	unsigned off;
2748	switch (iEncoding)
2749	{
2750	case 0:
2751	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2752	off = Bs3Cg1InsertOpcodes(pThis, off);
2753	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2754	break;
2755	case 1:
2756	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - ignored/, 1 /~R/);
2757	off = Bs3Cg1InsertOpcodes(pThis, off);
2758	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
2759	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2760	break;
2761	#if ARCH_BITS == 64
2762	case 2:
2763	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - ignored/, 0 /~R/);
2764	off = Bs3Cg1InsertOpcodes(pThis, off);
2765	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2766	break;
2767	#endif
2768	case 3:
2769	iEncoding = 3;
2770	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, 0 /L/, 1 /~R/);
2771	off = Bs3Cg1InsertOpcodes(pThis, off);
2772	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2773	pThis->fInvalidEncoding = true;
2774	break;
2775	case 4:
2776	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2777	off = Bs3Cg1InsertOpcodes(pThis, off);
2778	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2779	break;
2780	case 5:
2781	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L-ignored/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2782	off = Bs3Cg1InsertOpcodes(pThis, off);
2783	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2784	break;
2785	case 6:
2786	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2787	off = Bs3Cg1InsertOpcodes(pThis, off);
2788	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2789	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2790	break;
2791	#if ARCH_BITS == 64
2792	case 7:
2793	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2794	off = Bs3Cg1InsertOpcodes(pThis, off);
2795	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2796	break;
2797	case 8:
2798	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 0 /~B-ignored/, 0 /W/);
2799	off = Bs3Cg1InsertOpcodes(pThis, off);
2800	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2801	break;
2802	case 9:
2803	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 0 /~X-ignored/, 1 /~B/, 0 /W/);
2804	off = Bs3Cg1InsertOpcodes(pThis, off);
2805	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2806	break;
2807	#endif
2808	case 10:
2809	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2810	off = Bs3Cg1InsertOpcodes(pThis, off);
2811	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2812	pThis->fInvalidEncoding = true;
2813	break;
2814	case 11:
2815	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 7 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2816	off = Bs3Cg1InsertOpcodes(pThis, off);
2817	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2818	pThis->fInvalidEncoding = true;
2819	break;
2820	default:
2821	return 0;
2822	}
2823	pThis->cbCurInstr = off;
2824	return iEncoding + 1;
2825	}
2826
2827
2828	/**
2829	* Wip - VEX.W ignored.
2830	* L0 - VEX.L must be zero.
2831	*/
2832	static unsigned BS3_NEAR_CODE
2833	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
2834	{
2835	unsigned off;
2836	switch (iEncoding)
2837	{
2838	case 0:
2839	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
2840	off = Bs3Cg1InsertOpcodes(pThis, off);
2841	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2842	break;
2843	case 1:
2844	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - invalid/, 1 /~R/);
2845	off = Bs3Cg1InsertOpcodes(pThis, off);
2846	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
2847	pThis->fInvalidEncoding = true;
2848	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 : 0;
2849	break;
2850	#if ARCH_BITS == 64
2851	case 2:
2852	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/);
2853	off = Bs3Cg1InsertOpcodes(pThis, off);
2854	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2855	break;
2856	case 3:
2857	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - invalid/, 0 /~R/);
2858	off = Bs3Cg1InsertOpcodes(pThis, off);
2859	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5 + 8);
2860	pThis->fInvalidEncoding = true;
2861	break;
2862	#endif
2863	case 4:
2864	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, 0 /L/, 1 /~R/);
2865	off = Bs3Cg1InsertOpcodes(pThis, off);
2866	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2867	pThis->fInvalidEncoding = true;
2868	break;
2869	case 5:
2870	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2871	off = Bs3Cg1InsertOpcodes(pThis, off);
2872	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2873	break;
2874	case 6:
2875	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L - invalid/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2876	off = Bs3Cg1InsertOpcodes(pThis, off);
2877	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2878	pThis->fInvalidEncoding = true;
2879	break;
2880	case 7:
2881	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2882	off = Bs3Cg1InsertOpcodes(pThis, off);
2883	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2884	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2885	break;
2886	#if ARCH_BITS == 64
2887	case 8:
2888	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2889	off = Bs3Cg1InsertOpcodes(pThis, off);
2890	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2891	break;
2892	case 9:
2893	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 0 /~B-ignored/, 0 /W/);
2894	off = Bs3Cg1InsertOpcodes(pThis, off);
2895	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2896	break;
2897	case 10:
2898	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 0 /~X-ignored/, 1 /~B/, 0 /W/);
2899	off = Bs3Cg1InsertOpcodes(pThis, off);
2900	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2901	break;
2902	#endif
2903	case 11:
2904	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2905	off = Bs3Cg1InsertOpcodes(pThis, off);
2906	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2907	pThis->fInvalidEncoding = true;
2908	break;
2909	case 12:
2910	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 7 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2911	off = Bs3Cg1InsertOpcodes(pThis, off);
2912	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2913	pThis->fInvalidEncoding = true;
2914	break;
2915	default:
2916	return 0;
2917	}
2918	pThis->cbCurInstr = off;
2919	return iEncoding + 1;
2920	}
2921
2922
2923	/**
2924	* Wip - VEX.W ignored.
2925	*/
2926	static unsigned BS3_NEAR_CODE
2927	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding, uint8_t uVexL)
2928	{
2929	unsigned off;
2930	switch (iEncoding)
2931	{
2932	case 0:
2933	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 1 /~R/);
2934	off = Bs3Cg1InsertOpcodes(pThis, off);
2935	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2936	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
2937	break;
2938	#if ARCH_BITS == 64
2939	case 1:
2940	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 0 /~R/);
2941	off = Bs3Cg1InsertOpcodes(pThis, off);
2942	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
2943	break;
2944	#endif
2945	case 2:
2946	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, uVexL, 1 /~R/);
2947	off = Bs3Cg1InsertOpcodes(pThis, off);
2948	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
2949	pThis->fInvalidEncoding = true;
2950	break;
2951	case 3:
2952	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2953	off = Bs3Cg1InsertOpcodes(pThis, off);
2954	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2955	break;
2956	case 4:
2957	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
2958	off = Bs3Cg1InsertOpcodes(pThis, off);
2959	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2960	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
2961	break;
2962	#if ARCH_BITS == 64
2963	case 5:
2964	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2965	off = Bs3Cg1InsertOpcodes(pThis, off);
2966	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
2967	break;
2968	case 6:
2969	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 1 /~R/, 1 /~X/, 0 /~B-ignored/, 0 /W/);
2970	off = Bs3Cg1InsertOpcodes(pThis, off);
2971	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
2972	break;
2973	case 7:
2974	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, uVexL, 1 /~R/, 0 /~X-ignored/, 1 /~B/, 0 /W/);
2975	off = Bs3Cg1InsertOpcodes(pThis, off);
2976	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2977	break;
2978	#endif
2979	case 8:
2980	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, uVexL, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2981	off = Bs3Cg1InsertOpcodes(pThis, off);
2982	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
2983	pThis->fInvalidEncoding = true;
2984	break;
2985	case 9:
2986	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 7 /~V/, uVexL, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
2987	off = Bs3Cg1InsertOpcodes(pThis, off);
2988	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
2989	pThis->fInvalidEncoding = true;
2990	break;
2991	default:
2992	return 0;
2993	}
2994	pThis->cbCurInstr = off;
2995	return iEncoding + 1;
2996	}
2997
2998
2999	/**
3000	* Wip - VEX.W ignored.
3001	* L0 - VEX.L is zero (encoding may exist where it isn't).
3002	*/
3003	static unsigned BS3_NEAR_CODE
3004	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3005	{
3006	return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 0 /uVexL/);
3007	}
3008
3009
3010	/**
3011	* Wip - VEX.W ignored.
3012	* L1 - VEX.L is one (encoding may exist where it isn't).
3013	*/
3014	static unsigned BS3_NEAR_CODE
3015	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3016	{
3017	return Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lxx_OR_ViceVersa(pThis, iEncoding, 1 /uVexL/);
3018	}
3019
3020
3021
3022	/**
3023	* Wip - VEX.W ignored.
3024	*/
3025	static unsigned BS3_NEAR_CODE
3026	Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3027	{
3028	unsigned off;
3029	switch (iEncoding)
3030	{
3031	case 0:
3032	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xc /~V/, 0 /L/, 1 /~R/);
3033	off = Bs3Cg1InsertOpcodes(pThis, off);
3034	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
3035	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 3;
3036	break;
3037	case 1:
3038	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/);
3039	off = Bs3Cg1InsertOpcodes(pThis, off);
3040	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7);
3041	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3042	pThis->fInvalidEncoding = true;
3043	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
3044	break;
3045	#if ARCH_BITS == 64
3046	case 2:
3047	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0x1 /~V/, 0 /L/, 0 /~R/);
3048	off = Bs3Cg1InsertOpcodes(pThis, off);
3049	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 7 + 8);
3050	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 14;
3051	break;
3052	#endif
3053	case 3:
3054	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, 0 /L/, 1 /~R/);
3055	off = Bs3Cg1InsertOpcodes(pThis, off);
3056	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 0);
3057	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 1;
3058	break;
3059	case 4:
3060	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3061	off = Bs3Cg1InsertOpcodes(pThis, off);
3062	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3063	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3064	break;
3065	case 5:
3066	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L-ignored/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3067	off = Bs3Cg1InsertOpcodes(pThis, off);
3068	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3069	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3070	pThis->fInvalidEncoding = true;
3071	break;
3072	case 6:
3073	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W-ignored/);
3074	off = Bs3Cg1InsertOpcodes(pThis, off);
3075	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
3076	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3077	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 3 : 0;
3078	break;
3079	#if ARCH_BITS == 64
3080	case 7:
3081	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 0 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3082	off = Bs3Cg1InsertOpcodes(pThis, off);
3083	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5+8);
3084	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3085	break;
3086	case 8:
3087	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 0 /~B-ignored/, 0 /W/);
3088	off = Bs3Cg1InsertOpcodes(pThis, off);
3089	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 1);
3090	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3091	break;
3092	case 9:
3093	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 0 /~X-ignored/, 1 /~B/, 0 /W/);
3094	off = Bs3Cg1InsertOpcodes(pThis, off);
3095	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2);
3096	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0;
3097	break;
3098	#endif
3099	case 10:
3100	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 1 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3101	off = Bs3Cg1InsertOpcodes(pThis, off);
3102	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 5);
3103	pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3CG1_IS_64BIT_TARGET(pThis) ? 15 : 7);
3104	pThis->fInvalidEncoding = true;
3105	break;
3106	default:
3107	return 0;
3108	}
3109	pThis->cbCurInstr = off;
3110	return iEncoding + 1;
3111	}
3112
3113
3114	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding)
3115	{
3116	unsigned off;
3117	switch (iEncoding)
3118	{
3119	case 0:
3120	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3121	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3122	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3123	break;
3124	case 1:
3125	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3126	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3127	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3128	break;
3129	case 2:
3130	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0x7 /~V-invalid/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3131	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3132	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3133	pThis->fInvalidEncoding = true;
3134	break;
3135	case 3:
3136	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3137	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3138	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3139	pThis->fInvalidEncoding = true;
3140	break;
3141	case 4:
3142	pThis->abCurInstr[0] = P_OZ;
3143	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3144	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3145	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3146	pThis->fInvalidEncoding = true;
3147	break;
3148	case 5:
3149	pThis->abCurInstr[0] = P_RZ;
3150	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3151	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3152	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3153	pThis->fInvalidEncoding = true;
3154	break;
3155	case 6:
3156	pThis->abCurInstr[0] = P_RN;
3157	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3158	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3159	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3160	pThis->fInvalidEncoding = true;
3161	break;
3162	case 7:
3163	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
3164	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3165	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3166	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 1 : 0;
3167	break;
3168	#if ARCH_BITS == 64
3169	case 8:
3170	pThis->abCurInstr[0] = REX_____;
3171	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3172	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
3173	off = Bs3Cfg1EncodeMemMod0DispWithDefaultsAndNoReg(pThis, off);
3174	pThis->fInvalidEncoding = true;
3175	break;
3176	#endif
3177	default:
3178	return 0;
3179	}
3180
3181	pThis->cbCurInstr = off;
3182	return iEncoding + 1;
3183	}
3184
3185
3186	/**
3187	* Wip = VEX.W ignored.
3188	* Lmbz = VEX.L must be zero.
3189	*/
3190	static unsigned BS3_NEAR_CODE
3191	Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3192	{
3193	unsigned off;
3194	switch (iEncoding)
3195	{
3196	/* 128-bit wide stuff goes first, then we'll update the operand widths afterwards. */
3197	case 0:
3198	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3199	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3200	off = Bs3Cg1InsertOpcodes(pThis, off);
3201	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3202	break;
3203
3204	case 1:
3205	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3206	off = Bs3Cg1InsertOpcodes(pThis, off);
3207	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3208	break;
3209	case 2:
3210	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W - ignored/);
3211	off = Bs3Cg1InsertOpcodes(pThis, off);
3212	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 5, 4);
3213	break;
3214	case 3:
3215	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
3216	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3217	off = Bs3Cg1InsertOpcodes(pThis, off);
3218	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /iReg/);
3219	break;
3220	case 4:
3221	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3222	off = Bs3Cg1InsertOpcodes(pThis, off);
3223	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /iReg/);
3224	break;
3225	case 5:
3226	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W - ignored /);
3227	off = Bs3Cg1InsertOpcodes(pThis, off);
3228	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /iReg/);
3229	break;
3230	case 6:
3231	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3232	off = Bs3Cg1InsertOpcodes(pThis, off);
3233	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /iReg/, 1 /cbMisalign/);
3234	if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3235	pThis->bAlignmentXcpt = X86_XCPT_GP;
3236	break;
3237	case 7:
3238	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3239	off = Bs3Cg1InsertOpcodes(pThis, off);
3240	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /iReg/, 1 /cbMisalign/);
3241	if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3242	pThis->bAlignmentXcpt = X86_XCPT_GP;
3243	break;
3244	/* 128-bit invalid encodings: */
3245	case 8:
3246	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3247	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, 0 /L/, 1 /~R/); /* Bad V value */
3248	off = Bs3Cg1InsertOpcodes(pThis, off);
3249	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3250	pThis->fInvalidEncoding = true;
3251	break;
3252	case 9:
3253	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3254	off = Bs3Cg1InsertOpcodes(pThis, off);
3255	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3256	pThis->fInvalidEncoding = true;
3257	iEncoding = 20-1;
3258	break;
3259
3260	default:
3261	return 0;
3262	}
3263
3264	pThis->cbCurInstr = off;
3265	return iEncoding + 1;
3266	}
3267
3268
3269	/**
3270	* Wip = VEX.W ignored.
3271	*/
3272	static unsigned BS3_NEAR_CODE
3273	Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding)
3274	{
3275	unsigned off;
3276
3277	switch (iEncoding)
3278	{
3279	case 20: /* switch to 256-bit */
3280	pThis->aOperands[pThis->iRmOp ].cbOp = 32;
3281	pThis->aOperands[pThis->iRmOp ].idxFieldBase = BS3CG1DST_YMM0;
3282	pThis->aOperands[pThis->iRegOp].cbOp = 32;
3283	pThis->aOperands[pThis->iRegOp].idxFieldBase = BS3CG1DST_YMM0;
3284	RT_FALL_THRU();
3285	case 0:
3286	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3287	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/);
3288	off = Bs3Cg1InsertOpcodes(pThis, off);
3289	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3290	break;
3291
3292	case 1:
3293	case 21:
3294	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3295	off = Bs3Cg1InsertOpcodes(pThis, off);
3296	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3297	break;
3298	case 2:
3299	case 22:
3300	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W - ignored/);
3301	off = Bs3Cg1InsertOpcodes(pThis, off);
3302	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 5, 4);
3303	break;
3304	case 3:
3305	case 23:
3306	pThis->aOperands[pThis->iRmOp].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationMem;
3307	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/);
3308	off = Bs3Cg1InsertOpcodes(pThis, off);
3309	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 2 /iReg/);
3310	break;
3311	case 4:
3312	case 24:
3313	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3314	off = Bs3Cg1InsertOpcodes(pThis, off);
3315	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /iReg/);
3316	break;
3317	case 5:
3318	case 25:
3319	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W - ignored /);
3320	off = Bs3Cg1InsertOpcodes(pThis, off);
3321	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, off, 3 /iReg/);
3322	break;
3323	case 6:
3324	case 26:
3325	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/);
3326	off = Bs3Cg1InsertOpcodes(pThis, off);
3327	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /iReg/, 1 /cbMisalign/);
3328	if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3329	pThis->bAlignmentXcpt = X86_XCPT_GP;
3330	break;
3331	case 7:
3332	case 27:
3333	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3334	off = Bs3Cg1InsertOpcodes(pThis, off);
3335	off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaultsMisaligned(pThis, off, 3 /iReg/, 1 /cbMisalign/);
3336	if (!Bs3Cg1XcptTypeIsVexUnaligned(pThis->enmXcptType))
3337	pThis->bAlignmentXcpt = X86_XCPT_GP;
3338	break;
3339	/* invalid encodings: */
3340	case 8:
3341	case 28:
3342	pThis->aOperands[pThis->iRmOp ].enmLocation = pThis->aOperands[pThis->iRmOp].enmLocationReg;
3343	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xe /~V/, iEncoding >= 20 /L/, 1 /~R/); /* Bad V value */
3344	off = Bs3Cg1InsertOpcodes(pThis, off);
3345	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1, 0);
3346	pThis->fInvalidEncoding = true;
3347	break;
3348	case 9:
3349	case 29:
3350	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0 /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3351	off = Bs3Cg1InsertOpcodes(pThis, off);
3352	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3353	pThis->fInvalidEncoding = true;
3354	break;
3355
3356	case 10:
3357	case 30:
3358	pThis->abCurInstr[0] = P_RN;
3359	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3360	off = Bs3Cg1InsertOpcodes(pThis, off);
3361	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3362	pThis->fInvalidEncoding = true;
3363	break;
3364	case 11:
3365	case 31:
3366	pThis->abCurInstr[0] = P_RZ;
3367	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3368	off = Bs3Cg1InsertOpcodes(pThis, off);
3369	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3370	pThis->fInvalidEncoding = true;
3371	break;
3372	case 12:
3373	case 32:
3374	pThis->abCurInstr[0] = P_OZ;
3375	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3376	off = Bs3Cg1InsertOpcodes(pThis, off);
3377	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3378	pThis->fInvalidEncoding = true;
3379	break;
3380	case 13:
3381	case 33:
3382	pThis->abCurInstr[0] = P_LK;
3383	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3384	off = Bs3Cg1InsertOpcodes(pThis, off);
3385	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 4, 5);
3386	pThis->fInvalidEncoding = true;
3387	iEncoding += !BS3CG1_IS_64BIT_TARGET(pThis) ? 2 + 4 : 0;
3388	break;
3389
3390	#if ARCH_BITS == 64
3391	/* 64-bit mode registers */
3392	case 14:
3393	case 34:
3394	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 0 /~R/);
3395	off = Bs3Cg1InsertOpcodes(pThis, off);
3396	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 3+8, 4);
3397	break;
3398	case 15:
3399	case 35:
3400	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, iEncoding >= 20 /L/, 0 /~R/, 1 /~X/, 0 /~B/, 0 /W/);
3401	off = Bs3Cg1InsertOpcodes(pThis, off);
3402	off = Bs3Cg1InsertModRmWithRegFields(pThis, off, 1+8, 4+8);
3403	iEncoding += 4;
3404	break;
3405	#endif
3406	default:
3407	return 0;
3408	}
3409
3410	pThis->cbCurInstr = off;
3411	return iEncoding + 1;
3412	}
3413
3414
3415	//static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
3416	//{
3417	// unsigned off;
3418	// if (iEncoding == 0)
3419	// off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3420	// else if (iEncoding == 0)
3421	// off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3422	// else
3423	// return 0;
3424	// pThis->cbCurInstr = off;
3425	// return iEncoding + 1;
3426	//}
3427
3428
3429	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
3430	{
3431	unsigned off;
3432	if (iEncoding < 8)
3433	{
3434	if (iEncoding & 1)
3435	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3436	else
3437	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3438	off = Bs3Cg1InsertOpcodes(pThis, off);
3439	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
3440	}
3441	else if (iEncoding < 16)
3442	{
3443	if (iEncoding & 1)
3444	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/);
3445	else
3446	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3447	off = Bs3Cg1InsertOpcodes(pThis, off);
3448	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding & 7, 1);
3449	}
3450	else if (iEncoding < 24)
3451	{
3452	if (iEncoding & 1)
3453	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
3454	else
3455	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
3456	off = Bs3Cg1InsertOpcodes(pThis, off);
3457	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
3458	}
3459	else if (iEncoding < 32)
3460	{
3461	if (iEncoding & 1)
3462	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, (iEncoding & 3) != 0 /L/, 1 /~R/);
3463	else
3464	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, (iEncoding & 2) != 0 /L/, 1 /~R/, 1 /~X/,
3465	1 /~B/, (iEncoding & 4) != 0 /W/);
3466	off = Bs3Cg1InsertOpcodes(pThis, off);
3467	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding & 7);
3468	}
3469	else
3470	return 0;
3471	pThis->cbCurInstr = off;
3472
3473	return iEncoding + 1;
3474	}
3475
3476
3477	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
3478	{
3479	unsigned off;
3480	if (iEncoding < 8)
3481	{
3482	unsigned iMod = iEncoding % 3;
3483	if (iEncoding & 1)
3484	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, (iEncoding & 2) != 0 /L/, 1 /~R/);
3485	else
3486	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, (iEncoding & 2) != 0 /L/, 1 /~R/,
3487	1 /~X/, 1 /~B/, (iEncoding & 4) != 0 /W/);
3488	off = Bs3Cg1InsertOpcodes(pThis, off);
3489	pThis->abCurInstr[off++] = X86_MODRM_MAKE(iMod, 0, 1);
3490	if (iMod >= 1)
3491	pThis->abCurInstr[off++] = 0x7f;
3492	if (iMod == 2)
3493	{
3494	pThis->abCurInstr[off++] = 0x5f;
3495	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
3496	{
3497	pThis->abCurInstr[off++] = 0x3f;
3498	pThis->abCurInstr[off++] = 0x1f;
3499	}
3500	}
3501	}
3502	else
3503	return 0;
3504	pThis->cbCurInstr = off;
3505	return iEncoding + 1;
3506	}
3507
3508
3509	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM(PBS3CG1STATE pThis, unsigned iEncoding)
3510	{
3511	const unsigned cFirstEncodings = 32;
3512	if (iEncoding < cFirstEncodings)
3513	{
3514	unsigned iRet = Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3(pThis, iEncoding);
3515	BS3_ASSERT(iRet > iEncoding);
3516	return iRet;
3517	}
3518	return Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3(pThis, iEncoding - cFirstEncodings) + cFirstEncodings;
3519	}
3520
3521	#endif /* BS3CG1_WITH_VEX */
3522
3523
3524	/**
3525	* Encodes the next instruction.
3526	*
3527	* @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
3528	* that there are no more encodings to test.
3529	* @param pThis The state.
3530	* @param iEncoding The encoding to produce. Meaning is specific to
3531	* each BS3CG1ENC_XXX value and should be considered
3532	* internal.
3533	*/
3534	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
3535	{
3536	pThis->bAlignmentXcpt = UINT8_MAX;
3537	pThis->uVexL = UINT8_MAX;
3538	if (pThis->pfnEncoder)
3539	return pThis->pfnEncoder(pThis, iEncoding);
3540
3541	Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
3542	return iEncoding;
3543	}
3544
3545
3546	/**
3547	* Prepares doing instruction encodings.
3548	*
3549	* This is in part specific to how the instruction is encoded, but generally it
3550	* sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
3551	* is called from within the loop.
3552	*
3553	* @returns Success indicator (true/false).
3554	* @param pThis The state.
3555	*/
3556	#define Bs3Cg1EncodePrep BS3_CMN_NM(Bs3Cg1EncodePrep)
3557	bool BS3_NEAR_CODE Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
3558	{
3559	unsigned i = 4;
3560	while (i-- > 0)
3561	pThis->aSavedSegRegs[i].ds = pThis->aInitialCtxs[i].ds;
3562
3563	i = RT_ELEMENTS(pThis->aOperands);
3564	while (i-- > 0)
3565	{
3566	pThis->aOperands[i].enmLocationReg = BS3CG1OPLOC_INVALID;
3567	pThis->aOperands[i].enmLocationMem = BS3CG1OPLOC_INVALID;
3568	pThis->aOperands[i].idxFieldBase = BS3CG1DST_INVALID;
3569	}
3570
3571	pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
3572	pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
3573	pThis->fSameRingNotOkay = false;
3574	pThis->cbOperand = 0;
3575	pThis->pfnEncoder = NULL;
3576
3577	switch (pThis->enmEncoding)
3578	{
3579	case BS3CG1ENC_MODRM_Eb_Gb:
3580	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa;
3581	pThis->iRmOp = 0;
3582	pThis->iRegOp = 1;
3583	pThis->aOperands[0].cbOp = 1;
3584	pThis->aOperands[1].cbOp = 1;
3585	pThis->aOperands[0].idxFieldBase = BS3CG1DST_AL;
3586	pThis->aOperands[1].idxFieldBase = BS3CG1DST_AL;
3587	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3588	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_RW;
3589	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3590	break;
3591
3592	case BS3CG1ENC_MODRM_Ev_Gv:
3593	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv;
3594	pThis->iRmOp = 0;
3595	pThis->iRegOp = 1;
3596	pThis->cbOperand = 2;
3597	pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3598	pThis->aOperands[1].idxFieldBase = BS3CG1DST_OZ_RAX;
3599	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3600	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_RW;
3601	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3602	break;
3603
3604	case BS3CG1ENC_MODRM_Ed_WO_Pd_WZ:
3605	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ;
3606	pThis->iRmOp = 0;
3607	pThis->iRegOp = 1;
3608	pThis->aOperands[0].cbOp = 4;
3609	pThis->aOperands[1].cbOp = 4;
3610	pThis->aOperands[0].idxFieldBase = BS3CG1DST_EAX;
3611	pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3612	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3613	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3614	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3615	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3616	break;
3617
3618	case BS3CG1ENC_MODRM_Eq_WO_Pq_WNZ:
3619	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ;
3620	pThis->iRmOp = 0;
3621	pThis->iRegOp = 1;
3622	pThis->aOperands[0].cbOp = 8;
3623	pThis->aOperands[1].cbOp = 8;
3624	pThis->aOperands[0].idxFieldBase = BS3CG1DST_RAX;
3625	pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3626	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3627	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3628	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3629	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3630	break;
3631
3632	case BS3CG1ENC_MODRM_Ed_WO_Vd_WZ:
3633	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ;
3634	pThis->iRmOp = 0;
3635	pThis->iRegOp = 1;
3636	pThis->aOperands[0].cbOp = 4;
3637	pThis->aOperands[1].cbOp = 4;
3638	pThis->aOperands[0].idxFieldBase = BS3CG1DST_EAX;
3639	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3640	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3641	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3642	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3643	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3644	break;
3645
3646	case BS3CG1ENC_MODRM_Eq_WO_Vq_WNZ:
3647	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ;
3648	pThis->iRmOp = 0;
3649	pThis->iRegOp = 1;
3650	pThis->aOperands[0].cbOp = 8;
3651	pThis->aOperands[1].cbOp = 8;
3652	pThis->aOperands[0].idxFieldBase = BS3CG1DST_RAX;
3653	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3654	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3655	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3656	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3657	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3658	break;
3659
3660	case BS3CG1ENC_MODRM_Gb_Eb:
3661	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Eb_Gb_OR_ViceVersa;
3662	pThis->iRegOp = 0;
3663	pThis->iRmOp = 1;
3664	pThis->aOperands[0].cbOp = 1;
3665	pThis->aOperands[1].cbOp = 1;
3666	pThis->aOperands[0].idxFieldBase = BS3CG1DST_AL;
3667	pThis->aOperands[1].idxFieldBase = BS3CG1DST_AL;
3668	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3669	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3670	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3671	break;
3672
3673	case BS3CG1ENC_MODRM_Gv_Ev:
3674	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_Ev__OR__MODRM_Ev_Gv;
3675	pThis->iRegOp = 0;
3676	pThis->iRmOp = 1;
3677	pThis->cbOperand = 2;
3678	pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3679	pThis->aOperands[1].idxFieldBase = BS3CG1DST_OZ_RAX;
3680	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3681	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3682	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3683	break;
3684
3685	case BS3CG1ENC_MODRM_Gv_RO_Ma: /* bound instr */
3686	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Gv_RO_Ma;
3687	pThis->iRmOp = 1;
3688	pThis->iRegOp = 0;
3689	pThis->cbOperand = 2;
3690	pThis->aOperands[0].cbOp = 2;
3691	pThis->aOperands[1].cbOp = 4;
3692	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3693	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3694	pThis->aOperands[0].idxFieldBase = BS3CG1DST_OZ_RAX;
3695	break;
3696
3697	case BS3CG1ENC_MODRM_Wss_WO_Vss:
3698	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3699	pThis->iRmOp = 0;
3700	pThis->iRegOp = 1;
3701	pThis->aOperands[0].cbOp = 4;
3702	pThis->aOperands[1].cbOp = 4;
3703	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0;
3704	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_DW0;
3705	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3706	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3707	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3708	break;
3709
3710	case BS3CG1ENC_MODRM_Wsd_WO_Vsd:
3711	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3712	pThis->iRmOp = 0;
3713	pThis->iRegOp = 1;
3714	pThis->aOperands[0].cbOp = 8;
3715	pThis->aOperands[1].cbOp = 8;
3716	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3717	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3718	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3719	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3720	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3721	break;
3722
3723	case BS3CG1ENC_MODRM_WqZxReg_WO_Vq:
3724	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3725	pThis->iRmOp = 0;
3726	pThis->iRegOp = 1;
3727	pThis->aOperands[0].cbOp = 8;
3728	pThis->aOperands[1].cbOp = 8;
3729	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3730	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3731	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3732	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3733	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3734	break;
3735
3736	case BS3CG1ENC_MODRM_Wps_WO_Vps:
3737	case BS3CG1ENC_MODRM_Wpd_WO_Vpd:
3738	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3739	pThis->iRmOp = 0;
3740	pThis->iRegOp = 1;
3741	pThis->aOperands[0].cbOp = 16;
3742	pThis->aOperands[1].cbOp = 16;
3743	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3744	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3745	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
3746	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3747	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3748	break;
3749
3750	case BS3CG1ENC_MODRM_Vdq_WO_Mdq:
3751	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3752	pThis->iRegOp = 0;
3753	pThis->iRmOp = 1;
3754	pThis->aOperands[0].cbOp = 16;
3755	pThis->aOperands[1].cbOp = 16;
3756	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3757	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3758	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3759	break;
3760
3761	case BS3CG1ENC_MODRM_Vdq_WO_Wdq:
3762	case BS3CG1ENC_MODRM_Vpd_WO_Wpd:
3763	case BS3CG1ENC_MODRM_Vps_WO_Wps:
3764	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3765	pThis->iRegOp = 0;
3766	pThis->iRmOp = 1;
3767	pThis->aOperands[0].cbOp = 16;
3768	pThis->aOperands[1].cbOp = 16;
3769	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
3770	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3771	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3772	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3773	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3774	break;
3775
3776	case BS3CG1ENC_MODRM_Pq_WO_Qq:
3777	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Qq;
3778	pThis->iRegOp = 0;
3779	pThis->iRmOp = 1;
3780	pThis->aOperands[0].cbOp = 8;
3781	pThis->aOperands[1].cbOp = 8;
3782	pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3783	pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3784	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3785	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3786	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3787	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3788	break;
3789
3790	case BS3CG1ENC_MODRM_Pq_WO_Uq:
3791	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Uq;
3792	pThis->iRegOp = 0;
3793	pThis->iRmOp = 1;
3794	pThis->aOperands[0].cbOp = 8;
3795	pThis->aOperands[1].cbOp = 8;
3796	pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3797	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3798	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3799	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; /* reg only */
3800	break;
3801
3802	case BS3CG1ENC_MODRM_PdZx_WO_Ed_WZ:
3803	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_PdZx_WO_Ed_WZ;
3804	pThis->iRegOp = 0;
3805	pThis->iRmOp = 1;
3806	pThis->aOperands[0].cbOp = 4;
3807	pThis->aOperands[1].cbOp = 4;
3808	pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0_LO_ZX;
3809	pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
3810	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3811	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3812	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3813	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3814	break;
3815
3816	case BS3CG1ENC_MODRM_Pq_WO_Eq_WNZ:
3817	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Pq_WO_Eq_WNZ;
3818	pThis->iRegOp = 0;
3819	pThis->iRmOp = 1;
3820	pThis->aOperands[0].cbOp = 8;
3821	pThis->aOperands[1].cbOp = 8;
3822	pThis->aOperands[0].idxFieldBase = BS3CG1DST_MM0;
3823	pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
3824	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3825	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3826	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3827	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3828	break;
3829
3830	case BS3CG1ENC_MODRM_VdZx_WO_Ed_WZ:
3831	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vd_WO_Ed_WZ;
3832	pThis->iRegOp = 0;
3833	pThis->iRmOp = 1;
3834	pThis->aOperands[0].cbOp = 4;
3835	pThis->aOperands[1].cbOp = 4;
3836	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
3837	pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
3838	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3839	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3840	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3841	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3842	break;
3843
3844	case BS3CG1ENC_MODRM_VqZx_WO_Eq_WNZ:
3845	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vq_WO_Eq_WNZ;
3846	pThis->iRegOp = 0;
3847	pThis->iRmOp = 1;
3848	pThis->aOperands[0].cbOp = 8;
3849	pThis->aOperands[1].cbOp = 8;
3850	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3851	pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
3852	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3853	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3854	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3855	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3856	break;
3857
3858	case BS3CG1ENC_MODRM_Vq_WO_UqHi:
3859	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa;
3860	pThis->iRegOp = 0;
3861	pThis->iRmOp = 1;
3862	pThis->aOperands[0].cbOp = 8;
3863	pThis->aOperands[1].cbOp = 8;
3864	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3865	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
3866	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3867	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3868	break;
3869
3870	case BS3CG1ENC_MODRM_VqHi_WO_Uq:
3871	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Usomething_OR_ViceVersa;
3872	pThis->iRegOp = 0;
3873	pThis->iRmOp = 1;
3874	pThis->aOperands[0].cbOp = 8;
3875	pThis->aOperands[1].cbOp = 8;
3876	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_HI;
3877	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3878	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3879	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3880	break;
3881
3882	case BS3CG1ENC_MODRM_VqHi_WO_Mq:
3883	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3884	pThis->iRegOp = 0;
3885	pThis->iRmOp = 1;
3886	pThis->aOperands[0].cbOp = 8;
3887	pThis->aOperands[1].cbOp = 8;
3888	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_HI;
3889	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3890	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3891	break;
3892
3893	case BS3CG1ENC_MODRM_Vq_WO_Mq:
3894	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3895	pThis->iRegOp = 0;
3896	pThis->iRmOp = 1;
3897	pThis->aOperands[0].cbOp = 8;
3898	pThis->aOperands[1].cbOp = 8;
3899	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
3900	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3901	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
3902	break;
3903
3904	case BS3CG1ENC_MODRM_VssZx_WO_Wss:
3905	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3906	pThis->iRegOp = 0;
3907	pThis->iRmOp = 1;
3908	pThis->aOperands[0].cbOp = 4;
3909	pThis->aOperands[1].cbOp = 4;
3910	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3911	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3912	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3913	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
3914	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3915	break;
3916
3917	case BS3CG1ENC_MODRM_VqZx_WO_Nq:
3918	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Nsomething;
3919	pThis->iRegOp = 0;
3920	pThis->iRmOp = 1;
3921	pThis->aOperands[0].cbOp = 8;
3922	pThis->aOperands[1].cbOp = 8;
3923	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3924	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3925	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3926	pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3927	break;
3928
3929	case BS3CG1ENC_MODRM_VsdZx_WO_Wsd:
3930	case BS3CG1ENC_MODRM_VqZx_WO_Wq:
3931	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Vsomething_Wsomething_OR_ViceVersa;
3932	pThis->iRegOp = 0;
3933	pThis->iRmOp = 1;
3934	pThis->aOperands[0].cbOp = 8;
3935	pThis->aOperands[1].cbOp = 8;
3936	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
3937	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3938	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
3939	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
3940	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
3941	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
3942	break;
3943
3944	case BS3CG1ENC_MODRM_Mb_RO:
3945	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3946	pThis->iRmOp = 0;
3947	pThis->aOperands[0].cbOp = 1;
3948	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
3949	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM;
3950	break;
3951
3952	case BS3CG1ENC_MODRM_Md_RO:
3953	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3954	pThis->iRmOp = 0;
3955	pThis->aOperands[0].cbOp = 4;
3956	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
3957	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM;
3958	break;
3959
3960	case BS3CG1ENC_MODRM_Md_WO:
3961	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething;
3962	pThis->iRmOp = 0;
3963	pThis->aOperands[0].cbOp = 4;
3964	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3965	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3966	break;
3967
3968	case BS3CG1ENC_MODRM_Mdq_WO_Vdq:
3969	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3970	pThis->iRmOp = 0;
3971	pThis->iRegOp = 1;
3972	pThis->aOperands[0].cbOp = 16;
3973	pThis->aOperands[1].cbOp = 16;
3974	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3975	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3976	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
3977	break;
3978
3979	case BS3CG1ENC_MODRM_Mq_WO_Pq:
3980	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Psomething;
3981	pThis->iRmOp = 0;
3982	pThis->iRegOp = 1;
3983	pThis->aOperands[0].cbOp = 8;
3984	pThis->aOperands[1].cbOp = 8;
3985	pThis->aOperands[1].idxFieldBase = BS3CG1DST_MM0;
3986	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3987	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
3988	break;
3989
3990	case BS3CG1ENC_MODRM_Mq_WO_Vq:
3991	case BS3CG1ENC_MODRM_Mq_WO_VqHi:
3992	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
3993	pThis->iRmOp = 0;
3994	pThis->iRegOp = 1;
3995	pThis->aOperands[0].cbOp = 8;
3996	pThis->aOperands[1].cbOp = 8;
3997	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
3998	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
3999	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4000	pThis->aOperands[1].idxFieldBase = pThis->enmEncoding == BS3CG1ENC_MODRM_Mq_WO_Vq
4001	? BS3CG1DST_XMM0_LO : BS3CG1DST_XMM0_HI;
4002	break;
4003
4004	case BS3CG1ENC_MODRM_Mps_WO_Vps:
4005	case BS3CG1ENC_MODRM_Mpd_WO_Vpd:
4006	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_Msomething_Vsomething_OR_ViceVersa;
4007	pThis->iRmOp = 0;
4008	pThis->iRegOp = 1;
4009	pThis->aOperands[0].cbOp = 16;
4010	pThis->aOperands[1].cbOp = 16;
4011	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4012	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4013	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4014	break;
4015
4016	case BS3CG1ENC_FIXED:
4017	pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED;
4018	break;
4019
4020	case BS3CG1ENC_FIXED_AL_Ib:
4021	pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED_AL_Ib;
4022	pThis->aOperands[0].cbOp = 1;
4023	pThis->aOperands[1].cbOp = 1;
4024	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4025	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
4026	pThis->aOperands[0].idxField = BS3CG1DST_AL;
4027	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
4028	break;
4029
4030	case BS3CG1ENC_FIXED_rAX_Iz:
4031	pThis->pfnEncoder = Bs3Cg1EncodeNext_FIXED_rAX_Iz;
4032	pThis->aOperands[0].cbOp = 2;
4033	pThis->aOperands[1].cbOp = 2;
4034	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4035	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
4036	pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
4037	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
4038	break;
4039
4040	/* Unused or invalid instructions mostly. */
4041	case BS3CG1ENC_MODRM_MOD_EQ_3:
4042	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_EQ_3;
4043	break;
4044	case BS3CG1ENC_MODRM_MOD_NE_3:
4045	pThis->pfnEncoder = Bs3Cg1EncodeNext_MODRM_MOD_NE_3;
4046	break;
4047
4048	#ifdef BS3CG1_WITH_VEX
4049
4050	case BS3CG1ENC_VEX_MODRM_Vd_WO_Ed_WZ:
4051	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vd_WO_Ed_WZ;
4052	pThis->iRegOp = 0;
4053	pThis->iRmOp = 1;
4054	pThis->aOperands[0].cbOp = 4;
4055	pThis->aOperands[1].cbOp = 4;
4056	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
4057	pThis->aOperands[1].idxFieldBase = BS3CG1DST_EAX;
4058	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4059	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4060	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4061	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4062	break;
4063
4064	case BS3CG1ENC_VEX_MODRM_Vq_WO_Eq_WNZ:
4065	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vq_WO_Eq_WNZ;
4066	pThis->iRegOp = 0;
4067	pThis->iRmOp = 1;
4068	pThis->aOperands[0].cbOp = 8;
4069	pThis->aOperands[1].cbOp = 8;
4070	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
4071	pThis->aOperands[1].idxFieldBase = BS3CG1DST_RAX;
4072	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4073	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4074	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4075	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4076	break;
4077
4078	case BS3CG1ENC_VEX_MODRM_Vps_WO_Wps:
4079	case BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd:
4080	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4081	pThis->iRegOp = 0;
4082	pThis->iRmOp = 1;
4083	pThis->aOperands[0].cbOp = 16;
4084	pThis->aOperands[1].cbOp = 16;
4085	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4086	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4087	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4088	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4089	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4090	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4091	break;
4092
4093	case BS3CG1ENC_VEX_MODRM_VssZx_WO_Md:
4094	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4095	pThis->iRmOp = 1;
4096	pThis->iRegOp = 0;
4097	pThis->aOperands[0].cbOp = 4;
4098	pThis->aOperands[1].cbOp = 4;
4099	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4100	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4101	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_DW0;
4102	pThis->aOperands[1].idxFieldBase = BS3CG1DST_INVALID;
4103	break;
4104
4105	case BS3CG1ENC_VEX_MODRM_Vss_WO_HssHi_Uss:
4106	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4107	pThis->iRegOp = 0;
4108	pThis->iRmOp = 2;
4109	pThis->aOperands[0].cbOp = 16;
4110	pThis->aOperands[1].cbOp = 12;
4111	pThis->aOperands[2].cbOp = 4;
4112	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4113	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4114	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4115	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4116	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI96;
4117	pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
4118	break;
4119
4120	case BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq:
4121	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4122	pThis->iRmOp = 1;
4123	pThis->iRegOp = 0;
4124	pThis->aOperands[0].cbOp = 8;
4125	pThis->aOperands[1].cbOp = 8;
4126	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4127	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4128	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
4129	pThis->aOperands[1].idxFieldBase = BS3CG1DST_INVALID;
4130	break;
4131
4132	case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L0:
4133	BS3_ASSERT(!(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO));
4134	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L0_OR_ViceVersa;
4135	pThis->iRegOp = 0;
4136	pThis->iRmOp = 1;
4137	pThis->aOperands[0].cbOp = 16;
4138	pThis->aOperands[1].cbOp = 16;
4139	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4140	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4141	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4142	break;
4143
4144	case BS3CG1ENC_VEX_MODRM_Vx_WO_Mx_L1:
4145	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_L1_OR_ViceVersa;
4146	pThis->iRegOp = 0;
4147	pThis->iRmOp = 1;
4148	pThis->aOperands[0].cbOp = 32;
4149	pThis->aOperands[1].cbOp = 32;
4150	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4151	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
4152	pThis->aOperands[0].idxFieldBase = BS3CG1DST_YMM0;
4153	break;
4154
4155	case BS3CG1ENC_VEX_MODRM_Vsd_WO_HsdHi_Usd:
4156	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4157	pThis->iRegOp = 0;
4158	pThis->iRmOp = 2;
4159	pThis->aOperands[0].cbOp = 16;
4160	pThis->aOperands[1].cbOp = 8;
4161	pThis->aOperands[2].cbOp = 8;
4162	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4163	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4164	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4165	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4166	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4167	pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
4168	break;
4169
4170	case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_UqHi:
4171	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa;
4172	pThis->iRegOp = 0;
4173	pThis->iRmOp = 2;
4174	pThis->aOperands[0].cbOp = 16;
4175	pThis->aOperands[1].cbOp = 8;
4176	pThis->aOperands[2].cbOp = 8;
4177	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4178	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4179	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4180	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4181	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4182	pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_HI;
4183	break;
4184
4185	case BS3CG1ENC_VEX_MODRM_Vq_WO_HqHi_Mq:
4186	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa;
4187	pThis->iRegOp = 0;
4188	pThis->iRmOp = 2;
4189	pThis->aOperands[0].cbOp = 16;
4190	pThis->aOperands[1].cbOp = 8;
4191	pThis->aOperands[2].cbOp = 8;
4192	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4193	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4194	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_MEM;
4195	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4196	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4197	pThis->aOperands[2].idxFieldBase = BS3CG1DST_INVALID;
4198	break;
4199
4200	case BS3CG1ENC_VEX_MODRM_Vq_WO_Wq:
4201	BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO);
4202	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa;
4203	pThis->iRegOp = 0;
4204	pThis->iRmOp = 1;
4205	pThis->aOperands[0].cbOp = 8;
4206	pThis->aOperands[1].cbOp = 8;
4207	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4208	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4209	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4210	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4211	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
4212	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
4213	break;
4214
4215	case BS3CG1ENC_VEX_MODRM_Vx_WO_Wx:
4216	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4217	pThis->iRegOp = 0;
4218	pThis->iRmOp = 1;
4219	pThis->aOperands[0].cbOp = 16;
4220	pThis->aOperands[1].cbOp = 16;
4221	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4222	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4223	pThis->aOperands[1].enmLocationReg = BS3CG1OPLOC_CTX;
4224	pThis->aOperands[1].enmLocationMem = BS3CG1OPLOC_MEM;
4225	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4226	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4227	break;
4228
4229	case BS3CG1ENC_VEX_MODRM_Ed_WO_Vd_WZ:
4230	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vd_WO_Ed_WZ;
4231	pThis->iRmOp = 0;
4232	pThis->iRegOp = 1;
4233	pThis->aOperands[0].cbOp = 4;
4234	pThis->aOperands[1].cbOp = 4;
4235	pThis->aOperands[0].idxFieldBase = BS3CG1DST_EAX;
4236	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_DW0_ZX;
4237	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4238	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
4239	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4240	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4241	break;
4242
4243	case BS3CG1ENC_VEX_MODRM_Eq_WO_Vq_WNZ:
4244	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Vq_WO_Eq_WNZ;
4245	pThis->iRmOp = 0;
4246	pThis->iRegOp = 1;
4247	pThis->aOperands[0].cbOp = 8;
4248	pThis->aOperands[1].cbOp = 8;
4249	pThis->aOperands[0].idxFieldBase = BS3CG1DST_RAX;
4250	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO_ZX;
4251	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
4252	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX;
4253	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4254	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4255	break;
4256
4257	case BS3CG1ENC_VEX_MODRM_Md_WO:
4258	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_Md_WO;
4259	pThis->iRmOp = 0;
4260	pThis->aOperands[0].cbOp = 4;
4261	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4262	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4263	break;
4264
4265	case BS3CG1ENC_VEX_MODRM_Md_WO_Vss:
4266	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4267	pThis->iRmOp = 0;
4268	pThis->iRegOp = 1;
4269	pThis->aOperands[0].cbOp = 4;
4270	pThis->aOperands[1].cbOp = 4;
4271	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4272	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4273	pThis->aOperands[0].idxFieldBase = BS3CG1DST_INVALID;
4274	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_DW0;
4275	break;
4276
4277	case BS3CG1ENC_VEX_MODRM_Mq_WO_Vq:
4278	BS3_ASSERT(pThis->fFlags & (BS3CG1INSTR_F_VEX_L_ZERO \| BS3CG1INSTR_F_VEX_L_IGNORED));
4279	pThis->pfnEncoder = pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO
4280	? Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lmbz_OR_ViceVersa
4281	: Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4282	pThis->iRmOp = 0;
4283	pThis->iRegOp = 1;
4284	pThis->aOperands[0].cbOp = 8;
4285	pThis->aOperands[1].cbOp = 8;
4286	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4287	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4288	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
4289	break;
4290
4291	case BS3CG1ENC_VEX_MODRM_Mq_WO_Vsd:
4292	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa;
4293	pThis->iRmOp = 0;
4294	pThis->iRegOp = 1;
4295	pThis->aOperands[0].cbOp = 8;
4296	pThis->aOperands[1].cbOp = 8;
4297	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4298	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4299	pThis->aOperands[0].idxFieldBase = BS3CG1DST_INVALID;
4300	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
4301	break;
4302
4303	case BS3CG1ENC_VEX_MODRM_Mps_WO_Vps:
4304	case BS3CG1ENC_VEX_MODRM_Mpd_WO_Vpd:
4305	case BS3CG1ENC_VEX_MODRM_Mx_WO_Vx:
4306	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_OR_ViceVersa;
4307	pThis->iRmOp = 0;
4308	pThis->iRegOp = 1;
4309	pThis->aOperands[0].cbOp = 16;
4310	pThis->aOperands[1].cbOp = 16;
4311	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_WO;
4312	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4313	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4314	break;
4315
4316	case BS3CG1ENC_VEX_MODRM_Uss_WO_HssHi_Vss:
4317	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4318	pThis->iRegOp = 2;
4319	pThis->iRmOp = 0;
4320	pThis->aOperands[0].cbOp = 16;
4321	pThis->aOperands[1].cbOp = 96;
4322	pThis->aOperands[2].cbOp = 4;
4323	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4324	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4325	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4326	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4327	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI96;
4328	pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_DW0;
4329	break;
4330
4331	case BS3CG1ENC_VEX_MODRM_Usd_WO_HsdHi_Vsd:
4332	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Usomething_Lip_Wip_OR_ViceVersa;
4333	pThis->iRegOp = 2;
4334	pThis->iRmOp = 0;
4335	pThis->aOperands[0].cbOp = 16;
4336	pThis->aOperands[1].cbOp = 8;
4337	pThis->aOperands[2].cbOp = 8;
4338	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4339	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4340	pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX;
4341	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4342	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_HI;
4343	pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_LO;
4344	break;
4345
4346	case BS3CG1ENC_VEX_MODRM_Wps_WO_Vps:
4347	case BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd:
4348	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4349	pThis->iRmOp = 0;
4350	pThis->iRegOp = 1;
4351	pThis->aOperands[0].cbOp = 16;
4352	pThis->aOperands[1].cbOp = 16;
4353	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4354	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX_ZX_VLMAX;
4355	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4356	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4357	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4358	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4359	break;
4360
4361	case BS3CG1ENC_VEX_MODRM_Wq_WO_Vq:
4362	BS3_ASSERT(pThis->fFlags & BS3CG1INSTR_F_VEX_L_ZERO);
4363	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_Lmbz_OR_ViceVersa;
4364	pThis->iRegOp = 1;
4365	pThis->iRmOp = 0;
4366	pThis->aOperands[0].cbOp = 8;
4367	pThis->aOperands[1].cbOp = 8;
4368	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4369	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX_ZX_VLMAX;
4370	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4371	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4372	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0_LO;
4373	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0_LO;
4374	break;
4375
4376	case BS3CG1ENC_VEX_MODRM_Wx_WO_Vx:
4377	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_WsomethingWO_Vsomething_Wip_OR_ViceVersa;
4378	pThis->iRmOp = 0;
4379	pThis->iRegOp = 1;
4380	pThis->aOperands[0].cbOp = 16;
4381	pThis->aOperands[1].cbOp = 16;
4382	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX;
4383	pThis->aOperands[0].enmLocationReg = BS3CG1OPLOC_CTX_ZX_VLMAX;
4384	pThis->aOperands[0].enmLocationMem = BS3CG1OPLOC_MEM_WO;
4385	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
4386	pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0;
4387	pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0;
4388	break;
4389
4390
4391	/* Unused or invalid instructions mostly. */
4392	//case BS3CG1ENC_VEX_FIXED:
4393	// pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_FIXED;
4394	// break;
4395	case BS3CG1ENC_VEX_MODRM_MOD_EQ_3:
4396	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_MOD_EQ_3;
4397	break;
4398	case BS3CG1ENC_VEX_MODRM_MOD_NE_3:
4399	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_MOD_NE_3;
4400	break;
4401	case BS3CG1ENC_VEX_MODRM:
4402	pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM;
4403	break;
4404
4405	#endif /* BS3CG1_WITH_VEX */
4406
4407	default:
4408	Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
4409	pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
4410	return false;
4411	}
4412	return true;
4413	}
4414
4415
4416	/**
4417	* Calculates the appropriate non-intel invalid instruction encoding.
4418	*
4419	* @returns the encoding to use instead.
4420	* @param enmEncoding The intel invalid instruction encoding.
4421	*/
4422	static BS3CG1ENC Bs3Cg1CalcNoneIntelInvalidEncoding(BS3CG1ENC enmEncoding)
4423	{
4424	switch (enmEncoding)
4425	{
4426	case BS3CG1ENC_MODRM_Gb_Eb:
4427	case BS3CG1ENC_MODRM_Gv_RO_Ma:
4428	case BS3CG1ENC_FIXED:
4429	return BS3CG1ENC_FIXED;
4430	default:
4431	Bs3TestFailedF("Bs3Cg1CalcNoneIntelInvalidEncoding: Unsupported encoding: %d\n", enmEncoding);
4432	return BS3CG1ENC_FIXED;
4433	}
4434	}
4435
4436
4437	/**
4438	* Sets cbOpDefault, cbOpOvrd66 and cbOpOvrdRexW.
4439	*
4440	* @param pThis The state.
4441	* @param bMode The mode (only code part is used).
4442	*/
4443	static void Bs3Cg1SetOpSizes(PBS3CG1STATE pThis, uint8_t bMode)
4444	{
4445	if (BS3_MODE_IS_16BIT_CODE(bMode))
4446	{
4447	pThis->cbOpDefault = 2;
4448	pThis->cbOpOvrd66 = 4;
4449	pThis->cbOpOvrdRexW = 0;
4450	}
4451	else if (BS3_MODE_IS_32BIT_CODE(bMode))
4452	{
4453	pThis->cbOpDefault = 4;
4454	pThis->cbOpOvrd66 = 2;
4455	pThis->cbOpOvrdRexW = 0;
4456	}
4457	else
4458	{
4459	pThis->cbOpDefault = 4;
4460	pThis->cbOpOvrd66 = 2;
4461	pThis->cbOpOvrdRexW = 8;
4462	}
4463	}
4464
4465
4466	/**
4467	* Sets up SSE and maybe AVX.
4468	*
4469	* @returns true (if successful, false if not and the SSE instructions ends up
4470	* being invalid).
4471	* @param pThis The state.
4472	*/
4473	static bool BS3_NEAR_CODE Bs3Cg3SetupSseAndAvx(PBS3CG1STATE pThis)
4474	{
4475	if (!pThis->fWorkExtCtx)
4476	{
4477	unsigned i;
4478	uint32_t cr0 = ASMGetCR0();
4479	uint32_t cr4 = ASMGetCR4();
4480
4481	cr0 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
4482	cr0 \|= X86_CR0_NE;
4483	ASMSetCR0(cr0);
4484	if (pThis->pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
4485	{
4486	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE;
4487	ASMSetCR4(cr4);
4488	ASMSetXcr0(pThis->pExtCtx->fXcr0Nominal);
4489	}
4490	else
4491	{
4492	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT;
4493	ASMSetCR4(cr4);
4494	}
4495
4496	for (i = 0; i < RT_ELEMENTS(pThis->aInitialCtxs); i++)
4497	{
4498	pThis->aInitialCtxs[i].cr0.u32 = cr0;
4499	pThis->aInitialCtxs[i].cr4.u32 = cr4;
4500	}
4501	pThis->fWorkExtCtx = true;
4502	}
4503
4504	return true;
4505	}
4506
4507
4508	/**
4509	* Next CPU configuration to test the current instruction in.
4510	*
4511	* This is for testing FPU, SSE and AVX instructions with the various lazy state
4512	* load and enable bits in different configurations to ensure we're getting the
4513	* right response.
4514	*
4515	* This also cleans up the CPU and test driver state.
4516	*
4517	* @returns true if we're to do another round, false if we're done.
4518	* @param pThis The state.
4519	* @param iCpuSetup The current CPU setup number.
4520	* @param pfInvalidInstr Where to indicate whether the setup causes an
4521	* invalid instruction or not. This is also used as
4522	* input to avoid unnecessary CPUID work.
4523	*/
4524	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupNext(PBS3CG1STATE pThis, unsigned iCpuSetup, bool BS3_FAR *pfInvalidInstr)
4525	{
4526	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
4527	&& BS3CG1_IS_64BIT_TARGET(pThis))
4528	return false;
4529
4530	switch (pThis->enmCpuTest)
4531	{
4532	case BS3CG1CPU_ANY:
4533	case BS3CG1CPU_GE_80186:
4534	case BS3CG1CPU_GE_80286:
4535	case BS3CG1CPU_GE_80386:
4536	case BS3CG1CPU_GE_80486:
4537	case BS3CG1CPU_GE_Pentium:
4538	case BS3CG1CPU_CLFSH:
4539	case BS3CG1CPU_CLFLUSHOPT:
4540	return false;
4541
4542	case BS3CG1CPU_MMX:
4543	return false;
4544
4545	case BS3CG1CPU_SSE:
4546	case BS3CG1CPU_SSE2:
4547	case BS3CG1CPU_SSE3:
4548	case BS3CG1CPU_SSE4_1:
4549	case BS3CG1CPU_AVX:
4550	case BS3CG1CPU_AVX2:
4551	if (iCpuSetup > 0 \|\| *pfInvalidInstr)
4552	{
4553	/** @todo do more configs here. */
4554	pThis->fWorkExtCtx = false;
4555	ASMSetCR0(ASMGetCR0() \| X86_CR0_EM \| X86_CR0_MP);
4556	ASMSetCR4(ASMGetCR4() & ~(X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE));
4557	return false;
4558	}
4559	return false;
4560
4561	default:
4562	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
4563	return false;
4564	}
4565	}
4566
4567
4568	/**
4569	* Check if the instruction is supported by the CPU, possibly making state
4570	* adjustments to enable support for it.
4571	*
4572	* @returns true if supported, false if not.
4573	* @param pThis The state.
4574	*/
4575	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupFirst(PBS3CG1STATE pThis)
4576	{
4577	uint32_t fEax;
4578	uint32_t fEbx;
4579	uint32_t fEcx;
4580	uint32_t fEdx;
4581
4582	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
4583	&& BS3CG1_IS_64BIT_TARGET(pThis))
4584	return false;
4585
4586	switch (pThis->enmCpuTest)
4587	{
4588	case BS3CG1CPU_ANY:
4589	return true;
4590
4591	case BS3CG1CPU_GE_80186:
4592	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80186)
4593	return true;
4594	return false;
4595
4596	case BS3CG1CPU_GE_80286:
4597	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286)
4598	return true;
4599	return false;
4600
4601	case BS3CG1CPU_GE_80386:
4602	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
4603	return true;
4604	return false;
4605
4606	case BS3CG1CPU_GE_80486:
4607	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
4608	return true;
4609	return false;
4610
4611	case BS3CG1CPU_GE_Pentium:
4612	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_Pentium)
4613	return true;
4614	return false;
4615
4616	case BS3CG1CPU_MMX:
4617	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4618	{
4619	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
4620	if (fEdx & X86_CPUID_FEATURE_EDX_MMX)
4621	return Bs3Cg3SetupSseAndAvx(pThis); /** @todo only do FNSAVE/FXSAVE here? */
4622	}
4623	return false;
4624
4625	case BS3CG1CPU_SSE:
4626	case BS3CG1CPU_SSE2:
4627	case BS3CG1CPU_SSE3:
4628	case BS3CG1CPU_SSE4_1:
4629	case BS3CG1CPU_AVX:
4630	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4631	{
4632	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
4633	switch (pThis->enmCpuTest)
4634	{
4635	case BS3CG1CPU_SSE:
4636	if (fEdx & X86_CPUID_FEATURE_EDX_SSE)
4637	return Bs3Cg3SetupSseAndAvx(pThis);
4638	return false;
4639	case BS3CG1CPU_SSE2:
4640	if (fEdx & X86_CPUID_FEATURE_EDX_SSE2)
4641	return Bs3Cg3SetupSseAndAvx(pThis);
4642	return false;
4643	case BS3CG1CPU_SSE3:
4644	if (fEcx & X86_CPUID_FEATURE_ECX_SSE3)
4645	return Bs3Cg3SetupSseAndAvx(pThis);
4646	return false;
4647	case BS3CG1CPU_SSE4_1:
4648	if (fEcx & X86_CPUID_FEATURE_ECX_SSE4_1)
4649	return Bs3Cg3SetupSseAndAvx(pThis);
4650	return false;
4651	case BS3CG1CPU_AVX:
4652	if (fEcx & X86_CPUID_FEATURE_ECX_AVX)
4653	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
4654	return false;
4655	default: BS3_ASSERT(0); /* impossible */
4656	}
4657	}
4658	return false;
4659
4660	case BS3CG1CPU_AVX2:
4661	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4662	{
4663	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, &fEax, &fEbx, &fEcx, &fEdx);
4664	switch (pThis->enmCpuTest)
4665	{
4666	case BS3CG1CPU_AVX2:
4667	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2)
4668	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
4669	return false;
4670	default: BS3_ASSERT(0); return false; /* impossible */
4671	}
4672	}
4673	return false;
4674
4675	case BS3CG1CPU_CLFSH:
4676	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4677	{
4678	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
4679	if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
4680	return true;
4681	}
4682	return false;
4683
4684	case BS3CG1CPU_CLFLUSHOPT:
4685	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
4686	{
4687	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, NULL, &fEbx, NULL, NULL);
4688	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
4689	return true;
4690	}
4691	return false;
4692
4693	default:
4694	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
4695	return false;
4696	}
4697	}
4698
4699
4700
4701	/**
4702	* Checks the preconditions for a test.
4703	*
4704	* @returns true if the test be executed, false if not.
4705	* @param pThis The state.
4706	* @param pHdr The test header.
4707	*/
4708	static bool BS3_NEAR_CODE Bs3Cg1RunSelector(PBS3CG1STATE pThis, PCBS3CG1TESTHDR pHdr)
4709	{
4710
4711	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1);
4712	unsigned cbLeft = pHdr->cbSelector;
4713	while (cbLeft-- > 0)
4714	{
4715	switch (*pbCode++)
4716	{
4717	#define CASE_PRED(a_Pred, a_Expr) \
4718	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_TRUE: \
4719	if (!(a_Expr)) return false; \
4720	break; \
4721	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_FALSE: \
4722	if (a_Expr) return false; \
4723	break
4724	CASE_PRED(BS3CG1PRED_SIZE_O16, pThis->cbOperand == 2);
4725	CASE_PRED(BS3CG1PRED_SIZE_O32, pThis->cbOperand == 4);
4726	CASE_PRED(BS3CG1PRED_SIZE_O64, pThis->cbOperand == 8);
4727	CASE_PRED(BS3CG1PRED_VEXL_0, pThis->uVexL == 0);
4728	CASE_PRED(BS3CG1PRED_VEXL_1, pThis->uVexL == 1);
4729	CASE_PRED(BS3CG1PRED_RING_0, pThis->uCpl == 0);
4730	CASE_PRED(BS3CG1PRED_RING_1, pThis->uCpl == 1);
4731	CASE_PRED(BS3CG1PRED_RING_2, pThis->uCpl == 2);
4732	CASE_PRED(BS3CG1PRED_RING_3, pThis->uCpl == 3);
4733	CASE_PRED(BS3CG1PRED_RING_0_THRU_2, pThis->uCpl <= 2);
4734	CASE_PRED(BS3CG1PRED_RING_1_THRU_3, pThis->uCpl >= 1);
4735	CASE_PRED(BS3CG1PRED_CODE_64BIT, BS3CG1_IS_64BIT_TARGET(pThis));
4736	CASE_PRED(BS3CG1PRED_CODE_32BIT, BS3_MODE_IS_32BIT_CODE(pThis->bMode));
4737	CASE_PRED(BS3CG1PRED_CODE_16BIT, BS3_MODE_IS_16BIT_CODE(pThis->bMode));
4738	CASE_PRED(BS3CG1PRED_MODE_REAL, BS3_MODE_IS_RM_SYS(pThis->bMode));
4739	CASE_PRED(BS3CG1PRED_MODE_PROT, BS3_MODE_IS_PM_SYS(pThis->bMode));
4740	CASE_PRED(BS3CG1PRED_MODE_LONG, BS3_MODE_IS_64BIT_SYS(pThis->bMode));
4741	CASE_PRED(BS3CG1PRED_MODE_SMM, false);
4742	CASE_PRED(BS3CG1PRED_MODE_VMX, false);
4743	CASE_PRED(BS3CG1PRED_MODE_SVM, false);
4744	CASE_PRED(BS3CG1PRED_PAGING_ON, BS3_MODE_IS_PAGED(pThis->bMode));
4745	CASE_PRED(BS3CG1PRED_PAGING_OFF, !BS3_MODE_IS_PAGED(pThis->bMode));
4746	CASE_PRED(BS3CG1PRED_VENDOR_AMD, pThis->bCpuVendor == BS3CPUVENDOR_AMD);
4747	CASE_PRED(BS3CG1PRED_VENDOR_INTEL, pThis->bCpuVendor == BS3CPUVENDOR_INTEL);
4748	CASE_PRED(BS3CG1PRED_VENDOR_VIA, pThis->bCpuVendor == BS3CPUVENDOR_VIA);
4749	CASE_PRED(BS3CG1PRED_VENDOR_SHANGHAI, pThis->bCpuVendor == BS3CPUVENDOR_SHANGHAI);
4750	CASE_PRED(BS3CG1PRED_VENDOR_HYGON, pThis->bCpuVendor == BS3CPUVENDOR_HYGON);
4751
4752	#undef CASE_PRED
4753	default:
4754	return Bs3TestFailedF("Invalid selector opcode %#x!", pbCode[-1]);
4755	}
4756	}
4757
4758	return true;
4759	}
4760
4761
4762	#ifdef BS3CG1_DEBUG_CTX_MOD
4763	/**
4764	* Translates the operator into a string.
4765	*
4766	* @returns Read-only string pointer.
4767	* @param bOpcode The context modifier program opcode.
4768	*/
4769	static const char BS3_FAR * BS3_NEAR_CODE Bs3Cg1CtxOpToString(uint8_t bOpcode)
4770	{
4771	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
4772	{
4773	case BS3CG1_CTXOP_ASSIGN: return "=";
4774	case BS3CG1_CTXOP_OR: return "\|=";
4775	case BS3CG1_CTXOP_AND: return "&=";
4776	case BS3CG1_CTXOP_AND_INV: return "&~=";
4777	default: return "?WTF?";
4778	}
4779	}
4780	#endif
4781
4782
4783	/**
4784	* Runs a context modifier program.
4785	*
4786	* @returns Success indicator (true/false).
4787	* @param pThis The state.
4788	* @param pCtx The context.
4789	* @param pHdr The program header.
4790	* @param off The program offset relative to the end of the header.
4791	* @param cb The program size.
4792	* @param pEflCtx The context to take undefined EFLAGS from. (This is NULL
4793	* if we're processing a input context modifier program.)
4794	* @param pbInstr Points to the first instruction byte. For storing
4795	* immediate operands during input context modification.
4796	* NULL for output contexts.
4797	*/
4798	static bool BS3_NEAR_CODE Bs3Cg1RunContextModifier(PBS3CG1STATE pThis, PBS3REGCTX pCtx, PCBS3CG1TESTHDR pHdr,
4799	unsigned off, unsigned cb,
4800	PCBS3REGCTX pEflCtx, uint8_t BS3_FAR *pbInstr)
4801	{
4802	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1) + off;
4803	int cbLeft = cb;
4804	while (cbLeft-- > 0)
4805	{
4806	/*
4807	* Decode the instruction.
4808	*/
4809	uint8_t const bOpcode = *pbCode++;
4810	unsigned cbValue;
4811	unsigned cbDst;
4812	BS3CG1DST idxField;
4813	BS3PTRUNION PtrField;
4814	uint8_t BS3_FAR *pbMemCopy = NULL;
4815	bool fZxVlMax;
4816
4817	/* Expand the destiation field (can be escaped). Set fZxVlMax. */
4818	switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
4819	{
4820	case BS3CG1_CTXOP_OP1:
4821	idxField = pThis->aOperands[0].idxField;
4822	if (idxField == BS3CG1DST_INVALID)
4823	idxField = BS3CG1DST_OP1;
4824	fZxVlMax = pEflCtx != NULL && pThis->aOperands[0].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
4825	break;
4826
4827	case BS3CG1_CTXOP_OP2:
4828	idxField = pThis->aOperands[1].idxField;
4829	if (idxField == BS3CG1DST_INVALID)
4830	idxField = BS3CG1DST_OP2;
4831	fZxVlMax = pEflCtx != NULL && pThis->aOperands[1].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
4832	break;
4833
4834	case BS3CG1_CTXOP_EFL:
4835	idxField = BS3CG1DST_EFL;
4836	fZxVlMax = false;
4837	break;
4838
4839	case BS3CG1_CTXOP_DST_ESC:
4840	if (cbLeft-- > 0)
4841	{
4842	idxField = (BS3CG1DST)*pbCode++;
4843	if (idxField <= BS3CG1DST_OP4)
4844	{
4845	if (idxField > BS3CG1DST_INVALID)
4846	{
4847	unsigned idxOp = idxField - BS3CG1DST_OP1;
4848	uint8_t idxField2 = pThis->aOperands[idxOp].idxField;
4849	if (idxField2 != BS3CG1DST_INVALID)
4850	idxField = idxField2;
4851	fZxVlMax = pEflCtx != NULL && pThis->aOperands[idxOp].enmLocation == BS3CG1OPLOC_CTX_ZX_VLMAX;
4852	break;
4853	}
4854	}
4855	else if (idxField < BS3CG1DST_END)
4856	{
4857	fZxVlMax = false;
4858	break;
4859	}
4860	return Bs3TestFailedF("Malformed context instruction: idxField=%d", idxField);
4861	}
4862	RT_FALL_THRU();
4863	default:
4864	return Bs3TestFailed("Malformed context instruction: Destination");
4865	}
4866
4867	/* Expand value size (can be escaped). */
4868	switch (bOpcode & BS3CG1_CTXOP_SIZE_MASK)
4869	{
4870	case BS3CG1_CTXOP_1_BYTE: cbValue = 1; break;
4871	case BS3CG1_CTXOP_2_BYTES: cbValue = 2; break;
4872	case BS3CG1_CTXOP_4_BYTES: cbValue = 4; break;
4873	case BS3CG1_CTXOP_8_BYTES: cbValue = 8; break;
4874	case BS3CG1_CTXOP_16_BYTES: cbValue = 16; break;
4875	case BS3CG1_CTXOP_32_BYTES: cbValue = 32; break;
4876	case BS3CG1_CTXOP_12_BYTES: cbValue = 12; break;
4877	case BS3CG1_CTXOP_SIZE_ESC:
4878	if (cbLeft-- > 0)
4879	{
4880	cbValue = *pbCode++;
4881	if (cbValue)
4882	break;
4883	}
4884	RT_FALL_THRU();
4885	default:
4886	return Bs3TestFailed("Malformed context instruction: size");
4887	}
4888
4889	/* Make sure there is enough instruction bytes for the value. */
4890	if (cbValue <= cbLeft)
4891	{ /* likely */ }
4892	else
4893	return Bs3TestFailedF("Malformed context instruction: %u bytes value, %u bytes left", cbValue, cbLeft);
4894
4895	/*
4896	* Do value processing specific to the target field size.
4897	*/
4898	cbDst = g_acbBs3Cg1DstFields[idxField];
4899	if (cbDst == BS3CG1DSTSIZE_OPERAND)
4900	cbDst = pThis->aOperands[idxField - BS3CG1DST_OP1].cbOp;
4901	else if (cbDst == BS3CG1DSTSIZE_OPERAND_SIZE_GRP)
4902	cbDst = pThis->cbOperand;
4903	if (cbDst <= 8)
4904	{
4905	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
4906
4907	/*
4908	* Deal with fields up to 8-byte wide.
4909	*/
4910
4911	/* Get the value. */
4912	uint64_t uValue;
4913	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT))
4914	switch (cbValue)
4915	{
4916	case 1: uValue = (int8_t const BS3_FAR )pbCode; break;
4917	case 2: uValue = (int16_t const BS3_FAR )pbCode; break;
4918	case 4: uValue = (int32_t const BS3_FAR )pbCode; break;
4919	default:
4920	if (cbValue >= 8)
4921	{
4922	uValue = (uint64_t const BS3_FAR )pbCode;
4923	break;
4924	}
4925	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
4926	}
4927	else
4928	switch (cbValue)
4929	{
4930	case 1: uValue = (uint8_t const BS3_FAR )pbCode; break;
4931	case 2: uValue = (uint16_t const BS3_FAR )pbCode; break;
4932	case 4: uValue = (uint32_t const BS3_FAR )pbCode; break;
4933	default:
4934	if (cbValue >= 8)
4935	{
4936	uValue = (uint64_t const BS3_FAR )pbCode;
4937	break;
4938	}
4939	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
4940	}
4941
4942	/* Find the field. */
4943	if (offField < sizeof(BS3REGCTX))
4944	PtrField.pu8 = (uint8_t BS3_FAR *)pCtx + offField;
4945	/* Non-register operands: */
4946	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
4947	{
4948	unsigned const idxOp = idxField - BS3CG1DST_OP1;
4949
4950	switch (pThis->aOperands[idxOp].enmLocation)
4951	{
4952	case BS3CG1OPLOC_IMM:
4953	if (pbInstr)
4954	PtrField.pu8 = &pbInstr[pThis->aOperands[idxOp].off];
4955	else
4956	return Bs3TestFailedF("Immediate operand referenced in output context!");
4957	break;
4958
4959	case BS3CG1OPLOC_MEM:
4960	if (!pbInstr)
4961	return Bs3TestFailedF("Read only operand specified in output!");
4962	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
4963	break;
4964
4965	case BS3CG1OPLOC_MEM_RW:
4966	case BS3CG1OPLOC_MEM_WO:
4967	if (pbInstr)
4968	{
4969	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
4970	pbMemCopy = pThis->MemOp.ab;
4971	}
4972	else
4973	PtrField.pu8 = pThis->MemOp.ab;
4974	break;
4975
4976	default:
4977	if (pThis->enmEncoding != pThis->enmEncodingNonInvalid)
4978	goto l_advance_to_next;
4979	return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
4980	cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
4981	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
4982	}
4983	}
4984	/* Special field: Copying in undefined EFLAGS from the result context. */
4985	else if (idxField == BS3CG1DST_EFL_UNDEF)
4986	{
4987	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN)
4988	return Bs3TestFailed("Invalid BS3CG1DST_EFL_UNDEF usage");
4989	PtrField.pu32 = &pCtx->rflags.u32;
4990	uValue = (*PtrField.pu32 & ~(uint32_t)uValue) \| (pEflCtx->rflags.u32 & (uint32_t)uValue);
4991	}
4992	/* Special field: Expected value (in/result) exception. */
4993	else if (idxField == BS3CG1DST_VALUE_XCPT)
4994	{
4995	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN \|\| cbDst != 1)
4996	return Bs3TestFailed("Invalid BS3CG1DST_VALUE_XCPT usage");
4997	PtrField.pu8 = &pThis->bValueXcpt;
4998	}
4999	/* FPU and FXSAVE format. */
5000	else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
5001	&& offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15]))
5002	{
5003	if (pThis->fWorkExtCtx)
5004	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
5005	else if (!pThis->fCpuSetupFirstResult)
5006	{
5007	BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification (<=8)\n"));
5008	goto l_advance_to_next;
5009	}
5010	else
5011	return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n",
5012	idxField, g_aszBs3Cg1DstFields[idxField].sz, offField, cbDst);
5013	}
5014	/** @todo other FPU fields and FPU state formats. */
5015	else
5016	return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d %s offField=%#x (<= 8)",
5017	cbDst, idxField, g_aszBs3Cg1DstFields[idxField].sz, offField);
5018
5019	#ifdef BS3CG1_DEBUG_CTX_MOD
5020	switch (cbDst)
5021	{
5022	case 1:
5023	BS3CG1_DPRINTF(("dbg: modify %s: %#04RX8 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
5024	*PtrField.pu8, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
5025	break;
5026	case 2:
5027	BS3CG1_DPRINTF(("dbg: modify %s: %#06RX16 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
5028	*PtrField.pu16, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
5029	break;
5030	case 4:
5031	BS3CG1_DPRINTF(("dbg: modify %s: %#010RX32 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
5032	*PtrField.pu32, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
5033	break;
5034	default:
5035	BS3CG1_DPRINTF(("dbg: modify %s: %#018RX64 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
5036	*PtrField.pu64, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
5037	break;
5038	}
5039	#endif
5040
5041	/* Modify the field. */
5042	switch (cbDst)
5043	{
5044	case 1:
5045	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5046	{
5047	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu8 = (uint8_t)uValue; break;
5048	case BS3CG1_CTXOP_OR: *PtrField.pu8 \|= (uint8_t)uValue; break;
5049	case BS3CG1_CTXOP_AND: *PtrField.pu8 &= (uint8_t)uValue; break;
5050	case BS3CG1_CTXOP_AND_INV: *PtrField.pu8 &= ~(uint8_t)uValue; break;
5051	}
5052	break;
5053
5054	case 2:
5055	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5056	{
5057	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu16 = (uint16_t)uValue; break;
5058	case BS3CG1_CTXOP_OR: *PtrField.pu16 \|= (uint16_t)uValue; break;
5059	case BS3CG1_CTXOP_AND: *PtrField.pu16 &= (uint16_t)uValue; break;
5060	case BS3CG1_CTXOP_AND_INV: *PtrField.pu16 &= ~(uint16_t)uValue; break;
5061	}
5062	break;
5063
5064	case 4:
5065	if ( (unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX)
5066	\|\| fZxVlMax)
5067	{
5068	PtrField.pu32[1] = 0;
5069	PtrField.pu64[1] = 0;
5070	}
5071	else if (offField <= RT_UOFFSETOF(BS3REGCTX, r15) /* Clear the top dword. */)
5072	PtrField.pu32[1] = 0;
5073	else if ((unsigned)(idxField - BS3CG1DST_MM0_LO_ZX) <= (unsigned)(BS3CG1DST_MM7_LO_ZX - BS3CG1DST_MM0_LO_ZX))
5074	{
5075	PtrField.pu32[1] = 0;
5076	PtrField.pu32[2] = 0xffff; /* observed on skylake */
5077	}
5078	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5079	{
5080	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu32 = (uint32_t)uValue; break;
5081	case BS3CG1_CTXOP_OR: *PtrField.pu32 \|= (uint32_t)uValue; break;
5082	case BS3CG1_CTXOP_AND: *PtrField.pu32 &= (uint32_t)uValue; break;
5083	case BS3CG1_CTXOP_AND_INV: *PtrField.pu32 &= ~(uint32_t)uValue; break;
5084	}
5085	break;
5086
5087	case 8:
5088	if ( (unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX)
5089	\|\| fZxVlMax)
5090	PtrField.pu64[1] = 0;
5091	else if ((unsigned)(idxField - BS3CG1DST_MM0) <= (unsigned)(BS3CG1DST_MM7 - BS3CG1DST_MM0))
5092	PtrField.pu32[2] = 0xffff; /* observed on skylake */
5093
5094	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5095	{
5096	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu64 = (uint64_t)uValue; break;
5097	case BS3CG1_CTXOP_OR: *PtrField.pu64 \|= (uint64_t)uValue; break;
5098	case BS3CG1_CTXOP_AND: *PtrField.pu64 &= (uint64_t)uValue; break;
5099	case BS3CG1_CTXOP_AND_INV: *PtrField.pu64 &= ~(uint64_t)uValue; break;
5100	}
5101	break;
5102
5103	default:
5104	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, expected 1, 2, 4, or 8", cbDst);
5105	}
5106
5107	#ifdef BS3CG1_DEBUG_CTX_MOD
5108	switch (cbDst)
5109	{
5110	case 1: BS3CG1_DPRINTF(("dbg: --> %s: %#04RX8\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu8)); break;
5111	case 2: BS3CG1_DPRINTF(("dbg: --> %s: %#06RX16\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu16)); break;
5112	case 4: BS3CG1_DPRINTF(("dbg: --> %s: %#010RX32\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu32)); break;
5113	default: BS3CG1_DPRINTF(("dbg: --> %s: %#018RX64\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu64)); break;
5114	}
5115	#endif
5116	if (fZxVlMax)
5117	{
5118	uintptr_t iReg = ((uintptr_t)PtrField.pu8 - (uintptr_t)&pThis->pExtCtx->Ctx.x87.aXMM[0])
5119	/ sizeof(pThis->pExtCtx->Ctx.x87.aXMM[0]);
5120	pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0] = 0;
5121	pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[1] = 0;
5122	#ifdef BS3CG1_DEBUG_CTX_MOD
5123	BS3CG1_DPRINTF(("dbg: --> cleared YMM%u_HI\n", iReg));
5124	#endif
5125	}
5126	}
5127	/*
5128	* Deal with larger field (FPU, SSE, AVX, ...).
5129	*/
5130	else if (pThis->fWorkExtCtx)
5131	{
5132	union
5133	{
5134	X86FPUREG FpuReg;
5135	X86XMMREG XmmReg;
5136	X86YMMREG YmmReg;
5137	X86ZMMREG ZmmReg;
5138	uint8_t ab[sizeof(X86ZMMREG)];
5139	uint32_t au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
5140	uint64_t au64[sizeof(X86ZMMREG) / sizeof(uint64_t)];
5141	} Value;
5142	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
5143	unsigned iReg;
5144
5145	/* Copy the value into the union, doing the zero padding / extending. */
5146	Bs3MemCpy(&Value, pbCode, cbValue);
5147	if (cbValue < sizeof(Value))
5148	{
5149	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
5150	Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
5151	else
5152	Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
5153	}
5154
5155	/* Optimized access to XMM and STx registers. */
5156	if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
5157	&& offField - sizeof(BS3REGCTX) < RT_UOFFSET_AFTER(BS3EXTCTX, Ctx.x87.aXMM[15]) )
5158	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
5159	/* Non-register operands: */
5160	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
5161	{
5162	unsigned const idxOp = idxField - BS3CG1DST_OP1;
5163	switch (pThis->aOperands[idxOp].enmLocation)
5164	{
5165	case BS3CG1OPLOC_MEM:
5166	if (!pbInstr)
5167	return Bs3TestFailedF("Read only operand specified in output!");
5168	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
5169	break;
5170
5171	case BS3CG1OPLOC_MEM_RW:
5172	case BS3CG1OPLOC_MEM_WO:
5173	if (pbInstr)
5174	{
5175	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
5176	pbMemCopy = pThis->MemOp.ab;
5177	}
5178	else
5179	PtrField.pu8 = pThis->MemOp.ab;
5180	break;
5181
5182	default:
5183	return Bs3TestFailedF("Internal error: Field %d (%d) @ %#x LB %u: enmLocation=%u off=%#x idxField=%u",
5184	idxField, idxOp, offField, cbDst, pThis->aOperands[idxOp].enmLocation,
5185	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
5186	}
5187	}
5188	/* The YMM (AVX) registers have split storage in the state, so they need special handling. */
5189	else if ((iReg = idxField - BS3CG1DST_YMM0) < 16U)
5190	{
5191	/* The first 128-bits in XMM land. */
5192	PtrField.pu64 = &pThis->pExtCtx->Ctx.x87.aXMM[iReg].au64[0];
5193	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5194	{
5195	case BS3CG1_CTXOP_ASSIGN:
5196	PtrField.pu64[0] = Value.au64[0];
5197	PtrField.pu64[1] = Value.au64[1];
5198	break;
5199	case BS3CG1_CTXOP_OR:
5200	PtrField.pu64[0] \|= Value.au64[0];
5201	PtrField.pu64[1] \|= Value.au64[1];
5202	break;
5203	case BS3CG1_CTXOP_AND:
5204	PtrField.pu64[0] &= Value.au64[0];
5205	PtrField.pu64[1] &= Value.au64[1];
5206	break;
5207	case BS3CG1_CTXOP_AND_INV:
5208	PtrField.pu64[0] &= ~Value.au64[0];
5209	PtrField.pu64[1] &= ~Value.au64[1];
5210	break;
5211	}
5212
5213	/* The second 128-bit in YMM_HI land. */
5214	PtrField.pu64 = &pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0];
5215	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5216	{
5217	case BS3CG1_CTXOP_ASSIGN:
5218	PtrField.pu64[0] = Value.au64[2];
5219	PtrField.pu64[1] = Value.au64[3];
5220	break;
5221	case BS3CG1_CTXOP_OR:
5222	PtrField.pu64[0] \|= Value.au64[2];
5223	PtrField.pu64[1] \|= Value.au64[3];
5224	break;
5225	case BS3CG1_CTXOP_AND:
5226	PtrField.pu64[0] &= Value.au64[2];
5227	PtrField.pu64[1] &= Value.au64[3];
5228	break;
5229	case BS3CG1_CTXOP_AND_INV:
5230	PtrField.pu64[0] &= ~Value.au64[2];
5231	PtrField.pu64[1] &= ~Value.au64[3];
5232	break;
5233	}
5234	PtrField.pb = NULL;
5235	}
5236	/* AVX512 needs handling like above, but more complicated. */
5237	else
5238	return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
5239
5240	if (PtrField.pb)
5241	{
5242	/* Modify the field / memory. */
5243	unsigned i;
5244	if (cbDst & 3)
5245	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
5246
5247	#ifdef BS3CG1_DEBUG_CTX_MOD
5248	BS3CG1_DPRINTF(("dbg: modify %s: %.Rhxs (LB %u) %s %.Rhxs (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
5249	cbDst, PtrField.pb, cbDst, Bs3Cg1CtxOpToString(bOpcode), cbValue, Value.ab, cbValue));
5250	#endif
5251
5252	i = cbDst / 4;
5253	while (i-- > 0)
5254	{
5255	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
5256	{
5257	case BS3CG1_CTXOP_ASSIGN: PtrField.pu32[i] = Value.au32[i]; break;
5258	case BS3CG1_CTXOP_OR: PtrField.pu32[i] \|= Value.au32[i]; break;
5259	case BS3CG1_CTXOP_AND: PtrField.pu32[i] &= Value.au32[i]; break;
5260	case BS3CG1_CTXOP_AND_INV: PtrField.pu32[i] &= ~Value.au32[i]; break;
5261	}
5262	}
5263
5264	#ifdef BS3CG1_DEBUG_CTX_MOD
5265	BS3CG1_DPRINTF(("dbg: --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
5266	#endif
5267
5268	if (fZxVlMax)
5269	{
5270	uintptr_t iReg = ((uintptr_t)PtrField.pu8 - (uintptr_t)&pThis->pExtCtx->Ctx.x87.aXMM[0])
5271	/ sizeof(pThis->pExtCtx->Ctx.x87.aXMM[0]);
5272	if (cbDst < 16)
5273	{
5274	for (i = cbDst / 4; i < 4; i++)
5275	PtrField.pu32[i++] = 0;
5276	#ifdef BS3CG1_DEBUG_CTX_MOD
5277	BS3CG1_DPRINTF(("dbg: --> cleared high %u bytes of XMM%u\n", 16 - cbDst, iReg));
5278	#endif
5279	}
5280	pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[0] = 0;
5281	pThis->pExtCtx->Ctx.x.u.YmmHi.aYmmHi[iReg].au64[1] = 0;
5282	#ifdef BS3CG1_DEBUG_CTX_MOD
5283	BS3CG1_DPRINTF(("dbg: --> cleared YMM%u_HI\n", iReg));
5284	#endif
5285	}
5286	}
5287
5288	/*
5289	* Hack! Update pThis->MemOp when setting up the inputs so we can
5290	* correctly validate value and alignment exceptions.
5291	*/
5292	if (pbMemCopy && PtrField.pv)
5293	Bs3MemCpy(pbMemCopy, PtrField.pv, cbDst);
5294	}
5295	/* !pThis->fWorkExtCtx: */
5296	else if (pThis->fCpuSetupFirstResult)
5297	return Bs3TestFailedF("Extended context disabled: Field %d (%s) @ %#x LB %u\n",
5298	idxField, g_aszBs3Cg1DstFields[idxField].sz, g_aoffBs3Cg1DstFields[idxField], cbDst);
5299	else
5300	BS3CG1_DPRINTF(("dbg: Extended context disabled: skipping modification [> 8]\n"));
5301
5302	/*
5303	* Advance to the next instruction.
5304	*/
5305	l_advance_to_next:
5306	pbCode += cbValue;
5307	cbLeft -= cbValue;
5308	}
5309
5310	return true;
5311	}
5312
5313
5314	/**
5315	* Checks the result of a run.
5316	*
5317	* @returns true if successful, false if not.
5318	* @param pThis The state.
5319	* @param bTestXcptExpected The exception causing the test code to stop
5320	* executing.
5321	* @param fInvalidEncodingPgFault Set if we've cut the instruction a byte
5322	* short and is expecting a \#PF on the page
5323	* boundrary rather than a \#UD. Only set if
5324	* fInvalidEncoding is also set.
5325	* @param iEncoding For error reporting.
5326	*/
5327	static bool BS3_NEAR_CODE Bs3Cg1CheckResult(PBS3CG1STATE pThis, uint8_t bTestXcptExpected,
5328	bool fInvalidEncodingPgFault, unsigned iEncoding)
5329	{
5330	unsigned iOperand;
5331
5332	/*
5333	* Check the exception state first.
5334	*/
5335	uint8_t bExpectedXcpt;
5336	uint8_t cbAdjustPc;
5337	if (!pThis->fInvalidEncoding)
5338	{
5339	bExpectedXcpt = pThis->bAlignmentXcpt;
5340	if (bExpectedXcpt == UINT8_MAX)
5341	bExpectedXcpt = pThis->bValueXcpt;
5342	if (bExpectedXcpt == UINT8_MAX)
5343	{
5344	cbAdjustPc = pThis->cbCurInstr;
5345	bExpectedXcpt = bTestXcptExpected;
5346	if (bTestXcptExpected == X86_XCPT_PF)
5347	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
5348	}
5349	else
5350	cbAdjustPc = 0;
5351	}
5352	else
5353	{
5354	cbAdjustPc = 0;
5355	if (!fInvalidEncodingPgFault)
5356	bExpectedXcpt = X86_XCPT_UD;
5357	else
5358	{
5359	bExpectedXcpt = X86_XCPT_PF;
5360	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
5361	}
5362	}
5363	if (RT_LIKELY( pThis->TrapFrame.bXcpt == bExpectedXcpt
5364	&& pThis->TrapFrame.Ctx.rip.u == pThis->Ctx.rip.u + cbAdjustPc))
5365	{
5366	/*
5367	* Check the register content.
5368	*/
5369	bool fOkay = Bs3TestCheckRegCtxEx(&pThis->TrapFrame.Ctx, &pThis->Ctx,
5370	cbAdjustPc, 0 /cbSpAdjust/, 0 /fExtraEfl/,
5371	pThis->pszMode, iEncoding);
5372
5373	/*
5374	* Check memory output operands.
5375	*/
5376	if (!pThis->fInvalidEncoding)
5377	{
5378	iOperand = pThis->cOperands;
5379	while (iOperand-- > 0)
5380	if ( pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW
5381	\|\| pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_WO)
5382	{
5383	if (pThis->aOperands[iOperand].off)
5384	{
5385	BS3PTRUNION PtrUnion;
5386	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
5387	switch (pThis->aOperands[iOperand].cbOp)
5388	{
5389	case 1:
5390	if (*PtrUnion.pu8 == pThis->MemOp.ab[0])
5391	continue;
5392	Bs3TestFailedF("op%u: Wrote %#04RX8, expected %#04RX8",
5393	iOperand, *PtrUnion.pu8, pThis->MemOp.ab[0]);
5394	break;
5395	case 2:
5396	if (*PtrUnion.pu16 == pThis->MemOp.au16[0])
5397	continue;
5398	Bs3TestFailedF("op%u: Wrote %#06RX16, expected %#06RX16",
5399	iOperand, *PtrUnion.pu16, pThis->MemOp.au16[0]);
5400	break;
5401	case 4:
5402	if (*PtrUnion.pu32 == pThis->MemOp.au32[0])
5403	continue;
5404	Bs3TestFailedF("op%u: Wrote %#010RX32, expected %#010RX32",
5405	iOperand, *PtrUnion.pu32, pThis->MemOp.au32[0]);
5406	break;
5407	case 8:
5408	if (*PtrUnion.pu64 == pThis->MemOp.au64[0])
5409	continue;
5410	Bs3TestFailedF("op%u: Wrote %#018RX64, expected %#018RX64",
5411	iOperand, *PtrUnion.pu64, pThis->MemOp.au64[0]);
5412	break;
5413	default:
5414	if (Bs3MemCmp(PtrUnion.pb, pThis->MemOp.ab, pThis->aOperands[iOperand].cbOp) == 0)
5415	continue;
5416	Bs3TestFailedF("op%u: Wrote %.Rhxs, expected %.Rhxs",
5417	iOperand,
5418	pThis->aOperands[iOperand].cbOp, PtrUnion.pb,
5419	pThis->aOperands[iOperand].cbOp, pThis->MemOp.ab);
5420	break;
5421	}
5422	}
5423	else
5424	Bs3TestFailedF("op%u: off is zero\n", iOperand);
5425	fOkay = false;
5426	}
5427	}
5428
5429	/*
5430	* Check extended context if enabled.
5431	*/
5432	if (pThis->fWorkExtCtx)
5433	{
5434	PBS3EXTCTX pExpect = pThis->pExtCtx;
5435	PBS3EXTCTX pResult = pThis->pResultExtCtx;
5436	unsigned i;
5437	if ( pExpect->enmMethod == BS3EXTCTXMETHOD_XSAVE
5438	\|\| pExpect->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
5439	{
5440	/* Compare the x87 state, ASSUMING XCR0 bit 1 is set. */
5441	#define CHECK_FIELD(a_Field, a_szFmt) \
5442	if (pResult->Ctx.a_Field != pExpect->Ctx.a_Field) fOkay = Bs3TestFailedF(a_szFmt, pResult->Ctx.a_Field, pExpect->Ctx.a_Field)
5443	CHECK_FIELD(x87.FCW, "FCW: %#06x, expected %#06x");
5444	CHECK_FIELD(x87.FSW, "FSW: %#06x, expected %#06x");
5445	CHECK_FIELD(x87.FTW, "FTW: %#06x, expected %#06x");
5446	//CHECK_FIELD(x87.FOP, "FOP: %#06x, expected %#06x");
5447	//CHECK_FIELD(x87.FPUIP, "FPUIP: %#010RX32, expected %#010RX32");
5448	//CHECK_FIELD(x87.CS, "FPUCS: %#06x, expected %#06x");
5449	//CHECK_FIELD(x87.Rsrvd1, "Rsrvd1: %#06x, expected %#06x");
5450	//CHECK_FIELD(x87.DP, "FPUDP: %#010RX32, expected %#010RX32");
5451	//CHECK_FIELD(x87.DS, "FPUDS: %#06x, expected %#06x");
5452	//CHECK_FIELD(x87.Rsrvd2, "Rsrvd2: %#06x, expected %#06x");
5453	CHECK_FIELD(x87.MXCSR, "MXCSR: %#010RX32, expected %#010RX32");
5454	#undef CHECK_FIELD
5455	for (i = 0; i < RT_ELEMENTS(pExpect->Ctx.x87.aRegs); i++)
5456	if ( pResult->Ctx.x87.aRegs[i].au64[0] != pExpect->Ctx.x87.aRegs[i].au64[0]
5457	\|\| pResult->Ctx.x87.aRegs[i].au16[4] != pExpect->Ctx.x87.aRegs[i].au16[4])
5458	fOkay = Bs3TestFailedF("ST[%u]: %c m=%#RX64 e=%d, expected %c m=%#RX64 e=%d", i,
5459	pResult->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
5460	pResult->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
5461	pResult->Ctx.x87.aRegs[i].r80Ex.s.uExponent,
5462	pExpect->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
5463	pExpect->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
5464	pExpect->Ctx.x87.aRegs[i].r80Ex.s.uExponent);
5465	for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
5466	if ( pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
5467	\|\| pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
5468	fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
5469	pResult->Ctx.x87.aXMM[i].au64[1],
5470	pResult->Ctx.x87.aXMM[i].au64[0],
5471	pExpect->Ctx.x87.aXMM[i].au64[1],
5472	pExpect->Ctx.x87.aXMM[i].au64[0]);
5473	if (pExpect->fXcr0Saved & XSAVE_C_YMM)
5474	for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
5475	if ( pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[0] != pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[0]
5476	\|\| pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[1] != pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[1])
5477	fOkay = Bs3TestFailedF("YMM%u_HI: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
5478	pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[1],
5479	pResult->Ctx.x.u.YmmHi.aYmmHi[i].au64[0],
5480	pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[1],
5481	pExpect->Ctx.x.u.YmmHi.aYmmHi[i].au64[0]);
5482	}
5483	else
5484	fOkay = Bs3TestFailedF("Unsupported extended CPU context method: %d", pExpect->enmMethod);
5485	}
5486
5487	/*
5488	* Done.
5489	*/
5490	if (fOkay)
5491	return true;
5492
5493	/*
5494	* Report failure.
5495	*/
5496	Bs3TestFailedF("ins#%RU32/test#%u: encoding #%u: %.*Rhxs%s",
5497	pThis->iInstr, pThis->iTest, iEncoding, pThis->cbCurInstr, pThis->abCurInstr,
5498	fInvalidEncodingPgFault ? " (cut short)" : "");
5499	}
5500	else
5501	Bs3TestFailedF("ins#%RU32/test#%u: bXcpt=%#x expected %#x; rip=%RX64 expected %RX64; encoding#%u: %.*Rhxs%s",
5502	pThis->iInstr, pThis->iTest,
5503	pThis->TrapFrame.bXcpt, bExpectedXcpt,
5504	pThis->TrapFrame.Ctx.rip.u, pThis->Ctx.rip.u + cbAdjustPc,
5505	iEncoding, pThis->cbCurInstr, pThis->abCurInstr, fInvalidEncodingPgFault ? " (cut short)" : "");
5506	Bs3TestPrintf("cpl=%u cbOperands=%u\n", pThis->uCpl, pThis->cbOperand);
5507
5508	/*
5509	* Display memory operands.
5510	*/
5511	for (iOperand = 0; iOperand < pThis->cOperands; iOperand++)
5512	{
5513	BS3PTRUNION PtrUnion;
5514	switch (pThis->aOperands[iOperand].enmLocation)
5515	{
5516	case BS3CG1OPLOC_CTX:
5517	{
5518	uint8_t idxField = pThis->aOperands[iOperand].idxField;
5519	unsigned offField = g_aoffBs3Cg1DstFields[idxField];
5520	if (offField <= sizeof(BS3REGCTX))
5521	PtrUnion.pb = (uint8_t BS3_FAR *)&pThis->Ctx + offField;
5522	else
5523	{
5524	Bs3TestPrintf("op%u: ctx%u: xxxx\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
5525	break;
5526	}
5527	switch (pThis->aOperands[iOperand].cbOp)
5528	{
5529	case 1: Bs3TestPrintf("op%u: ctx08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
5530	case 2: Bs3TestPrintf("op%u: ctx16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
5531	case 4: Bs3TestPrintf("op%u: ctx32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
5532	case 8: Bs3TestPrintf("op%u: ctx64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
5533	default:
5534	Bs3TestPrintf("op%u: ctx%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
5535	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
5536	break;
5537	}
5538	break;
5539	}
5540
5541	case BS3CG1OPLOC_IMM:
5542	PtrUnion.pb = &pThis->pbCodePg[pThis->aOperands[iOperand].off];
5543	switch (pThis->aOperands[iOperand].cbOp)
5544	{
5545	case 1: Bs3TestPrintf("op%u: imm08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
5546	case 2: Bs3TestPrintf("op%u: imm16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
5547	case 4: Bs3TestPrintf("op%u: imm32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
5548	case 8: Bs3TestPrintf("op%u: imm64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
5549	default:
5550	Bs3TestPrintf("op%u: imm%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
5551	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
5552	break;
5553	}
5554	break;
5555
5556	case BS3CG1OPLOC_MEM:
5557	case BS3CG1OPLOC_MEM_RW:
5558	case BS3CG1OPLOC_MEM_WO:
5559	if (pThis->aOperands[iOperand].off)
5560	{
5561	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
5562	switch (pThis->aOperands[iOperand].cbOp)
5563	{
5564	case 1: Bs3TestPrintf("op%u: result mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
5565	case 2: Bs3TestPrintf("op%u: result mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
5566	case 4: Bs3TestPrintf("op%u: result mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
5567	case 8: Bs3TestPrintf("op%u: result mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
5568	default:
5569	Bs3TestPrintf("op%u: result mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
5570	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
5571	break;
5572	}
5573	if ( pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_WO
5574	\|\| pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
5575	{
5576	PtrUnion.pb = pThis->MemOp.ab;
5577	switch (pThis->aOperands[iOperand].cbOp)
5578	{
5579	case 1: Bs3TestPrintf("op%u: expect mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
5580	case 2: Bs3TestPrintf("op%u: expect mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
5581	case 4: Bs3TestPrintf("op%u: expect mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
5582	case 8: Bs3TestPrintf("op%u: expect mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
5583	default:
5584	Bs3TestPrintf("op%u: expect mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
5585	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
5586	break;
5587	}
5588	}
5589	}
5590	else
5591	Bs3TestPrintf("op%u: mem%u: zero off value!!\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
5592	break;
5593	}
5594	}
5595
5596	/*
5597	* Display contexts.
5598	*/
5599	Bs3TestPrintf("-- Expected context:\n");
5600	Bs3RegCtxPrint(&pThis->Ctx);
5601	if (pThis->fWorkExtCtx)
5602	Bs3TestPrintf("xcr0=%RX64\n", pThis->pExtCtx->fXcr0Saved);
5603	Bs3TestPrintf("-- Actual context:\n");
5604	Bs3TrapPrintFrame(&pThis->TrapFrame);
5605	if (pThis->fWorkExtCtx)
5606	Bs3TestPrintf("xcr0=%RX64\n", pThis->pResultExtCtx->fXcr0Saved);
5607	Bs3TestPrintf("\n");
5608	ASMHalt();
5609	return false;
5610	}
5611
5612
5613	/**
5614	* Destroys the state, freeing all allocations and such.
5615	*
5616	* @param pThis The state.
5617	*/
5618	static void BS3_NEAR_CODE Bs3Cg1Destroy(PBS3CG1STATE pThis)
5619	{
5620	if (BS3_MODE_IS_PAGED(pThis->bMode))
5621	{
5622	#if ARCH_BITS != 16
5623	Bs3MemGuardedTestPageFree(pThis->pbCodePg);
5624	Bs3MemGuardedTestPageFree(pThis->pbDataPg);
5625	#endif
5626	}
5627	else
5628	{
5629	Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
5630	Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
5631	}
5632
5633	if (pThis->pExtCtx)
5634	Bs3MemFree(pThis->pExtCtx, pThis->pExtCtx->cb * 3);
5635
5636	pThis->pbCodePg = NULL;
5637	pThis->pbDataPg = NULL;
5638	pThis->pExtCtx = NULL;
5639	pThis->pResultExtCtx = NULL;
5640	pThis->pInitialExtCtx = NULL;
5641	}
5642
5643
5644	/**
5645	* Initializes the state.
5646	*
5647	* @returns Success indicator (true/false)
5648	* @param pThis The state.
5649	* @param bMode The mode being tested.
5650	*/
5651	bool BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1Init)(PBS3CG1STATE pThis, uint8_t bMode)
5652	{
5653	BS3MEMKIND const enmMemKind = BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL
5654	: !BS3_MODE_IS_64BIT_CODE(bMode) ? BS3MEMKIND_TILED : BS3MEMKIND_FLAT32;
5655	unsigned iRing;
5656	unsigned cb;
5657	unsigned i;
5658	uint64_t fFlags;
5659	PBS3EXTCTX pExtCtx;
5660
5661	Bs3MemSet(pThis, 0, sizeof(*pThis));
5662
5663	pThis->iFirstRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
5664	pThis->iEndRing = BS3_MODE_IS_RM_SYS(bMode) ? 1 : 4;
5665	pThis->bMode = bMode;
5666	pThis->pszMode = Bs3GetModeName(bMode);
5667	pThis->pszModeShort = Bs3GetModeNameShortLower(bMode);
5668	pThis->bCpuVendor = Bs3GetCpuVendor();
5669	pThis->pchMnemonic = g_achBs3Cg1Mnemonics;
5670	pThis->pabOperands = g_abBs3Cg1Operands;
5671	pThis->pabOpcodes = g_abBs3Cg1Opcodes;
5672	pThis->fAdvanceMnemonic = 1;
5673
5674	/* Allocate extended context structures. */
5675	cb = Bs3ExtCtxGetSize(&fFlags);
5676	pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 3);
5677	if (!pExtCtx)
5678	return Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 3);
5679	pThis->pExtCtx = pExtCtx;
5680	pThis->pResultExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb);
5681	pThis->pInitialExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb + cb);
5682
5683	Bs3ExtCtxInit(pThis->pExtCtx, cb, fFlags);
5684	Bs3ExtCtxInit(pThis->pResultExtCtx, cb, fFlags);
5685	Bs3ExtCtxInit(pThis->pInitialExtCtx, cb, fFlags);
5686	//Bs3TestPrintf("fCR0=%RX64 cbExtCtx=%#x method=%d\n", fFlags, cb, pExtCtx->enmMethod);
5687
5688	/* Allocate guarded exectuable and data memory. */
5689	if (BS3_MODE_IS_PAGED(bMode))
5690	{
5691	#if ARCH_BITS != 16
5692	pThis->pbCodePg = Bs3MemGuardedTestPageAlloc(enmMemKind);
5693	pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
5694	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
5695	{
5696	Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
5697	Bs3MemPrintInfo();
5698	Bs3Shutdown();
5699	return Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
5700	}
5701	if ( BS3_MODE_IS_64BIT_CODE(bMode)
5702	&& (uintptr_t)pThis->pbDataPg >= _2G)
5703	return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
5704	#else
5705	return Bs3TestFailed("WTF?! #1");
5706	#endif
5707	}
5708	else
5709	{
5710	pThis->pbCodePg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
5711	pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
5712	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
5713	{
5714	Bs3MemPrintInfo();
5715	return Bs3TestFailedF("Bs3MemAlloc(%d,Pg) failed", enmMemKind);
5716	}
5717	}
5718	pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
5719	pThis->uDataPgFlat = Bs3SelPtrToFlat(pThis->pbDataPg);
5720	#if ARCH_BITS == 16
5721	pThis->CodePgFar.sel = BS3_FP_SEG(pThis->pbCodePg);
5722	pThis->CodePgFar.off = BS3_FP_OFF(pThis->pbCodePg);
5723	pThis->CodePgRip = BS3_FP_OFF(pThis->pbCodePg);
5724	pThis->DataPgFar.sel = BS3_FP_SEG(pThis->pbDataPg);
5725	pThis->DataPgFar.off = BS3_FP_OFF(pThis->pbDataPg);
5726	#else
5727	if (BS3_MODE_IS_RM_OR_V86(bMode))
5728	{
5729	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToRealMode(pThis->uDataPgFlat);
5730	ASMCompilerBarrier();
5731	pThis->CodePgFar.off = 0;
5732	pThis->CodePgFar.sel = pThis->uCodePgFlat >> 4;
5733	pThis->CodePgRip = pThis->CodePgFar.off;
5734	}
5735	else if (BS3_MODE_IS_16BIT_CODE(bMode))
5736	{
5737	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
5738	ASMCompilerBarrier();
5739	pThis->CodePgFar.sel = BS3_SEL_SPARE_00;
5740	pThis->CodePgFar.off = 0;
5741	pThis->CodePgRip = 0;
5742	}
5743	else if (BS3_MODE_IS_32BIT_CODE(bMode))
5744	{
5745	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
5746	ASMCompilerBarrier();
5747	pThis->CodePgFar.sel = 0;
5748	pThis->CodePgFar.off = 0;
5749	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
5750	}
5751	else
5752	{
5753	pThis->DataPgFar.off = 0;
5754	pThis->DataPgFar.sel = 0;
5755	pThis->CodePgFar.off = 0;
5756	pThis->CodePgFar.sel = 0;
5757	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
5758	}
5759	#endif
5760	BS3CG1_DPRINTF(("pbDataPg=%p %04x:%04x pbCodePg=%p %04x:%04x\n",
5761	pThis->pbDataPg, pThis->DataPgFar.sel, pThis->DataPgFar.off,
5762	pThis->pbCodePg, pThis->CodePgFar.sel, pThis->CodePgFar.off));
5763
5764	/*
5765	* Create basic context for each target ring.
5766	*
5767	* In protected 16-bit code we need set up code selectors that can access
5768	* pbCodePg.
5769	*
5770	* In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
5771	* bits set so we can check that the implicit clearing is tested.
5772	*/
5773	Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
5774	#if ARCH_BITS == 64
5775	pThis->aInitialCtxs[pThis->iFirstRing].rax.u \|= UINT64_C(0x0101010100000000);
5776	pThis->aInitialCtxs[pThis->iFirstRing].rbx.u \|= UINT64_C(0x0202020200000000);
5777	pThis->aInitialCtxs[pThis->iFirstRing].rcx.u \|= UINT64_C(0x0303030300000000);
5778	pThis->aInitialCtxs[pThis->iFirstRing].rdx.u \|= UINT64_C(0x0404040400000000);
5779	pThis->aInitialCtxs[pThis->iFirstRing].rbp.u \|= UINT64_C(0x0505050500000000);
5780	pThis->aInitialCtxs[pThis->iFirstRing].rdi.u \|= UINT64_C(0x0606060600000000);
5781	pThis->aInitialCtxs[pThis->iFirstRing].rsi.u \|= UINT64_C(0x0707070700000000);
5782	pThis->aInitialCtxs[pThis->iFirstRing].r8.u \|= UINT64_C(0x0808080800000000);
5783	pThis->aInitialCtxs[pThis->iFirstRing].r9.u \|= UINT64_C(0x0909090900000000);
5784	pThis->aInitialCtxs[pThis->iFirstRing].r10.u \|= UINT64_C(0x1010101000000000);
5785	pThis->aInitialCtxs[pThis->iFirstRing].r11.u \|= UINT64_C(0x1111111100000000);
5786	pThis->aInitialCtxs[pThis->iFirstRing].r12.u \|= UINT64_C(0x1212121200000000);
5787	pThis->aInitialCtxs[pThis->iFirstRing].r13.u \|= UINT64_C(0x1313131300000000);
5788	pThis->aInitialCtxs[pThis->iFirstRing].r14.u \|= UINT64_C(0x1414141400000000);
5789	pThis->aInitialCtxs[pThis->iFirstRing].r15.u \|= UINT64_C(0x1515151500000000);
5790	#endif
5791
5792	if (BS3_MODE_IS_RM_OR_V86(bMode))
5793	{
5794	pThis->aInitialCtxs[pThis->iFirstRing].cs = pThis->CodePgFar.sel;
5795	BS3_ASSERT(pThis->iFirstRing + 1 == pThis->iEndRing);
5796	}
5797	else if (BS3_MODE_IS_16BIT_CODE(bMode))
5798	{
5799	#if ARCH_BITS == 16
5800	uintptr_t const uFlatCodePgSeg = Bs3SelPtrToFlat(BS3_FP_MAKE(BS3_FP_SEG(pThis->pbCodePg), 0));
5801	#else
5802	uintptr_t const uFlatCodePgSeg = (uintptr_t)pThis->pbCodePg;
5803	#endif
5804	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
5805	{
5806	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
5807	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
5808	}
5809	for (iRing = pThis->iFirstRing; iRing < pThis->iEndRing; iRing++)
5810	{
5811	pThis->aInitialCtxs[iRing].cs = BS3_SEL_SPARE_00 + iRing * 8 + iRing;
5812	Bs3SelSetup16BitCode(&Bs3GdteSpare00 + iRing, uFlatCodePgSeg, iRing);
5813	}
5814	}
5815	else
5816	{
5817	Bs3RegCtxSetRipCsFromCurPtr(&pThis->aInitialCtxs[pThis->iFirstRing], (FPFNBS3FAR)pThis->pbCodePg);
5818	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
5819	{
5820	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
5821	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
5822	}
5823	}
5824
5825	/*
5826	* Create an initial extended CPU context.
5827	*/
5828	pExtCtx = pThis->pInitialExtCtx;
5829	if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
5830	\|\| pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
5831	{
5832	pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL \| X86_FCW_PC_64 \| X86_FCW_RC_NEAREST;
5833	pExtCtx->Ctx.x87.FSW = 0;
5834	pExtCtx->Ctx.x87.MXCSR = X86_MXCSR_IM \| X86_MXCSR_DM \| X86_MXCSR_RC_NEAREST;
5835	pExtCtx->Ctx.x87.MXCSR_MASK = 0;
5836	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
5837	{
5838	pExtCtx->Ctx.x87.aRegs[i].au16[0] = i << 4;
5839	pExtCtx->Ctx.x87.aRegs[i].au16[1] = i << 4;
5840	pExtCtx->Ctx.x87.aRegs[i].au16[2] = i << 4;
5841	pExtCtx->Ctx.x87.aRegs[i].au16[3] = i << 4;
5842	}
5843	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
5844	{
5845	pExtCtx->Ctx.x87.aXMM[i].au16[0] = i \| UINT16_C(0x8f00);
5846	pExtCtx->Ctx.x87.aXMM[i].au16[1] = i \| UINT16_C(0x8e00);
5847	pExtCtx->Ctx.x87.aXMM[i].au16[2] = i \| UINT16_C(0x8d00);
5848	pExtCtx->Ctx.x87.aXMM[i].au16[3] = i \| UINT16_C(0x8c00);
5849	pExtCtx->Ctx.x87.aXMM[i].au16[4] = i \| UINT16_C(0x8b00);
5850	pExtCtx->Ctx.x87.aXMM[i].au16[5] = i \| UINT16_C(0x8a00);
5851	pExtCtx->Ctx.x87.aXMM[i].au16[6] = i \| UINT16_C(0x8900);
5852	pExtCtx->Ctx.x87.aXMM[i].au16[7] = i \| UINT16_C(0x8800);
5853	}
5854	if (pExtCtx->fXcr0Nominal & XSAVE_C_YMM)
5855	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.YmmHi.aYmmHi); i++)
5856	{
5857	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[0] = (i << 8) \| (i << 12) \| 0xff;
5858	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[1] = (i << 8) \| (i << 12) \| 0xfe;
5859	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[2] = (i << 8) \| (i << 12) \| 0xfd;
5860	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[3] = (i << 8) \| (i << 12) \| 0xfc;
5861	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[4] = (i << 8) \| (i << 12) \| 0xfb;
5862	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[5] = (i << 8) \| (i << 12) \| 0xfa;
5863	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[6] = (i << 8) \| (i << 12) \| 0xf9;
5864	pExtCtx->Ctx.x.u.YmmHi.aYmmHi[i].au16[7] = (i << 8) \| (i << 12) \| 0xf8;
5865	}
5866
5867	}
5868	//else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_ANCIENT)
5869	else
5870	return Bs3TestFailedF("Unsupported extended CPU context method: %d", pExtCtx->enmMethod);
5871
5872	return true;
5873	}
5874
5875
5876	static uint8_t BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1WorkerInner)(PBS3CG1STATE pThis)
5877	{
5878	uint8_t iRing;
5879	unsigned iInstr;
5880
5881	/*
5882	* Test the instructions.
5883	*/
5884	for (iInstr = 0; iInstr < g_cBs3Cg1Instructions;
5885	iInstr++,
5886	pThis->pchMnemonic += pThis->fAdvanceMnemonic * pThis->cchMnemonic,
5887	pThis->pabOperands += pThis->cOperands,
5888	pThis->pabOpcodes += pThis->cbOpcodes)
5889	{
5890	uint8_t const bTestXcptExpected = BS3_MODE_IS_PAGED(pThis->bMode) ? X86_XCPT_PF : X86_XCPT_UD;
5891	bool fOuterInvalidInstr = false;
5892	unsigned iCpuSetup;
5893
5894	/*
5895	* Expand the instruction information into the state.
5896	* Note! 16-bit will switch to a two level test header lookup once we exceed 64KB.
5897	*/
5898	PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
5899	pThis->iInstr = iInstr;
5900	pThis->pTestHdr = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
5901	pThis->fFlags = pInstr->fFlags;
5902	pThis->enmEncoding = (BS3CG1ENC)pInstr->enmEncoding;
5903	pThis->enmEncodingNonInvalid = (BS3CG1ENC)pInstr->enmEncoding;
5904	pThis->enmCpuTest = (BS3CG1CPU)pInstr->enmCpuTest;
5905	pThis->enmPrefixKind = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
5906	pThis->enmXcptType = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
5907	pThis->cchMnemonic = pInstr->cchMnemonic;
5908	if (pThis->fAdvanceMnemonic)
5909	Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
5910	pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
5911	pThis->uOpcodeMap = pInstr->uOpcodeMap;
5912	pThis->cOperands = pInstr->cOperands;
5913	pThis->cbOpcodes = pInstr->cbOpcodes;
5914	switch (pThis->cOperands)
5915	{
5916	case 4: pThis->aenmOperands[3] = (BS3CG1OP)pThis->pabOperands[3];
5917	case 3: pThis->aenmOperands[2] = (BS3CG1OP)pThis->pabOperands[2];
5918	case 2: pThis->aenmOperands[1] = (BS3CG1OP)pThis->pabOperands[1];
5919	case 1: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
5920	}
5921	switch (pThis->cbOpcodes)
5922	{
5923	case 4: pThis->abOpcodes[3] = pThis->pabOpcodes[3];
5924	case 3: pThis->abOpcodes[2] = pThis->pabOpcodes[2];
5925	case 2: pThis->abOpcodes[1] = pThis->pabOpcodes[1];
5926	case 1: pThis->abOpcodes[0] = pThis->pabOpcodes[0];
5927	}
5928
5929	/*
5930	* Check if the CPU supports the instruction.
5931	*/
5932	pThis->fCpuSetupFirstResult = Bs3Cg1CpuSetupFirst(pThis);
5933	if ( !pThis->fCpuSetupFirstResult
5934	\|\| (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID)))
5935	fOuterInvalidInstr = true;
5936
5937	/* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
5938	if ( (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
5939	&& pThis->bCpuVendor != BS3CPUVENDOR_INTEL
5940	&& ( (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
5941	\|\| (BS3CG1_IS_64BIT_TARGET(pThis) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT))
5942	\|\| fOuterInvalidInstr ) )
5943	pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
5944
5945	for (iCpuSetup = 0;; iCpuSetup++)
5946	{
5947	unsigned iEncoding;
5948	unsigned iEncodingNext;
5949
5950	/*
5951	* Prep the operands and encoding handling.
5952	*/
5953	Bs3Cg1SetOpSizes(pThis, pThis->bMode);
5954	if (!Bs3Cg1EncodePrep(pThis))
5955	break;
5956
5957	/*
5958	* Encode the instruction in various ways and check out the test values.
5959	*/
5960	for (iEncoding = 0;; iEncoding = iEncodingNext)
5961	{
5962	/*
5963	* Encode the next instruction variation.
5964	*/
5965	pThis->fInvalidEncoding = fOuterInvalidInstr;
5966	iEncodingNext = Bs3Cg1EncodeNext(pThis, iEncoding);
5967	if (iEncodingNext <= iEncoding)
5968	break;
5969	BS3CG1_DPRINTF(("\ndbg: Encoding #%u: cbCurInst=%u: %.*Rhxs fInvalidEncoding=%d\n",
5970	iEncoding, pThis->cbCurInstr, pThis->cbCurInstr, pThis->abCurInstr, pThis->fInvalidEncoding));
5971
5972	/*
5973	* Do the rings.
5974	*/
5975	for (iRing = pThis->iFirstRing + pThis->fSameRingNotOkay; iRing < pThis->iEndRing; iRing++)
5976	{
5977	PCBS3CG1TESTHDR pHdr;
5978
5979	pThis->uCpl = iRing;
5980	BS3CG1_DPRINTF(("dbg: Ring %u\n", iRing));
5981
5982	/*
5983	* Do the tests one by one.
5984	*/
5985	pHdr = pThis->pTestHdr;
5986	for (pThis->iTest = 0;; pThis->iTest++)
5987	{
5988	if (Bs3Cg1RunSelector(pThis, pHdr))
5989	{
5990	/* Okay, set up the execution context. */
5991	unsigned offCode;
5992	uint8_t BS3_FAR *pbCode;
5993
5994	Bs3MemCpy(&pThis->Ctx, &pThis->aInitialCtxs[iRing], sizeof(pThis->Ctx));
5995	if (pThis->fWorkExtCtx)
5996	Bs3ExtCtxCopy(pThis->pExtCtx, pThis->pInitialExtCtx);
5997	if (BS3_MODE_IS_PAGED(pThis->bMode))
5998	{
5999	offCode = X86_PAGE_SIZE - pThis->cbCurInstr;
6000	pbCode = &pThis->pbCodePg[offCode];
6001	//if (iEncoding > 0) { pbCode[-1] = 0xf4; offCode--; }
6002	}
6003	else
6004	{
6005	pbCode = pThis->pbCodePg;
6006	pbCode[pThis->cbCurInstr] = 0x0f; /* UD2 */
6007	pbCode[pThis->cbCurInstr + 1] = 0x0b;
6008	offCode = 0;
6009	}
6010	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
6011	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr);
6012
6013	if (Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr, pHdr->cbSelector, pHdr->cbInput, NULL, pbCode))
6014	{
6015	/* Run the instruction. */
6016	BS3CG1_DPRINTF(("dbg: Running test #%u\n", pThis->iTest));
6017	//Bs3RegCtxPrint(&pThis->Ctx);
6018	if (pThis->fWorkExtCtx)
6019	Bs3ExtCtxRestore(pThis->pExtCtx);
6020	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
6021	if (pThis->fWorkExtCtx)
6022	Bs3ExtCtxSave(pThis->pResultExtCtx);
6023	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64\n",
6024	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
6025
6026	/*
6027	* Apply the output modification program to the context.
6028	*/
6029	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
6030	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
6031	pThis->bValueXcpt = UINT8_MAX; //???
6032	if ( pThis->fInvalidEncoding
6033	\|\| pThis->bAlignmentXcpt != UINT8_MAX
6034	\|\| pThis->bValueXcpt != UINT8_MAX
6035	\|\| Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr,
6036	pHdr->cbSelector + pHdr->cbInput, pHdr->cbOutput,
6037	&pThis->TrapFrame.Ctx, NULL /pbCode/))
6038	Bs3Cg1CheckResult(pThis, bTestXcptExpected, false /fInvalidEncodingPgFault/, iEncoding);
6039	else
6040	{
6041	Bs3TestPrintf("Bs3Cg1RunContextModifier(out): iEncoding=%u iTest=%RU32 iInstr=%u %.*s\n",
6042	iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic);
6043	ASMHalt();
6044	}
6045
6046	/*
6047	* If this is an invalid encoding or instruction, check that we
6048	* get a page fault when shortening it by one byte.
6049	* (Since we didn't execute the output context modifier, we don't
6050	* need to re-initialize the start context.)
6051	*/
6052	if ( pThis->fInvalidEncoding
6053	&& BS3_MODE_IS_PAGED(pThis->bMode)
6054	&& pThis->cbCurInstr)
6055	{
6056	pbCode += 1;
6057	offCode += 1;
6058	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
6059	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr - 1);
6060
6061	/* Run the instruction. */
6062	BS3CG1_DPRINTF(("dbg: Running test #%u (cut short #PF)\n", pThis->iTest));
6063	//Bs3RegCtxPrint(&pThis->Ctx);
6064	if (pThis->fWorkExtCtx)
6065	Bs3ExtCtxRestore(pThis->pExtCtx);
6066	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
6067	if (pThis->fWorkExtCtx)
6068	Bs3ExtCtxSave(pThis->pResultExtCtx);
6069	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64 (cut short #PF)\n",
6070	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
6071
6072	/* Check it */
6073	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
6074	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
6075	Bs3Cg1CheckResult(pThis, X86_XCPT_PF, true /fInvalidEncodingPgFault/, iEncoding);
6076	}
6077	}
6078	else
6079	{
6080	Bs3TestPrintf("Bs3Cg1RunContextModifier(in): iEncoding=%u iTest=%u iInstr=%RU32 %.*s\n",
6081	iEncoding, pThis->iTest, pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic);
6082	ASMHalt();
6083	}
6084	}
6085	else
6086	BS3CG1_DPRINTF(("dbg: Skipping #%u\n", pThis->iTest));
6087
6088	/* advance */
6089	if (pHdr->fLast)
6090	{
6091	BS3CG1_DPRINTF(("dbg: Last\n\n"));
6092	break;
6093	}
6094	pHdr = (PCBS3CG1TESTHDR)((uint8_t BS3_FAR *)(pHdr + 1) + pHdr->cbInput + pHdr->cbOutput + pHdr->cbSelector);
6095	}
6096	}
6097	}
6098
6099	/*
6100	* Clean up (segment registers, etc) and get the next CPU config.
6101	*/
6102	Bs3Cg1EncodeCleanup(pThis);
6103	if (!Bs3Cg1CpuSetupNext(pThis, iCpuSetup, &fOuterInvalidInstr))
6104	break;
6105	if (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
6106	fOuterInvalidInstr = true;
6107	}
6108	}
6109
6110	return 0;
6111	}
6112
6113
6114	BS3_DECL_FAR(uint8_t) BS3_CMN_NM(Bs3Cg1Worker)(uint8_t bMode)
6115	{
6116	uint8_t bRet = 1;
6117	BS3CG1STATE This;
6118
6119	#if 0
6120	/* (for debugging) */
6121	if (bMode != BS3_MODE_LM64)
6122	return BS3TESTDOMODE_SKIPPED;
6123	#endif
6124
6125	if (BS3_CMN_NM(Bs3Cg1Init)(&This, bMode))
6126	{
6127	bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
6128	Bs3TestSubDone();
6129	}
6130	Bs3Cg1Destroy(&This);
6131
6132	#if 0
6133	/* (for debugging) */
6134	if (bMode == BS3_MODE_PPV86)
6135	{
6136	Bs3TestTerm();
6137	Bs3Shutdown();
6138	}
6139	#endif
6140	return bRet;
6141	}
6142

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 83878

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