bs3-cpu-generated-1.h@ 66283

Last change on this file since 66283 was 66283, checked in by vboxsync, 8 years ago
bs3-cpu-generated-1,IEM: More SSE testing stuff.
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1	/* $Id: bs3-cpu-generated-1.h 66283 2017-03-28 09:02:56Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wsd,
47	BS3CG1OP_Wps,
48
49	BS3CG1OP_Gb,
50	BS3CG1OP_Gv,
51	BS3CG1OP_Vsd,
52	BS3CG1OP_Vps,
53
54	BS3CG1OP_Ib,
55	BS3CG1OP_Iz,
56
57	BS3CG1OP_AL,
58	BS3CG1OP_rAX,
59
60	BS3CG1OP_Ma,
61
62	BS3CG1OP_END
63	} BS3CG1OP;
64	/** Pointer to a const operand enum. */
65	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
66
67
68	/**
69	* Instruction encoding format.
70	*
71	* This duplicates some of the info in the operand array, however it makes it
72	* easier to figure out encoding variations.
73	*/
74	typedef enum BS3CG1ENC
75	{
76	BS3CG1ENC_INVALID = 0,
77
78	BS3CG1ENC_MODRM_Eb_Gb,
79	BS3CG1ENC_MODRM_Ev_Gv,
80	BS3CG1ENC_MODRM_Wsd_Vsd,
81	BS3CG1ENC_MODRM_Wps_Vps,
82
83	BS3CG1ENC_MODRM_Gb_Eb,
84	BS3CG1ENC_MODRM_Gv_Ev,
85	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
86
87	BS3CG1ENC_FIXED,
88	BS3CG1ENC_FIXED_AL_Ib,
89	BS3CG1ENC_FIXED_rAX_Iz,
90
91	BS3CG1ENC_END
92	} BS3CG1ENC;
93
94
95	/**
96	* Prefix sensitivitiy kind.
97	*/
98	typedef enum BS3CGPFXKIND
99	{
100	BS3CGPFXKIND_INVALID = 0,
101
102	BS3CGPFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
103	BS3CGPFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
104	BS3CGPFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
105	BS3CGPFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
106
107	/** @todo more work to be done here... */
108	BS3CGPFXKIND_MODRM,
109	BS3CGPFXKIND_MODRM_NO_OP_SIZES,
110
111	BS3CGPFXKIND_END
112	} BS3CGPFXKIND;
113
114	/**
115	* CPU selection or CPU ID.
116	*/
117	typedef enum BS3CG1CPU
118	{
119	/** Works with an CPU. */
120	BS3CG1CPU_ANY = 0,
121	BS3CG1CPU_GE_80186,
122	BS3CG1CPU_GE_80286,
123	BS3CG1CPU_GE_80386,
124	BS3CG1CPU_GE_80486,
125	BS3CG1CPU_GE_Pentium,
126
127	BS3CG1CPU_SSE,
128	BS3CG1CPU_SSE2,
129	BS3CG1CPU_SSE3,
130	BS3CG1CPU_AVX,
131	BS3CG1CPU_AVX2,
132	BS3CG1CPU_END
133	} BS3CG1CPU;
134
135	/**
136	* Generated instruction info.
137	*/
138	typedef struct BS3CG1INSTR
139	{
140	/** The opcode size. */
141	uint32_t cbOpcodes : 2;
142	/** The number of operands. */
143	uint32_t cOperands : 2;
144	/** The length of the mnemonic. */
145	uint32_t cchMnemonic : 3;
146	/** Whether to advance the mnemonic array pointer. */
147	uint32_t fAdvanceMnemonic : 1;
148	/** Offset into g_abBs3Cg1Tests of the first test. */
149	uint32_t offTests : 23;
150	/** BS3CG1ENC values. */
151	uint32_t enmEncoding : 10;
152	/** BS3CGPFXKIND values. */
153	uint32_t enmPrefixKind : 4;
154	/** CPU test / CPU ID bit test (BS3CG1CPU). */
155	uint32_t enmCpuTest : 6;
156	/** Currently unused bits. */
157	uint32_t uUnused : 12;
158	/** BS3CG1INSTR_F_XXX. */
159	uint32_t fFlags;
160	} BS3CG1INSTR;
161	AssertCompileSize(BS3CG1INSTR, 12);
162	/** Pointer to a const instruction. */
163	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
164
165
166	/** @name BS3CG1INSTR_F_XXX
167	* @{ */
168	/** Defaults to SS rather than DS. */
169	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
170	/** Invalid instruction in 64-bit mode. */
171	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
172	/** @} */
173
174
175	/**
176	* Test header.
177	*/
178	typedef struct BS3CG1TESTHDR
179	{
180	/** The size of the selector program in bytes.
181	* This is also the offset of the input context modification program. */
182	uint32_t cbSelector : 8;
183	/** The size of the input context modification program in bytes.
184	* This immediately follows the selector program. */
185	uint32_t cbInput : 12;
186	/** The size of the output context modification program in bytes.
187	* This immediately follows the input context modification program. The
188	* program takes the result of the input program as starting point. */
189	uint32_t cbOutput : 11;
190	/** Indicates whether this is the last test or not. */
191	uint32_t fLast : 1;
192	} BS3CG1TESTHDR;
193	AssertCompileSize(BS3CG1TESTHDR, 4);
194	/** Pointer to a const test header. */
195	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
196
197	/** @name Opcode format for the BS3CG1 context modifier.
198	*
199	* Used by both the input and output context programs.
200	*
201	* The most common operations are encoded as a single byte opcode followed by
202	* one or more immediate bytes with data.
203	*
204	* @{ */
205	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
206	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
207	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
208	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
209	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
210	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
211	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
212	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
213	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
214
215	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
216	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
217	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
218	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
219	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
220
221	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
222
223	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
224	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
225	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
226	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
227	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
228	/** @} */
229
230	/**
231	* Escaped destination values
232	*
233	* These are just uppercased versions of TestInOut.kdFields, where dots are
234	* replaced by underscores.
235	*/
236	typedef enum BS3CG1DST
237	{
238	BS3CG1DST_INVALID = 0,
239	/* Operands. */
240	BS3CG1DST_OP1,
241	BS3CG1DST_OP2,
242	BS3CG1DST_OP3,
243	BS3CG1DST_OP4,
244	/* Flags. */
245	BS3CG1DST_EFL,
246	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
247	/* 8-bit GPRs. */
248	BS3CG1DST_AL,
249	BS3CG1DST_CL,
250	BS3CG1DST_DL,
251	BS3CG1DST_BL,
252	BS3CG1DST_AH,
253	BS3CG1DST_CH,
254	BS3CG1DST_DH,
255	BS3CG1DST_BH,
256	BS3CG1DST_SPL,
257	BS3CG1DST_BPL,
258	BS3CG1DST_SIL,
259	BS3CG1DST_DIL,
260	BS3CG1DST_R8L,
261	BS3CG1DST_R9L,
262	BS3CG1DST_R10L,
263	BS3CG1DST_R11L,
264	BS3CG1DST_R12L,
265	BS3CG1DST_R13L,
266	BS3CG1DST_R14L,
267	BS3CG1DST_R15L,
268	/* 16-bit GPRs. */
269	BS3CG1DST_AX,
270	BS3CG1DST_CX,
271	BS3CG1DST_DX,
272	BS3CG1DST_BX,
273	BS3CG1DST_SP,
274	BS3CG1DST_BP,
275	BS3CG1DST_SI,
276	BS3CG1DST_DI,
277	BS3CG1DST_R8W,
278	BS3CG1DST_R9W,
279	BS3CG1DST_R10W,
280	BS3CG1DST_R11W,
281	BS3CG1DST_R12W,
282	BS3CG1DST_R13W,
283	BS3CG1DST_R14W,
284	BS3CG1DST_R15W,
285	/* 32-bit GPRs. */
286	BS3CG1DST_EAX,
287	BS3CG1DST_ECX,
288	BS3CG1DST_EDX,
289	BS3CG1DST_EBX,
290	BS3CG1DST_ESP,
291	BS3CG1DST_EBP,
292	BS3CG1DST_ESI,
293	BS3CG1DST_EDI,
294	BS3CG1DST_R8D,
295	BS3CG1DST_R9D,
296	BS3CG1DST_R10D,
297	BS3CG1DST_R11D,
298	BS3CG1DST_R12D,
299	BS3CG1DST_R13D,
300	BS3CG1DST_R14D,
301	BS3CG1DST_R15D,
302	/* 64-bit GPRs. */
303	BS3CG1DST_RAX,
304	BS3CG1DST_RCX,
305	BS3CG1DST_RDX,
306	BS3CG1DST_RBX,
307	BS3CG1DST_RSP,
308	BS3CG1DST_RBP,
309	BS3CG1DST_RSI,
310	BS3CG1DST_RDI,
311	BS3CG1DST_R8,
312	BS3CG1DST_R9,
313	BS3CG1DST_R10,
314	BS3CG1DST_R11,
315	BS3CG1DST_R12,
316	BS3CG1DST_R13,
317	BS3CG1DST_R14,
318	BS3CG1DST_R15,
319	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
320	BS3CG1DST_OZ_RAX,
321	BS3CG1DST_OZ_RCX,
322	BS3CG1DST_OZ_RDX,
323	BS3CG1DST_OZ_RBX,
324	BS3CG1DST_OZ_RSP,
325	BS3CG1DST_OZ_RBP,
326	BS3CG1DST_OZ_RSI,
327	BS3CG1DST_OZ_RDI,
328	BS3CG1DST_OZ_R8,
329	BS3CG1DST_OZ_R9,
330	BS3CG1DST_OZ_R10,
331	BS3CG1DST_OZ_R11,
332	BS3CG1DST_OZ_R12,
333	BS3CG1DST_OZ_R13,
334	BS3CG1DST_OZ_R14,
335	BS3CG1DST_OZ_R15,
336
337	/* FPU registers. */
338	BS3CG1DST_FPU_FIRST,
339	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
340	BS3CG1DST_FSW,
341	BS3CG1DST_FTW,
342	BS3CG1DST_FOP,
343	BS3CG1DST_FPUIP,
344	BS3CG1DST_FPUCS,
345	BS3CG1DST_FPUDP,
346	BS3CG1DST_FPUDS,
347	BS3CG1DST_MXCSR,
348	BS3CG1DST_MXCSR_MASK,
349	BS3CG1DST_ST0,
350	BS3CG1DST_ST1,
351	BS3CG1DST_ST2,
352	BS3CG1DST_ST3,
353	BS3CG1DST_ST4,
354	BS3CG1DST_ST5,
355	BS3CG1DST_ST6,
356	BS3CG1DST_ST7,
357	/* MMX registers. */
358	BS3CG1DST_MM0,
359	BS3CG1DST_MM1,
360	BS3CG1DST_MM2,
361	BS3CG1DST_MM3,
362	BS3CG1DST_MM4,
363	BS3CG1DST_MM5,
364	BS3CG1DST_MM6,
365	BS3CG1DST_MM7,
366	/* SSE registers. */
367	BS3CG1DST_XMM0,
368	BS3CG1DST_XMM1,
369	BS3CG1DST_XMM2,
370	BS3CG1DST_XMM3,
371	BS3CG1DST_XMM4,
372	BS3CG1DST_XMM5,
373	BS3CG1DST_XMM6,
374	BS3CG1DST_XMM7,
375	BS3CG1DST_XMM8,
376	BS3CG1DST_XMM9,
377	BS3CG1DST_XMM10,
378	BS3CG1DST_XMM11,
379	BS3CG1DST_XMM12,
380	BS3CG1DST_XMM13,
381	BS3CG1DST_XMM14,
382	BS3CG1DST_XMM15,
383	BS3CG1DST_XMM0_LO,
384	BS3CG1DST_XMM1_LO,
385	BS3CG1DST_XMM2_LO,
386	BS3CG1DST_XMM3_LO,
387	BS3CG1DST_XMM4_LO,
388	BS3CG1DST_XMM5_LO,
389	BS3CG1DST_XMM6_LO,
390	BS3CG1DST_XMM7_LO,
391	BS3CG1DST_XMM8_LO,
392	BS3CG1DST_XMM9_LO,
393	BS3CG1DST_XMM10_LO,
394	BS3CG1DST_XMM11_LO,
395	BS3CG1DST_XMM12_LO,
396	BS3CG1DST_XMM13_LO,
397	BS3CG1DST_XMM14_LO,
398	BS3CG1DST_XMM15_LO,
399	BS3CG1DST_XMM0_HI,
400	BS3CG1DST_XMM1_HI,
401	BS3CG1DST_XMM2_HI,
402	BS3CG1DST_XMM3_HI,
403	BS3CG1DST_XMM4_HI,
404	BS3CG1DST_XMM5_HI,
405	BS3CG1DST_XMM6_HI,
406	BS3CG1DST_XMM7_HI,
407	BS3CG1DST_XMM8_HI,
408	BS3CG1DST_XMM9_HI,
409	BS3CG1DST_XMM10_HI,
410	BS3CG1DST_XMM11_HI,
411	BS3CG1DST_XMM12_HI,
412	BS3CG1DST_XMM13_HI,
413	BS3CG1DST_XMM14_HI,
414	BS3CG1DST_XMM15_HI,
415	/* AVX registers. */
416	BS3CG1DST_YMM0,
417	BS3CG1DST_YMM1,
418	BS3CG1DST_YMM2,
419	BS3CG1DST_YMM3,
420	BS3CG1DST_YMM4,
421	BS3CG1DST_YMM5,
422	BS3CG1DST_YMM6,
423	BS3CG1DST_YMM7,
424	BS3CG1DST_YMM8,
425	BS3CG1DST_YMM9,
426	BS3CG1DST_YMM10,
427	BS3CG1DST_YMM11,
428	BS3CG1DST_YMM12,
429	BS3CG1DST_YMM13,
430	BS3CG1DST_YMM14,
431	BS3CG1DST_YMM15,
432
433	/* Special fields: */
434	BS3CG1DST_SPECIAL_START,
435	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
436
437	BS3CG1DST_END
438	} BS3CG1DST;
439
440	/** @name Selector opcode definitions.
441	*
442	* Selector programs are very simple, they are zero or more predicate tests
443	* that are ANDed together. If a predicate test fails, the test is skipped.
444	*
445	* One instruction is encoded as byte, where the first bit indicates what kind
446	* of test and the 7 remaining bits indicates which predicate to check.
447	*
448	* @{ */
449	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
450	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
451	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
452	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
453	/** @} */
454
455	/**
456	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
457	*/
458	typedef enum BS3CG1PRED
459	{
460	BS3CG1PRED_INVALID = 0,
461
462	/* Operand size. */
463	BS3CG1PRED_SIZE_O16,
464	BS3CG1PRED_SIZE_O32,
465	BS3CG1PRED_SIZE_O64,
466	/* Execution ring. */
467	BS3CG1PRED_RING_0,
468	BS3CG1PRED_RING_1,
469	BS3CG1PRED_RING_2,
470	BS3CG1PRED_RING_3,
471	BS3CG1PRED_RING_0_THRU_2,
472	BS3CG1PRED_RING_1_THRU_3,
473	/* Basic code mode. */
474	BS3CG1PRED_CODE_64BIT,
475	BS3CG1PRED_CODE_32BIT,
476	BS3CG1PRED_CODE_16BIT,
477	/* CPU modes. */
478	BS3CG1PRED_MODE_REAL,
479	BS3CG1PRED_MODE_PROT,
480	BS3CG1PRED_MODE_LONG,
481	BS3CG1PRED_MODE_V86,
482	BS3CG1PRED_MODE_SMM,
483	BS3CG1PRED_MODE_VMX,
484	BS3CG1PRED_MODE_SVM,
485	/* Paging on/off */
486	BS3CG1PRED_PAGING_ON,
487	BS3CG1PRED_PAGING_OFF,
488
489	BS3CG1PRED_END
490	} BS3CG1PRED;
491
492
493	/** The test instructions (generated). */
494	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
495	/** The number of test instructions (generated). */
496	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
497	/** The mnemonics (generated).
498	* Variable length sequence of mnemonics that runs in parallel to
499	* g_aBs3Cg1Instructions. */
500	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
501	/** The opcodes (generated).
502	* Variable length sequence of opcode bytes that runs in parallel to
503	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
504	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
505	/** The operands (generated).
506	* Variable length sequence of opcode values (BS3CG1OP) that runs in
507	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
508	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
509	/** The test data that BS3CG1INSTR.
510	* In order to simplify generating these, we use a byte array. */
511	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
512
513
514	#endif
515

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