bs3-cpu-generated-1.h@ 66303

Last change on this file since 66303 was 66303, checked in by vboxsync, 8 years ago
IEM: Implemented movupd Wpd,Vpd (66 0f 11).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 14.9 KB

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1	/* $Id: bs3-cpu-generated-1.h 66303 2017-03-28 14:22:58Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wsd,
47	BS3CG1OP_Wps,
48	BS3CG1OP_Wpd,
49
50	BS3CG1OP_Gb,
51	BS3CG1OP_Gv,
52	BS3CG1OP_Vsd,
53	BS3CG1OP_Vps,
54	BS3CG1OP_Vpd,
55
56	BS3CG1OP_Ib,
57	BS3CG1OP_Iz,
58
59	BS3CG1OP_AL,
60	BS3CG1OP_rAX,
61
62	BS3CG1OP_Ma,
63
64	BS3CG1OP_END
65	} BS3CG1OP;
66	/** Pointer to a const operand enum. */
67	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
68
69
70	/**
71	* Instruction encoding format.
72	*
73	* This duplicates some of the info in the operand array, however it makes it
74	* easier to figure out encoding variations.
75	*/
76	typedef enum BS3CG1ENC
77	{
78	BS3CG1ENC_INVALID = 0,
79
80	BS3CG1ENC_MODRM_Eb_Gb,
81	BS3CG1ENC_MODRM_Ev_Gv,
82	BS3CG1ENC_MODRM_Wsd_Vsd,
83	BS3CG1ENC_MODRM_Wps_Vps,
84	BS3CG1ENC_MODRM_Wpd_Vpd,
85
86	BS3CG1ENC_MODRM_Gb_Eb,
87	BS3CG1ENC_MODRM_Gv_Ev,
88	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
89
90	BS3CG1ENC_FIXED,
91	BS3CG1ENC_FIXED_AL_Ib,
92	BS3CG1ENC_FIXED_rAX_Iz,
93
94	BS3CG1ENC_END
95	} BS3CG1ENC;
96
97
98	/**
99	* Prefix sensitivitiy kind.
100	*/
101	typedef enum BS3CG1PFXKIND
102	{
103	BS3CG1PFXKIND_INVALID = 0,
104
105	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
106	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
107	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
108	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
109
110	/** @todo more work to be done here... */
111	BS3CG1PFXKIND_MODRM,
112	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
113
114	BS3CG1PFXKIND_END
115	} BS3CG1PFXKIND;
116
117	/**
118	* CPU selection or CPU ID.
119	*/
120	typedef enum BS3CG1CPU
121	{
122	/** Works with an CPU. */
123	BS3CG1CPU_ANY = 0,
124	BS3CG1CPU_GE_80186,
125	BS3CG1CPU_GE_80286,
126	BS3CG1CPU_GE_80386,
127	BS3CG1CPU_GE_80486,
128	BS3CG1CPU_GE_Pentium,
129
130	BS3CG1CPU_SSE,
131	BS3CG1CPU_SSE2,
132	BS3CG1CPU_SSE3,
133	BS3CG1CPU_AVX,
134	BS3CG1CPU_AVX2,
135	BS3CG1CPU_END
136	} BS3CG1CPU;
137
138
139	/**
140	* SSE & AVX exception types.
141	*/
142	typedef enum BS3CG1XCPTTYPE
143	{
144	BS3CG1XCPTTYPE_NONE = 0,
145	/* SSE: */
146	BS3CG1XCPTTYPE_1,
147	BS3CG1XCPTTYPE_2,
148	BS3CG1XCPTTYPE_3,
149	BS3CG1XCPTTYPE_4,
150	BS3CG1XCPTTYPE_4UA,
151	BS3CG1XCPTTYPE_5,
152	BS3CG1XCPTTYPE_6,
153	BS3CG1XCPTTYPE_7,
154	BS3CG1XCPTTYPE_8,
155	BS3CG1XCPTTYPE_11,
156	BS3CG1XCPTTYPE_12,
157	/* EVEX: */
158	BS3CG1XCPTTYPE_E1,
159	BS3CG1XCPTTYPE_E1NF,
160	BS3CG1XCPTTYPE_E2,
161	BS3CG1XCPTTYPE_E3,
162	BS3CG1XCPTTYPE_E3NF,
163	BS3CG1XCPTTYPE_E4,
164	BS3CG1XCPTTYPE_E4NF,
165	BS3CG1XCPTTYPE_E5,
166	BS3CG1XCPTTYPE_E5NF,
167	BS3CG1XCPTTYPE_E6,
168	BS3CG1XCPTTYPE_E6NF,
169	BS3CG1XCPTTYPE_E7NF,
170	BS3CG1XCPTTYPE_E9,
171	BS3CG1XCPTTYPE_E9NF,
172	BS3CG1XCPTTYPE_E10,
173	BS3CG1XCPTTYPE_E11,
174	BS3CG1XCPTTYPE_E12,
175	BS3CG1XCPTTYPE_E12NF,
176	BS3CG1XCPTTYPE_END
177	} BS3CG1XCPTTYPE;
178	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
179
180
181	/**
182	* Generated instruction info.
183	*/
184	typedef struct BS3CG1INSTR
185	{
186	/** The opcode size. */
187	uint32_t cbOpcodes : 2;
188	/** The number of operands. */
189	uint32_t cOperands : 2;
190	/** The length of the mnemonic. */
191	uint32_t cchMnemonic : 3;
192	/** Whether to advance the mnemonic array pointer. */
193	uint32_t fAdvanceMnemonic : 1;
194	/** Offset into g_abBs3Cg1Tests of the first test. */
195	uint32_t offTests : 23;
196	/** BS3CG1ENC values. */
197	uint32_t enmEncoding : 10;
198	/** BS3CG1PFXKIND values. */
199	uint32_t enmPrefixKind : 4;
200	/** CPU test / CPU ID bit test (BS3CG1CPU). */
201	uint32_t enmCpuTest : 6;
202	/** Exception type (BS3CG1XCPTTYPE) */
203	uint32_t enmXcptType : 5;
204	/** Currently unused bits. */
205	uint32_t uUnused : 7;
206	/** BS3CG1INSTR_F_XXX. */
207	uint32_t fFlags;
208	} BS3CG1INSTR;
209	AssertCompileSize(BS3CG1INSTR, 12);
210	/** Pointer to a const instruction. */
211	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
212
213
214	/** @name BS3CG1INSTR_F_XXX
215	* @{ */
216	/** Defaults to SS rather than DS. */
217	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
218	/** Invalid instruction in 64-bit mode. */
219	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
220	/** @} */
221
222
223	/**
224	* Test header.
225	*/
226	typedef struct BS3CG1TESTHDR
227	{
228	/** The size of the selector program in bytes.
229	* This is also the offset of the input context modification program. */
230	uint32_t cbSelector : 8;
231	/** The size of the input context modification program in bytes.
232	* This immediately follows the selector program. */
233	uint32_t cbInput : 12;
234	/** The size of the output context modification program in bytes.
235	* This immediately follows the input context modification program. The
236	* program takes the result of the input program as starting point. */
237	uint32_t cbOutput : 11;
238	/** Indicates whether this is the last test or not. */
239	uint32_t fLast : 1;
240	} BS3CG1TESTHDR;
241	AssertCompileSize(BS3CG1TESTHDR, 4);
242	/** Pointer to a const test header. */
243	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
244
245	/** @name Opcode format for the BS3CG1 context modifier.
246	*
247	* Used by both the input and output context programs.
248	*
249	* The most common operations are encoded as a single byte opcode followed by
250	* one or more immediate bytes with data.
251	*
252	* @{ */
253	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
254	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
255	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
256	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
257	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
258	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
259	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
260	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
261	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
262
263	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
264	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
265	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
266	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
267	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
268
269	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
270
271	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
272	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
273	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
274	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
275	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
276	/** @} */
277
278	/**
279	* Escaped destination values
280	*
281	* These are just uppercased versions of TestInOut.kdFields, where dots are
282	* replaced by underscores.
283	*/
284	typedef enum BS3CG1DST
285	{
286	BS3CG1DST_INVALID = 0,
287	/* Operands. */
288	BS3CG1DST_OP1,
289	BS3CG1DST_OP2,
290	BS3CG1DST_OP3,
291	BS3CG1DST_OP4,
292	/* Flags. */
293	BS3CG1DST_EFL,
294	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
295	/* 8-bit GPRs. */
296	BS3CG1DST_AL,
297	BS3CG1DST_CL,
298	BS3CG1DST_DL,
299	BS3CG1DST_BL,
300	BS3CG1DST_AH,
301	BS3CG1DST_CH,
302	BS3CG1DST_DH,
303	BS3CG1DST_BH,
304	BS3CG1DST_SPL,
305	BS3CG1DST_BPL,
306	BS3CG1DST_SIL,
307	BS3CG1DST_DIL,
308	BS3CG1DST_R8L,
309	BS3CG1DST_R9L,
310	BS3CG1DST_R10L,
311	BS3CG1DST_R11L,
312	BS3CG1DST_R12L,
313	BS3CG1DST_R13L,
314	BS3CG1DST_R14L,
315	BS3CG1DST_R15L,
316	/* 16-bit GPRs. */
317	BS3CG1DST_AX,
318	BS3CG1DST_CX,
319	BS3CG1DST_DX,
320	BS3CG1DST_BX,
321	BS3CG1DST_SP,
322	BS3CG1DST_BP,
323	BS3CG1DST_SI,
324	BS3CG1DST_DI,
325	BS3CG1DST_R8W,
326	BS3CG1DST_R9W,
327	BS3CG1DST_R10W,
328	BS3CG1DST_R11W,
329	BS3CG1DST_R12W,
330	BS3CG1DST_R13W,
331	BS3CG1DST_R14W,
332	BS3CG1DST_R15W,
333	/* 32-bit GPRs. */
334	BS3CG1DST_EAX,
335	BS3CG1DST_ECX,
336	BS3CG1DST_EDX,
337	BS3CG1DST_EBX,
338	BS3CG1DST_ESP,
339	BS3CG1DST_EBP,
340	BS3CG1DST_ESI,
341	BS3CG1DST_EDI,
342	BS3CG1DST_R8D,
343	BS3CG1DST_R9D,
344	BS3CG1DST_R10D,
345	BS3CG1DST_R11D,
346	BS3CG1DST_R12D,
347	BS3CG1DST_R13D,
348	BS3CG1DST_R14D,
349	BS3CG1DST_R15D,
350	/* 64-bit GPRs. */
351	BS3CG1DST_RAX,
352	BS3CG1DST_RCX,
353	BS3CG1DST_RDX,
354	BS3CG1DST_RBX,
355	BS3CG1DST_RSP,
356	BS3CG1DST_RBP,
357	BS3CG1DST_RSI,
358	BS3CG1DST_RDI,
359	BS3CG1DST_R8,
360	BS3CG1DST_R9,
361	BS3CG1DST_R10,
362	BS3CG1DST_R11,
363	BS3CG1DST_R12,
364	BS3CG1DST_R13,
365	BS3CG1DST_R14,
366	BS3CG1DST_R15,
367	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
368	BS3CG1DST_OZ_RAX,
369	BS3CG1DST_OZ_RCX,
370	BS3CG1DST_OZ_RDX,
371	BS3CG1DST_OZ_RBX,
372	BS3CG1DST_OZ_RSP,
373	BS3CG1DST_OZ_RBP,
374	BS3CG1DST_OZ_RSI,
375	BS3CG1DST_OZ_RDI,
376	BS3CG1DST_OZ_R8,
377	BS3CG1DST_OZ_R9,
378	BS3CG1DST_OZ_R10,
379	BS3CG1DST_OZ_R11,
380	BS3CG1DST_OZ_R12,
381	BS3CG1DST_OZ_R13,
382	BS3CG1DST_OZ_R14,
383	BS3CG1DST_OZ_R15,
384
385	/* FPU registers. */
386	BS3CG1DST_FPU_FIRST,
387	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
388	BS3CG1DST_FSW,
389	BS3CG1DST_FTW,
390	BS3CG1DST_FOP,
391	BS3CG1DST_FPUIP,
392	BS3CG1DST_FPUCS,
393	BS3CG1DST_FPUDP,
394	BS3CG1DST_FPUDS,
395	BS3CG1DST_MXCSR,
396	BS3CG1DST_MXCSR_MASK,
397	BS3CG1DST_ST0,
398	BS3CG1DST_ST1,
399	BS3CG1DST_ST2,
400	BS3CG1DST_ST3,
401	BS3CG1DST_ST4,
402	BS3CG1DST_ST5,
403	BS3CG1DST_ST6,
404	BS3CG1DST_ST7,
405	/* MMX registers. */
406	BS3CG1DST_MM0,
407	BS3CG1DST_MM1,
408	BS3CG1DST_MM2,
409	BS3CG1DST_MM3,
410	BS3CG1DST_MM4,
411	BS3CG1DST_MM5,
412	BS3CG1DST_MM6,
413	BS3CG1DST_MM7,
414	/* SSE registers. */
415	BS3CG1DST_XMM0,
416	BS3CG1DST_XMM1,
417	BS3CG1DST_XMM2,
418	BS3CG1DST_XMM3,
419	BS3CG1DST_XMM4,
420	BS3CG1DST_XMM5,
421	BS3CG1DST_XMM6,
422	BS3CG1DST_XMM7,
423	BS3CG1DST_XMM8,
424	BS3CG1DST_XMM9,
425	BS3CG1DST_XMM10,
426	BS3CG1DST_XMM11,
427	BS3CG1DST_XMM12,
428	BS3CG1DST_XMM13,
429	BS3CG1DST_XMM14,
430	BS3CG1DST_XMM15,
431	BS3CG1DST_XMM0_LO,
432	BS3CG1DST_XMM1_LO,
433	BS3CG1DST_XMM2_LO,
434	BS3CG1DST_XMM3_LO,
435	BS3CG1DST_XMM4_LO,
436	BS3CG1DST_XMM5_LO,
437	BS3CG1DST_XMM6_LO,
438	BS3CG1DST_XMM7_LO,
439	BS3CG1DST_XMM8_LO,
440	BS3CG1DST_XMM9_LO,
441	BS3CG1DST_XMM10_LO,
442	BS3CG1DST_XMM11_LO,
443	BS3CG1DST_XMM12_LO,
444	BS3CG1DST_XMM13_LO,
445	BS3CG1DST_XMM14_LO,
446	BS3CG1DST_XMM15_LO,
447	BS3CG1DST_XMM0_HI,
448	BS3CG1DST_XMM1_HI,
449	BS3CG1DST_XMM2_HI,
450	BS3CG1DST_XMM3_HI,
451	BS3CG1DST_XMM4_HI,
452	BS3CG1DST_XMM5_HI,
453	BS3CG1DST_XMM6_HI,
454	BS3CG1DST_XMM7_HI,
455	BS3CG1DST_XMM8_HI,
456	BS3CG1DST_XMM9_HI,
457	BS3CG1DST_XMM10_HI,
458	BS3CG1DST_XMM11_HI,
459	BS3CG1DST_XMM12_HI,
460	BS3CG1DST_XMM13_HI,
461	BS3CG1DST_XMM14_HI,
462	BS3CG1DST_XMM15_HI,
463	/* AVX registers. */
464	BS3CG1DST_YMM0,
465	BS3CG1DST_YMM1,
466	BS3CG1DST_YMM2,
467	BS3CG1DST_YMM3,
468	BS3CG1DST_YMM4,
469	BS3CG1DST_YMM5,
470	BS3CG1DST_YMM6,
471	BS3CG1DST_YMM7,
472	BS3CG1DST_YMM8,
473	BS3CG1DST_YMM9,
474	BS3CG1DST_YMM10,
475	BS3CG1DST_YMM11,
476	BS3CG1DST_YMM12,
477	BS3CG1DST_YMM13,
478	BS3CG1DST_YMM14,
479	BS3CG1DST_YMM15,
480
481	/* Special fields: */
482	BS3CG1DST_SPECIAL_START,
483	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
484
485	BS3CG1DST_END
486	} BS3CG1DST;
487
488	/** @name Selector opcode definitions.
489	*
490	* Selector programs are very simple, they are zero or more predicate tests
491	* that are ANDed together. If a predicate test fails, the test is skipped.
492	*
493	* One instruction is encoded as byte, where the first bit indicates what kind
494	* of test and the 7 remaining bits indicates which predicate to check.
495	*
496	* @{ */
497	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
498	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
499	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
500	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
501	/** @} */
502
503	/**
504	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
505	*/
506	typedef enum BS3CG1PRED
507	{
508	BS3CG1PRED_INVALID = 0,
509
510	/* Operand size. */
511	BS3CG1PRED_SIZE_O16,
512	BS3CG1PRED_SIZE_O32,
513	BS3CG1PRED_SIZE_O64,
514	/* Execution ring. */
515	BS3CG1PRED_RING_0,
516	BS3CG1PRED_RING_1,
517	BS3CG1PRED_RING_2,
518	BS3CG1PRED_RING_3,
519	BS3CG1PRED_RING_0_THRU_2,
520	BS3CG1PRED_RING_1_THRU_3,
521	/* Basic code mode. */
522	BS3CG1PRED_CODE_64BIT,
523	BS3CG1PRED_CODE_32BIT,
524	BS3CG1PRED_CODE_16BIT,
525	/* CPU modes. */
526	BS3CG1PRED_MODE_REAL,
527	BS3CG1PRED_MODE_PROT,
528	BS3CG1PRED_MODE_LONG,
529	BS3CG1PRED_MODE_V86,
530	BS3CG1PRED_MODE_SMM,
531	BS3CG1PRED_MODE_VMX,
532	BS3CG1PRED_MODE_SVM,
533	/* Paging on/off */
534	BS3CG1PRED_PAGING_ON,
535	BS3CG1PRED_PAGING_OFF,
536
537	BS3CG1PRED_END
538	} BS3CG1PRED;
539
540
541	/** The test instructions (generated). */
542	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
543	/** The number of test instructions (generated). */
544	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
545	/** The mnemonics (generated).
546	* Variable length sequence of mnemonics that runs in parallel to
547	* g_aBs3Cg1Instructions. */
548	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
549	/** The opcodes (generated).
550	* Variable length sequence of opcode bytes that runs in parallel to
551	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
552	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
553	/** The operands (generated).
554	* Variable length sequence of opcode values (BS3CG1OP) that runs in
555	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
556	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
557	/** The test data that BS3CG1INSTR.
558	* In order to simplify generating these, we use a byte array. */
559	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
560
561
562	#endif
563

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66303

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