bs3-cpu-generated-1.h@ 66315

Last change on this file since 66315 was 66315, checked in by vboxsync, 8 years ago
IEM: Implemented movsldup Vdq,Wdq (f3 0f 12)
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1	/* $Id: bs3-cpu-generated-1.h 66315 2017-03-28 21:34:58Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51
52	BS3CG1OP_Gb,
53	BS3CG1OP_Gv,
54	BS3CG1OP_Uq,
55	BS3CG1OP_UqHi,
56	BS3CG1OP_Vss,
57	BS3CG1OP_Vsd,
58	BS3CG1OP_Vps,
59	BS3CG1OP_Vpd,
60	BS3CG1OP_Vq,
61	BS3CG1OP_Vdq,
62
63	BS3CG1OP_Ib,
64	BS3CG1OP_Iz,
65
66	BS3CG1OP_AL,
67	BS3CG1OP_rAX,
68
69	BS3CG1OP_Ma,
70	BS3CG1OP_Mq,
71
72	BS3CG1OP_END
73	} BS3CG1OP;
74	/** Pointer to a const operand enum. */
75	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
76
77
78	/**
79	* Instruction encoding format.
80	*
81	* This duplicates some of the info in the operand array, however it makes it
82	* easier to figure out encoding variations.
83	*/
84	typedef enum BS3CG1ENC
85	{
86	BS3CG1ENC_INVALID = 0,
87
88	BS3CG1ENC_MODRM_Eb_Gb,
89	BS3CG1ENC_MODRM_Ev_Gv,
90	BS3CG1ENC_MODRM_Wss_Vss,
91	BS3CG1ENC_MODRM_Wsd_Vsd,
92	BS3CG1ENC_MODRM_Wps_Vps,
93	BS3CG1ENC_MODRM_Wpd_Vpd,
94
95	BS3CG1ENC_MODRM_Gb_Eb,
96	BS3CG1ENC_MODRM_Gv_Ev,
97	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
98	BS3CG1ENC_MODRM_Vq_UqHi,
99	BS3CG1ENC_MODRM_Vq_Mq,
100	BS3CG1ENC_MODRM_Vdq_Wdq,
101
102	BS3CG1ENC_FIXED,
103	BS3CG1ENC_FIXED_AL_Ib,
104	BS3CG1ENC_FIXED_rAX_Iz,
105
106	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
107	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
108
109	BS3CG1ENC_END
110	} BS3CG1ENC;
111
112
113	/**
114	* Prefix sensitivitiy kind.
115	*/
116	typedef enum BS3CG1PFXKIND
117	{
118	BS3CG1PFXKIND_INVALID = 0,
119
120	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
121	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
122	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
123	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
124
125	/** @todo more work to be done here... */
126	BS3CG1PFXKIND_MODRM,
127	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
128
129	BS3CG1PFXKIND_END
130	} BS3CG1PFXKIND;
131
132	/**
133	* CPU selection or CPU ID.
134	*/
135	typedef enum BS3CG1CPU
136	{
137	/** Works with an CPU. */
138	BS3CG1CPU_ANY = 0,
139	BS3CG1CPU_GE_80186,
140	BS3CG1CPU_GE_80286,
141	BS3CG1CPU_GE_80386,
142	BS3CG1CPU_GE_80486,
143	BS3CG1CPU_GE_Pentium,
144
145	BS3CG1CPU_SSE,
146	BS3CG1CPU_SSE2,
147	BS3CG1CPU_SSE3,
148	BS3CG1CPU_AVX,
149	BS3CG1CPU_AVX2,
150	BS3CG1CPU_END
151	} BS3CG1CPU;
152
153
154	/**
155	* SSE & AVX exception types.
156	*/
157	typedef enum BS3CG1XCPTTYPE
158	{
159	BS3CG1XCPTTYPE_NONE = 0,
160	/* SSE: */
161	BS3CG1XCPTTYPE_1,
162	BS3CG1XCPTTYPE_2,
163	BS3CG1XCPTTYPE_3,
164	BS3CG1XCPTTYPE_4,
165	BS3CG1XCPTTYPE_4UA,
166	BS3CG1XCPTTYPE_5,
167	BS3CG1XCPTTYPE_6,
168	BS3CG1XCPTTYPE_7,
169	BS3CG1XCPTTYPE_8,
170	BS3CG1XCPTTYPE_11,
171	BS3CG1XCPTTYPE_12,
172	/* EVEX: */
173	BS3CG1XCPTTYPE_E1,
174	BS3CG1XCPTTYPE_E1NF,
175	BS3CG1XCPTTYPE_E2,
176	BS3CG1XCPTTYPE_E3,
177	BS3CG1XCPTTYPE_E3NF,
178	BS3CG1XCPTTYPE_E4,
179	BS3CG1XCPTTYPE_E4NF,
180	BS3CG1XCPTTYPE_E5,
181	BS3CG1XCPTTYPE_E5NF,
182	BS3CG1XCPTTYPE_E6,
183	BS3CG1XCPTTYPE_E6NF,
184	BS3CG1XCPTTYPE_E7NF,
185	BS3CG1XCPTTYPE_E9,
186	BS3CG1XCPTTYPE_E9NF,
187	BS3CG1XCPTTYPE_E10,
188	BS3CG1XCPTTYPE_E11,
189	BS3CG1XCPTTYPE_E12,
190	BS3CG1XCPTTYPE_E12NF,
191	BS3CG1XCPTTYPE_END
192	} BS3CG1XCPTTYPE;
193	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
194
195
196	/**
197	* Generated instruction info.
198	*/
199	typedef struct BS3CG1INSTR
200	{
201	/** The opcode size. */
202	uint32_t cbOpcodes : 2;
203	/** The number of operands. */
204	uint32_t cOperands : 2;
205	/** The length of the mnemonic. */
206	uint32_t cchMnemonic : 4;
207	/** Whether to advance the mnemonic array pointer. */
208	uint32_t fAdvanceMnemonic : 1;
209	/** Offset into g_abBs3Cg1Tests of the first test. */
210	uint32_t offTests : 23;
211	/** BS3CG1ENC values. */
212	uint32_t enmEncoding : 10;
213	/** BS3CG1PFXKIND values. */
214	uint32_t enmPrefixKind : 4;
215	/** CPU test / CPU ID bit test (BS3CG1CPU). */
216	uint32_t enmCpuTest : 6;
217	/** Exception type (BS3CG1XCPTTYPE) */
218	uint32_t enmXcptType : 5;
219	/** Currently unused bits. */
220	uint32_t uUnused : 6;
221	/** BS3CG1INSTR_F_XXX. */
222	uint32_t fFlags;
223	} BS3CG1INSTR;
224	AssertCompileSize(BS3CG1INSTR, 12);
225	/** Pointer to a const instruction. */
226	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
227
228
229	/** @name BS3CG1INSTR_F_XXX
230	* @{ */
231	/** Defaults to SS rather than DS. */
232	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
233	/** Invalid instruction in 64-bit mode. */
234	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
235	/** Unused instruction. */
236	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
237	/** @} */
238
239
240	/**
241	* Test header.
242	*/
243	typedef struct BS3CG1TESTHDR
244	{
245	/** The size of the selector program in bytes.
246	* This is also the offset of the input context modification program. */
247	uint32_t cbSelector : 8;
248	/** The size of the input context modification program in bytes.
249	* This immediately follows the selector program. */
250	uint32_t cbInput : 12;
251	/** The size of the output context modification program in bytes.
252	* This immediately follows the input context modification program. The
253	* program takes the result of the input program as starting point. */
254	uint32_t cbOutput : 11;
255	/** Indicates whether this is the last test or not. */
256	uint32_t fLast : 1;
257	} BS3CG1TESTHDR;
258	AssertCompileSize(BS3CG1TESTHDR, 4);
259	/** Pointer to a const test header. */
260	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
261
262	/** @name Opcode format for the BS3CG1 context modifier.
263	*
264	* Used by both the input and output context programs.
265	*
266	* The most common operations are encoded as a single byte opcode followed by
267	* one or more immediate bytes with data.
268	*
269	* @{ */
270	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
271	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
272	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
273	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
274	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
275	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
276	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
277	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
278	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
279
280	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
281	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
282	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
283	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
284	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
285
286	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
287
288	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
289	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
290	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
291	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
292	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
293	/** @} */
294
295	/**
296	* Escaped destination values
297	*
298	* These are just uppercased versions of TestInOut.kdFields, where dots are
299	* replaced by underscores.
300	*/
301	typedef enum BS3CG1DST
302	{
303	BS3CG1DST_INVALID = 0,
304	/* Operands. */
305	BS3CG1DST_OP1,
306	BS3CG1DST_OP2,
307	BS3CG1DST_OP3,
308	BS3CG1DST_OP4,
309	/* Flags. */
310	BS3CG1DST_EFL,
311	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
312	/* 8-bit GPRs. */
313	BS3CG1DST_AL,
314	BS3CG1DST_CL,
315	BS3CG1DST_DL,
316	BS3CG1DST_BL,
317	BS3CG1DST_AH,
318	BS3CG1DST_CH,
319	BS3CG1DST_DH,
320	BS3CG1DST_BH,
321	BS3CG1DST_SPL,
322	BS3CG1DST_BPL,
323	BS3CG1DST_SIL,
324	BS3CG1DST_DIL,
325	BS3CG1DST_R8L,
326	BS3CG1DST_R9L,
327	BS3CG1DST_R10L,
328	BS3CG1DST_R11L,
329	BS3CG1DST_R12L,
330	BS3CG1DST_R13L,
331	BS3CG1DST_R14L,
332	BS3CG1DST_R15L,
333	/* 16-bit GPRs. */
334	BS3CG1DST_AX,
335	BS3CG1DST_CX,
336	BS3CG1DST_DX,
337	BS3CG1DST_BX,
338	BS3CG1DST_SP,
339	BS3CG1DST_BP,
340	BS3CG1DST_SI,
341	BS3CG1DST_DI,
342	BS3CG1DST_R8W,
343	BS3CG1DST_R9W,
344	BS3CG1DST_R10W,
345	BS3CG1DST_R11W,
346	BS3CG1DST_R12W,
347	BS3CG1DST_R13W,
348	BS3CG1DST_R14W,
349	BS3CG1DST_R15W,
350	/* 32-bit GPRs. */
351	BS3CG1DST_EAX,
352	BS3CG1DST_ECX,
353	BS3CG1DST_EDX,
354	BS3CG1DST_EBX,
355	BS3CG1DST_ESP,
356	BS3CG1DST_EBP,
357	BS3CG1DST_ESI,
358	BS3CG1DST_EDI,
359	BS3CG1DST_R8D,
360	BS3CG1DST_R9D,
361	BS3CG1DST_R10D,
362	BS3CG1DST_R11D,
363	BS3CG1DST_R12D,
364	BS3CG1DST_R13D,
365	BS3CG1DST_R14D,
366	BS3CG1DST_R15D,
367	/* 64-bit GPRs. */
368	BS3CG1DST_RAX,
369	BS3CG1DST_RCX,
370	BS3CG1DST_RDX,
371	BS3CG1DST_RBX,
372	BS3CG1DST_RSP,
373	BS3CG1DST_RBP,
374	BS3CG1DST_RSI,
375	BS3CG1DST_RDI,
376	BS3CG1DST_R8,
377	BS3CG1DST_R9,
378	BS3CG1DST_R10,
379	BS3CG1DST_R11,
380	BS3CG1DST_R12,
381	BS3CG1DST_R13,
382	BS3CG1DST_R14,
383	BS3CG1DST_R15,
384	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
385	BS3CG1DST_OZ_RAX,
386	BS3CG1DST_OZ_RCX,
387	BS3CG1DST_OZ_RDX,
388	BS3CG1DST_OZ_RBX,
389	BS3CG1DST_OZ_RSP,
390	BS3CG1DST_OZ_RBP,
391	BS3CG1DST_OZ_RSI,
392	BS3CG1DST_OZ_RDI,
393	BS3CG1DST_OZ_R8,
394	BS3CG1DST_OZ_R9,
395	BS3CG1DST_OZ_R10,
396	BS3CG1DST_OZ_R11,
397	BS3CG1DST_OZ_R12,
398	BS3CG1DST_OZ_R13,
399	BS3CG1DST_OZ_R14,
400	BS3CG1DST_OZ_R15,
401
402	/* FPU registers. */
403	BS3CG1DST_FPU_FIRST,
404	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
405	BS3CG1DST_FSW,
406	BS3CG1DST_FTW,
407	BS3CG1DST_FOP,
408	BS3CG1DST_FPUIP,
409	BS3CG1DST_FPUCS,
410	BS3CG1DST_FPUDP,
411	BS3CG1DST_FPUDS,
412	BS3CG1DST_MXCSR,
413	BS3CG1DST_MXCSR_MASK,
414	BS3CG1DST_ST0,
415	BS3CG1DST_ST1,
416	BS3CG1DST_ST2,
417	BS3CG1DST_ST3,
418	BS3CG1DST_ST4,
419	BS3CG1DST_ST5,
420	BS3CG1DST_ST6,
421	BS3CG1DST_ST7,
422	/* MMX registers. */
423	BS3CG1DST_MM0,
424	BS3CG1DST_MM1,
425	BS3CG1DST_MM2,
426	BS3CG1DST_MM3,
427	BS3CG1DST_MM4,
428	BS3CG1DST_MM5,
429	BS3CG1DST_MM6,
430	BS3CG1DST_MM7,
431	/* SSE registers. */
432	BS3CG1DST_XMM0,
433	BS3CG1DST_XMM1,
434	BS3CG1DST_XMM2,
435	BS3CG1DST_XMM3,
436	BS3CG1DST_XMM4,
437	BS3CG1DST_XMM5,
438	BS3CG1DST_XMM6,
439	BS3CG1DST_XMM7,
440	BS3CG1DST_XMM8,
441	BS3CG1DST_XMM9,
442	BS3CG1DST_XMM10,
443	BS3CG1DST_XMM11,
444	BS3CG1DST_XMM12,
445	BS3CG1DST_XMM13,
446	BS3CG1DST_XMM14,
447	BS3CG1DST_XMM15,
448	BS3CG1DST_XMM0_LO,
449	BS3CG1DST_XMM1_LO,
450	BS3CG1DST_XMM2_LO,
451	BS3CG1DST_XMM3_LO,
452	BS3CG1DST_XMM4_LO,
453	BS3CG1DST_XMM5_LO,
454	BS3CG1DST_XMM6_LO,
455	BS3CG1DST_XMM7_LO,
456	BS3CG1DST_XMM8_LO,
457	BS3CG1DST_XMM9_LO,
458	BS3CG1DST_XMM10_LO,
459	BS3CG1DST_XMM11_LO,
460	BS3CG1DST_XMM12_LO,
461	BS3CG1DST_XMM13_LO,
462	BS3CG1DST_XMM14_LO,
463	BS3CG1DST_XMM15_LO,
464	BS3CG1DST_XMM0_HI,
465	BS3CG1DST_XMM1_HI,
466	BS3CG1DST_XMM2_HI,
467	BS3CG1DST_XMM3_HI,
468	BS3CG1DST_XMM4_HI,
469	BS3CG1DST_XMM5_HI,
470	BS3CG1DST_XMM6_HI,
471	BS3CG1DST_XMM7_HI,
472	BS3CG1DST_XMM8_HI,
473	BS3CG1DST_XMM9_HI,
474	BS3CG1DST_XMM10_HI,
475	BS3CG1DST_XMM11_HI,
476	BS3CG1DST_XMM12_HI,
477	BS3CG1DST_XMM13_HI,
478	BS3CG1DST_XMM14_HI,
479	BS3CG1DST_XMM15_HI,
480	BS3CG1DST_XMM0_DW0,
481	BS3CG1DST_XMM1_DW0,
482	BS3CG1DST_XMM2_DW0,
483	BS3CG1DST_XMM3_DW0,
484	BS3CG1DST_XMM4_DW0,
485	BS3CG1DST_XMM5_DW0,
486	BS3CG1DST_XMM6_DW0,
487	BS3CG1DST_XMM7_DW0,
488	BS3CG1DST_XMM8_DW0,
489	BS3CG1DST_XMM9_DW0,
490	BS3CG1DST_XMM10_DW0,
491	BS3CG1DST_XMM11_DW0,
492	BS3CG1DST_XMM12_DW0,
493	BS3CG1DST_XMM13_DW0,
494	BS3CG1DST_XMM14_DW0,
495	BS3CG1DST_XMM15_DW0,
496	/* AVX registers. */
497	BS3CG1DST_YMM0,
498	BS3CG1DST_YMM1,
499	BS3CG1DST_YMM2,
500	BS3CG1DST_YMM3,
501	BS3CG1DST_YMM4,
502	BS3CG1DST_YMM5,
503	BS3CG1DST_YMM6,
504	BS3CG1DST_YMM7,
505	BS3CG1DST_YMM8,
506	BS3CG1DST_YMM9,
507	BS3CG1DST_YMM10,
508	BS3CG1DST_YMM11,
509	BS3CG1DST_YMM12,
510	BS3CG1DST_YMM13,
511	BS3CG1DST_YMM14,
512	BS3CG1DST_YMM15,
513
514	/* Special fields: */
515	BS3CG1DST_SPECIAL_START,
516	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
517
518	BS3CG1DST_END
519	} BS3CG1DST;
520
521	/** @name Selector opcode definitions.
522	*
523	* Selector programs are very simple, they are zero or more predicate tests
524	* that are ANDed together. If a predicate test fails, the test is skipped.
525	*
526	* One instruction is encoded as byte, where the first bit indicates what kind
527	* of test and the 7 remaining bits indicates which predicate to check.
528	*
529	* @{ */
530	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
531	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
532	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
533	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
534	/** @} */
535
536	/**
537	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
538	*/
539	typedef enum BS3CG1PRED
540	{
541	BS3CG1PRED_INVALID = 0,
542
543	/* Operand size. */
544	BS3CG1PRED_SIZE_O16,
545	BS3CG1PRED_SIZE_O32,
546	BS3CG1PRED_SIZE_O64,
547	/* Execution ring. */
548	BS3CG1PRED_RING_0,
549	BS3CG1PRED_RING_1,
550	BS3CG1PRED_RING_2,
551	BS3CG1PRED_RING_3,
552	BS3CG1PRED_RING_0_THRU_2,
553	BS3CG1PRED_RING_1_THRU_3,
554	/* Basic code mode. */
555	BS3CG1PRED_CODE_64BIT,
556	BS3CG1PRED_CODE_32BIT,
557	BS3CG1PRED_CODE_16BIT,
558	/* CPU modes. */
559	BS3CG1PRED_MODE_REAL,
560	BS3CG1PRED_MODE_PROT,
561	BS3CG1PRED_MODE_LONG,
562	BS3CG1PRED_MODE_V86,
563	BS3CG1PRED_MODE_SMM,
564	BS3CG1PRED_MODE_VMX,
565	BS3CG1PRED_MODE_SVM,
566	/* Paging on/off */
567	BS3CG1PRED_PAGING_ON,
568	BS3CG1PRED_PAGING_OFF,
569
570	BS3CG1PRED_END
571	} BS3CG1PRED;
572
573
574	/** The test instructions (generated). */
575	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
576	/** The number of test instructions (generated). */
577	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
578	/** The mnemonics (generated).
579	* Variable length sequence of mnemonics that runs in parallel to
580	* g_aBs3Cg1Instructions. */
581	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
582	/** The opcodes (generated).
583	* Variable length sequence of opcode bytes that runs in parallel to
584	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
585	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
586	/** The operands (generated).
587	* Variable length sequence of opcode values (BS3CG1OP) that runs in
588	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
589	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
590	/** The test data that BS3CG1INSTR.
591	* In order to simplify generating these, we use a byte array. */
592	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
593
594
595	#endif
596

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66315

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