bs3-cpu-generated-1.h@ 66327

Last change on this file since 66327 was 66327, checked in by vboxsync, 8 years ago
IEM,CPUM: Implemented clflush Mb (0f ae /7).
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1	/* $Id: bs3-cpu-generated-1.h 66327 2017-03-29 10:12:02Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51	BS3CG1OP_WqZxReg,
52
53	BS3CG1OP_Gb,
54	BS3CG1OP_Gv,
55	BS3CG1OP_Uq,
56	BS3CG1OP_UqHi,
57	BS3CG1OP_Vss,
58	BS3CG1OP_Vsd,
59	BS3CG1OP_Vps,
60	BS3CG1OP_Vpd,
61	BS3CG1OP_Vq,
62	BS3CG1OP_Vdq,
63
64	BS3CG1OP_Ib,
65	BS3CG1OP_Iz,
66
67	BS3CG1OP_AL,
68	BS3CG1OP_rAX,
69
70	BS3CG1OP_Ma,
71	BS3CG1OP_MbRO,
72	BS3CG1OP_Mq,
73
74	BS3CG1OP_END
75	} BS3CG1OP;
76	/** Pointer to a const operand enum. */
77	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
78
79
80	/**
81	* Instruction encoding format.
82	*
83	* This duplicates some of the info in the operand array, however it makes it
84	* easier to figure out encoding variations.
85	*/
86	typedef enum BS3CG1ENC
87	{
88	BS3CG1ENC_INVALID = 0,
89
90	BS3CG1ENC_MODRM_Eb_Gb,
91	BS3CG1ENC_MODRM_Ev_Gv,
92	BS3CG1ENC_MODRM_Wss_Vss,
93	BS3CG1ENC_MODRM_Wsd_Vsd,
94	BS3CG1ENC_MODRM_Wps_Vps,
95	BS3CG1ENC_MODRM_Wpd_Vpd,
96	BS3CG1ENC_MODRM_WqZxReg_Vq,
97
98	BS3CG1ENC_MODRM_Gb_Eb,
99	BS3CG1ENC_MODRM_Gv_Ev,
100	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
101	BS3CG1ENC_MODRM_Vq_UqHi,
102	BS3CG1ENC_MODRM_Vq_Mq,
103	BS3CG1ENC_MODRM_Vdq_Wdq,
104	BS3CG1ENC_MODRM_MbRO,
105
106	BS3CG1ENC_FIXED,
107	BS3CG1ENC_FIXED_AL_Ib,
108	BS3CG1ENC_FIXED_rAX_Iz,
109
110	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
111	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
112
113	BS3CG1ENC_END
114	} BS3CG1ENC;
115
116
117	/**
118	* Prefix sensitivitiy kind.
119	*/
120	typedef enum BS3CG1PFXKIND
121	{
122	BS3CG1PFXKIND_INVALID = 0,
123
124	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
125	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
126	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
127	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
128
129	/** @todo more work to be done here... */
130	BS3CG1PFXKIND_MODRM,
131	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
132
133	BS3CG1PFXKIND_END
134	} BS3CG1PFXKIND;
135
136	/**
137	* CPU selection or CPU ID.
138	*/
139	typedef enum BS3CG1CPU
140	{
141	/** Works with an CPU. */
142	BS3CG1CPU_ANY = 0,
143	BS3CG1CPU_GE_80186,
144	BS3CG1CPU_GE_80286,
145	BS3CG1CPU_GE_80386,
146	BS3CG1CPU_GE_80486,
147	BS3CG1CPU_GE_Pentium,
148
149	BS3CG1CPU_SSE,
150	BS3CG1CPU_SSE2,
151	BS3CG1CPU_SSE3,
152	BS3CG1CPU_AVX,
153	BS3CG1CPU_AVX2,
154	BS3CG1CPU_CLFSH,
155
156	BS3CG1CPU_END
157	} BS3CG1CPU;
158
159
160	/**
161	* SSE & AVX exception types.
162	*/
163	typedef enum BS3CG1XCPTTYPE
164	{
165	BS3CG1XCPTTYPE_NONE = 0,
166	/* SSE: */
167	BS3CG1XCPTTYPE_1,
168	BS3CG1XCPTTYPE_2,
169	BS3CG1XCPTTYPE_3,
170	BS3CG1XCPTTYPE_4,
171	BS3CG1XCPTTYPE_4UA,
172	BS3CG1XCPTTYPE_5,
173	BS3CG1XCPTTYPE_6,
174	BS3CG1XCPTTYPE_7,
175	BS3CG1XCPTTYPE_8,
176	BS3CG1XCPTTYPE_11,
177	BS3CG1XCPTTYPE_12,
178	/* EVEX: */
179	BS3CG1XCPTTYPE_E1,
180	BS3CG1XCPTTYPE_E1NF,
181	BS3CG1XCPTTYPE_E2,
182	BS3CG1XCPTTYPE_E3,
183	BS3CG1XCPTTYPE_E3NF,
184	BS3CG1XCPTTYPE_E4,
185	BS3CG1XCPTTYPE_E4NF,
186	BS3CG1XCPTTYPE_E5,
187	BS3CG1XCPTTYPE_E5NF,
188	BS3CG1XCPTTYPE_E6,
189	BS3CG1XCPTTYPE_E6NF,
190	BS3CG1XCPTTYPE_E7NF,
191	BS3CG1XCPTTYPE_E9,
192	BS3CG1XCPTTYPE_E9NF,
193	BS3CG1XCPTTYPE_E10,
194	BS3CG1XCPTTYPE_E11,
195	BS3CG1XCPTTYPE_E12,
196	BS3CG1XCPTTYPE_E12NF,
197	BS3CG1XCPTTYPE_END
198	} BS3CG1XCPTTYPE;
199	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
200
201
202	/**
203	* Generated instruction info.
204	*/
205	typedef struct BS3CG1INSTR
206	{
207	/** The opcode size. */
208	uint32_t cbOpcodes : 2;
209	/** The number of operands. */
210	uint32_t cOperands : 2;
211	/** The length of the mnemonic. */
212	uint32_t cchMnemonic : 4;
213	/** Whether to advance the mnemonic array pointer. */
214	uint32_t fAdvanceMnemonic : 1;
215	/** Offset into g_abBs3Cg1Tests of the first test. */
216	uint32_t offTests : 23;
217	/** BS3CG1ENC values. */
218	uint32_t enmEncoding : 10;
219	/** BS3CG1PFXKIND values. */
220	uint32_t enmPrefixKind : 4;
221	/** CPU test / CPU ID bit test (BS3CG1CPU). */
222	uint32_t enmCpuTest : 6;
223	/** Exception type (BS3CG1XCPTTYPE) */
224	uint32_t enmXcptType : 5;
225	/** Currently unused bits. */
226	uint32_t uUnused : 6;
227	/** BS3CG1INSTR_F_XXX. */
228	uint32_t fFlags;
229	} BS3CG1INSTR;
230	AssertCompileSize(BS3CG1INSTR, 12);
231	/** Pointer to a const instruction. */
232	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
233
234
235	/** @name BS3CG1INSTR_F_XXX
236	* @{ */
237	/** Defaults to SS rather than DS. */
238	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
239	/** Invalid instruction in 64-bit mode. */
240	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
241	/** Unused instruction. */
242	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
243	/** @} */
244
245
246	/**
247	* Test header.
248	*/
249	typedef struct BS3CG1TESTHDR
250	{
251	/** The size of the selector program in bytes.
252	* This is also the offset of the input context modification program. */
253	uint32_t cbSelector : 8;
254	/** The size of the input context modification program in bytes.
255	* This immediately follows the selector program. */
256	uint32_t cbInput : 12;
257	/** The size of the output context modification program in bytes.
258	* This immediately follows the input context modification program. The
259	* program takes the result of the input program as starting point. */
260	uint32_t cbOutput : 11;
261	/** Indicates whether this is the last test or not. */
262	uint32_t fLast : 1;
263	} BS3CG1TESTHDR;
264	AssertCompileSize(BS3CG1TESTHDR, 4);
265	/** Pointer to a const test header. */
266	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
267
268	/** @name Opcode format for the BS3CG1 context modifier.
269	*
270	* Used by both the input and output context programs.
271	*
272	* The most common operations are encoded as a single byte opcode followed by
273	* one or more immediate bytes with data.
274	*
275	* @{ */
276	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
277	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
278	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
279	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
280	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
281	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
282	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
283	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
284	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
285
286	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
287	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
288	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
289	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
290	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
291
292	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
293
294	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
295	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
296	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
297	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
298	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
299	/** @} */
300
301	/**
302	* Escaped destination values
303	*
304	* These are just uppercased versions of TestInOut.kdFields, where dots are
305	* replaced by underscores.
306	*/
307	typedef enum BS3CG1DST
308	{
309	BS3CG1DST_INVALID = 0,
310	/* Operands. */
311	BS3CG1DST_OP1,
312	BS3CG1DST_OP2,
313	BS3CG1DST_OP3,
314	BS3CG1DST_OP4,
315	/* Flags. */
316	BS3CG1DST_EFL,
317	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
318	/* 8-bit GPRs. */
319	BS3CG1DST_AL,
320	BS3CG1DST_CL,
321	BS3CG1DST_DL,
322	BS3CG1DST_BL,
323	BS3CG1DST_AH,
324	BS3CG1DST_CH,
325	BS3CG1DST_DH,
326	BS3CG1DST_BH,
327	BS3CG1DST_SPL,
328	BS3CG1DST_BPL,
329	BS3CG1DST_SIL,
330	BS3CG1DST_DIL,
331	BS3CG1DST_R8L,
332	BS3CG1DST_R9L,
333	BS3CG1DST_R10L,
334	BS3CG1DST_R11L,
335	BS3CG1DST_R12L,
336	BS3CG1DST_R13L,
337	BS3CG1DST_R14L,
338	BS3CG1DST_R15L,
339	/* 16-bit GPRs. */
340	BS3CG1DST_AX,
341	BS3CG1DST_CX,
342	BS3CG1DST_DX,
343	BS3CG1DST_BX,
344	BS3CG1DST_SP,
345	BS3CG1DST_BP,
346	BS3CG1DST_SI,
347	BS3CG1DST_DI,
348	BS3CG1DST_R8W,
349	BS3CG1DST_R9W,
350	BS3CG1DST_R10W,
351	BS3CG1DST_R11W,
352	BS3CG1DST_R12W,
353	BS3CG1DST_R13W,
354	BS3CG1DST_R14W,
355	BS3CG1DST_R15W,
356	/* 32-bit GPRs. */
357	BS3CG1DST_EAX,
358	BS3CG1DST_ECX,
359	BS3CG1DST_EDX,
360	BS3CG1DST_EBX,
361	BS3CG1DST_ESP,
362	BS3CG1DST_EBP,
363	BS3CG1DST_ESI,
364	BS3CG1DST_EDI,
365	BS3CG1DST_R8D,
366	BS3CG1DST_R9D,
367	BS3CG1DST_R10D,
368	BS3CG1DST_R11D,
369	BS3CG1DST_R12D,
370	BS3CG1DST_R13D,
371	BS3CG1DST_R14D,
372	BS3CG1DST_R15D,
373	/* 64-bit GPRs. */
374	BS3CG1DST_RAX,
375	BS3CG1DST_RCX,
376	BS3CG1DST_RDX,
377	BS3CG1DST_RBX,
378	BS3CG1DST_RSP,
379	BS3CG1DST_RBP,
380	BS3CG1DST_RSI,
381	BS3CG1DST_RDI,
382	BS3CG1DST_R8,
383	BS3CG1DST_R9,
384	BS3CG1DST_R10,
385	BS3CG1DST_R11,
386	BS3CG1DST_R12,
387	BS3CG1DST_R13,
388	BS3CG1DST_R14,
389	BS3CG1DST_R15,
390	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
391	BS3CG1DST_OZ_RAX,
392	BS3CG1DST_OZ_RCX,
393	BS3CG1DST_OZ_RDX,
394	BS3CG1DST_OZ_RBX,
395	BS3CG1DST_OZ_RSP,
396	BS3CG1DST_OZ_RBP,
397	BS3CG1DST_OZ_RSI,
398	BS3CG1DST_OZ_RDI,
399	BS3CG1DST_OZ_R8,
400	BS3CG1DST_OZ_R9,
401	BS3CG1DST_OZ_R10,
402	BS3CG1DST_OZ_R11,
403	BS3CG1DST_OZ_R12,
404	BS3CG1DST_OZ_R13,
405	BS3CG1DST_OZ_R14,
406	BS3CG1DST_OZ_R15,
407
408	/* FPU registers. */
409	BS3CG1DST_FPU_FIRST,
410	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
411	BS3CG1DST_FSW,
412	BS3CG1DST_FTW,
413	BS3CG1DST_FOP,
414	BS3CG1DST_FPUIP,
415	BS3CG1DST_FPUCS,
416	BS3CG1DST_FPUDP,
417	BS3CG1DST_FPUDS,
418	BS3CG1DST_MXCSR,
419	BS3CG1DST_MXCSR_MASK,
420	BS3CG1DST_ST0,
421	BS3CG1DST_ST1,
422	BS3CG1DST_ST2,
423	BS3CG1DST_ST3,
424	BS3CG1DST_ST4,
425	BS3CG1DST_ST5,
426	BS3CG1DST_ST6,
427	BS3CG1DST_ST7,
428	/* MMX registers. */
429	BS3CG1DST_MM0,
430	BS3CG1DST_MM1,
431	BS3CG1DST_MM2,
432	BS3CG1DST_MM3,
433	BS3CG1DST_MM4,
434	BS3CG1DST_MM5,
435	BS3CG1DST_MM6,
436	BS3CG1DST_MM7,
437	/* SSE registers. */
438	BS3CG1DST_XMM0,
439	BS3CG1DST_XMM1,
440	BS3CG1DST_XMM2,
441	BS3CG1DST_XMM3,
442	BS3CG1DST_XMM4,
443	BS3CG1DST_XMM5,
444	BS3CG1DST_XMM6,
445	BS3CG1DST_XMM7,
446	BS3CG1DST_XMM8,
447	BS3CG1DST_XMM9,
448	BS3CG1DST_XMM10,
449	BS3CG1DST_XMM11,
450	BS3CG1DST_XMM12,
451	BS3CG1DST_XMM13,
452	BS3CG1DST_XMM14,
453	BS3CG1DST_XMM15,
454	BS3CG1DST_XMM0_LO,
455	BS3CG1DST_XMM1_LO,
456	BS3CG1DST_XMM2_LO,
457	BS3CG1DST_XMM3_LO,
458	BS3CG1DST_XMM4_LO,
459	BS3CG1DST_XMM5_LO,
460	BS3CG1DST_XMM6_LO,
461	BS3CG1DST_XMM7_LO,
462	BS3CG1DST_XMM8_LO,
463	BS3CG1DST_XMM9_LO,
464	BS3CG1DST_XMM10_LO,
465	BS3CG1DST_XMM11_LO,
466	BS3CG1DST_XMM12_LO,
467	BS3CG1DST_XMM13_LO,
468	BS3CG1DST_XMM14_LO,
469	BS3CG1DST_XMM15_LO,
470	BS3CG1DST_XMM0_HI,
471	BS3CG1DST_XMM1_HI,
472	BS3CG1DST_XMM2_HI,
473	BS3CG1DST_XMM3_HI,
474	BS3CG1DST_XMM4_HI,
475	BS3CG1DST_XMM5_HI,
476	BS3CG1DST_XMM6_HI,
477	BS3CG1DST_XMM7_HI,
478	BS3CG1DST_XMM8_HI,
479	BS3CG1DST_XMM9_HI,
480	BS3CG1DST_XMM10_HI,
481	BS3CG1DST_XMM11_HI,
482	BS3CG1DST_XMM12_HI,
483	BS3CG1DST_XMM13_HI,
484	BS3CG1DST_XMM14_HI,
485	BS3CG1DST_XMM15_HI,
486	BS3CG1DST_XMM0_LO_ZX,
487	BS3CG1DST_XMM1_LO_ZX,
488	BS3CG1DST_XMM2_LO_ZX,
489	BS3CG1DST_XMM3_LO_ZX,
490	BS3CG1DST_XMM4_LO_ZX,
491	BS3CG1DST_XMM5_LO_ZX,
492	BS3CG1DST_XMM6_LO_ZX,
493	BS3CG1DST_XMM7_LO_ZX,
494	BS3CG1DST_XMM8_LO_ZX,
495	BS3CG1DST_XMM9_LO_ZX,
496	BS3CG1DST_XMM10_LO_ZX,
497	BS3CG1DST_XMM11_LO_ZX,
498	BS3CG1DST_XMM12_LO_ZX,
499	BS3CG1DST_XMM13_LO_ZX,
500	BS3CG1DST_XMM14_LO_ZX,
501	BS3CG1DST_XMM15_LO_ZX,
502	BS3CG1DST_XMM0_DW0,
503	BS3CG1DST_XMM1_DW0,
504	BS3CG1DST_XMM2_DW0,
505	BS3CG1DST_XMM3_DW0,
506	BS3CG1DST_XMM4_DW0,
507	BS3CG1DST_XMM5_DW0,
508	BS3CG1DST_XMM6_DW0,
509	BS3CG1DST_XMM7_DW0,
510	BS3CG1DST_XMM8_DW0,
511	BS3CG1DST_XMM9_DW0,
512	BS3CG1DST_XMM10_DW0,
513	BS3CG1DST_XMM11_DW0,
514	BS3CG1DST_XMM12_DW0,
515	BS3CG1DST_XMM13_DW0,
516	BS3CG1DST_XMM14_DW0,
517	BS3CG1DST_XMM15_DW0,
518	/* AVX registers. */
519	BS3CG1DST_YMM0,
520	BS3CG1DST_YMM1,
521	BS3CG1DST_YMM2,
522	BS3CG1DST_YMM3,
523	BS3CG1DST_YMM4,
524	BS3CG1DST_YMM5,
525	BS3CG1DST_YMM6,
526	BS3CG1DST_YMM7,
527	BS3CG1DST_YMM8,
528	BS3CG1DST_YMM9,
529	BS3CG1DST_YMM10,
530	BS3CG1DST_YMM11,
531	BS3CG1DST_YMM12,
532	BS3CG1DST_YMM13,
533	BS3CG1DST_YMM14,
534	BS3CG1DST_YMM15,
535
536	/* Special fields: */
537	BS3CG1DST_SPECIAL_START,
538	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
539
540	BS3CG1DST_END
541	} BS3CG1DST;
542	AssertCompile(BS3CG1DST_END <= 256);
543
544	/** @name Selector opcode definitions.
545	*
546	* Selector programs are very simple, they are zero or more predicate tests
547	* that are ANDed together. If a predicate test fails, the test is skipped.
548	*
549	* One instruction is encoded as byte, where the first bit indicates what kind
550	* of test and the 7 remaining bits indicates which predicate to check.
551	*
552	* @{ */
553	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
554	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
555	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
556	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
557	/** @} */
558
559	/**
560	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
561	*/
562	typedef enum BS3CG1PRED
563	{
564	BS3CG1PRED_INVALID = 0,
565
566	/* Operand size. */
567	BS3CG1PRED_SIZE_O16,
568	BS3CG1PRED_SIZE_O32,
569	BS3CG1PRED_SIZE_O64,
570	/* Execution ring. */
571	BS3CG1PRED_RING_0,
572	BS3CG1PRED_RING_1,
573	BS3CG1PRED_RING_2,
574	BS3CG1PRED_RING_3,
575	BS3CG1PRED_RING_0_THRU_2,
576	BS3CG1PRED_RING_1_THRU_3,
577	/* Basic code mode. */
578	BS3CG1PRED_CODE_64BIT,
579	BS3CG1PRED_CODE_32BIT,
580	BS3CG1PRED_CODE_16BIT,
581	/* CPU modes. */
582	BS3CG1PRED_MODE_REAL,
583	BS3CG1PRED_MODE_PROT,
584	BS3CG1PRED_MODE_LONG,
585	BS3CG1PRED_MODE_V86,
586	BS3CG1PRED_MODE_SMM,
587	BS3CG1PRED_MODE_VMX,
588	BS3CG1PRED_MODE_SVM,
589	/* Paging on/off */
590	BS3CG1PRED_PAGING_ON,
591	BS3CG1PRED_PAGING_OFF,
592
593	BS3CG1PRED_END
594	} BS3CG1PRED;
595
596
597	/** The test instructions (generated). */
598	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
599	/** The number of test instructions (generated). */
600	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
601	/** The mnemonics (generated).
602	* Variable length sequence of mnemonics that runs in parallel to
603	* g_aBs3Cg1Instructions. */
604	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
605	/** The opcodes (generated).
606	* Variable length sequence of opcode bytes that runs in parallel to
607	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
608	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
609	/** The operands (generated).
610	* Variable length sequence of opcode values (BS3CG1OP) that runs in
611	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
612	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
613	/** The test data that BS3CG1INSTR.
614	* In order to simplify generating these, we use a byte array. */
615	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
616
617
618	#endif
619

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66327

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