bs3-cpu-generated-1.h@ 66791

Last change on this file since 66791 was 66791, checked in by vboxsync, 8 years ago
IEM: Implemented movhps Mq,Vq (0f 17).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 17.7 KB

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1	/* $Id: bs3-cpu-generated-1.h 66791 2017-05-04 12:29:02Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51	BS3CG1OP_WqZxReg,
52
53	BS3CG1OP_Gb,
54	BS3CG1OP_Gv,
55	BS3CG1OP_Uq,
56	BS3CG1OP_UqHi,
57	BS3CG1OP_Vss,
58	BS3CG1OP_VssZxReg,
59	BS3CG1OP_Vsd,
60	BS3CG1OP_VsdZxReg,
61	BS3CG1OP_Vps,
62	BS3CG1OP_Vpd,
63	BS3CG1OP_Vq,
64	BS3CG1OP_Vdq,
65	BS3CG1OP_VqHi,
66
67	BS3CG1OP_Ib,
68	BS3CG1OP_Iz,
69
70	BS3CG1OP_AL,
71	BS3CG1OP_rAX,
72
73	BS3CG1OP_Ma,
74	BS3CG1OP_MbRO,
75	BS3CG1OP_MdRO,
76	BS3CG1OP_MdWO,
77	BS3CG1OP_Mq,
78	BS3CG1OP_MqWO,
79
80	BS3CG1OP_END
81	} BS3CG1OP;
82	/** Pointer to a const operand enum. */
83	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
84
85
86	/**
87	* Instruction encoding format.
88	*
89	* This duplicates some of the info in the operand array, however it makes it
90	* easier to figure out encoding variations.
91	*/
92	typedef enum BS3CG1ENC
93	{
94	BS3CG1ENC_INVALID = 0,
95
96	BS3CG1ENC_MODRM_Eb_Gb,
97	BS3CG1ENC_MODRM_Ev_Gv,
98	BS3CG1ENC_MODRM_Wss_Vss,
99	BS3CG1ENC_MODRM_Wsd_Vsd,
100	BS3CG1ENC_MODRM_Wps_Vps,
101	BS3CG1ENC_MODRM_Wpd_Vpd,
102	BS3CG1ENC_MODRM_WqZxReg_Vq,
103
104	BS3CG1ENC_MODRM_Gb_Eb,
105	BS3CG1ENC_MODRM_Gv_Ev,
106	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
107	BS3CG1ENC_MODRM_Vq_UqHi,
108	BS3CG1ENC_MODRM_Vq_Mq,
109	BS3CG1ENC_MODRM_VqHi_Uq,
110	BS3CG1ENC_MODRM_VqHi_Mq,
111	BS3CG1ENC_MODRM_Vdq_Wdq,
112	BS3CG1ENC_MODRM_Vpd_Wpd,
113	BS3CG1ENC_MODRM_Vps_Wps,
114	BS3CG1ENC_MODRM_VssZxReg_Wss,
115	BS3CG1ENC_MODRM_VsdZxReg_Wsd,
116	BS3CG1ENC_MODRM_MbRO,
117	BS3CG1ENC_MODRM_MdRO,
118	BS3CG1ENC_MODRM_MdWO,
119	BS3CG1ENC_MODRM_MqWO_Vq,
120	BS3CG1ENC_MODRM_MqWO_VqHi,
121
122	BS3CG1ENC_VEX_MODRM_MdWO,
123
124	BS3CG1ENC_FIXED,
125	BS3CG1ENC_FIXED_AL_Ib,
126	BS3CG1ENC_FIXED_rAX_Iz,
127
128	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
129	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
130
131	BS3CG1ENC_END
132	} BS3CG1ENC;
133
134
135	/**
136	* Prefix sensitivitiy kind.
137	*/
138	typedef enum BS3CG1PFXKIND
139	{
140	BS3CG1PFXKIND_INVALID = 0,
141
142	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
143	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
144	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
145	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
146
147	/** @todo more work to be done here... */
148	BS3CG1PFXKIND_MODRM,
149	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
150
151	BS3CG1PFXKIND_END
152	} BS3CG1PFXKIND;
153
154	/**
155	* CPU selection or CPU ID.
156	*/
157	typedef enum BS3CG1CPU
158	{
159	/** Works with an CPU. */
160	BS3CG1CPU_ANY = 0,
161	BS3CG1CPU_GE_80186,
162	BS3CG1CPU_GE_80286,
163	BS3CG1CPU_GE_80386,
164	BS3CG1CPU_GE_80486,
165	BS3CG1CPU_GE_Pentium,
166
167	BS3CG1CPU_SSE,
168	BS3CG1CPU_SSE2,
169	BS3CG1CPU_SSE3,
170	BS3CG1CPU_AVX,
171	BS3CG1CPU_AVX2,
172	BS3CG1CPU_CLFSH,
173	BS3CG1CPU_CLFLUSHOPT,
174
175	BS3CG1CPU_END
176	} BS3CG1CPU;
177
178
179	/**
180	* SSE & AVX exception types.
181	*/
182	typedef enum BS3CG1XCPTTYPE
183	{
184	BS3CG1XCPTTYPE_NONE = 0,
185	/* SSE: */
186	BS3CG1XCPTTYPE_1,
187	BS3CG1XCPTTYPE_2,
188	BS3CG1XCPTTYPE_3,
189	BS3CG1XCPTTYPE_4,
190	BS3CG1XCPTTYPE_4UA,
191	BS3CG1XCPTTYPE_5,
192	BS3CG1XCPTTYPE_6,
193	BS3CG1XCPTTYPE_7,
194	BS3CG1XCPTTYPE_8,
195	BS3CG1XCPTTYPE_11,
196	BS3CG1XCPTTYPE_12,
197	/* EVEX: */
198	BS3CG1XCPTTYPE_E1,
199	BS3CG1XCPTTYPE_E1NF,
200	BS3CG1XCPTTYPE_E2,
201	BS3CG1XCPTTYPE_E3,
202	BS3CG1XCPTTYPE_E3NF,
203	BS3CG1XCPTTYPE_E4,
204	BS3CG1XCPTTYPE_E4NF,
205	BS3CG1XCPTTYPE_E5,
206	BS3CG1XCPTTYPE_E5NF,
207	BS3CG1XCPTTYPE_E6,
208	BS3CG1XCPTTYPE_E6NF,
209	BS3CG1XCPTTYPE_E7NF,
210	BS3CG1XCPTTYPE_E9,
211	BS3CG1XCPTTYPE_E9NF,
212	BS3CG1XCPTTYPE_E10,
213	BS3CG1XCPTTYPE_E11,
214	BS3CG1XCPTTYPE_E12,
215	BS3CG1XCPTTYPE_E12NF,
216	BS3CG1XCPTTYPE_END
217	} BS3CG1XCPTTYPE;
218	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
219
220
221	/**
222	* Generated instruction info.
223	*/
224	typedef struct BS3CG1INSTR
225	{
226	/** The opcode size. */
227	uint32_t cbOpcodes : 2;
228	/** The number of operands. */
229	uint32_t cOperands : 2;
230	/** The length of the mnemonic. */
231	uint32_t cchMnemonic : 4;
232	/** Whether to advance the mnemonic array pointer. */
233	uint32_t fAdvanceMnemonic : 1;
234	/** Offset into g_abBs3Cg1Tests of the first test. */
235	uint32_t offTests : 23;
236	/** BS3CG1ENC values. */
237	uint32_t enmEncoding : 10;
238	/** BS3CG1PFXKIND values. */
239	uint32_t enmPrefixKind : 4;
240	/** CPU test / CPU ID bit test (BS3CG1CPU). */
241	uint32_t enmCpuTest : 6;
242	/** Exception type (BS3CG1XCPTTYPE) */
243	uint32_t enmXcptType : 5;
244	/** Currently unused bits. */
245	uint32_t uUnused : 6;
246	/** BS3CG1INSTR_F_XXX. */
247	uint32_t fFlags;
248	} BS3CG1INSTR;
249	AssertCompileSize(BS3CG1INSTR, 12);
250	/** Pointer to a const instruction. */
251	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
252
253
254	/** @name BS3CG1INSTR_F_XXX
255	* @{ */
256	/** Defaults to SS rather than DS. */
257	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
258	/** Invalid instruction in 64-bit mode. */
259	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
260	/** Unused instruction. */
261	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
262	/** Invalid instruction. */
263	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
264	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
265	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
266	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
267	/** @} */
268
269
270	/**
271	* Test header.
272	*/
273	typedef struct BS3CG1TESTHDR
274	{
275	/** The size of the selector program in bytes.
276	* This is also the offset of the input context modification program. */
277	uint32_t cbSelector : 8;
278	/** The size of the input context modification program in bytes.
279	* This immediately follows the selector program. */
280	uint32_t cbInput : 12;
281	/** The size of the output context modification program in bytes.
282	* This immediately follows the input context modification program. The
283	* program takes the result of the input program as starting point. */
284	uint32_t cbOutput : 11;
285	/** Indicates whether this is the last test or not. */
286	uint32_t fLast : 1;
287	} BS3CG1TESTHDR;
288	AssertCompileSize(BS3CG1TESTHDR, 4);
289	/** Pointer to a const test header. */
290	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
291
292	/** @name Opcode format for the BS3CG1 context modifier.
293	*
294	* Used by both the input and output context programs.
295	*
296	* The most common operations are encoded as a single byte opcode followed by
297	* one or more immediate bytes with data.
298	*
299	* @{ */
300	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
301	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
302	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
303	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
304	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
305	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
306	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
307	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
308	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
309
310	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
311	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
312	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
313	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
314	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
315
316	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
317
318	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
319	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
320	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
321	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
322	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
323	/** @} */
324
325	/**
326	* Escaped destination values
327	*
328	* These are just uppercased versions of TestInOut.kdFields, where dots are
329	* replaced by underscores.
330	*/
331	typedef enum BS3CG1DST
332	{
333	BS3CG1DST_INVALID = 0,
334	/* Operands. */
335	BS3CG1DST_OP1,
336	BS3CG1DST_OP2,
337	BS3CG1DST_OP3,
338	BS3CG1DST_OP4,
339	/* Flags. */
340	BS3CG1DST_EFL,
341	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
342	/* 8-bit GPRs. */
343	BS3CG1DST_AL,
344	BS3CG1DST_CL,
345	BS3CG1DST_DL,
346	BS3CG1DST_BL,
347	BS3CG1DST_AH,
348	BS3CG1DST_CH,
349	BS3CG1DST_DH,
350	BS3CG1DST_BH,
351	BS3CG1DST_SPL,
352	BS3CG1DST_BPL,
353	BS3CG1DST_SIL,
354	BS3CG1DST_DIL,
355	BS3CG1DST_R8L,
356	BS3CG1DST_R9L,
357	BS3CG1DST_R10L,
358	BS3CG1DST_R11L,
359	BS3CG1DST_R12L,
360	BS3CG1DST_R13L,
361	BS3CG1DST_R14L,
362	BS3CG1DST_R15L,
363	/* 16-bit GPRs. */
364	BS3CG1DST_AX,
365	BS3CG1DST_CX,
366	BS3CG1DST_DX,
367	BS3CG1DST_BX,
368	BS3CG1DST_SP,
369	BS3CG1DST_BP,
370	BS3CG1DST_SI,
371	BS3CG1DST_DI,
372	BS3CG1DST_R8W,
373	BS3CG1DST_R9W,
374	BS3CG1DST_R10W,
375	BS3CG1DST_R11W,
376	BS3CG1DST_R12W,
377	BS3CG1DST_R13W,
378	BS3CG1DST_R14W,
379	BS3CG1DST_R15W,
380	/* 32-bit GPRs. */
381	BS3CG1DST_EAX,
382	BS3CG1DST_ECX,
383	BS3CG1DST_EDX,
384	BS3CG1DST_EBX,
385	BS3CG1DST_ESP,
386	BS3CG1DST_EBP,
387	BS3CG1DST_ESI,
388	BS3CG1DST_EDI,
389	BS3CG1DST_R8D,
390	BS3CG1DST_R9D,
391	BS3CG1DST_R10D,
392	BS3CG1DST_R11D,
393	BS3CG1DST_R12D,
394	BS3CG1DST_R13D,
395	BS3CG1DST_R14D,
396	BS3CG1DST_R15D,
397	/* 64-bit GPRs. */
398	BS3CG1DST_RAX,
399	BS3CG1DST_RCX,
400	BS3CG1DST_RDX,
401	BS3CG1DST_RBX,
402	BS3CG1DST_RSP,
403	BS3CG1DST_RBP,
404	BS3CG1DST_RSI,
405	BS3CG1DST_RDI,
406	BS3CG1DST_R8,
407	BS3CG1DST_R9,
408	BS3CG1DST_R10,
409	BS3CG1DST_R11,
410	BS3CG1DST_R12,
411	BS3CG1DST_R13,
412	BS3CG1DST_R14,
413	BS3CG1DST_R15,
414	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
415	BS3CG1DST_OZ_RAX,
416	BS3CG1DST_OZ_RCX,
417	BS3CG1DST_OZ_RDX,
418	BS3CG1DST_OZ_RBX,
419	BS3CG1DST_OZ_RSP,
420	BS3CG1DST_OZ_RBP,
421	BS3CG1DST_OZ_RSI,
422	BS3CG1DST_OZ_RDI,
423	BS3CG1DST_OZ_R8,
424	BS3CG1DST_OZ_R9,
425	BS3CG1DST_OZ_R10,
426	BS3CG1DST_OZ_R11,
427	BS3CG1DST_OZ_R12,
428	BS3CG1DST_OZ_R13,
429	BS3CG1DST_OZ_R14,
430	BS3CG1DST_OZ_R15,
431
432	/* Control registers.*/
433	BS3CG1DST_CR0,
434	BS3CG1DST_CR4,
435	BS3CG1DST_XCR0,
436
437	/* FPU registers. */
438	BS3CG1DST_FPU_FIRST,
439	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
440	BS3CG1DST_FSW,
441	BS3CG1DST_FTW,
442	BS3CG1DST_FOP,
443	BS3CG1DST_FPUIP,
444	BS3CG1DST_FPUCS,
445	BS3CG1DST_FPUDP,
446	BS3CG1DST_FPUDS,
447	BS3CG1DST_MXCSR,
448	BS3CG1DST_ST0,
449	BS3CG1DST_ST1,
450	BS3CG1DST_ST2,
451	BS3CG1DST_ST3,
452	BS3CG1DST_ST4,
453	BS3CG1DST_ST5,
454	BS3CG1DST_ST6,
455	BS3CG1DST_ST7,
456	/* MMX registers. */
457	BS3CG1DST_MM0,
458	BS3CG1DST_MM1,
459	BS3CG1DST_MM2,
460	BS3CG1DST_MM3,
461	BS3CG1DST_MM4,
462	BS3CG1DST_MM5,
463	BS3CG1DST_MM6,
464	BS3CG1DST_MM7,
465	/* SSE registers. */
466	BS3CG1DST_XMM0,
467	BS3CG1DST_XMM1,
468	BS3CG1DST_XMM2,
469	BS3CG1DST_XMM3,
470	BS3CG1DST_XMM4,
471	BS3CG1DST_XMM5,
472	BS3CG1DST_XMM6,
473	BS3CG1DST_XMM7,
474	BS3CG1DST_XMM8,
475	BS3CG1DST_XMM9,
476	BS3CG1DST_XMM10,
477	BS3CG1DST_XMM11,
478	BS3CG1DST_XMM12,
479	BS3CG1DST_XMM13,
480	BS3CG1DST_XMM14,
481	BS3CG1DST_XMM15,
482	BS3CG1DST_XMM0_LO,
483	BS3CG1DST_XMM1_LO,
484	BS3CG1DST_XMM2_LO,
485	BS3CG1DST_XMM3_LO,
486	BS3CG1DST_XMM4_LO,
487	BS3CG1DST_XMM5_LO,
488	BS3CG1DST_XMM6_LO,
489	BS3CG1DST_XMM7_LO,
490	BS3CG1DST_XMM8_LO,
491	BS3CG1DST_XMM9_LO,
492	BS3CG1DST_XMM10_LO,
493	BS3CG1DST_XMM11_LO,
494	BS3CG1DST_XMM12_LO,
495	BS3CG1DST_XMM13_LO,
496	BS3CG1DST_XMM14_LO,
497	BS3CG1DST_XMM15_LO,
498	BS3CG1DST_XMM0_HI,
499	BS3CG1DST_XMM1_HI,
500	BS3CG1DST_XMM2_HI,
501	BS3CG1DST_XMM3_HI,
502	BS3CG1DST_XMM4_HI,
503	BS3CG1DST_XMM5_HI,
504	BS3CG1DST_XMM6_HI,
505	BS3CG1DST_XMM7_HI,
506	BS3CG1DST_XMM8_HI,
507	BS3CG1DST_XMM9_HI,
508	BS3CG1DST_XMM10_HI,
509	BS3CG1DST_XMM11_HI,
510	BS3CG1DST_XMM12_HI,
511	BS3CG1DST_XMM13_HI,
512	BS3CG1DST_XMM14_HI,
513	BS3CG1DST_XMM15_HI,
514	BS3CG1DST_XMM0_LO_ZX,
515	BS3CG1DST_XMM1_LO_ZX,
516	BS3CG1DST_XMM2_LO_ZX,
517	BS3CG1DST_XMM3_LO_ZX,
518	BS3CG1DST_XMM4_LO_ZX,
519	BS3CG1DST_XMM5_LO_ZX,
520	BS3CG1DST_XMM6_LO_ZX,
521	BS3CG1DST_XMM7_LO_ZX,
522	BS3CG1DST_XMM8_LO_ZX,
523	BS3CG1DST_XMM9_LO_ZX,
524	BS3CG1DST_XMM10_LO_ZX,
525	BS3CG1DST_XMM11_LO_ZX,
526	BS3CG1DST_XMM12_LO_ZX,
527	BS3CG1DST_XMM13_LO_ZX,
528	BS3CG1DST_XMM14_LO_ZX,
529	BS3CG1DST_XMM15_LO_ZX,
530	BS3CG1DST_XMM0_DW0,
531	BS3CG1DST_XMM1_DW0,
532	BS3CG1DST_XMM2_DW0,
533	BS3CG1DST_XMM3_DW0,
534	BS3CG1DST_XMM4_DW0,
535	BS3CG1DST_XMM5_DW0,
536	BS3CG1DST_XMM6_DW0,
537	BS3CG1DST_XMM7_DW0,
538	BS3CG1DST_XMM8_DW0,
539	BS3CG1DST_XMM9_DW0,
540	BS3CG1DST_XMM10_DW0,
541	BS3CG1DST_XMM11_DW0,
542	BS3CG1DST_XMM12_DW0,
543	BS3CG1DST_XMM13_DW0,
544	BS3CG1DST_XMM14_DW0,
545	BS3CG1DST_XMM15_DW0,
546	BS3CG1DST_XMM0_DW0_ZX,
547	BS3CG1DST_XMM1_DW0_ZX,
548	BS3CG1DST_XMM2_DW0_ZX,
549	BS3CG1DST_XMM3_DW0_ZX,
550	BS3CG1DST_XMM4_DW0_ZX,
551	BS3CG1DST_XMM5_DW0_ZX,
552	BS3CG1DST_XMM6_DW0_ZX,
553	BS3CG1DST_XMM7_DW0_ZX,
554	BS3CG1DST_XMM8_DW0_ZX,
555	BS3CG1DST_XMM9_DW0_ZX,
556	BS3CG1DST_XMM10_DW0_ZX,
557	BS3CG1DST_XMM11_DW0_ZX,
558	BS3CG1DST_XMM12_DW0_ZX,
559	BS3CG1DST_XMM13_DW0_ZX,
560	BS3CG1DST_XMM14_DW0_ZX,
561	BS3CG1DST_XMM15_DW0_ZX,
562	/* AVX registers. */
563	BS3CG1DST_YMM0,
564	BS3CG1DST_YMM1,
565	BS3CG1DST_YMM2,
566	BS3CG1DST_YMM3,
567	BS3CG1DST_YMM4,
568	BS3CG1DST_YMM5,
569	BS3CG1DST_YMM6,
570	BS3CG1DST_YMM7,
571	BS3CG1DST_YMM8,
572	BS3CG1DST_YMM9,
573	BS3CG1DST_YMM10,
574	BS3CG1DST_YMM11,
575	BS3CG1DST_YMM12,
576	BS3CG1DST_YMM13,
577	BS3CG1DST_YMM14,
578	BS3CG1DST_YMM15,
579
580	/* Special fields: */
581	BS3CG1DST_SPECIAL_START,
582	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
583
584	BS3CG1DST_END
585	} BS3CG1DST;
586	AssertCompile(BS3CG1DST_END <= 256);
587
588	/** @name Selector opcode definitions.
589	*
590	* Selector programs are very simple, they are zero or more predicate tests
591	* that are ANDed together. If a predicate test fails, the test is skipped.
592	*
593	* One instruction is encoded as byte, where the first bit indicates what kind
594	* of test and the 7 remaining bits indicates which predicate to check.
595	*
596	* @{ */
597	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
598	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
599	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
600	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
601	/** @} */
602
603	/**
604	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
605	*/
606	typedef enum BS3CG1PRED
607	{
608	BS3CG1PRED_INVALID = 0,
609
610	/* Operand size. */
611	BS3CG1PRED_SIZE_O16,
612	BS3CG1PRED_SIZE_O32,
613	BS3CG1PRED_SIZE_O64,
614	/* Execution ring. */
615	BS3CG1PRED_RING_0,
616	BS3CG1PRED_RING_1,
617	BS3CG1PRED_RING_2,
618	BS3CG1PRED_RING_3,
619	BS3CG1PRED_RING_0_THRU_2,
620	BS3CG1PRED_RING_1_THRU_3,
621	/* Basic code mode. */
622	BS3CG1PRED_CODE_64BIT,
623	BS3CG1PRED_CODE_32BIT,
624	BS3CG1PRED_CODE_16BIT,
625	/* CPU modes. */
626	BS3CG1PRED_MODE_REAL,
627	BS3CG1PRED_MODE_PROT,
628	BS3CG1PRED_MODE_LONG,
629	BS3CG1PRED_MODE_V86,
630	BS3CG1PRED_MODE_SMM,
631	BS3CG1PRED_MODE_VMX,
632	BS3CG1PRED_MODE_SVM,
633	/* Paging on/off */
634	BS3CG1PRED_PAGING_ON,
635	BS3CG1PRED_PAGING_OFF,
636	/* CPU Vendors. */
637	BS3CG1PRED_VENDOR_AMD,
638	BS3CG1PRED_VENDOR_INTEL,
639	BS3CG1PRED_VENDOR_VIA,
640
641	BS3CG1PRED_END
642	} BS3CG1PRED;
643
644
645	/** The test instructions (generated). */
646	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
647	/** The number of test instructions (generated). */
648	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
649	/** The mnemonics (generated).
650	* Variable length sequence of mnemonics that runs in parallel to
651	* g_aBs3Cg1Instructions. */
652	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
653	/** The opcodes (generated).
654	* Variable length sequence of opcode bytes that runs in parallel to
655	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
656	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
657	/** The operands (generated).
658	* Variable length sequence of opcode values (BS3CG1OP) that runs in
659	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
660	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
661	/** The test data that BS3CG1INSTR.
662	* In order to simplify generating these, we use a byte array. */
663	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
664
665
666	#endif
667

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66791

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