bs3-cpu-generated-1.h@ 66815

Last change on this file since 66815 was 66815, checked in by vboxsync, 8 years ago
IEM: s/V$[a-z]*$ZxReg/V\1ZxReg/g because 'V' can only indicate a register so the 'Reg' part is superfluous.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.2 KB

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1	/* $Id: bs3-cpu-generated-1.h 66815 2017-05-05 19:35:39Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wss_WO,
48	BS3CG1OP_Wsd,
49	BS3CG1OP_Wsd_WO,
50	BS3CG1OP_Wps,
51	BS3CG1OP_Wps_WO,
52	BS3CG1OP_Wpd,
53	BS3CG1OP_Wpd_WO,
54	BS3CG1OP_Wdq,
55	BS3CG1OP_Wdq_WO,
56	BS3CG1OP_Wq,
57	BS3CG1OP_Wq_WO,
58	BS3CG1OP_WqZxReg_WO,
59
60	BS3CG1OP_Gb,
61	BS3CG1OP_Gv,
62	BS3CG1OP_Gv_RO,
63	BS3CG1OP_Nq,
64	BS3CG1OP_Pq_WO,
65	BS3CG1OP_Uq,
66	BS3CG1OP_UqHi,
67	BS3CG1OP_Vss,
68	BS3CG1OP_Vss_WO,
69	BS3CG1OP_VssZx_WO,
70	BS3CG1OP_Vsd,
71	BS3CG1OP_Vsd_WO,
72	BS3CG1OP_VsdZx_WO,
73	BS3CG1OP_Vps,
74	BS3CG1OP_Vps_WO,
75	BS3CG1OP_Vpd,
76	BS3CG1OP_Vpd_WO,
77	BS3CG1OP_Vq,
78	BS3CG1OP_Vq_WO,
79	BS3CG1OP_Vdq,
80	BS3CG1OP_Vdq_WO,
81	BS3CG1OP_VqHi,
82	BS3CG1OP_VqHi_WO,
83	BS3CG1OP_VqZx_WO,
84
85	BS3CG1OP_Ib,
86	BS3CG1OP_Iz,
87
88	BS3CG1OP_AL,
89	BS3CG1OP_rAX,
90
91	BS3CG1OP_Ma,
92	BS3CG1OP_Mb_RO,
93	BS3CG1OP_Md_RO,
94	BS3CG1OP_Md_WO,
95	BS3CG1OP_Mq,
96	BS3CG1OP_Mq_WO,
97
98	BS3CG1OP_END
99	} BS3CG1OP;
100	/** Pointer to a const operand enum. */
101	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
102
103
104	/**
105	* Instruction encoding format.
106	*
107	* This duplicates some of the info in the operand array, however it makes it
108	* easier to figure out encoding variations.
109	*/
110	typedef enum BS3CG1ENC
111	{
112	BS3CG1ENC_INVALID = 0,
113
114	BS3CG1ENC_MODRM_Eb_Gb,
115	BS3CG1ENC_MODRM_Ev_Gv,
116	BS3CG1ENC_MODRM_Wss_WO_Vss,
117	BS3CG1ENC_MODRM_Wsd_WO_Vsd,
118	BS3CG1ENC_MODRM_Wps_WO_Vps,
119	BS3CG1ENC_MODRM_Wpd_WO_Vpd,
120	BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
121
122	BS3CG1ENC_MODRM_Gb_Eb,
123	BS3CG1ENC_MODRM_Gv_Ev,
124	BS3CG1ENC_MODRM_Gv_RO_Ma, /*< bound instruction /
125	BS3CG1ENC_MODRM_Pq_WO_Uq,
126	BS3CG1ENC_MODRM_Vq_WO_UqHi,
127	BS3CG1ENC_MODRM_Vq_WO_Mq,
128	BS3CG1ENC_MODRM_VqHi_WO_Uq,
129	BS3CG1ENC_MODRM_VqHi_WO_Mq,
130	BS3CG1ENC_MODRM_Vdq_WO_Wdq,
131	BS3CG1ENC_MODRM_Vpd_WO_Wpd,
132	BS3CG1ENC_MODRM_Vps_WO_Wps,
133	BS3CG1ENC_MODRM_VssZx_WO_Wss,
134	BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
135	BS3CG1ENC_MODRM_VqZx_WO_Wq,
136	BS3CG1ENC_MODRM_VqZx_WO_Nq,
137	BS3CG1ENC_MODRM_Mb_RO,
138	BS3CG1ENC_MODRM_Md_RO,
139	BS3CG1ENC_MODRM_Md_WO,
140	BS3CG1ENC_MODRM_Mq_WO_Vq,
141	BS3CG1ENC_MODRM_Mq_WO_VqHi,
142
143	BS3CG1ENC_VEX_MODRM_Md_WO,
144
145	BS3CG1ENC_FIXED,
146	BS3CG1ENC_FIXED_AL_Ib,
147	BS3CG1ENC_FIXED_rAX_Iz,
148
149	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
150	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
151
152	BS3CG1ENC_END
153	} BS3CG1ENC;
154
155
156	/**
157	* Prefix sensitivitiy kind.
158	*/
159	typedef enum BS3CG1PFXKIND
160	{
161	BS3CG1PFXKIND_INVALID = 0,
162
163	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
164	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
165	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
166	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
167
168	/** @todo more work to be done here... */
169	BS3CG1PFXKIND_MODRM,
170	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
171
172	BS3CG1PFXKIND_END
173	} BS3CG1PFXKIND;
174
175	/**
176	* CPU selection or CPU ID.
177	*/
178	typedef enum BS3CG1CPU
179	{
180	/** Works with an CPU. */
181	BS3CG1CPU_ANY = 0,
182	BS3CG1CPU_GE_80186,
183	BS3CG1CPU_GE_80286,
184	BS3CG1CPU_GE_80386,
185	BS3CG1CPU_GE_80486,
186	BS3CG1CPU_GE_Pentium,
187
188	BS3CG1CPU_SSE,
189	BS3CG1CPU_SSE2,
190	BS3CG1CPU_SSE3,
191	BS3CG1CPU_AVX,
192	BS3CG1CPU_AVX2,
193	BS3CG1CPU_CLFSH,
194	BS3CG1CPU_CLFLUSHOPT,
195
196	BS3CG1CPU_END
197	} BS3CG1CPU;
198
199
200	/**
201	* SSE & AVX exception types.
202	*/
203	typedef enum BS3CG1XCPTTYPE
204	{
205	BS3CG1XCPTTYPE_NONE = 0,
206	/* SSE: */
207	BS3CG1XCPTTYPE_1,
208	BS3CG1XCPTTYPE_2,
209	BS3CG1XCPTTYPE_3,
210	BS3CG1XCPTTYPE_4,
211	BS3CG1XCPTTYPE_4UA,
212	BS3CG1XCPTTYPE_5,
213	BS3CG1XCPTTYPE_6,
214	BS3CG1XCPTTYPE_7,
215	BS3CG1XCPTTYPE_8,
216	BS3CG1XCPTTYPE_11,
217	BS3CG1XCPTTYPE_12,
218	/* EVEX: */
219	BS3CG1XCPTTYPE_E1,
220	BS3CG1XCPTTYPE_E1NF,
221	BS3CG1XCPTTYPE_E2,
222	BS3CG1XCPTTYPE_E3,
223	BS3CG1XCPTTYPE_E3NF,
224	BS3CG1XCPTTYPE_E4,
225	BS3CG1XCPTTYPE_E4NF,
226	BS3CG1XCPTTYPE_E5,
227	BS3CG1XCPTTYPE_E5NF,
228	BS3CG1XCPTTYPE_E6,
229	BS3CG1XCPTTYPE_E6NF,
230	BS3CG1XCPTTYPE_E7NF,
231	BS3CG1XCPTTYPE_E9,
232	BS3CG1XCPTTYPE_E9NF,
233	BS3CG1XCPTTYPE_E10,
234	BS3CG1XCPTTYPE_E11,
235	BS3CG1XCPTTYPE_E12,
236	BS3CG1XCPTTYPE_E12NF,
237	BS3CG1XCPTTYPE_END
238	} BS3CG1XCPTTYPE;
239	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
240
241
242	/**
243	* Generated instruction info.
244	*/
245	typedef struct BS3CG1INSTR
246	{
247	/** The opcode size. */
248	uint32_t cbOpcodes : 2;
249	/** The number of operands. */
250	uint32_t cOperands : 2;
251	/** The length of the mnemonic. */
252	uint32_t cchMnemonic : 4;
253	/** Whether to advance the mnemonic array pointer. */
254	uint32_t fAdvanceMnemonic : 1;
255	/** Offset into g_abBs3Cg1Tests of the first test. */
256	uint32_t offTests : 23;
257	/** BS3CG1ENC values. */
258	uint32_t enmEncoding : 10;
259	/** BS3CG1PFXKIND values. */
260	uint32_t enmPrefixKind : 4;
261	/** CPU test / CPU ID bit test (BS3CG1CPU). */
262	uint32_t enmCpuTest : 6;
263	/** Exception type (BS3CG1XCPTTYPE) */
264	uint32_t enmXcptType : 5;
265	/** Currently unused bits. */
266	uint32_t uUnused : 6;
267	/** BS3CG1INSTR_F_XXX. */
268	uint32_t fFlags;
269	} BS3CG1INSTR;
270	AssertCompileSize(BS3CG1INSTR, 12);
271	/** Pointer to a const instruction. */
272	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
273
274
275	/** @name BS3CG1INSTR_F_XXX
276	* @{ */
277	/** Defaults to SS rather than DS. */
278	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
279	/** Invalid instruction in 64-bit mode. */
280	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
281	/** Unused instruction. */
282	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
283	/** Invalid instruction. */
284	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
285	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
286	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
287	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
288	/** @} */
289
290
291	/**
292	* Test header.
293	*/
294	typedef struct BS3CG1TESTHDR
295	{
296	/** The size of the selector program in bytes.
297	* This is also the offset of the input context modification program. */
298	uint32_t cbSelector : 8;
299	/** The size of the input context modification program in bytes.
300	* This immediately follows the selector program. */
301	uint32_t cbInput : 12;
302	/** The size of the output context modification program in bytes.
303	* This immediately follows the input context modification program. The
304	* program takes the result of the input program as starting point. */
305	uint32_t cbOutput : 11;
306	/** Indicates whether this is the last test or not. */
307	uint32_t fLast : 1;
308	} BS3CG1TESTHDR;
309	AssertCompileSize(BS3CG1TESTHDR, 4);
310	/** Pointer to a const test header. */
311	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
312
313	/** @name Opcode format for the BS3CG1 context modifier.
314	*
315	* Used by both the input and output context programs.
316	*
317	* The most common operations are encoded as a single byte opcode followed by
318	* one or more immediate bytes with data.
319	*
320	* @{ */
321	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
322	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
323	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
324	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
325	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
326	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
327	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
328	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
329	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
330
331	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
332	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
333	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
334	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
335	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
336
337	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
338
339	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
340	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
341	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
342	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
343	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
344	/** @} */
345
346	/**
347	* Escaped destination values
348	*
349	* These are just uppercased versions of TestInOut.kdFields, where dots are
350	* replaced by underscores.
351	*/
352	typedef enum BS3CG1DST
353	{
354	BS3CG1DST_INVALID = 0,
355	/* Operands. */
356	BS3CG1DST_OP1,
357	BS3CG1DST_OP2,
358	BS3CG1DST_OP3,
359	BS3CG1DST_OP4,
360	/* Flags. */
361	BS3CG1DST_EFL,
362	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
363	/* 8-bit GPRs. */
364	BS3CG1DST_AL,
365	BS3CG1DST_CL,
366	BS3CG1DST_DL,
367	BS3CG1DST_BL,
368	BS3CG1DST_AH,
369	BS3CG1DST_CH,
370	BS3CG1DST_DH,
371	BS3CG1DST_BH,
372	BS3CG1DST_SPL,
373	BS3CG1DST_BPL,
374	BS3CG1DST_SIL,
375	BS3CG1DST_DIL,
376	BS3CG1DST_R8L,
377	BS3CG1DST_R9L,
378	BS3CG1DST_R10L,
379	BS3CG1DST_R11L,
380	BS3CG1DST_R12L,
381	BS3CG1DST_R13L,
382	BS3CG1DST_R14L,
383	BS3CG1DST_R15L,
384	/* 16-bit GPRs. */
385	BS3CG1DST_AX,
386	BS3CG1DST_CX,
387	BS3CG1DST_DX,
388	BS3CG1DST_BX,
389	BS3CG1DST_SP,
390	BS3CG1DST_BP,
391	BS3CG1DST_SI,
392	BS3CG1DST_DI,
393	BS3CG1DST_R8W,
394	BS3CG1DST_R9W,
395	BS3CG1DST_R10W,
396	BS3CG1DST_R11W,
397	BS3CG1DST_R12W,
398	BS3CG1DST_R13W,
399	BS3CG1DST_R14W,
400	BS3CG1DST_R15W,
401	/* 32-bit GPRs. */
402	BS3CG1DST_EAX,
403	BS3CG1DST_ECX,
404	BS3CG1DST_EDX,
405	BS3CG1DST_EBX,
406	BS3CG1DST_ESP,
407	BS3CG1DST_EBP,
408	BS3CG1DST_ESI,
409	BS3CG1DST_EDI,
410	BS3CG1DST_R8D,
411	BS3CG1DST_R9D,
412	BS3CG1DST_R10D,
413	BS3CG1DST_R11D,
414	BS3CG1DST_R12D,
415	BS3CG1DST_R13D,
416	BS3CG1DST_R14D,
417	BS3CG1DST_R15D,
418	/* 64-bit GPRs. */
419	BS3CG1DST_RAX,
420	BS3CG1DST_RCX,
421	BS3CG1DST_RDX,
422	BS3CG1DST_RBX,
423	BS3CG1DST_RSP,
424	BS3CG1DST_RBP,
425	BS3CG1DST_RSI,
426	BS3CG1DST_RDI,
427	BS3CG1DST_R8,
428	BS3CG1DST_R9,
429	BS3CG1DST_R10,
430	BS3CG1DST_R11,
431	BS3CG1DST_R12,
432	BS3CG1DST_R13,
433	BS3CG1DST_R14,
434	BS3CG1DST_R15,
435	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
436	BS3CG1DST_OZ_RAX,
437	BS3CG1DST_OZ_RCX,
438	BS3CG1DST_OZ_RDX,
439	BS3CG1DST_OZ_RBX,
440	BS3CG1DST_OZ_RSP,
441	BS3CG1DST_OZ_RBP,
442	BS3CG1DST_OZ_RSI,
443	BS3CG1DST_OZ_RDI,
444	BS3CG1DST_OZ_R8,
445	BS3CG1DST_OZ_R9,
446	BS3CG1DST_OZ_R10,
447	BS3CG1DST_OZ_R11,
448	BS3CG1DST_OZ_R12,
449	BS3CG1DST_OZ_R13,
450	BS3CG1DST_OZ_R14,
451	BS3CG1DST_OZ_R15,
452
453	/* Control registers.*/
454	BS3CG1DST_CR0,
455	BS3CG1DST_CR4,
456	BS3CG1DST_XCR0,
457
458	/* FPU registers. */
459	BS3CG1DST_FPU_FIRST,
460	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
461	BS3CG1DST_FSW,
462	BS3CG1DST_FTW,
463	BS3CG1DST_FOP,
464	BS3CG1DST_FPUIP,
465	BS3CG1DST_FPUCS,
466	BS3CG1DST_FPUDP,
467	BS3CG1DST_FPUDS,
468	BS3CG1DST_MXCSR,
469	BS3CG1DST_ST0,
470	BS3CG1DST_ST1,
471	BS3CG1DST_ST2,
472	BS3CG1DST_ST3,
473	BS3CG1DST_ST4,
474	BS3CG1DST_ST5,
475	BS3CG1DST_ST6,
476	BS3CG1DST_ST7,
477	/* MMX registers. */
478	BS3CG1DST_MM0,
479	BS3CG1DST_MM1,
480	BS3CG1DST_MM2,
481	BS3CG1DST_MM3,
482	BS3CG1DST_MM4,
483	BS3CG1DST_MM5,
484	BS3CG1DST_MM6,
485	BS3CG1DST_MM7,
486	/* SSE registers. */
487	BS3CG1DST_XMM0,
488	BS3CG1DST_XMM1,
489	BS3CG1DST_XMM2,
490	BS3CG1DST_XMM3,
491	BS3CG1DST_XMM4,
492	BS3CG1DST_XMM5,
493	BS3CG1DST_XMM6,
494	BS3CG1DST_XMM7,
495	BS3CG1DST_XMM8,
496	BS3CG1DST_XMM9,
497	BS3CG1DST_XMM10,
498	BS3CG1DST_XMM11,
499	BS3CG1DST_XMM12,
500	BS3CG1DST_XMM13,
501	BS3CG1DST_XMM14,
502	BS3CG1DST_XMM15,
503	BS3CG1DST_XMM0_LO,
504	BS3CG1DST_XMM1_LO,
505	BS3CG1DST_XMM2_LO,
506	BS3CG1DST_XMM3_LO,
507	BS3CG1DST_XMM4_LO,
508	BS3CG1DST_XMM5_LO,
509	BS3CG1DST_XMM6_LO,
510	BS3CG1DST_XMM7_LO,
511	BS3CG1DST_XMM8_LO,
512	BS3CG1DST_XMM9_LO,
513	BS3CG1DST_XMM10_LO,
514	BS3CG1DST_XMM11_LO,
515	BS3CG1DST_XMM12_LO,
516	BS3CG1DST_XMM13_LO,
517	BS3CG1DST_XMM14_LO,
518	BS3CG1DST_XMM15_LO,
519	BS3CG1DST_XMM0_HI,
520	BS3CG1DST_XMM1_HI,
521	BS3CG1DST_XMM2_HI,
522	BS3CG1DST_XMM3_HI,
523	BS3CG1DST_XMM4_HI,
524	BS3CG1DST_XMM5_HI,
525	BS3CG1DST_XMM6_HI,
526	BS3CG1DST_XMM7_HI,
527	BS3CG1DST_XMM8_HI,
528	BS3CG1DST_XMM9_HI,
529	BS3CG1DST_XMM10_HI,
530	BS3CG1DST_XMM11_HI,
531	BS3CG1DST_XMM12_HI,
532	BS3CG1DST_XMM13_HI,
533	BS3CG1DST_XMM14_HI,
534	BS3CG1DST_XMM15_HI,
535	BS3CG1DST_XMM0_LO_ZX,
536	BS3CG1DST_XMM1_LO_ZX,
537	BS3CG1DST_XMM2_LO_ZX,
538	BS3CG1DST_XMM3_LO_ZX,
539	BS3CG1DST_XMM4_LO_ZX,
540	BS3CG1DST_XMM5_LO_ZX,
541	BS3CG1DST_XMM6_LO_ZX,
542	BS3CG1DST_XMM7_LO_ZX,
543	BS3CG1DST_XMM8_LO_ZX,
544	BS3CG1DST_XMM9_LO_ZX,
545	BS3CG1DST_XMM10_LO_ZX,
546	BS3CG1DST_XMM11_LO_ZX,
547	BS3CG1DST_XMM12_LO_ZX,
548	BS3CG1DST_XMM13_LO_ZX,
549	BS3CG1DST_XMM14_LO_ZX,
550	BS3CG1DST_XMM15_LO_ZX,
551	BS3CG1DST_XMM0_DW0,
552	BS3CG1DST_XMM1_DW0,
553	BS3CG1DST_XMM2_DW0,
554	BS3CG1DST_XMM3_DW0,
555	BS3CG1DST_XMM4_DW0,
556	BS3CG1DST_XMM5_DW0,
557	BS3CG1DST_XMM6_DW0,
558	BS3CG1DST_XMM7_DW0,
559	BS3CG1DST_XMM8_DW0,
560	BS3CG1DST_XMM9_DW0,
561	BS3CG1DST_XMM10_DW0,
562	BS3CG1DST_XMM11_DW0,
563	BS3CG1DST_XMM12_DW0,
564	BS3CG1DST_XMM13_DW0,
565	BS3CG1DST_XMM14_DW0,
566	BS3CG1DST_XMM15_DW0,
567	BS3CG1DST_XMM0_DW0_ZX,
568	BS3CG1DST_XMM1_DW0_ZX,
569	BS3CG1DST_XMM2_DW0_ZX,
570	BS3CG1DST_XMM3_DW0_ZX,
571	BS3CG1DST_XMM4_DW0_ZX,
572	BS3CG1DST_XMM5_DW0_ZX,
573	BS3CG1DST_XMM6_DW0_ZX,
574	BS3CG1DST_XMM7_DW0_ZX,
575	BS3CG1DST_XMM8_DW0_ZX,
576	BS3CG1DST_XMM9_DW0_ZX,
577	BS3CG1DST_XMM10_DW0_ZX,
578	BS3CG1DST_XMM11_DW0_ZX,
579	BS3CG1DST_XMM12_DW0_ZX,
580	BS3CG1DST_XMM13_DW0_ZX,
581	BS3CG1DST_XMM14_DW0_ZX,
582	BS3CG1DST_XMM15_DW0_ZX,
583	/* AVX registers. */
584	BS3CG1DST_YMM0,
585	BS3CG1DST_YMM1,
586	BS3CG1DST_YMM2,
587	BS3CG1DST_YMM3,
588	BS3CG1DST_YMM4,
589	BS3CG1DST_YMM5,
590	BS3CG1DST_YMM6,
591	BS3CG1DST_YMM7,
592	BS3CG1DST_YMM8,
593	BS3CG1DST_YMM9,
594	BS3CG1DST_YMM10,
595	BS3CG1DST_YMM11,
596	BS3CG1DST_YMM12,
597	BS3CG1DST_YMM13,
598	BS3CG1DST_YMM14,
599	BS3CG1DST_YMM15,
600
601	/* Special fields: */
602	BS3CG1DST_SPECIAL_START,
603	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
604
605	BS3CG1DST_END
606	} BS3CG1DST;
607	AssertCompile(BS3CG1DST_END <= 256);
608
609	/** @name Selector opcode definitions.
610	*
611	* Selector programs are very simple, they are zero or more predicate tests
612	* that are ANDed together. If a predicate test fails, the test is skipped.
613	*
614	* One instruction is encoded as byte, where the first bit indicates what kind
615	* of test and the 7 remaining bits indicates which predicate to check.
616	*
617	* @{ */
618	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
619	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
620	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
621	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
622	/** @} */
623
624	/**
625	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
626	*/
627	typedef enum BS3CG1PRED
628	{
629	BS3CG1PRED_INVALID = 0,
630
631	/* Operand size. */
632	BS3CG1PRED_SIZE_O16,
633	BS3CG1PRED_SIZE_O32,
634	BS3CG1PRED_SIZE_O64,
635	/* Execution ring. */
636	BS3CG1PRED_RING_0,
637	BS3CG1PRED_RING_1,
638	BS3CG1PRED_RING_2,
639	BS3CG1PRED_RING_3,
640	BS3CG1PRED_RING_0_THRU_2,
641	BS3CG1PRED_RING_1_THRU_3,
642	/* Basic code mode. */
643	BS3CG1PRED_CODE_64BIT,
644	BS3CG1PRED_CODE_32BIT,
645	BS3CG1PRED_CODE_16BIT,
646	/* CPU modes. */
647	BS3CG1PRED_MODE_REAL,
648	BS3CG1PRED_MODE_PROT,
649	BS3CG1PRED_MODE_LONG,
650	BS3CG1PRED_MODE_V86,
651	BS3CG1PRED_MODE_SMM,
652	BS3CG1PRED_MODE_VMX,
653	BS3CG1PRED_MODE_SVM,
654	/* Paging on/off */
655	BS3CG1PRED_PAGING_ON,
656	BS3CG1PRED_PAGING_OFF,
657	/* CPU Vendors. */
658	BS3CG1PRED_VENDOR_AMD,
659	BS3CG1PRED_VENDOR_INTEL,
660	BS3CG1PRED_VENDOR_VIA,
661
662	BS3CG1PRED_END
663	} BS3CG1PRED;
664
665
666	/** The test instructions (generated). */
667	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
668	/** The number of test instructions (generated). */
669	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
670	/** The mnemonics (generated).
671	* Variable length sequence of mnemonics that runs in parallel to
672	* g_aBs3Cg1Instructions. */
673	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
674	/** The opcodes (generated).
675	* Variable length sequence of opcode bytes that runs in parallel to
676	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
677	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
678	/** The operands (generated).
679	* Variable length sequence of opcode values (BS3CG1OP) that runs in
680	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
681	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
682	/** The test data that BS3CG1INSTR.
683	* In order to simplify generating these, we use a byte array. */
684	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
685
686
687	#endif
688

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Last change on this file since 66815 was 66815, checked in by vboxsync, 8 years ago
IEM: s/V\([a-z]*\)ZxReg/V\1ZxReg/g because 'V' can only indicate a register so the 'Reg' part is superfluous.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.2 KB

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66815

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