bs3-cpu-generated-1.h@ 66906

Last change on this file since 66906 was 66906, checked in by vboxsync, 8 years ago
IEM: Implemented vmovsd Vsd,Hsd,Usd (VEX.F2.0F 10 mod=3), vmovsd Vsd,Mq (VEX.F2.0F 10 mod!=3).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.5 KB

Line
1	/* $Id: bs3-cpu-generated-1.h 66906 2017-05-16 09:58:00Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wss_WO,
48	BS3CG1OP_Wsd,
49	BS3CG1OP_Wsd_WO,
50	BS3CG1OP_Wps,
51	BS3CG1OP_Wps_WO,
52	BS3CG1OP_Wpd,
53	BS3CG1OP_Wpd_WO,
54	BS3CG1OP_Wdq,
55	BS3CG1OP_Wdq_WO,
56	BS3CG1OP_Wq,
57	BS3CG1OP_Wq_WO,
58	BS3CG1OP_WqZxReg_WO,
59
60	BS3CG1OP_Gb,
61	BS3CG1OP_Gv,
62	BS3CG1OP_Gv_RO,
63	BS3CG1OP_HdqCss,
64	BS3CG1OP_HdqCsd,
65	BS3CG1OP_Nq,
66	BS3CG1OP_Pq_WO,
67	BS3CG1OP_Uq,
68	BS3CG1OP_UqHi,
69	BS3CG1OP_Uss,
70	BS3CG1OP_Usd,
71	BS3CG1OP_Vss,
72	BS3CG1OP_Vss_WO,
73	BS3CG1OP_VssZx_WO,
74	BS3CG1OP_Vsd,
75	BS3CG1OP_Vsd_WO,
76	BS3CG1OP_VsdZx_WO,
77	BS3CG1OP_Vps,
78	BS3CG1OP_Vps_WO,
79	BS3CG1OP_Vpd,
80	BS3CG1OP_Vpd_WO,
81	BS3CG1OP_Vq,
82	BS3CG1OP_Vq_WO,
83	BS3CG1OP_Vdq,
84	BS3CG1OP_Vdq_WO,
85	BS3CG1OP_VqHi,
86	BS3CG1OP_VqHi_WO,
87	BS3CG1OP_VqZx_WO,
88
89	BS3CG1OP_Ib,
90	BS3CG1OP_Iz,
91
92	BS3CG1OP_AL,
93	BS3CG1OP_rAX,
94
95	BS3CG1OP_Ma,
96	BS3CG1OP_Mb_RO,
97	BS3CG1OP_Md_RO,
98	BS3CG1OP_Md_WO,
99	BS3CG1OP_Mq,
100	BS3CG1OP_Mq_WO,
101
102	BS3CG1OP_END
103	} BS3CG1OP;
104	/** Pointer to a const operand enum. */
105	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
106
107
108	/**
109	* Instruction encoding format.
110	*
111	* This duplicates some of the info in the operand array, however it makes it
112	* easier to figure out encoding variations.
113	*/
114	typedef enum BS3CG1ENC
115	{
116	BS3CG1ENC_INVALID = 0,
117
118	BS3CG1ENC_MODRM_Eb_Gb,
119	BS3CG1ENC_MODRM_Ev_Gv,
120	BS3CG1ENC_MODRM_Wss_WO_Vss,
121	BS3CG1ENC_MODRM_Wsd_WO_Vsd,
122	BS3CG1ENC_MODRM_Wps_WO_Vps,
123	BS3CG1ENC_MODRM_Wpd_WO_Vpd,
124	BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
125
126	BS3CG1ENC_MODRM_Gb_Eb,
127	BS3CG1ENC_MODRM_Gv_Ev,
128	BS3CG1ENC_MODRM_Gv_RO_Ma, /*< bound instruction /
129	BS3CG1ENC_MODRM_Pq_WO_Uq,
130	BS3CG1ENC_MODRM_Vq_WO_UqHi,
131	BS3CG1ENC_MODRM_Vq_WO_Mq,
132	BS3CG1ENC_MODRM_VqHi_WO_Uq,
133	BS3CG1ENC_MODRM_VqHi_WO_Mq,
134	BS3CG1ENC_MODRM_Vdq_WO_Wdq,
135	BS3CG1ENC_MODRM_Vpd_WO_Wpd,
136	BS3CG1ENC_MODRM_Vps_WO_Wps,
137	BS3CG1ENC_MODRM_VssZx_WO_Wss,
138	BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
139	BS3CG1ENC_MODRM_VqZx_WO_Wq,
140	BS3CG1ENC_MODRM_VqZx_WO_Nq,
141	BS3CG1ENC_MODRM_Mb_RO,
142	BS3CG1ENC_MODRM_Md_RO,
143	BS3CG1ENC_MODRM_Md_WO,
144	BS3CG1ENC_MODRM_Mq_WO_Vq,
145	BS3CG1ENC_MODRM_Mq_WO_VqHi,
146
147	BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
148	BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
149	BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss,
150	BS3CG1ENC_VEX_MODRM_VssZx_WO_Wss,
151	BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd,
152	BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
153	BS3CG1ENC_VEX_MODRM_Md_WO,
154
155	BS3CG1ENC_FIXED,
156	BS3CG1ENC_FIXED_AL_Ib,
157	BS3CG1ENC_FIXED_rAX_Iz,
158
159	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
160	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
161
162	BS3CG1ENC_END
163	} BS3CG1ENC;
164
165
166	/**
167	* Prefix sensitivitiy kind.
168	*/
169	typedef enum BS3CG1PFXKIND
170	{
171	BS3CG1PFXKIND_INVALID = 0,
172
173	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
174	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
175	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
176	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
177
178	/** @todo more work to be done here... */
179	BS3CG1PFXKIND_MODRM,
180	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
181
182	BS3CG1PFXKIND_END
183	} BS3CG1PFXKIND;
184
185	/**
186	* CPU selection or CPU ID.
187	*/
188	typedef enum BS3CG1CPU
189	{
190	/** Works with an CPU. */
191	BS3CG1CPU_ANY = 0,
192	BS3CG1CPU_GE_80186,
193	BS3CG1CPU_GE_80286,
194	BS3CG1CPU_GE_80386,
195	BS3CG1CPU_GE_80486,
196	BS3CG1CPU_GE_Pentium,
197
198	BS3CG1CPU_SSE,
199	BS3CG1CPU_SSE2,
200	BS3CG1CPU_SSE3,
201	BS3CG1CPU_AVX,
202	BS3CG1CPU_AVX2,
203	BS3CG1CPU_CLFSH,
204	BS3CG1CPU_CLFLUSHOPT,
205
206	BS3CG1CPU_END
207	} BS3CG1CPU;
208
209
210	/**
211	* SSE & AVX exception types.
212	*/
213	typedef enum BS3CG1XCPTTYPE
214	{
215	BS3CG1XCPTTYPE_NONE = 0,
216	/* SSE: */
217	BS3CG1XCPTTYPE_1,
218	BS3CG1XCPTTYPE_2,
219	BS3CG1XCPTTYPE_3,
220	BS3CG1XCPTTYPE_4,
221	BS3CG1XCPTTYPE_4UA,
222	BS3CG1XCPTTYPE_5,
223	BS3CG1XCPTTYPE_6,
224	BS3CG1XCPTTYPE_7,
225	BS3CG1XCPTTYPE_8,
226	BS3CG1XCPTTYPE_11,
227	BS3CG1XCPTTYPE_12,
228	/* EVEX: */
229	BS3CG1XCPTTYPE_E1,
230	BS3CG1XCPTTYPE_E1NF,
231	BS3CG1XCPTTYPE_E2,
232	BS3CG1XCPTTYPE_E3,
233	BS3CG1XCPTTYPE_E3NF,
234	BS3CG1XCPTTYPE_E4,
235	BS3CG1XCPTTYPE_E4NF,
236	BS3CG1XCPTTYPE_E5,
237	BS3CG1XCPTTYPE_E5NF,
238	BS3CG1XCPTTYPE_E6,
239	BS3CG1XCPTTYPE_E6NF,
240	BS3CG1XCPTTYPE_E7NF,
241	BS3CG1XCPTTYPE_E9,
242	BS3CG1XCPTTYPE_E9NF,
243	BS3CG1XCPTTYPE_E10,
244	BS3CG1XCPTTYPE_E11,
245	BS3CG1XCPTTYPE_E12,
246	BS3CG1XCPTTYPE_E12NF,
247	BS3CG1XCPTTYPE_END
248	} BS3CG1XCPTTYPE;
249	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
250
251
252	/**
253	* Generated instruction info.
254	*/
255	typedef struct BS3CG1INSTR
256	{
257	/** The opcode size. */
258	uint32_t cbOpcodes : 2;
259	/** The number of operands. */
260	uint32_t cOperands : 2;
261	/** The length of the mnemonic. */
262	uint32_t cchMnemonic : 4;
263	/** Whether to advance the mnemonic array pointer. */
264	uint32_t fAdvanceMnemonic : 1;
265	/** Offset into g_abBs3Cg1Tests of the first test. */
266	uint32_t offTests : 23;
267	/** BS3CG1ENC values. */
268	uint32_t enmEncoding : 10;
269	/** BS3CG1PFXKIND values. */
270	uint32_t enmPrefixKind : 4;
271	/** CPU test / CPU ID bit test (BS3CG1CPU). */
272	uint32_t enmCpuTest : 6;
273	/** Exception type (BS3CG1XCPTTYPE) */
274	uint32_t enmXcptType : 5;
275	/** Currently unused bits. */
276	uint32_t uUnused : 6;
277	/** BS3CG1INSTR_F_XXX. */
278	uint32_t fFlags;
279	} BS3CG1INSTR;
280	AssertCompileSize(BS3CG1INSTR, 12);
281	/** Pointer to a const instruction. */
282	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
283
284
285	/** @name BS3CG1INSTR_F_XXX
286	* @{ */
287	/** Defaults to SS rather than DS. */
288	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
289	/** Invalid instruction in 64-bit mode. */
290	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
291	/** Unused instruction. */
292	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
293	/** Invalid instruction. */
294	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
295	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
296	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
297	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
298	/** @} */
299
300
301	/**
302	* Test header.
303	*/
304	typedef struct BS3CG1TESTHDR
305	{
306	/** The size of the selector program in bytes.
307	* This is also the offset of the input context modification program. */
308	uint32_t cbSelector : 8;
309	/** The size of the input context modification program in bytes.
310	* This immediately follows the selector program. */
311	uint32_t cbInput : 12;
312	/** The size of the output context modification program in bytes.
313	* This immediately follows the input context modification program. The
314	* program takes the result of the input program as starting point. */
315	uint32_t cbOutput : 11;
316	/** Indicates whether this is the last test or not. */
317	uint32_t fLast : 1;
318	} BS3CG1TESTHDR;
319	AssertCompileSize(BS3CG1TESTHDR, 4);
320	/** Pointer to a const test header. */
321	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
322
323	/** @name Opcode format for the BS3CG1 context modifier.
324	*
325	* Used by both the input and output context programs.
326	*
327	* The most common operations are encoded as a single byte opcode followed by
328	* one or more immediate bytes with data.
329	*
330	* @{ */
331	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
332	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
333	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
334	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
335	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
336	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
337	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
338	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
339	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
340
341	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
342	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
343	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
344	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
345	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
346
347	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
348
349	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
350	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
351	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
352	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
353	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
354	/** @} */
355
356	/**
357	* Escaped destination values
358	*
359	* These are just uppercased versions of TestInOut.kdFields, where dots are
360	* replaced by underscores.
361	*/
362	typedef enum BS3CG1DST
363	{
364	BS3CG1DST_INVALID = 0,
365	/* Operands. */
366	BS3CG1DST_OP1,
367	BS3CG1DST_OP2,
368	BS3CG1DST_OP3,
369	BS3CG1DST_OP4,
370	/* Flags. */
371	BS3CG1DST_EFL,
372	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
373	/* 8-bit GPRs. */
374	BS3CG1DST_AL,
375	BS3CG1DST_CL,
376	BS3CG1DST_DL,
377	BS3CG1DST_BL,
378	BS3CG1DST_AH,
379	BS3CG1DST_CH,
380	BS3CG1DST_DH,
381	BS3CG1DST_BH,
382	BS3CG1DST_SPL,
383	BS3CG1DST_BPL,
384	BS3CG1DST_SIL,
385	BS3CG1DST_DIL,
386	BS3CG1DST_R8L,
387	BS3CG1DST_R9L,
388	BS3CG1DST_R10L,
389	BS3CG1DST_R11L,
390	BS3CG1DST_R12L,
391	BS3CG1DST_R13L,
392	BS3CG1DST_R14L,
393	BS3CG1DST_R15L,
394	/* 16-bit GPRs. */
395	BS3CG1DST_AX,
396	BS3CG1DST_CX,
397	BS3CG1DST_DX,
398	BS3CG1DST_BX,
399	BS3CG1DST_SP,
400	BS3CG1DST_BP,
401	BS3CG1DST_SI,
402	BS3CG1DST_DI,
403	BS3CG1DST_R8W,
404	BS3CG1DST_R9W,
405	BS3CG1DST_R10W,
406	BS3CG1DST_R11W,
407	BS3CG1DST_R12W,
408	BS3CG1DST_R13W,
409	BS3CG1DST_R14W,
410	BS3CG1DST_R15W,
411	/* 32-bit GPRs. */
412	BS3CG1DST_EAX,
413	BS3CG1DST_ECX,
414	BS3CG1DST_EDX,
415	BS3CG1DST_EBX,
416	BS3CG1DST_ESP,
417	BS3CG1DST_EBP,
418	BS3CG1DST_ESI,
419	BS3CG1DST_EDI,
420	BS3CG1DST_R8D,
421	BS3CG1DST_R9D,
422	BS3CG1DST_R10D,
423	BS3CG1DST_R11D,
424	BS3CG1DST_R12D,
425	BS3CG1DST_R13D,
426	BS3CG1DST_R14D,
427	BS3CG1DST_R15D,
428	/* 64-bit GPRs. */
429	BS3CG1DST_RAX,
430	BS3CG1DST_RCX,
431	BS3CG1DST_RDX,
432	BS3CG1DST_RBX,
433	BS3CG1DST_RSP,
434	BS3CG1DST_RBP,
435	BS3CG1DST_RSI,
436	BS3CG1DST_RDI,
437	BS3CG1DST_R8,
438	BS3CG1DST_R9,
439	BS3CG1DST_R10,
440	BS3CG1DST_R11,
441	BS3CG1DST_R12,
442	BS3CG1DST_R13,
443	BS3CG1DST_R14,
444	BS3CG1DST_R15,
445	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
446	BS3CG1DST_OZ_RAX,
447	BS3CG1DST_OZ_RCX,
448	BS3CG1DST_OZ_RDX,
449	BS3CG1DST_OZ_RBX,
450	BS3CG1DST_OZ_RSP,
451	BS3CG1DST_OZ_RBP,
452	BS3CG1DST_OZ_RSI,
453	BS3CG1DST_OZ_RDI,
454	BS3CG1DST_OZ_R8,
455	BS3CG1DST_OZ_R9,
456	BS3CG1DST_OZ_R10,
457	BS3CG1DST_OZ_R11,
458	BS3CG1DST_OZ_R12,
459	BS3CG1DST_OZ_R13,
460	BS3CG1DST_OZ_R14,
461	BS3CG1DST_OZ_R15,
462
463	/* Control registers.*/
464	BS3CG1DST_CR0,
465	BS3CG1DST_CR4,
466	BS3CG1DST_XCR0,
467
468	/* FPU registers. */
469	BS3CG1DST_FPU_FIRST,
470	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
471	BS3CG1DST_FSW,
472	BS3CG1DST_FTW,
473	BS3CG1DST_FOP,
474	BS3CG1DST_FPUIP,
475	BS3CG1DST_FPUCS,
476	BS3CG1DST_FPUDP,
477	BS3CG1DST_FPUDS,
478	BS3CG1DST_MXCSR,
479	BS3CG1DST_ST0,
480	BS3CG1DST_ST1,
481	BS3CG1DST_ST2,
482	BS3CG1DST_ST3,
483	BS3CG1DST_ST4,
484	BS3CG1DST_ST5,
485	BS3CG1DST_ST6,
486	BS3CG1DST_ST7,
487	/* MMX registers. */
488	BS3CG1DST_MM0,
489	BS3CG1DST_MM1,
490	BS3CG1DST_MM2,
491	BS3CG1DST_MM3,
492	BS3CG1DST_MM4,
493	BS3CG1DST_MM5,
494	BS3CG1DST_MM6,
495	BS3CG1DST_MM7,
496	/* SSE registers. */
497	BS3CG1DST_XMM0,
498	BS3CG1DST_XMM1,
499	BS3CG1DST_XMM2,
500	BS3CG1DST_XMM3,
501	BS3CG1DST_XMM4,
502	BS3CG1DST_XMM5,
503	BS3CG1DST_XMM6,
504	BS3CG1DST_XMM7,
505	BS3CG1DST_XMM8,
506	BS3CG1DST_XMM9,
507	BS3CG1DST_XMM10,
508	BS3CG1DST_XMM11,
509	BS3CG1DST_XMM12,
510	BS3CG1DST_XMM13,
511	BS3CG1DST_XMM14,
512	BS3CG1DST_XMM15,
513	BS3CG1DST_XMM0_LO,
514	BS3CG1DST_XMM1_LO,
515	BS3CG1DST_XMM2_LO,
516	BS3CG1DST_XMM3_LO,
517	BS3CG1DST_XMM4_LO,
518	BS3CG1DST_XMM5_LO,
519	BS3CG1DST_XMM6_LO,
520	BS3CG1DST_XMM7_LO,
521	BS3CG1DST_XMM8_LO,
522	BS3CG1DST_XMM9_LO,
523	BS3CG1DST_XMM10_LO,
524	BS3CG1DST_XMM11_LO,
525	BS3CG1DST_XMM12_LO,
526	BS3CG1DST_XMM13_LO,
527	BS3CG1DST_XMM14_LO,
528	BS3CG1DST_XMM15_LO,
529	BS3CG1DST_XMM0_HI,
530	BS3CG1DST_XMM1_HI,
531	BS3CG1DST_XMM2_HI,
532	BS3CG1DST_XMM3_HI,
533	BS3CG1DST_XMM4_HI,
534	BS3CG1DST_XMM5_HI,
535	BS3CG1DST_XMM6_HI,
536	BS3CG1DST_XMM7_HI,
537	BS3CG1DST_XMM8_HI,
538	BS3CG1DST_XMM9_HI,
539	BS3CG1DST_XMM10_HI,
540	BS3CG1DST_XMM11_HI,
541	BS3CG1DST_XMM12_HI,
542	BS3CG1DST_XMM13_HI,
543	BS3CG1DST_XMM14_HI,
544	BS3CG1DST_XMM15_HI,
545	BS3CG1DST_XMM0_LO_ZX,
546	BS3CG1DST_XMM1_LO_ZX,
547	BS3CG1DST_XMM2_LO_ZX,
548	BS3CG1DST_XMM3_LO_ZX,
549	BS3CG1DST_XMM4_LO_ZX,
550	BS3CG1DST_XMM5_LO_ZX,
551	BS3CG1DST_XMM6_LO_ZX,
552	BS3CG1DST_XMM7_LO_ZX,
553	BS3CG1DST_XMM8_LO_ZX,
554	BS3CG1DST_XMM9_LO_ZX,
555	BS3CG1DST_XMM10_LO_ZX,
556	BS3CG1DST_XMM11_LO_ZX,
557	BS3CG1DST_XMM12_LO_ZX,
558	BS3CG1DST_XMM13_LO_ZX,
559	BS3CG1DST_XMM14_LO_ZX,
560	BS3CG1DST_XMM15_LO_ZX,
561	BS3CG1DST_XMM0_DW0,
562	BS3CG1DST_XMM1_DW0,
563	BS3CG1DST_XMM2_DW0,
564	BS3CG1DST_XMM3_DW0,
565	BS3CG1DST_XMM4_DW0,
566	BS3CG1DST_XMM5_DW0,
567	BS3CG1DST_XMM6_DW0,
568	BS3CG1DST_XMM7_DW0,
569	BS3CG1DST_XMM8_DW0,
570	BS3CG1DST_XMM9_DW0,
571	BS3CG1DST_XMM10_DW0,
572	BS3CG1DST_XMM11_DW0,
573	BS3CG1DST_XMM12_DW0,
574	BS3CG1DST_XMM13_DW0,
575	BS3CG1DST_XMM14_DW0,
576	BS3CG1DST_XMM15_DW0,
577	BS3CG1DST_XMM0_DW0_ZX,
578	BS3CG1DST_XMM1_DW0_ZX,
579	BS3CG1DST_XMM2_DW0_ZX,
580	BS3CG1DST_XMM3_DW0_ZX,
581	BS3CG1DST_XMM4_DW0_ZX,
582	BS3CG1DST_XMM5_DW0_ZX,
583	BS3CG1DST_XMM6_DW0_ZX,
584	BS3CG1DST_XMM7_DW0_ZX,
585	BS3CG1DST_XMM8_DW0_ZX,
586	BS3CG1DST_XMM9_DW0_ZX,
587	BS3CG1DST_XMM10_DW0_ZX,
588	BS3CG1DST_XMM11_DW0_ZX,
589	BS3CG1DST_XMM12_DW0_ZX,
590	BS3CG1DST_XMM13_DW0_ZX,
591	BS3CG1DST_XMM14_DW0_ZX,
592	BS3CG1DST_XMM15_DW0_ZX,
593	/* AVX registers. */
594	BS3CG1DST_YMM0,
595	BS3CG1DST_YMM1,
596	BS3CG1DST_YMM2,
597	BS3CG1DST_YMM3,
598	BS3CG1DST_YMM4,
599	BS3CG1DST_YMM5,
600	BS3CG1DST_YMM6,
601	BS3CG1DST_YMM7,
602	BS3CG1DST_YMM8,
603	BS3CG1DST_YMM9,
604	BS3CG1DST_YMM10,
605	BS3CG1DST_YMM11,
606	BS3CG1DST_YMM12,
607	BS3CG1DST_YMM13,
608	BS3CG1DST_YMM14,
609	BS3CG1DST_YMM15,
610
611	/* Special fields: */
612	BS3CG1DST_SPECIAL_START,
613	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
614
615	BS3CG1DST_END
616	} BS3CG1DST;
617	AssertCompile(BS3CG1DST_END <= 256);
618
619	/** @name Selector opcode definitions.
620	*
621	* Selector programs are very simple, they are zero or more predicate tests
622	* that are ANDed together. If a predicate test fails, the test is skipped.
623	*
624	* One instruction is encoded as byte, where the first bit indicates what kind
625	* of test and the 7 remaining bits indicates which predicate to check.
626	*
627	* @{ */
628	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
629	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
630	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
631	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
632	/** @} */
633
634	/**
635	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
636	*/
637	typedef enum BS3CG1PRED
638	{
639	BS3CG1PRED_INVALID = 0,
640
641	/* Operand size. */
642	BS3CG1PRED_SIZE_O16,
643	BS3CG1PRED_SIZE_O32,
644	BS3CG1PRED_SIZE_O64,
645	/* Execution ring. */
646	BS3CG1PRED_RING_0,
647	BS3CG1PRED_RING_1,
648	BS3CG1PRED_RING_2,
649	BS3CG1PRED_RING_3,
650	BS3CG1PRED_RING_0_THRU_2,
651	BS3CG1PRED_RING_1_THRU_3,
652	/* Basic code mode. */
653	BS3CG1PRED_CODE_64BIT,
654	BS3CG1PRED_CODE_32BIT,
655	BS3CG1PRED_CODE_16BIT,
656	/* CPU modes. */
657	BS3CG1PRED_MODE_REAL,
658	BS3CG1PRED_MODE_PROT,
659	BS3CG1PRED_MODE_LONG,
660	BS3CG1PRED_MODE_V86,
661	BS3CG1PRED_MODE_SMM,
662	BS3CG1PRED_MODE_VMX,
663	BS3CG1PRED_MODE_SVM,
664	/* Paging on/off */
665	BS3CG1PRED_PAGING_ON,
666	BS3CG1PRED_PAGING_OFF,
667	/* CPU Vendors. */
668	BS3CG1PRED_VENDOR_AMD,
669	BS3CG1PRED_VENDOR_INTEL,
670	BS3CG1PRED_VENDOR_VIA,
671
672	BS3CG1PRED_END
673	} BS3CG1PRED;
674
675
676	/** The test instructions (generated). */
677	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
678	/** The number of test instructions (generated). */
679	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
680	/** The mnemonics (generated).
681	* Variable length sequence of mnemonics that runs in parallel to
682	* g_aBs3Cg1Instructions. */
683	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
684	/** The opcodes (generated).
685	* Variable length sequence of opcode bytes that runs in parallel to
686	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
687	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
688	/** The operands (generated).
689	* Variable length sequence of opcode values (BS3CG1OP) that runs in
690	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
691	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
692	/** The test data that BS3CG1INSTR.
693	* In order to simplify generating these, we use a byte array. */
694	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
695
696
697	#endif
698

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66906

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