bs3-cpu-generated-1.h@ 66920

Last change on this file since 66920 was 66920, checked in by vboxsync, 8 years ago
IEM: Implemented movss Uss,Hss,Vss (VEX.F3.0F 11 mod=3) and movss Md,Vss (VEX.F3.0F 11 mod!=3).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 18.8 KB

Line
1	/* $Id: bs3-cpu-generated-1.h 66920 2017-05-16 19:21:21Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wss_WO,
48	BS3CG1OP_Wsd,
49	BS3CG1OP_Wsd_WO,
50	BS3CG1OP_Wps,
51	BS3CG1OP_Wps_WO,
52	BS3CG1OP_Wpd,
53	BS3CG1OP_Wpd_WO,
54	BS3CG1OP_Wdq,
55	BS3CG1OP_Wdq_WO,
56	BS3CG1OP_Wq,
57	BS3CG1OP_Wq_WO,
58	BS3CG1OP_WqZxReg_WO,
59
60	BS3CG1OP_Gb,
61	BS3CG1OP_Gv,
62	BS3CG1OP_Gv_RO,
63	BS3CG1OP_HdqCss,
64	BS3CG1OP_HdqCsd,
65	BS3CG1OP_Nq,
66	BS3CG1OP_Pq_WO,
67	BS3CG1OP_Uq,
68	BS3CG1OP_UqHi,
69	BS3CG1OP_Uss,
70	BS3CG1OP_Uss_WO,
71	BS3CG1OP_Usd,
72	BS3CG1OP_Usd_WO,
73	BS3CG1OP_Vss,
74	BS3CG1OP_Vss_WO,
75	BS3CG1OP_VssZx_WO,
76	BS3CG1OP_Vsd,
77	BS3CG1OP_Vsd_WO,
78	BS3CG1OP_VsdZx_WO,
79	BS3CG1OP_Vps,
80	BS3CG1OP_Vps_WO,
81	BS3CG1OP_Vpd,
82	BS3CG1OP_Vpd_WO,
83	BS3CG1OP_Vq,
84	BS3CG1OP_Vq_WO,
85	BS3CG1OP_Vdq,
86	BS3CG1OP_Vdq_WO,
87	BS3CG1OP_VqHi,
88	BS3CG1OP_VqHi_WO,
89	BS3CG1OP_VqZx_WO,
90
91	BS3CG1OP_Ib,
92	BS3CG1OP_Iz,
93
94	BS3CG1OP_AL,
95	BS3CG1OP_rAX,
96
97	BS3CG1OP_Ma,
98	BS3CG1OP_Mb_RO,
99	BS3CG1OP_Md,
100	BS3CG1OP_Md_RO,
101	BS3CG1OP_Md_WO,
102	BS3CG1OP_Mq,
103	BS3CG1OP_Mq_WO,
104
105	BS3CG1OP_END
106	} BS3CG1OP;
107	/** Pointer to a const operand enum. */
108	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
109
110
111	/**
112	* Instruction encoding format.
113	*
114	* This duplicates some of the info in the operand array, however it makes it
115	* easier to figure out encoding variations.
116	*/
117	typedef enum BS3CG1ENC
118	{
119	BS3CG1ENC_INVALID = 0,
120
121	BS3CG1ENC_MODRM_Eb_Gb,
122	BS3CG1ENC_MODRM_Ev_Gv,
123	BS3CG1ENC_MODRM_Wss_WO_Vss,
124	BS3CG1ENC_MODRM_Wsd_WO_Vsd,
125	BS3CG1ENC_MODRM_Wps_WO_Vps,
126	BS3CG1ENC_MODRM_Wpd_WO_Vpd,
127	BS3CG1ENC_MODRM_WqZxReg_WO_Vq,
128
129	BS3CG1ENC_MODRM_Gb_Eb,
130	BS3CG1ENC_MODRM_Gv_Ev,
131	BS3CG1ENC_MODRM_Gv_RO_Ma, /*< bound instruction /
132	BS3CG1ENC_MODRM_Pq_WO_Uq,
133	BS3CG1ENC_MODRM_Vq_WO_UqHi,
134	BS3CG1ENC_MODRM_Vq_WO_Mq,
135	BS3CG1ENC_MODRM_VqHi_WO_Uq,
136	BS3CG1ENC_MODRM_VqHi_WO_Mq,
137	BS3CG1ENC_MODRM_Vdq_WO_Wdq,
138	BS3CG1ENC_MODRM_Vpd_WO_Wpd,
139	BS3CG1ENC_MODRM_Vps_WO_Wps,
140	BS3CG1ENC_MODRM_VssZx_WO_Wss,
141	BS3CG1ENC_MODRM_VsdZx_WO_Wsd,
142	BS3CG1ENC_MODRM_VqZx_WO_Wq,
143	BS3CG1ENC_MODRM_VqZx_WO_Nq,
144	BS3CG1ENC_MODRM_Mb_RO,
145	BS3CG1ENC_MODRM_Md_RO,
146	BS3CG1ENC_MODRM_Md_WO,
147	BS3CG1ENC_MODRM_Mq_WO_Vq,
148	BS3CG1ENC_MODRM_Mq_WO_VqHi,
149
150	BS3CG1ENC_VEX_MODRM_Vps_WO_Wps,
151	BS3CG1ENC_VEX_MODRM_Vpd_WO_Wpd,
152	BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss,
153	BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd,
154	BS3CG1ENC_VEX_MODRM_VssZx_WO_Md,
155	BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq,
156	BS3CG1ENC_VEX_MODRM_Md_WO,
157	BS3CG1ENC_VEX_MODRM_Md_WO_Vss,
158	BS3CG1ENC_VEX_MODRM_Md_WO_Vsd,
159	BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss,
160	BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd,
161	BS3CG1ENC_VEX_MODRM_Wps_WO_Vps,
162	BS3CG1ENC_VEX_MODRM_Wpd_WO_Vpd,
163
164	BS3CG1ENC_FIXED,
165	BS3CG1ENC_FIXED_AL_Ib,
166	BS3CG1ENC_FIXED_rAX_Iz,
167
168	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
169	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
170
171	BS3CG1ENC_END
172	} BS3CG1ENC;
173
174
175	/**
176	* Prefix sensitivitiy kind.
177	*/
178	typedef enum BS3CG1PFXKIND
179	{
180	BS3CG1PFXKIND_INVALID = 0,
181
182	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
183	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
184	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
185	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
186
187	/** @todo more work to be done here... */
188	BS3CG1PFXKIND_MODRM,
189	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
190
191	BS3CG1PFXKIND_END
192	} BS3CG1PFXKIND;
193
194	/**
195	* CPU selection or CPU ID.
196	*/
197	typedef enum BS3CG1CPU
198	{
199	/** Works with an CPU. */
200	BS3CG1CPU_ANY = 0,
201	BS3CG1CPU_GE_80186,
202	BS3CG1CPU_GE_80286,
203	BS3CG1CPU_GE_80386,
204	BS3CG1CPU_GE_80486,
205	BS3CG1CPU_GE_Pentium,
206
207	BS3CG1CPU_SSE,
208	BS3CG1CPU_SSE2,
209	BS3CG1CPU_SSE3,
210	BS3CG1CPU_AVX,
211	BS3CG1CPU_AVX2,
212	BS3CG1CPU_CLFSH,
213	BS3CG1CPU_CLFLUSHOPT,
214
215	BS3CG1CPU_END
216	} BS3CG1CPU;
217
218
219	/**
220	* SSE & AVX exception types.
221	*/
222	typedef enum BS3CG1XCPTTYPE
223	{
224	BS3CG1XCPTTYPE_NONE = 0,
225	/* SSE: */
226	BS3CG1XCPTTYPE_1,
227	BS3CG1XCPTTYPE_2,
228	BS3CG1XCPTTYPE_3,
229	BS3CG1XCPTTYPE_4,
230	BS3CG1XCPTTYPE_4UA,
231	BS3CG1XCPTTYPE_5,
232	BS3CG1XCPTTYPE_6,
233	BS3CG1XCPTTYPE_7,
234	BS3CG1XCPTTYPE_8,
235	BS3CG1XCPTTYPE_11,
236	BS3CG1XCPTTYPE_12,
237	/* EVEX: */
238	BS3CG1XCPTTYPE_E1,
239	BS3CG1XCPTTYPE_E1NF,
240	BS3CG1XCPTTYPE_E2,
241	BS3CG1XCPTTYPE_E3,
242	BS3CG1XCPTTYPE_E3NF,
243	BS3CG1XCPTTYPE_E4,
244	BS3CG1XCPTTYPE_E4NF,
245	BS3CG1XCPTTYPE_E5,
246	BS3CG1XCPTTYPE_E5NF,
247	BS3CG1XCPTTYPE_E6,
248	BS3CG1XCPTTYPE_E6NF,
249	BS3CG1XCPTTYPE_E7NF,
250	BS3CG1XCPTTYPE_E9,
251	BS3CG1XCPTTYPE_E9NF,
252	BS3CG1XCPTTYPE_E10,
253	BS3CG1XCPTTYPE_E11,
254	BS3CG1XCPTTYPE_E12,
255	BS3CG1XCPTTYPE_E12NF,
256	BS3CG1XCPTTYPE_END
257	} BS3CG1XCPTTYPE;
258	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
259
260
261	/**
262	* Generated instruction info.
263	*/
264	typedef struct BS3CG1INSTR
265	{
266	/** The opcode size. */
267	uint32_t cbOpcodes : 2;
268	/** The number of operands. */
269	uint32_t cOperands : 2;
270	/** The length of the mnemonic. */
271	uint32_t cchMnemonic : 4;
272	/** Whether to advance the mnemonic array pointer. */
273	uint32_t fAdvanceMnemonic : 1;
274	/** Offset into g_abBs3Cg1Tests of the first test. */
275	uint32_t offTests : 23;
276	/** BS3CG1ENC values. */
277	uint32_t enmEncoding : 10;
278	/** BS3CG1PFXKIND values. */
279	uint32_t enmPrefixKind : 4;
280	/** CPU test / CPU ID bit test (BS3CG1CPU). */
281	uint32_t enmCpuTest : 6;
282	/** Exception type (BS3CG1XCPTTYPE) */
283	uint32_t enmXcptType : 5;
284	/** Currently unused bits. */
285	uint32_t uUnused : 6;
286	/** BS3CG1INSTR_F_XXX. */
287	uint32_t fFlags;
288	} BS3CG1INSTR;
289	AssertCompileSize(BS3CG1INSTR, 12);
290	/** Pointer to a const instruction. */
291	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
292
293
294	/** @name BS3CG1INSTR_F_XXX
295	* @{ */
296	/** Defaults to SS rather than DS. */
297	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
298	/** Invalid instruction in 64-bit mode. */
299	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
300	/** Unused instruction. */
301	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
302	/** Invalid instruction. */
303	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
304	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
305	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
306	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
307	/** @} */
308
309
310	/**
311	* Test header.
312	*/
313	typedef struct BS3CG1TESTHDR
314	{
315	/** The size of the selector program in bytes.
316	* This is also the offset of the input context modification program. */
317	uint32_t cbSelector : 8;
318	/** The size of the input context modification program in bytes.
319	* This immediately follows the selector program. */
320	uint32_t cbInput : 12;
321	/** The size of the output context modification program in bytes.
322	* This immediately follows the input context modification program. The
323	* program takes the result of the input program as starting point. */
324	uint32_t cbOutput : 11;
325	/** Indicates whether this is the last test or not. */
326	uint32_t fLast : 1;
327	} BS3CG1TESTHDR;
328	AssertCompileSize(BS3CG1TESTHDR, 4);
329	/** Pointer to a const test header. */
330	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
331
332	/** @name Opcode format for the BS3CG1 context modifier.
333	*
334	* Used by both the input and output context programs.
335	*
336	* The most common operations are encoded as a single byte opcode followed by
337	* one or more immediate bytes with data.
338	*
339	* @{ */
340	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
341	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
342	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
343	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
344	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
345	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
346	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
347	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
348	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
349
350	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
351	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
352	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
353	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
354	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
355
356	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
357
358	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
359	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
360	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
361	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
362	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
363	/** @} */
364
365	/**
366	* Escaped destination values
367	*
368	* These are just uppercased versions of TestInOut.kdFields, where dots are
369	* replaced by underscores.
370	*/
371	typedef enum BS3CG1DST
372	{
373	BS3CG1DST_INVALID = 0,
374	/* Operands. */
375	BS3CG1DST_OP1,
376	BS3CG1DST_OP2,
377	BS3CG1DST_OP3,
378	BS3CG1DST_OP4,
379	/* Flags. */
380	BS3CG1DST_EFL,
381	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
382	/* 8-bit GPRs. */
383	BS3CG1DST_AL,
384	BS3CG1DST_CL,
385	BS3CG1DST_DL,
386	BS3CG1DST_BL,
387	BS3CG1DST_AH,
388	BS3CG1DST_CH,
389	BS3CG1DST_DH,
390	BS3CG1DST_BH,
391	BS3CG1DST_SPL,
392	BS3CG1DST_BPL,
393	BS3CG1DST_SIL,
394	BS3CG1DST_DIL,
395	BS3CG1DST_R8L,
396	BS3CG1DST_R9L,
397	BS3CG1DST_R10L,
398	BS3CG1DST_R11L,
399	BS3CG1DST_R12L,
400	BS3CG1DST_R13L,
401	BS3CG1DST_R14L,
402	BS3CG1DST_R15L,
403	/* 16-bit GPRs. */
404	BS3CG1DST_AX,
405	BS3CG1DST_CX,
406	BS3CG1DST_DX,
407	BS3CG1DST_BX,
408	BS3CG1DST_SP,
409	BS3CG1DST_BP,
410	BS3CG1DST_SI,
411	BS3CG1DST_DI,
412	BS3CG1DST_R8W,
413	BS3CG1DST_R9W,
414	BS3CG1DST_R10W,
415	BS3CG1DST_R11W,
416	BS3CG1DST_R12W,
417	BS3CG1DST_R13W,
418	BS3CG1DST_R14W,
419	BS3CG1DST_R15W,
420	/* 32-bit GPRs. */
421	BS3CG1DST_EAX,
422	BS3CG1DST_ECX,
423	BS3CG1DST_EDX,
424	BS3CG1DST_EBX,
425	BS3CG1DST_ESP,
426	BS3CG1DST_EBP,
427	BS3CG1DST_ESI,
428	BS3CG1DST_EDI,
429	BS3CG1DST_R8D,
430	BS3CG1DST_R9D,
431	BS3CG1DST_R10D,
432	BS3CG1DST_R11D,
433	BS3CG1DST_R12D,
434	BS3CG1DST_R13D,
435	BS3CG1DST_R14D,
436	BS3CG1DST_R15D,
437	/* 64-bit GPRs. */
438	BS3CG1DST_RAX,
439	BS3CG1DST_RCX,
440	BS3CG1DST_RDX,
441	BS3CG1DST_RBX,
442	BS3CG1DST_RSP,
443	BS3CG1DST_RBP,
444	BS3CG1DST_RSI,
445	BS3CG1DST_RDI,
446	BS3CG1DST_R8,
447	BS3CG1DST_R9,
448	BS3CG1DST_R10,
449	BS3CG1DST_R11,
450	BS3CG1DST_R12,
451	BS3CG1DST_R13,
452	BS3CG1DST_R14,
453	BS3CG1DST_R15,
454	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
455	BS3CG1DST_OZ_RAX,
456	BS3CG1DST_OZ_RCX,
457	BS3CG1DST_OZ_RDX,
458	BS3CG1DST_OZ_RBX,
459	BS3CG1DST_OZ_RSP,
460	BS3CG1DST_OZ_RBP,
461	BS3CG1DST_OZ_RSI,
462	BS3CG1DST_OZ_RDI,
463	BS3CG1DST_OZ_R8,
464	BS3CG1DST_OZ_R9,
465	BS3CG1DST_OZ_R10,
466	BS3CG1DST_OZ_R11,
467	BS3CG1DST_OZ_R12,
468	BS3CG1DST_OZ_R13,
469	BS3CG1DST_OZ_R14,
470	BS3CG1DST_OZ_R15,
471
472	/* Control registers.*/
473	BS3CG1DST_CR0,
474	BS3CG1DST_CR4,
475	BS3CG1DST_XCR0,
476
477	/* FPU registers. */
478	BS3CG1DST_FPU_FIRST,
479	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
480	BS3CG1DST_FSW,
481	BS3CG1DST_FTW,
482	BS3CG1DST_FOP,
483	BS3CG1DST_FPUIP,
484	BS3CG1DST_FPUCS,
485	BS3CG1DST_FPUDP,
486	BS3CG1DST_FPUDS,
487	BS3CG1DST_MXCSR,
488	BS3CG1DST_ST0,
489	BS3CG1DST_ST1,
490	BS3CG1DST_ST2,
491	BS3CG1DST_ST3,
492	BS3CG1DST_ST4,
493	BS3CG1DST_ST5,
494	BS3CG1DST_ST6,
495	BS3CG1DST_ST7,
496	/* MMX registers. */
497	BS3CG1DST_MM0,
498	BS3CG1DST_MM1,
499	BS3CG1DST_MM2,
500	BS3CG1DST_MM3,
501	BS3CG1DST_MM4,
502	BS3CG1DST_MM5,
503	BS3CG1DST_MM6,
504	BS3CG1DST_MM7,
505	/* SSE registers. */
506	BS3CG1DST_XMM0,
507	BS3CG1DST_XMM1,
508	BS3CG1DST_XMM2,
509	BS3CG1DST_XMM3,
510	BS3CG1DST_XMM4,
511	BS3CG1DST_XMM5,
512	BS3CG1DST_XMM6,
513	BS3CG1DST_XMM7,
514	BS3CG1DST_XMM8,
515	BS3CG1DST_XMM9,
516	BS3CG1DST_XMM10,
517	BS3CG1DST_XMM11,
518	BS3CG1DST_XMM12,
519	BS3CG1DST_XMM13,
520	BS3CG1DST_XMM14,
521	BS3CG1DST_XMM15,
522	BS3CG1DST_XMM0_LO,
523	BS3CG1DST_XMM1_LO,
524	BS3CG1DST_XMM2_LO,
525	BS3CG1DST_XMM3_LO,
526	BS3CG1DST_XMM4_LO,
527	BS3CG1DST_XMM5_LO,
528	BS3CG1DST_XMM6_LO,
529	BS3CG1DST_XMM7_LO,
530	BS3CG1DST_XMM8_LO,
531	BS3CG1DST_XMM9_LO,
532	BS3CG1DST_XMM10_LO,
533	BS3CG1DST_XMM11_LO,
534	BS3CG1DST_XMM12_LO,
535	BS3CG1DST_XMM13_LO,
536	BS3CG1DST_XMM14_LO,
537	BS3CG1DST_XMM15_LO,
538	BS3CG1DST_XMM0_HI,
539	BS3CG1DST_XMM1_HI,
540	BS3CG1DST_XMM2_HI,
541	BS3CG1DST_XMM3_HI,
542	BS3CG1DST_XMM4_HI,
543	BS3CG1DST_XMM5_HI,
544	BS3CG1DST_XMM6_HI,
545	BS3CG1DST_XMM7_HI,
546	BS3CG1DST_XMM8_HI,
547	BS3CG1DST_XMM9_HI,
548	BS3CG1DST_XMM10_HI,
549	BS3CG1DST_XMM11_HI,
550	BS3CG1DST_XMM12_HI,
551	BS3CG1DST_XMM13_HI,
552	BS3CG1DST_XMM14_HI,
553	BS3CG1DST_XMM15_HI,
554	BS3CG1DST_XMM0_LO_ZX,
555	BS3CG1DST_XMM1_LO_ZX,
556	BS3CG1DST_XMM2_LO_ZX,
557	BS3CG1DST_XMM3_LO_ZX,
558	BS3CG1DST_XMM4_LO_ZX,
559	BS3CG1DST_XMM5_LO_ZX,
560	BS3CG1DST_XMM6_LO_ZX,
561	BS3CG1DST_XMM7_LO_ZX,
562	BS3CG1DST_XMM8_LO_ZX,
563	BS3CG1DST_XMM9_LO_ZX,
564	BS3CG1DST_XMM10_LO_ZX,
565	BS3CG1DST_XMM11_LO_ZX,
566	BS3CG1DST_XMM12_LO_ZX,
567	BS3CG1DST_XMM13_LO_ZX,
568	BS3CG1DST_XMM14_LO_ZX,
569	BS3CG1DST_XMM15_LO_ZX,
570	BS3CG1DST_XMM0_DW0,
571	BS3CG1DST_XMM1_DW0,
572	BS3CG1DST_XMM2_DW0,
573	BS3CG1DST_XMM3_DW0,
574	BS3CG1DST_XMM4_DW0,
575	BS3CG1DST_XMM5_DW0,
576	BS3CG1DST_XMM6_DW0,
577	BS3CG1DST_XMM7_DW0,
578	BS3CG1DST_XMM8_DW0,
579	BS3CG1DST_XMM9_DW0,
580	BS3CG1DST_XMM10_DW0,
581	BS3CG1DST_XMM11_DW0,
582	BS3CG1DST_XMM12_DW0,
583	BS3CG1DST_XMM13_DW0,
584	BS3CG1DST_XMM14_DW0,
585	BS3CG1DST_XMM15_DW0,
586	BS3CG1DST_XMM0_DW0_ZX,
587	BS3CG1DST_XMM1_DW0_ZX,
588	BS3CG1DST_XMM2_DW0_ZX,
589	BS3CG1DST_XMM3_DW0_ZX,
590	BS3CG1DST_XMM4_DW0_ZX,
591	BS3CG1DST_XMM5_DW0_ZX,
592	BS3CG1DST_XMM6_DW0_ZX,
593	BS3CG1DST_XMM7_DW0_ZX,
594	BS3CG1DST_XMM8_DW0_ZX,
595	BS3CG1DST_XMM9_DW0_ZX,
596	BS3CG1DST_XMM10_DW0_ZX,
597	BS3CG1DST_XMM11_DW0_ZX,
598	BS3CG1DST_XMM12_DW0_ZX,
599	BS3CG1DST_XMM13_DW0_ZX,
600	BS3CG1DST_XMM14_DW0_ZX,
601	BS3CG1DST_XMM15_DW0_ZX,
602	/* AVX registers. */
603	BS3CG1DST_YMM0,
604	BS3CG1DST_YMM1,
605	BS3CG1DST_YMM2,
606	BS3CG1DST_YMM3,
607	BS3CG1DST_YMM4,
608	BS3CG1DST_YMM5,
609	BS3CG1DST_YMM6,
610	BS3CG1DST_YMM7,
611	BS3CG1DST_YMM8,
612	BS3CG1DST_YMM9,
613	BS3CG1DST_YMM10,
614	BS3CG1DST_YMM11,
615	BS3CG1DST_YMM12,
616	BS3CG1DST_YMM13,
617	BS3CG1DST_YMM14,
618	BS3CG1DST_YMM15,
619
620	/* Special fields: */
621	BS3CG1DST_SPECIAL_START,
622	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
623
624	BS3CG1DST_END
625	} BS3CG1DST;
626	AssertCompile(BS3CG1DST_END <= 256);
627
628	/** @name Selector opcode definitions.
629	*
630	* Selector programs are very simple, they are zero or more predicate tests
631	* that are ANDed together. If a predicate test fails, the test is skipped.
632	*
633	* One instruction is encoded as byte, where the first bit indicates what kind
634	* of test and the 7 remaining bits indicates which predicate to check.
635	*
636	* @{ */
637	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
638	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
639	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
640	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
641	/** @} */
642
643	/**
644	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
645	*/
646	typedef enum BS3CG1PRED
647	{
648	BS3CG1PRED_INVALID = 0,
649
650	/* Operand size. */
651	BS3CG1PRED_SIZE_O16,
652	BS3CG1PRED_SIZE_O32,
653	BS3CG1PRED_SIZE_O64,
654	/* Execution ring. */
655	BS3CG1PRED_RING_0,
656	BS3CG1PRED_RING_1,
657	BS3CG1PRED_RING_2,
658	BS3CG1PRED_RING_3,
659	BS3CG1PRED_RING_0_THRU_2,
660	BS3CG1PRED_RING_1_THRU_3,
661	/* Basic code mode. */
662	BS3CG1PRED_CODE_64BIT,
663	BS3CG1PRED_CODE_32BIT,
664	BS3CG1PRED_CODE_16BIT,
665	/* CPU modes. */
666	BS3CG1PRED_MODE_REAL,
667	BS3CG1PRED_MODE_PROT,
668	BS3CG1PRED_MODE_LONG,
669	BS3CG1PRED_MODE_V86,
670	BS3CG1PRED_MODE_SMM,
671	BS3CG1PRED_MODE_VMX,
672	BS3CG1PRED_MODE_SVM,
673	/* Paging on/off */
674	BS3CG1PRED_PAGING_ON,
675	BS3CG1PRED_PAGING_OFF,
676	/* CPU Vendors. */
677	BS3CG1PRED_VENDOR_AMD,
678	BS3CG1PRED_VENDOR_INTEL,
679	BS3CG1PRED_VENDOR_VIA,
680
681	BS3CG1PRED_END
682	} BS3CG1PRED;
683
684
685	/** The test instructions (generated). */
686	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
687	/** The number of test instructions (generated). */
688	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
689	/** The mnemonics (generated).
690	* Variable length sequence of mnemonics that runs in parallel to
691	* g_aBs3Cg1Instructions. */
692	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
693	/** The opcodes (generated).
694	* Variable length sequence of opcode bytes that runs in parallel to
695	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
696	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
697	/** The operands (generated).
698	* Variable length sequence of opcode values (BS3CG1OP) that runs in
699	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
700	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
701	/** The test data that BS3CG1INSTR.
702	* In order to simplify generating these, we use a byte array. */
703	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
704
705
706	#endif
707

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66920

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